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TARGET_EFM32PG12_STK3402/TOOLCHAIN_GCC_ARM/efm32pg12b_trng.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32pg12b_trng.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32PG12B_TRNG register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32PG12B_TRNG
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32PG12B_TRNG Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CONTROL; /**< Main Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
AnnaBridge 171:3a7713b1edbc 45 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 46 __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t KEY0; /**< Key Register 0 */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t KEY1; /**< Key Register 1 */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t KEY2; /**< Key Register 2 */
AnnaBridge 171:3a7713b1edbc 50 __IOM uint32_t KEY3; /**< Key Register 3 */
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t TESTDATA; /**< Test Data Register */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 54 __IOM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
AnnaBridge 171:3a7713b1edbc 56 uint32_t RESERVED2[50]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 57 __IM uint32_t FIFO; /**< FIFO Data */
AnnaBridge 171:3a7713b1edbc 58 } TRNG_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 61 * @defgroup EFM32PG12B_TRNG_BitFields
AnnaBridge 171:3a7713b1edbc 62 * @{
AnnaBridge 171:3a7713b1edbc 63 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* Bit fields for TRNG CONTROL */
AnnaBridge 171:3a7713b1edbc 66 #define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 67 #define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 68 #define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */
AnnaBridge 171:3a7713b1edbc 69 #define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */
AnnaBridge 171:3a7713b1edbc 70 #define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */
AnnaBridge 171:3a7713b1edbc 71 #define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 72 #define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 73 #define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 74 #define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 75 #define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 76 #define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 77 #define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */
AnnaBridge 171:3a7713b1edbc 78 #define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */
AnnaBridge 171:3a7713b1edbc 79 #define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */
AnnaBridge 171:3a7713b1edbc 80 #define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 81 #define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 82 #define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 83 #define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 84 #define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 85 #define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 86 #define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */
AnnaBridge 171:3a7713b1edbc 87 #define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */
AnnaBridge 171:3a7713b1edbc 88 #define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */
AnnaBridge 171:3a7713b1edbc 89 #define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 90 #define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 91 #define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 92 #define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 93 #define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 94 #define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 95 #define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */
AnnaBridge 171:3a7713b1edbc 96 #define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */
AnnaBridge 171:3a7713b1edbc 97 #define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */
AnnaBridge 171:3a7713b1edbc 98 #define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 99 #define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 100 #define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */
AnnaBridge 171:3a7713b1edbc 101 #define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */
AnnaBridge 171:3a7713b1edbc 102 #define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */
AnnaBridge 171:3a7713b1edbc 103 #define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 104 #define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 105 #define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */
AnnaBridge 171:3a7713b1edbc 106 #define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */
AnnaBridge 171:3a7713b1edbc 107 #define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */
AnnaBridge 171:3a7713b1edbc 108 #define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 109 #define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 110 #define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */
AnnaBridge 171:3a7713b1edbc 111 #define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */
AnnaBridge 171:3a7713b1edbc 112 #define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */
AnnaBridge 171:3a7713b1edbc 113 #define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 114 #define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 115 #define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */
AnnaBridge 171:3a7713b1edbc 116 #define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */
AnnaBridge 171:3a7713b1edbc 117 #define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */
AnnaBridge 171:3a7713b1edbc 118 #define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 119 #define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 120 #define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 121 #define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 122 #define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 123 #define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 124 #define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */
AnnaBridge 171:3a7713b1edbc 125 #define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */
AnnaBridge 171:3a7713b1edbc 126 #define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */
AnnaBridge 171:3a7713b1edbc 127 #define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 128 #define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 129 #define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */
AnnaBridge 171:3a7713b1edbc 130 #define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */
AnnaBridge 171:3a7713b1edbc 131 #define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */
AnnaBridge 171:3a7713b1edbc 132 #define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 133 #define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 134 #define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */
AnnaBridge 171:3a7713b1edbc 135 #define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */
AnnaBridge 171:3a7713b1edbc 136 #define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */
AnnaBridge 171:3a7713b1edbc 137 #define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 138 #define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 139 #define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 140 #define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 141 #define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 142 #define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 143 #define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */
AnnaBridge 171:3a7713b1edbc 144 #define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */
AnnaBridge 171:3a7713b1edbc 145 #define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */
AnnaBridge 171:3a7713b1edbc 146 #define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 147 #define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 148 #define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 149 #define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 150 #define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 151 #define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 152 #define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */
AnnaBridge 171:3a7713b1edbc 153 #define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */
AnnaBridge 171:3a7713b1edbc 154 #define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */
AnnaBridge 171:3a7713b1edbc 155 #define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 156 #define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 157 #define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 158 #define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 159 #define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 160 #define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 /* Bit fields for TRNG FIFOLEVEL */
AnnaBridge 171:3a7713b1edbc 163 #define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */
AnnaBridge 171:3a7713b1edbc 164 #define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */
AnnaBridge 171:3a7713b1edbc 165 #define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 166 #define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 167 #define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */
AnnaBridge 171:3a7713b1edbc 168 #define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /* Bit fields for TRNG FIFODEPTH */
AnnaBridge 171:3a7713b1edbc 171 #define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */
AnnaBridge 171:3a7713b1edbc 172 #define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */
AnnaBridge 171:3a7713b1edbc 173 #define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 174 #define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 175 #define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */
AnnaBridge 171:3a7713b1edbc 176 #define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /* Bit fields for TRNG KEY0 */
AnnaBridge 171:3a7713b1edbc 179 #define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */
AnnaBridge 171:3a7713b1edbc 180 #define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */
AnnaBridge 171:3a7713b1edbc 181 #define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 182 #define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 183 #define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */
AnnaBridge 171:3a7713b1edbc 184 #define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /* Bit fields for TRNG KEY1 */
AnnaBridge 171:3a7713b1edbc 187 #define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */
AnnaBridge 171:3a7713b1edbc 188 #define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */
AnnaBridge 171:3a7713b1edbc 189 #define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 190 #define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 191 #define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */
AnnaBridge 171:3a7713b1edbc 192 #define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /* Bit fields for TRNG KEY2 */
AnnaBridge 171:3a7713b1edbc 195 #define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */
AnnaBridge 171:3a7713b1edbc 196 #define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */
AnnaBridge 171:3a7713b1edbc 197 #define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 198 #define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 199 #define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */
AnnaBridge 171:3a7713b1edbc 200 #define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /* Bit fields for TRNG KEY3 */
AnnaBridge 171:3a7713b1edbc 203 #define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */
AnnaBridge 171:3a7713b1edbc 204 #define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */
AnnaBridge 171:3a7713b1edbc 205 #define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 206 #define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 207 #define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */
AnnaBridge 171:3a7713b1edbc 208 #define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /* Bit fields for TRNG TESTDATA */
AnnaBridge 171:3a7713b1edbc 211 #define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */
AnnaBridge 171:3a7713b1edbc 212 #define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */
AnnaBridge 171:3a7713b1edbc 213 #define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 214 #define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 215 #define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */
AnnaBridge 171:3a7713b1edbc 216 #define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* Bit fields for TRNG STATUS */
AnnaBridge 171:3a7713b1edbc 219 #define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 220 #define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 221 #define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */
AnnaBridge 171:3a7713b1edbc 222 #define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */
AnnaBridge 171:3a7713b1edbc 223 #define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */
AnnaBridge 171:3a7713b1edbc 224 #define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 225 #define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 226 #define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 227 #define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 228 #define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 229 #define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 230 #define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */
AnnaBridge 171:3a7713b1edbc 231 #define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */
AnnaBridge 171:3a7713b1edbc 232 #define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */
AnnaBridge 171:3a7713b1edbc 233 #define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 234 #define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 235 #define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */
AnnaBridge 171:3a7713b1edbc 236 #define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */
AnnaBridge 171:3a7713b1edbc 237 #define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */
AnnaBridge 171:3a7713b1edbc 238 #define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 239 #define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 240 #define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */
AnnaBridge 171:3a7713b1edbc 241 #define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */
AnnaBridge 171:3a7713b1edbc 242 #define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */
AnnaBridge 171:3a7713b1edbc 243 #define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 244 #define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 245 #define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */
AnnaBridge 171:3a7713b1edbc 246 #define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */
AnnaBridge 171:3a7713b1edbc 247 #define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */
AnnaBridge 171:3a7713b1edbc 248 #define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 249 #define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 250 #define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */
AnnaBridge 171:3a7713b1edbc 251 #define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */
AnnaBridge 171:3a7713b1edbc 252 #define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */
AnnaBridge 171:3a7713b1edbc 253 #define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 254 #define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 255 #define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */
AnnaBridge 171:3a7713b1edbc 256 #define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */
AnnaBridge 171:3a7713b1edbc 257 #define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */
AnnaBridge 171:3a7713b1edbc 258 #define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 259 #define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /* Bit fields for TRNG INITWAITVAL */
AnnaBridge 171:3a7713b1edbc 262 #define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */
AnnaBridge 171:3a7713b1edbc 263 #define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */
AnnaBridge 171:3a7713b1edbc 264 #define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 265 #define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 266 #define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */
AnnaBridge 171:3a7713b1edbc 267 #define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /* Bit fields for TRNG FIFO */
AnnaBridge 171:3a7713b1edbc 270 #define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */
AnnaBridge 171:3a7713b1edbc 271 #define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */
AnnaBridge 171:3a7713b1edbc 272 #define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 273 #define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
AnnaBridge 171:3a7713b1edbc 274 #define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */
AnnaBridge 171:3a7713b1edbc 275 #define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /** @} End of group EFM32PG12B_TRNG */
AnnaBridge 171:3a7713b1edbc 278 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 279