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TARGET_EFM32PG12_STK3402/TOOLCHAIN_GCC_ARM/efm32pg12b_prs_signals.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32pg12b_prs_signals.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @addtogroup EFM32PG12B_PRS_Signals
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief PRS Signal names
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 #define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */
AnnaBridge 171:3a7713b1edbc 42 #define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */
AnnaBridge 171:3a7713b1edbc 43 #define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */
AnnaBridge 171:3a7713b1edbc 44 #define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */
AnnaBridge 171:3a7713b1edbc 45 #define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */
AnnaBridge 171:3a7713b1edbc 46 #define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */
AnnaBridge 171:3a7713b1edbc 47 #define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */
AnnaBridge 171:3a7713b1edbc 48 #define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */
AnnaBridge 171:3a7713b1edbc 49 #define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */
AnnaBridge 171:3a7713b1edbc 50 #define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */
AnnaBridge 171:3a7713b1edbc 51 #define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */
AnnaBridge 171:3a7713b1edbc 52 #define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */
AnnaBridge 171:3a7713b1edbc 53 #define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */
AnnaBridge 171:3a7713b1edbc 54 #define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */
AnnaBridge 171:3a7713b1edbc 55 #define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */
AnnaBridge 171:3a7713b1edbc 56 #define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */
AnnaBridge 171:3a7713b1edbc 57 #define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
AnnaBridge 171:3a7713b1edbc 58 #define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
AnnaBridge 171:3a7713b1edbc 59 #define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
AnnaBridge 171:3a7713b1edbc 60 #define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
AnnaBridge 171:3a7713b1edbc 61 #define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
AnnaBridge 171:3a7713b1edbc 62 #define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
AnnaBridge 171:3a7713b1edbc 63 #define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
AnnaBridge 171:3a7713b1edbc 64 #define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
AnnaBridge 171:3a7713b1edbc 65 #define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
AnnaBridge 171:3a7713b1edbc 66 #define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
AnnaBridge 171:3a7713b1edbc 67 #define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
AnnaBridge 171:3a7713b1edbc 68 #define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
AnnaBridge 171:3a7713b1edbc 69 #define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
AnnaBridge 171:3a7713b1edbc 70 #define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
AnnaBridge 171:3a7713b1edbc 71 #define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
AnnaBridge 171:3a7713b1edbc 72 #define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
AnnaBridge 171:3a7713b1edbc 73 #define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */
AnnaBridge 171:3a7713b1edbc 74 #define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */
AnnaBridge 171:3a7713b1edbc 75 #define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */
AnnaBridge 171:3a7713b1edbc 76 #define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */
AnnaBridge 171:3a7713b1edbc 77 #define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */
AnnaBridge 171:3a7713b1edbc 78 #define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */
AnnaBridge 171:3a7713b1edbc 79 #define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */
AnnaBridge 171:3a7713b1edbc 80 #define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */
AnnaBridge 171:3a7713b1edbc 81 #define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */
AnnaBridge 171:3a7713b1edbc 82 #define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */
AnnaBridge 171:3a7713b1edbc 83 #define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */
AnnaBridge 171:3a7713b1edbc 84 #define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */
AnnaBridge 171:3a7713b1edbc 85 #define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */
AnnaBridge 171:3a7713b1edbc 86 #define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */
AnnaBridge 171:3a7713b1edbc 87 #define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */
AnnaBridge 171:3a7713b1edbc 88 #define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */
AnnaBridge 171:3a7713b1edbc 89 #define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */
AnnaBridge 171:3a7713b1edbc 90 #define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */
AnnaBridge 171:3a7713b1edbc 91 #define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */
AnnaBridge 171:3a7713b1edbc 92 #define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */
AnnaBridge 171:3a7713b1edbc 93 #define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */
AnnaBridge 171:3a7713b1edbc 94 #define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */
AnnaBridge 171:3a7713b1edbc 95 #define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */
AnnaBridge 171:3a7713b1edbc 96 #define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */
AnnaBridge 171:3a7713b1edbc 97 #define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */
AnnaBridge 171:3a7713b1edbc 98 #define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */
AnnaBridge 171:3a7713b1edbc 99 #define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */
AnnaBridge 171:3a7713b1edbc 100 #define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */
AnnaBridge 171:3a7713b1edbc 101 #define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */
AnnaBridge 171:3a7713b1edbc 102 #define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */
AnnaBridge 171:3a7713b1edbc 103 #define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */
AnnaBridge 171:3a7713b1edbc 104 #define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */
AnnaBridge 171:3a7713b1edbc 105 #define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */
AnnaBridge 171:3a7713b1edbc 106 #define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */
AnnaBridge 171:3a7713b1edbc 107 #define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */
AnnaBridge 171:3a7713b1edbc 108 #define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */
AnnaBridge 171:3a7713b1edbc 109 #define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */
AnnaBridge 171:3a7713b1edbc 110 #define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */
AnnaBridge 171:3a7713b1edbc 111 #define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */
AnnaBridge 171:3a7713b1edbc 112 #define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */
AnnaBridge 171:3a7713b1edbc 113 #define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */
AnnaBridge 171:3a7713b1edbc 114 #define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */
AnnaBridge 171:3a7713b1edbc 115 #define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */
AnnaBridge 171:3a7713b1edbc 116 #define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */
AnnaBridge 171:3a7713b1edbc 117 #define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */
AnnaBridge 171:3a7713b1edbc 118 #define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 119 #define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */
AnnaBridge 171:3a7713b1edbc 120 #define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */
AnnaBridge 171:3a7713b1edbc 121 #define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */
AnnaBridge 171:3a7713b1edbc 122 #define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */
AnnaBridge 171:3a7713b1edbc 123 #define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 124 #define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */
AnnaBridge 171:3a7713b1edbc 125 #define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */
AnnaBridge 171:3a7713b1edbc 126 #define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */
AnnaBridge 171:3a7713b1edbc 127 #define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */
AnnaBridge 171:3a7713b1edbc 128 #define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */
AnnaBridge 171:3a7713b1edbc 129 #define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 130 #define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */
AnnaBridge 171:3a7713b1edbc 131 #define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */
AnnaBridge 171:3a7713b1edbc 132 #define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */
AnnaBridge 171:3a7713b1edbc 133 #define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */
AnnaBridge 171:3a7713b1edbc 134 #define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 135 #define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */
AnnaBridge 171:3a7713b1edbc 136 #define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */
AnnaBridge 171:3a7713b1edbc 137 #define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */
AnnaBridge 171:3a7713b1edbc 138 #define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */
AnnaBridge 171:3a7713b1edbc 139 #define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */
AnnaBridge 171:3a7713b1edbc 140 #define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 141 #define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 142 #define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 143 #define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */
AnnaBridge 171:3a7713b1edbc 144 #define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */
AnnaBridge 171:3a7713b1edbc 145 #define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 146 #define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 147 #define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 148 #define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
AnnaBridge 171:3a7713b1edbc 149 #define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */
AnnaBridge 171:3a7713b1edbc 150 #define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */
AnnaBridge 171:3a7713b1edbc 151 #define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 152 #define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 153 #define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 154 #define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */
AnnaBridge 171:3a7713b1edbc 155 #define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */
AnnaBridge 171:3a7713b1edbc 156 #define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 157 #define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 158 #define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 159 #define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */
AnnaBridge 171:3a7713b1edbc 160 #define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */
AnnaBridge 171:3a7713b1edbc 161 #define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */
AnnaBridge 171:3a7713b1edbc 162 #define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /** @} End of group EFM32PG12B_PRS */
AnnaBridge 171:3a7713b1edbc 165 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 166