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TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/efm32gg_lcd.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32gg_lcd.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32GG_LCD register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32GG_LCD
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32GG_LCD Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t DISPCTRL; /**< Display Control Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t SEGEN; /**< Segment Enable Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */
AnnaBridge 171:3a7713b1edbc 47 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t AREGA; /**< Animation Register A */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t AREGB; /**< Animation Register B */
AnnaBridge 171:3a7713b1edbc 50 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 52 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 uint32_t RESERVED0[5]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */
AnnaBridge 171:3a7713b1edbc 59 __IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */
AnnaBridge 171:3a7713b1edbc 60 __IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */
AnnaBridge 171:3a7713b1edbc 61 __IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */
AnnaBridge 171:3a7713b1edbc 62 __IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */
AnnaBridge 171:3a7713b1edbc 63 __IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 __IOM uint32_t FREEZE; /**< Freeze Register */
AnnaBridge 171:3a7713b1edbc 66 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 uint32_t RESERVED1[19]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 69 __IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */
AnnaBridge 171:3a7713b1edbc 70 __IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */
AnnaBridge 171:3a7713b1edbc 71 __IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */
AnnaBridge 171:3a7713b1edbc 72 __IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */
AnnaBridge 171:3a7713b1edbc 73 uint32_t RESERVED2[2]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 74 __IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */
AnnaBridge 171:3a7713b1edbc 75 __IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */
AnnaBridge 171:3a7713b1edbc 76 __IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */
AnnaBridge 171:3a7713b1edbc 77 __IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */
AnnaBridge 171:3a7713b1edbc 78 } LCD_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 81 * @defgroup EFM32GG_LCD_BitFields
AnnaBridge 171:3a7713b1edbc 82 * @{
AnnaBridge 171:3a7713b1edbc 83 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /* Bit fields for LCD CTRL */
AnnaBridge 171:3a7713b1edbc 86 #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 88 #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
AnnaBridge 171:3a7713b1edbc 89 #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
AnnaBridge 171:3a7713b1edbc 90 #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
AnnaBridge 171:3a7713b1edbc 91 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 93 #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
AnnaBridge 171:3a7713b1edbc 94 #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
AnnaBridge 171:3a7713b1edbc 95 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 96 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 98 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 99 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 100 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 101 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 103 #define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
AnnaBridge 171:3a7713b1edbc 104 #define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
AnnaBridge 171:3a7713b1edbc 105 #define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
AnnaBridge 171:3a7713b1edbc 106 #define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 107 #define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /* Bit fields for LCD DISPCTRL */
AnnaBridge 171:3a7713b1edbc 110 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 111 #define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 112 #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
AnnaBridge 171:3a7713b1edbc 113 #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */
AnnaBridge 171:3a7713b1edbc 114 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 115 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 116 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 117 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 118 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 119 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 120 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 121 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 122 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 123 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 124 #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */
AnnaBridge 171:3a7713b1edbc 125 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */
AnnaBridge 171:3a7713b1edbc 126 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 127 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 128 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 129 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 130 #define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 131 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 132 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 133 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 134 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 135 #define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 136 #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
AnnaBridge 171:3a7713b1edbc 137 #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
AnnaBridge 171:3a7713b1edbc 138 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
AnnaBridge 171:3a7713b1edbc 139 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 140 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 141 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 142 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 143 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 144 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 145 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */
AnnaBridge 171:3a7713b1edbc 146 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */
AnnaBridge 171:3a7713b1edbc 147 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 148 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 149 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 150 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 151 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 152 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 153 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */
AnnaBridge 171:3a7713b1edbc 154 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */
AnnaBridge 171:3a7713b1edbc 155 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */
AnnaBridge 171:3a7713b1edbc 156 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 157 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 158 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 159 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 160 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 161 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 162 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */
AnnaBridge 171:3a7713b1edbc 163 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */
AnnaBridge 171:3a7713b1edbc 164 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */
AnnaBridge 171:3a7713b1edbc 165 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 166 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 167 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 168 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 169 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 170 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 171 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */
AnnaBridge 171:3a7713b1edbc 172 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */
AnnaBridge 171:3a7713b1edbc 173 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 174 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 175 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 176 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 177 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 178 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 179 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 180 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 181 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 182 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 183 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 184 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 185 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 186 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 187 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 188 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 189 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 190 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 191 #define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */
AnnaBridge 171:3a7713b1edbc 192 #define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */
AnnaBridge 171:3a7713b1edbc 193 #define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */
AnnaBridge 171:3a7713b1edbc 194 #define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 195 #define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 196 #define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 197 #define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 198 #define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 199 #define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /* Bit fields for LCD SEGEN */
AnnaBridge 171:3a7713b1edbc 202 #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 203 #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 204 #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 205 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 206 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 207 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 /* Bit fields for LCD BACTRL */
AnnaBridge 171:3a7713b1edbc 210 #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 211 #define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 212 #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
AnnaBridge 171:3a7713b1edbc 213 #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
AnnaBridge 171:3a7713b1edbc 214 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
AnnaBridge 171:3a7713b1edbc 215 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 216 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 217 #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
AnnaBridge 171:3a7713b1edbc 218 #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
AnnaBridge 171:3a7713b1edbc 219 #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
AnnaBridge 171:3a7713b1edbc 220 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 221 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 222 #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
AnnaBridge 171:3a7713b1edbc 223 #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
AnnaBridge 171:3a7713b1edbc 224 #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
AnnaBridge 171:3a7713b1edbc 225 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 226 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 227 #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
AnnaBridge 171:3a7713b1edbc 228 #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
AnnaBridge 171:3a7713b1edbc 229 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 230 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 231 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 232 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 233 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 234 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 235 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 236 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 237 #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
AnnaBridge 171:3a7713b1edbc 238 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
AnnaBridge 171:3a7713b1edbc 239 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 240 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 241 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 242 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 243 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 244 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 245 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 246 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 247 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
AnnaBridge 171:3a7713b1edbc 248 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
AnnaBridge 171:3a7713b1edbc 249 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
AnnaBridge 171:3a7713b1edbc 250 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 251 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 252 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 253 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 254 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 255 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 256 #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
AnnaBridge 171:3a7713b1edbc 257 #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
AnnaBridge 171:3a7713b1edbc 258 #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
AnnaBridge 171:3a7713b1edbc 259 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 260 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 261 #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
AnnaBridge 171:3a7713b1edbc 262 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
AnnaBridge 171:3a7713b1edbc 263 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 264 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 265 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 266 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 267 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 268 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 269 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 270 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 271 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 272 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 273 #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
AnnaBridge 171:3a7713b1edbc 274 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
AnnaBridge 171:3a7713b1edbc 275 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 276 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 277 #define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
AnnaBridge 171:3a7713b1edbc 278 #define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
AnnaBridge 171:3a7713b1edbc 279 #define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
AnnaBridge 171:3a7713b1edbc 280 #define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 281 #define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 282 #define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 283 #define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 284 #define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 285 #define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /* Bit fields for LCD STATUS */
AnnaBridge 171:3a7713b1edbc 288 #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 289 #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 290 #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
AnnaBridge 171:3a7713b1edbc 291 #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
AnnaBridge 171:3a7713b1edbc 292 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 293 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 294 #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
AnnaBridge 171:3a7713b1edbc 295 #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
AnnaBridge 171:3a7713b1edbc 296 #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
AnnaBridge 171:3a7713b1edbc 297 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 298 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 /* Bit fields for LCD AREGA */
AnnaBridge 171:3a7713b1edbc 301 #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 302 #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 303 #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 304 #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 305 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 306 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /* Bit fields for LCD AREGB */
AnnaBridge 171:3a7713b1edbc 309 #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 310 #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 311 #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 312 #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 313 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 314 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /* Bit fields for LCD IF */
AnnaBridge 171:3a7713b1edbc 317 #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
AnnaBridge 171:3a7713b1edbc 318 #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
AnnaBridge 171:3a7713b1edbc 319 #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 320 #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
AnnaBridge 171:3a7713b1edbc 321 #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
AnnaBridge 171:3a7713b1edbc 322 #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
AnnaBridge 171:3a7713b1edbc 323 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /* Bit fields for LCD IFS */
AnnaBridge 171:3a7713b1edbc 326 #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
AnnaBridge 171:3a7713b1edbc 327 #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
AnnaBridge 171:3a7713b1edbc 328 #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 329 #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
AnnaBridge 171:3a7713b1edbc 330 #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
AnnaBridge 171:3a7713b1edbc 331 #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
AnnaBridge 171:3a7713b1edbc 332 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /* Bit fields for LCD IFC */
AnnaBridge 171:3a7713b1edbc 335 #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
AnnaBridge 171:3a7713b1edbc 336 #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
AnnaBridge 171:3a7713b1edbc 337 #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 338 #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
AnnaBridge 171:3a7713b1edbc 339 #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
AnnaBridge 171:3a7713b1edbc 340 #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
AnnaBridge 171:3a7713b1edbc 341 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /* Bit fields for LCD IEN */
AnnaBridge 171:3a7713b1edbc 344 #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
AnnaBridge 171:3a7713b1edbc 345 #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
AnnaBridge 171:3a7713b1edbc 346 #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 347 #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
AnnaBridge 171:3a7713b1edbc 348 #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
AnnaBridge 171:3a7713b1edbc 349 #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
AnnaBridge 171:3a7713b1edbc 350 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 /* Bit fields for LCD SEGD0L */
AnnaBridge 171:3a7713b1edbc 353 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 354 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 355 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 356 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 357 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 358 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /* Bit fields for LCD SEGD1L */
AnnaBridge 171:3a7713b1edbc 361 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 362 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 363 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 364 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 365 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 366 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /* Bit fields for LCD SEGD2L */
AnnaBridge 171:3a7713b1edbc 369 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 370 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 371 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 372 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 373 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 374 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376 /* Bit fields for LCD SEGD3L */
AnnaBridge 171:3a7713b1edbc 377 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 378 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 379 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 380 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 381 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 382 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 383
AnnaBridge 171:3a7713b1edbc 384 /* Bit fields for LCD SEGD0H */
AnnaBridge 171:3a7713b1edbc 385 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 386 #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 387 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 388 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 389 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 390 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 /* Bit fields for LCD SEGD1H */
AnnaBridge 171:3a7713b1edbc 393 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 394 #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 395 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 396 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 397 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 398 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /* Bit fields for LCD SEGD2H */
AnnaBridge 171:3a7713b1edbc 401 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 402 #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 403 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 404 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 405 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 406 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 /* Bit fields for LCD SEGD3H */
AnnaBridge 171:3a7713b1edbc 409 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 410 #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 411 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 412 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 413 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 414 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /* Bit fields for LCD FREEZE */
AnnaBridge 171:3a7713b1edbc 417 #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 418 #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 419 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
AnnaBridge 171:3a7713b1edbc 420 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
AnnaBridge 171:3a7713b1edbc 421 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
AnnaBridge 171:3a7713b1edbc 422 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 423 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 424 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 425 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 426 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 427 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /* Bit fields for LCD SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 430 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 431 #define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 432 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
AnnaBridge 171:3a7713b1edbc 433 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 434 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
AnnaBridge 171:3a7713b1edbc 435 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 436 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 437 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
AnnaBridge 171:3a7713b1edbc 438 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 439 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
AnnaBridge 171:3a7713b1edbc 440 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 441 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 442 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
AnnaBridge 171:3a7713b1edbc 443 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 444 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
AnnaBridge 171:3a7713b1edbc 445 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 446 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 447 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
AnnaBridge 171:3a7713b1edbc 448 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 449 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
AnnaBridge 171:3a7713b1edbc 450 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 451 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 452 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
AnnaBridge 171:3a7713b1edbc 453 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 454 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
AnnaBridge 171:3a7713b1edbc 455 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 456 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 457 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
AnnaBridge 171:3a7713b1edbc 458 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 459 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
AnnaBridge 171:3a7713b1edbc 460 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 461 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 462 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
AnnaBridge 171:3a7713b1edbc 463 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 464 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
AnnaBridge 171:3a7713b1edbc 465 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 466 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 467 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
AnnaBridge 171:3a7713b1edbc 468 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 469 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
AnnaBridge 171:3a7713b1edbc 470 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 471 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 472 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
AnnaBridge 171:3a7713b1edbc 473 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 474 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
AnnaBridge 171:3a7713b1edbc 475 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 476 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 477 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
AnnaBridge 171:3a7713b1edbc 478 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 479 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
AnnaBridge 171:3a7713b1edbc 480 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 481 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 482 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
AnnaBridge 171:3a7713b1edbc 483 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 484 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
AnnaBridge 171:3a7713b1edbc 485 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 486 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 487 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
AnnaBridge 171:3a7713b1edbc 488 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 489 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
AnnaBridge 171:3a7713b1edbc 490 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 491 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 492 #define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */
AnnaBridge 171:3a7713b1edbc 493 #define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 494 #define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 495 #define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 496 #define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 497 #define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */
AnnaBridge 171:3a7713b1edbc 498 #define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 499 #define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 500 #define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 501 #define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 502 #define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */
AnnaBridge 171:3a7713b1edbc 503 #define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 504 #define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 505 #define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 506 #define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 507 #define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */
AnnaBridge 171:3a7713b1edbc 508 #define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 509 #define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 510 #define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 511 #define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 512 #define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */
AnnaBridge 171:3a7713b1edbc 513 #define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 514 #define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 515 #define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 516 #define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 517 #define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */
AnnaBridge 171:3a7713b1edbc 518 #define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 519 #define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 520 #define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 521 #define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 522 #define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */
AnnaBridge 171:3a7713b1edbc 523 #define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 524 #define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 525 #define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 526 #define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 527 #define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */
AnnaBridge 171:3a7713b1edbc 528 #define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 529 #define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 530 #define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 531 #define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 532
AnnaBridge 171:3a7713b1edbc 533 /* Bit fields for LCD SEGD4H */
AnnaBridge 171:3a7713b1edbc 534 #define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 535 #define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 536 #define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 537 #define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 538 #define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 539 #define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
AnnaBridge 171:3a7713b1edbc 540
AnnaBridge 171:3a7713b1edbc 541 /* Bit fields for LCD SEGD5H */
AnnaBridge 171:3a7713b1edbc 542 #define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 543 #define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 544 #define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 545 #define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 546 #define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 547 #define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /* Bit fields for LCD SEGD6H */
AnnaBridge 171:3a7713b1edbc 550 #define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 551 #define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 552 #define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 553 #define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 554 #define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 555 #define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /* Bit fields for LCD SEGD7H */
AnnaBridge 171:3a7713b1edbc 558 #define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 559 #define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 560 #define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 561 #define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 562 #define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 563 #define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 /* Bit fields for LCD SEGD4L */
AnnaBridge 171:3a7713b1edbc 566 #define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 567 #define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 568 #define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 569 #define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 570 #define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 571 #define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /* Bit fields for LCD SEGD5L */
AnnaBridge 171:3a7713b1edbc 574 #define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 575 #define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 576 #define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 577 #define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 578 #define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 579 #define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /* Bit fields for LCD SEGD6L */
AnnaBridge 171:3a7713b1edbc 582 #define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 583 #define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 584 #define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 585 #define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 586 #define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 587 #define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 /* Bit fields for LCD SEGD7L */
AnnaBridge 171:3a7713b1edbc 590 #define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 591 #define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 592 #define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 593 #define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 594 #define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 595 #define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /** @} End of group EFM32GG_LCD */
AnnaBridge 171:3a7713b1edbc 598 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 599