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TARGET_EFM32GG11_STK3701/TOOLCHAIN_IAR/efm32gg11b_sdio.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_sdio.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_SDIO register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43 /**************************************************************************//**
AnnaBridge 170:e95d10626187 44 * @defgroup EFM32GG11B_SDIO SDIO
AnnaBridge 170:e95d10626187 45 * @{
AnnaBridge 170:e95d10626187 46 * @brief EFM32GG11B_SDIO Register Declaration
AnnaBridge 170:e95d10626187 47 *****************************************************************************/
AnnaBridge 170:e95d10626187 48 /** SDIO Register Declaration */
AnnaBridge 170:e95d10626187 49 typedef struct {
AnnaBridge 170:e95d10626187 50 __IOM uint32_t SDMASYSADDR; /**< SDMA System address register */
AnnaBridge 170:e95d10626187 51 __IOM uint32_t BLKSIZE; /**< Block Size and Block count Register */
AnnaBridge 170:e95d10626187 52 __IOM uint32_t CMDARG1; /**< SD Command Argument Register */
AnnaBridge 170:e95d10626187 53 __IOM uint32_t TFRMODE; /**< Transfer mode and command Register */
AnnaBridge 170:e95d10626187 54 __IM uint32_t RESP0; /**< Response0 and Response1 Register */
AnnaBridge 170:e95d10626187 55 __IM uint32_t RESP2; /**< Response2 and Response3 Register */
AnnaBridge 170:e95d10626187 56 __IM uint32_t RESP4; /**< Response4 and Response5 Register */
AnnaBridge 170:e95d10626187 57 __IM uint32_t RESP6; /**< Response6 and Response7 Register */
AnnaBridge 170:e95d10626187 58 __IOM uint32_t BUFDATPORT; /**< Buffer Data Register */
AnnaBridge 170:e95d10626187 59 __IM uint32_t PRSSTAT; /**< Preset state Register */
AnnaBridge 170:e95d10626187 60 __IOM uint32_t HOSTCTRL1; /**< Host Control1, Power, Block gap and Wakeup-up control register */
AnnaBridge 170:e95d10626187 61 __IOM uint32_t CLOCKCTRL; /**< Clock Control, Timeout control and Software Register */
AnnaBridge 170:e95d10626187 62 __IOM uint32_t IFCR; /**< Normal and Error Interrupt status Register */
AnnaBridge 170:e95d10626187 63 __IOM uint32_t IFENC; /**< Normal and Error Interrupt status enable Register */
AnnaBridge 170:e95d10626187 64 __IOM uint32_t IEN; /**< Normal and Error Interrupt Signal Enable Register */
AnnaBridge 170:e95d10626187 65 __IOM uint32_t AC12ERRSTAT; /**< AUTO CMD12 Error Status and Host Control2 Register */
AnnaBridge 170:e95d10626187 66 __IM uint32_t CAPAB0; /**< Capabilities Register to hold bits 31~0 */
AnnaBridge 170:e95d10626187 67 __IM uint32_t CAPAB2; /**< Capabilities Register to hold bits 63~32 */
AnnaBridge 170:e95d10626187 68 __IM uint32_t MAXCURCAPAB; /**< Maximum Current Capabilities Register */
AnnaBridge 170:e95d10626187 69 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 70 __IOM uint32_t FEVTERRSTAT; /**< Force Event Register for Auto CMD error status */
AnnaBridge 170:e95d10626187 71 __IM uint32_t ADMAES; /**< ADMA Error Status Register */
AnnaBridge 170:e95d10626187 72 __IOM uint32_t ADSADDR; /**< ADMA System Address Register */
AnnaBridge 170:e95d10626187 73 uint32_t RESERVED1[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 74 __IM uint32_t PRSTVAL0; /**< Preset value for Initialization and Default Speed mode */
AnnaBridge 170:e95d10626187 75 __IM uint32_t PRSTVAL2; /**< Preset value for High Speed and SDR12 modes */
AnnaBridge 170:e95d10626187 76 __IM uint32_t PRSTVAL4; /**< Preset value for SDR25 and SDR50 modes */
AnnaBridge 170:e95d10626187 77 __IM uint32_t PRSTVAL6; /**< Preset value for SDR104 and DDR50 modes */
AnnaBridge 170:e95d10626187 78 __IOM uint32_t BOOTTOCTRL; /**< Boot Timeout Control Register */
AnnaBridge 170:e95d10626187 79 uint32_t RESERVED2[34]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 80 __IM uint32_t SLOTINTSTAT; /**< Slot Interrupt Status Register */
AnnaBridge 170:e95d10626187 81
AnnaBridge 170:e95d10626187 82 uint32_t RESERVED3[448]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 83 __IOM uint32_t CTRL; /**< Core Control Signals */
AnnaBridge 170:e95d10626187 84 __IOM uint32_t CFG0; /**< Core Configuration 0 */
AnnaBridge 170:e95d10626187 85 __IOM uint32_t CFG1; /**< Core Configuration 1 */
AnnaBridge 170:e95d10626187 86 __IOM uint32_t CFGPRESETVAL0; /**< Core Configuration preset value 0 */
AnnaBridge 170:e95d10626187 87 __IOM uint32_t CFGPRESETVAL1; /**< Core Configuration preset value 1 */
AnnaBridge 170:e95d10626187 88 __IOM uint32_t CFGPRESETVAL2; /**< Core Configuration preset value 2 */
AnnaBridge 170:e95d10626187 89 __IOM uint32_t CFGPRESETVAL3; /**< Core Configuration preset value 3 */
AnnaBridge 170:e95d10626187 90 __IOM uint32_t ROUTELOC0; /**< I/O LOCATION Register */
AnnaBridge 170:e95d10626187 91 __IOM uint32_t ROUTELOC1; /**< I/O LOCATION Register */
AnnaBridge 170:e95d10626187 92 __IOM uint32_t ROUTEPEN; /**< I/O LOCATION Enable Register */
AnnaBridge 170:e95d10626187 93 } SDIO_TypeDef; /** @} */
AnnaBridge 170:e95d10626187 94
AnnaBridge 170:e95d10626187 95 /**************************************************************************//**
AnnaBridge 170:e95d10626187 96 * @addtogroup EFM32GG11B_SDIO
AnnaBridge 170:e95d10626187 97 * @{
AnnaBridge 170:e95d10626187 98 * @defgroup EFM32GG11B_SDIO_BitFields SDIO Bit Fields
AnnaBridge 170:e95d10626187 99 * @{
AnnaBridge 170:e95d10626187 100 *****************************************************************************/
AnnaBridge 170:e95d10626187 101
AnnaBridge 170:e95d10626187 102 /* Bit fields for SDIO SDMASYSADDR */
AnnaBridge 170:e95d10626187 103 #define _SDIO_SDMASYSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_SDMASYSADDR */
AnnaBridge 170:e95d10626187 104 #define _SDIO_SDMASYSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_SDMASYSADDR */
AnnaBridge 170:e95d10626187 105 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_SHIFT 0 /**< Shift value for SDIO_SDMASYSADDRARG */
AnnaBridge 170:e95d10626187 106 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_SDMASYSADDRARG */
AnnaBridge 170:e95d10626187 107 #define _SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SDMASYSADDR */
AnnaBridge 170:e95d10626187 108 #define SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT (_SDIO_SDMASYSADDR_SDMASYSADDRARG_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SDMASYSADDR */
AnnaBridge 170:e95d10626187 109
AnnaBridge 170:e95d10626187 110 /* Bit fields for SDIO BLKSIZE */
AnnaBridge 170:e95d10626187 111 #define _SDIO_BLKSIZE_RESETVALUE 0x00000000UL /**< Default value for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 112 #define _SDIO_BLKSIZE_MASK 0xFFFF7FFFUL /**< Mask for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 113 #define _SDIO_BLKSIZE_TFRBLKSIZE_SHIFT 0 /**< Shift value for SDIO_TFRBLKSIZE */
AnnaBridge 170:e95d10626187 114 #define _SDIO_BLKSIZE_TFRBLKSIZE_MASK 0xFFFUL /**< Bit mask for SDIO_TFRBLKSIZE */
AnnaBridge 170:e95d10626187 115 #define _SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 116 #define _SDIO_BLKSIZE_TFRBLKSIZE_NOXFER 0x00000000UL /**< Mode NOXFER for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 117 #define SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT (_SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 118 #define SDIO_BLKSIZE_TFRBLKSIZE_NOXFER (_SDIO_BLKSIZE_TFRBLKSIZE_NOXFER << 0) /**< Shifted mode NOXFER for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 119 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SHIFT 12 /**< Shift value for SDIO_HSTSDMABUFSIZE */
AnnaBridge 170:e95d10626187 120 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_MASK 0x7000UL /**< Bit mask for SDIO_HSTSDMABUFSIZE */
AnnaBridge 170:e95d10626187 121 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 122 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 0x00000000UL /**< Mode SIZE4 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 123 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 0x00000001UL /**< Mode SIZE8 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 124 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 0x00000002UL /**< Mode SIZE16 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 125 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 0x00000003UL /**< Mode SIZE32 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 126 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 0x00000004UL /**< Mode SIZE64 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 127 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 0x00000005UL /**< Mode SIZE128 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 128 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 0x00000006UL /**< Mode SIZE256 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 129 #define _SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 0x00000007UL /**< Mode SIZE512 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 130 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT (_SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 131 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4 << 12) /**< Shifted mode SIZE4 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 132 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8 << 12) /**< Shifted mode SIZE8 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 133 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16 << 12) /**< Shifted mode SIZE16 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 134 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32 << 12) /**< Shifted mode SIZE32 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 135 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64 << 12) /**< Shifted mode SIZE64 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 136 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128 << 12) /**< Shifted mode SIZE128 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 137 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256 << 12) /**< Shifted mode SIZE256 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 138 #define SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 (_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512 << 12) /**< Shifted mode SIZE512 for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 139 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_SHIFT 16 /**< Shift value for SDIO_BLKSCNTFORCURRTFR */
AnnaBridge 170:e95d10626187 140 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_MASK 0xFFFF0000UL /**< Bit mask for SDIO_BLKSCNTFORCURRTFR */
AnnaBridge 170:e95d10626187 141 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 142 #define _SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT 0x00000000UL /**< Mode STOPCNT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 143 #define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 144 #define SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT (_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT << 16) /**< Shifted mode STOPCNT for SDIO_BLKSIZE */
AnnaBridge 170:e95d10626187 145
AnnaBridge 170:e95d10626187 146 /* Bit fields for SDIO CMDARG1 */
AnnaBridge 170:e95d10626187 147 #define _SDIO_CMDARG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 148 #define _SDIO_CMDARG1_MASK 0xFFFFFFFFUL /**< Mask for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 149 #define _SDIO_CMDARG1_CMDARG1_SHIFT 0 /**< Shift value for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 150 #define _SDIO_CMDARG1_CMDARG1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 151 #define _SDIO_CMDARG1_CMDARG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 152 #define SDIO_CMDARG1_CMDARG1_DEFAULT (_SDIO_CMDARG1_CMDARG1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CMDARG1 */
AnnaBridge 170:e95d10626187 153
AnnaBridge 170:e95d10626187 154 /* Bit fields for SDIO TFRMODE */
AnnaBridge 170:e95d10626187 155 #define _SDIO_TFRMODE_RESETVALUE 0x00000000UL /**< Default value for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 156 #define _SDIO_TFRMODE_MASK 0x3FFB003FUL /**< Mask for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 157 #define SDIO_TFRMODE_DMAEN (0x1UL << 0) /**< DMA Enable */
AnnaBridge 170:e95d10626187 158 #define _SDIO_TFRMODE_DMAEN_SHIFT 0 /**< Shift value for SDIO_DMAEN */
AnnaBridge 170:e95d10626187 159 #define _SDIO_TFRMODE_DMAEN_MASK 0x1UL /**< Bit mask for SDIO_DMAEN */
AnnaBridge 170:e95d10626187 160 #define _SDIO_TFRMODE_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 161 #define _SDIO_TFRMODE_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 162 #define _SDIO_TFRMODE_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 163 #define SDIO_TFRMODE_DMAEN_DEFAULT (_SDIO_TFRMODE_DMAEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 164 #define SDIO_TFRMODE_DMAEN_DISABLE (_SDIO_TFRMODE_DMAEN_DISABLE << 0) /**< Shifted mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 165 #define SDIO_TFRMODE_DMAEN_ENABLE (_SDIO_TFRMODE_DMAEN_ENABLE << 0) /**< Shifted mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 166 #define SDIO_TFRMODE_BLKCNTEN (0x1UL << 1) /**< Block Count Enable */
AnnaBridge 170:e95d10626187 167 #define _SDIO_TFRMODE_BLKCNTEN_SHIFT 1 /**< Shift value for SDIO_BLKCNTEN */
AnnaBridge 170:e95d10626187 168 #define _SDIO_TFRMODE_BLKCNTEN_MASK 0x2UL /**< Bit mask for SDIO_BLKCNTEN */
AnnaBridge 170:e95d10626187 169 #define _SDIO_TFRMODE_BLKCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 170 #define _SDIO_TFRMODE_BLKCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 171 #define _SDIO_TFRMODE_BLKCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 172 #define SDIO_TFRMODE_BLKCNTEN_DEFAULT (_SDIO_TFRMODE_BLKCNTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 173 #define SDIO_TFRMODE_BLKCNTEN_DISABLE (_SDIO_TFRMODE_BLKCNTEN_DISABLE << 1) /**< Shifted mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 174 #define SDIO_TFRMODE_BLKCNTEN_ENABLE (_SDIO_TFRMODE_BLKCNTEN_ENABLE << 1) /**< Shifted mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 175 #define _SDIO_TFRMODE_AUTOCMDEN_SHIFT 2 /**< Shift value for SDIO_AUTOCMDEN */
AnnaBridge 170:e95d10626187 176 #define _SDIO_TFRMODE_AUTOCMDEN_MASK 0xCUL /**< Bit mask for SDIO_AUTOCMDEN */
AnnaBridge 170:e95d10626187 177 #define _SDIO_TFRMODE_AUTOCMDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 178 #define _SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED 0x00000000UL /**< Mode ACMDDISABLED for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 179 #define _SDIO_TFRMODE_AUTOCMDEN_ACMD12EN 0x00000001UL /**< Mode ACMD12EN for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 180 #define _SDIO_TFRMODE_AUTOCMDEN_ACMD23EN 0x00000002UL /**< Mode ACMD23EN for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 181 #define SDIO_TFRMODE_AUTOCMDEN_DEFAULT (_SDIO_TFRMODE_AUTOCMDEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 182 #define SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED (_SDIO_TFRMODE_AUTOCMDEN_ACMDDISABLED << 2) /**< Shifted mode ACMDDISABLED for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 183 #define SDIO_TFRMODE_AUTOCMDEN_ACMD12EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD12EN << 2) /**< Shifted mode ACMD12EN for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 184 #define SDIO_TFRMODE_AUTOCMDEN_ACMD23EN (_SDIO_TFRMODE_AUTOCMDEN_ACMD23EN << 2) /**< Shifted mode ACMD23EN for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 185 #define SDIO_TFRMODE_DATDIRSEL (0x1UL << 4) /**< Data Transfer Direction Select */
AnnaBridge 170:e95d10626187 186 #define _SDIO_TFRMODE_DATDIRSEL_SHIFT 4 /**< Shift value for SDIO_DATDIRSEL */
AnnaBridge 170:e95d10626187 187 #define _SDIO_TFRMODE_DATDIRSEL_MASK 0x10UL /**< Bit mask for SDIO_DATDIRSEL */
AnnaBridge 170:e95d10626187 188 #define _SDIO_TFRMODE_DATDIRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 189 #define _SDIO_TFRMODE_DATDIRSEL_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 190 #define _SDIO_TFRMODE_DATDIRSEL_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 191 #define SDIO_TFRMODE_DATDIRSEL_DEFAULT (_SDIO_TFRMODE_DATDIRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 192 #define SDIO_TFRMODE_DATDIRSEL_DISABLE (_SDIO_TFRMODE_DATDIRSEL_DISABLE << 4) /**< Shifted mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 193 #define SDIO_TFRMODE_DATDIRSEL_ENABLE (_SDIO_TFRMODE_DATDIRSEL_ENABLE << 4) /**< Shifted mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 194 #define SDIO_TFRMODE_MULTSINGBLKSEL (0x1UL << 5) /**< Multiple or Single block data transfer selection */
AnnaBridge 170:e95d10626187 195 #define _SDIO_TFRMODE_MULTSINGBLKSEL_SHIFT 5 /**< Shift value for SDIO_MULTSINGBLKSEL */
AnnaBridge 170:e95d10626187 196 #define _SDIO_TFRMODE_MULTSINGBLKSEL_MASK 0x20UL /**< Bit mask for SDIO_MULTSINGBLKSEL */
AnnaBridge 170:e95d10626187 197 #define _SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 198 #define _SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK 0x00000000UL /**< Mode SINGLEBLK for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 199 #define _SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK 0x00000001UL /**< Mode MULTIBLK for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 200 #define SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT (_SDIO_TFRMODE_MULTSINGBLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 201 #define SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_SINGLEBLK << 5) /**< Shifted mode SINGLEBLK for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 202 #define SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK (_SDIO_TFRMODE_MULTSINGBLKSEL_MULTIBLK << 5) /**< Shifted mode MULTIBLK for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 203 #define _SDIO_TFRMODE_RESPTYPESEL_SHIFT 16 /**< Shift value for SDIO_RESPTYPESEL */
AnnaBridge 170:e95d10626187 204 #define _SDIO_TFRMODE_RESPTYPESEL_MASK 0x30000UL /**< Bit mask for SDIO_RESPTYPESEL */
AnnaBridge 170:e95d10626187 205 #define _SDIO_TFRMODE_RESPTYPESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 206 #define _SDIO_TFRMODE_RESPTYPESEL_NORESP 0x00000000UL /**< Mode NORESP for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 207 #define _SDIO_TFRMODE_RESPTYPESEL_RESP136 0x00000001UL /**< Mode RESP136 for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 208 #define _SDIO_TFRMODE_RESPTYPESEL_RESP48 0x00000002UL /**< Mode RESP48 for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 209 #define _SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP 0x00000003UL /**< Mode BUSYAFTRESP for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 210 #define SDIO_TFRMODE_RESPTYPESEL_DEFAULT (_SDIO_TFRMODE_RESPTYPESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 211 #define SDIO_TFRMODE_RESPTYPESEL_NORESP (_SDIO_TFRMODE_RESPTYPESEL_NORESP << 16) /**< Shifted mode NORESP for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 212 #define SDIO_TFRMODE_RESPTYPESEL_RESP136 (_SDIO_TFRMODE_RESPTYPESEL_RESP136 << 16) /**< Shifted mode RESP136 for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 213 #define SDIO_TFRMODE_RESPTYPESEL_RESP48 (_SDIO_TFRMODE_RESPTYPESEL_RESP48 << 16) /**< Shifted mode RESP48 for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 214 #define SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP (_SDIO_TFRMODE_RESPTYPESEL_BUSYAFTRESP << 16) /**< Shifted mode BUSYAFTRESP for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 215 #define SDIO_TFRMODE_CMDCRCCHKEN (0x1UL << 19) /**< Command CRC Check Enable */
AnnaBridge 170:e95d10626187 216 #define _SDIO_TFRMODE_CMDCRCCHKEN_SHIFT 19 /**< Shift value for SDIO_CMDCRCCHKEN */
AnnaBridge 170:e95d10626187 217 #define _SDIO_TFRMODE_CMDCRCCHKEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDCRCCHKEN */
AnnaBridge 170:e95d10626187 218 #define _SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 219 #define _SDIO_TFRMODE_CMDCRCCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 220 #define _SDIO_TFRMODE_CMDCRCCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 221 #define SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT (_SDIO_TFRMODE_CMDCRCCHKEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 222 #define SDIO_TFRMODE_CMDCRCCHKEN_DISABLE (_SDIO_TFRMODE_CMDCRCCHKEN_DISABLE << 19) /**< Shifted mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 223 #define SDIO_TFRMODE_CMDCRCCHKEN_ENABLE (_SDIO_TFRMODE_CMDCRCCHKEN_ENABLE << 19) /**< Shifted mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 224 #define SDIO_TFRMODE_CMDINDXCHKEN (0x1UL << 20) /**< Command Index Check Enable */
AnnaBridge 170:e95d10626187 225 #define _SDIO_TFRMODE_CMDINDXCHKEN_SHIFT 20 /**< Shift value for SDIO_CMDINDXCHKEN */
AnnaBridge 170:e95d10626187 226 #define _SDIO_TFRMODE_CMDINDXCHKEN_MASK 0x100000UL /**< Bit mask for SDIO_CMDINDXCHKEN */
AnnaBridge 170:e95d10626187 227 #define _SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 228 #define _SDIO_TFRMODE_CMDINDXCHKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 229 #define _SDIO_TFRMODE_CMDINDXCHKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 230 #define SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT (_SDIO_TFRMODE_CMDINDXCHKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 231 #define SDIO_TFRMODE_CMDINDXCHKEN_DISABLE (_SDIO_TFRMODE_CMDINDXCHKEN_DISABLE << 20) /**< Shifted mode DISABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 232 #define SDIO_TFRMODE_CMDINDXCHKEN_ENABLE (_SDIO_TFRMODE_CMDINDXCHKEN_ENABLE << 20) /**< Shifted mode ENABLE for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 233 #define SDIO_TFRMODE_DATPRESSEL (0x1UL << 21) /**< Data Present Select */
AnnaBridge 170:e95d10626187 234 #define _SDIO_TFRMODE_DATPRESSEL_SHIFT 21 /**< Shift value for SDIO_DATPRESSEL */
AnnaBridge 170:e95d10626187 235 #define _SDIO_TFRMODE_DATPRESSEL_MASK 0x200000UL /**< Bit mask for SDIO_DATPRESSEL */
AnnaBridge 170:e95d10626187 236 #define _SDIO_TFRMODE_DATPRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 237 #define _SDIO_TFRMODE_DATPRESSEL_NODATA 0x00000000UL /**< Mode NODATA for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 238 #define _SDIO_TFRMODE_DATPRESSEL_DATA 0x00000001UL /**< Mode DATA for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 239 #define SDIO_TFRMODE_DATPRESSEL_DEFAULT (_SDIO_TFRMODE_DATPRESSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 240 #define SDIO_TFRMODE_DATPRESSEL_NODATA (_SDIO_TFRMODE_DATPRESSEL_NODATA << 21) /**< Shifted mode NODATA for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 241 #define SDIO_TFRMODE_DATPRESSEL_DATA (_SDIO_TFRMODE_DATPRESSEL_DATA << 21) /**< Shifted mode DATA for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 242 #define _SDIO_TFRMODE_CMDTYPE_SHIFT 22 /**< Shift value for SDIO_CMDTYPE */
AnnaBridge 170:e95d10626187 243 #define _SDIO_TFRMODE_CMDTYPE_MASK 0xC00000UL /**< Bit mask for SDIO_CMDTYPE */
AnnaBridge 170:e95d10626187 244 #define _SDIO_TFRMODE_CMDTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 245 #define _SDIO_TFRMODE_CMDTYPE_NORMAL 0x00000000UL /**< Mode NORMAL for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 246 #define _SDIO_TFRMODE_CMDTYPE_SUSPEND 0x00000001UL /**< Mode SUSPEND for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 247 #define _SDIO_TFRMODE_CMDTYPE_RESUME 0x00000002UL /**< Mode RESUME for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 248 #define _SDIO_TFRMODE_CMDTYPE_ABORT 0x00000003UL /**< Mode ABORT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 249 #define SDIO_TFRMODE_CMDTYPE_DEFAULT (_SDIO_TFRMODE_CMDTYPE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 250 #define SDIO_TFRMODE_CMDTYPE_NORMAL (_SDIO_TFRMODE_CMDTYPE_NORMAL << 22) /**< Shifted mode NORMAL for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 251 #define SDIO_TFRMODE_CMDTYPE_SUSPEND (_SDIO_TFRMODE_CMDTYPE_SUSPEND << 22) /**< Shifted mode SUSPEND for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 252 #define SDIO_TFRMODE_CMDTYPE_RESUME (_SDIO_TFRMODE_CMDTYPE_RESUME << 22) /**< Shifted mode RESUME for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 253 #define SDIO_TFRMODE_CMDTYPE_ABORT (_SDIO_TFRMODE_CMDTYPE_ABORT << 22) /**< Shifted mode ABORT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 254 #define _SDIO_TFRMODE_CMDINDEX_SHIFT 24 /**< Shift value for SDIO_CMDINDEX */
AnnaBridge 170:e95d10626187 255 #define _SDIO_TFRMODE_CMDINDEX_MASK 0x3F000000UL /**< Bit mask for SDIO_CMDINDEX */
AnnaBridge 170:e95d10626187 256 #define _SDIO_TFRMODE_CMDINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 257 #define SDIO_TFRMODE_CMDINDEX_DEFAULT (_SDIO_TFRMODE_CMDINDEX_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_TFRMODE */
AnnaBridge 170:e95d10626187 258
AnnaBridge 170:e95d10626187 259 /* Bit fields for SDIO RESP0 */
AnnaBridge 170:e95d10626187 260 #define _SDIO_RESP0_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP0 */
AnnaBridge 170:e95d10626187 261 #define _SDIO_RESP0_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP0 */
AnnaBridge 170:e95d10626187 262 #define _SDIO_RESP0_CMDRESP0_SHIFT 0 /**< Shift value for SDIO_CMDRESP0 */
AnnaBridge 170:e95d10626187 263 #define _SDIO_RESP0_CMDRESP0_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP0 */
AnnaBridge 170:e95d10626187 264 #define _SDIO_RESP0_CMDRESP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP0 */
AnnaBridge 170:e95d10626187 265 #define SDIO_RESP0_CMDRESP0_DEFAULT (_SDIO_RESP0_CMDRESP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP0 */
AnnaBridge 170:e95d10626187 266
AnnaBridge 170:e95d10626187 267 /* Bit fields for SDIO RESP2 */
AnnaBridge 170:e95d10626187 268 #define _SDIO_RESP2_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP2 */
AnnaBridge 170:e95d10626187 269 #define _SDIO_RESP2_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP2 */
AnnaBridge 170:e95d10626187 270 #define _SDIO_RESP2_CMDRESP1_SHIFT 0 /**< Shift value for SDIO_CMDRESP1 */
AnnaBridge 170:e95d10626187 271 #define _SDIO_RESP2_CMDRESP1_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP1 */
AnnaBridge 170:e95d10626187 272 #define _SDIO_RESP2_CMDRESP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP2 */
AnnaBridge 170:e95d10626187 273 #define SDIO_RESP2_CMDRESP1_DEFAULT (_SDIO_RESP2_CMDRESP1_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP2 */
AnnaBridge 170:e95d10626187 274
AnnaBridge 170:e95d10626187 275 /* Bit fields for SDIO RESP4 */
AnnaBridge 170:e95d10626187 276 #define _SDIO_RESP4_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP4 */
AnnaBridge 170:e95d10626187 277 #define _SDIO_RESP4_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP4 */
AnnaBridge 170:e95d10626187 278 #define _SDIO_RESP4_CMDRESP2_SHIFT 0 /**< Shift value for SDIO_CMDRESP2 */
AnnaBridge 170:e95d10626187 279 #define _SDIO_RESP4_CMDRESP2_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP2 */
AnnaBridge 170:e95d10626187 280 #define _SDIO_RESP4_CMDRESP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP4 */
AnnaBridge 170:e95d10626187 281 #define SDIO_RESP4_CMDRESP2_DEFAULT (_SDIO_RESP4_CMDRESP2_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP4 */
AnnaBridge 170:e95d10626187 282
AnnaBridge 170:e95d10626187 283 /* Bit fields for SDIO RESP6 */
AnnaBridge 170:e95d10626187 284 #define _SDIO_RESP6_RESETVALUE 0x00000000UL /**< Default value for SDIO_RESP6 */
AnnaBridge 170:e95d10626187 285 #define _SDIO_RESP6_MASK 0xFFFFFFFFUL /**< Mask for SDIO_RESP6 */
AnnaBridge 170:e95d10626187 286 #define _SDIO_RESP6_CMDRESP3_SHIFT 0 /**< Shift value for SDIO_CMDRESP3 */
AnnaBridge 170:e95d10626187 287 #define _SDIO_RESP6_CMDRESP3_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_CMDRESP3 */
AnnaBridge 170:e95d10626187 288 #define _SDIO_RESP6_CMDRESP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_RESP6 */
AnnaBridge 170:e95d10626187 289 #define SDIO_RESP6_CMDRESP3_DEFAULT (_SDIO_RESP6_CMDRESP3_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_RESP6 */
AnnaBridge 170:e95d10626187 290
AnnaBridge 170:e95d10626187 291 /* Bit fields for SDIO BUFDATPORT */
AnnaBridge 170:e95d10626187 292 #define _SDIO_BUFDATPORT_RESETVALUE 0x00000000UL /**< Default value for SDIO_BUFDATPORT */
AnnaBridge 170:e95d10626187 293 #define _SDIO_BUFDATPORT_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BUFDATPORT */
AnnaBridge 170:e95d10626187 294 #define _SDIO_BUFDATPORT_BUFDAT_SHIFT 0 /**< Shift value for SDIO_BUFDAT */
AnnaBridge 170:e95d10626187 295 #define _SDIO_BUFDATPORT_BUFDAT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BUFDAT */
AnnaBridge 170:e95d10626187 296 #define _SDIO_BUFDATPORT_BUFDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BUFDATPORT */
AnnaBridge 170:e95d10626187 297 #define SDIO_BUFDATPORT_BUFDAT_DEFAULT (_SDIO_BUFDATPORT_BUFDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BUFDATPORT */
AnnaBridge 170:e95d10626187 298
AnnaBridge 170:e95d10626187 299 /* Bit fields for SDIO PRSSTAT */
AnnaBridge 170:e95d10626187 300 #define _SDIO_PRSSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 301 #define _SDIO_PRSSTAT_MASK 0x1FFF0F0FUL /**< Mask for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 302 #define SDIO_PRSSTAT_CMDINHIBITCMD (0x1UL << 0) /**< Command Inhibit (CMD) */
AnnaBridge 170:e95d10626187 303 #define _SDIO_PRSSTAT_CMDINHIBITCMD_SHIFT 0 /**< Shift value for SDIO_CMDINHIBITCMD */
AnnaBridge 170:e95d10626187 304 #define _SDIO_PRSSTAT_CMDINHIBITCMD_MASK 0x1UL /**< Bit mask for SDIO_CMDINHIBITCMD */
AnnaBridge 170:e95d10626187 305 #define _SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 306 #define SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 307 #define SDIO_PRSSTAT_CMDINHIBITDAT (0x1UL << 1) /**< Command Inhibit (DAT) */
AnnaBridge 170:e95d10626187 308 #define _SDIO_PRSSTAT_CMDINHIBITDAT_SHIFT 1 /**< Shift value for SDIO_CMDINHIBITDAT */
AnnaBridge 170:e95d10626187 309 #define _SDIO_PRSSTAT_CMDINHIBITDAT_MASK 0x2UL /**< Bit mask for SDIO_CMDINHIBITDAT */
AnnaBridge 170:e95d10626187 310 #define _SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 311 #define SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT (_SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 312 #define SDIO_PRSSTAT_DATLINEACTIVE (0x1UL << 2) /**< DAT line active */
AnnaBridge 170:e95d10626187 313 #define _SDIO_PRSSTAT_DATLINEACTIVE_SHIFT 2 /**< Shift value for SDIO_DATLINEACTIVE */
AnnaBridge 170:e95d10626187 314 #define _SDIO_PRSSTAT_DATLINEACTIVE_MASK 0x4UL /**< Bit mask for SDIO_DATLINEACTIVE */
AnnaBridge 170:e95d10626187 315 #define _SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 316 #define SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT (_SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 317 #define SDIO_PRSSTAT_RETUNINGREQ (0x1UL << 3) /**< Re-Tuning Request */
AnnaBridge 170:e95d10626187 318 #define _SDIO_PRSSTAT_RETUNINGREQ_SHIFT 3 /**< Shift value for SDIO_RETUNINGREQ */
AnnaBridge 170:e95d10626187 319 #define _SDIO_PRSSTAT_RETUNINGREQ_MASK 0x8UL /**< Bit mask for SDIO_RETUNINGREQ */
AnnaBridge 170:e95d10626187 320 #define _SDIO_PRSSTAT_RETUNINGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 321 #define SDIO_PRSSTAT_RETUNINGREQ_DEFAULT (_SDIO_PRSSTAT_RETUNINGREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 322 #define SDIO_PRSSTAT_WRTRANACT (0x1UL << 8) /**< Write Transfer Active */
AnnaBridge 170:e95d10626187 323 #define _SDIO_PRSSTAT_WRTRANACT_SHIFT 8 /**< Shift value for SDIO_WRTRANACT */
AnnaBridge 170:e95d10626187 324 #define _SDIO_PRSSTAT_WRTRANACT_MASK 0x100UL /**< Bit mask for SDIO_WRTRANACT */
AnnaBridge 170:e95d10626187 325 #define _SDIO_PRSSTAT_WRTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 326 #define SDIO_PRSSTAT_WRTRANACT_DEFAULT (_SDIO_PRSSTAT_WRTRANACT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 327 #define SDIO_PRSSTAT_RDTRANACT (0x1UL << 9) /**< Read Transfer Active */
AnnaBridge 170:e95d10626187 328 #define _SDIO_PRSSTAT_RDTRANACT_SHIFT 9 /**< Shift value for SDIO_RDTRANACT */
AnnaBridge 170:e95d10626187 329 #define _SDIO_PRSSTAT_RDTRANACT_MASK 0x200UL /**< Bit mask for SDIO_RDTRANACT */
AnnaBridge 170:e95d10626187 330 #define _SDIO_PRSSTAT_RDTRANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 331 #define SDIO_PRSSTAT_RDTRANACT_DEFAULT (_SDIO_PRSSTAT_RDTRANACT_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 332 #define SDIO_PRSSTAT_BUFFERWRITEENABLE (0x1UL << 10) /**< Buffer Write Enable */
AnnaBridge 170:e95d10626187 333 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_SHIFT 10 /**< Shift value for SDIO_BUFFERWRITEENABLE */
AnnaBridge 170:e95d10626187 334 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_MASK 0x400UL /**< Bit mask for SDIO_BUFFERWRITEENABLE */
AnnaBridge 170:e95d10626187 335 #define _SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 336 #define SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT (_SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 337 #define SDIO_PRSSTAT_BUFRDEN (0x1UL << 11) /**< Buffer Read Enable */
AnnaBridge 170:e95d10626187 338 #define _SDIO_PRSSTAT_BUFRDEN_SHIFT 11 /**< Shift value for SDIO_BUFRDEN */
AnnaBridge 170:e95d10626187 339 #define _SDIO_PRSSTAT_BUFRDEN_MASK 0x800UL /**< Bit mask for SDIO_BUFRDEN */
AnnaBridge 170:e95d10626187 340 #define _SDIO_PRSSTAT_BUFRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 341 #define SDIO_PRSSTAT_BUFRDEN_DEFAULT (_SDIO_PRSSTAT_BUFRDEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 342 #define SDIO_PRSSTAT_CARDINS (0x1UL << 16) /**< Card Inserted Status */
AnnaBridge 170:e95d10626187 343 #define _SDIO_PRSSTAT_CARDINS_SHIFT 16 /**< Shift value for SDIO_CARDINS */
AnnaBridge 170:e95d10626187 344 #define _SDIO_PRSSTAT_CARDINS_MASK 0x10000UL /**< Bit mask for SDIO_CARDINS */
AnnaBridge 170:e95d10626187 345 #define _SDIO_PRSSTAT_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 346 #define SDIO_PRSSTAT_CARDINS_DEFAULT (_SDIO_PRSSTAT_CARDINS_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 347 #define SDIO_PRSSTAT_CARDSTATESTABLE (0x1UL << 17) /**< Card state Stable status */
AnnaBridge 170:e95d10626187 348 #define _SDIO_PRSSTAT_CARDSTATESTABLE_SHIFT 17 /**< Shift value for SDIO_CARDSTATESTABLE */
AnnaBridge 170:e95d10626187 349 #define _SDIO_PRSSTAT_CARDSTATESTABLE_MASK 0x20000UL /**< Bit mask for SDIO_CARDSTATESTABLE */
AnnaBridge 170:e95d10626187 350 #define _SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 351 #define SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT (_SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 352 #define SDIO_PRSSTAT_CARDDETPINLVL (0x1UL << 18) /**< Card Detect Pin Level */
AnnaBridge 170:e95d10626187 353 #define _SDIO_PRSSTAT_CARDDETPINLVL_SHIFT 18 /**< Shift value for SDIO_CARDDETPINLVL */
AnnaBridge 170:e95d10626187 354 #define _SDIO_PRSSTAT_CARDDETPINLVL_MASK 0x40000UL /**< Bit mask for SDIO_CARDDETPINLVL */
AnnaBridge 170:e95d10626187 355 #define _SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 356 #define SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT (_SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 357 #define SDIO_PRSSTAT_WRPROTSWPINLVL (0x1UL << 19) /**< Write Protect Switch Pin level */
AnnaBridge 170:e95d10626187 358 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_SHIFT 19 /**< Shift value for SDIO_WRPROTSWPINLVL */
AnnaBridge 170:e95d10626187 359 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_MASK 0x80000UL /**< Bit mask for SDIO_WRPROTSWPINLVL */
AnnaBridge 170:e95d10626187 360 #define _SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 361 #define SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT (_SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 362 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_SHIFT 20 /**< Shift value for SDIO_DAT3TO0SIGLVL */
AnnaBridge 170:e95d10626187 363 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_MASK 0xF00000UL /**< Bit mask for SDIO_DAT3TO0SIGLVL */
AnnaBridge 170:e95d10626187 364 #define _SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 365 #define SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 366 #define SDIO_PRSSTAT_CMDSIGLVL (0x1UL << 24) /**< Command Line Signal level */
AnnaBridge 170:e95d10626187 367 #define _SDIO_PRSSTAT_CMDSIGLVL_SHIFT 24 /**< Shift value for SDIO_CMDSIGLVL */
AnnaBridge 170:e95d10626187 368 #define _SDIO_PRSSTAT_CMDSIGLVL_MASK 0x1000000UL /**< Bit mask for SDIO_CMDSIGLVL */
AnnaBridge 170:e95d10626187 369 #define _SDIO_PRSSTAT_CMDSIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 370 #define SDIO_PRSSTAT_CMDSIGLVL_DEFAULT (_SDIO_PRSSTAT_CMDSIGLVL_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 371 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_SHIFT 25 /**< Shift value for SDIO_DAT7TO4SIGLVL */
AnnaBridge 170:e95d10626187 372 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_MASK 0x1E000000UL /**< Bit mask for SDIO_DAT7TO4SIGLVL */
AnnaBridge 170:e95d10626187 373 #define _SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 374 #define SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT (_SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_PRSSTAT */
AnnaBridge 170:e95d10626187 375
AnnaBridge 170:e95d10626187 376 /* Bit fields for SDIO HOSTCTRL1 */
AnnaBridge 170:e95d10626187 377 #define _SDIO_HOSTCTRL1_RESETVALUE 0x00800000UL /**< Default value for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 378 #define _SDIO_HOSTCTRL1_MASK 0x07FF1FFFUL /**< Mask for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 379 #define SDIO_HOSTCTRL1_LEDCTRL (0x1UL << 0) /**< LED Control */
AnnaBridge 170:e95d10626187 380 #define _SDIO_HOSTCTRL1_LEDCTRL_SHIFT 0 /**< Shift value for SDIO_LEDCTRL */
AnnaBridge 170:e95d10626187 381 #define _SDIO_HOSTCTRL1_LEDCTRL_MASK 0x1UL /**< Bit mask for SDIO_LEDCTRL */
AnnaBridge 170:e95d10626187 382 #define _SDIO_HOSTCTRL1_LEDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 383 #define _SDIO_HOSTCTRL1_LEDCTRL_LEDOFF 0x00000000UL /**< Mode LEDOFF for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 384 #define _SDIO_HOSTCTRL1_LEDCTRL_LEDON 0x00000001UL /**< Mode LEDON for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 385 #define SDIO_HOSTCTRL1_LEDCTRL_DEFAULT (_SDIO_HOSTCTRL1_LEDCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 386 #define SDIO_HOSTCTRL1_LEDCTRL_LEDOFF (_SDIO_HOSTCTRL1_LEDCTRL_LEDOFF << 0) /**< Shifted mode LEDOFF for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 387 #define SDIO_HOSTCTRL1_LEDCTRL_LEDON (_SDIO_HOSTCTRL1_LEDCTRL_LEDON << 0) /**< Shifted mode LEDON for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 388 #define SDIO_HOSTCTRL1_DATTRANWD (0x1UL << 1) /**< Data Transfer width 1-bit or 4-bit mode */
AnnaBridge 170:e95d10626187 389 #define _SDIO_HOSTCTRL1_DATTRANWD_SHIFT 1 /**< Shift value for SDIO_DATTRANWD */
AnnaBridge 170:e95d10626187 390 #define _SDIO_HOSTCTRL1_DATTRANWD_MASK 0x2UL /**< Bit mask for SDIO_DATTRANWD */
AnnaBridge 170:e95d10626187 391 #define _SDIO_HOSTCTRL1_DATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 392 #define _SDIO_HOSTCTRL1_DATTRANWD_SD1 0x00000000UL /**< Mode SD1 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 393 #define _SDIO_HOSTCTRL1_DATTRANWD_SD4 0x00000001UL /**< Mode SD4 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 394 #define SDIO_HOSTCTRL1_DATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_DATTRANWD_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 395 #define SDIO_HOSTCTRL1_DATTRANWD_SD1 (_SDIO_HOSTCTRL1_DATTRANWD_SD1 << 1) /**< Shifted mode SD1 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 396 #define SDIO_HOSTCTRL1_DATTRANWD_SD4 (_SDIO_HOSTCTRL1_DATTRANWD_SD4 << 1) /**< Shifted mode SD4 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 397 #define SDIO_HOSTCTRL1_HSEN (0x1UL << 2) /**< High Speed Enable */
AnnaBridge 170:e95d10626187 398 #define _SDIO_HOSTCTRL1_HSEN_SHIFT 2 /**< Shift value for SDIO_HSEN */
AnnaBridge 170:e95d10626187 399 #define _SDIO_HOSTCTRL1_HSEN_MASK 0x4UL /**< Bit mask for SDIO_HSEN */
AnnaBridge 170:e95d10626187 400 #define _SDIO_HOSTCTRL1_HSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 401 #define _SDIO_HOSTCTRL1_HSEN_NS 0x00000000UL /**< Mode NS for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 402 #define _SDIO_HOSTCTRL1_HSEN_HS 0x00000001UL /**< Mode HS for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 403 #define SDIO_HOSTCTRL1_HSEN_DEFAULT (_SDIO_HOSTCTRL1_HSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 404 #define SDIO_HOSTCTRL1_HSEN_NS (_SDIO_HOSTCTRL1_HSEN_NS << 2) /**< Shifted mode NS for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 405 #define SDIO_HOSTCTRL1_HSEN_HS (_SDIO_HOSTCTRL1_HSEN_HS << 2) /**< Shifted mode HS for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 406 #define _SDIO_HOSTCTRL1_DMASEL_SHIFT 3 /**< Shift value for SDIO_DMASEL */
AnnaBridge 170:e95d10626187 407 #define _SDIO_HOSTCTRL1_DMASEL_MASK 0x18UL /**< Bit mask for SDIO_DMASEL */
AnnaBridge 170:e95d10626187 408 #define _SDIO_HOSTCTRL1_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 409 #define _SDIO_HOSTCTRL1_DMASEL_SDMA 0x00000000UL /**< Mode SDMA for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 410 #define _SDIO_HOSTCTRL1_DMASEL_ADMA1 0x00000001UL /**< Mode ADMA1 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 411 #define _SDIO_HOSTCTRL1_DMASEL_ADMA2 0x00000002UL /**< Mode ADMA2 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 412 #define _SDIO_HOSTCTRL1_DMASEL_64BITADMA2 0x00000003UL /**< Mode 64BITADMA2 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 413 #define SDIO_HOSTCTRL1_DMASEL_DEFAULT (_SDIO_HOSTCTRL1_DMASEL_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 414 #define SDIO_HOSTCTRL1_DMASEL_SDMA (_SDIO_HOSTCTRL1_DMASEL_SDMA << 3) /**< Shifted mode SDMA for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 415 #define SDIO_HOSTCTRL1_DMASEL_ADMA1 (_SDIO_HOSTCTRL1_DMASEL_ADMA1 << 3) /**< Shifted mode ADMA1 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 416 #define SDIO_HOSTCTRL1_DMASEL_ADMA2 (_SDIO_HOSTCTRL1_DMASEL_ADMA2 << 3) /**< Shifted mode ADMA2 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 417 #define SDIO_HOSTCTRL1_DMASEL_64BITADMA2 (_SDIO_HOSTCTRL1_DMASEL_64BITADMA2 << 3) /**< Shifted mode 64BITADMA2 for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 418 #define SDIO_HOSTCTRL1_EXTDATTRANWD (0x1UL << 5) /**< Extended Data Transfer Width */
AnnaBridge 170:e95d10626187 419 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_SHIFT 5 /**< Shift value for SDIO_EXTDATTRANWD */
AnnaBridge 170:e95d10626187 420 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_MASK 0x20UL /**< Bit mask for SDIO_EXTDATTRANWD */
AnnaBridge 170:e95d10626187 421 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 422 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT 0x00000000UL /**< Mode 8BIT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 423 #define _SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR 0x00000001UL /**< Mode DATXFR for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 424 #define SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT (_SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 425 #define SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT (_SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT << 5) /**< Shifted mode 8BIT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 426 #define SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR (_SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR << 5) /**< Shifted mode DATXFR for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 427 #define SDIO_HOSTCTRL1_CDTSTLVL (0x1UL << 6) /**< Card Detect Test Level */
AnnaBridge 170:e95d10626187 428 #define _SDIO_HOSTCTRL1_CDTSTLVL_SHIFT 6 /**< Shift value for SDIO_CDTSTLVL */
AnnaBridge 170:e95d10626187 429 #define _SDIO_HOSTCTRL1_CDTSTLVL_MASK 0x40UL /**< Bit mask for SDIO_CDTSTLVL */
AnnaBridge 170:e95d10626187 430 #define _SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 431 #define _SDIO_HOSTCTRL1_CDTSTLVL_NOCARD 0x00000000UL /**< Mode NOCARD for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 432 #define _SDIO_HOSTCTRL1_CDTSTLVL_CARDIN 0x00000001UL /**< Mode CARDIN for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 433 #define SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT (_SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 434 #define SDIO_HOSTCTRL1_CDTSTLVL_NOCARD (_SDIO_HOSTCTRL1_CDTSTLVL_NOCARD << 6) /**< Shifted mode NOCARD for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 435 #define SDIO_HOSTCTRL1_CDTSTLVL_CARDIN (_SDIO_HOSTCTRL1_CDTSTLVL_CARDIN << 6) /**< Shifted mode CARDIN for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 436 #define SDIO_HOSTCTRL1_CDSIGDET (0x1UL << 7) /**< Card detetct signal detection */
AnnaBridge 170:e95d10626187 437 #define _SDIO_HOSTCTRL1_CDSIGDET_SHIFT 7 /**< Shift value for SDIO_CDSIGDET */
AnnaBridge 170:e95d10626187 438 #define _SDIO_HOSTCTRL1_CDSIGDET_MASK 0x80UL /**< Bit mask for SDIO_CDSIGDET */
AnnaBridge 170:e95d10626187 439 #define _SDIO_HOSTCTRL1_CDSIGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 440 #define _SDIO_HOSTCTRL1_CDSIGDET_SDCD 0x00000000UL /**< Mode SDCD for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 441 #define _SDIO_HOSTCTRL1_CDSIGDET_TSTLVL 0x00000001UL /**< Mode TSTLVL for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 442 #define SDIO_HOSTCTRL1_CDSIGDET_DEFAULT (_SDIO_HOSTCTRL1_CDSIGDET_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 443 #define SDIO_HOSTCTRL1_CDSIGDET_SDCD (_SDIO_HOSTCTRL1_CDSIGDET_SDCD << 7) /**< Shifted mode SDCD for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 444 #define SDIO_HOSTCTRL1_CDSIGDET_TSTLVL (_SDIO_HOSTCTRL1_CDSIGDET_TSTLVL << 7) /**< Shifted mode TSTLVL for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 445 #define SDIO_HOSTCTRL1_SDBUSPOWER (0x1UL << 8) /**< SD Bus Power */
AnnaBridge 170:e95d10626187 446 #define _SDIO_HOSTCTRL1_SDBUSPOWER_SHIFT 8 /**< Shift value for SDIO_SDBUSPOWER */
AnnaBridge 170:e95d10626187 447 #define _SDIO_HOSTCTRL1_SDBUSPOWER_MASK 0x100UL /**< Bit mask for SDIO_SDBUSPOWER */
AnnaBridge 170:e95d10626187 448 #define _SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 449 #define SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT (_SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 450 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_SHIFT 9 /**< Shift value for SDIO_SDBUSVOLTSEL */
AnnaBridge 170:e95d10626187 451 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_MASK 0xE00UL /**< Bit mask for SDIO_SDBUSVOLTSEL */
AnnaBridge 170:e95d10626187 452 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 453 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V 0x00000005UL /**< Mode 1P8V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 454 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V 0x00000006UL /**< Mode 3P0V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 455 #define _SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V 0x00000007UL /**< Mode 3P3V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 456 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 457 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V << 9) /**< Shifted mode 1P8V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 458 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V << 9) /**< Shifted mode 3P0V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 459 #define SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V (_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V << 9) /**< Shifted mode 3P3V for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 460 #define SDIO_HOSTCTRL1_HRDRST (0x1UL << 12) /**< Hardware reset signal */
AnnaBridge 170:e95d10626187 461 #define _SDIO_HOSTCTRL1_HRDRST_SHIFT 12 /**< Shift value for SDIO_HRDRST */
AnnaBridge 170:e95d10626187 462 #define _SDIO_HOSTCTRL1_HRDRST_MASK 0x1000UL /**< Bit mask for SDIO_HRDRST */
AnnaBridge 170:e95d10626187 463 #define _SDIO_HOSTCTRL1_HRDRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 464 #define SDIO_HOSTCTRL1_HRDRST_DEFAULT (_SDIO_HOSTCTRL1_HRDRST_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 465 #define SDIO_HOSTCTRL1_STOPATBLKGAPREQ (0x1UL << 16) /**< Stop At Block Gap Request */
AnnaBridge 170:e95d10626187 466 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_SHIFT 16 /**< Shift value for SDIO_STOPATBLKGAPREQ */
AnnaBridge 170:e95d10626187 467 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_MASK 0x10000UL /**< Bit mask for SDIO_STOPATBLKGAPREQ */
AnnaBridge 170:e95d10626187 468 #define _SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 469 #define SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT (_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 470 #define SDIO_HOSTCTRL1_CONTINUEREQ (0x1UL << 17) /**< Continue Request */
AnnaBridge 170:e95d10626187 471 #define _SDIO_HOSTCTRL1_CONTINUEREQ_SHIFT 17 /**< Shift value for SDIO_CONTINUEREQ */
AnnaBridge 170:e95d10626187 472 #define _SDIO_HOSTCTRL1_CONTINUEREQ_MASK 0x20000UL /**< Bit mask for SDIO_CONTINUEREQ */
AnnaBridge 170:e95d10626187 473 #define _SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 474 #define SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT (_SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 475 #define SDIO_HOSTCTRL1_RDWAITCTRL (0x1UL << 18) /**< Read Wait Control */
AnnaBridge 170:e95d10626187 476 #define _SDIO_HOSTCTRL1_RDWAITCTRL_SHIFT 18 /**< Shift value for SDIO_RDWAITCTRL */
AnnaBridge 170:e95d10626187 477 #define _SDIO_HOSTCTRL1_RDWAITCTRL_MASK 0x40000UL /**< Bit mask for SDIO_RDWAITCTRL */
AnnaBridge 170:e95d10626187 478 #define _SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 479 #define SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT (_SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 480 #define SDIO_HOSTCTRL1_INTATBLKGAP (0x1UL << 19) /**< Interrupt At Block Gap */
AnnaBridge 170:e95d10626187 481 #define _SDIO_HOSTCTRL1_INTATBLKGAP_SHIFT 19 /**< Shift value for SDIO_INTATBLKGAP */
AnnaBridge 170:e95d10626187 482 #define _SDIO_HOSTCTRL1_INTATBLKGAP_MASK 0x80000UL /**< Bit mask for SDIO_INTATBLKGAP */
AnnaBridge 170:e95d10626187 483 #define _SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 484 #define SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT (_SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 485 #define SDIO_HOSTCTRL1_SPIMODE (0x1UL << 20) /**< SPI Mode Enable */
AnnaBridge 170:e95d10626187 486 #define _SDIO_HOSTCTRL1_SPIMODE_SHIFT 20 /**< Shift value for SDIO_SPIMODE */
AnnaBridge 170:e95d10626187 487 #define _SDIO_HOSTCTRL1_SPIMODE_MASK 0x100000UL /**< Bit mask for SDIO_SPIMODE */
AnnaBridge 170:e95d10626187 488 #define _SDIO_HOSTCTRL1_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 489 #define SDIO_HOSTCTRL1_SPIMODE_DEFAULT (_SDIO_HOSTCTRL1_SPIMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 490 #define SDIO_HOSTCTRL1_BOOTEN (0x1UL << 21) /**< Boot Enable */
AnnaBridge 170:e95d10626187 491 #define _SDIO_HOSTCTRL1_BOOTEN_SHIFT 21 /**< Shift value for SDIO_BOOTEN */
AnnaBridge 170:e95d10626187 492 #define _SDIO_HOSTCTRL1_BOOTEN_MASK 0x200000UL /**< Bit mask for SDIO_BOOTEN */
AnnaBridge 170:e95d10626187 493 #define _SDIO_HOSTCTRL1_BOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 494 #define SDIO_HOSTCTRL1_BOOTEN_DEFAULT (_SDIO_HOSTCTRL1_BOOTEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 495 #define SDIO_HOSTCTRL1_ALTBOOTEN (0x1UL << 22) /**< Alternate Boot Enable */
AnnaBridge 170:e95d10626187 496 #define _SDIO_HOSTCTRL1_ALTBOOTEN_SHIFT 22 /**< Shift value for SDIO_ALTBOOTEN */
AnnaBridge 170:e95d10626187 497 #define _SDIO_HOSTCTRL1_ALTBOOTEN_MASK 0x400000UL /**< Bit mask for SDIO_ALTBOOTEN */
AnnaBridge 170:e95d10626187 498 #define _SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 499 #define SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT (_SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 500 #define SDIO_HOSTCTRL1_BOOTACKCHK (0x1UL << 23) /**< Boot Ack Check */
AnnaBridge 170:e95d10626187 501 #define _SDIO_HOSTCTRL1_BOOTACKCHK_SHIFT 23 /**< Shift value for SDIO_BOOTACKCHK */
AnnaBridge 170:e95d10626187 502 #define _SDIO_HOSTCTRL1_BOOTACKCHK_MASK 0x800000UL /**< Bit mask for SDIO_BOOTACKCHK */
AnnaBridge 170:e95d10626187 503 #define _SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 504 #define SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT (_SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 505 #define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT (0x1UL << 24) /**< Wakeup Event Enable On Card Interrupt */
AnnaBridge 170:e95d10626187 506 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_SHIFT 24 /**< Shift value for SDIO_WKUPEVNTENONCARDINT */
AnnaBridge 170:e95d10626187 507 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_MASK 0x1000000UL /**< Bit mask for SDIO_WKUPEVNTENONCARDINT */
AnnaBridge 170:e95d10626187 508 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 509 #define SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 510 #define SDIO_HOSTCTRL1_WKUPEVNTENONCINS (0x1UL << 25) /**< Wakeup Event Enable On SD Card Insertion */
AnnaBridge 170:e95d10626187 511 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_SHIFT 25 /**< Shift value for SDIO_WKUPEVNTENONCINS */
AnnaBridge 170:e95d10626187 512 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_MASK 0x2000000UL /**< Bit mask for SDIO_WKUPEVNTENONCINS */
AnnaBridge 170:e95d10626187 513 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 514 #define SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 515 #define SDIO_HOSTCTRL1_WKUPEVNTENONCRM (0x1UL << 26) /**< Wakeup Event Enable On SD Card Removal */
AnnaBridge 170:e95d10626187 516 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_SHIFT 26 /**< Shift value for SDIO_WKUPEVNTENONCRM */
AnnaBridge 170:e95d10626187 517 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_MASK 0x4000000UL /**< Bit mask for SDIO_WKUPEVNTENONCRM */
AnnaBridge 170:e95d10626187 518 #define _SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 519 #define SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT (_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_HOSTCTRL1 */
AnnaBridge 170:e95d10626187 520
AnnaBridge 170:e95d10626187 521 /* Bit fields for SDIO CLOCKCTRL */
AnnaBridge 170:e95d10626187 522 #define _SDIO_CLOCKCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 523 #define _SDIO_CLOCKCTRL_MASK 0x070FFFE7UL /**< Mask for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 524 #define SDIO_CLOCKCTRL_INTCLKEN (0x1UL << 0) /**< Internal Clock Enable */
AnnaBridge 170:e95d10626187 525 #define _SDIO_CLOCKCTRL_INTCLKEN_SHIFT 0 /**< Shift value for SDIO_INTCLKEN */
AnnaBridge 170:e95d10626187 526 #define _SDIO_CLOCKCTRL_INTCLKEN_MASK 0x1UL /**< Bit mask for SDIO_INTCLKEN */
AnnaBridge 170:e95d10626187 527 #define _SDIO_CLOCKCTRL_INTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 528 #define SDIO_CLOCKCTRL_INTCLKEN_DEFAULT (_SDIO_CLOCKCTRL_INTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 529 #define SDIO_CLOCKCTRL_INTCLKSTABLE (0x1UL << 1) /**< Internal Clock Stable */
AnnaBridge 170:e95d10626187 530 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_SHIFT 1 /**< Shift value for SDIO_INTCLKSTABLE */
AnnaBridge 170:e95d10626187 531 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_MASK 0x2UL /**< Bit mask for SDIO_INTCLKSTABLE */
AnnaBridge 170:e95d10626187 532 #define _SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 533 #define SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT (_SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 534 #define SDIO_CLOCKCTRL_SDCLKEN (0x1UL << 2) /**< SDIO_CLK Pin Clock Enable */
AnnaBridge 170:e95d10626187 535 #define _SDIO_CLOCKCTRL_SDCLKEN_SHIFT 2 /**< Shift value for SDIO_SDCLKEN */
AnnaBridge 170:e95d10626187 536 #define _SDIO_CLOCKCTRL_SDCLKEN_MASK 0x4UL /**< Bit mask for SDIO_SDCLKEN */
AnnaBridge 170:e95d10626187 537 #define _SDIO_CLOCKCTRL_SDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 538 #define SDIO_CLOCKCTRL_SDCLKEN_DEFAULT (_SDIO_CLOCKCTRL_SDCLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 539 #define SDIO_CLOCKCTRL_CLKGENSEL (0x1UL << 5) /**< Clock Generator Select */
AnnaBridge 170:e95d10626187 540 #define _SDIO_CLOCKCTRL_CLKGENSEL_SHIFT 5 /**< Shift value for SDIO_CLKGENSEL */
AnnaBridge 170:e95d10626187 541 #define _SDIO_CLOCKCTRL_CLKGENSEL_MASK 0x20UL /**< Bit mask for SDIO_CLKGENSEL */
AnnaBridge 170:e95d10626187 542 #define _SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 543 #define SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT (_SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 544 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_SHIFT 6 /**< Shift value for SDIO_UPPSDCLKFRE */
AnnaBridge 170:e95d10626187 545 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_MASK 0xC0UL /**< Bit mask for SDIO_UPPSDCLKFRE */
AnnaBridge 170:e95d10626187 546 #define _SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 547 #define SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT (_SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 548 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_SHIFT 8 /**< Shift value for SDIO_SDCLKFREQSEL */
AnnaBridge 170:e95d10626187 549 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_MASK 0xFF00UL /**< Bit mask for SDIO_SDCLKFREQSEL */
AnnaBridge 170:e95d10626187 550 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 551 #define _SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION 0x00000000UL /**< Mode NODIVISION for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 552 #define SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT (_SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 553 #define SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION (_SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION << 8) /**< Shifted mode NODIVISION for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 554 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_SHIFT 16 /**< Shift value for SDIO_DATTOUTCNTVAL */
AnnaBridge 170:e95d10626187 555 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_MASK 0xF0000UL /**< Bit mask for SDIO_DATTOUTCNTVAL */
AnnaBridge 170:e95d10626187 556 #define _SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 557 #define SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT (_SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 558 #define SDIO_CLOCKCTRL_SFTRSTA (0x1UL << 24) /**< Software Reset for All */
AnnaBridge 170:e95d10626187 559 #define _SDIO_CLOCKCTRL_SFTRSTA_SHIFT 24 /**< Shift value for SDIO_SFTRSTA */
AnnaBridge 170:e95d10626187 560 #define _SDIO_CLOCKCTRL_SFTRSTA_MASK 0x1000000UL /**< Bit mask for SDIO_SFTRSTA */
AnnaBridge 170:e95d10626187 561 #define _SDIO_CLOCKCTRL_SFTRSTA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 562 #define SDIO_CLOCKCTRL_SFTRSTA_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTA_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 563 #define SDIO_CLOCKCTRL_SFTRSTCMD (0x1UL << 25) /**< Software Reset for CMD Line */
AnnaBridge 170:e95d10626187 564 #define _SDIO_CLOCKCTRL_SFTRSTCMD_SHIFT 25 /**< Shift value for SDIO_SFTRSTCMD */
AnnaBridge 170:e95d10626187 565 #define _SDIO_CLOCKCTRL_SFTRSTCMD_MASK 0x2000000UL /**< Bit mask for SDIO_SFTRSTCMD */
AnnaBridge 170:e95d10626187 566 #define _SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 567 #define SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 568 #define SDIO_CLOCKCTRL_SFTRSTDAT (0x1UL << 26) /**< Software Reset for DAT Line */
AnnaBridge 170:e95d10626187 569 #define _SDIO_CLOCKCTRL_SFTRSTDAT_SHIFT 26 /**< Shift value for SDIO_SFTRSTDAT */
AnnaBridge 170:e95d10626187 570 #define _SDIO_CLOCKCTRL_SFTRSTDAT_MASK 0x4000000UL /**< Bit mask for SDIO_SFTRSTDAT */
AnnaBridge 170:e95d10626187 571 #define _SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 572 #define SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT (_SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CLOCKCTRL */
AnnaBridge 170:e95d10626187 573
AnnaBridge 170:e95d10626187 574 /* Bit fields for SDIO IFCR */
AnnaBridge 170:e95d10626187 575 #define _SDIO_IFCR_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFCR */
AnnaBridge 170:e95d10626187 576 #define _SDIO_IFCR_MASK 0x13FFF1FFUL /**< Mask for SDIO_IFCR */
AnnaBridge 170:e95d10626187 577 #define SDIO_IFCR_CMDCOM (0x1UL << 0) /**< Command Complete */
AnnaBridge 170:e95d10626187 578 #define _SDIO_IFCR_CMDCOM_SHIFT 0 /**< Shift value for SDIO_CMDCOM */
AnnaBridge 170:e95d10626187 579 #define _SDIO_IFCR_CMDCOM_MASK 0x1UL /**< Bit mask for SDIO_CMDCOM */
AnnaBridge 170:e95d10626187 580 #define _SDIO_IFCR_CMDCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 581 #define SDIO_IFCR_CMDCOM_DEFAULT (_SDIO_IFCR_CMDCOM_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 582 #define SDIO_IFCR_TRANCOM (0x1UL << 1) /**< Transfer Complete */
AnnaBridge 170:e95d10626187 583 #define _SDIO_IFCR_TRANCOM_SHIFT 1 /**< Shift value for SDIO_TRANCOM */
AnnaBridge 170:e95d10626187 584 #define _SDIO_IFCR_TRANCOM_MASK 0x2UL /**< Bit mask for SDIO_TRANCOM */
AnnaBridge 170:e95d10626187 585 #define _SDIO_IFCR_TRANCOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 586 #define SDIO_IFCR_TRANCOM_DEFAULT (_SDIO_IFCR_TRANCOM_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 587 #define SDIO_IFCR_BLKGAPEVT (0x1UL << 2) /**< Block Gap Event */
AnnaBridge 170:e95d10626187 588 #define _SDIO_IFCR_BLKGAPEVT_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVT */
AnnaBridge 170:e95d10626187 589 #define _SDIO_IFCR_BLKGAPEVT_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVT */
AnnaBridge 170:e95d10626187 590 #define _SDIO_IFCR_BLKGAPEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 591 #define SDIO_IFCR_BLKGAPEVT_DEFAULT (_SDIO_IFCR_BLKGAPEVT_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 592 #define SDIO_IFCR_DMAINT (0x1UL << 3) /**< DMA Interrupt */
AnnaBridge 170:e95d10626187 593 #define _SDIO_IFCR_DMAINT_SHIFT 3 /**< Shift value for SDIO_DMAINT */
AnnaBridge 170:e95d10626187 594 #define _SDIO_IFCR_DMAINT_MASK 0x8UL /**< Bit mask for SDIO_DMAINT */
AnnaBridge 170:e95d10626187 595 #define _SDIO_IFCR_DMAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 596 #define SDIO_IFCR_DMAINT_DEFAULT (_SDIO_IFCR_DMAINT_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 597 #define SDIO_IFCR_BFRWRRDY (0x1UL << 4) /**< Buffer Write Ready */
AnnaBridge 170:e95d10626187 598 #define _SDIO_IFCR_BFRWRRDY_SHIFT 4 /**< Shift value for SDIO_BFRWRRDY */
AnnaBridge 170:e95d10626187 599 #define _SDIO_IFCR_BFRWRRDY_MASK 0x10UL /**< Bit mask for SDIO_BFRWRRDY */
AnnaBridge 170:e95d10626187 600 #define _SDIO_IFCR_BFRWRRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 601 #define SDIO_IFCR_BFRWRRDY_DEFAULT (_SDIO_IFCR_BFRWRRDY_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 602 #define SDIO_IFCR_BFRRDRDY (0x1UL << 5) /**< Buffer Read Ready */
AnnaBridge 170:e95d10626187 603 #define _SDIO_IFCR_BFRRDRDY_SHIFT 5 /**< Shift value for SDIO_BFRRDRDY */
AnnaBridge 170:e95d10626187 604 #define _SDIO_IFCR_BFRRDRDY_MASK 0x20UL /**< Bit mask for SDIO_BFRRDRDY */
AnnaBridge 170:e95d10626187 605 #define _SDIO_IFCR_BFRRDRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 606 #define SDIO_IFCR_BFRRDRDY_DEFAULT (_SDIO_IFCR_BFRRDRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 607 #define SDIO_IFCR_CARDINS (0x1UL << 6) /**< Card Insertion */
AnnaBridge 170:e95d10626187 608 #define _SDIO_IFCR_CARDINS_SHIFT 6 /**< Shift value for SDIO_CARDINS */
AnnaBridge 170:e95d10626187 609 #define _SDIO_IFCR_CARDINS_MASK 0x40UL /**< Bit mask for SDIO_CARDINS */
AnnaBridge 170:e95d10626187 610 #define _SDIO_IFCR_CARDINS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 611 #define SDIO_IFCR_CARDINS_DEFAULT (_SDIO_IFCR_CARDINS_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 612 #define SDIO_IFCR_CARDRM (0x1UL << 7) /**< Card Removal */
AnnaBridge 170:e95d10626187 613 #define _SDIO_IFCR_CARDRM_SHIFT 7 /**< Shift value for SDIO_CARDRM */
AnnaBridge 170:e95d10626187 614 #define _SDIO_IFCR_CARDRM_MASK 0x80UL /**< Bit mask for SDIO_CARDRM */
AnnaBridge 170:e95d10626187 615 #define _SDIO_IFCR_CARDRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 616 #define SDIO_IFCR_CARDRM_DEFAULT (_SDIO_IFCR_CARDRM_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 617 #define SDIO_IFCR_CARDINT (0x1UL << 8) /**< Card Interrupt */
AnnaBridge 170:e95d10626187 618 #define _SDIO_IFCR_CARDINT_SHIFT 8 /**< Shift value for SDIO_CARDINT */
AnnaBridge 170:e95d10626187 619 #define _SDIO_IFCR_CARDINT_MASK 0x100UL /**< Bit mask for SDIO_CARDINT */
AnnaBridge 170:e95d10626187 620 #define _SDIO_IFCR_CARDINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 621 #define SDIO_IFCR_CARDINT_DEFAULT (_SDIO_IFCR_CARDINT_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 622 #define SDIO_IFCR_RETUNINGEVT (0x1UL << 12) /**< Re-Tunning Event */
AnnaBridge 170:e95d10626187 623 #define _SDIO_IFCR_RETUNINGEVT_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVT */
AnnaBridge 170:e95d10626187 624 #define _SDIO_IFCR_RETUNINGEVT_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVT */
AnnaBridge 170:e95d10626187 625 #define _SDIO_IFCR_RETUNINGEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 626 #define SDIO_IFCR_RETUNINGEVT_DEFAULT (_SDIO_IFCR_RETUNINGEVT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 627 #define SDIO_IFCR_BOOTACKRCV (0x1UL << 13) /**< Boot Ack received */
AnnaBridge 170:e95d10626187 628 #define _SDIO_IFCR_BOOTACKRCV_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCV */
AnnaBridge 170:e95d10626187 629 #define _SDIO_IFCR_BOOTACKRCV_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCV */
AnnaBridge 170:e95d10626187 630 #define _SDIO_IFCR_BOOTACKRCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 631 #define SDIO_IFCR_BOOTACKRCV_DEFAULT (_SDIO_IFCR_BOOTACKRCV_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 632 #define SDIO_IFCR_BOOTTERMINATE (0x1UL << 14) /**< Boot terminate interrupt */
AnnaBridge 170:e95d10626187 633 #define _SDIO_IFCR_BOOTTERMINATE_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATE */
AnnaBridge 170:e95d10626187 634 #define _SDIO_IFCR_BOOTTERMINATE_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATE */
AnnaBridge 170:e95d10626187 635 #define _SDIO_IFCR_BOOTTERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 636 #define SDIO_IFCR_BOOTTERMINATE_DEFAULT (_SDIO_IFCR_BOOTTERMINATE_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 637 #define SDIO_IFCR_ERRINT (0x1UL << 15) /**< Error Interrupt */
AnnaBridge 170:e95d10626187 638 #define _SDIO_IFCR_ERRINT_SHIFT 15 /**< Shift value for SDIO_ERRINT */
AnnaBridge 170:e95d10626187 639 #define _SDIO_IFCR_ERRINT_MASK 0x8000UL /**< Bit mask for SDIO_ERRINT */
AnnaBridge 170:e95d10626187 640 #define _SDIO_IFCR_ERRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 641 #define SDIO_IFCR_ERRINT_DEFAULT (_SDIO_IFCR_ERRINT_DEFAULT << 15) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 642 #define SDIO_IFCR_CMDTOUTERR (0x1UL << 16) /**< Command Timeout Error */
AnnaBridge 170:e95d10626187 643 #define _SDIO_IFCR_CMDTOUTERR_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERR */
AnnaBridge 170:e95d10626187 644 #define _SDIO_IFCR_CMDTOUTERR_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERR */
AnnaBridge 170:e95d10626187 645 #define _SDIO_IFCR_CMDTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 646 #define SDIO_IFCR_CMDTOUTERR_DEFAULT (_SDIO_IFCR_CMDTOUTERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 647 #define SDIO_IFCR_CMDCRCERR (0x1UL << 17) /**< CMD CRC Error */
AnnaBridge 170:e95d10626187 648 #define _SDIO_IFCR_CMDCRCERR_SHIFT 17 /**< Shift value for SDIO_CMDCRCERR */
AnnaBridge 170:e95d10626187 649 #define _SDIO_IFCR_CMDCRCERR_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERR */
AnnaBridge 170:e95d10626187 650 #define _SDIO_IFCR_CMDCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 651 #define SDIO_IFCR_CMDCRCERR_DEFAULT (_SDIO_IFCR_CMDCRCERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 652 #define SDIO_IFCR_CMDENDBITERR (0x1UL << 18) /**< Command End Bit Error */
AnnaBridge 170:e95d10626187 653 #define _SDIO_IFCR_CMDENDBITERR_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERR */
AnnaBridge 170:e95d10626187 654 #define _SDIO_IFCR_CMDENDBITERR_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERR */
AnnaBridge 170:e95d10626187 655 #define _SDIO_IFCR_CMDENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 656 #define SDIO_IFCR_CMDENDBITERR_DEFAULT (_SDIO_IFCR_CMDENDBITERR_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 657 #define SDIO_IFCR_CMDINDEXERR (0x1UL << 19) /**< Command Index Error */
AnnaBridge 170:e95d10626187 658 #define _SDIO_IFCR_CMDINDEXERR_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERR */
AnnaBridge 170:e95d10626187 659 #define _SDIO_IFCR_CMDINDEXERR_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERR */
AnnaBridge 170:e95d10626187 660 #define _SDIO_IFCR_CMDINDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 661 #define SDIO_IFCR_CMDINDEXERR_DEFAULT (_SDIO_IFCR_CMDINDEXERR_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 662 #define SDIO_IFCR_DATTOUTERR (0x1UL << 20) /**< Data Time-out Error */
AnnaBridge 170:e95d10626187 663 #define _SDIO_IFCR_DATTOUTERR_SHIFT 20 /**< Shift value for SDIO_DATTOUTERR */
AnnaBridge 170:e95d10626187 664 #define _SDIO_IFCR_DATTOUTERR_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERR */
AnnaBridge 170:e95d10626187 665 #define _SDIO_IFCR_DATTOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 666 #define SDIO_IFCR_DATTOUTERR_DEFAULT (_SDIO_IFCR_DATTOUTERR_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 667 #define SDIO_IFCR_DATCRCERR (0x1UL << 21) /**< Data CRC Error */
AnnaBridge 170:e95d10626187 668 #define _SDIO_IFCR_DATCRCERR_SHIFT 21 /**< Shift value for SDIO_DATCRCERR */
AnnaBridge 170:e95d10626187 669 #define _SDIO_IFCR_DATCRCERR_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERR */
AnnaBridge 170:e95d10626187 670 #define _SDIO_IFCR_DATCRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 671 #define SDIO_IFCR_DATCRCERR_DEFAULT (_SDIO_IFCR_DATCRCERR_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 672 #define SDIO_IFCR_DATENDBITERR (0x1UL << 22) /**< Data End Bit Error */
AnnaBridge 170:e95d10626187 673 #define _SDIO_IFCR_DATENDBITERR_SHIFT 22 /**< Shift value for SDIO_DATENDBITERR */
AnnaBridge 170:e95d10626187 674 #define _SDIO_IFCR_DATENDBITERR_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERR */
AnnaBridge 170:e95d10626187 675 #define _SDIO_IFCR_DATENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 676 #define SDIO_IFCR_DATENDBITERR_DEFAULT (_SDIO_IFCR_DATENDBITERR_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 677 #define SDIO_IFCR_CURRENTLIMITERR (0x1UL << 23) /**< Current Limit Error */
AnnaBridge 170:e95d10626187 678 #define _SDIO_IFCR_CURRENTLIMITERR_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERR */
AnnaBridge 170:e95d10626187 679 #define _SDIO_IFCR_CURRENTLIMITERR_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERR */
AnnaBridge 170:e95d10626187 680 #define _SDIO_IFCR_CURRENTLIMITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 681 #define SDIO_IFCR_CURRENTLIMITERR_DEFAULT (_SDIO_IFCR_CURRENTLIMITERR_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 682 #define SDIO_IFCR_AUTOCMDERR (0x1UL << 24) /**< Auto CMD Error */
AnnaBridge 170:e95d10626187 683 #define _SDIO_IFCR_AUTOCMDERR_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERR */
AnnaBridge 170:e95d10626187 684 #define _SDIO_IFCR_AUTOCMDERR_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERR */
AnnaBridge 170:e95d10626187 685 #define _SDIO_IFCR_AUTOCMDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 686 #define SDIO_IFCR_AUTOCMDERR_DEFAULT (_SDIO_IFCR_AUTOCMDERR_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 687 #define SDIO_IFCR_ADMAERR (0x1UL << 25) /**< ADMA Error */
AnnaBridge 170:e95d10626187 688 #define _SDIO_IFCR_ADMAERR_SHIFT 25 /**< Shift value for SDIO_ADMAERR */
AnnaBridge 170:e95d10626187 689 #define _SDIO_IFCR_ADMAERR_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERR */
AnnaBridge 170:e95d10626187 690 #define _SDIO_IFCR_ADMAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 691 #define SDIO_IFCR_ADMAERR_DEFAULT (_SDIO_IFCR_ADMAERR_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 692 #define SDIO_IFCR_TARGETRESP (0x1UL << 28) /**< Specific error STAT */
AnnaBridge 170:e95d10626187 693 #define _SDIO_IFCR_TARGETRESP_SHIFT 28 /**< Shift value for SDIO_TARGETRESP */
AnnaBridge 170:e95d10626187 694 #define _SDIO_IFCR_TARGETRESP_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESP */
AnnaBridge 170:e95d10626187 695 #define _SDIO_IFCR_TARGETRESP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 696 #define SDIO_IFCR_TARGETRESP_DEFAULT (_SDIO_IFCR_TARGETRESP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFCR */
AnnaBridge 170:e95d10626187 697
AnnaBridge 170:e95d10626187 698 /* Bit fields for SDIO IFENC */
AnnaBridge 170:e95d10626187 699 #define _SDIO_IFENC_RESETVALUE 0x00000000UL /**< Default value for SDIO_IFENC */
AnnaBridge 170:e95d10626187 700 #define _SDIO_IFENC_MASK 0x17FF71FFUL /**< Mask for SDIO_IFENC */
AnnaBridge 170:e95d10626187 701 #define SDIO_IFENC_CMDCOMEN (0x1UL << 0) /**< Command Complete Signal Enable */
AnnaBridge 170:e95d10626187 702 #define _SDIO_IFENC_CMDCOMEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMEN */
AnnaBridge 170:e95d10626187 703 #define _SDIO_IFENC_CMDCOMEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMEN */
AnnaBridge 170:e95d10626187 704 #define _SDIO_IFENC_CMDCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 705 #define SDIO_IFENC_CMDCOMEN_DEFAULT (_SDIO_IFENC_CMDCOMEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 706 #define SDIO_IFENC_TRANCOMEN (0x1UL << 1) /**< Transfer Complete Signal Enable */
AnnaBridge 170:e95d10626187 707 #define _SDIO_IFENC_TRANCOMEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMEN */
AnnaBridge 170:e95d10626187 708 #define _SDIO_IFENC_TRANCOMEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMEN */
AnnaBridge 170:e95d10626187 709 #define _SDIO_IFENC_TRANCOMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 710 #define SDIO_IFENC_TRANCOMEN_DEFAULT (_SDIO_IFENC_TRANCOMEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 711 #define SDIO_IFENC_BLKGAPEVTEN (0x1UL << 2) /**< Block Gap Event Signal Enable */
AnnaBridge 170:e95d10626187 712 #define _SDIO_IFENC_BLKGAPEVTEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTEN */
AnnaBridge 170:e95d10626187 713 #define _SDIO_IFENC_BLKGAPEVTEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTEN */
AnnaBridge 170:e95d10626187 714 #define _SDIO_IFENC_BLKGAPEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 715 #define SDIO_IFENC_BLKGAPEVTEN_DEFAULT (_SDIO_IFENC_BLKGAPEVTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 716 #define SDIO_IFENC_DMAINTEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 717 #define _SDIO_IFENC_DMAINTEN_SHIFT 3 /**< Shift value for SDIO_DMAINTEN */
AnnaBridge 170:e95d10626187 718 #define _SDIO_IFENC_DMAINTEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTEN */
AnnaBridge 170:e95d10626187 719 #define _SDIO_IFENC_DMAINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 720 #define SDIO_IFENC_DMAINTEN_DEFAULT (_SDIO_IFENC_DMAINTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 721 #define SDIO_IFENC_BUFWRRDYEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */
AnnaBridge 170:e95d10626187 722 #define _SDIO_IFENC_BUFWRRDYEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYEN */
AnnaBridge 170:e95d10626187 723 #define _SDIO_IFENC_BUFWRRDYEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYEN */
AnnaBridge 170:e95d10626187 724 #define _SDIO_IFENC_BUFWRRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 725 #define SDIO_IFENC_BUFWRRDYEN_DEFAULT (_SDIO_IFENC_BUFWRRDYEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 726 #define SDIO_IFENC_BUFRDRDYEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */
AnnaBridge 170:e95d10626187 727 #define _SDIO_IFENC_BUFRDRDYEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYEN */
AnnaBridge 170:e95d10626187 728 #define _SDIO_IFENC_BUFRDRDYEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYEN */
AnnaBridge 170:e95d10626187 729 #define _SDIO_IFENC_BUFRDRDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 730 #define SDIO_IFENC_BUFRDRDYEN_DEFAULT (_SDIO_IFENC_BUFRDRDYEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 731 #define SDIO_IFENC_CARDINSEN (0x1UL << 6) /**< Card Insertion Signal Enable */
AnnaBridge 170:e95d10626187 732 #define _SDIO_IFENC_CARDINSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSEN */
AnnaBridge 170:e95d10626187 733 #define _SDIO_IFENC_CARDINSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSEN */
AnnaBridge 170:e95d10626187 734 #define _SDIO_IFENC_CARDINSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 735 #define SDIO_IFENC_CARDINSEN_DEFAULT (_SDIO_IFENC_CARDINSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 736 #define SDIO_IFENC_CARDRMEN (0x1UL << 7) /**< Card Removal Signal Enable */
AnnaBridge 170:e95d10626187 737 #define _SDIO_IFENC_CARDRMEN_SHIFT 7 /**< Shift value for SDIO_CARDRMEN */
AnnaBridge 170:e95d10626187 738 #define _SDIO_IFENC_CARDRMEN_MASK 0x80UL /**< Bit mask for SDIO_CARDRMEN */
AnnaBridge 170:e95d10626187 739 #define _SDIO_IFENC_CARDRMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 740 #define SDIO_IFENC_CARDRMEN_DEFAULT (_SDIO_IFENC_CARDRMEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 741 #define SDIO_IFENC_CARDINTEN (0x1UL << 8) /**< Card Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 742 #define _SDIO_IFENC_CARDINTEN_SHIFT 8 /**< Shift value for SDIO_CARDINTEN */
AnnaBridge 170:e95d10626187 743 #define _SDIO_IFENC_CARDINTEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTEN */
AnnaBridge 170:e95d10626187 744 #define _SDIO_IFENC_CARDINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 745 #define SDIO_IFENC_CARDINTEN_DEFAULT (_SDIO_IFENC_CARDINTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 746 #define SDIO_IFENC_RETUNINGEVTEN (0x1UL << 12) /**< Re-Tunning Event Signal Enable */
AnnaBridge 170:e95d10626187 747 #define _SDIO_IFENC_RETUNINGEVTEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTEN */
AnnaBridge 170:e95d10626187 748 #define _SDIO_IFENC_RETUNINGEVTEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTEN */
AnnaBridge 170:e95d10626187 749 #define _SDIO_IFENC_RETUNINGEVTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 750 #define SDIO_IFENC_RETUNINGEVTEN_DEFAULT (_SDIO_IFENC_RETUNINGEVTEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 751 #define SDIO_IFENC_BOOTACKRCVEN (0x1UL << 13) /**< Boot Ack Received Signal Enable */
AnnaBridge 170:e95d10626187 752 #define _SDIO_IFENC_BOOTACKRCVEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVEN */
AnnaBridge 170:e95d10626187 753 #define _SDIO_IFENC_BOOTACKRCVEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVEN */
AnnaBridge 170:e95d10626187 754 #define _SDIO_IFENC_BOOTACKRCVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 755 #define SDIO_IFENC_BOOTACKRCVEN_DEFAULT (_SDIO_IFENC_BOOTACKRCVEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 756 #define SDIO_IFENC_BOOTTERMINATEEN (0x1UL << 14) /**< Boot terminate Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 757 #define _SDIO_IFENC_BOOTTERMINATEEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATEEN */
AnnaBridge 170:e95d10626187 758 #define _SDIO_IFENC_BOOTTERMINATEEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATEEN */
AnnaBridge 170:e95d10626187 759 #define _SDIO_IFENC_BOOTTERMINATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 760 #define SDIO_IFENC_BOOTTERMINATEEN_DEFAULT (_SDIO_IFENC_BOOTTERMINATEEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 761 #define SDIO_IFENC_CMDTOUTERREN (0x1UL << 16) /**< Command Time-out Error Status Enable */
AnnaBridge 170:e95d10626187 762 #define _SDIO_IFENC_CMDTOUTERREN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERREN */
AnnaBridge 170:e95d10626187 763 #define _SDIO_IFENC_CMDTOUTERREN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERREN */
AnnaBridge 170:e95d10626187 764 #define _SDIO_IFENC_CMDTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 765 #define SDIO_IFENC_CMDTOUTERREN_DEFAULT (_SDIO_IFENC_CMDTOUTERREN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 766 #define SDIO_IFENC_CMDCRCERREN (0x1UL << 17) /**< Command CRC Error Status Enable */
AnnaBridge 170:e95d10626187 767 #define _SDIO_IFENC_CMDCRCERREN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERREN */
AnnaBridge 170:e95d10626187 768 #define _SDIO_IFENC_CMDCRCERREN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERREN */
AnnaBridge 170:e95d10626187 769 #define _SDIO_IFENC_CMDCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 770 #define SDIO_IFENC_CMDCRCERREN_DEFAULT (_SDIO_IFENC_CMDCRCERREN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 771 #define SDIO_IFENC_CMDENDBITERREN (0x1UL << 18) /**< Command End Bit Error Status Enable */
AnnaBridge 170:e95d10626187 772 #define _SDIO_IFENC_CMDENDBITERREN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERREN */
AnnaBridge 170:e95d10626187 773 #define _SDIO_IFENC_CMDENDBITERREN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERREN */
AnnaBridge 170:e95d10626187 774 #define _SDIO_IFENC_CMDENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 775 #define SDIO_IFENC_CMDENDBITERREN_DEFAULT (_SDIO_IFENC_CMDENDBITERREN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 776 #define SDIO_IFENC_CMDINDEXERREN (0x1UL << 19) /**< Command Index Error Status Enable */
AnnaBridge 170:e95d10626187 777 #define _SDIO_IFENC_CMDINDEXERREN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERREN */
AnnaBridge 170:e95d10626187 778 #define _SDIO_IFENC_CMDINDEXERREN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERREN */
AnnaBridge 170:e95d10626187 779 #define _SDIO_IFENC_CMDINDEXERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 780 #define SDIO_IFENC_CMDINDEXERREN_DEFAULT (_SDIO_IFENC_CMDINDEXERREN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 781 #define SDIO_IFENC_DATTOUTERREN (0x1UL << 20) /**< Data Timeout Error Status Enable */
AnnaBridge 170:e95d10626187 782 #define _SDIO_IFENC_DATTOUTERREN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERREN */
AnnaBridge 170:e95d10626187 783 #define _SDIO_IFENC_DATTOUTERREN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERREN */
AnnaBridge 170:e95d10626187 784 #define _SDIO_IFENC_DATTOUTERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 785 #define SDIO_IFENC_DATTOUTERREN_DEFAULT (_SDIO_IFENC_DATTOUTERREN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 786 #define SDIO_IFENC_DATCRCERREN (0x1UL << 21) /**< Data CRC Error Status Enable */
AnnaBridge 170:e95d10626187 787 #define _SDIO_IFENC_DATCRCERREN_SHIFT 21 /**< Shift value for SDIO_DATCRCERREN */
AnnaBridge 170:e95d10626187 788 #define _SDIO_IFENC_DATCRCERREN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERREN */
AnnaBridge 170:e95d10626187 789 #define _SDIO_IFENC_DATCRCERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 790 #define SDIO_IFENC_DATCRCERREN_DEFAULT (_SDIO_IFENC_DATCRCERREN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 791 #define SDIO_IFENC_DATENDBITERREN (0x1UL << 22) /**< Data End Bit Error Status Enable */
AnnaBridge 170:e95d10626187 792 #define _SDIO_IFENC_DATENDBITERREN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERREN */
AnnaBridge 170:e95d10626187 793 #define _SDIO_IFENC_DATENDBITERREN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERREN */
AnnaBridge 170:e95d10626187 794 #define _SDIO_IFENC_DATENDBITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 795 #define SDIO_IFENC_DATENDBITERREN_DEFAULT (_SDIO_IFENC_DATENDBITERREN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 796 #define SDIO_IFENC_CURRENTLIMITERREN (0x1UL << 23) /**< Current Limit Error Status Enable */
AnnaBridge 170:e95d10626187 797 #define _SDIO_IFENC_CURRENTLIMITERREN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERREN */
AnnaBridge 170:e95d10626187 798 #define _SDIO_IFENC_CURRENTLIMITERREN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERREN */
AnnaBridge 170:e95d10626187 799 #define _SDIO_IFENC_CURRENTLIMITERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 800 #define SDIO_IFENC_CURRENTLIMITERREN_DEFAULT (_SDIO_IFENC_CURRENTLIMITERREN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 801 #define SDIO_IFENC_AUTOCMDERREN (0x1UL << 24) /**< Auto CMD12 Error Status Enable */
AnnaBridge 170:e95d10626187 802 #define _SDIO_IFENC_AUTOCMDERREN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERREN */
AnnaBridge 170:e95d10626187 803 #define _SDIO_IFENC_AUTOCMDERREN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERREN */
AnnaBridge 170:e95d10626187 804 #define _SDIO_IFENC_AUTOCMDERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 805 #define SDIO_IFENC_AUTOCMDERREN_DEFAULT (_SDIO_IFENC_AUTOCMDERREN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 806 #define SDIO_IFENC_ADMAERREN (0x1UL << 25) /**< ADMA Error Status Enable */
AnnaBridge 170:e95d10626187 807 #define _SDIO_IFENC_ADMAERREN_SHIFT 25 /**< Shift value for SDIO_ADMAERREN */
AnnaBridge 170:e95d10626187 808 #define _SDIO_IFENC_ADMAERREN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERREN */
AnnaBridge 170:e95d10626187 809 #define _SDIO_IFENC_ADMAERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 810 #define SDIO_IFENC_ADMAERREN_DEFAULT (_SDIO_IFENC_ADMAERREN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 811 #define SDIO_IFENC_TUNINGERREN (0x1UL << 26) /**< Tuning Error Status Enable */
AnnaBridge 170:e95d10626187 812 #define _SDIO_IFENC_TUNINGERREN_SHIFT 26 /**< Shift value for SDIO_TUNINGERREN */
AnnaBridge 170:e95d10626187 813 #define _SDIO_IFENC_TUNINGERREN_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERREN */
AnnaBridge 170:e95d10626187 814 #define _SDIO_IFENC_TUNINGERREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 815 #define SDIO_IFENC_TUNINGERREN_DEFAULT (_SDIO_IFENC_TUNINGERREN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 816 #define SDIO_IFENC_TARGETRESPEN (0x1UL << 28) /**< Target Response/Host Error Status Enable */
AnnaBridge 170:e95d10626187 817 #define _SDIO_IFENC_TARGETRESPEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPEN */
AnnaBridge 170:e95d10626187 818 #define _SDIO_IFENC_TARGETRESPEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPEN */
AnnaBridge 170:e95d10626187 819 #define _SDIO_IFENC_TARGETRESPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 820 #define SDIO_IFENC_TARGETRESPEN_DEFAULT (_SDIO_IFENC_TARGETRESPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IFENC */
AnnaBridge 170:e95d10626187 821
AnnaBridge 170:e95d10626187 822 /* Bit fields for SDIO IEN */
AnnaBridge 170:e95d10626187 823 #define _SDIO_IEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_IEN */
AnnaBridge 170:e95d10626187 824 #define _SDIO_IEN_MASK 0x17FF71FFUL /**< Mask for SDIO_IEN */
AnnaBridge 170:e95d10626187 825 #define SDIO_IEN_CMDCOMSEN (0x1UL << 0) /**< Command complete Signal Enable */
AnnaBridge 170:e95d10626187 826 #define _SDIO_IEN_CMDCOMSEN_SHIFT 0 /**< Shift value for SDIO_CMDCOMSEN */
AnnaBridge 170:e95d10626187 827 #define _SDIO_IEN_CMDCOMSEN_MASK 0x1UL /**< Bit mask for SDIO_CMDCOMSEN */
AnnaBridge 170:e95d10626187 828 #define _SDIO_IEN_CMDCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 829 #define SDIO_IEN_CMDCOMSEN_DEFAULT (_SDIO_IEN_CMDCOMSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 830 #define SDIO_IEN_TRANCOMSEN (0x1UL << 1) /**< Transfer complete Signal Enable */
AnnaBridge 170:e95d10626187 831 #define _SDIO_IEN_TRANCOMSEN_SHIFT 1 /**< Shift value for SDIO_TRANCOMSEN */
AnnaBridge 170:e95d10626187 832 #define _SDIO_IEN_TRANCOMSEN_MASK 0x2UL /**< Bit mask for SDIO_TRANCOMSEN */
AnnaBridge 170:e95d10626187 833 #define _SDIO_IEN_TRANCOMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 834 #define SDIO_IEN_TRANCOMSEN_DEFAULT (_SDIO_IEN_TRANCOMSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 835 #define SDIO_IEN_BLKGAPEVTSEN (0x1UL << 2) /**< Block Gap Event Signal Enable */
AnnaBridge 170:e95d10626187 836 #define _SDIO_IEN_BLKGAPEVTSEN_SHIFT 2 /**< Shift value for SDIO_BLKGAPEVTSEN */
AnnaBridge 170:e95d10626187 837 #define _SDIO_IEN_BLKGAPEVTSEN_MASK 0x4UL /**< Bit mask for SDIO_BLKGAPEVTSEN */
AnnaBridge 170:e95d10626187 838 #define _SDIO_IEN_BLKGAPEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 839 #define SDIO_IEN_BLKGAPEVTSEN_DEFAULT (_SDIO_IEN_BLKGAPEVTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 840 #define SDIO_IEN_DMAINTSEN (0x1UL << 3) /**< DMA Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 841 #define _SDIO_IEN_DMAINTSEN_SHIFT 3 /**< Shift value for SDIO_DMAINTSEN */
AnnaBridge 170:e95d10626187 842 #define _SDIO_IEN_DMAINTSEN_MASK 0x8UL /**< Bit mask for SDIO_DMAINTSEN */
AnnaBridge 170:e95d10626187 843 #define _SDIO_IEN_DMAINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 844 #define SDIO_IEN_DMAINTSEN_DEFAULT (_SDIO_IEN_DMAINTSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 845 #define SDIO_IEN_BUFWRRDYSEN (0x1UL << 4) /**< Buffer Write Ready Signal Enable */
AnnaBridge 170:e95d10626187 846 #define _SDIO_IEN_BUFWRRDYSEN_SHIFT 4 /**< Shift value for SDIO_BUFWRRDYSEN */
AnnaBridge 170:e95d10626187 847 #define _SDIO_IEN_BUFWRRDYSEN_MASK 0x10UL /**< Bit mask for SDIO_BUFWRRDYSEN */
AnnaBridge 170:e95d10626187 848 #define _SDIO_IEN_BUFWRRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 849 #define SDIO_IEN_BUFWRRDYSEN_DEFAULT (_SDIO_IEN_BUFWRRDYSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 850 #define SDIO_IEN_BUFRDRDYSEN (0x1UL << 5) /**< Buffer Read Ready Signal Enable */
AnnaBridge 170:e95d10626187 851 #define _SDIO_IEN_BUFRDRDYSEN_SHIFT 5 /**< Shift value for SDIO_BUFRDRDYSEN */
AnnaBridge 170:e95d10626187 852 #define _SDIO_IEN_BUFRDRDYSEN_MASK 0x20UL /**< Bit mask for SDIO_BUFRDRDYSEN */
AnnaBridge 170:e95d10626187 853 #define _SDIO_IEN_BUFRDRDYSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 854 #define SDIO_IEN_BUFRDRDYSEN_DEFAULT (_SDIO_IEN_BUFRDRDYSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 855 #define SDIO_IEN_CARDINSSEN (0x1UL << 6) /**< Card Insertion Signal Enable */
AnnaBridge 170:e95d10626187 856 #define _SDIO_IEN_CARDINSSEN_SHIFT 6 /**< Shift value for SDIO_CARDINSSEN */
AnnaBridge 170:e95d10626187 857 #define _SDIO_IEN_CARDINSSEN_MASK 0x40UL /**< Bit mask for SDIO_CARDINSSEN */
AnnaBridge 170:e95d10626187 858 #define _SDIO_IEN_CARDINSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 859 #define SDIO_IEN_CARDINSSEN_DEFAULT (_SDIO_IEN_CARDINSSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 860 #define SDIO_IEN_CARDREMSEN (0x1UL << 7) /**< Card Removal Signal Enable */
AnnaBridge 170:e95d10626187 861 #define _SDIO_IEN_CARDREMSEN_SHIFT 7 /**< Shift value for SDIO_CARDREMSEN */
AnnaBridge 170:e95d10626187 862 #define _SDIO_IEN_CARDREMSEN_MASK 0x80UL /**< Bit mask for SDIO_CARDREMSEN */
AnnaBridge 170:e95d10626187 863 #define _SDIO_IEN_CARDREMSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 864 #define SDIO_IEN_CARDREMSEN_DEFAULT (_SDIO_IEN_CARDREMSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 865 #define SDIO_IEN_CARDINTSEN (0x1UL << 8) /**< Card Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 866 #define _SDIO_IEN_CARDINTSEN_SHIFT 8 /**< Shift value for SDIO_CARDINTSEN */
AnnaBridge 170:e95d10626187 867 #define _SDIO_IEN_CARDINTSEN_MASK 0x100UL /**< Bit mask for SDIO_CARDINTSEN */
AnnaBridge 170:e95d10626187 868 #define _SDIO_IEN_CARDINTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 869 #define SDIO_IEN_CARDINTSEN_DEFAULT (_SDIO_IEN_CARDINTSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 870 #define SDIO_IEN_RETUNINGEVTSEN (0x1UL << 12) /**< Re-Tuning Event Signal Enable */
AnnaBridge 170:e95d10626187 871 #define _SDIO_IEN_RETUNINGEVTSEN_SHIFT 12 /**< Shift value for SDIO_RETUNINGEVTSEN */
AnnaBridge 170:e95d10626187 872 #define _SDIO_IEN_RETUNINGEVTSEN_MASK 0x1000UL /**< Bit mask for SDIO_RETUNINGEVTSEN */
AnnaBridge 170:e95d10626187 873 #define _SDIO_IEN_RETUNINGEVTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 874 #define SDIO_IEN_RETUNINGEVTSEN_DEFAULT (_SDIO_IEN_RETUNINGEVTSEN_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 875 #define SDIO_IEN_BOOTACKRCVSEN (0x1UL << 13) /**< Boot Ack received Signal Enable */
AnnaBridge 170:e95d10626187 876 #define _SDIO_IEN_BOOTACKRCVSEN_SHIFT 13 /**< Shift value for SDIO_BOOTACKRCVSEN */
AnnaBridge 170:e95d10626187 877 #define _SDIO_IEN_BOOTACKRCVSEN_MASK 0x2000UL /**< Bit mask for SDIO_BOOTACKRCVSEN */
AnnaBridge 170:e95d10626187 878 #define _SDIO_IEN_BOOTACKRCVSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 879 #define SDIO_IEN_BOOTACKRCVSEN_DEFAULT (_SDIO_IEN_BOOTACKRCVSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 880 #define SDIO_IEN_BOOTTERMINATESEN (0x1UL << 14) /**< Boot Terminate Interrupt Signal Enable */
AnnaBridge 170:e95d10626187 881 #define _SDIO_IEN_BOOTTERMINATESEN_SHIFT 14 /**< Shift value for SDIO_BOOTTERMINATESEN */
AnnaBridge 170:e95d10626187 882 #define _SDIO_IEN_BOOTTERMINATESEN_MASK 0x4000UL /**< Bit mask for SDIO_BOOTTERMINATESEN */
AnnaBridge 170:e95d10626187 883 #define _SDIO_IEN_BOOTTERMINATESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 884 #define SDIO_IEN_BOOTTERMINATESEN_DEFAULT (_SDIO_IEN_BOOTTERMINATESEN_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 885 #define SDIO_IEN_CMDTOUTERRSEN (0x1UL << 16) /**< Command Timeout Error Signal Enable */
AnnaBridge 170:e95d10626187 886 #define _SDIO_IEN_CMDTOUTERRSEN_SHIFT 16 /**< Shift value for SDIO_CMDTOUTERRSEN */
AnnaBridge 170:e95d10626187 887 #define _SDIO_IEN_CMDTOUTERRSEN_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOUTERRSEN */
AnnaBridge 170:e95d10626187 888 #define _SDIO_IEN_CMDTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 889 #define SDIO_IEN_CMDTOUTERRSEN_DEFAULT (_SDIO_IEN_CMDTOUTERRSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 890 #define SDIO_IEN_CMDCRCERRSEN (0x1UL << 17) /**< Command CRC Error Signal Enable */
AnnaBridge 170:e95d10626187 891 #define _SDIO_IEN_CMDCRCERRSEN_SHIFT 17 /**< Shift value for SDIO_CMDCRCERRSEN */
AnnaBridge 170:e95d10626187 892 #define _SDIO_IEN_CMDCRCERRSEN_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCERRSEN */
AnnaBridge 170:e95d10626187 893 #define _SDIO_IEN_CMDCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 894 #define SDIO_IEN_CMDCRCERRSEN_DEFAULT (_SDIO_IEN_CMDCRCERRSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 895 #define SDIO_IEN_CMDENDBITERRSEN (0x1UL << 18) /**< Command End Bit Error Signal Enable */
AnnaBridge 170:e95d10626187 896 #define _SDIO_IEN_CMDENDBITERRSEN_SHIFT 18 /**< Shift value for SDIO_CMDENDBITERRSEN */
AnnaBridge 170:e95d10626187 897 #define _SDIO_IEN_CMDENDBITERRSEN_MASK 0x40000UL /**< Bit mask for SDIO_CMDENDBITERRSEN */
AnnaBridge 170:e95d10626187 898 #define _SDIO_IEN_CMDENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 899 #define SDIO_IEN_CMDENDBITERRSEN_DEFAULT (_SDIO_IEN_CMDENDBITERRSEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 900 #define SDIO_IEN_CMDINDEXERRSEN (0x1UL << 19) /**< Command Index Error Signal Enable */
AnnaBridge 170:e95d10626187 901 #define _SDIO_IEN_CMDINDEXERRSEN_SHIFT 19 /**< Shift value for SDIO_CMDINDEXERRSEN */
AnnaBridge 170:e95d10626187 902 #define _SDIO_IEN_CMDINDEXERRSEN_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDEXERRSEN */
AnnaBridge 170:e95d10626187 903 #define _SDIO_IEN_CMDINDEXERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 904 #define SDIO_IEN_CMDINDEXERRSEN_DEFAULT (_SDIO_IEN_CMDINDEXERRSEN_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 905 #define SDIO_IEN_DATTOUTERRSEN (0x1UL << 20) /**< Data Timeout Error Signal Enable */
AnnaBridge 170:e95d10626187 906 #define _SDIO_IEN_DATTOUTERRSEN_SHIFT 20 /**< Shift value for SDIO_DATTOUTERRSEN */
AnnaBridge 170:e95d10626187 907 #define _SDIO_IEN_DATTOUTERRSEN_MASK 0x100000UL /**< Bit mask for SDIO_DATTOUTERRSEN */
AnnaBridge 170:e95d10626187 908 #define _SDIO_IEN_DATTOUTERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 909 #define SDIO_IEN_DATTOUTERRSEN_DEFAULT (_SDIO_IEN_DATTOUTERRSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 910 #define SDIO_IEN_DATCRCERRSEN (0x1UL << 21) /**< Data CRC Error Signal Enable */
AnnaBridge 170:e95d10626187 911 #define _SDIO_IEN_DATCRCERRSEN_SHIFT 21 /**< Shift value for SDIO_DATCRCERRSEN */
AnnaBridge 170:e95d10626187 912 #define _SDIO_IEN_DATCRCERRSEN_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCERRSEN */
AnnaBridge 170:e95d10626187 913 #define _SDIO_IEN_DATCRCERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 914 #define SDIO_IEN_DATCRCERRSEN_DEFAULT (_SDIO_IEN_DATCRCERRSEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 915 #define SDIO_IEN_DATENDBITERRSEN (0x1UL << 22) /**< Data End Bit Error Signal Enable */
AnnaBridge 170:e95d10626187 916 #define _SDIO_IEN_DATENDBITERRSEN_SHIFT 22 /**< Shift value for SDIO_DATENDBITERRSEN */
AnnaBridge 170:e95d10626187 917 #define _SDIO_IEN_DATENDBITERRSEN_MASK 0x400000UL /**< Bit mask for SDIO_DATENDBITERRSEN */
AnnaBridge 170:e95d10626187 918 #define _SDIO_IEN_DATENDBITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 919 #define SDIO_IEN_DATENDBITERRSEN_DEFAULT (_SDIO_IEN_DATENDBITERRSEN_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 920 #define SDIO_IEN_CURRENTLIMITERRSEN (0x1UL << 23) /**< Current Limit Error Signal Enable */
AnnaBridge 170:e95d10626187 921 #define _SDIO_IEN_CURRENTLIMITERRSEN_SHIFT 23 /**< Shift value for SDIO_CURRENTLIMITERRSEN */
AnnaBridge 170:e95d10626187 922 #define _SDIO_IEN_CURRENTLIMITERRSEN_MASK 0x800000UL /**< Bit mask for SDIO_CURRENTLIMITERRSEN */
AnnaBridge 170:e95d10626187 923 #define _SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 924 #define SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT (_SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 925 #define SDIO_IEN_AUTOCMDERRSEN (0x1UL << 24) /**< Auto CMD12 Error Signal Enable */
AnnaBridge 170:e95d10626187 926 #define _SDIO_IEN_AUTOCMDERRSEN_SHIFT 24 /**< Shift value for SDIO_AUTOCMDERRSEN */
AnnaBridge 170:e95d10626187 927 #define _SDIO_IEN_AUTOCMDERRSEN_MASK 0x1000000UL /**< Bit mask for SDIO_AUTOCMDERRSEN */
AnnaBridge 170:e95d10626187 928 #define _SDIO_IEN_AUTOCMDERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 929 #define SDIO_IEN_AUTOCMDERRSEN_DEFAULT (_SDIO_IEN_AUTOCMDERRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 930 #define SDIO_IEN_ADMAERRSEN (0x1UL << 25) /**< ADMA Error Signal Enable */
AnnaBridge 170:e95d10626187 931 #define _SDIO_IEN_ADMAERRSEN_SHIFT 25 /**< Shift value for SDIO_ADMAERRSEN */
AnnaBridge 170:e95d10626187 932 #define _SDIO_IEN_ADMAERRSEN_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAERRSEN */
AnnaBridge 170:e95d10626187 933 #define _SDIO_IEN_ADMAERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 934 #define SDIO_IEN_ADMAERRSEN_DEFAULT (_SDIO_IEN_ADMAERRSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 935 #define SDIO_IEN_TUNINGERRSIGNALENABLE (0x1UL << 26) /**< Tuning Error Signal Enable */
AnnaBridge 170:e95d10626187 936 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_SHIFT 26 /**< Shift value for SDIO_TUNINGERRSIGNALENABLE */
AnnaBridge 170:e95d10626187 937 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGERRSIGNALENABLE */
AnnaBridge 170:e95d10626187 938 #define _SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 939 #define SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT (_SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 940 #define SDIO_IEN_TARGETRESPERRSEN (0x1UL << 28) /**< Target Response Error Signal Enable */
AnnaBridge 170:e95d10626187 941 #define _SDIO_IEN_TARGETRESPERRSEN_SHIFT 28 /**< Shift value for SDIO_TARGETRESPERRSEN */
AnnaBridge 170:e95d10626187 942 #define _SDIO_IEN_TARGETRESPERRSEN_MASK 0x10000000UL /**< Bit mask for SDIO_TARGETRESPERRSEN */
AnnaBridge 170:e95d10626187 943 #define _SDIO_IEN_TARGETRESPERRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 944 #define SDIO_IEN_TARGETRESPERRSEN_DEFAULT (_SDIO_IEN_TARGETRESPERRSEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_IEN */
AnnaBridge 170:e95d10626187 945
AnnaBridge 170:e95d10626187 946 /* Bit fields for SDIO AC12ERRSTAT */
AnnaBridge 170:e95d10626187 947 #define _SDIO_AC12ERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 948 #define _SDIO_AC12ERRSTAT_MASK 0xC0FF009FUL /**< Mask for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 949 #define SDIO_AC12ERRSTAT_AC12NOTEXE (0x1UL << 0) /**< Auto CMD12 not executed */
AnnaBridge 170:e95d10626187 950 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_SHIFT 0 /**< Shift value for SDIO_AC12NOTEXE */
AnnaBridge 170:e95d10626187 951 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_MASK 0x1UL /**< Bit mask for SDIO_AC12NOTEXE */
AnnaBridge 170:e95d10626187 952 #define _SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 953 #define SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT (_SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 954 #define SDIO_AC12ERRSTAT_AC12TOE (0x1UL << 1) /**< Auto CMD12 Timeout Error */
AnnaBridge 170:e95d10626187 955 #define _SDIO_AC12ERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */
AnnaBridge 170:e95d10626187 956 #define _SDIO_AC12ERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */
AnnaBridge 170:e95d10626187 957 #define _SDIO_AC12ERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 958 #define SDIO_AC12ERRSTAT_AC12TOE_DEFAULT (_SDIO_AC12ERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 959 #define SDIO_AC12ERRSTAT_AC12CRCERR (0x1UL << 2) /**< Auto CMD CRC Error */
AnnaBridge 170:e95d10626187 960 #define _SDIO_AC12ERRSTAT_AC12CRCERR_SHIFT 2 /**< Shift value for SDIO_AC12CRCERR */
AnnaBridge 170:e95d10626187 961 #define _SDIO_AC12ERRSTAT_AC12CRCERR_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCERR */
AnnaBridge 170:e95d10626187 962 #define _SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 963 #define SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 964 #define SDIO_AC12ERRSTAT_AC12ENDBITERR (0x1UL << 3) /**< Auto CMD End Bit Error */
AnnaBridge 170:e95d10626187 965 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_SHIFT 3 /**< Shift value for SDIO_AC12ENDBITERR */
AnnaBridge 170:e95d10626187 966 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_MASK 0x8UL /**< Bit mask for SDIO_AC12ENDBITERR */
AnnaBridge 170:e95d10626187 967 #define _SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 968 #define SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 969 #define SDIO_AC12ERRSTAT_AC12INDEXERR (0x1UL << 4) /**< Auto CMD Index Error */
AnnaBridge 170:e95d10626187 970 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_SHIFT 4 /**< Shift value for SDIO_AC12INDEXERR */
AnnaBridge 170:e95d10626187 971 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_MASK 0x10UL /**< Bit mask for SDIO_AC12INDEXERR */
AnnaBridge 170:e95d10626187 972 #define _SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 973 #define SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT (_SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 974 #define SDIO_AC12ERRSTAT_CNIBAC12ERR (0x1UL << 7) /**< Command Not issued by Auto CMD12 Error */
AnnaBridge 170:e95d10626187 975 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_SHIFT 7 /**< Shift value for SDIO_CNIBAC12ERR */
AnnaBridge 170:e95d10626187 976 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12ERR */
AnnaBridge 170:e95d10626187 977 #define _SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 978 #define SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT (_SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 979 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SHIFT 16 /**< Shift value for SDIO_UHSMODESEL */
AnnaBridge 170:e95d10626187 980 #define _SDIO_AC12ERRSTAT_UHSMODESEL_MASK 0x70000UL /**< Bit mask for SDIO_UHSMODESEL */
AnnaBridge 170:e95d10626187 981 #define _SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 982 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 0x00000000UL /**< Mode SDR12 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 983 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 0x00000001UL /**< Mode SDR25 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 984 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 0x00000002UL /**< Mode SDR50 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 985 #define _SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 0x00000003UL /**< Mode SDR104 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 986 #define _SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 0x00000004UL /**< Mode DDR50 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 987 #define SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT (_SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 988 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR12 << 16) /**< Shifted mode SDR12 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 989 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR25 << 16) /**< Shifted mode SDR25 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 990 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR50 << 16) /**< Shifted mode SDR50 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 991 #define SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 (_SDIO_AC12ERRSTAT_UHSMODESEL_SDR104 << 16) /**< Shifted mode SDR104 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 992 #define SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 (_SDIO_AC12ERRSTAT_UHSMODESEL_DDR50 << 16) /**< Shifted mode DDR50 for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 993 #define SDIO_AC12ERRSTAT_SIGEN1P8V (0x1UL << 19) /**< Voltage 1.8V Signal Enable */
AnnaBridge 170:e95d10626187 994 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_SHIFT 19 /**< Shift value for SDIO_SIGEN1P8V */
AnnaBridge 170:e95d10626187 995 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_MASK 0x80000UL /**< Bit mask for SDIO_SIGEN1P8V */
AnnaBridge 170:e95d10626187 996 #define _SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 997 #define SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT (_SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 998 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_SHIFT 20 /**< Shift value for SDIO_DRVSTNSEL */
AnnaBridge 170:e95d10626187 999 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_MASK 0x300000UL /**< Bit mask for SDIO_DRVSTNSEL */
AnnaBridge 170:e95d10626187 1000 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1001 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1002 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1003 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1004 #define _SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1005 #define SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT (_SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1006 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB << 20) /**< Shifted mode TYPEB for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1007 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA << 20) /**< Shifted mode TYPEA for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1008 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC << 20) /**< Shifted mode TYPEC for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1009 #define SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED (_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED << 20) /**< Shifted mode TYPED for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1010 #define SDIO_AC12ERRSTAT_EXETUNING (0x1UL << 22) /**< Execute Tuning */
AnnaBridge 170:e95d10626187 1011 #define _SDIO_AC12ERRSTAT_EXETUNING_SHIFT 22 /**< Shift value for SDIO_EXETUNING */
AnnaBridge 170:e95d10626187 1012 #define _SDIO_AC12ERRSTAT_EXETUNING_MASK 0x400000UL /**< Bit mask for SDIO_EXETUNING */
AnnaBridge 170:e95d10626187 1013 #define _SDIO_AC12ERRSTAT_EXETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1014 #define SDIO_AC12ERRSTAT_EXETUNING_DEFAULT (_SDIO_AC12ERRSTAT_EXETUNING_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1015 #define SDIO_AC12ERRSTAT_SAMPCLKSEL (0x1UL << 23) /**< Sampling Clock Select */
AnnaBridge 170:e95d10626187 1016 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_SHIFT 23 /**< Shift value for SDIO_SAMPCLKSEL */
AnnaBridge 170:e95d10626187 1017 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_MASK 0x800000UL /**< Bit mask for SDIO_SAMPCLKSEL */
AnnaBridge 170:e95d10626187 1018 #define _SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1019 #define SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT (_SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1020 #define SDIO_AC12ERRSTAT_ASYNCINTEN (0x1UL << 30) /**< Asynchronous Interrupt Enable */
AnnaBridge 170:e95d10626187 1021 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_SHIFT 30 /**< Shift value for SDIO_ASYNCINTEN */
AnnaBridge 170:e95d10626187 1022 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_MASK 0x40000000UL /**< Bit mask for SDIO_ASYNCINTEN */
AnnaBridge 170:e95d10626187 1023 #define _SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1024 #define SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT (_SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1025 #define SDIO_AC12ERRSTAT_PRSTVALEN (0x1UL << 31) /**< Preset Value Enable */
AnnaBridge 170:e95d10626187 1026 #define _SDIO_AC12ERRSTAT_PRSTVALEN_SHIFT 31 /**< Shift value for SDIO_PRSTVALEN */
AnnaBridge 170:e95d10626187 1027 #define _SDIO_AC12ERRSTAT_PRSTVALEN_MASK 0x80000000UL /**< Bit mask for SDIO_PRSTVALEN */
AnnaBridge 170:e95d10626187 1028 #define _SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1029 #define SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT (_SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for SDIO_AC12ERRSTAT */
AnnaBridge 170:e95d10626187 1030
AnnaBridge 170:e95d10626187 1031 /* Bit fields for SDIO CAPAB0 */
AnnaBridge 170:e95d10626187 1032 #define _SDIO_CAPAB0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1033 #define _SDIO_CAPAB0_MASK 0xF7EFFFBFUL /**< Mask for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1034 #define _SDIO_CAPAB0_TMOUTCLKFREQ_SHIFT 0 /**< Shift value for SDIO_TMOUTCLKFREQ */
AnnaBridge 170:e95d10626187 1035 #define _SDIO_CAPAB0_TMOUTCLKFREQ_MASK 0x3FUL /**< Bit mask for SDIO_TMOUTCLKFREQ */
AnnaBridge 170:e95d10626187 1036 #define _SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1037 #define SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT (_SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1038 #define SDIO_CAPAB0_TMOUTCLKUNIT (0x1UL << 7) /**< Timeout Clock Unit */
AnnaBridge 170:e95d10626187 1039 #define _SDIO_CAPAB0_TMOUTCLKUNIT_SHIFT 7 /**< Shift value for SDIO_TMOUTCLKUNIT */
AnnaBridge 170:e95d10626187 1040 #define _SDIO_CAPAB0_TMOUTCLKUNIT_MASK 0x80UL /**< Bit mask for SDIO_TMOUTCLKUNIT */
AnnaBridge 170:e95d10626187 1041 #define _SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1042 #define SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT (_SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1043 #define _SDIO_CAPAB0_BASECLKFREQSD_SHIFT 8 /**< Shift value for SDIO_BASECLKFREQSD */
AnnaBridge 170:e95d10626187 1044 #define _SDIO_CAPAB0_BASECLKFREQSD_MASK 0xFF00UL /**< Bit mask for SDIO_BASECLKFREQSD */
AnnaBridge 170:e95d10626187 1045 #define _SDIO_CAPAB0_BASECLKFREQSD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1046 #define SDIO_CAPAB0_BASECLKFREQSD_DEFAULT (_SDIO_CAPAB0_BASECLKFREQSD_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1047 #define _SDIO_CAPAB0_MAXBLOCKLEN_SHIFT 16 /**< Shift value for SDIO_MAXBLOCKLEN */
AnnaBridge 170:e95d10626187 1048 #define _SDIO_CAPAB0_MAXBLOCKLEN_MASK 0x30000UL /**< Bit mask for SDIO_MAXBLOCKLEN */
AnnaBridge 170:e95d10626187 1049 #define _SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1050 #define SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT (_SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1051 #define SDIO_CAPAB0_EXTMEDIABUSSUP (0x1UL << 18) /**< Extended Media Bus Support */
AnnaBridge 170:e95d10626187 1052 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_SHIFT 18 /**< Shift value for SDIO_EXTMEDIABUSSUP */
AnnaBridge 170:e95d10626187 1053 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_MASK 0x40000UL /**< Bit mask for SDIO_EXTMEDIABUSSUP */
AnnaBridge 170:e95d10626187 1054 #define _SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1055 #define SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT (_SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1056 #define SDIO_CAPAB0_ADMA2SUP (0x1UL << 19) /**< ADMA2 support */
AnnaBridge 170:e95d10626187 1057 #define _SDIO_CAPAB0_ADMA2SUP_SHIFT 19 /**< Shift value for SDIO_ADMA2SUP */
AnnaBridge 170:e95d10626187 1058 #define _SDIO_CAPAB0_ADMA2SUP_MASK 0x80000UL /**< Bit mask for SDIO_ADMA2SUP */
AnnaBridge 170:e95d10626187 1059 #define _SDIO_CAPAB0_ADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1060 #define SDIO_CAPAB0_ADMA2SUP_DEFAULT (_SDIO_CAPAB0_ADMA2SUP_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1061 #define SDIO_CAPAB0_HSSUP (0x1UL << 21) /**< High Speed Support */
AnnaBridge 170:e95d10626187 1062 #define _SDIO_CAPAB0_HSSUP_SHIFT 21 /**< Shift value for SDIO_HSSUP */
AnnaBridge 170:e95d10626187 1063 #define _SDIO_CAPAB0_HSSUP_MASK 0x200000UL /**< Bit mask for SDIO_HSSUP */
AnnaBridge 170:e95d10626187 1064 #define _SDIO_CAPAB0_HSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1065 #define SDIO_CAPAB0_HSSUP_DEFAULT (_SDIO_CAPAB0_HSSUP_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1066 #define SDIO_CAPAB0_SDMASUP (0x1UL << 22) /**< SDMA Support */
AnnaBridge 170:e95d10626187 1067 #define _SDIO_CAPAB0_SDMASUP_SHIFT 22 /**< Shift value for SDIO_SDMASUP */
AnnaBridge 170:e95d10626187 1068 #define _SDIO_CAPAB0_SDMASUP_MASK 0x400000UL /**< Bit mask for SDIO_SDMASUP */
AnnaBridge 170:e95d10626187 1069 #define _SDIO_CAPAB0_SDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1070 #define SDIO_CAPAB0_SDMASUP_DEFAULT (_SDIO_CAPAB0_SDMASUP_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1071 #define SDIO_CAPAB0_SUSRESSUP (0x1UL << 23) /**< Suspend / Resume Support */
AnnaBridge 170:e95d10626187 1072 #define _SDIO_CAPAB0_SUSRESSUP_SHIFT 23 /**< Shift value for SDIO_SUSRESSUP */
AnnaBridge 170:e95d10626187 1073 #define _SDIO_CAPAB0_SUSRESSUP_MASK 0x800000UL /**< Bit mask for SDIO_SUSRESSUP */
AnnaBridge 170:e95d10626187 1074 #define _SDIO_CAPAB0_SUSRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1075 #define SDIO_CAPAB0_SUSRESSUP_DEFAULT (_SDIO_CAPAB0_SUSRESSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1076 #define SDIO_CAPAB0_VOLTSUP3P3V (0x1UL << 24) /**< Voltage Support 3.3V */
AnnaBridge 170:e95d10626187 1077 #define _SDIO_CAPAB0_VOLTSUP3P3V_SHIFT 24 /**< Shift value for SDIO_VOLTSUP3P3V */
AnnaBridge 170:e95d10626187 1078 #define _SDIO_CAPAB0_VOLTSUP3P3V_MASK 0x1000000UL /**< Bit mask for SDIO_VOLTSUP3P3V */
AnnaBridge 170:e95d10626187 1079 #define _SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1080 #define SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1081 #define SDIO_CAPAB0_VOLTSUP3P0V (0x1UL << 25) /**< Voltage Support 3.0V */
AnnaBridge 170:e95d10626187 1082 #define _SDIO_CAPAB0_VOLTSUP3P0V_SHIFT 25 /**< Shift value for SDIO_VOLTSUP3P0V */
AnnaBridge 170:e95d10626187 1083 #define _SDIO_CAPAB0_VOLTSUP3P0V_MASK 0x2000000UL /**< Bit mask for SDIO_VOLTSUP3P0V */
AnnaBridge 170:e95d10626187 1084 #define _SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1085 #define SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT (_SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1086 #define SDIO_CAPAB0_VOLTSUP1P8V (0x1UL << 26) /**< Voltage Support 1.8V */
AnnaBridge 170:e95d10626187 1087 #define _SDIO_CAPAB0_VOLTSUP1P8V_SHIFT 26 /**< Shift value for SDIO_VOLTSUP1P8V */
AnnaBridge 170:e95d10626187 1088 #define _SDIO_CAPAB0_VOLTSUP1P8V_MASK 0x4000000UL /**< Bit mask for SDIO_VOLTSUP1P8V */
AnnaBridge 170:e95d10626187 1089 #define _SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1090 #define SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT (_SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1091 #define SDIO_CAPAB0_SYSBUS64BSUP (0x1UL << 28) /**< System Bus 64-bit Support */
AnnaBridge 170:e95d10626187 1092 #define _SDIO_CAPAB0_SYSBUS64BSUP_SHIFT 28 /**< Shift value for SDIO_SYSBUS64BSUP */
AnnaBridge 170:e95d10626187 1093 #define _SDIO_CAPAB0_SYSBUS64BSUP_MASK 0x10000000UL /**< Bit mask for SDIO_SYSBUS64BSUP */
AnnaBridge 170:e95d10626187 1094 #define _SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1095 #define SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT (_SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1096 #define SDIO_CAPAB0_ASYNCINTSUP (0x1UL << 29) /**< Asynchronous Interrupt Support */
AnnaBridge 170:e95d10626187 1097 #define _SDIO_CAPAB0_ASYNCINTSUP_SHIFT 29 /**< Shift value for SDIO_ASYNCINTSUP */
AnnaBridge 170:e95d10626187 1098 #define _SDIO_CAPAB0_ASYNCINTSUP_MASK 0x20000000UL /**< Bit mask for SDIO_ASYNCINTSUP */
AnnaBridge 170:e95d10626187 1099 #define _SDIO_CAPAB0_ASYNCINTSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1100 #define SDIO_CAPAB0_ASYNCINTSUP_DEFAULT (_SDIO_CAPAB0_ASYNCINTSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1101 #define _SDIO_CAPAB0_IFSLOTTYPE_SHIFT 30 /**< Shift value for SDIO_IFSLOTTYPE */
AnnaBridge 170:e95d10626187 1102 #define _SDIO_CAPAB0_IFSLOTTYPE_MASK 0xC0000000UL /**< Bit mask for SDIO_IFSLOTTYPE */
AnnaBridge 170:e95d10626187 1103 #define _SDIO_CAPAB0_IFSLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1104 #define _SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE 0x00000000UL /**< Mode REMOVABLE for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1105 #define _SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED 0x00000001UL /**< Mode EMBEDDED for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1106 #define _SDIO_CAPAB0_IFSLOTTYPE_SHARED 0x00000002UL /**< Mode SHARED for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1107 #define SDIO_CAPAB0_IFSLOTTYPE_DEFAULT (_SDIO_CAPAB0_IFSLOTTYPE_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1108 #define SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE (_SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE << 30) /**< Shifted mode REMOVABLE for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1109 #define SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED (_SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED << 30) /**< Shifted mode EMBEDDED for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1110 #define SDIO_CAPAB0_IFSLOTTYPE_SHARED (_SDIO_CAPAB0_IFSLOTTYPE_SHARED << 30) /**< Shifted mode SHARED for SDIO_CAPAB0 */
AnnaBridge 170:e95d10626187 1111
AnnaBridge 170:e95d10626187 1112 /* Bit fields for SDIO CAPAB2 */
AnnaBridge 170:e95d10626187 1113 #define _SDIO_CAPAB2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1114 #define _SDIO_CAPAB2_MASK 0x03FFEF77UL /**< Mask for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1115 #define SDIO_CAPAB2_SDR50SUP (0x1UL << 0) /**< SDR50 Support */
AnnaBridge 170:e95d10626187 1116 #define _SDIO_CAPAB2_SDR50SUP_SHIFT 0 /**< Shift value for SDIO_SDR50SUP */
AnnaBridge 170:e95d10626187 1117 #define _SDIO_CAPAB2_SDR50SUP_MASK 0x1UL /**< Bit mask for SDIO_SDR50SUP */
AnnaBridge 170:e95d10626187 1118 #define _SDIO_CAPAB2_SDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1119 #define SDIO_CAPAB2_SDR50SUP_DEFAULT (_SDIO_CAPAB2_SDR50SUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1120 #define SDIO_CAPAB2_SDR104SUP (0x1UL << 1) /**< SDR104 Support */
AnnaBridge 170:e95d10626187 1121 #define _SDIO_CAPAB2_SDR104SUP_SHIFT 1 /**< Shift value for SDIO_SDR104SUP */
AnnaBridge 170:e95d10626187 1122 #define _SDIO_CAPAB2_SDR104SUP_MASK 0x2UL /**< Bit mask for SDIO_SDR104SUP */
AnnaBridge 170:e95d10626187 1123 #define _SDIO_CAPAB2_SDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1124 #define SDIO_CAPAB2_SDR104SUP_DEFAULT (_SDIO_CAPAB2_SDR104SUP_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1125 #define SDIO_CAPAB2_DDR50SUP (0x1UL << 2) /**< DDR50 Support */
AnnaBridge 170:e95d10626187 1126 #define _SDIO_CAPAB2_DDR50SUP_SHIFT 2 /**< Shift value for SDIO_DDR50SUP */
AnnaBridge 170:e95d10626187 1127 #define _SDIO_CAPAB2_DDR50SUP_MASK 0x4UL /**< Bit mask for SDIO_DDR50SUP */
AnnaBridge 170:e95d10626187 1128 #define _SDIO_CAPAB2_DDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1129 #define SDIO_CAPAB2_DDR50SUP_DEFAULT (_SDIO_CAPAB2_DDR50SUP_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1130 #define SDIO_CAPAB2_DRVTYPASUP (0x1UL << 4) /**< Driver Type A Support */
AnnaBridge 170:e95d10626187 1131 #define _SDIO_CAPAB2_DRVTYPASUP_SHIFT 4 /**< Shift value for SDIO_DRVTYPASUP */
AnnaBridge 170:e95d10626187 1132 #define _SDIO_CAPAB2_DRVTYPASUP_MASK 0x10UL /**< Bit mask for SDIO_DRVTYPASUP */
AnnaBridge 170:e95d10626187 1133 #define _SDIO_CAPAB2_DRVTYPASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1134 #define SDIO_CAPAB2_DRVTYPASUP_DEFAULT (_SDIO_CAPAB2_DRVTYPASUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1135 #define SDIO_CAPAB2_DRVTYPCSUP (0x1UL << 5) /**< Driver Type C Support */
AnnaBridge 170:e95d10626187 1136 #define _SDIO_CAPAB2_DRVTYPCSUP_SHIFT 5 /**< Shift value for SDIO_DRVTYPCSUP */
AnnaBridge 170:e95d10626187 1137 #define _SDIO_CAPAB2_DRVTYPCSUP_MASK 0x20UL /**< Bit mask for SDIO_DRVTYPCSUP */
AnnaBridge 170:e95d10626187 1138 #define _SDIO_CAPAB2_DRVTYPCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1139 #define SDIO_CAPAB2_DRVTYPCSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPCSUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1140 #define SDIO_CAPAB2_DRVTYPDSUP (0x1UL << 6) /**< Driver Type D Support */
AnnaBridge 170:e95d10626187 1141 #define _SDIO_CAPAB2_DRVTYPDSUP_SHIFT 6 /**< Shift value for SDIO_DRVTYPDSUP */
AnnaBridge 170:e95d10626187 1142 #define _SDIO_CAPAB2_DRVTYPDSUP_MASK 0x40UL /**< Bit mask for SDIO_DRVTYPDSUP */
AnnaBridge 170:e95d10626187 1143 #define _SDIO_CAPAB2_DRVTYPDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1144 #define SDIO_CAPAB2_DRVTYPDSUP_DEFAULT (_SDIO_CAPAB2_DRVTYPDSUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1145 #define _SDIO_CAPAB2_TIMCNTRETUN_SHIFT 8 /**< Shift value for SDIO_TIMCNTRETUN */
AnnaBridge 170:e95d10626187 1146 #define _SDIO_CAPAB2_TIMCNTRETUN_MASK 0xF00UL /**< Bit mask for SDIO_TIMCNTRETUN */
AnnaBridge 170:e95d10626187 1147 #define _SDIO_CAPAB2_TIMCNTRETUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1148 #define SDIO_CAPAB2_TIMCNTRETUN_DEFAULT (_SDIO_CAPAB2_TIMCNTRETUN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1149 #define SDIO_CAPAB2_USETUNSDR50 (0x1UL << 13) /**< Use Tuning for SDR50 */
AnnaBridge 170:e95d10626187 1150 #define _SDIO_CAPAB2_USETUNSDR50_SHIFT 13 /**< Shift value for SDIO_USETUNSDR50 */
AnnaBridge 170:e95d10626187 1151 #define _SDIO_CAPAB2_USETUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_USETUNSDR50 */
AnnaBridge 170:e95d10626187 1152 #define _SDIO_CAPAB2_USETUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1153 #define SDIO_CAPAB2_USETUNSDR50_DEFAULT (_SDIO_CAPAB2_USETUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1154 #define _SDIO_CAPAB2_RETUNEMODES_SHIFT 14 /**< Shift value for SDIO_RETUNEMODES */
AnnaBridge 170:e95d10626187 1155 #define _SDIO_CAPAB2_RETUNEMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNEMODES */
AnnaBridge 170:e95d10626187 1156 #define _SDIO_CAPAB2_RETUNEMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1157 #define SDIO_CAPAB2_RETUNEMODES_DEFAULT (_SDIO_CAPAB2_RETUNEMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1158 #define _SDIO_CAPAB2_CLOCKKMUL_SHIFT 16 /**< Shift value for SDIO_CLOCKKMUL */
AnnaBridge 170:e95d10626187 1159 #define _SDIO_CAPAB2_CLOCKKMUL_MASK 0xFF0000UL /**< Bit mask for SDIO_CLOCKKMUL */
AnnaBridge 170:e95d10626187 1160 #define _SDIO_CAPAB2_CLOCKKMUL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1161 #define SDIO_CAPAB2_CLOCKKMUL_DEFAULT (_SDIO_CAPAB2_CLOCKKMUL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1162 #define SDIO_CAPAB2_SPIMODE (0x1UL << 24) /**< SPI mode support */
AnnaBridge 170:e95d10626187 1163 #define _SDIO_CAPAB2_SPIMODE_SHIFT 24 /**< Shift value for SDIO_SPIMODE */
AnnaBridge 170:e95d10626187 1164 #define _SDIO_CAPAB2_SPIMODE_MASK 0x1000000UL /**< Bit mask for SDIO_SPIMODE */
AnnaBridge 170:e95d10626187 1165 #define _SDIO_CAPAB2_SPIMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1166 #define SDIO_CAPAB2_SPIMODE_DEFAULT (_SDIO_CAPAB2_SPIMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1167 #define SDIO_CAPAB2_SPIBLOCKMODE (0x1UL << 25) /**< SPI Block mode support */
AnnaBridge 170:e95d10626187 1168 #define _SDIO_CAPAB2_SPIBLOCKMODE_SHIFT 25 /**< Shift value for SDIO_SPIBLOCKMODE */
AnnaBridge 170:e95d10626187 1169 #define _SDIO_CAPAB2_SPIBLOCKMODE_MASK 0x2000000UL /**< Bit mask for SDIO_SPIBLOCKMODE */
AnnaBridge 170:e95d10626187 1170 #define _SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1171 #define SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT (_SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CAPAB2 */
AnnaBridge 170:e95d10626187 1172
AnnaBridge 170:e95d10626187 1173 /* Bit fields for SDIO MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1174 #define _SDIO_MAXCURCAPAB_RESETVALUE 0x00000000UL /**< Default value for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1175 #define _SDIO_MAXCURCAPAB_MASK 0x00FFFFFFUL /**< Mask for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1176 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_SHIFT 0 /**< Shift value for SDIO_MAXCUR3P3VAL */
AnnaBridge 170:e95d10626187 1177 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_MASK 0xFFUL /**< Bit mask for SDIO_MAXCUR3P3VAL */
AnnaBridge 170:e95d10626187 1178 #define _SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1179 #define SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1180 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_SHIFT 8 /**< Shift value for SDIO_MAXCUR3P0VAL */
AnnaBridge 170:e95d10626187 1181 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_MASK 0xFF00UL /**< Bit mask for SDIO_MAXCUR3P0VAL */
AnnaBridge 170:e95d10626187 1182 #define _SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1183 #define SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1184 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_SHIFT 16 /**< Shift value for SDIO_MAXCUR1P8VAL */
AnnaBridge 170:e95d10626187 1185 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_MASK 0xFF0000UL /**< Bit mask for SDIO_MAXCUR1P8VAL */
AnnaBridge 170:e95d10626187 1186 #define _SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1187 #define SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT (_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_MAXCURCAPAB */
AnnaBridge 170:e95d10626187 1188
AnnaBridge 170:e95d10626187 1189 /* Bit fields for SDIO FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1190 #define _SDIO_FEVTERRSTAT_RESETVALUE 0x00000000UL /**< Default value for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1191 #define _SDIO_FEVTERRSTAT_MASK 0xF7FF009FUL /**< Mask for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1192 #define SDIO_FEVTERRSTAT_AC12NEX (0x1UL << 0) /**< Force Event for command not issued by Auto CM12 Not Executed */
AnnaBridge 170:e95d10626187 1193 #define _SDIO_FEVTERRSTAT_AC12NEX_SHIFT 0 /**< Shift value for SDIO_AC12NEX */
AnnaBridge 170:e95d10626187 1194 #define _SDIO_FEVTERRSTAT_AC12NEX_MASK 0x1UL /**< Bit mask for SDIO_AC12NEX */
AnnaBridge 170:e95d10626187 1195 #define _SDIO_FEVTERRSTAT_AC12NEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1196 #define SDIO_FEVTERRSTAT_AC12NEX_DEFAULT (_SDIO_FEVTERRSTAT_AC12NEX_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1197 #define SDIO_FEVTERRSTAT_AC12TOE (0x1UL << 1) /**< Force Event for Auto CMD Timeout Error */
AnnaBridge 170:e95d10626187 1198 #define _SDIO_FEVTERRSTAT_AC12TOE_SHIFT 1 /**< Shift value for SDIO_AC12TOE */
AnnaBridge 170:e95d10626187 1199 #define _SDIO_FEVTERRSTAT_AC12TOE_MASK 0x2UL /**< Bit mask for SDIO_AC12TOE */
AnnaBridge 170:e95d10626187 1200 #define _SDIO_FEVTERRSTAT_AC12TOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1201 #define SDIO_FEVTERRSTAT_AC12TOE_DEFAULT (_SDIO_FEVTERRSTAT_AC12TOE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1202 #define SDIO_FEVTERRSTAT_AC12CRCE (0x1UL << 2) /**< Force Event for Auto CMD CRC Error */
AnnaBridge 170:e95d10626187 1203 #define _SDIO_FEVTERRSTAT_AC12CRCE_SHIFT 2 /**< Shift value for SDIO_AC12CRCE */
AnnaBridge 170:e95d10626187 1204 #define _SDIO_FEVTERRSTAT_AC12CRCE_MASK 0x4UL /**< Bit mask for SDIO_AC12CRCE */
AnnaBridge 170:e95d10626187 1205 #define _SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1206 #define SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT (_SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1207 #define SDIO_FEVTERRSTAT_AC12EBE (0x1UL << 3) /**< Force Event for Auto CMD End bit Error */
AnnaBridge 170:e95d10626187 1208 #define _SDIO_FEVTERRSTAT_AC12EBE_SHIFT 3 /**< Shift value for SDIO_AC12EBE */
AnnaBridge 170:e95d10626187 1209 #define _SDIO_FEVTERRSTAT_AC12EBE_MASK 0x8UL /**< Bit mask for SDIO_AC12EBE */
AnnaBridge 170:e95d10626187 1210 #define _SDIO_FEVTERRSTAT_AC12EBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1211 #define SDIO_FEVTERRSTAT_AC12EBE_DEFAULT (_SDIO_FEVTERRSTAT_AC12EBE_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1212 #define SDIO_FEVTERRSTAT_AC12INDXE (0x1UL << 4) /**< Force Event for Auto CMD Index Error */
AnnaBridge 170:e95d10626187 1213 #define _SDIO_FEVTERRSTAT_AC12INDXE_SHIFT 4 /**< Shift value for SDIO_AC12INDXE */
AnnaBridge 170:e95d10626187 1214 #define _SDIO_FEVTERRSTAT_AC12INDXE_MASK 0x10UL /**< Bit mask for SDIO_AC12INDXE */
AnnaBridge 170:e95d10626187 1215 #define _SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1216 #define SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT (_SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1217 #define SDIO_FEVTERRSTAT_CNIBAC12E (0x1UL << 7) /**< Force Event for command not issued by Auto CMD12 Error */
AnnaBridge 170:e95d10626187 1218 #define _SDIO_FEVTERRSTAT_CNIBAC12E_SHIFT 7 /**< Shift value for SDIO_CNIBAC12E */
AnnaBridge 170:e95d10626187 1219 #define _SDIO_FEVTERRSTAT_CNIBAC12E_MASK 0x80UL /**< Bit mask for SDIO_CNIBAC12E */
AnnaBridge 170:e95d10626187 1220 #define _SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1221 #define SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT (_SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1222 #define SDIO_FEVTERRSTAT_CMDTOE (0x1UL << 16) /**< Force Event for Command Timeout Error */
AnnaBridge 170:e95d10626187 1223 #define _SDIO_FEVTERRSTAT_CMDTOE_SHIFT 16 /**< Shift value for SDIO_CMDTOE */
AnnaBridge 170:e95d10626187 1224 #define _SDIO_FEVTERRSTAT_CMDTOE_MASK 0x10000UL /**< Bit mask for SDIO_CMDTOE */
AnnaBridge 170:e95d10626187 1225 #define _SDIO_FEVTERRSTAT_CMDTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1226 #define SDIO_FEVTERRSTAT_CMDTOE_DEFAULT (_SDIO_FEVTERRSTAT_CMDTOE_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1227 #define SDIO_FEVTERRSTAT_CMDCRCE (0x1UL << 17) /**< Force Event for Command CRC Error */
AnnaBridge 170:e95d10626187 1228 #define _SDIO_FEVTERRSTAT_CMDCRCE_SHIFT 17 /**< Shift value for SDIO_CMDCRCE */
AnnaBridge 170:e95d10626187 1229 #define _SDIO_FEVTERRSTAT_CMDCRCE_MASK 0x20000UL /**< Bit mask for SDIO_CMDCRCE */
AnnaBridge 170:e95d10626187 1230 #define _SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1231 #define SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT (_SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT << 17) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1232 #define SDIO_FEVTERRSTAT_CMDEBE (0x1UL << 18) /**< Force Event for Command End Bit Error */
AnnaBridge 170:e95d10626187 1233 #define _SDIO_FEVTERRSTAT_CMDEBE_SHIFT 18 /**< Shift value for SDIO_CMDEBE */
AnnaBridge 170:e95d10626187 1234 #define _SDIO_FEVTERRSTAT_CMDEBE_MASK 0x40000UL /**< Bit mask for SDIO_CMDEBE */
AnnaBridge 170:e95d10626187 1235 #define _SDIO_FEVTERRSTAT_CMDEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1236 #define SDIO_FEVTERRSTAT_CMDEBE_DEFAULT (_SDIO_FEVTERRSTAT_CMDEBE_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1237 #define SDIO_FEVTERRSTAT_CMDINDXE (0x1UL << 19) /**< Force Event for Command Index Error */
AnnaBridge 170:e95d10626187 1238 #define _SDIO_FEVTERRSTAT_CMDINDXE_SHIFT 19 /**< Shift value for SDIO_CMDINDXE */
AnnaBridge 170:e95d10626187 1239 #define _SDIO_FEVTERRSTAT_CMDINDXE_MASK 0x80000UL /**< Bit mask for SDIO_CMDINDXE */
AnnaBridge 170:e95d10626187 1240 #define _SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1241 #define SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT (_SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT << 19) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1242 #define SDIO_FEVTERRSTAT_DATTOE (0x1UL << 20) /**< Force Event for Data Timeout Error */
AnnaBridge 170:e95d10626187 1243 #define _SDIO_FEVTERRSTAT_DATTOE_SHIFT 20 /**< Shift value for SDIO_DATTOE */
AnnaBridge 170:e95d10626187 1244 #define _SDIO_FEVTERRSTAT_DATTOE_MASK 0x100000UL /**< Bit mask for SDIO_DATTOE */
AnnaBridge 170:e95d10626187 1245 #define _SDIO_FEVTERRSTAT_DATTOE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1246 #define SDIO_FEVTERRSTAT_DATTOE_DEFAULT (_SDIO_FEVTERRSTAT_DATTOE_DEFAULT << 20) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1247 #define SDIO_FEVTERRSTAT_DATCRCE (0x1UL << 21) /**< Force Event for Data CRC Error */
AnnaBridge 170:e95d10626187 1248 #define _SDIO_FEVTERRSTAT_DATCRCE_SHIFT 21 /**< Shift value for SDIO_DATCRCE */
AnnaBridge 170:e95d10626187 1249 #define _SDIO_FEVTERRSTAT_DATCRCE_MASK 0x200000UL /**< Bit mask for SDIO_DATCRCE */
AnnaBridge 170:e95d10626187 1250 #define _SDIO_FEVTERRSTAT_DATCRCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1251 #define SDIO_FEVTERRSTAT_DATCRCE_DEFAULT (_SDIO_FEVTERRSTAT_DATCRCE_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1252 #define SDIO_FEVTERRSTAT_DATEBE (0x1UL << 22) /**< Force Event for Data End Bit Error */
AnnaBridge 170:e95d10626187 1253 #define _SDIO_FEVTERRSTAT_DATEBE_SHIFT 22 /**< Shift value for SDIO_DATEBE */
AnnaBridge 170:e95d10626187 1254 #define _SDIO_FEVTERRSTAT_DATEBE_MASK 0x400000UL /**< Bit mask for SDIO_DATEBE */
AnnaBridge 170:e95d10626187 1255 #define _SDIO_FEVTERRSTAT_DATEBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1256 #define SDIO_FEVTERRSTAT_DATEBE_DEFAULT (_SDIO_FEVTERRSTAT_DATEBE_DEFAULT << 22) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1257 #define SDIO_FEVTERRSTAT_CURLIMITE (0x1UL << 23) /**< Force Event for Current Limit Error */
AnnaBridge 170:e95d10626187 1258 #define _SDIO_FEVTERRSTAT_CURLIMITE_SHIFT 23 /**< Shift value for SDIO_CURLIMITE */
AnnaBridge 170:e95d10626187 1259 #define _SDIO_FEVTERRSTAT_CURLIMITE_MASK 0x800000UL /**< Bit mask for SDIO_CURLIMITE */
AnnaBridge 170:e95d10626187 1260 #define _SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1261 #define SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT (_SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1262 #define SDIO_FEVTERRSTAT_AC12E (0x1UL << 24) /**< Force Event for Auto CMD Error */
AnnaBridge 170:e95d10626187 1263 #define _SDIO_FEVTERRSTAT_AC12E_SHIFT 24 /**< Shift value for SDIO_AC12E */
AnnaBridge 170:e95d10626187 1264 #define _SDIO_FEVTERRSTAT_AC12E_MASK 0x1000000UL /**< Bit mask for SDIO_AC12E */
AnnaBridge 170:e95d10626187 1265 #define _SDIO_FEVTERRSTAT_AC12E_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1266 #define SDIO_FEVTERRSTAT_AC12E_DEFAULT (_SDIO_FEVTERRSTAT_AC12E_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1267 #define SDIO_FEVTERRSTAT_ADMAE (0x1UL << 25) /**< Force Event for ADMA Error */
AnnaBridge 170:e95d10626187 1268 #define _SDIO_FEVTERRSTAT_ADMAE_SHIFT 25 /**< Shift value for SDIO_ADMAE */
AnnaBridge 170:e95d10626187 1269 #define _SDIO_FEVTERRSTAT_ADMAE_MASK 0x2000000UL /**< Bit mask for SDIO_ADMAE */
AnnaBridge 170:e95d10626187 1270 #define _SDIO_FEVTERRSTAT_ADMAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1271 #define SDIO_FEVTERRSTAT_ADMAE_DEFAULT (_SDIO_FEVTERRSTAT_ADMAE_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1272 #define SDIO_FEVTERRSTAT_TUNINGE (0x1UL << 26) /**< Force Event for Tuning Errro */
AnnaBridge 170:e95d10626187 1273 #define _SDIO_FEVTERRSTAT_TUNINGE_SHIFT 26 /**< Shift value for SDIO_TUNINGE */
AnnaBridge 170:e95d10626187 1274 #define _SDIO_FEVTERRSTAT_TUNINGE_MASK 0x4000000UL /**< Bit mask for SDIO_TUNINGE */
AnnaBridge 170:e95d10626187 1275 #define _SDIO_FEVTERRSTAT_TUNINGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1276 #define SDIO_FEVTERRSTAT_TUNINGE_DEFAULT (_SDIO_FEVTERRSTAT_TUNINGE_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1277 #define _SDIO_FEVTERRSTAT_VENSPECE_SHIFT 28 /**< Shift value for SDIO_VENSPECE */
AnnaBridge 170:e95d10626187 1278 #define _SDIO_FEVTERRSTAT_VENSPECE_MASK 0xF0000000UL /**< Bit mask for SDIO_VENSPECE */
AnnaBridge 170:e95d10626187 1279 #define _SDIO_FEVTERRSTAT_VENSPECE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1280 #define SDIO_FEVTERRSTAT_VENSPECE_DEFAULT (_SDIO_FEVTERRSTAT_VENSPECE_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_FEVTERRSTAT */
AnnaBridge 170:e95d10626187 1281
AnnaBridge 170:e95d10626187 1282 /* Bit fields for SDIO ADMAES */
AnnaBridge 170:e95d10626187 1283 #define _SDIO_ADMAES_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1284 #define _SDIO_ADMAES_MASK 0x00000007UL /**< Mask for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1285 #define _SDIO_ADMAES_ADMAES_SHIFT 0 /**< Shift value for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1286 #define _SDIO_ADMAES_ADMAES_MASK 0x3UL /**< Bit mask for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1287 #define _SDIO_ADMAES_ADMAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1288 #define SDIO_ADMAES_ADMAES_DEFAULT (_SDIO_ADMAES_ADMAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1289 #define SDIO_ADMAES_ADMALME (0x1UL << 2) /**< ADMA Length Mismatch Error */
AnnaBridge 170:e95d10626187 1290 #define _SDIO_ADMAES_ADMALME_SHIFT 2 /**< Shift value for SDIO_ADMALME */
AnnaBridge 170:e95d10626187 1291 #define _SDIO_ADMAES_ADMALME_MASK 0x4UL /**< Bit mask for SDIO_ADMALME */
AnnaBridge 170:e95d10626187 1292 #define _SDIO_ADMAES_ADMALME_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1293 #define SDIO_ADMAES_ADMALME_DEFAULT (_SDIO_ADMAES_ADMALME_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ADMAES */
AnnaBridge 170:e95d10626187 1294
AnnaBridge 170:e95d10626187 1295 /* Bit fields for SDIO ADSADDR */
AnnaBridge 170:e95d10626187 1296 #define _SDIO_ADSADDR_RESETVALUE 0x00000000UL /**< Default value for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1297 #define _SDIO_ADSADDR_MASK 0xFFFFFFFFUL /**< Mask for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1298 #define _SDIO_ADSADDR_ADSADDR_SHIFT 0 /**< Shift value for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1299 #define _SDIO_ADSADDR_ADSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1300 #define _SDIO_ADSADDR_ADSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1301 #define SDIO_ADSADDR_ADSADDR_DEFAULT (_SDIO_ADSADDR_ADSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ADSADDR */
AnnaBridge 170:e95d10626187 1302
AnnaBridge 170:e95d10626187 1303 /* Bit fields for SDIO PRSTVAL0 */
AnnaBridge 170:e95d10626187 1304 #define _SDIO_PRSTVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1305 #define _SDIO_PRSTVAL0_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1306 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1307 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1308 #define _SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1309 #define SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1310 #define SDIO_PRSTVAL0_INITCLCKGENVAL (0x1UL << 10) /**< Clock generator select value for Initialization */
AnnaBridge 170:e95d10626187 1311 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_SHIFT 10 /**< Shift value for SDIO_INITCLCKGENVAL */
AnnaBridge 170:e95d10626187 1312 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_INITCLCKGENVAL */
AnnaBridge 170:e95d10626187 1313 #define _SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1314 #define SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT (_SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1315 #define _SDIO_PRSTVAL0_INITDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_INITDRVSTVAL */
AnnaBridge 170:e95d10626187 1316 #define _SDIO_PRSTVAL0_INITDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_INITDRVSTVAL */
AnnaBridge 170:e95d10626187 1317 #define _SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1318 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1319 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1320 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1321 #define _SDIO_PRSTVAL0_INITDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1322 #define SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1323 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1324 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1325 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1326 #define SDIO_PRSTVAL0_INITDRVSTVAL_TYPED (_SDIO_PRSTVAL0_INITDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1327 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1328 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1329 #define _SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1330 #define SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1331 #define SDIO_PRSTVAL0_DSPCLKGENVAL (0x1UL << 26) /**< Clock generator select value for Default Speed */
AnnaBridge 170:e95d10626187 1332 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENVAL */
AnnaBridge 170:e95d10626187 1333 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENVAL */
AnnaBridge 170:e95d10626187 1334 #define _SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1335 #define SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1336 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DSPDRVSTVAL */
AnnaBridge 170:e95d10626187 1337 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DSPDRVSTVAL */
AnnaBridge 170:e95d10626187 1338 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1339 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1340 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1341 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1342 #define _SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1343 #define SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1344 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1345 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1346 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1347 #define SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED (_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL0 */
AnnaBridge 170:e95d10626187 1348
AnnaBridge 170:e95d10626187 1349 /* Bit fields for SDIO PRSTVAL2 */
AnnaBridge 170:e95d10626187 1350 #define _SDIO_PRSTVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1351 #define _SDIO_PRSTVAL2_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1352 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1353 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1354 #define _SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1355 #define SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1356 #define SDIO_PRSTVAL2_HSPCLKGENVAL (0x1UL << 10) /**< Clock generator select value for High Speed */
AnnaBridge 170:e95d10626187 1357 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENVAL */
AnnaBridge 170:e95d10626187 1358 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENVAL */
AnnaBridge 170:e95d10626187 1359 #define _SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1360 #define SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1361 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_SHIFT 14 /**< Shift value for SDIO_HSPDRVSTVAL */
AnnaBridge 170:e95d10626187 1362 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_HSPDRVSTVAL */
AnnaBridge 170:e95d10626187 1363 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1364 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1365 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1366 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1367 #define _SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1368 #define SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1369 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1370 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1371 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1372 #define SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED (_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1373 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1374 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1375 #define _SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1376 #define SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1377 #define SDIO_PRSTVAL2_SDR12CLKGENVAL (0x1UL << 26) /**< Clock generator select value for SDR12 */
AnnaBridge 170:e95d10626187 1378 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENVAL */
AnnaBridge 170:e95d10626187 1379 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENVAL */
AnnaBridge 170:e95d10626187 1380 #define _SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1381 #define SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1382 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR12DRVSTVAL */
AnnaBridge 170:e95d10626187 1383 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR12DRVSTVAL */
AnnaBridge 170:e95d10626187 1384 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1385 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1386 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1387 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1388 #define _SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1389 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT (_SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1390 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1391 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1392 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1393 #define SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED (_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL2 */
AnnaBridge 170:e95d10626187 1394
AnnaBridge 170:e95d10626187 1395 /* Bit fields for SDIO PRSTVAL4 */
AnnaBridge 170:e95d10626187 1396 #define _SDIO_PRSTVAL4_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1397 #define _SDIO_PRSTVAL4_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1398 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1399 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1400 #define _SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1401 #define SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1402 #define SDIO_PRSTVAL4_SDR25CLKGENVAL (0x1UL << 10) /**< Clock generator select value for SDR25 */
AnnaBridge 170:e95d10626187 1403 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENVAL */
AnnaBridge 170:e95d10626187 1404 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENVAL */
AnnaBridge 170:e95d10626187 1405 #define _SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1406 #define SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1407 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR25DRVSTVAL */
AnnaBridge 170:e95d10626187 1408 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR25DRVSTVAL */
AnnaBridge 170:e95d10626187 1409 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1410 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1411 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1412 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1413 #define _SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1414 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1415 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1416 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1417 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1418 #define SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1419 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1420 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1421 #define _SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1422 #define SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1423 #define SDIO_PRSTVAL4_SDR50CLCKGENVAL (0x1UL << 26) /**< Clock generator select value for SDR50 */
AnnaBridge 170:e95d10626187 1424 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_SHIFT 26 /**< Shift value for SDIO_SDR50CLCKGENVAL */
AnnaBridge 170:e95d10626187 1425 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLCKGENVAL */
AnnaBridge 170:e95d10626187 1426 #define _SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1427 #define SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1428 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_SDR50DRVSTVAL */
AnnaBridge 170:e95d10626187 1429 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_SDR50DRVSTVAL */
AnnaBridge 170:e95d10626187 1430 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1431 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1432 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1433 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1434 #define _SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1435 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1436 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1437 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1438 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1439 #define SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL4 */
AnnaBridge 170:e95d10626187 1440
AnnaBridge 170:e95d10626187 1441 /* Bit fields for SDIO PRSTVAL6 */
AnnaBridge 170:e95d10626187 1442 #define _SDIO_PRSTVAL6_RESETVALUE 0x00000000UL /**< Default value for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1443 #define _SDIO_PRSTVAL6_MASK 0xC7FFC7FFUL /**< Mask for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1444 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1445 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1446 #define _SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1447 #define SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1448 #define SDIO_PRSTVAL6_SDR104CLKGENVAL (0x1UL << 10) /**< Clock generator select value for SDR104 */
AnnaBridge 170:e95d10626187 1449 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENVAL */
AnnaBridge 170:e95d10626187 1450 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENVAL */
AnnaBridge 170:e95d10626187 1451 #define _SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1452 #define SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1453 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_SHIFT 14 /**< Shift value for SDIO_SDR104DRVSTVAL */
AnnaBridge 170:e95d10626187 1454 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_MASK 0xC000UL /**< Bit mask for SDIO_SDR104DRVSTVAL */
AnnaBridge 170:e95d10626187 1455 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1456 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1457 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1458 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1459 #define _SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1460 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1461 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB << 14) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1462 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA << 14) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1463 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC << 14) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1464 #define SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED (_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED << 14) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1465 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1466 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQVAL */
AnnaBridge 170:e95d10626187 1467 #define _SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1468 #define SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1469 #define SDIO_PRSTVAL6_DDR50CLKGENVAL (0x1UL << 26) /**< Clock generator select value for DDR50 */
AnnaBridge 170:e95d10626187 1470 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENVAL */
AnnaBridge 170:e95d10626187 1471 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENVAL */
AnnaBridge 170:e95d10626187 1472 #define _SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1473 #define SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1474 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_SHIFT 30 /**< Shift value for SDIO_DDR50DRVSTVAL */
AnnaBridge 170:e95d10626187 1475 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_MASK 0xC0000000UL /**< Bit mask for SDIO_DDR50DRVSTVAL */
AnnaBridge 170:e95d10626187 1476 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1477 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB 0x00000000UL /**< Mode TYPEB for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1478 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA 0x00000001UL /**< Mode TYPEA for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1479 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC 0x00000002UL /**< Mode TYPEC for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1480 #define _SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED 0x00000003UL /**< Mode TYPED for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1481 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT (_SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1482 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB << 30) /**< Shifted mode TYPEB for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1483 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA << 30) /**< Shifted mode TYPEA for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1484 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC << 30) /**< Shifted mode TYPEC for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1485 #define SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED (_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED << 30) /**< Shifted mode TYPED for SDIO_PRSTVAL6 */
AnnaBridge 170:e95d10626187 1486
AnnaBridge 170:e95d10626187 1487 /* Bit fields for SDIO BOOTTOCTRL */
AnnaBridge 170:e95d10626187 1488 #define _SDIO_BOOTTOCTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_BOOTTOCTRL */
AnnaBridge 170:e95d10626187 1489 #define _SDIO_BOOTTOCTRL_MASK 0xFFFFFFFFUL /**< Mask for SDIO_BOOTTOCTRL */
AnnaBridge 170:e95d10626187 1490 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_SHIFT 0 /**< Shift value for SDIO_BOOTDATTOCNT */
AnnaBridge 170:e95d10626187 1491 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_MASK 0xFFFFFFFFUL /**< Bit mask for SDIO_BOOTDATTOCNT */
AnnaBridge 170:e95d10626187 1492 #define _SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_BOOTTOCTRL */
AnnaBridge 170:e95d10626187 1493 #define SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT (_SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_BOOTTOCTRL */
AnnaBridge 170:e95d10626187 1494
AnnaBridge 170:e95d10626187 1495 /* Bit fields for SDIO SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1496 #define _SDIO_SLOTINTSTAT_RESETVALUE 0x10020000UL /**< Default value for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1497 #define _SDIO_SLOTINTSTAT_MASK 0xFFFF0001UL /**< Mask for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1498 #define SDIO_SLOTINTSTAT_INTSLOT0 (0x1UL << 0) /**< Interrupt Signal for Slot#0 */
AnnaBridge 170:e95d10626187 1499 #define _SDIO_SLOTINTSTAT_INTSLOT0_SHIFT 0 /**< Shift value for SDIO_INTSLOT0 */
AnnaBridge 170:e95d10626187 1500 #define _SDIO_SLOTINTSTAT_INTSLOT0_MASK 0x1UL /**< Bit mask for SDIO_INTSLOT0 */
AnnaBridge 170:e95d10626187 1501 #define _SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1502 #define SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT (_SDIO_SLOTINTSTAT_INTSLOT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1503 #define _SDIO_SLOTINTSTAT_SPECVERNUM_SHIFT 16 /**< Shift value for SDIO_SPECVERNUM */
AnnaBridge 170:e95d10626187 1504 #define _SDIO_SLOTINTSTAT_SPECVERNUM_MASK 0xFF0000UL /**< Bit mask for SDIO_SPECVERNUM */
AnnaBridge 170:e95d10626187 1505 #define _SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT 0x00000002UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1506 #define SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_SPECVERNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1507 #define _SDIO_SLOTINTSTAT_VENDVERNUM_SHIFT 24 /**< Shift value for SDIO_VENDVERNUM */
AnnaBridge 170:e95d10626187 1508 #define _SDIO_SLOTINTSTAT_VENDVERNUM_MASK 0xFF000000UL /**< Bit mask for SDIO_VENDVERNUM */
AnnaBridge 170:e95d10626187 1509 #define _SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT 0x00000010UL /**< Mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1510 #define SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT (_SDIO_SLOTINTSTAT_VENDVERNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_SLOTINTSTAT */
AnnaBridge 170:e95d10626187 1511
AnnaBridge 170:e95d10626187 1512 /* Bit fields for SDIO CTRL */
AnnaBridge 170:e95d10626187 1513 #define _SDIO_CTRL_RESETVALUE 0x00000000UL /**< Default value for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1514 #define _SDIO_CTRL_MASK 0x00030FFFUL /**< Mask for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1515 #define SDIO_CTRL_ITAPDLYEN (0x1UL << 0) /**< Selective tap Delay Line Enable on rxclk_in */
AnnaBridge 170:e95d10626187 1516 #define _SDIO_CTRL_ITAPDLYEN_SHIFT 0 /**< Shift value for SDIO_ITAPDLYEN */
AnnaBridge 170:e95d10626187 1517 #define _SDIO_CTRL_ITAPDLYEN_MASK 0x1UL /**< Bit mask for SDIO_ITAPDLYEN */
AnnaBridge 170:e95d10626187 1518 #define _SDIO_CTRL_ITAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1519 #define SDIO_CTRL_ITAPDLYEN_DEFAULT (_SDIO_CTRL_ITAPDLYEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1520 #define _SDIO_CTRL_ITAPDLYSEL_SHIFT 1 /**< Shift value for SDIO_ITAPDLYSEL */
AnnaBridge 170:e95d10626187 1521 #define _SDIO_CTRL_ITAPDLYSEL_MASK 0x3EUL /**< Bit mask for SDIO_ITAPDLYSEL */
AnnaBridge 170:e95d10626187 1522 #define _SDIO_CTRL_ITAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1523 #define SDIO_CTRL_ITAPDLYSEL_DEFAULT (_SDIO_CTRL_ITAPDLYSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1524 #define SDIO_CTRL_ITAPCHGWIN (0x1UL << 6) /**< Gating signal for Tap Delay change */
AnnaBridge 170:e95d10626187 1525 #define _SDIO_CTRL_ITAPCHGWIN_SHIFT 6 /**< Shift value for SDIO_ITAPCHGWIN */
AnnaBridge 170:e95d10626187 1526 #define _SDIO_CTRL_ITAPCHGWIN_MASK 0x40UL /**< Bit mask for SDIO_ITAPCHGWIN */
AnnaBridge 170:e95d10626187 1527 #define _SDIO_CTRL_ITAPCHGWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1528 #define SDIO_CTRL_ITAPCHGWIN_DEFAULT (_SDIO_CTRL_ITAPCHGWIN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1529 #define SDIO_CTRL_OTAPDLYEN (0x1UL << 7) /**< Selective tap Delay Line Enable on SDIO_CLK pin */
AnnaBridge 170:e95d10626187 1530 #define _SDIO_CTRL_OTAPDLYEN_SHIFT 7 /**< Shift value for SDIO_OTAPDLYEN */
AnnaBridge 170:e95d10626187 1531 #define _SDIO_CTRL_OTAPDLYEN_MASK 0x80UL /**< Bit mask for SDIO_OTAPDLYEN */
AnnaBridge 170:e95d10626187 1532 #define _SDIO_CTRL_OTAPDLYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1533 #define SDIO_CTRL_OTAPDLYEN_DEFAULT (_SDIO_CTRL_OTAPDLYEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1534 #define _SDIO_CTRL_OTAPDLYSEL_SHIFT 8 /**< Shift value for SDIO_OTAPDLYSEL */
AnnaBridge 170:e95d10626187 1535 #define _SDIO_CTRL_OTAPDLYSEL_MASK 0xF00UL /**< Bit mask for SDIO_OTAPDLYSEL */
AnnaBridge 170:e95d10626187 1536 #define _SDIO_CTRL_OTAPDLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1537 #define SDIO_CTRL_OTAPDLYSEL_DEFAULT (_SDIO_CTRL_OTAPDLYSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1538 #define _SDIO_CTRL_TXDLYMUXSEL_SHIFT 16 /**< Shift value for SDIO_TXDLYMUXSEL */
AnnaBridge 170:e95d10626187 1539 #define _SDIO_CTRL_TXDLYMUXSEL_MASK 0x30000UL /**< Bit mask for SDIO_TXDLYMUXSEL */
AnnaBridge 170:e95d10626187 1540 #define _SDIO_CTRL_TXDLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1541 #define SDIO_CTRL_TXDLYMUXSEL_DEFAULT (_SDIO_CTRL_TXDLYMUXSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CTRL */
AnnaBridge 170:e95d10626187 1542
AnnaBridge 170:e95d10626187 1543 /* Bit fields for SDIO CFG0 */
AnnaBridge 170:e95d10626187 1544 #define _SDIO_CFG0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1545 #define _SDIO_CFG0_MASK 0x7FFFFFFFUL /**< Mask for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1546 #define _SDIO_CFG0_TUNINGCNT_SHIFT 0 /**< Shift value for SDIO_TUNINGCNT */
AnnaBridge 170:e95d10626187 1547 #define _SDIO_CFG0_TUNINGCNT_MASK 0x3FUL /**< Bit mask for SDIO_TUNINGCNT */
AnnaBridge 170:e95d10626187 1548 #define _SDIO_CFG0_TUNINGCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1549 #define SDIO_CFG0_TUNINGCNT_DEFAULT (_SDIO_CFG0_TUNINGCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1550 #define _SDIO_CFG0_TOUTCLKFREQ_SHIFT 6 /**< Shift value for SDIO_TOUTCLKFREQ */
AnnaBridge 170:e95d10626187 1551 #define _SDIO_CFG0_TOUTCLKFREQ_MASK 0xFC0UL /**< Bit mask for SDIO_TOUTCLKFREQ */
AnnaBridge 170:e95d10626187 1552 #define _SDIO_CFG0_TOUTCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1553 #define SDIO_CFG0_TOUTCLKFREQ_DEFAULT (_SDIO_CFG0_TOUTCLKFREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1554 #define SDIO_CFG0_TOUTCLKUNIT (0x1UL << 12) /**< Timeout Clock Unit in kHz or MHz */
AnnaBridge 170:e95d10626187 1555 #define _SDIO_CFG0_TOUTCLKUNIT_SHIFT 12 /**< Shift value for SDIO_TOUTCLKUNIT */
AnnaBridge 170:e95d10626187 1556 #define _SDIO_CFG0_TOUTCLKUNIT_MASK 0x1000UL /**< Bit mask for SDIO_TOUTCLKUNIT */
AnnaBridge 170:e95d10626187 1557 #define _SDIO_CFG0_TOUTCLKUNIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1558 #define SDIO_CFG0_TOUTCLKUNIT_DEFAULT (_SDIO_CFG0_TOUTCLKUNIT_DEFAULT << 12) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1559 #define _SDIO_CFG0_BASECLKFREQ_SHIFT 13 /**< Shift value for SDIO_BASECLKFREQ */
AnnaBridge 170:e95d10626187 1560 #define _SDIO_CFG0_BASECLKFREQ_MASK 0x1FE000UL /**< Bit mask for SDIO_BASECLKFREQ */
AnnaBridge 170:e95d10626187 1561 #define _SDIO_CFG0_BASECLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1562 #define SDIO_CFG0_BASECLKFREQ_DEFAULT (_SDIO_CFG0_BASECLKFREQ_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1563 #define _SDIO_CFG0_MAXBLKLEN_SHIFT 21 /**< Shift value for SDIO_MAXBLKLEN */
AnnaBridge 170:e95d10626187 1564 #define _SDIO_CFG0_MAXBLKLEN_MASK 0x600000UL /**< Bit mask for SDIO_MAXBLKLEN */
AnnaBridge 170:e95d10626187 1565 #define _SDIO_CFG0_MAXBLKLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1566 #define _SDIO_CFG0_MAXBLKLEN_512B 0x00000000UL /**< Mode 512B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1567 #define _SDIO_CFG0_MAXBLKLEN_1024B 0x00000001UL /**< Mode 1024B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1568 #define _SDIO_CFG0_MAXBLKLEN_2048B 0x00000002UL /**< Mode 2048B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1569 #define SDIO_CFG0_MAXBLKLEN_DEFAULT (_SDIO_CFG0_MAXBLKLEN_DEFAULT << 21) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1570 #define SDIO_CFG0_MAXBLKLEN_512B (_SDIO_CFG0_MAXBLKLEN_512B << 21) /**< Shifted mode 512B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1571 #define SDIO_CFG0_MAXBLKLEN_1024B (_SDIO_CFG0_MAXBLKLEN_1024B << 21) /**< Shifted mode 1024B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1572 #define SDIO_CFG0_MAXBLKLEN_2048B (_SDIO_CFG0_MAXBLKLEN_2048B << 21) /**< Shifted mode 2048B for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1573 #define SDIO_CFG0_C8BITSUP (0x1UL << 23) /**< 8-bit interface support */
AnnaBridge 170:e95d10626187 1574 #define _SDIO_CFG0_C8BITSUP_SHIFT 23 /**< Shift value for SDIO_C8BITSUP */
AnnaBridge 170:e95d10626187 1575 #define _SDIO_CFG0_C8BITSUP_MASK 0x800000UL /**< Bit mask for SDIO_C8BITSUP */
AnnaBridge 170:e95d10626187 1576 #define _SDIO_CFG0_C8BITSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1577 #define SDIO_CFG0_C8BITSUP_DEFAULT (_SDIO_CFG0_C8BITSUP_DEFAULT << 23) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1578 #define SDIO_CFG0_CADMA2SUP (0x1UL << 24) /**< ADMA2 mode support */
AnnaBridge 170:e95d10626187 1579 #define _SDIO_CFG0_CADMA2SUP_SHIFT 24 /**< Shift value for SDIO_CADMA2SUP */
AnnaBridge 170:e95d10626187 1580 #define _SDIO_CFG0_CADMA2SUP_MASK 0x1000000UL /**< Bit mask for SDIO_CADMA2SUP */
AnnaBridge 170:e95d10626187 1581 #define _SDIO_CFG0_CADMA2SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1582 #define SDIO_CFG0_CADMA2SUP_DEFAULT (_SDIO_CFG0_CADMA2SUP_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1583 #define SDIO_CFG0_CHSSUP (0x1UL << 25) /**< High Speed mode support */
AnnaBridge 170:e95d10626187 1584 #define _SDIO_CFG0_CHSSUP_SHIFT 25 /**< Shift value for SDIO_CHSSUP */
AnnaBridge 170:e95d10626187 1585 #define _SDIO_CFG0_CHSSUP_MASK 0x2000000UL /**< Bit mask for SDIO_CHSSUP */
AnnaBridge 170:e95d10626187 1586 #define _SDIO_CFG0_CHSSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1587 #define SDIO_CFG0_CHSSUP_DEFAULT (_SDIO_CFG0_CHSSUP_DEFAULT << 25) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1588 #define SDIO_CFG0_CSDMASUP (0x1UL << 26) /**< SDMA mode support */
AnnaBridge 170:e95d10626187 1589 #define _SDIO_CFG0_CSDMASUP_SHIFT 26 /**< Shift value for SDIO_CSDMASUP */
AnnaBridge 170:e95d10626187 1590 #define _SDIO_CFG0_CSDMASUP_MASK 0x4000000UL /**< Bit mask for SDIO_CSDMASUP */
AnnaBridge 170:e95d10626187 1591 #define _SDIO_CFG0_CSDMASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1592 #define SDIO_CFG0_CSDMASUP_DEFAULT (_SDIO_CFG0_CSDMASUP_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1593 #define SDIO_CFG0_CSUSPRESSUP (0x1UL << 27) /**< Suspend/Resume support */
AnnaBridge 170:e95d10626187 1594 #define _SDIO_CFG0_CSUSPRESSUP_SHIFT 27 /**< Shift value for SDIO_CSUSPRESSUP */
AnnaBridge 170:e95d10626187 1595 #define _SDIO_CFG0_CSUSPRESSUP_MASK 0x8000000UL /**< Bit mask for SDIO_CSUSPRESSUP */
AnnaBridge 170:e95d10626187 1596 #define _SDIO_CFG0_CSUSPRESSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1597 #define SDIO_CFG0_CSUSPRESSUP_DEFAULT (_SDIO_CFG0_CSUSPRESSUP_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1598 #define SDIO_CFG0_C3P3VSUP (0x1UL << 28) /**< Core 3P3V support */
AnnaBridge 170:e95d10626187 1599 #define _SDIO_CFG0_C3P3VSUP_SHIFT 28 /**< Shift value for SDIO_C3P3VSUP */
AnnaBridge 170:e95d10626187 1600 #define _SDIO_CFG0_C3P3VSUP_MASK 0x10000000UL /**< Bit mask for SDIO_C3P3VSUP */
AnnaBridge 170:e95d10626187 1601 #define _SDIO_CFG0_C3P3VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1602 #define SDIO_CFG0_C3P3VSUP_DEFAULT (_SDIO_CFG0_C3P3VSUP_DEFAULT << 28) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1603 #define SDIO_CFG0_C3P0VSUP (0x1UL << 29) /**< 3P0V support */
AnnaBridge 170:e95d10626187 1604 #define _SDIO_CFG0_C3P0VSUP_SHIFT 29 /**< Shift value for SDIO_C3P0VSUP */
AnnaBridge 170:e95d10626187 1605 #define _SDIO_CFG0_C3P0VSUP_MASK 0x20000000UL /**< Bit mask for SDIO_C3P0VSUP */
AnnaBridge 170:e95d10626187 1606 #define _SDIO_CFG0_C3P0VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1607 #define SDIO_CFG0_C3P0VSUP_DEFAULT (_SDIO_CFG0_C3P0VSUP_DEFAULT << 29) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1608 #define SDIO_CFG0_C1P8VSUP (0x1UL << 30) /**< 1P8V support */
AnnaBridge 170:e95d10626187 1609 #define _SDIO_CFG0_C1P8VSUP_SHIFT 30 /**< Shift value for SDIO_C1P8VSUP */
AnnaBridge 170:e95d10626187 1610 #define _SDIO_CFG0_C1P8VSUP_MASK 0x40000000UL /**< Bit mask for SDIO_C1P8VSUP */
AnnaBridge 170:e95d10626187 1611 #define _SDIO_CFG0_C1P8VSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1612 #define SDIO_CFG0_C1P8VSUP_DEFAULT (_SDIO_CFG0_C1P8VSUP_DEFAULT << 30) /**< Shifted mode DEFAULT for SDIO_CFG0 */
AnnaBridge 170:e95d10626187 1613
AnnaBridge 170:e95d10626187 1614 /* Bit fields for SDIO CFG1 */
AnnaBridge 170:e95d10626187 1615 #define _SDIO_CFG1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1616 #define _SDIO_CFG1_MASK 0x0005FFFFUL /**< Mask for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1617 #define SDIO_CFG1_ASYNCINTRSUP (0x1UL << 0) /**< Asynchronous Interrupt Support */
AnnaBridge 170:e95d10626187 1618 #define _SDIO_CFG1_ASYNCINTRSUP_SHIFT 0 /**< Shift value for SDIO_ASYNCINTRSUP */
AnnaBridge 170:e95d10626187 1619 #define _SDIO_CFG1_ASYNCINTRSUP_MASK 0x1UL /**< Bit mask for SDIO_ASYNCINTRSUP */
AnnaBridge 170:e95d10626187 1620 #define _SDIO_CFG1_ASYNCINTRSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1621 #define SDIO_CFG1_ASYNCINTRSUP_DEFAULT (_SDIO_CFG1_ASYNCINTRSUP_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1622 #define _SDIO_CFG1_SLOTTYPE_SHIFT 1 /**< Shift value for SDIO_SLOTTYPE */
AnnaBridge 170:e95d10626187 1623 #define _SDIO_CFG1_SLOTTYPE_MASK 0x6UL /**< Bit mask for SDIO_SLOTTYPE */
AnnaBridge 170:e95d10626187 1624 #define _SDIO_CFG1_SLOTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1625 #define _SDIO_CFG1_SLOTTYPE_RMSDSLOT 0x00000000UL /**< Mode RMSDSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1626 #define _SDIO_CFG1_SLOTTYPE_EMSDSLOT 0x00000001UL /**< Mode EMSDSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1627 #define _SDIO_CFG1_SLOTTYPE_SHBUSSLOT 0x00000002UL /**< Mode SHBUSSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1628 #define SDIO_CFG1_SLOTTYPE_DEFAULT (_SDIO_CFG1_SLOTTYPE_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1629 #define SDIO_CFG1_SLOTTYPE_RMSDSLOT (_SDIO_CFG1_SLOTTYPE_RMSDSLOT << 1) /**< Shifted mode RMSDSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1630 #define SDIO_CFG1_SLOTTYPE_EMSDSLOT (_SDIO_CFG1_SLOTTYPE_EMSDSLOT << 1) /**< Shifted mode EMSDSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1631 #define SDIO_CFG1_SLOTTYPE_SHBUSSLOT (_SDIO_CFG1_SLOTTYPE_SHBUSSLOT << 1) /**< Shifted mode SHBUSSLOT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1632 #define SDIO_CFG1_CSDR50SUP (0x1UL << 3) /**< Core Support SDR50 */
AnnaBridge 170:e95d10626187 1633 #define _SDIO_CFG1_CSDR50SUP_SHIFT 3 /**< Shift value for SDIO_CSDR50SUP */
AnnaBridge 170:e95d10626187 1634 #define _SDIO_CFG1_CSDR50SUP_MASK 0x8UL /**< Bit mask for SDIO_CSDR50SUP */
AnnaBridge 170:e95d10626187 1635 #define _SDIO_CFG1_CSDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1636 #define SDIO_CFG1_CSDR50SUP_DEFAULT (_SDIO_CFG1_CSDR50SUP_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1637 #define SDIO_CFG1_CSDR104SUP (0x1UL << 4) /**< Support SDR104 */
AnnaBridge 170:e95d10626187 1638 #define _SDIO_CFG1_CSDR104SUP_SHIFT 4 /**< Shift value for SDIO_CSDR104SUP */
AnnaBridge 170:e95d10626187 1639 #define _SDIO_CFG1_CSDR104SUP_MASK 0x10UL /**< Bit mask for SDIO_CSDR104SUP */
AnnaBridge 170:e95d10626187 1640 #define _SDIO_CFG1_CSDR104SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1641 #define SDIO_CFG1_CSDR104SUP_DEFAULT (_SDIO_CFG1_CSDR104SUP_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1642 #define SDIO_CFG1_CDDR50SUP (0x1UL << 5) /**< Support DDR50 */
AnnaBridge 170:e95d10626187 1643 #define _SDIO_CFG1_CDDR50SUP_SHIFT 5 /**< Shift value for SDIO_CDDR50SUP */
AnnaBridge 170:e95d10626187 1644 #define _SDIO_CFG1_CDDR50SUP_MASK 0x20UL /**< Bit mask for SDIO_CDDR50SUP */
AnnaBridge 170:e95d10626187 1645 #define _SDIO_CFG1_CDDR50SUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1646 #define SDIO_CFG1_CDDR50SUP_DEFAULT (_SDIO_CFG1_CDDR50SUP_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1647 #define SDIO_CFG1_CDRVASUP (0x1UL << 6) /**< Support Type A Driver */
AnnaBridge 170:e95d10626187 1648 #define _SDIO_CFG1_CDRVASUP_SHIFT 6 /**< Shift value for SDIO_CDRVASUP */
AnnaBridge 170:e95d10626187 1649 #define _SDIO_CFG1_CDRVASUP_MASK 0x40UL /**< Bit mask for SDIO_CDRVASUP */
AnnaBridge 170:e95d10626187 1650 #define _SDIO_CFG1_CDRVASUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1651 #define SDIO_CFG1_CDRVASUP_DEFAULT (_SDIO_CFG1_CDRVASUP_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1652 #define SDIO_CFG1_CDRVCSUP (0x1UL << 7) /**< Support Type C Driver */
AnnaBridge 170:e95d10626187 1653 #define _SDIO_CFG1_CDRVCSUP_SHIFT 7 /**< Shift value for SDIO_CDRVCSUP */
AnnaBridge 170:e95d10626187 1654 #define _SDIO_CFG1_CDRVCSUP_MASK 0x80UL /**< Bit mask for SDIO_CDRVCSUP */
AnnaBridge 170:e95d10626187 1655 #define _SDIO_CFG1_CDRVCSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1656 #define SDIO_CFG1_CDRVCSUP_DEFAULT (_SDIO_CFG1_CDRVCSUP_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1657 #define SDIO_CFG1_CDRVDSUP (0x1UL << 8) /**< Support Type D Driver */
AnnaBridge 170:e95d10626187 1658 #define _SDIO_CFG1_CDRVDSUP_SHIFT 8 /**< Shift value for SDIO_CDRVDSUP */
AnnaBridge 170:e95d10626187 1659 #define _SDIO_CFG1_CDRVDSUP_MASK 0x100UL /**< Bit mask for SDIO_CDRVDSUP */
AnnaBridge 170:e95d10626187 1660 #define _SDIO_CFG1_CDRVDSUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1661 #define SDIO_CFG1_CDRVDSUP_DEFAULT (_SDIO_CFG1_CDRVDSUP_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1662 #define _SDIO_CFG1_RETUNTMRCTL_SHIFT 9 /**< Shift value for SDIO_RETUNTMRCTL */
AnnaBridge 170:e95d10626187 1663 #define _SDIO_CFG1_RETUNTMRCTL_MASK 0x1E00UL /**< Bit mask for SDIO_RETUNTMRCTL */
AnnaBridge 170:e95d10626187 1664 #define _SDIO_CFG1_RETUNTMRCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1665 #define SDIO_CFG1_RETUNTMRCTL_DEFAULT (_SDIO_CFG1_RETUNTMRCTL_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1666 #define SDIO_CFG1_TUNSDR50 (0x1UL << 13) /**< Tuning for SDR50 */
AnnaBridge 170:e95d10626187 1667 #define _SDIO_CFG1_TUNSDR50_SHIFT 13 /**< Shift value for SDIO_TUNSDR50 */
AnnaBridge 170:e95d10626187 1668 #define _SDIO_CFG1_TUNSDR50_MASK 0x2000UL /**< Bit mask for SDIO_TUNSDR50 */
AnnaBridge 170:e95d10626187 1669 #define _SDIO_CFG1_TUNSDR50_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1670 #define SDIO_CFG1_TUNSDR50_DEFAULT (_SDIO_CFG1_TUNSDR50_DEFAULT << 13) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1671 #define _SDIO_CFG1_RETUNMODES_SHIFT 14 /**< Shift value for SDIO_RETUNMODES */
AnnaBridge 170:e95d10626187 1672 #define _SDIO_CFG1_RETUNMODES_MASK 0xC000UL /**< Bit mask for SDIO_RETUNMODES */
AnnaBridge 170:e95d10626187 1673 #define _SDIO_CFG1_RETUNMODES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1674 #define SDIO_CFG1_RETUNMODES_DEFAULT (_SDIO_CFG1_RETUNMODES_DEFAULT << 14) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1675 #define SDIO_CFG1_SPISUP (0x1UL << 16) /**< SPI Support */
AnnaBridge 170:e95d10626187 1676 #define _SDIO_CFG1_SPISUP_SHIFT 16 /**< Shift value for SDIO_SPISUP */
AnnaBridge 170:e95d10626187 1677 #define _SDIO_CFG1_SPISUP_MASK 0x10000UL /**< Bit mask for SDIO_SPISUP */
AnnaBridge 170:e95d10626187 1678 #define _SDIO_CFG1_SPISUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1679 #define SDIO_CFG1_SPISUP_DEFAULT (_SDIO_CFG1_SPISUP_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1680 #define SDIO_CFG1_ASYNCWKUPEN (0x1UL << 18) /**< asynchronous wakeup enable */
AnnaBridge 170:e95d10626187 1681 #define _SDIO_CFG1_ASYNCWKUPEN_SHIFT 18 /**< Shift value for SDIO_ASYNCWKUPEN */
AnnaBridge 170:e95d10626187 1682 #define _SDIO_CFG1_ASYNCWKUPEN_MASK 0x40000UL /**< Bit mask for SDIO_ASYNCWKUPEN */
AnnaBridge 170:e95d10626187 1683 #define _SDIO_CFG1_ASYNCWKUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1684 #define SDIO_CFG1_ASYNCWKUPEN_DEFAULT (_SDIO_CFG1_ASYNCWKUPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SDIO_CFG1 */
AnnaBridge 170:e95d10626187 1685
AnnaBridge 170:e95d10626187 1686 /* Bit fields for SDIO CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1687 #define _SDIO_CFGPRESETVAL0_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1688 #define _SDIO_CFGPRESETVAL0_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1689 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_INITSDCLKFREQ */
AnnaBridge 170:e95d10626187 1690 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_INITSDCLKFREQ */
AnnaBridge 170:e95d10626187 1691 #define _SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1692 #define SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1693 #define SDIO_CFGPRESETVAL0_INITCLKGENEN (0x1UL << 10) /**< Initial Clock Gen Enable */
AnnaBridge 170:e95d10626187 1694 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_SHIFT 10 /**< Shift value for SDIO_INITCLKGENEN */
AnnaBridge 170:e95d10626187 1695 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_INITCLKGENEN */
AnnaBridge 170:e95d10626187 1696 #define _SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1697 #define SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1698 #define _SDIO_CFGPRESETVAL0_INITDRVST_SHIFT 11 /**< Shift value for SDIO_INITDRVST */
AnnaBridge 170:e95d10626187 1699 #define _SDIO_CFGPRESETVAL0_INITDRVST_MASK 0x1800UL /**< Bit mask for SDIO_INITDRVST */
AnnaBridge 170:e95d10626187 1700 #define _SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1701 #define SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1702 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DSPSDCLKFREQ */
AnnaBridge 170:e95d10626187 1703 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DSPSDCLKFREQ */
AnnaBridge 170:e95d10626187 1704 #define _SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1705 #define SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1706 #define SDIO_CFGPRESETVAL0_DSPCLKGENEN (0x1UL << 26) /**< Default Speed Clock Gen Enable */
AnnaBridge 170:e95d10626187 1707 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_SHIFT 26 /**< Shift value for SDIO_DSPCLKGENEN */
AnnaBridge 170:e95d10626187 1708 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DSPCLKGENEN */
AnnaBridge 170:e95d10626187 1709 #define _SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1710 #define SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1711 #define _SDIO_CFGPRESETVAL0_DSPDRVST_SHIFT 27 /**< Shift value for SDIO_DSPDRVST */
AnnaBridge 170:e95d10626187 1712 #define _SDIO_CFGPRESETVAL0_DSPDRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DSPDRVST */
AnnaBridge 170:e95d10626187 1713 #define _SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1714 #define SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL0 */
AnnaBridge 170:e95d10626187 1715
AnnaBridge 170:e95d10626187 1716 /* Bit fields for SDIO CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1717 #define _SDIO_CFGPRESETVAL1_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1718 #define _SDIO_CFGPRESETVAL1_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1719 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_HSPSDCLKFREQ */
AnnaBridge 170:e95d10626187 1720 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_HSPSDCLKFREQ */
AnnaBridge 170:e95d10626187 1721 #define _SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1722 #define SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1723 #define SDIO_CFGPRESETVAL1_HSPCLKGENEN (0x1UL << 10) /**< High Speed SD_CLK Gen Enable */
AnnaBridge 170:e95d10626187 1724 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_SHIFT 10 /**< Shift value for SDIO_HSPCLKGENEN */
AnnaBridge 170:e95d10626187 1725 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_HSPCLKGENEN */
AnnaBridge 170:e95d10626187 1726 #define _SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1727 #define SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1728 #define _SDIO_CFGPRESETVAL1_HSPDRVST_SHIFT 11 /**< Shift value for SDIO_HSPDRVST */
AnnaBridge 170:e95d10626187 1729 #define _SDIO_CFGPRESETVAL1_HSPDRVST_MASK 0x1800UL /**< Bit mask for SDIO_HSPDRVST */
AnnaBridge 170:e95d10626187 1730 #define _SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1731 #define SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT (_SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1732 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR12SDCLKFREQ */
AnnaBridge 170:e95d10626187 1733 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR12SDCLKFREQ */
AnnaBridge 170:e95d10626187 1734 #define _SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1735 #define SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1736 #define SDIO_CFGPRESETVAL1_SDR12CLKGENEN (0x1UL << 26) /**< SDR12 Speed Clock Gen Enable */
AnnaBridge 170:e95d10626187 1737 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR12CLKGENEN */
AnnaBridge 170:e95d10626187 1738 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR12CLKGENEN */
AnnaBridge 170:e95d10626187 1739 #define _SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1740 #define SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1741 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_SHIFT 27 /**< Shift value for SDIO_SDR12DRVST */
AnnaBridge 170:e95d10626187 1742 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR12DRVST */
AnnaBridge 170:e95d10626187 1743 #define _SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1744 #define SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT (_SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL1 */
AnnaBridge 170:e95d10626187 1745
AnnaBridge 170:e95d10626187 1746 /* Bit fields for SDIO CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1747 #define _SDIO_CFGPRESETVAL2_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1748 #define _SDIO_CFGPRESETVAL2_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1749 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR25SDCLKFREQ */
AnnaBridge 170:e95d10626187 1750 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR25SDCLKFREQ */
AnnaBridge 170:e95d10626187 1751 #define _SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1752 #define SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1753 #define SDIO_CFGPRESETVAL2_SDR25CLKGENEN (0x1UL << 10) /**< SDR25 SD_CLK Gen Enable */
AnnaBridge 170:e95d10626187 1754 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR25CLKGENEN */
AnnaBridge 170:e95d10626187 1755 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR25CLKGENEN */
AnnaBridge 170:e95d10626187 1756 #define _SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1757 #define SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1758 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_SHIFT 11 /**< Shift value for SDIO_SDR25DRVST */
AnnaBridge 170:e95d10626187 1759 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR25DRVST */
AnnaBridge 170:e95d10626187 1760 #define _SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1761 #define SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1762 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_SDR50SDCLKFREQ */
AnnaBridge 170:e95d10626187 1763 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_SDR50SDCLKFREQ */
AnnaBridge 170:e95d10626187 1764 #define _SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1765 #define SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1766 #define SDIO_CFGPRESETVAL2_SDR50CLKGENEN (0x1UL << 26) /**< SDR50 Speed Clock Gen Enable */
AnnaBridge 170:e95d10626187 1767 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_SDR50CLKGENEN */
AnnaBridge 170:e95d10626187 1768 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_SDR50CLKGENEN */
AnnaBridge 170:e95d10626187 1769 #define _SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1770 #define SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1771 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_SHIFT 27 /**< Shift value for SDIO_SDR50DRVST */
AnnaBridge 170:e95d10626187 1772 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_SDR50DRVST */
AnnaBridge 170:e95d10626187 1773 #define _SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1774 #define SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL2 */
AnnaBridge 170:e95d10626187 1775
AnnaBridge 170:e95d10626187 1776 /* Bit fields for SDIO CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1777 #define _SDIO_CFGPRESETVAL3_RESETVALUE 0x00000000UL /**< Default value for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1778 #define _SDIO_CFGPRESETVAL3_MASK 0x1FFF1FFFUL /**< Mask for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1779 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_SHIFT 0 /**< Shift value for SDIO_SDR104SDCLKFREQ */
AnnaBridge 170:e95d10626187 1780 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_MASK 0x3FFUL /**< Bit mask for SDIO_SDR104SDCLKFREQ */
AnnaBridge 170:e95d10626187 1781 #define _SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1782 #define SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1783 #define SDIO_CFGPRESETVAL3_SDR104CLKGENEN (0x1UL << 10) /**< SDR104 SD_CLK Gen Enable */
AnnaBridge 170:e95d10626187 1784 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_SHIFT 10 /**< Shift value for SDIO_SDR104CLKGENEN */
AnnaBridge 170:e95d10626187 1785 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_MASK 0x400UL /**< Bit mask for SDIO_SDR104CLKGENEN */
AnnaBridge 170:e95d10626187 1786 #define _SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1787 #define SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1788 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_SHIFT 11 /**< Shift value for SDIO_SDR104DRVST */
AnnaBridge 170:e95d10626187 1789 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_MASK 0x1800UL /**< Bit mask for SDIO_SDR104DRVST */
AnnaBridge 170:e95d10626187 1790 #define _SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1791 #define SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT << 11) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1792 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_SHIFT 16 /**< Shift value for SDIO_DDR50SDCLKFREQ */
AnnaBridge 170:e95d10626187 1793 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_MASK 0x3FF0000UL /**< Bit mask for SDIO_DDR50SDCLKFREQ */
AnnaBridge 170:e95d10626187 1794 #define _SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1795 #define SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1796 #define SDIO_CFGPRESETVAL3_DDR50CLKGENEN (0x1UL << 26) /**< DDR50 Speed Clock Gen Enable */
AnnaBridge 170:e95d10626187 1797 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_SHIFT 26 /**< Shift value for SDIO_DDR50CLKGENEN */
AnnaBridge 170:e95d10626187 1798 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_MASK 0x4000000UL /**< Bit mask for SDIO_DDR50CLKGENEN */
AnnaBridge 170:e95d10626187 1799 #define _SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1800 #define SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT << 26) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1801 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_SHIFT 27 /**< Shift value for SDIO_DDR50DRVST */
AnnaBridge 170:e95d10626187 1802 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_MASK 0x18000000UL /**< Bit mask for SDIO_DDR50DRVST */
AnnaBridge 170:e95d10626187 1803 #define _SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1804 #define SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT (_SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT << 27) /**< Shifted mode DEFAULT for SDIO_CFGPRESETVAL3 */
AnnaBridge 170:e95d10626187 1805
AnnaBridge 170:e95d10626187 1806 /* Bit fields for SDIO ROUTELOC0 */
AnnaBridge 170:e95d10626187 1807 #define _SDIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1808 #define _SDIO_ROUTELOC0_MASK 0x01030301UL /**< Mask for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1809 #define _SDIO_ROUTELOC0_DATLOC_SHIFT 0 /**< Shift value for SDIO_DATLOC */
AnnaBridge 170:e95d10626187 1810 #define _SDIO_ROUTELOC0_DATLOC_MASK 0x1UL /**< Bit mask for SDIO_DATLOC */
AnnaBridge 170:e95d10626187 1811 #define _SDIO_ROUTELOC0_DATLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1812 #define _SDIO_ROUTELOC0_DATLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1813 #define _SDIO_ROUTELOC0_DATLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1814 #define SDIO_ROUTELOC0_DATLOC_LOC0 (_SDIO_ROUTELOC0_DATLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1815 #define SDIO_ROUTELOC0_DATLOC_DEFAULT (_SDIO_ROUTELOC0_DATLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1816 #define SDIO_ROUTELOC0_DATLOC_LOC1 (_SDIO_ROUTELOC0_DATLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1817 #define _SDIO_ROUTELOC0_CDLOC_SHIFT 8 /**< Shift value for SDIO_CDLOC */
AnnaBridge 170:e95d10626187 1818 #define _SDIO_ROUTELOC0_CDLOC_MASK 0x300UL /**< Bit mask for SDIO_CDLOC */
AnnaBridge 170:e95d10626187 1819 #define _SDIO_ROUTELOC0_CDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1820 #define _SDIO_ROUTELOC0_CDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1821 #define _SDIO_ROUTELOC0_CDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1822 #define _SDIO_ROUTELOC0_CDLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1823 #define _SDIO_ROUTELOC0_CDLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1824 #define SDIO_ROUTELOC0_CDLOC_LOC0 (_SDIO_ROUTELOC0_CDLOC_LOC0 << 8) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1825 #define SDIO_ROUTELOC0_CDLOC_DEFAULT (_SDIO_ROUTELOC0_CDLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1826 #define SDIO_ROUTELOC0_CDLOC_LOC1 (_SDIO_ROUTELOC0_CDLOC_LOC1 << 8) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1827 #define SDIO_ROUTELOC0_CDLOC_LOC2 (_SDIO_ROUTELOC0_CDLOC_LOC2 << 8) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1828 #define SDIO_ROUTELOC0_CDLOC_LOC3 (_SDIO_ROUTELOC0_CDLOC_LOC3 << 8) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1829 #define _SDIO_ROUTELOC0_WPLOC_SHIFT 16 /**< Shift value for SDIO_WPLOC */
AnnaBridge 170:e95d10626187 1830 #define _SDIO_ROUTELOC0_WPLOC_MASK 0x30000UL /**< Bit mask for SDIO_WPLOC */
AnnaBridge 170:e95d10626187 1831 #define _SDIO_ROUTELOC0_WPLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1832 #define _SDIO_ROUTELOC0_WPLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1833 #define _SDIO_ROUTELOC0_WPLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1834 #define _SDIO_ROUTELOC0_WPLOC_LOC2 0x00000002UL /**< Mode LOC2 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1835 #define _SDIO_ROUTELOC0_WPLOC_LOC3 0x00000003UL /**< Mode LOC3 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1836 #define SDIO_ROUTELOC0_WPLOC_LOC0 (_SDIO_ROUTELOC0_WPLOC_LOC0 << 16) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1837 #define SDIO_ROUTELOC0_WPLOC_DEFAULT (_SDIO_ROUTELOC0_WPLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1838 #define SDIO_ROUTELOC0_WPLOC_LOC1 (_SDIO_ROUTELOC0_WPLOC_LOC1 << 16) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1839 #define SDIO_ROUTELOC0_WPLOC_LOC2 (_SDIO_ROUTELOC0_WPLOC_LOC2 << 16) /**< Shifted mode LOC2 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1840 #define SDIO_ROUTELOC0_WPLOC_LOC3 (_SDIO_ROUTELOC0_WPLOC_LOC3 << 16) /**< Shifted mode LOC3 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1841 #define _SDIO_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for SDIO_CLKLOC */
AnnaBridge 170:e95d10626187 1842 #define _SDIO_ROUTELOC0_CLKLOC_MASK 0x1000000UL /**< Bit mask for SDIO_CLKLOC */
AnnaBridge 170:e95d10626187 1843 #define _SDIO_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1844 #define _SDIO_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1845 #define _SDIO_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1846 #define SDIO_ROUTELOC0_CLKLOC_LOC0 (_SDIO_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1847 #define SDIO_ROUTELOC0_CLKLOC_DEFAULT (_SDIO_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1848 #define SDIO_ROUTELOC0_CLKLOC_LOC1 (_SDIO_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for SDIO_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1849
AnnaBridge 170:e95d10626187 1850 /* Bit fields for SDIO ROUTELOC1 */
AnnaBridge 170:e95d10626187 1851 #define _SDIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1852 #define _SDIO_ROUTELOC1_MASK 0x00000001UL /**< Mask for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1853 #define _SDIO_ROUTELOC1_CMDLOC_SHIFT 0 /**< Shift value for SDIO_CMDLOC */
AnnaBridge 170:e95d10626187 1854 #define _SDIO_ROUTELOC1_CMDLOC_MASK 0x1UL /**< Bit mask for SDIO_CMDLOC */
AnnaBridge 170:e95d10626187 1855 #define _SDIO_ROUTELOC1_CMDLOC_LOC0 0x00000000UL /**< Mode LOC0 for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1856 #define _SDIO_ROUTELOC1_CMDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1857 #define _SDIO_ROUTELOC1_CMDLOC_LOC1 0x00000001UL /**< Mode LOC1 for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1858 #define SDIO_ROUTELOC1_CMDLOC_LOC0 (_SDIO_ROUTELOC1_CMDLOC_LOC0 << 0) /**< Shifted mode LOC0 for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1859 #define SDIO_ROUTELOC1_CMDLOC_DEFAULT (_SDIO_ROUTELOC1_CMDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1860 #define SDIO_ROUTELOC1_CMDLOC_LOC1 (_SDIO_ROUTELOC1_CMDLOC_LOC1 << 0) /**< Shifted mode LOC1 for SDIO_ROUTELOC1 */
AnnaBridge 170:e95d10626187 1861
AnnaBridge 170:e95d10626187 1862 /* Bit fields for SDIO ROUTEPEN */
AnnaBridge 170:e95d10626187 1863 #define _SDIO_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1864 #define _SDIO_ROUTEPEN_MASK 0x000003FFUL /**< Mask for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1865 #define SDIO_ROUTEPEN_CLKPEN (0x1UL << 0) /**< CLK I/O Enable */
AnnaBridge 170:e95d10626187 1866 #define _SDIO_ROUTEPEN_CLKPEN_SHIFT 0 /**< Shift value for SDIO_CLKPEN */
AnnaBridge 170:e95d10626187 1867 #define _SDIO_ROUTEPEN_CLKPEN_MASK 0x1UL /**< Bit mask for SDIO_CLKPEN */
AnnaBridge 170:e95d10626187 1868 #define _SDIO_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1869 #define SDIO_ROUTEPEN_CLKPEN_DEFAULT (_SDIO_ROUTEPEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1870 #define SDIO_ROUTEPEN_CMDPEN (0x1UL << 1) /**< CMD I/O Enable */
AnnaBridge 170:e95d10626187 1871 #define _SDIO_ROUTEPEN_CMDPEN_SHIFT 1 /**< Shift value for SDIO_CMDPEN */
AnnaBridge 170:e95d10626187 1872 #define _SDIO_ROUTEPEN_CMDPEN_MASK 0x2UL /**< Bit mask for SDIO_CMDPEN */
AnnaBridge 170:e95d10626187 1873 #define _SDIO_ROUTEPEN_CMDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1874 #define SDIO_ROUTEPEN_CMDPEN_DEFAULT (_SDIO_ROUTEPEN_CMDPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1875 #define SDIO_ROUTEPEN_D0PEN (0x1UL << 2) /**< Dat0 I/O Enable */
AnnaBridge 170:e95d10626187 1876 #define _SDIO_ROUTEPEN_D0PEN_SHIFT 2 /**< Shift value for SDIO_D0PEN */
AnnaBridge 170:e95d10626187 1877 #define _SDIO_ROUTEPEN_D0PEN_MASK 0x4UL /**< Bit mask for SDIO_D0PEN */
AnnaBridge 170:e95d10626187 1878 #define _SDIO_ROUTEPEN_D0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1879 #define SDIO_ROUTEPEN_D0PEN_DEFAULT (_SDIO_ROUTEPEN_D0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1880 #define SDIO_ROUTEPEN_D1PEN (0x1UL << 3) /**< Dat1 I/O Enable */
AnnaBridge 170:e95d10626187 1881 #define _SDIO_ROUTEPEN_D1PEN_SHIFT 3 /**< Shift value for SDIO_D1PEN */
AnnaBridge 170:e95d10626187 1882 #define _SDIO_ROUTEPEN_D1PEN_MASK 0x8UL /**< Bit mask for SDIO_D1PEN */
AnnaBridge 170:e95d10626187 1883 #define _SDIO_ROUTEPEN_D1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1884 #define SDIO_ROUTEPEN_D1PEN_DEFAULT (_SDIO_ROUTEPEN_D1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1885 #define SDIO_ROUTEPEN_D2PEN (0x1UL << 4) /**< Dat2 I/O Enable */
AnnaBridge 170:e95d10626187 1886 #define _SDIO_ROUTEPEN_D2PEN_SHIFT 4 /**< Shift value for SDIO_D2PEN */
AnnaBridge 170:e95d10626187 1887 #define _SDIO_ROUTEPEN_D2PEN_MASK 0x10UL /**< Bit mask for SDIO_D2PEN */
AnnaBridge 170:e95d10626187 1888 #define _SDIO_ROUTEPEN_D2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1889 #define SDIO_ROUTEPEN_D2PEN_DEFAULT (_SDIO_ROUTEPEN_D2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1890 #define SDIO_ROUTEPEN_D3PEN (0x1UL << 5) /**< Dat3 I/O Enable */
AnnaBridge 170:e95d10626187 1891 #define _SDIO_ROUTEPEN_D3PEN_SHIFT 5 /**< Shift value for SDIO_D3PEN */
AnnaBridge 170:e95d10626187 1892 #define _SDIO_ROUTEPEN_D3PEN_MASK 0x20UL /**< Bit mask for SDIO_D3PEN */
AnnaBridge 170:e95d10626187 1893 #define _SDIO_ROUTEPEN_D3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1894 #define SDIO_ROUTEPEN_D3PEN_DEFAULT (_SDIO_ROUTEPEN_D3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1895 #define SDIO_ROUTEPEN_D4PEN (0x1UL << 6) /**< Dat4 I/O Enable */
AnnaBridge 170:e95d10626187 1896 #define _SDIO_ROUTEPEN_D4PEN_SHIFT 6 /**< Shift value for SDIO_D4PEN */
AnnaBridge 170:e95d10626187 1897 #define _SDIO_ROUTEPEN_D4PEN_MASK 0x40UL /**< Bit mask for SDIO_D4PEN */
AnnaBridge 170:e95d10626187 1898 #define _SDIO_ROUTEPEN_D4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1899 #define SDIO_ROUTEPEN_D4PEN_DEFAULT (_SDIO_ROUTEPEN_D4PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1900 #define SDIO_ROUTEPEN_D5PEN (0x1UL << 7) /**< Dat5 Enable */
AnnaBridge 170:e95d10626187 1901 #define _SDIO_ROUTEPEN_D5PEN_SHIFT 7 /**< Shift value for SDIO_D5PEN */
AnnaBridge 170:e95d10626187 1902 #define _SDIO_ROUTEPEN_D5PEN_MASK 0x80UL /**< Bit mask for SDIO_D5PEN */
AnnaBridge 170:e95d10626187 1903 #define _SDIO_ROUTEPEN_D5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1904 #define SDIO_ROUTEPEN_D5PEN_DEFAULT (_SDIO_ROUTEPEN_D5PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1905 #define SDIO_ROUTEPEN_D6PEN (0x1UL << 8) /**< Dat6 Enable */
AnnaBridge 170:e95d10626187 1906 #define _SDIO_ROUTEPEN_D6PEN_SHIFT 8 /**< Shift value for SDIO_D6PEN */
AnnaBridge 170:e95d10626187 1907 #define _SDIO_ROUTEPEN_D6PEN_MASK 0x100UL /**< Bit mask for SDIO_D6PEN */
AnnaBridge 170:e95d10626187 1908 #define _SDIO_ROUTEPEN_D6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1909 #define SDIO_ROUTEPEN_D6PEN_DEFAULT (_SDIO_ROUTEPEN_D6PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1910 #define SDIO_ROUTEPEN_D7PEN (0x1UL << 9) /**< Data7 I/O Enable */
AnnaBridge 170:e95d10626187 1911 #define _SDIO_ROUTEPEN_D7PEN_SHIFT 9 /**< Shift value for SDIO_D7PEN */
AnnaBridge 170:e95d10626187 1912 #define _SDIO_ROUTEPEN_D7PEN_MASK 0x200UL /**< Bit mask for SDIO_D7PEN */
AnnaBridge 170:e95d10626187 1913 #define _SDIO_ROUTEPEN_D7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1914 #define SDIO_ROUTEPEN_D7PEN_DEFAULT (_SDIO_ROUTEPEN_D7PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SDIO_ROUTEPEN */
AnnaBridge 170:e95d10626187 1915
AnnaBridge 170:e95d10626187 1916 /** @} */
AnnaBridge 170:e95d10626187 1917 /** @} End of group EFM32GG11B_SDIO */
AnnaBridge 170:e95d10626187 1918 /** @} End of group Parts */