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TARGET_EFM32GG11_STK3701/TOOLCHAIN_IAR/efm32gg11b_ldma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_ldma.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_LDMA register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43 /**************************************************************************//**
AnnaBridge 170:e95d10626187 44 * @defgroup EFM32GG11B_LDMA LDMA
AnnaBridge 170:e95d10626187 45 * @{
AnnaBridge 170:e95d10626187 46 * @brief EFM32GG11B_LDMA Register Declaration
AnnaBridge 170:e95d10626187 47 *****************************************************************************/
AnnaBridge 170:e95d10626187 48 /** LDMA Register Declaration */
AnnaBridge 170:e95d10626187 49 typedef struct {
AnnaBridge 170:e95d10626187 50 __IOM uint32_t CTRL; /**< DMA Control Register */
AnnaBridge 170:e95d10626187 51 __IM uint32_t STATUS; /**< DMA Status Register */
AnnaBridge 170:e95d10626187 52 __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
AnnaBridge 170:e95d10626187 53 uint32_t RESERVED0[5]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 54 __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
AnnaBridge 170:e95d10626187 55 __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
AnnaBridge 170:e95d10626187 56 __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
AnnaBridge 170:e95d10626187 57 __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
AnnaBridge 170:e95d10626187 58 __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
AnnaBridge 170:e95d10626187 59 __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
AnnaBridge 170:e95d10626187 60 __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
AnnaBridge 170:e95d10626187 61 __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
AnnaBridge 170:e95d10626187 62 __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
AnnaBridge 170:e95d10626187 63 uint32_t RESERVED1[7]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 64 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 170:e95d10626187 65 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 170:e95d10626187 66 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 170:e95d10626187 67 __IOM uint32_t IEN; /**< Interrupt Enable register */
AnnaBridge 170:e95d10626187 68
AnnaBridge 170:e95d10626187 69 uint32_t RESERVED2[4]; /**< Reserved registers */
AnnaBridge 170:e95d10626187 70 LDMA_CH_TypeDef CH[24]; /**< DMA Channel Registers */
AnnaBridge 170:e95d10626187 71 } LDMA_TypeDef; /** @} */
AnnaBridge 170:e95d10626187 72
AnnaBridge 170:e95d10626187 73 /**************************************************************************//**
AnnaBridge 170:e95d10626187 74 * @addtogroup EFM32GG11B_LDMA
AnnaBridge 170:e95d10626187 75 * @{
AnnaBridge 170:e95d10626187 76 * @defgroup EFM32GG11B_LDMA_BitFields LDMA Bit Fields
AnnaBridge 170:e95d10626187 77 * @{
AnnaBridge 170:e95d10626187 78 *****************************************************************************/
AnnaBridge 170:e95d10626187 79
AnnaBridge 170:e95d10626187 80 /* Bit fields for LDMA CTRL */
AnnaBridge 170:e95d10626187 81 #define _LDMA_CTRL_RESETVALUE 0x17000000UL /**< Default value for LDMA_CTRL */
AnnaBridge 170:e95d10626187 82 #define _LDMA_CTRL_MASK 0x1F00FFFFUL /**< Mask for LDMA_CTRL */
AnnaBridge 170:e95d10626187 83 #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
AnnaBridge 170:e95d10626187 84 #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
AnnaBridge 170:e95d10626187 85 #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 86 #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 87 #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
AnnaBridge 170:e95d10626187 88 #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
AnnaBridge 170:e95d10626187 89 #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 90 #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 91 #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
AnnaBridge 170:e95d10626187 92 #define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */
AnnaBridge 170:e95d10626187 93 #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000017UL /**< Mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 94 #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
AnnaBridge 170:e95d10626187 95
AnnaBridge 170:e95d10626187 96 /* Bit fields for LDMA STATUS */
AnnaBridge 170:e95d10626187 97 #define _LDMA_STATUS_RESETVALUE 0x18100000UL /**< Default value for LDMA_STATUS */
AnnaBridge 170:e95d10626187 98 #define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */
AnnaBridge 170:e95d10626187 99 #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
AnnaBridge 170:e95d10626187 100 #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
AnnaBridge 170:e95d10626187 101 #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
AnnaBridge 170:e95d10626187 102 #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 103 #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 104 #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
AnnaBridge 170:e95d10626187 105 #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
AnnaBridge 170:e95d10626187 106 #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
AnnaBridge 170:e95d10626187 107 #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 108 #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 109 #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
AnnaBridge 170:e95d10626187 110 #define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */
AnnaBridge 170:e95d10626187 111 #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 112 #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 113 #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
AnnaBridge 170:e95d10626187 114 #define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */
AnnaBridge 170:e95d10626187 115 #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 116 #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 117 #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
AnnaBridge 170:e95d10626187 118 #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
AnnaBridge 170:e95d10626187 119 #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 120 #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 121 #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
AnnaBridge 170:e95d10626187 122 #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
AnnaBridge 170:e95d10626187 123 #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000018UL /**< Mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 124 #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
AnnaBridge 170:e95d10626187 125
AnnaBridge 170:e95d10626187 126 /* Bit fields for LDMA SYNC */
AnnaBridge 170:e95d10626187 127 #define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
AnnaBridge 170:e95d10626187 128 #define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
AnnaBridge 170:e95d10626187 129 #define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
AnnaBridge 170:e95d10626187 130 #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
AnnaBridge 170:e95d10626187 131 #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
AnnaBridge 170:e95d10626187 132 #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
AnnaBridge 170:e95d10626187 133
AnnaBridge 170:e95d10626187 134 /* Bit fields for LDMA CHEN */
AnnaBridge 170:e95d10626187 135 #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
AnnaBridge 170:e95d10626187 136 #define _LDMA_CHEN_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHEN */
AnnaBridge 170:e95d10626187 137 #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
AnnaBridge 170:e95d10626187 138 #define _LDMA_CHEN_CHEN_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHEN */
AnnaBridge 170:e95d10626187 139 #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
AnnaBridge 170:e95d10626187 140 #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
AnnaBridge 170:e95d10626187 141
AnnaBridge 170:e95d10626187 142 /* Bit fields for LDMA CHBUSY */
AnnaBridge 170:e95d10626187 143 #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
AnnaBridge 170:e95d10626187 144 #define _LDMA_CHBUSY_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHBUSY */
AnnaBridge 170:e95d10626187 145 #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
AnnaBridge 170:e95d10626187 146 #define _LDMA_CHBUSY_BUSY_MASK 0xFFFFFFUL /**< Bit mask for LDMA_BUSY */
AnnaBridge 170:e95d10626187 147 #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
AnnaBridge 170:e95d10626187 148 #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
AnnaBridge 170:e95d10626187 149
AnnaBridge 170:e95d10626187 150 /* Bit fields for LDMA CHDONE */
AnnaBridge 170:e95d10626187 151 #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 152 #define _LDMA_CHDONE_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 153 #define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 154 #define _LDMA_CHDONE_CHDONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 155 #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 156 #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
AnnaBridge 170:e95d10626187 157
AnnaBridge 170:e95d10626187 158 /* Bit fields for LDMA DBGHALT */
AnnaBridge 170:e95d10626187 159 #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 160 #define _LDMA_DBGHALT_MASK 0x00FFFFFFUL /**< Mask for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 161 #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 162 #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 163 #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 164 #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
AnnaBridge 170:e95d10626187 165
AnnaBridge 170:e95d10626187 166 /* Bit fields for LDMA SWREQ */
AnnaBridge 170:e95d10626187 167 #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 168 #define _LDMA_SWREQ_MASK 0x00FFFFFFUL /**< Mask for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 169 #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 170 #define _LDMA_SWREQ_SWREQ_MASK 0xFFFFFFUL /**< Bit mask for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 171 #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 172 #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
AnnaBridge 170:e95d10626187 173
AnnaBridge 170:e95d10626187 174 /* Bit fields for LDMA REQDIS */
AnnaBridge 170:e95d10626187 175 #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 176 #define _LDMA_REQDIS_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 177 #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 178 #define _LDMA_REQDIS_REQDIS_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 179 #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 180 #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
AnnaBridge 170:e95d10626187 181
AnnaBridge 170:e95d10626187 182 /* Bit fields for LDMA REQPEND */
AnnaBridge 170:e95d10626187 183 #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 184 #define _LDMA_REQPEND_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 185 #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 186 #define _LDMA_REQPEND_REQPEND_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 187 #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 188 #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
AnnaBridge 170:e95d10626187 189
AnnaBridge 170:e95d10626187 190 /* Bit fields for LDMA LINKLOAD */
AnnaBridge 170:e95d10626187 191 #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 192 #define _LDMA_LINKLOAD_MASK 0x00FFFFFFUL /**< Mask for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 193 #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 194 #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFFFFFUL /**< Bit mask for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 195 #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 196 #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
AnnaBridge 170:e95d10626187 197
AnnaBridge 170:e95d10626187 198 /* Bit fields for LDMA REQCLEAR */
AnnaBridge 170:e95d10626187 199 #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 200 #define _LDMA_REQCLEAR_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 201 #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 202 #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 203 #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 204 #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
AnnaBridge 170:e95d10626187 205
AnnaBridge 170:e95d10626187 206 /* Bit fields for LDMA IF */
AnnaBridge 170:e95d10626187 207 #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
AnnaBridge 170:e95d10626187 208 #define _LDMA_IF_MASK 0x80FFFFFFUL /**< Mask for LDMA_IF */
AnnaBridge 170:e95d10626187 209 #define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
AnnaBridge 170:e95d10626187 210 #define _LDMA_IF_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
AnnaBridge 170:e95d10626187 211 #define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
AnnaBridge 170:e95d10626187 212 #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
AnnaBridge 170:e95d10626187 213 #define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
AnnaBridge 170:e95d10626187 214 #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
AnnaBridge 170:e95d10626187 215 #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
AnnaBridge 170:e95d10626187 216 #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
AnnaBridge 170:e95d10626187 217 #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
AnnaBridge 170:e95d10626187 218
AnnaBridge 170:e95d10626187 219 /* Bit fields for LDMA IFS */
AnnaBridge 170:e95d10626187 220 #define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
AnnaBridge 170:e95d10626187 221 #define _LDMA_IFS_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFS */
AnnaBridge 170:e95d10626187 222 #define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
AnnaBridge 170:e95d10626187 223 #define _LDMA_IFS_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
AnnaBridge 170:e95d10626187 224 #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
AnnaBridge 170:e95d10626187 225 #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
AnnaBridge 170:e95d10626187 226 #define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
AnnaBridge 170:e95d10626187 227 #define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
AnnaBridge 170:e95d10626187 228 #define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
AnnaBridge 170:e95d10626187 229 #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
AnnaBridge 170:e95d10626187 230 #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
AnnaBridge 170:e95d10626187 231
AnnaBridge 170:e95d10626187 232 /* Bit fields for LDMA IFC */
AnnaBridge 170:e95d10626187 233 #define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
AnnaBridge 170:e95d10626187 234 #define _LDMA_IFC_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFC */
AnnaBridge 170:e95d10626187 235 #define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
AnnaBridge 170:e95d10626187 236 #define _LDMA_IFC_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
AnnaBridge 170:e95d10626187 237 #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
AnnaBridge 170:e95d10626187 238 #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
AnnaBridge 170:e95d10626187 239 #define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
AnnaBridge 170:e95d10626187 240 #define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
AnnaBridge 170:e95d10626187 241 #define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
AnnaBridge 170:e95d10626187 242 #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
AnnaBridge 170:e95d10626187 243 #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
AnnaBridge 170:e95d10626187 244
AnnaBridge 170:e95d10626187 245 /* Bit fields for LDMA IEN */
AnnaBridge 170:e95d10626187 246 #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
AnnaBridge 170:e95d10626187 247 #define _LDMA_IEN_MASK 0x80FFFFFFUL /**< Mask for LDMA_IEN */
AnnaBridge 170:e95d10626187 248 #define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
AnnaBridge 170:e95d10626187 249 #define _LDMA_IEN_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
AnnaBridge 170:e95d10626187 250 #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
AnnaBridge 170:e95d10626187 251 #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
AnnaBridge 170:e95d10626187 252 #define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
AnnaBridge 170:e95d10626187 253 #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
AnnaBridge 170:e95d10626187 254 #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
AnnaBridge 170:e95d10626187 255 #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
AnnaBridge 170:e95d10626187 256 #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
AnnaBridge 170:e95d10626187 257
AnnaBridge 170:e95d10626187 258 /* Bit fields for LDMA CH_REQSEL */
AnnaBridge 170:e95d10626187 259 #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 260 #define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 261 #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
AnnaBridge 170:e95d10626187 262 #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
AnnaBridge 170:e95d10626187 263 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 264 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 265 #define _LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 266 #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 267 #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 268 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 269 #define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 270 #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 271 #define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV 0x00000000UL /**< Mode USART4RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 272 #define _LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV 0x00000000UL /**< Mode USART5RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 273 #define _LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 274 #define _LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 275 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 276 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 277 #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 278 #define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 279 #define _LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /**< Mode I2C2RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 280 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 281 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 282 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 283 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 284 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000000UL /**< Mode TIMER4UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 285 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000000UL /**< Mode TIMER5UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 286 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000000UL /**< Mode TIMER6UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 287 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 288 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 289 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF 0x00000000UL /**< Mode WTIMER2UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 290 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF 0x00000000UL /**< Mode WTIMER3UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 291 #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 292 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 293 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 294 #define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 295 #define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 296 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 297 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 298 #define _LDMA_CH_REQSEL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 299 #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 300 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 301 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 302 #define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 303 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 304 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXBL 0x00000001UL /**< Mode USART4TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 305 #define _LDMA_CH_REQSEL_SIGSEL_USART5TXBL 0x00000001UL /**< Mode USART5TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 306 #define _LDMA_CH_REQSEL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 307 #define _LDMA_CH_REQSEL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 308 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 309 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 310 #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 311 #define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 312 #define _LDMA_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /**< Mode I2C2TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 313 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 314 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 315 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 316 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 317 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000001UL /**< Mode TIMER4CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 318 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000001UL /**< Mode TIMER5CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 319 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000001UL /**< Mode TIMER6CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 320 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 321 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 322 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 0x00000001UL /**< Mode WTIMER2CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 323 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 0x00000001UL /**< Mode WTIMER3CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 324 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 325 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 326 #define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 327 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 328 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 329 #define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 330 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 331 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY 0x00000002UL /**< Mode USART4TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 332 #define _LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY 0x00000002UL /**< Mode USART5TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 333 #define _LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 334 #define _LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 335 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 336 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 337 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 338 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 339 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 340 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 341 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000002UL /**< Mode TIMER4CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 342 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000002UL /**< Mode TIMER5CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 343 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000002UL /**< Mode TIMER6CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 344 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 345 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 346 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 0x00000002UL /**< Mode WTIMER2CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 347 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 0x00000002UL /**< Mode WTIMER3CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 348 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 349 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 350 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 351 #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 352 #define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT 0x00000003UL /**< Mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 353 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 354 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 355 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 356 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 357 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000003UL /**< Mode TIMER4CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 358 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000003UL /**< Mode TIMER5CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 359 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000003UL /**< Mode TIMER6CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 360 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 361 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 362 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 0x00000003UL /**< Mode WTIMER2CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 363 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 0x00000003UL /**< Mode WTIMER3CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 364 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 365 #define _LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 366 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 367 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 368 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT 0x00000004UL /**< Mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 369 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 370 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 371 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 372 #define _LDMA_CH_REQSEL_SIGSEL_EBIVSYNC 0x00000004UL /**< Mode EBIVSYNC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 373 #define _LDMA_CH_REQSEL_SIGSEL_EBIHSYNC 0x00000005UL /**< Mode EBIHSYNC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 374 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 375 #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 376 #define LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 377 #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 378 #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 379 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 380 #define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 381 #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 382 #define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 383 #define LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 384 #define LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 385 #define LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 386 #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 387 #define LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 388 #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 389 #define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 390 #define LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /**< Shifted mode I2C2RXDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 391 #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 392 #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 393 #define LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 394 #define LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 395 #define LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /**< Shifted mode TIMER4UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 396 #define LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /**< Shifted mode TIMER5UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 397 #define LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /**< Shifted mode TIMER6UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 398 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 399 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 400 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF << 0) /**< Shifted mode WTIMER2UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 401 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF << 0) /**< Shifted mode WTIMER3UFOF for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 402 #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 403 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 404 #define LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 405 #define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 406 #define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 407 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 408 #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 409 #define LDMA_CH_REQSEL_SIGSEL_ADC1SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 410 #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 411 #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 412 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 413 #define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 414 #define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 415 #define LDMA_CH_REQSEL_SIGSEL_USART4TXBL (_LDMA_CH_REQSEL_SIGSEL_USART4TXBL << 0) /**< Shifted mode USART4TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 416 #define LDMA_CH_REQSEL_SIGSEL_USART5TXBL (_LDMA_CH_REQSEL_SIGSEL_USART5TXBL << 0) /**< Shifted mode USART5TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 417 #define LDMA_CH_REQSEL_SIGSEL_UART0TXBL (_LDMA_CH_REQSEL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 418 #define LDMA_CH_REQSEL_SIGSEL_UART1TXBL (_LDMA_CH_REQSEL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 419 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 420 #define LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 421 #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 422 #define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 423 #define LDMA_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /**< Shifted mode I2C2TXBL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 424 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 425 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 426 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 427 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 428 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 429 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 430 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 431 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 432 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 433 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 434 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 435 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 436 #define LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 437 #define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 438 #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 439 #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 440 #define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 441 #define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 442 #define LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY << 0) /**< Shifted mode USART4TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 443 #define LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY << 0) /**< Shifted mode USART5TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 444 #define LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 445 #define LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 446 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 447 #define LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 448 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 449 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 450 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 451 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 452 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 453 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 454 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 455 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 456 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 457 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 458 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 459 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 460 #define LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL (_LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 461 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 462 #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 463 #define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT << 0) /**< Shifted mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 464 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 465 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 466 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 467 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 468 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 469 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 470 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 471 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 472 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 473 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 474 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 475 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 476 #define LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 477 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 478 #define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 479 #define LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT << 0) /**< Shifted mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 480 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 481 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 482 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 483 #define LDMA_CH_REQSEL_SIGSEL_EBIVSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIVSYNC << 0) /**< Shifted mode EBIVSYNC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 484 #define LDMA_CH_REQSEL_SIGSEL_EBIHSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIHSYNC << 0) /**< Shifted mode EBIHSYNC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 485 #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
AnnaBridge 170:e95d10626187 486 #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
AnnaBridge 170:e95d10626187 487 #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 488 #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 489 #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 490 #define _LDMA_CH_REQSEL_SOURCESEL_ADC1 0x00000009UL /**< Mode ADC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 491 #define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 492 #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 493 #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 494 #define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 495 #define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 496 #define _LDMA_CH_REQSEL_SOURCESEL_USART4 0x00000010UL /**< Mode USART4 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 497 #define _LDMA_CH_REQSEL_SOURCESEL_USART5 0x00000011UL /**< Mode USART5 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 498 #define _LDMA_CH_REQSEL_SOURCESEL_UART0 0x00000012UL /**< Mode UART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 499 #define _LDMA_CH_REQSEL_SOURCESEL_UART1 0x00000013UL /**< Mode UART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 500 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000014UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 501 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART1 0x00000015UL /**< Mode LEUART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 502 #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000016UL /**< Mode I2C0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 503 #define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000017UL /**< Mode I2C1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 504 #define _LDMA_CH_REQSEL_SOURCESEL_I2C2 0x00000018UL /**< Mode I2C2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 505 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000019UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 506 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x0000001AUL /**< Mode TIMER1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 507 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER2 0x0000001BUL /**< Mode TIMER2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 508 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER3 0x0000001CUL /**< Mode TIMER3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 509 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER4 0x0000001DUL /**< Mode TIMER4 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 510 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER5 0x0000001EUL /**< Mode TIMER5 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 511 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER6 0x0000001FUL /**< Mode TIMER6 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 512 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x00000020UL /**< Mode WTIMER0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 513 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x00000021UL /**< Mode WTIMER1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 514 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER2 0x00000022UL /**< Mode WTIMER2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 515 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER3 0x00000023UL /**< Mode WTIMER3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 516 #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 517 #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 518 #define _LDMA_CH_REQSEL_SOURCESEL_EBI 0x00000032UL /**< Mode EBI for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 519 #define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x0000003DUL /**< Mode CSEN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 520 #define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x0000003EUL /**< Mode LESENSE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 521 #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 522 #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 523 #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 524 #define LDMA_CH_REQSEL_SOURCESEL_ADC1 (_LDMA_CH_REQSEL_SOURCESEL_ADC1 << 16) /**< Shifted mode ADC1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 525 #define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 526 #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 527 #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 528 #define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 529 #define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 530 #define LDMA_CH_REQSEL_SOURCESEL_USART4 (_LDMA_CH_REQSEL_SOURCESEL_USART4 << 16) /**< Shifted mode USART4 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 531 #define LDMA_CH_REQSEL_SOURCESEL_USART5 (_LDMA_CH_REQSEL_SOURCESEL_USART5 << 16) /**< Shifted mode USART5 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 532 #define LDMA_CH_REQSEL_SOURCESEL_UART0 (_LDMA_CH_REQSEL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 533 #define LDMA_CH_REQSEL_SOURCESEL_UART1 (_LDMA_CH_REQSEL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 534 #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 535 #define LDMA_CH_REQSEL_SOURCESEL_LEUART1 (_LDMA_CH_REQSEL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 536 #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 537 #define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 538 #define LDMA_CH_REQSEL_SOURCESEL_I2C2 (_LDMA_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted mode I2C2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 539 #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 540 #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 541 #define LDMA_CH_REQSEL_SOURCESEL_TIMER2 (_LDMA_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 542 #define LDMA_CH_REQSEL_SOURCESEL_TIMER3 (_LDMA_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 543 #define LDMA_CH_REQSEL_SOURCESEL_TIMER4 (_LDMA_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted mode TIMER4 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 544 #define LDMA_CH_REQSEL_SOURCESEL_TIMER5 (_LDMA_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted mode TIMER5 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 545 #define LDMA_CH_REQSEL_SOURCESEL_TIMER6 (_LDMA_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted mode TIMER6 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 546 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 547 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 548 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER2 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER2 << 16) /**< Shifted mode WTIMER2 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 549 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER3 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER3 << 16) /**< Shifted mode WTIMER3 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 550 #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 551 #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 552 #define LDMA_CH_REQSEL_SOURCESEL_EBI (_LDMA_CH_REQSEL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 553 #define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 554 #define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */
AnnaBridge 170:e95d10626187 555
AnnaBridge 170:e95d10626187 556 /* Bit fields for LDMA CH_CFG */
AnnaBridge 170:e95d10626187 557 #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 558 #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 559 #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
AnnaBridge 170:e95d10626187 560 #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
AnnaBridge 170:e95d10626187 561 #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 562 #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 563 #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 564 #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 565 #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 566 #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 567 #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 568 #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 569 #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 570 #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 571 #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
AnnaBridge 170:e95d10626187 572 #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
AnnaBridge 170:e95d10626187 573 #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
AnnaBridge 170:e95d10626187 574 #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 575 #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 576 #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 577 #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 578 #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 579 #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 580 #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
AnnaBridge 170:e95d10626187 581 #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
AnnaBridge 170:e95d10626187 582 #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
AnnaBridge 170:e95d10626187 583 #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 584 #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 585 #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 586 #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 587 #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 588 #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
AnnaBridge 170:e95d10626187 589
AnnaBridge 170:e95d10626187 590 /* Bit fields for LDMA CH_LOOP */
AnnaBridge 170:e95d10626187 591 #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
AnnaBridge 170:e95d10626187 592 #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
AnnaBridge 170:e95d10626187 593 #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
AnnaBridge 170:e95d10626187 594 #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
AnnaBridge 170:e95d10626187 595 #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
AnnaBridge 170:e95d10626187 596 #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
AnnaBridge 170:e95d10626187 597
AnnaBridge 170:e95d10626187 598 /* Bit fields for LDMA CH_CTRL */
AnnaBridge 170:e95d10626187 599 #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 600 #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 601 #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
AnnaBridge 170:e95d10626187 602 #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
AnnaBridge 170:e95d10626187 603 #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 604 #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 605 #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 606 #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 607 #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 608 #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 609 #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 610 #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 611 #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
AnnaBridge 170:e95d10626187 612 #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
AnnaBridge 170:e95d10626187 613 #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
AnnaBridge 170:e95d10626187 614 #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 615 #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 616 #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
AnnaBridge 170:e95d10626187 617 #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
AnnaBridge 170:e95d10626187 618 #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 619 #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 620 #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
AnnaBridge 170:e95d10626187 621 #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
AnnaBridge 170:e95d10626187 622 #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
AnnaBridge 170:e95d10626187 623 #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 624 #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 625 #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
AnnaBridge 170:e95d10626187 626 #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
AnnaBridge 170:e95d10626187 627 #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 628 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 629 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 630 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 631 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 632 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 633 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 634 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 635 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 636 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 637 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 638 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 639 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 640 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 641 #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 642 #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 643 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 644 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 645 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 646 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 647 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 648 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 649 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 650 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 651 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 652 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 653 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 654 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 655 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 656 #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 657 #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
AnnaBridge 170:e95d10626187 658 #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
AnnaBridge 170:e95d10626187 659 #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
AnnaBridge 170:e95d10626187 660 #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 661 #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 662 #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
AnnaBridge 170:e95d10626187 663 #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
AnnaBridge 170:e95d10626187 664 #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
AnnaBridge 170:e95d10626187 665 #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 666 #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 667 #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 668 #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 669 #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 670 #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 671 #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
AnnaBridge 170:e95d10626187 672 #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
AnnaBridge 170:e95d10626187 673 #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
AnnaBridge 170:e95d10626187 674 #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 675 #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 676 #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
AnnaBridge 170:e95d10626187 677 #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
AnnaBridge 170:e95d10626187 678 #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
AnnaBridge 170:e95d10626187 679 #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 680 #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 681 #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
AnnaBridge 170:e95d10626187 682 #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
AnnaBridge 170:e95d10626187 683 #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 684 #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 685 #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 686 #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 687 #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 688 #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 689 #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 690 #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 691 #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 692 #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 693 #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
AnnaBridge 170:e95d10626187 694 #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
AnnaBridge 170:e95d10626187 695 #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 696 #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 697 #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 698 #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 699 #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 700 #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 701 #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 702 #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 703 #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
AnnaBridge 170:e95d10626187 704 #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
AnnaBridge 170:e95d10626187 705 #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 706 #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 707 #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 708 #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 709 #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 710 #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 711 #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 712 #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 713 #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 714 #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 715 #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
AnnaBridge 170:e95d10626187 716 #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
AnnaBridge 170:e95d10626187 717 #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
AnnaBridge 170:e95d10626187 718 #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 719 #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 720 #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 721 #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 722 #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 723 #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 724 #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
AnnaBridge 170:e95d10626187 725 #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
AnnaBridge 170:e95d10626187 726 #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
AnnaBridge 170:e95d10626187 727 #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 728 #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 729 #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 730 #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 731 #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 732 #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
AnnaBridge 170:e95d10626187 733
AnnaBridge 170:e95d10626187 734 /* Bit fields for LDMA CH_SRC */
AnnaBridge 170:e95d10626187 735 #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
AnnaBridge 170:e95d10626187 736 #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
AnnaBridge 170:e95d10626187 737 #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
AnnaBridge 170:e95d10626187 738 #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
AnnaBridge 170:e95d10626187 739 #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
AnnaBridge 170:e95d10626187 740 #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
AnnaBridge 170:e95d10626187 741
AnnaBridge 170:e95d10626187 742 /* Bit fields for LDMA CH_DST */
AnnaBridge 170:e95d10626187 743 #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
AnnaBridge 170:e95d10626187 744 #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
AnnaBridge 170:e95d10626187 745 #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
AnnaBridge 170:e95d10626187 746 #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
AnnaBridge 170:e95d10626187 747 #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
AnnaBridge 170:e95d10626187 748 #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
AnnaBridge 170:e95d10626187 749
AnnaBridge 170:e95d10626187 750 /* Bit fields for LDMA CH_LINK */
AnnaBridge 170:e95d10626187 751 #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 752 #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 753 #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
AnnaBridge 170:e95d10626187 754 #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
AnnaBridge 170:e95d10626187 755 #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
AnnaBridge 170:e95d10626187 756 #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 757 #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 758 #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 759 #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 760 #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 761 #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 762 #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
AnnaBridge 170:e95d10626187 763 #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
AnnaBridge 170:e95d10626187 764 #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
AnnaBridge 170:e95d10626187 765 #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 766 #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 767 #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
AnnaBridge 170:e95d10626187 768 #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
AnnaBridge 170:e95d10626187 769 #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 770 #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
AnnaBridge 170:e95d10626187 771
AnnaBridge 170:e95d10626187 772 /** @} */
AnnaBridge 170:e95d10626187 773 /** @} End of group EFM32GG11B_LDMA */
AnnaBridge 170:e95d10626187 774 /** @} End of group Parts */