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TARGET_EFM32GG11_STK3701/TOOLCHAIN_IAR/efm32gg11b_fpueh.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_fpueh.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_FPUEH register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43 /**************************************************************************//**
AnnaBridge 170:e95d10626187 44 * @defgroup EFM32GG11B_FPUEH FPUEH
AnnaBridge 170:e95d10626187 45 * @{
AnnaBridge 170:e95d10626187 46 * @brief EFM32GG11B_FPUEH Register Declaration
AnnaBridge 170:e95d10626187 47 *****************************************************************************/
AnnaBridge 170:e95d10626187 48 /** FPUEH Register Declaration */
AnnaBridge 170:e95d10626187 49 typedef struct {
AnnaBridge 170:e95d10626187 50 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 170:e95d10626187 51 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 170:e95d10626187 52 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 170:e95d10626187 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 170:e95d10626187 54 } FPUEH_TypeDef; /** @} */
AnnaBridge 170:e95d10626187 55
AnnaBridge 170:e95d10626187 56 /**************************************************************************//**
AnnaBridge 170:e95d10626187 57 * @addtogroup EFM32GG11B_FPUEH
AnnaBridge 170:e95d10626187 58 * @{
AnnaBridge 170:e95d10626187 59 * @defgroup EFM32GG11B_FPUEH_BitFields FPUEH Bit Fields
AnnaBridge 170:e95d10626187 60 * @{
AnnaBridge 170:e95d10626187 61 *****************************************************************************/
AnnaBridge 170:e95d10626187 62
AnnaBridge 170:e95d10626187 63 /* Bit fields for FPUEH IF */
AnnaBridge 170:e95d10626187 64 #define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
AnnaBridge 170:e95d10626187 65 #define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
AnnaBridge 170:e95d10626187 66 #define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
AnnaBridge 170:e95d10626187 67 #define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 68 #define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 69 #define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 70 #define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 71 #define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
AnnaBridge 170:e95d10626187 72 #define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 73 #define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 74 #define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 75 #define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 76 #define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
AnnaBridge 170:e95d10626187 77 #define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 78 #define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 79 #define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 80 #define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 81 #define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
AnnaBridge 170:e95d10626187 82 #define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 83 #define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 84 #define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 85 #define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 86 #define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
AnnaBridge 170:e95d10626187 87 #define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 88 #define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 89 #define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 90 #define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 91 #define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
AnnaBridge 170:e95d10626187 92 #define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 93 #define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 94 #define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 95 #define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 170:e95d10626187 96
AnnaBridge 170:e95d10626187 97 /* Bit fields for FPUEH IFS */
AnnaBridge 170:e95d10626187 98 #define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
AnnaBridge 170:e95d10626187 99 #define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
AnnaBridge 170:e95d10626187 100 #define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
AnnaBridge 170:e95d10626187 101 #define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 102 #define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 103 #define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 104 #define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 105 #define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
AnnaBridge 170:e95d10626187 106 #define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 107 #define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 108 #define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 109 #define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 110 #define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
AnnaBridge 170:e95d10626187 111 #define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 112 #define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 113 #define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 114 #define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 115 #define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
AnnaBridge 170:e95d10626187 116 #define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 117 #define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 118 #define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 119 #define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 120 #define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
AnnaBridge 170:e95d10626187 121 #define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 122 #define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 123 #define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 124 #define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 125 #define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
AnnaBridge 170:e95d10626187 126 #define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 127 #define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 128 #define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 129 #define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 170:e95d10626187 130
AnnaBridge 170:e95d10626187 131 /* Bit fields for FPUEH IFC */
AnnaBridge 170:e95d10626187 132 #define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
AnnaBridge 170:e95d10626187 133 #define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
AnnaBridge 170:e95d10626187 134 #define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
AnnaBridge 170:e95d10626187 135 #define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 136 #define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 137 #define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 138 #define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 139 #define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
AnnaBridge 170:e95d10626187 140 #define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 141 #define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 142 #define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 143 #define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 144 #define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
AnnaBridge 170:e95d10626187 145 #define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 146 #define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 147 #define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 148 #define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 149 #define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
AnnaBridge 170:e95d10626187 150 #define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 151 #define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 152 #define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 153 #define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 154 #define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
AnnaBridge 170:e95d10626187 155 #define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 156 #define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 157 #define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 158 #define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 159 #define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
AnnaBridge 170:e95d10626187 160 #define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 161 #define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 162 #define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 163 #define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 170:e95d10626187 164
AnnaBridge 170:e95d10626187 165 /* Bit fields for FPUEH IEN */
AnnaBridge 170:e95d10626187 166 #define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
AnnaBridge 170:e95d10626187 167 #define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
AnnaBridge 170:e95d10626187 168 #define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
AnnaBridge 170:e95d10626187 169 #define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 170 #define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 170:e95d10626187 171 #define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 172 #define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 173 #define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
AnnaBridge 170:e95d10626187 174 #define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 175 #define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 170:e95d10626187 176 #define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 177 #define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 178 #define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
AnnaBridge 170:e95d10626187 179 #define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 180 #define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 170:e95d10626187 181 #define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 182 #define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 183 #define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
AnnaBridge 170:e95d10626187 184 #define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 185 #define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 170:e95d10626187 186 #define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 187 #define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 188 #define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
AnnaBridge 170:e95d10626187 189 #define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 190 #define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 170:e95d10626187 191 #define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 192 #define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 193 #define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
AnnaBridge 170:e95d10626187 194 #define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 195 #define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 170:e95d10626187 196 #define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 197 #define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 170:e95d10626187 198
AnnaBridge 170:e95d10626187 199 /** @} */
AnnaBridge 170:e95d10626187 200 /** @} End of group EFM32GG11B_FPUEH */
AnnaBridge 170:e95d10626187 201 /** @} End of group Parts */