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TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/stm32f303xc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /** |
| AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f303xc.h |
| AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
| AnnaBridge | 163:e59c8e839560 | 5 | * @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File. |
| AnnaBridge | 163:e59c8e839560 | 6 | * |
| AnnaBridge | 163:e59c8e839560 | 7 | * This file contains: |
| AnnaBridge | 163:e59c8e839560 | 8 | * - Data structures and the address mapping for all peripherals |
| AnnaBridge | 163:e59c8e839560 | 9 | * - Peripheral's registers declarations and bits definition |
| AnnaBridge | 163:e59c8e839560 | 10 | * - Macros to access peripherals registers hardware |
| AnnaBridge | 163:e59c8e839560 | 11 | * |
| AnnaBridge | 163:e59c8e839560 | 12 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 13 | * @attention |
| AnnaBridge | 163:e59c8e839560 | 14 | * |
| AnnaBridge | 163:e59c8e839560 | 15 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 163:e59c8e839560 | 16 | * |
| AnnaBridge | 163:e59c8e839560 | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 18 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 20 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 22 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 163:e59c8e839560 | 23 | * and/or other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 163:e59c8e839560 | 25 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 163:e59c8e839560 | 26 | * without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 27 | * |
| AnnaBridge | 163:e59c8e839560 | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 163:e59c8e839560 | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 163:e59c8e839560 | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 163:e59c8e839560 | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 163:e59c8e839560 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 163:e59c8e839560 | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 163:e59c8e839560 | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 163:e59c8e839560 | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 163:e59c8e839560 | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 38 | * |
| AnnaBridge | 163:e59c8e839560 | 39 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 40 | */ |
| AnnaBridge | 163:e59c8e839560 | 41 | |
| AnnaBridge | 163:e59c8e839560 | 42 | /** @addtogroup CMSIS_Device |
| AnnaBridge | 163:e59c8e839560 | 43 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 44 | */ |
| AnnaBridge | 163:e59c8e839560 | 45 | |
| AnnaBridge | 163:e59c8e839560 | 46 | /** @addtogroup stm32f303xc |
| AnnaBridge | 163:e59c8e839560 | 47 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 48 | */ |
| AnnaBridge | 163:e59c8e839560 | 49 | |
| AnnaBridge | 163:e59c8e839560 | 50 | #ifndef __STM32F303xC_H |
| AnnaBridge | 163:e59c8e839560 | 51 | #define __STM32F303xC_H |
| AnnaBridge | 163:e59c8e839560 | 52 | |
| AnnaBridge | 163:e59c8e839560 | 53 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 54 | extern "C" { |
| AnnaBridge | 163:e59c8e839560 | 55 | #endif /* __cplusplus */ |
| AnnaBridge | 163:e59c8e839560 | 56 | |
| AnnaBridge | 163:e59c8e839560 | 57 | /** @addtogroup Configuration_section_for_CMSIS |
| AnnaBridge | 163:e59c8e839560 | 58 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 59 | */ |
| AnnaBridge | 163:e59c8e839560 | 60 | |
| AnnaBridge | 163:e59c8e839560 | 61 | /** |
| AnnaBridge | 163:e59c8e839560 | 62 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| AnnaBridge | 163:e59c8e839560 | 63 | */ |
| AnnaBridge | 163:e59c8e839560 | 64 | #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ |
| AnnaBridge | 163:e59c8e839560 | 65 | #define __MPU_PRESENT 1U /*!< STM32F303xC devices provide an MPU */ |
| AnnaBridge | 163:e59c8e839560 | 66 | #define __NVIC_PRIO_BITS 4U /*!< STM32F303xC devices use 4 Bits for the Priority Levels */ |
| AnnaBridge | 163:e59c8e839560 | 67 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| AnnaBridge | 163:e59c8e839560 | 68 | #ifndef __FPU_PRESENT |
| AnnaBridge | 163:e59c8e839560 | 69 | #define __FPU_PRESENT 1U /*!< STM32F303xC devices provide an FPU */ |
| AnnaBridge | 163:e59c8e839560 | 70 | #endif |
| AnnaBridge | 163:e59c8e839560 | 71 | /** |
| AnnaBridge | 163:e59c8e839560 | 72 | * @} |
| AnnaBridge | 163:e59c8e839560 | 73 | */ |
| AnnaBridge | 163:e59c8e839560 | 74 | |
| AnnaBridge | 163:e59c8e839560 | 75 | /** @addtogroup Peripheral_interrupt_number_definition |
| AnnaBridge | 163:e59c8e839560 | 76 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 77 | */ |
| AnnaBridge | 163:e59c8e839560 | 78 | |
| AnnaBridge | 163:e59c8e839560 | 79 | /** |
| AnnaBridge | 163:e59c8e839560 | 80 | * @brief STM32F303xC devices Interrupt Number Definition, according to the selected device |
| AnnaBridge | 163:e59c8e839560 | 81 | * in @ref Library_configuration_section |
| AnnaBridge | 163:e59c8e839560 | 82 | */ |
| AnnaBridge | 163:e59c8e839560 | 83 | typedef enum |
| AnnaBridge | 163:e59c8e839560 | 84 | { |
| AnnaBridge | 163:e59c8e839560 | 85 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 86 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 87 | HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 88 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 89 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 90 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 91 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 92 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 93 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 94 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 95 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 96 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 97 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 98 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 99 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 100 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 101 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 102 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 103 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 104 | EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 105 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 106 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 107 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 108 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 109 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 110 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 111 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 112 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 113 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 114 | ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 115 | USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 116 | USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 117 | CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 118 | CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 119 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 120 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 121 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 122 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 123 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 124 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 125 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 126 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 127 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 128 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 129 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 130 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 131 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 132 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 133 | USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 134 | USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 135 | USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 136 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 137 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 138 | USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 139 | TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 140 | TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 141 | TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 142 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 143 | ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 144 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 145 | UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 146 | UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ |
| AnnaBridge | 163:e59c8e839560 | 147 | TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 148 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 149 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 150 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 151 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 152 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 153 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 154 | ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 155 | COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ |
| AnnaBridge | 163:e59c8e839560 | 156 | COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ |
| AnnaBridge | 163:e59c8e839560 | 157 | COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ |
| AnnaBridge | 163:e59c8e839560 | 158 | USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 159 | USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 160 | USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ |
| AnnaBridge | 163:e59c8e839560 | 161 | FPU_IRQn = 81, /*!< Floating point Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 162 | } IRQn_Type; |
| AnnaBridge | 163:e59c8e839560 | 163 | |
| AnnaBridge | 163:e59c8e839560 | 164 | /** |
| AnnaBridge | 163:e59c8e839560 | 165 | * @} |
| AnnaBridge | 163:e59c8e839560 | 166 | */ |
| AnnaBridge | 163:e59c8e839560 | 167 | |
| AnnaBridge | 163:e59c8e839560 | 168 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 169 | #include "system_stm32f3xx.h" /* STM32F3xx System Header */ |
| AnnaBridge | 163:e59c8e839560 | 170 | #include <stdint.h> |
| AnnaBridge | 163:e59c8e839560 | 171 | |
| AnnaBridge | 163:e59c8e839560 | 172 | /** @addtogroup Peripheral_registers_structures |
| AnnaBridge | 163:e59c8e839560 | 173 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 174 | */ |
| AnnaBridge | 163:e59c8e839560 | 175 | |
| AnnaBridge | 163:e59c8e839560 | 176 | /** |
| AnnaBridge | 163:e59c8e839560 | 177 | * @brief Analog to Digital Converter |
| AnnaBridge | 163:e59c8e839560 | 178 | */ |
| AnnaBridge | 163:e59c8e839560 | 179 | |
| AnnaBridge | 163:e59c8e839560 | 180 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 181 | { |
| AnnaBridge | 163:e59c8e839560 | 182 | __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 183 | __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 184 | __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 185 | __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 186 | uint32_t RESERVED0; /*!< Reserved, 0x010 */ |
| AnnaBridge | 163:e59c8e839560 | 187 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 188 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 189 | uint32_t RESERVED1; /*!< Reserved, 0x01C */ |
| AnnaBridge | 163:e59c8e839560 | 190 | __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 191 | __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 192 | __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 193 | uint32_t RESERVED2; /*!< Reserved, 0x02C */ |
| AnnaBridge | 163:e59c8e839560 | 194 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 195 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 196 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 197 | __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 198 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 199 | uint32_t RESERVED3; /*!< Reserved, 0x044 */ |
| AnnaBridge | 163:e59c8e839560 | 200 | uint32_t RESERVED4; /*!< Reserved, 0x048 */ |
| AnnaBridge | 163:e59c8e839560 | 201 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 202 | uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ |
| AnnaBridge | 163:e59c8e839560 | 203 | __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ |
| AnnaBridge | 163:e59c8e839560 | 204 | __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ |
| AnnaBridge | 163:e59c8e839560 | 205 | __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ |
| AnnaBridge | 163:e59c8e839560 | 206 | __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ |
| AnnaBridge | 163:e59c8e839560 | 207 | uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ |
| AnnaBridge | 163:e59c8e839560 | 208 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 209 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ |
| AnnaBridge | 163:e59c8e839560 | 210 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ |
| AnnaBridge | 163:e59c8e839560 | 211 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ |
| AnnaBridge | 163:e59c8e839560 | 212 | uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ |
| AnnaBridge | 163:e59c8e839560 | 213 | __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ |
| AnnaBridge | 163:e59c8e839560 | 214 | __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ |
| AnnaBridge | 163:e59c8e839560 | 215 | uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ |
| AnnaBridge | 163:e59c8e839560 | 216 | uint32_t RESERVED9; /*!< Reserved, 0x0AC */ |
| AnnaBridge | 163:e59c8e839560 | 217 | __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ |
| AnnaBridge | 163:e59c8e839560 | 218 | __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ |
| AnnaBridge | 163:e59c8e839560 | 219 | |
| AnnaBridge | 163:e59c8e839560 | 220 | } ADC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 221 | |
| AnnaBridge | 163:e59c8e839560 | 222 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 223 | { |
| AnnaBridge | 163:e59c8e839560 | 224 | __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ |
| AnnaBridge | 163:e59c8e839560 | 225 | uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ |
| AnnaBridge | 163:e59c8e839560 | 226 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ |
| AnnaBridge | 163:e59c8e839560 | 227 | __IO uint32_t CDR; /*!< ADC common regular data register for dual |
| AnnaBridge | 163:e59c8e839560 | 228 | AND triple modes, Address offset: ADC1/3 base address + 0x30C */ |
| AnnaBridge | 163:e59c8e839560 | 229 | } ADC_Common_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 230 | |
| AnnaBridge | 163:e59c8e839560 | 231 | /** |
| AnnaBridge | 163:e59c8e839560 | 232 | * @brief Controller Area Network TxMailBox |
| AnnaBridge | 163:e59c8e839560 | 233 | */ |
| AnnaBridge | 163:e59c8e839560 | 234 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 235 | { |
| AnnaBridge | 163:e59c8e839560 | 236 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| AnnaBridge | 163:e59c8e839560 | 237 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| AnnaBridge | 163:e59c8e839560 | 238 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| AnnaBridge | 163:e59c8e839560 | 239 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| AnnaBridge | 163:e59c8e839560 | 240 | } CAN_TxMailBox_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 241 | |
| AnnaBridge | 163:e59c8e839560 | 242 | /** |
| AnnaBridge | 163:e59c8e839560 | 243 | * @brief Controller Area Network FIFOMailBox |
| AnnaBridge | 163:e59c8e839560 | 244 | */ |
| AnnaBridge | 163:e59c8e839560 | 245 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 246 | { |
| AnnaBridge | 163:e59c8e839560 | 247 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| AnnaBridge | 163:e59c8e839560 | 248 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| AnnaBridge | 163:e59c8e839560 | 249 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| AnnaBridge | 163:e59c8e839560 | 250 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| AnnaBridge | 163:e59c8e839560 | 251 | } CAN_FIFOMailBox_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 252 | |
| AnnaBridge | 163:e59c8e839560 | 253 | /** |
| AnnaBridge | 163:e59c8e839560 | 254 | * @brief Controller Area Network FilterRegister |
| AnnaBridge | 163:e59c8e839560 | 255 | */ |
| AnnaBridge | 163:e59c8e839560 | 256 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 257 | { |
| AnnaBridge | 163:e59c8e839560 | 258 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| AnnaBridge | 163:e59c8e839560 | 259 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| AnnaBridge | 163:e59c8e839560 | 260 | } CAN_FilterRegister_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 261 | |
| AnnaBridge | 163:e59c8e839560 | 262 | /** |
| AnnaBridge | 163:e59c8e839560 | 263 | * @brief Controller Area Network |
| AnnaBridge | 163:e59c8e839560 | 264 | */ |
| AnnaBridge | 163:e59c8e839560 | 265 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 266 | { |
| AnnaBridge | 163:e59c8e839560 | 267 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 268 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 269 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 270 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 271 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 272 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 273 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 274 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 275 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| AnnaBridge | 163:e59c8e839560 | 276 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| AnnaBridge | 163:e59c8e839560 | 277 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| AnnaBridge | 163:e59c8e839560 | 278 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| AnnaBridge | 163:e59c8e839560 | 279 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| AnnaBridge | 163:e59c8e839560 | 280 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| AnnaBridge | 163:e59c8e839560 | 281 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| AnnaBridge | 163:e59c8e839560 | 282 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| AnnaBridge | 163:e59c8e839560 | 283 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| AnnaBridge | 163:e59c8e839560 | 284 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| AnnaBridge | 163:e59c8e839560 | 285 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| AnnaBridge | 163:e59c8e839560 | 286 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| AnnaBridge | 163:e59c8e839560 | 287 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| AnnaBridge | 163:e59c8e839560 | 288 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| AnnaBridge | 163:e59c8e839560 | 289 | } CAN_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 290 | |
| AnnaBridge | 163:e59c8e839560 | 291 | /** |
| AnnaBridge | 163:e59c8e839560 | 292 | * @brief Analog Comparators |
| AnnaBridge | 163:e59c8e839560 | 293 | */ |
| AnnaBridge | 163:e59c8e839560 | 294 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 295 | { |
| AnnaBridge | 163:e59c8e839560 | 296 | __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 297 | } COMP_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 298 | |
| AnnaBridge | 163:e59c8e839560 | 299 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 300 | { |
| AnnaBridge | 163:e59c8e839560 | 301 | __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 302 | } COMP_Common_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 303 | |
| AnnaBridge | 163:e59c8e839560 | 304 | /** |
| AnnaBridge | 163:e59c8e839560 | 305 | * @brief CRC calculation unit |
| AnnaBridge | 163:e59c8e839560 | 306 | */ |
| AnnaBridge | 163:e59c8e839560 | 307 | |
| AnnaBridge | 163:e59c8e839560 | 308 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 309 | { |
| AnnaBridge | 163:e59c8e839560 | 310 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 311 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 312 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| AnnaBridge | 163:e59c8e839560 | 313 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| AnnaBridge | 163:e59c8e839560 | 314 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 315 | uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 316 | __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 317 | __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 318 | } CRC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 319 | |
| AnnaBridge | 163:e59c8e839560 | 320 | /** |
| AnnaBridge | 163:e59c8e839560 | 321 | * @brief Digital to Analog Converter |
| AnnaBridge | 163:e59c8e839560 | 322 | */ |
| AnnaBridge | 163:e59c8e839560 | 323 | |
| AnnaBridge | 163:e59c8e839560 | 324 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 325 | { |
| AnnaBridge | 163:e59c8e839560 | 326 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 327 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 328 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 329 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 330 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 331 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 332 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 333 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 334 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 335 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 336 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 337 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 338 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 339 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 340 | } DAC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 341 | |
| AnnaBridge | 163:e59c8e839560 | 342 | /** |
| AnnaBridge | 163:e59c8e839560 | 343 | * @brief Debug MCU |
| AnnaBridge | 163:e59c8e839560 | 344 | */ |
| AnnaBridge | 163:e59c8e839560 | 345 | |
| AnnaBridge | 163:e59c8e839560 | 346 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 347 | { |
| AnnaBridge | 163:e59c8e839560 | 348 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 349 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 350 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 351 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 352 | }DBGMCU_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 353 | |
| AnnaBridge | 163:e59c8e839560 | 354 | /** |
| AnnaBridge | 163:e59c8e839560 | 355 | * @brief DMA Controller |
| AnnaBridge | 163:e59c8e839560 | 356 | */ |
| AnnaBridge | 163:e59c8e839560 | 357 | |
| AnnaBridge | 163:e59c8e839560 | 358 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 359 | { |
| AnnaBridge | 163:e59c8e839560 | 360 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 361 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| AnnaBridge | 163:e59c8e839560 | 362 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| AnnaBridge | 163:e59c8e839560 | 363 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| AnnaBridge | 163:e59c8e839560 | 364 | } DMA_Channel_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 365 | |
| AnnaBridge | 163:e59c8e839560 | 366 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 367 | { |
| AnnaBridge | 163:e59c8e839560 | 368 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 369 | __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 370 | } DMA_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 371 | |
| AnnaBridge | 163:e59c8e839560 | 372 | /** |
| AnnaBridge | 163:e59c8e839560 | 373 | * @brief External Interrupt/Event Controller |
| AnnaBridge | 163:e59c8e839560 | 374 | */ |
| AnnaBridge | 163:e59c8e839560 | 375 | |
| AnnaBridge | 163:e59c8e839560 | 376 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 377 | { |
| AnnaBridge | 163:e59c8e839560 | 378 | __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 379 | __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 380 | __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 381 | __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 382 | __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 383 | __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 384 | uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 385 | uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 386 | __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 387 | __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 388 | __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 389 | __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 390 | __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 391 | __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 392 | }EXTI_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 393 | |
| AnnaBridge | 163:e59c8e839560 | 394 | /** |
| AnnaBridge | 163:e59c8e839560 | 395 | * @brief FLASH Registers |
| AnnaBridge | 163:e59c8e839560 | 396 | */ |
| AnnaBridge | 163:e59c8e839560 | 397 | |
| AnnaBridge | 163:e59c8e839560 | 398 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 399 | { |
| AnnaBridge | 163:e59c8e839560 | 400 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 401 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 402 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 403 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 404 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 405 | __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 406 | uint32_t RESERVED; /*!< Reserved, 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 407 | __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 408 | __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 409 | |
| AnnaBridge | 163:e59c8e839560 | 410 | } FLASH_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 411 | |
| AnnaBridge | 163:e59c8e839560 | 412 | /** |
| AnnaBridge | 163:e59c8e839560 | 413 | * @brief Option Bytes Registers |
| AnnaBridge | 163:e59c8e839560 | 414 | */ |
| AnnaBridge | 163:e59c8e839560 | 415 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 416 | { |
| AnnaBridge | 163:e59c8e839560 | 417 | __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 418 | __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ |
| AnnaBridge | 163:e59c8e839560 | 419 | uint16_t RESERVED0; /*!< Reserved, 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 420 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| AnnaBridge | 163:e59c8e839560 | 421 | __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 422 | __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 423 | __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 424 | __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */ |
| AnnaBridge | 163:e59c8e839560 | 425 | } OB_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 426 | |
| AnnaBridge | 163:e59c8e839560 | 427 | /** |
| AnnaBridge | 163:e59c8e839560 | 428 | * @brief General Purpose I/O |
| AnnaBridge | 163:e59c8e839560 | 429 | */ |
| AnnaBridge | 163:e59c8e839560 | 430 | |
| AnnaBridge | 163:e59c8e839560 | 431 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 432 | { |
| AnnaBridge | 163:e59c8e839560 | 433 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 434 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 435 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 436 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 437 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 438 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 439 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ |
| AnnaBridge | 163:e59c8e839560 | 440 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 441 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 442 | __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 443 | }GPIO_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 444 | |
| AnnaBridge | 163:e59c8e839560 | 445 | /** |
| AnnaBridge | 163:e59c8e839560 | 446 | * @brief Operational Amplifier (OPAMP) |
| AnnaBridge | 163:e59c8e839560 | 447 | */ |
| AnnaBridge | 163:e59c8e839560 | 448 | |
| AnnaBridge | 163:e59c8e839560 | 449 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 450 | { |
| AnnaBridge | 163:e59c8e839560 | 451 | __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 452 | } OPAMP_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 453 | |
| AnnaBridge | 163:e59c8e839560 | 454 | /** |
| AnnaBridge | 163:e59c8e839560 | 455 | * @brief System configuration controller |
| AnnaBridge | 163:e59c8e839560 | 456 | */ |
| AnnaBridge | 163:e59c8e839560 | 457 | |
| AnnaBridge | 163:e59c8e839560 | 458 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 459 | { |
| AnnaBridge | 163:e59c8e839560 | 460 | __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 461 | __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 462 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 463 | __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 464 | } SYSCFG_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 465 | |
| AnnaBridge | 163:e59c8e839560 | 466 | /** |
| AnnaBridge | 163:e59c8e839560 | 467 | * @brief Inter-integrated Circuit Interface |
| AnnaBridge | 163:e59c8e839560 | 468 | */ |
| AnnaBridge | 163:e59c8e839560 | 469 | |
| AnnaBridge | 163:e59c8e839560 | 470 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 471 | { |
| AnnaBridge | 163:e59c8e839560 | 472 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 473 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 474 | __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 475 | __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 476 | __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 477 | __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 478 | __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 479 | __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 480 | __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 481 | __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 482 | __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 483 | }I2C_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 484 | |
| AnnaBridge | 163:e59c8e839560 | 485 | /** |
| AnnaBridge | 163:e59c8e839560 | 486 | * @brief Independent WATCHDOG |
| AnnaBridge | 163:e59c8e839560 | 487 | */ |
| AnnaBridge | 163:e59c8e839560 | 488 | |
| AnnaBridge | 163:e59c8e839560 | 489 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 490 | { |
| AnnaBridge | 163:e59c8e839560 | 491 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 492 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 493 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 494 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 495 | __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 496 | } IWDG_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 497 | |
| AnnaBridge | 163:e59c8e839560 | 498 | /** |
| AnnaBridge | 163:e59c8e839560 | 499 | * @brief Power Control |
| AnnaBridge | 163:e59c8e839560 | 500 | */ |
| AnnaBridge | 163:e59c8e839560 | 501 | |
| AnnaBridge | 163:e59c8e839560 | 502 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 503 | { |
| AnnaBridge | 163:e59c8e839560 | 504 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 505 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 506 | } PWR_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 507 | |
| AnnaBridge | 163:e59c8e839560 | 508 | /** |
| AnnaBridge | 163:e59c8e839560 | 509 | * @brief Reset and Clock Control |
| AnnaBridge | 163:e59c8e839560 | 510 | */ |
| AnnaBridge | 163:e59c8e839560 | 511 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 512 | { |
| AnnaBridge | 163:e59c8e839560 | 513 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 514 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 515 | __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 516 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 517 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 518 | __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 519 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 520 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 521 | __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 522 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 523 | __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 524 | __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 525 | __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 526 | } RCC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 527 | |
| AnnaBridge | 163:e59c8e839560 | 528 | /** |
| AnnaBridge | 163:e59c8e839560 | 529 | * @brief Real-Time Clock |
| AnnaBridge | 163:e59c8e839560 | 530 | */ |
| AnnaBridge | 163:e59c8e839560 | 531 | |
| AnnaBridge | 163:e59c8e839560 | 532 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 533 | { |
| AnnaBridge | 163:e59c8e839560 | 534 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 535 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 536 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 537 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 538 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 539 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 540 | uint32_t RESERVED0; /*!< Reserved, 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 541 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 542 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 543 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 544 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 545 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 546 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 547 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 548 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 549 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 550 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 551 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 552 | __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 553 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 554 | __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 555 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 556 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 557 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 558 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| AnnaBridge | 163:e59c8e839560 | 559 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| AnnaBridge | 163:e59c8e839560 | 560 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| AnnaBridge | 163:e59c8e839560 | 561 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| AnnaBridge | 163:e59c8e839560 | 562 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| AnnaBridge | 163:e59c8e839560 | 563 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| AnnaBridge | 163:e59c8e839560 | 564 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| AnnaBridge | 163:e59c8e839560 | 565 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| AnnaBridge | 163:e59c8e839560 | 566 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 567 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| AnnaBridge | 163:e59c8e839560 | 568 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| AnnaBridge | 163:e59c8e839560 | 569 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| AnnaBridge | 163:e59c8e839560 | 570 | } RTC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 571 | |
| AnnaBridge | 163:e59c8e839560 | 572 | |
| AnnaBridge | 163:e59c8e839560 | 573 | /** |
| AnnaBridge | 163:e59c8e839560 | 574 | * @brief Serial Peripheral Interface |
| AnnaBridge | 163:e59c8e839560 | 575 | */ |
| AnnaBridge | 163:e59c8e839560 | 576 | |
| AnnaBridge | 163:e59c8e839560 | 577 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 578 | { |
| AnnaBridge | 163:e59c8e839560 | 579 | __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 580 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 581 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 582 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 583 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 584 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 585 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 586 | __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 587 | __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 588 | } SPI_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 589 | |
| AnnaBridge | 163:e59c8e839560 | 590 | /** |
| AnnaBridge | 163:e59c8e839560 | 591 | * @brief TIM |
| AnnaBridge | 163:e59c8e839560 | 592 | */ |
| AnnaBridge | 163:e59c8e839560 | 593 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 594 | { |
| AnnaBridge | 163:e59c8e839560 | 595 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 596 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 597 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 598 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 599 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 600 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 601 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 602 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 603 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 604 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 605 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 606 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 607 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 608 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 609 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 610 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 611 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 612 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 613 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 614 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 615 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 616 | __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 617 | __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 618 | __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 619 | } TIM_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 620 | |
| AnnaBridge | 163:e59c8e839560 | 621 | /** |
| AnnaBridge | 163:e59c8e839560 | 622 | * @brief Touch Sensing Controller (TSC) |
| AnnaBridge | 163:e59c8e839560 | 623 | */ |
| AnnaBridge | 163:e59c8e839560 | 624 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 625 | { |
| AnnaBridge | 163:e59c8e839560 | 626 | __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 627 | __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 628 | __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 629 | __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 630 | __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 631 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 632 | __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 633 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 634 | __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 635 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 636 | __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 637 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 638 | __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 639 | __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
| AnnaBridge | 163:e59c8e839560 | 640 | } TSC_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 641 | |
| AnnaBridge | 163:e59c8e839560 | 642 | /** |
| AnnaBridge | 163:e59c8e839560 | 643 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| AnnaBridge | 163:e59c8e839560 | 644 | */ |
| AnnaBridge | 163:e59c8e839560 | 645 | |
| AnnaBridge | 163:e59c8e839560 | 646 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 647 | { |
| AnnaBridge | 163:e59c8e839560 | 648 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 649 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 650 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 651 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 652 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 653 | __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 654 | __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 655 | __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 656 | __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 657 | __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 658 | uint16_t RESERVED1; /*!< Reserved, 0x26 */ |
| AnnaBridge | 163:e59c8e839560 | 659 | __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 660 | uint16_t RESERVED2; /*!< Reserved, 0x2A */ |
| AnnaBridge | 163:e59c8e839560 | 661 | } USART_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 662 | |
| AnnaBridge | 163:e59c8e839560 | 663 | /** |
| AnnaBridge | 163:e59c8e839560 | 664 | * @brief Universal Serial Bus Full Speed Device |
| AnnaBridge | 163:e59c8e839560 | 665 | */ |
| AnnaBridge | 163:e59c8e839560 | 666 | |
| AnnaBridge | 163:e59c8e839560 | 667 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 668 | { |
| AnnaBridge | 163:e59c8e839560 | 669 | __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 670 | __IO uint16_t RESERVED0; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 671 | __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 672 | __IO uint16_t RESERVED1; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 673 | __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 674 | __IO uint16_t RESERVED2; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 675 | __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ |
| AnnaBridge | 163:e59c8e839560 | 676 | __IO uint16_t RESERVED3; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 677 | __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 678 | __IO uint16_t RESERVED4; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 679 | __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 680 | __IO uint16_t RESERVED5; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 681 | __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 682 | __IO uint16_t RESERVED6; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 683 | __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 684 | __IO uint16_t RESERVED7[17]; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 685 | __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 686 | __IO uint16_t RESERVED8; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 687 | __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 688 | __IO uint16_t RESERVED9; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 689 | __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 690 | __IO uint16_t RESERVEDA; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 691 | __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 692 | __IO uint16_t RESERVEDB; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 693 | __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 694 | __IO uint16_t RESERVEDC; /*!< Reserved */ |
| AnnaBridge | 163:e59c8e839560 | 695 | } USB_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 696 | |
| AnnaBridge | 163:e59c8e839560 | 697 | /** |
| AnnaBridge | 163:e59c8e839560 | 698 | * @brief Window WATCHDOG |
| AnnaBridge | 163:e59c8e839560 | 699 | */ |
| AnnaBridge | 163:e59c8e839560 | 700 | typedef struct |
| AnnaBridge | 163:e59c8e839560 | 701 | { |
| AnnaBridge | 163:e59c8e839560 | 702 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| AnnaBridge | 163:e59c8e839560 | 703 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| AnnaBridge | 163:e59c8e839560 | 704 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| AnnaBridge | 163:e59c8e839560 | 705 | } WWDG_TypeDef; |
| AnnaBridge | 163:e59c8e839560 | 706 | |
| AnnaBridge | 163:e59c8e839560 | 707 | /** @addtogroup Peripheral_memory_map |
| AnnaBridge | 163:e59c8e839560 | 708 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 709 | */ |
| AnnaBridge | 163:e59c8e839560 | 710 | |
| AnnaBridge | 163:e59c8e839560 | 711 | #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ |
| AnnaBridge | 163:e59c8e839560 | 712 | #define CCMDATARAM_BASE ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region */ |
| AnnaBridge | 163:e59c8e839560 | 713 | #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ |
| AnnaBridge | 163:e59c8e839560 | 714 | #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ |
| AnnaBridge | 163:e59c8e839560 | 715 | #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ |
| AnnaBridge | 163:e59c8e839560 | 716 | #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ |
| AnnaBridge | 163:e59c8e839560 | 717 | |
| AnnaBridge | 163:e59c8e839560 | 718 | |
| AnnaBridge | 163:e59c8e839560 | 719 | /*!< Peripheral memory map */ |
| AnnaBridge | 163:e59c8e839560 | 720 | #define APB1PERIPH_BASE PERIPH_BASE |
| AnnaBridge | 163:e59c8e839560 | 721 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
| AnnaBridge | 163:e59c8e839560 | 722 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) |
| AnnaBridge | 163:e59c8e839560 | 723 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) |
| AnnaBridge | 163:e59c8e839560 | 724 | #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 725 | |
| AnnaBridge | 163:e59c8e839560 | 726 | /*!< APB1 peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 727 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) |
| AnnaBridge | 163:e59c8e839560 | 728 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 729 | #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 730 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 731 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) |
| AnnaBridge | 163:e59c8e839560 | 732 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) |
| AnnaBridge | 163:e59c8e839560 | 733 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) |
| AnnaBridge | 163:e59c8e839560 | 734 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) |
| AnnaBridge | 163:e59c8e839560 | 735 | #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400U) |
| AnnaBridge | 163:e59c8e839560 | 736 | #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) |
| AnnaBridge | 163:e59c8e839560 | 737 | #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) |
| AnnaBridge | 163:e59c8e839560 | 738 | #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 739 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) |
| AnnaBridge | 163:e59c8e839560 | 740 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) |
| AnnaBridge | 163:e59c8e839560 | 741 | #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) |
| AnnaBridge | 163:e59c8e839560 | 742 | #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) |
| AnnaBridge | 163:e59c8e839560 | 743 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) |
| AnnaBridge | 163:e59c8e839560 | 744 | #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) |
| AnnaBridge | 163:e59c8e839560 | 745 | #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ |
| AnnaBridge | 163:e59c8e839560 | 746 | #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ |
| AnnaBridge | 163:e59c8e839560 | 747 | #define CAN_BASE (APB1PERIPH_BASE + 0x00006400U) |
| AnnaBridge | 163:e59c8e839560 | 748 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) |
| AnnaBridge | 163:e59c8e839560 | 749 | #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400U) |
| AnnaBridge | 163:e59c8e839560 | 750 | #define DAC_BASE DAC1_BASE |
| AnnaBridge | 163:e59c8e839560 | 751 | |
| AnnaBridge | 163:e59c8e839560 | 752 | /*!< APB2 peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 753 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) |
| AnnaBridge | 163:e59c8e839560 | 754 | #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CU) |
| AnnaBridge | 163:e59c8e839560 | 755 | #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 756 | #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024U) |
| AnnaBridge | 163:e59c8e839560 | 757 | #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028U) |
| AnnaBridge | 163:e59c8e839560 | 758 | #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CU) |
| AnnaBridge | 163:e59c8e839560 | 759 | #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030U) |
| AnnaBridge | 163:e59c8e839560 | 760 | #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034U) |
| AnnaBridge | 163:e59c8e839560 | 761 | #define COMP_BASE COMP1_BASE |
| AnnaBridge | 163:e59c8e839560 | 762 | #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038U) |
| AnnaBridge | 163:e59c8e839560 | 763 | #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CU) |
| AnnaBridge | 163:e59c8e839560 | 764 | #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 765 | #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044U) |
| AnnaBridge | 163:e59c8e839560 | 766 | #define OPAMP_BASE OPAMP1_BASE |
| AnnaBridge | 163:e59c8e839560 | 767 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 768 | #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) |
| AnnaBridge | 163:e59c8e839560 | 769 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) |
| AnnaBridge | 163:e59c8e839560 | 770 | #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U) |
| AnnaBridge | 163:e59c8e839560 | 771 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) |
| AnnaBridge | 163:e59c8e839560 | 772 | #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 773 | #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U) |
| AnnaBridge | 163:e59c8e839560 | 774 | #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U) |
| AnnaBridge | 163:e59c8e839560 | 775 | |
| AnnaBridge | 163:e59c8e839560 | 776 | /*!< AHB1 peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 777 | #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000U) |
| AnnaBridge | 163:e59c8e839560 | 778 | #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 779 | #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CU) |
| AnnaBridge | 163:e59c8e839560 | 780 | #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030U) |
| AnnaBridge | 163:e59c8e839560 | 781 | #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044U) |
| AnnaBridge | 163:e59c8e839560 | 782 | #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058U) |
| AnnaBridge | 163:e59c8e839560 | 783 | #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CU) |
| AnnaBridge | 163:e59c8e839560 | 784 | #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 785 | #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 786 | #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408U) |
| AnnaBridge | 163:e59c8e839560 | 787 | #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CU) |
| AnnaBridge | 163:e59c8e839560 | 788 | #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430U) |
| AnnaBridge | 163:e59c8e839560 | 789 | #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444U) |
| AnnaBridge | 163:e59c8e839560 | 790 | #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458U) |
| AnnaBridge | 163:e59c8e839560 | 791 | #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 792 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ |
| AnnaBridge | 163:e59c8e839560 | 793 | #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< Flash Option Bytes base address */ |
| AnnaBridge | 163:e59c8e839560 | 794 | #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */ |
| AnnaBridge | 163:e59c8e839560 | 795 | #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */ |
| AnnaBridge | 163:e59c8e839560 | 796 | #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000U) |
| AnnaBridge | 163:e59c8e839560 | 797 | #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 798 | |
| AnnaBridge | 163:e59c8e839560 | 799 | /*!< AHB2 peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 800 | #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000U) |
| AnnaBridge | 163:e59c8e839560 | 801 | #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 802 | #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 803 | #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00U) |
| AnnaBridge | 163:e59c8e839560 | 804 | #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 805 | #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400U) |
| AnnaBridge | 163:e59c8e839560 | 806 | |
| AnnaBridge | 163:e59c8e839560 | 807 | /*!< AHB3 peripherals */ |
| AnnaBridge | 163:e59c8e839560 | 808 | #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000U) |
| AnnaBridge | 163:e59c8e839560 | 809 | #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 810 | #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300U) |
| AnnaBridge | 163:e59c8e839560 | 811 | #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 812 | #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500U) |
| AnnaBridge | 163:e59c8e839560 | 813 | #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700U) |
| AnnaBridge | 163:e59c8e839560 | 814 | |
| AnnaBridge | 163:e59c8e839560 | 815 | #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ |
| AnnaBridge | 163:e59c8e839560 | 816 | /** |
| AnnaBridge | 163:e59c8e839560 | 817 | * @} |
| AnnaBridge | 163:e59c8e839560 | 818 | */ |
| AnnaBridge | 163:e59c8e839560 | 819 | |
| AnnaBridge | 163:e59c8e839560 | 820 | /** @addtogroup Peripheral_declaration |
| AnnaBridge | 163:e59c8e839560 | 821 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 822 | */ |
| AnnaBridge | 163:e59c8e839560 | 823 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 824 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 825 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 826 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 827 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 828 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 829 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| AnnaBridge | 163:e59c8e839560 | 830 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| AnnaBridge | 163:e59c8e839560 | 831 | #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
| AnnaBridge | 163:e59c8e839560 | 832 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 833 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 834 | #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
| AnnaBridge | 163:e59c8e839560 | 835 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 836 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 837 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 838 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 839 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 840 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 841 | #define CAN1 ((CAN_TypeDef *) CAN_BASE) |
| AnnaBridge | 163:e59c8e839560 | 842 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| AnnaBridge | 163:e59c8e839560 | 843 | #define DAC ((DAC_TypeDef *) DAC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 844 | #define DAC1 ((DAC_TypeDef *) DAC1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 845 | #define COMP1 ((COMP_TypeDef *) COMP1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 846 | #define COMP2 ((COMP_TypeDef *) COMP2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 847 | #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 848 | #define COMP3 ((COMP_TypeDef *) COMP3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 849 | #define COMP4 ((COMP_TypeDef *) COMP4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 850 | #define COMP34_COMMON ((COMP_Common_TypeDef *) COMP4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 851 | #define COMP5 ((COMP_TypeDef *) COMP5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 852 | #define COMP6 ((COMP_TypeDef *) COMP6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 853 | #define COMP56_COMMON ((COMP_Common_TypeDef *) COMP6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 854 | #define COMP7 ((COMP_TypeDef *) COMP7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 855 | /* Legacy define */ |
| AnnaBridge | 163:e59c8e839560 | 856 | #define COMP ((COMP_TypeDef *) COMP_BASE) |
| AnnaBridge | 163:e59c8e839560 | 857 | #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 858 | #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
| AnnaBridge | 163:e59c8e839560 | 859 | #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 860 | #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 861 | #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 862 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| AnnaBridge | 163:e59c8e839560 | 863 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| AnnaBridge | 163:e59c8e839560 | 864 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 865 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 866 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| AnnaBridge | 163:e59c8e839560 | 867 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 868 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| AnnaBridge | 163:e59c8e839560 | 869 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| AnnaBridge | 163:e59c8e839560 | 870 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| AnnaBridge | 163:e59c8e839560 | 871 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| AnnaBridge | 163:e59c8e839560 | 872 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 873 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 874 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 875 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 876 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 877 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 878 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 879 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 880 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 881 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 882 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 883 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 884 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 885 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 886 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 887 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| AnnaBridge | 163:e59c8e839560 | 888 | #define OB ((OB_TypeDef *) OB_BASE) |
| AnnaBridge | 163:e59c8e839560 | 889 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 890 | #define TSC ((TSC_TypeDef *) TSC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 891 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| AnnaBridge | 163:e59c8e839560 | 892 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| AnnaBridge | 163:e59c8e839560 | 893 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 894 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| AnnaBridge | 163:e59c8e839560 | 895 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| AnnaBridge | 163:e59c8e839560 | 896 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| AnnaBridge | 163:e59c8e839560 | 897 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 898 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 899 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 900 | #define ADC4 ((ADC_TypeDef *) ADC4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 901 | #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE) |
| AnnaBridge | 163:e59c8e839560 | 902 | #define ADC34_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE) |
| AnnaBridge | 163:e59c8e839560 | 903 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 904 | #define ADC1_2_COMMON ADC12_COMMON |
| AnnaBridge | 163:e59c8e839560 | 905 | #define ADC3_4_COMMON ADC34_COMMON |
| AnnaBridge | 163:e59c8e839560 | 906 | #define USB ((USB_TypeDef *) USB_BASE) |
| AnnaBridge | 163:e59c8e839560 | 907 | |
| AnnaBridge | 163:e59c8e839560 | 908 | /** |
| AnnaBridge | 163:e59c8e839560 | 909 | * @} |
| AnnaBridge | 163:e59c8e839560 | 910 | */ |
| AnnaBridge | 163:e59c8e839560 | 911 | |
| AnnaBridge | 163:e59c8e839560 | 912 | /** @addtogroup Exported_constants |
| AnnaBridge | 163:e59c8e839560 | 913 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 914 | */ |
| AnnaBridge | 163:e59c8e839560 | 915 | |
| AnnaBridge | 163:e59c8e839560 | 916 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| AnnaBridge | 163:e59c8e839560 | 917 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 918 | */ |
| AnnaBridge | 163:e59c8e839560 | 919 | |
| AnnaBridge | 163:e59c8e839560 | 920 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 921 | /* Peripheral Registers_Bits_Definition */ |
| AnnaBridge | 163:e59c8e839560 | 922 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 923 | |
| AnnaBridge | 163:e59c8e839560 | 924 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 925 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 926 | /* Analog to Digital Converter SAR (ADC) */ |
| AnnaBridge | 163:e59c8e839560 | 927 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 928 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 929 | |
| AnnaBridge | 163:e59c8e839560 | 930 | #define ADC5_V1_1 /*!< ADC IP version */ |
| AnnaBridge | 163:e59c8e839560 | 931 | |
| AnnaBridge | 163:e59c8e839560 | 932 | /* |
| AnnaBridge | 163:e59c8e839560 | 933 | * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| AnnaBridge | 163:e59c8e839560 | 934 | */ |
| AnnaBridge | 163:e59c8e839560 | 935 | #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ |
| AnnaBridge | 163:e59c8e839560 | 936 | |
| AnnaBridge | 163:e59c8e839560 | 937 | /******************** Bit definition for ADC_ISR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 938 | #define ADC_ISR_ADRDY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 939 | #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 940 | #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ |
| AnnaBridge | 163:e59c8e839560 | 941 | #define ADC_ISR_EOSMP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 942 | #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 943 | #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ |
| AnnaBridge | 163:e59c8e839560 | 944 | #define ADC_ISR_EOC_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 945 | #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 946 | #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 947 | #define ADC_ISR_EOS_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 948 | #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 949 | #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 950 | #define ADC_ISR_OVR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 951 | #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 952 | #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 953 | #define ADC_ISR_JEOC_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 954 | #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 955 | #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 956 | #define ADC_ISR_JEOS_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 957 | #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 958 | #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 959 | #define ADC_ISR_AWD1_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 960 | #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 961 | #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ |
| AnnaBridge | 163:e59c8e839560 | 962 | #define ADC_ISR_AWD2_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 963 | #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 964 | #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ |
| AnnaBridge | 163:e59c8e839560 | 965 | #define ADC_ISR_AWD3_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 966 | #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 967 | #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ |
| AnnaBridge | 163:e59c8e839560 | 968 | #define ADC_ISR_JQOVF_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 969 | #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 970 | #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ |
| AnnaBridge | 163:e59c8e839560 | 971 | |
| AnnaBridge | 163:e59c8e839560 | 972 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 973 | #define ADC_ISR_ADRD (ADC_ISR_ADRDY) |
| AnnaBridge | 163:e59c8e839560 | 974 | |
| AnnaBridge | 163:e59c8e839560 | 975 | /******************** Bit definition for ADC_IER register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 976 | #define ADC_IER_ADRDYIE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 977 | #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 978 | #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 979 | #define ADC_IER_EOSMPIE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 980 | #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 981 | #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 982 | #define ADC_IER_EOCIE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 983 | #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 984 | #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 985 | #define ADC_IER_EOSIE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 986 | #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 987 | #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 988 | #define ADC_IER_OVRIE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 989 | #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 990 | #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 991 | #define ADC_IER_JEOCIE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 992 | #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 993 | #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 994 | #define ADC_IER_JEOSIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 995 | #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 996 | #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 997 | #define ADC_IER_AWD1IE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 998 | #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 999 | #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 1000 | #define ADC_IER_AWD2IE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 1001 | #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1002 | #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 1003 | #define ADC_IER_AWD3IE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 1004 | #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1005 | #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 1006 | #define ADC_IER_JQOVFIE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 1007 | #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1008 | #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 1009 | |
| AnnaBridge | 163:e59c8e839560 | 1010 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 1011 | #define ADC_IER_RDY (ADC_IER_ADRDYIE) |
| AnnaBridge | 163:e59c8e839560 | 1012 | #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) |
| AnnaBridge | 163:e59c8e839560 | 1013 | #define ADC_IER_EOC (ADC_IER_EOCIE) |
| AnnaBridge | 163:e59c8e839560 | 1014 | #define ADC_IER_EOS (ADC_IER_EOSIE) |
| AnnaBridge | 163:e59c8e839560 | 1015 | #define ADC_IER_OVR (ADC_IER_OVRIE) |
| AnnaBridge | 163:e59c8e839560 | 1016 | #define ADC_IER_JEOC (ADC_IER_JEOCIE) |
| AnnaBridge | 163:e59c8e839560 | 1017 | #define ADC_IER_JEOS (ADC_IER_JEOSIE) |
| AnnaBridge | 163:e59c8e839560 | 1018 | #define ADC_IER_AWD1 (ADC_IER_AWD1IE) |
| AnnaBridge | 163:e59c8e839560 | 1019 | #define ADC_IER_AWD2 (ADC_IER_AWD2IE) |
| AnnaBridge | 163:e59c8e839560 | 1020 | #define ADC_IER_AWD3 (ADC_IER_AWD3IE) |
| AnnaBridge | 163:e59c8e839560 | 1021 | #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) |
| AnnaBridge | 163:e59c8e839560 | 1022 | |
| AnnaBridge | 163:e59c8e839560 | 1023 | /******************** Bit definition for ADC_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 1024 | #define ADC_CR_ADEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1025 | #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1026 | #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ |
| AnnaBridge | 163:e59c8e839560 | 1027 | #define ADC_CR_ADDIS_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 1028 | #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1029 | #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ |
| AnnaBridge | 163:e59c8e839560 | 1030 | #define ADC_CR_ADSTART_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 1031 | #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1032 | #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ |
| AnnaBridge | 163:e59c8e839560 | 1033 | #define ADC_CR_JADSTART_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1034 | #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1035 | #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ |
| AnnaBridge | 163:e59c8e839560 | 1036 | #define ADC_CR_ADSTP_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 1037 | #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1038 | #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ |
| AnnaBridge | 163:e59c8e839560 | 1039 | #define ADC_CR_JADSTP_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 1040 | #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1041 | #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ |
| AnnaBridge | 163:e59c8e839560 | 1042 | #define ADC_CR_ADVREGEN_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 1043 | #define ADC_CR_ADVREGEN_Msk (0x3U << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1044 | #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ |
| AnnaBridge | 163:e59c8e839560 | 1045 | #define ADC_CR_ADVREGEN_0 (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1046 | #define ADC_CR_ADVREGEN_1 (0x2U << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1047 | #define ADC_CR_ADCALDIF_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 1048 | #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1049 | #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ |
| AnnaBridge | 163:e59c8e839560 | 1050 | #define ADC_CR_ADCAL_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 1051 | #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1052 | #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| AnnaBridge | 163:e59c8e839560 | 1053 | |
| AnnaBridge | 163:e59c8e839560 | 1054 | /******************** Bit definition for ADC_CFGR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1055 | #define ADC_CFGR_DMAEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1056 | #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1057 | #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ |
| AnnaBridge | 163:e59c8e839560 | 1058 | #define ADC_CFGR_DMACFG_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 1059 | #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1060 | #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1061 | |
| AnnaBridge | 163:e59c8e839560 | 1062 | #define ADC_CFGR_RES_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1063 | #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 163:e59c8e839560 | 1064 | #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ |
| AnnaBridge | 163:e59c8e839560 | 1065 | #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1066 | #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1067 | |
| AnnaBridge | 163:e59c8e839560 | 1068 | #define ADC_CFGR_ALIGN_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 1069 | #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1070 | #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ |
| AnnaBridge | 163:e59c8e839560 | 1071 | |
| AnnaBridge | 163:e59c8e839560 | 1072 | #define ADC_CFGR_EXTSEL_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1073 | #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1074 | #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| AnnaBridge | 163:e59c8e839560 | 1075 | #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1076 | #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1077 | #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1078 | #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1079 | |
| AnnaBridge | 163:e59c8e839560 | 1080 | #define ADC_CFGR_EXTEN_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 1081 | #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 1082 | #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
| AnnaBridge | 163:e59c8e839560 | 1083 | #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1084 | #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1085 | |
| AnnaBridge | 163:e59c8e839560 | 1086 | #define ADC_CFGR_OVRMOD_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1087 | #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1088 | #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1089 | #define ADC_CFGR_CONT_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 1090 | #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1091 | #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| AnnaBridge | 163:e59c8e839560 | 1092 | #define ADC_CFGR_AUTDLY_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 1093 | #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1094 | #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ |
| AnnaBridge | 163:e59c8e839560 | 1095 | |
| AnnaBridge | 163:e59c8e839560 | 1096 | #define ADC_CFGR_DISCEN_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1097 | #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1098 | #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| AnnaBridge | 163:e59c8e839560 | 1099 | |
| AnnaBridge | 163:e59c8e839560 | 1100 | #define ADC_CFGR_DISCNUM_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 1101 | #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1102 | #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ |
| AnnaBridge | 163:e59c8e839560 | 1103 | #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1104 | #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1105 | #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1106 | |
| AnnaBridge | 163:e59c8e839560 | 1107 | #define ADC_CFGR_JDISCEN_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 1108 | #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1109 | #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ |
| AnnaBridge | 163:e59c8e839560 | 1110 | #define ADC_CFGR_JQM_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 1111 | #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1112 | #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ |
| AnnaBridge | 163:e59c8e839560 | 1113 | #define ADC_CFGR_AWD1SGL_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 1114 | #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1115 | #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| AnnaBridge | 163:e59c8e839560 | 1116 | #define ADC_CFGR_AWD1EN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 1117 | #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1118 | #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| AnnaBridge | 163:e59c8e839560 | 1119 | #define ADC_CFGR_JAWD1EN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1120 | #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1121 | #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
| AnnaBridge | 163:e59c8e839560 | 1122 | #define ADC_CFGR_JAUTO_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 1123 | #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1124 | #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
| AnnaBridge | 163:e59c8e839560 | 1125 | |
| AnnaBridge | 163:e59c8e839560 | 1126 | #define ADC_CFGR_AWD1CH_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1127 | #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1128 | #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1129 | #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1130 | #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1131 | #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1132 | #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1133 | #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1134 | |
| AnnaBridge | 163:e59c8e839560 | 1135 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 1136 | #define ADC_CFGR_AUTOFF_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 1137 | #define ADC_CFGR_AUTOFF_Msk (0x1U << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1138 | #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */ |
| AnnaBridge | 163:e59c8e839560 | 1139 | |
| AnnaBridge | 163:e59c8e839560 | 1140 | /******************** Bit definition for ADC_SMPR1 register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 1141 | #define ADC_SMPR1_SMP0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1142 | #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 1143 | #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1144 | #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1145 | #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1146 | #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1147 | |
| AnnaBridge | 163:e59c8e839560 | 1148 | #define ADC_SMPR1_SMP1_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1149 | #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 163:e59c8e839560 | 1150 | #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1151 | #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1152 | #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1153 | #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1154 | |
| AnnaBridge | 163:e59c8e839560 | 1155 | #define ADC_SMPR1_SMP2_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1156 | #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1157 | #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1158 | #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1159 | #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1160 | #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1161 | |
| AnnaBridge | 163:e59c8e839560 | 1162 | #define ADC_SMPR1_SMP3_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 1163 | #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 163:e59c8e839560 | 1164 | #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1165 | #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1166 | #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1167 | #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1168 | |
| AnnaBridge | 163:e59c8e839560 | 1169 | #define ADC_SMPR1_SMP4_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1170 | #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 1171 | #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1172 | #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1173 | #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1174 | #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1175 | |
| AnnaBridge | 163:e59c8e839560 | 1176 | #define ADC_SMPR1_SMP5_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 1177 | #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 163:e59c8e839560 | 1178 | #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1179 | #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1180 | #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1181 | #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1182 | |
| AnnaBridge | 163:e59c8e839560 | 1183 | #define ADC_SMPR1_SMP6_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1184 | #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1185 | #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1186 | #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1187 | #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1188 | #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1189 | |
| AnnaBridge | 163:e59c8e839560 | 1190 | #define ADC_SMPR1_SMP7_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 1191 | #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 163:e59c8e839560 | 1192 | #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1193 | #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1194 | #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1195 | #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1196 | |
| AnnaBridge | 163:e59c8e839560 | 1197 | #define ADC_SMPR1_SMP8_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1198 | #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1199 | #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1200 | #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1201 | #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1202 | #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1203 | |
| AnnaBridge | 163:e59c8e839560 | 1204 | #define ADC_SMPR1_SMP9_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 1205 | #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1206 | #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1207 | #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1208 | #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1209 | #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1210 | |
| AnnaBridge | 163:e59c8e839560 | 1211 | /******************** Bit definition for ADC_SMPR2 register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 1212 | #define ADC_SMPR2_SMP10_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1213 | #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 1214 | #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1215 | #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1216 | #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1217 | #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1218 | |
| AnnaBridge | 163:e59c8e839560 | 1219 | #define ADC_SMPR2_SMP11_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1220 | #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 163:e59c8e839560 | 1221 | #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1222 | #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1223 | #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1224 | #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1225 | |
| AnnaBridge | 163:e59c8e839560 | 1226 | #define ADC_SMPR2_SMP12_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1227 | #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1228 | #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1229 | #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1230 | #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1231 | #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1232 | |
| AnnaBridge | 163:e59c8e839560 | 1233 | #define ADC_SMPR2_SMP13_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 1234 | #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 163:e59c8e839560 | 1235 | #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1236 | #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1237 | #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1238 | #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1239 | |
| AnnaBridge | 163:e59c8e839560 | 1240 | #define ADC_SMPR2_SMP14_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1241 | #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 1242 | #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1243 | #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1244 | #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1245 | #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1246 | |
| AnnaBridge | 163:e59c8e839560 | 1247 | #define ADC_SMPR2_SMP15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 1248 | #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 163:e59c8e839560 | 1249 | #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1250 | #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1251 | #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1252 | #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1253 | |
| AnnaBridge | 163:e59c8e839560 | 1254 | #define ADC_SMPR2_SMP16_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1255 | #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1256 | #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1257 | #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1258 | #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1259 | #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1260 | |
| AnnaBridge | 163:e59c8e839560 | 1261 | #define ADC_SMPR2_SMP17_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 1262 | #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 163:e59c8e839560 | 1263 | #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1264 | #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1265 | #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1266 | #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1267 | |
| AnnaBridge | 163:e59c8e839560 | 1268 | #define ADC_SMPR2_SMP18_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1269 | #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1270 | #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ |
| AnnaBridge | 163:e59c8e839560 | 1271 | #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1272 | #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1273 | #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1274 | |
| AnnaBridge | 163:e59c8e839560 | 1275 | /******************** Bit definition for ADC_TR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 1276 | #define ADC_TR1_LT1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1277 | #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 1278 | #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ |
| AnnaBridge | 163:e59c8e839560 | 1279 | #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1280 | #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1281 | #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1282 | #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1283 | #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1284 | #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1285 | #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1286 | #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1287 | #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1288 | #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1289 | #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1290 | #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1291 | |
| AnnaBridge | 163:e59c8e839560 | 1292 | #define ADC_TR1_HT1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1293 | #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1294 | #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ |
| AnnaBridge | 163:e59c8e839560 | 1295 | #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1296 | #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1297 | #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1298 | #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1299 | #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1300 | #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1301 | #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1302 | #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1303 | #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1304 | #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1305 | #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1306 | #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1307 | |
| AnnaBridge | 163:e59c8e839560 | 1308 | /******************** Bit definition for ADC_TR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 1309 | #define ADC_TR2_LT2_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1310 | #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 1311 | #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ |
| AnnaBridge | 163:e59c8e839560 | 1312 | #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1313 | #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1314 | #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1315 | #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1316 | #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1317 | #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1318 | #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1319 | #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1320 | |
| AnnaBridge | 163:e59c8e839560 | 1321 | #define ADC_TR2_HT2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1322 | #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1323 | #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ |
| AnnaBridge | 163:e59c8e839560 | 1324 | #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1325 | #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1326 | #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1327 | #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1328 | #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1329 | #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1330 | #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1331 | #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1332 | |
| AnnaBridge | 163:e59c8e839560 | 1333 | /******************** Bit definition for ADC_TR3 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 1334 | #define ADC_TR3_LT3_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1335 | #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 1336 | #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ |
| AnnaBridge | 163:e59c8e839560 | 1337 | #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1338 | #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1339 | #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1340 | #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1341 | #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1342 | #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1343 | #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1344 | #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1345 | |
| AnnaBridge | 163:e59c8e839560 | 1346 | #define ADC_TR3_HT3_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1347 | #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1348 | #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ |
| AnnaBridge | 163:e59c8e839560 | 1349 | #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1350 | #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1351 | #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1352 | #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1353 | #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1354 | #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1355 | #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1356 | #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1357 | |
| AnnaBridge | 163:e59c8e839560 | 1358 | /******************** Bit definition for ADC_SQR1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1359 | #define ADC_SQR1_L_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1360 | #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 1361 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
| AnnaBridge | 163:e59c8e839560 | 1362 | #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1363 | #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1364 | #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1365 | #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1366 | |
| AnnaBridge | 163:e59c8e839560 | 1367 | #define ADC_SQR1_SQ1_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1368 | #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1369 | #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
| AnnaBridge | 163:e59c8e839560 | 1370 | #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1371 | #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1372 | #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1373 | #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1374 | #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1375 | |
| AnnaBridge | 163:e59c8e839560 | 1376 | #define ADC_SQR1_SQ2_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1377 | #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 163:e59c8e839560 | 1378 | #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
| AnnaBridge | 163:e59c8e839560 | 1379 | #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1380 | #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1381 | #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1382 | #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1383 | #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1384 | |
| AnnaBridge | 163:e59c8e839560 | 1385 | #define ADC_SQR1_SQ3_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1386 | #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1387 | #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
| AnnaBridge | 163:e59c8e839560 | 1388 | #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1389 | #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1390 | #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1391 | #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1392 | #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1393 | |
| AnnaBridge | 163:e59c8e839560 | 1394 | #define ADC_SQR1_SQ4_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1395 | #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1396 | #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
| AnnaBridge | 163:e59c8e839560 | 1397 | #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1398 | #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1399 | #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1400 | #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1401 | #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1402 | |
| AnnaBridge | 163:e59c8e839560 | 1403 | /******************** Bit definition for ADC_SQR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1404 | #define ADC_SQR2_SQ5_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1405 | #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 1406 | #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
| AnnaBridge | 163:e59c8e839560 | 1407 | #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1408 | #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1409 | #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1410 | #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1411 | #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1412 | |
| AnnaBridge | 163:e59c8e839560 | 1413 | #define ADC_SQR2_SQ6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1414 | #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1415 | #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
| AnnaBridge | 163:e59c8e839560 | 1416 | #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1417 | #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1418 | #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1419 | #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1420 | #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1421 | |
| AnnaBridge | 163:e59c8e839560 | 1422 | #define ADC_SQR2_SQ7_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1423 | #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 163:e59c8e839560 | 1424 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
| AnnaBridge | 163:e59c8e839560 | 1425 | #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1426 | #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1427 | #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1428 | #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1429 | #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1430 | |
| AnnaBridge | 163:e59c8e839560 | 1431 | #define ADC_SQR2_SQ8_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1432 | #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1433 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
| AnnaBridge | 163:e59c8e839560 | 1434 | #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1435 | #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1436 | #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1437 | #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1438 | #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1439 | |
| AnnaBridge | 163:e59c8e839560 | 1440 | #define ADC_SQR2_SQ9_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1441 | #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1442 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
| AnnaBridge | 163:e59c8e839560 | 1443 | #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1444 | #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1445 | #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1446 | #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1447 | #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1448 | |
| AnnaBridge | 163:e59c8e839560 | 1449 | /******************** Bit definition for ADC_SQR3 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1450 | #define ADC_SQR3_SQ10_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1451 | #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 1452 | #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
| AnnaBridge | 163:e59c8e839560 | 1453 | #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1454 | #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1455 | #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1456 | #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1457 | #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1458 | |
| AnnaBridge | 163:e59c8e839560 | 1459 | #define ADC_SQR3_SQ11_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1460 | #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1461 | #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ |
| AnnaBridge | 163:e59c8e839560 | 1462 | #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1463 | #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1464 | #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1465 | #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1466 | #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1467 | |
| AnnaBridge | 163:e59c8e839560 | 1468 | #define ADC_SQR3_SQ12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 1469 | #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 163:e59c8e839560 | 1470 | #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
| AnnaBridge | 163:e59c8e839560 | 1471 | #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1472 | #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1473 | #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1474 | #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1475 | #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1476 | |
| AnnaBridge | 163:e59c8e839560 | 1477 | #define ADC_SQR3_SQ13_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1478 | #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1479 | #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
| AnnaBridge | 163:e59c8e839560 | 1480 | #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1481 | #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1482 | #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1483 | #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1484 | #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1485 | |
| AnnaBridge | 163:e59c8e839560 | 1486 | #define ADC_SQR3_SQ14_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1487 | #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1488 | #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
| AnnaBridge | 163:e59c8e839560 | 1489 | #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1490 | #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1491 | #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1492 | #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1493 | #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1494 | |
| AnnaBridge | 163:e59c8e839560 | 1495 | /******************** Bit definition for ADC_SQR4 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1496 | #define ADC_SQR4_SQ15_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1497 | #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 1498 | #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
| AnnaBridge | 163:e59c8e839560 | 1499 | #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1500 | #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1501 | #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1502 | #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1503 | #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1504 | |
| AnnaBridge | 163:e59c8e839560 | 1505 | #define ADC_SQR4_SQ16_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1506 | #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1507 | #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
| AnnaBridge | 163:e59c8e839560 | 1508 | #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1509 | #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1510 | #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1511 | #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1512 | #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1513 | |
| AnnaBridge | 163:e59c8e839560 | 1514 | /******************** Bit definition for ADC_DR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 1515 | #define ADC_DR_RDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1516 | #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1517 | #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 1518 | #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1519 | #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1520 | #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1521 | #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1522 | #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1523 | #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1524 | #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1525 | #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1526 | #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1527 | #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1528 | #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1529 | #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1530 | #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1531 | #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1532 | #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1533 | #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1534 | |
| AnnaBridge | 163:e59c8e839560 | 1535 | /******************** Bit definition for ADC_JSQR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1536 | #define ADC_JSQR_JL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1537 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 1538 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
| AnnaBridge | 163:e59c8e839560 | 1539 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1540 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1541 | |
| AnnaBridge | 163:e59c8e839560 | 1542 | #define ADC_JSQR_JEXTSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 1543 | #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ |
| AnnaBridge | 163:e59c8e839560 | 1544 | #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
| AnnaBridge | 163:e59c8e839560 | 1545 | #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1546 | #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1547 | #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1548 | #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1549 | |
| AnnaBridge | 163:e59c8e839560 | 1550 | #define ADC_JSQR_JEXTEN_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1551 | #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 1552 | #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ |
| AnnaBridge | 163:e59c8e839560 | 1553 | #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1554 | #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1555 | |
| AnnaBridge | 163:e59c8e839560 | 1556 | #define ADC_JSQR_JSQ1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 1557 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 163:e59c8e839560 | 1558 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
| AnnaBridge | 163:e59c8e839560 | 1559 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1560 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1561 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1562 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1563 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1564 | |
| AnnaBridge | 163:e59c8e839560 | 1565 | #define ADC_JSQR_JSQ2_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 1566 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ |
| AnnaBridge | 163:e59c8e839560 | 1567 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
| AnnaBridge | 163:e59c8e839560 | 1568 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1569 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1570 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1571 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1572 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1573 | |
| AnnaBridge | 163:e59c8e839560 | 1574 | #define ADC_JSQR_JSQ3_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 1575 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 1576 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
| AnnaBridge | 163:e59c8e839560 | 1577 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1578 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1579 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1580 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1581 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1582 | |
| AnnaBridge | 163:e59c8e839560 | 1583 | #define ADC_JSQR_JSQ4_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1584 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1585 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
| AnnaBridge | 163:e59c8e839560 | 1586 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1587 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1588 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1589 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1590 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1591 | |
| AnnaBridge | 163:e59c8e839560 | 1592 | |
| AnnaBridge | 163:e59c8e839560 | 1593 | /******************** Bit definition for ADC_OFR1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1594 | #define ADC_OFR1_OFFSET1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1595 | #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 1596 | #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ |
| AnnaBridge | 163:e59c8e839560 | 1597 | #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1598 | #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1599 | #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1600 | #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1601 | #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1602 | #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1603 | #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1604 | #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1605 | #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1606 | #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1607 | #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1608 | #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1609 | |
| AnnaBridge | 163:e59c8e839560 | 1610 | #define ADC_OFR1_OFFSET1_CH_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1611 | #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1612 | #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1613 | #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1614 | #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1615 | #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1616 | #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1617 | #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1618 | |
| AnnaBridge | 163:e59c8e839560 | 1619 | #define ADC_OFR1_OFFSET1_EN_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 1620 | #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1621 | #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 1622 | |
| AnnaBridge | 163:e59c8e839560 | 1623 | /******************** Bit definition for ADC_OFR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1624 | #define ADC_OFR2_OFFSET2_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1625 | #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 1626 | #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ |
| AnnaBridge | 163:e59c8e839560 | 1627 | #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1628 | #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1629 | #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1630 | #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1631 | #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1632 | #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1633 | #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1634 | #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1635 | #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1636 | #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1637 | #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1638 | #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1639 | |
| AnnaBridge | 163:e59c8e839560 | 1640 | #define ADC_OFR2_OFFSET2_CH_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1641 | #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1642 | #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1643 | #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1644 | #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1645 | #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1646 | #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1647 | #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1648 | |
| AnnaBridge | 163:e59c8e839560 | 1649 | #define ADC_OFR2_OFFSET2_EN_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 1650 | #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1651 | #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 1652 | |
| AnnaBridge | 163:e59c8e839560 | 1653 | /******************** Bit definition for ADC_OFR3 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1654 | #define ADC_OFR3_OFFSET3_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1655 | #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 1656 | #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ |
| AnnaBridge | 163:e59c8e839560 | 1657 | #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1658 | #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1659 | #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1660 | #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1661 | #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1662 | #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1663 | #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1664 | #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1665 | #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1666 | #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1667 | #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1668 | #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1669 | |
| AnnaBridge | 163:e59c8e839560 | 1670 | #define ADC_OFR3_OFFSET3_CH_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1671 | #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1672 | #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1673 | #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1674 | #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1675 | #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1676 | #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1677 | #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1678 | |
| AnnaBridge | 163:e59c8e839560 | 1679 | #define ADC_OFR3_OFFSET3_EN_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 1680 | #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1681 | #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ |
| AnnaBridge | 163:e59c8e839560 | 1682 | |
| AnnaBridge | 163:e59c8e839560 | 1683 | /******************** Bit definition for ADC_OFR4 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1684 | #define ADC_OFR4_OFFSET4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1685 | #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 1686 | #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ |
| AnnaBridge | 163:e59c8e839560 | 1687 | #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1688 | #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1689 | #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1690 | #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1691 | #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1692 | #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1693 | #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1694 | #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1695 | #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1696 | #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1697 | #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1698 | #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1699 | |
| AnnaBridge | 163:e59c8e839560 | 1700 | #define ADC_OFR4_OFFSET4_CH_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1701 | #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1702 | #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1703 | #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1704 | #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1705 | #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1706 | #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1707 | #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1708 | |
| AnnaBridge | 163:e59c8e839560 | 1709 | #define ADC_OFR4_OFFSET4_EN_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 1710 | #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1711 | #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ |
| AnnaBridge | 163:e59c8e839560 | 1712 | |
| AnnaBridge | 163:e59c8e839560 | 1713 | /******************** Bit definition for ADC_JDR1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1714 | #define ADC_JDR1_JDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1715 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1716 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 1717 | #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1718 | #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1719 | #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1720 | #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1721 | #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1722 | #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1723 | #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1724 | #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1725 | #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1726 | #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1727 | #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1728 | #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1729 | #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1730 | #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1731 | #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1732 | #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1733 | |
| AnnaBridge | 163:e59c8e839560 | 1734 | /******************** Bit definition for ADC_JDR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1735 | #define ADC_JDR2_JDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1736 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1737 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 1738 | #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1739 | #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1740 | #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1741 | #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1742 | #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1743 | #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1744 | #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1745 | #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1746 | #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1747 | #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1748 | #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1749 | #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1750 | #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1751 | #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1752 | #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1753 | #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1754 | |
| AnnaBridge | 163:e59c8e839560 | 1755 | /******************** Bit definition for ADC_JDR3 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1756 | #define ADC_JDR3_JDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1757 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1758 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 1759 | #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1760 | #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1761 | #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1762 | #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1763 | #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1764 | #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1765 | #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1766 | #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1767 | #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1768 | #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1769 | #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1770 | #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1771 | #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1772 | #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1773 | #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1774 | #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1775 | |
| AnnaBridge | 163:e59c8e839560 | 1776 | /******************** Bit definition for ADC_JDR4 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 1777 | #define ADC_JDR4_JDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1778 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1779 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 1780 | #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1781 | #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1782 | #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1783 | #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1784 | #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1785 | #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1786 | #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1787 | #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1788 | #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1789 | #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1790 | #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1791 | #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1792 | #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1793 | #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1794 | #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1795 | #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1796 | |
| AnnaBridge | 163:e59c8e839560 | 1797 | /******************** Bit definition for ADC_AWD2CR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 1798 | #define ADC_AWD2CR_AWD2CH_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1799 | #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1800 | #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1801 | #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1802 | #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1803 | #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1804 | #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1805 | #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1806 | #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1807 | #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1808 | #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1809 | #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1810 | #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1811 | #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1812 | #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1813 | #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1814 | #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1815 | #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1816 | #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1817 | #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1818 | #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1819 | #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1820 | |
| AnnaBridge | 163:e59c8e839560 | 1821 | /******************** Bit definition for ADC_AWD3CR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 1822 | #define ADC_AWD3CR_AWD3CH_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1823 | #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1824 | #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ |
| AnnaBridge | 163:e59c8e839560 | 1825 | #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1826 | #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1827 | #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1828 | #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1829 | #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1830 | #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1831 | #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1832 | #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1833 | #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1834 | #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1835 | #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1836 | #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1837 | #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1838 | #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1839 | #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1840 | #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1841 | #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1842 | #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1843 | #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1844 | |
| AnnaBridge | 163:e59c8e839560 | 1845 | /******************** Bit definition for ADC_DIFSEL register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 1846 | #define ADC_DIFSEL_DIFSEL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1847 | #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 1848 | #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ |
| AnnaBridge | 163:e59c8e839560 | 1849 | #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1850 | #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1851 | #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1852 | #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1853 | #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1854 | #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1855 | #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1856 | #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1857 | #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1858 | #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1859 | #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1860 | #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 1861 | #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 1862 | #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 1863 | #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 1864 | #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 1865 | #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1866 | #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1867 | #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1868 | |
| AnnaBridge | 163:e59c8e839560 | 1869 | /******************** Bit definition for ADC_CALFACT register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 1870 | #define ADC_CALFACT_CALFACT_S_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1871 | #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 163:e59c8e839560 | 1872 | #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ |
| AnnaBridge | 163:e59c8e839560 | 1873 | #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1874 | #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1875 | #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1876 | #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1877 | #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1878 | #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1879 | #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1880 | |
| AnnaBridge | 163:e59c8e839560 | 1881 | #define ADC_CALFACT_CALFACT_D_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1882 | #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 1883 | #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ |
| AnnaBridge | 163:e59c8e839560 | 1884 | #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1885 | #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1886 | #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1887 | #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1888 | #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1889 | #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1890 | #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1891 | |
| AnnaBridge | 163:e59c8e839560 | 1892 | /************************* ADC Common registers *****************************/ |
| AnnaBridge | 163:e59c8e839560 | 1893 | /*************** Bit definition for ADC12_COMMON_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 1894 | #define ADC12_CSR_ADRDY_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1895 | #define ADC12_CSR_ADRDY_MST_Msk (0x1U << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1896 | #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ |
| AnnaBridge | 163:e59c8e839560 | 1897 | #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 1898 | #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1899 | #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1900 | #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 1901 | #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1902 | #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1903 | #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1904 | #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1905 | #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1906 | #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 1907 | #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1908 | #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1909 | #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 1910 | #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1911 | #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1912 | #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1913 | #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1914 | #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1915 | #define ADC12_CSR_AWD1_MST_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 1916 | #define ADC12_CSR_AWD1_MST_Msk (0x1U << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1917 | #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1918 | #define ADC12_CSR_AWD2_MST_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 1919 | #define ADC12_CSR_AWD2_MST_Msk (0x1U << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1920 | #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1921 | #define ADC12_CSR_AWD3_MST_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 1922 | #define ADC12_CSR_AWD3_MST_Msk (0x1U << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1923 | #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1924 | #define ADC12_CSR_JQOVF_MST_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 1925 | #define ADC12_CSR_JQOVF_MST_Msk (0x1U << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1926 | #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1927 | #define ADC12_CSR_ADRDY_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1928 | #define ADC12_CSR_ADRDY_SLV_Msk (0x1U << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1929 | #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ |
| AnnaBridge | 163:e59c8e839560 | 1930 | #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 1931 | #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 1932 | #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1933 | #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 1934 | #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 1935 | #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1936 | #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 1937 | #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 1938 | #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1939 | #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 1940 | #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 1941 | #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1942 | #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 1943 | #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 1944 | #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1945 | #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 1946 | #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 1947 | #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1948 | #define ADC12_CSR_AWD1_SLV_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 1949 | #define ADC12_CSR_AWD1_SLV_Msk (0x1U << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 1950 | #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1951 | #define ADC12_CSR_AWD2_SLV_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 1952 | #define ADC12_CSR_AWD2_SLV_Msk (0x1U << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1953 | #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1954 | #define ADC12_CSR_AWD3_SLV_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 1955 | #define ADC12_CSR_AWD3_SLV_Msk (0x1U << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1956 | #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1957 | #define ADC12_CSR_JQOVF_SLV_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 1958 | #define ADC12_CSR_JQOVF_SLV_Msk (0x1U << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 1959 | #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1960 | |
| AnnaBridge | 163:e59c8e839560 | 1961 | /*************** Bit definition for ADC34_COMMON_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 1962 | #define ADC34_CSR_ADRDY_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 1963 | #define ADC34_CSR_ADRDY_MST_Msk (0x1U << ADC34_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 1964 | #define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ |
| AnnaBridge | 163:e59c8e839560 | 1965 | #define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 1966 | #define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 1967 | #define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1968 | #define ADC34_CSR_ADRDY_EOC_MST_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 1969 | #define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 1970 | #define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1971 | #define ADC34_CSR_ADRDY_EOS_MST_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 1972 | #define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 1973 | #define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1974 | #define ADC34_CSR_ADRDY_OVR_MST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 1975 | #define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 1976 | #define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1977 | #define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 1978 | #define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 1979 | #define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1980 | #define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 1981 | #define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 1982 | #define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1983 | #define ADC34_CSR_AWD1_MST_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 1984 | #define ADC34_CSR_AWD1_MST_Msk (0x1U << ADC34_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 1985 | #define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1986 | #define ADC34_CSR_AWD2_MST_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 1987 | #define ADC34_CSR_AWD2_MST_Msk (0x1U << ADC34_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 1988 | #define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1989 | #define ADC34_CSR_AWD3_MST_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 1990 | #define ADC34_CSR_AWD3_MST_Msk (0x1U << ADC34_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 1991 | #define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1992 | #define ADC34_CSR_JQOVF_MST_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 1993 | #define ADC34_CSR_JQOVF_MST_Msk (0x1U << ADC34_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 1994 | #define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 1995 | #define ADC34_CSR_ADRDY_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 1996 | #define ADC34_CSR_ADRDY_SLV_Msk (0x1U << ADC34_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 1997 | #define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ |
| AnnaBridge | 163:e59c8e839560 | 1998 | #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 1999 | #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2000 | #define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2001 | #define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2002 | #define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2003 | #define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2004 | #define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 2005 | #define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2006 | #define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2007 | #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 2008 | #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2009 | #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2010 | #define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 2011 | #define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 2012 | #define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2013 | #define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 2014 | #define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2015 | #define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2016 | #define ADC34_CSR_AWD1_SLV_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 2017 | #define ADC34_CSR_AWD1_SLV_Msk (0x1U << ADC34_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2018 | #define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2019 | #define ADC34_CSR_AWD2_SLV_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2020 | #define ADC34_CSR_AWD2_SLV_Msk (0x1U << ADC34_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2021 | #define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2022 | #define ADC34_CSR_AWD3_SLV_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 2023 | #define ADC34_CSR_AWD3_SLV_Msk (0x1U << ADC34_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2024 | #define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2025 | #define ADC34_CSR_JQOVF_SLV_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 2026 | #define ADC34_CSR_JQOVF_SLV_Msk (0x1U << ADC34_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2027 | #define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2028 | |
| AnnaBridge | 163:e59c8e839560 | 2029 | /*************** Bit definition for ADC12_COMMON_CCR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2030 | #define ADC12_CCR_MULTI_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2031 | #define ADC12_CCR_MULTI_Msk (0x1FU << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 2032 | #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */ |
| AnnaBridge | 163:e59c8e839560 | 2033 | #define ADC12_CCR_MULTI_0 (0x01U << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2034 | #define ADC12_CCR_MULTI_1 (0x02U << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2035 | #define ADC12_CCR_MULTI_2 (0x04U << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2036 | #define ADC12_CCR_MULTI_3 (0x08U << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2037 | #define ADC12_CCR_MULTI_4 (0x10U << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2038 | #define ADC12_CCR_DELAY_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2039 | #define ADC12_CCR_DELAY_Msk (0xFU << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 2040 | #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ |
| AnnaBridge | 163:e59c8e839560 | 2041 | #define ADC12_CCR_DELAY_0 (0x1U << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2042 | #define ADC12_CCR_DELAY_1 (0x2U << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2043 | #define ADC12_CCR_DELAY_2 (0x4U << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2044 | #define ADC12_CCR_DELAY_3 (0x8U << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2045 | #define ADC12_CCR_DMACFG_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 2046 | #define ADC12_CCR_DMACFG_Msk (0x1U << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2047 | #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */ |
| AnnaBridge | 163:e59c8e839560 | 2048 | #define ADC12_CCR_MDMA_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2049 | #define ADC12_CCR_MDMA_Msk (0x3U << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2050 | #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */ |
| AnnaBridge | 163:e59c8e839560 | 2051 | #define ADC12_CCR_MDMA_0 (0x1U << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2052 | #define ADC12_CCR_MDMA_1 (0x2U << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2053 | #define ADC12_CCR_CKMODE_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2054 | #define ADC12_CCR_CKMODE_Msk (0x3U << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2055 | #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */ |
| AnnaBridge | 163:e59c8e839560 | 2056 | #define ADC12_CCR_CKMODE_0 (0x1U << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2057 | #define ADC12_CCR_CKMODE_1 (0x2U << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2058 | #define ADC12_CCR_VREFEN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 2059 | #define ADC12_CCR_VREFEN_Msk (0x1U << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2060 | #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */ |
| AnnaBridge | 163:e59c8e839560 | 2061 | #define ADC12_CCR_TSEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 2062 | #define ADC12_CCR_TSEN_Msk (0x1U << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2063 | #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */ |
| AnnaBridge | 163:e59c8e839560 | 2064 | #define ADC12_CCR_VBATEN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2065 | #define ADC12_CCR_VBATEN_Msk (0x1U << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2066 | #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */ |
| AnnaBridge | 163:e59c8e839560 | 2067 | |
| AnnaBridge | 163:e59c8e839560 | 2068 | /*************** Bit definition for ADC34_COMMON_CCR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2069 | #define ADC34_CCR_MULTI_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2070 | #define ADC34_CCR_MULTI_Msk (0x1FU << ADC34_CCR_MULTI_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 2071 | #define ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk /*!< Multi ADC mode selection */ |
| AnnaBridge | 163:e59c8e839560 | 2072 | #define ADC34_CCR_MULTI_0 (0x01U << ADC34_CCR_MULTI_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2073 | #define ADC34_CCR_MULTI_1 (0x02U << ADC34_CCR_MULTI_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2074 | #define ADC34_CCR_MULTI_2 (0x04U << ADC34_CCR_MULTI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2075 | #define ADC34_CCR_MULTI_3 (0x08U << ADC34_CCR_MULTI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2076 | #define ADC34_CCR_MULTI_4 (0x10U << ADC34_CCR_MULTI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2077 | |
| AnnaBridge | 163:e59c8e839560 | 2078 | #define ADC34_CCR_DELAY_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2079 | #define ADC34_CCR_DELAY_Msk (0xFU << ADC34_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 2080 | #define ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ |
| AnnaBridge | 163:e59c8e839560 | 2081 | #define ADC34_CCR_DELAY_0 (0x1U << ADC34_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2082 | #define ADC34_CCR_DELAY_1 (0x2U << ADC34_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2083 | #define ADC34_CCR_DELAY_2 (0x4U << ADC34_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2084 | #define ADC34_CCR_DELAY_3 (0x8U << ADC34_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2085 | |
| AnnaBridge | 163:e59c8e839560 | 2086 | #define ADC34_CCR_DMACFG_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 2087 | #define ADC34_CCR_DMACFG_Msk (0x1U << ADC34_CCR_DMACFG_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2088 | #define ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */ |
| AnnaBridge | 163:e59c8e839560 | 2089 | #define ADC34_CCR_MDMA_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2090 | #define ADC34_CCR_MDMA_Msk (0x3U << ADC34_CCR_MDMA_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2091 | #define ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */ |
| AnnaBridge | 163:e59c8e839560 | 2092 | #define ADC34_CCR_MDMA_0 (0x1U << ADC34_CCR_MDMA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2093 | #define ADC34_CCR_MDMA_1 (0x2U << ADC34_CCR_MDMA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2094 | |
| AnnaBridge | 163:e59c8e839560 | 2095 | #define ADC34_CCR_CKMODE_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2096 | #define ADC34_CCR_CKMODE_Msk (0x3U << ADC34_CCR_CKMODE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2097 | #define ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk /*!< ADC clock mode */ |
| AnnaBridge | 163:e59c8e839560 | 2098 | #define ADC34_CCR_CKMODE_0 (0x1U << ADC34_CCR_CKMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2099 | #define ADC34_CCR_CKMODE_1 (0x2U << ADC34_CCR_CKMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2100 | |
| AnnaBridge | 163:e59c8e839560 | 2101 | #define ADC34_CCR_VREFEN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 2102 | #define ADC34_CCR_VREFEN_Msk (0x1U << ADC34_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2103 | #define ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk /*!< VREFINT enable */ |
| AnnaBridge | 163:e59c8e839560 | 2104 | #define ADC34_CCR_TSEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 2105 | #define ADC34_CCR_TSEN_Msk (0x1U << ADC34_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2106 | #define ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk /*!< Temperature sensor enable */ |
| AnnaBridge | 163:e59c8e839560 | 2107 | #define ADC34_CCR_VBATEN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2108 | #define ADC34_CCR_VBATEN_Msk (0x1U << ADC34_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2109 | #define ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk /*!< VBAT enable */ |
| AnnaBridge | 163:e59c8e839560 | 2110 | |
| AnnaBridge | 163:e59c8e839560 | 2111 | /*************** Bit definition for ADC12_COMMON_CDR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2112 | #define ADC12_CDR_RDATA_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2113 | #define ADC12_CDR_RDATA_MST_Msk (0xFFFFU << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 2114 | #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2115 | #define ADC12_CDR_RDATA_MST_0 (0x0001U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2116 | #define ADC12_CDR_RDATA_MST_1 (0x0002U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2117 | #define ADC12_CDR_RDATA_MST_2 (0x0004U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2118 | #define ADC12_CDR_RDATA_MST_3 (0x0008U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2119 | #define ADC12_CDR_RDATA_MST_4 (0x0010U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2120 | #define ADC12_CDR_RDATA_MST_5 (0x0020U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2121 | #define ADC12_CDR_RDATA_MST_6 (0x0040U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2122 | #define ADC12_CDR_RDATA_MST_7 (0x0080U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2123 | #define ADC12_CDR_RDATA_MST_8 (0x0100U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2124 | #define ADC12_CDR_RDATA_MST_9 (0x0200U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2125 | #define ADC12_CDR_RDATA_MST_10 (0x0400U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2126 | #define ADC12_CDR_RDATA_MST_11 (0x0800U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2127 | #define ADC12_CDR_RDATA_MST_12 (0x1000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2128 | #define ADC12_CDR_RDATA_MST_13 (0x2000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2129 | #define ADC12_CDR_RDATA_MST_14 (0x4000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2130 | #define ADC12_CDR_RDATA_MST_15 (0x8000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2131 | |
| AnnaBridge | 163:e59c8e839560 | 2132 | #define ADC12_CDR_RDATA_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2133 | #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2134 | #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2135 | #define ADC12_CDR_RDATA_SLV_0 (0x0001U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2136 | #define ADC12_CDR_RDATA_SLV_1 (0x0002U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2137 | #define ADC12_CDR_RDATA_SLV_2 (0x0004U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2138 | #define ADC12_CDR_RDATA_SLV_3 (0x0008U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2139 | #define ADC12_CDR_RDATA_SLV_4 (0x0010U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2140 | #define ADC12_CDR_RDATA_SLV_5 (0x0020U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 2141 | #define ADC12_CDR_RDATA_SLV_6 (0x0040U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2142 | #define ADC12_CDR_RDATA_SLV_7 (0x0080U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2143 | #define ADC12_CDR_RDATA_SLV_8 (0x0100U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2144 | #define ADC12_CDR_RDATA_SLV_9 (0x0200U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2145 | #define ADC12_CDR_RDATA_SLV_10 (0x0400U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2146 | #define ADC12_CDR_RDATA_SLV_11 (0x0800U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2147 | #define ADC12_CDR_RDATA_SLV_12 (0x1000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2148 | #define ADC12_CDR_RDATA_SLV_13 (0x2000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2149 | #define ADC12_CDR_RDATA_SLV_14 (0x4000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2150 | #define ADC12_CDR_RDATA_SLV_15 (0x8000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2151 | |
| AnnaBridge | 163:e59c8e839560 | 2152 | /*************** Bit definition for ADC34_COMMON_CDR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2153 | #define ADC34_CDR_RDATA_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2154 | #define ADC34_CDR_RDATA_MST_Msk (0xFFFFU << ADC34_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 2155 | #define ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2156 | #define ADC34_CDR_RDATA_MST_0 (0x0001U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2157 | #define ADC34_CDR_RDATA_MST_1 (0x0002U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2158 | #define ADC34_CDR_RDATA_MST_2 (0x0004U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2159 | #define ADC34_CDR_RDATA_MST_3 (0x0008U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2160 | #define ADC34_CDR_RDATA_MST_4 (0x0010U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2161 | #define ADC34_CDR_RDATA_MST_5 (0x0020U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2162 | #define ADC34_CDR_RDATA_MST_6 (0x0040U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2163 | #define ADC34_CDR_RDATA_MST_7 (0x0080U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2164 | #define ADC34_CDR_RDATA_MST_8 (0x0100U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2165 | #define ADC34_CDR_RDATA_MST_9 (0x0200U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2166 | #define ADC34_CDR_RDATA_MST_10 (0x0400U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2167 | #define ADC34_CDR_RDATA_MST_11 (0x0800U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2168 | #define ADC34_CDR_RDATA_MST_12 (0x1000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2169 | #define ADC34_CDR_RDATA_MST_13 (0x2000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2170 | #define ADC34_CDR_RDATA_MST_14 (0x4000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2171 | #define ADC34_CDR_RDATA_MST_15 (0x8000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2172 | |
| AnnaBridge | 163:e59c8e839560 | 2173 | #define ADC34_CDR_RDATA_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2174 | #define ADC34_CDR_RDATA_SLV_Msk (0xFFFFU << ADC34_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2175 | #define ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */ |
| AnnaBridge | 163:e59c8e839560 | 2176 | #define ADC34_CDR_RDATA_SLV_0 (0x0001U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2177 | #define ADC34_CDR_RDATA_SLV_1 (0x0002U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2178 | #define ADC34_CDR_RDATA_SLV_2 (0x0004U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2179 | #define ADC34_CDR_RDATA_SLV_3 (0x0008U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2180 | #define ADC34_CDR_RDATA_SLV_4 (0x0010U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2181 | #define ADC34_CDR_RDATA_SLV_5 (0x0020U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 2182 | #define ADC34_CDR_RDATA_SLV_6 (0x0040U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2183 | #define ADC34_CDR_RDATA_SLV_7 (0x0080U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2184 | #define ADC34_CDR_RDATA_SLV_8 (0x0100U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2185 | #define ADC34_CDR_RDATA_SLV_9 (0x0200U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2186 | #define ADC34_CDR_RDATA_SLV_10 (0x0400U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2187 | #define ADC34_CDR_RDATA_SLV_11 (0x0800U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2188 | #define ADC34_CDR_RDATA_SLV_12 (0x1000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2189 | #define ADC34_CDR_RDATA_SLV_13 (0x2000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2190 | #define ADC34_CDR_RDATA_SLV_14 (0x4000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2191 | #define ADC34_CDR_RDATA_SLV_15 (0x8000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2192 | |
| AnnaBridge | 163:e59c8e839560 | 2193 | /******************** Bit definition for ADC_CSR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 2194 | #define ADC_CSR_ADRDY_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2195 | #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2196 | #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ |
| AnnaBridge | 163:e59c8e839560 | 2197 | #define ADC_CSR_EOSMP_MST_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2198 | #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2199 | #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ |
| AnnaBridge | 163:e59c8e839560 | 2200 | #define ADC_CSR_EOC_MST_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2201 | #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2202 | #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 2203 | #define ADC_CSR_EOS_MST_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 2204 | #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2205 | #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 2206 | #define ADC_CSR_OVR_MST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2207 | #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2208 | #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 2209 | #define ADC_CSR_JEOC_MST_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 2210 | #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2211 | #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 2212 | #define ADC_CSR_JEOS_MST_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 2213 | #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2214 | #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 2215 | #define ADC_CSR_AWD1_MST_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2216 | #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2217 | #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2218 | #define ADC_CSR_AWD2_MST_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2219 | #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2220 | #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2221 | #define ADC_CSR_AWD3_MST_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2222 | #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2223 | #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2224 | #define ADC_CSR_JQOVF_MST_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2225 | #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2226 | #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ |
| AnnaBridge | 163:e59c8e839560 | 2227 | |
| AnnaBridge | 163:e59c8e839560 | 2228 | #define ADC_CSR_ADRDY_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2229 | #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2230 | #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ |
| AnnaBridge | 163:e59c8e839560 | 2231 | #define ADC_CSR_EOSMP_SLV_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 2232 | #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2233 | #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ |
| AnnaBridge | 163:e59c8e839560 | 2234 | #define ADC_CSR_EOC_SLV_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2235 | #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2236 | #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 2237 | #define ADC_CSR_EOS_SLV_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 2238 | #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2239 | #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 2240 | #define ADC_CSR_OVR_SLV_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 2241 | #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2242 | #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 2243 | #define ADC_CSR_JEOC_SLV_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 2244 | #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 2245 | #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ |
| AnnaBridge | 163:e59c8e839560 | 2246 | #define ADC_CSR_JEOS_SLV_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 2247 | #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2248 | #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ |
| AnnaBridge | 163:e59c8e839560 | 2249 | #define ADC_CSR_AWD1_SLV_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 2250 | #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2251 | #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2252 | #define ADC_CSR_AWD2_SLV_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2253 | #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2254 | #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2255 | #define ADC_CSR_AWD3_SLV_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 2256 | #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2257 | #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ |
| AnnaBridge | 163:e59c8e839560 | 2258 | #define ADC_CSR_JQOVF_SLV_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 2259 | #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2260 | #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ |
| AnnaBridge | 163:e59c8e839560 | 2261 | |
| AnnaBridge | 163:e59c8e839560 | 2262 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 2263 | #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST |
| AnnaBridge | 163:e59c8e839560 | 2264 | #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST |
| AnnaBridge | 163:e59c8e839560 | 2265 | #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST |
| AnnaBridge | 163:e59c8e839560 | 2266 | #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST |
| AnnaBridge | 163:e59c8e839560 | 2267 | #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST |
| AnnaBridge | 163:e59c8e839560 | 2268 | #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST |
| AnnaBridge | 163:e59c8e839560 | 2269 | |
| AnnaBridge | 163:e59c8e839560 | 2270 | #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV |
| AnnaBridge | 163:e59c8e839560 | 2271 | #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV |
| AnnaBridge | 163:e59c8e839560 | 2272 | #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV |
| AnnaBridge | 163:e59c8e839560 | 2273 | #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV |
| AnnaBridge | 163:e59c8e839560 | 2274 | #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV |
| AnnaBridge | 163:e59c8e839560 | 2275 | #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV |
| AnnaBridge | 163:e59c8e839560 | 2276 | |
| AnnaBridge | 163:e59c8e839560 | 2277 | /******************** Bit definition for ADC_CCR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 2278 | #define ADC_CCR_DUAL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2279 | #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 2280 | #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ |
| AnnaBridge | 163:e59c8e839560 | 2281 | #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2282 | #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2283 | #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2284 | #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2285 | #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2286 | |
| AnnaBridge | 163:e59c8e839560 | 2287 | #define ADC_CCR_DELAY_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2288 | #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 2289 | #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ |
| AnnaBridge | 163:e59c8e839560 | 2290 | #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2291 | #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2292 | #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2293 | #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2294 | |
| AnnaBridge | 163:e59c8e839560 | 2295 | #define ADC_CCR_DMACFG_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 2296 | #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2297 | #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ |
| AnnaBridge | 163:e59c8e839560 | 2298 | |
| AnnaBridge | 163:e59c8e839560 | 2299 | #define ADC_CCR_MDMA_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2300 | #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2301 | #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ |
| AnnaBridge | 163:e59c8e839560 | 2302 | #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2303 | #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2304 | |
| AnnaBridge | 163:e59c8e839560 | 2305 | #define ADC_CCR_CKMODE_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2306 | #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2307 | #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ |
| AnnaBridge | 163:e59c8e839560 | 2308 | #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2309 | #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2310 | |
| AnnaBridge | 163:e59c8e839560 | 2311 | #define ADC_CCR_VREFEN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 2312 | #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2313 | #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ |
| AnnaBridge | 163:e59c8e839560 | 2314 | #define ADC_CCR_TSEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 2315 | #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2316 | #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ |
| AnnaBridge | 163:e59c8e839560 | 2317 | #define ADC_CCR_VBATEN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2318 | #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2319 | #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ |
| AnnaBridge | 163:e59c8e839560 | 2320 | |
| AnnaBridge | 163:e59c8e839560 | 2321 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 2322 | #define ADC_CCR_MULTI (ADC_CCR_DUAL) |
| AnnaBridge | 163:e59c8e839560 | 2323 | #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) |
| AnnaBridge | 163:e59c8e839560 | 2324 | #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) |
| AnnaBridge | 163:e59c8e839560 | 2325 | #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) |
| AnnaBridge | 163:e59c8e839560 | 2326 | #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) |
| AnnaBridge | 163:e59c8e839560 | 2327 | #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) |
| AnnaBridge | 163:e59c8e839560 | 2328 | |
| AnnaBridge | 163:e59c8e839560 | 2329 | /******************** Bit definition for ADC_CDR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 2330 | #define ADC_CDR_RDATA_MST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2331 | #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 2332 | #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 2333 | #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2334 | #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2335 | #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2336 | #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2337 | #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2338 | #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2339 | #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2340 | #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2341 | #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2342 | #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2343 | #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2344 | #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2345 | #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2346 | #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2347 | #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2348 | #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2349 | |
| AnnaBridge | 163:e59c8e839560 | 2350 | #define ADC_CDR_RDATA_SLV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2351 | #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2352 | #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ |
| AnnaBridge | 163:e59c8e839560 | 2353 | #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2354 | #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2355 | #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2356 | #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2357 | #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2358 | #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 2359 | #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 2360 | #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 2361 | #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2362 | #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2363 | #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2364 | #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2365 | #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2366 | #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2367 | #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2368 | #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2369 | |
| AnnaBridge | 163:e59c8e839560 | 2370 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 2371 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 2372 | /* Analog Comparators (COMP) */ |
| AnnaBridge | 163:e59c8e839560 | 2373 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 2374 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 2375 | |
| AnnaBridge | 163:e59c8e839560 | 2376 | #define COMP_V1_3_0_0 /*!< Comparator IP version */ |
| AnnaBridge | 163:e59c8e839560 | 2377 | |
| AnnaBridge | 163:e59c8e839560 | 2378 | /********************** Bit definition for COMP1_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2379 | #define COMP1_CSR_COMP1EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2380 | #define COMP1_CSR_COMP1EN_Msk (0x1U << COMP1_CSR_COMP1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2381 | #define COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk /*!< COMP1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2382 | #define COMP1_CSR_COMP1SW1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2383 | #define COMP1_CSR_COMP1SW1_Msk (0x1U << COMP1_CSR_COMP1SW1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2384 | #define COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */ |
| AnnaBridge | 163:e59c8e839560 | 2385 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 2386 | #define COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1 |
| AnnaBridge | 163:e59c8e839560 | 2387 | #define COMP1_CSR_COMP1MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2388 | #define COMP1_CSR_COMP1MODE_Msk (0x3U << COMP1_CSR_COMP1MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2389 | #define COMP1_CSR_COMP1MODE COMP1_CSR_COMP1MODE_Msk /*!< COMP1 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2390 | #define COMP1_CSR_COMP1MODE_0 (0x1U << COMP1_CSR_COMP1MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2391 | #define COMP1_CSR_COMP1MODE_1 (0x2U << COMP1_CSR_COMP1MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2392 | #define COMP1_CSR_COMP1INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2393 | #define COMP1_CSR_COMP1INSEL_Msk (0x7U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2394 | #define COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2395 | #define COMP1_CSR_COMP1INSEL_0 (0x1U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2396 | #define COMP1_CSR_COMP1INSEL_1 (0x2U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2397 | #define COMP1_CSR_COMP1INSEL_2 (0x4U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2398 | #define COMP1_CSR_COMP1OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2399 | #define COMP1_CSR_COMP1OUTSEL_Msk (0xFU << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2400 | #define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2401 | #define COMP1_CSR_COMP1OUTSEL_0 (0x1U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2402 | #define COMP1_CSR_COMP1OUTSEL_1 (0x2U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2403 | #define COMP1_CSR_COMP1OUTSEL_2 (0x4U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2404 | #define COMP1_CSR_COMP1OUTSEL_3 (0x8U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2405 | #define COMP1_CSR_COMP1POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2406 | #define COMP1_CSR_COMP1POL_Msk (0x1U << COMP1_CSR_COMP1POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2407 | #define COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk /*!< COMP1 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2408 | #define COMP1_CSR_COMP1HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2409 | #define COMP1_CSR_COMP1HYST_Msk (0x3U << COMP1_CSR_COMP1HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2410 | #define COMP1_CSR_COMP1HYST COMP1_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2411 | #define COMP1_CSR_COMP1HYST_0 (0x1U << COMP1_CSR_COMP1HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2412 | #define COMP1_CSR_COMP1HYST_1 (0x2U << COMP1_CSR_COMP1HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2413 | #define COMP1_CSR_COMP1BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2414 | #define COMP1_CSR_COMP1BLANKING_Msk (0x3U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2415 | #define COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk /*!< COMP1 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2416 | #define COMP1_CSR_COMP1BLANKING_0 (0x1U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2417 | #define COMP1_CSR_COMP1BLANKING_1 (0x2U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2418 | #define COMP1_CSR_COMP1BLANKING_2 (0x4U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2419 | #define COMP1_CSR_COMP1OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2420 | #define COMP1_CSR_COMP1OUT_Msk (0x1U << COMP1_CSR_COMP1OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2421 | #define COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk /*!< COMP1 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2422 | #define COMP1_CSR_COMP1LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2423 | #define COMP1_CSR_COMP1LOCK_Msk (0x1U << COMP1_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2424 | #define COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2425 | |
| AnnaBridge | 163:e59c8e839560 | 2426 | /********************** Bit definition for COMP2_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2427 | #define COMP2_CSR_COMP2EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2428 | #define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2429 | #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2430 | #define COMP2_CSR_COMP2MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2431 | #define COMP2_CSR_COMP2MODE_Msk (0x3U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2432 | #define COMP2_CSR_COMP2MODE COMP2_CSR_COMP2MODE_Msk /*!< COMP2 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2433 | #define COMP2_CSR_COMP2MODE_0 (0x1U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2434 | #define COMP2_CSR_COMP2MODE_1 (0x2U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2435 | #define COMP2_CSR_COMP2INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2436 | #define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2437 | #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2438 | #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2439 | #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 2440 | #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 2441 | #define COMP2_CSR_COMP2NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2442 | #define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2443 | #define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2444 | #define COMP2_CSR_COMP2WNDWEN_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2445 | #define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2446 | #define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2447 | #define COMP2_CSR_COMP2OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2448 | #define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2449 | #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2450 | #define COMP2_CSR_COMP2OUTSEL_0 (0x1U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2451 | #define COMP2_CSR_COMP2OUTSEL_1 (0x2U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2452 | #define COMP2_CSR_COMP2OUTSEL_2 (0x4U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2453 | #define COMP2_CSR_COMP2OUTSEL_3 (0x8U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2454 | #define COMP2_CSR_COMP2POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2455 | #define COMP2_CSR_COMP2POL_Msk (0x1U << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2456 | #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2457 | #define COMP2_CSR_COMP2HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2458 | #define COMP2_CSR_COMP2HYST_Msk (0x3U << COMP2_CSR_COMP2HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2459 | #define COMP2_CSR_COMP2HYST COMP2_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2460 | #define COMP2_CSR_COMP2HYST_0 (0x1U << COMP2_CSR_COMP2HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2461 | #define COMP2_CSR_COMP2HYST_1 (0x2U << COMP2_CSR_COMP2HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2462 | #define COMP2_CSR_COMP2BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2463 | #define COMP2_CSR_COMP2BLANKING_Msk (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2464 | #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2465 | #define COMP2_CSR_COMP2BLANKING_0 (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2466 | #define COMP2_CSR_COMP2BLANKING_1 (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2467 | #define COMP2_CSR_COMP2BLANKING_2 (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2468 | #define COMP2_CSR_COMP2OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2469 | #define COMP2_CSR_COMP2OUT_Msk (0x1U << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2470 | #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2471 | #define COMP2_CSR_COMP2LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2472 | #define COMP2_CSR_COMP2LOCK_Msk (0x1U << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2473 | #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2474 | |
| AnnaBridge | 163:e59c8e839560 | 2475 | /********************** Bit definition for COMP3_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2476 | #define COMP3_CSR_COMP3EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2477 | #define COMP3_CSR_COMP3EN_Msk (0x1U << COMP3_CSR_COMP3EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2478 | #define COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk /*!< COMP3 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2479 | #define COMP3_CSR_COMP3MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2480 | #define COMP3_CSR_COMP3MODE_Msk (0x3U << COMP3_CSR_COMP3MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2481 | #define COMP3_CSR_COMP3MODE COMP3_CSR_COMP3MODE_Msk /*!< COMP3 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2482 | #define COMP3_CSR_COMP3MODE_0 (0x1U << COMP3_CSR_COMP3MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2483 | #define COMP3_CSR_COMP3MODE_1 (0x2U << COMP3_CSR_COMP3MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2484 | #define COMP3_CSR_COMP3INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2485 | #define COMP3_CSR_COMP3INSEL_Msk (0x7U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2486 | #define COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk /*!< COMP3 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2487 | #define COMP3_CSR_COMP3INSEL_0 (0x1U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2488 | #define COMP3_CSR_COMP3INSEL_1 (0x2U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2489 | #define COMP3_CSR_COMP3INSEL_2 (0x4U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2490 | #define COMP3_CSR_COMP3NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2491 | #define COMP3_CSR_COMP3NONINSEL_Msk (0x1U << COMP3_CSR_COMP3NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2492 | #define COMP3_CSR_COMP3NONINSEL COMP3_CSR_COMP3NONINSEL_Msk /*!< COMP3 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2493 | #define COMP3_CSR_COMP3OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2494 | #define COMP3_CSR_COMP3OUTSEL_Msk (0xFU << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2495 | #define COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk /*!< COMP3 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2496 | #define COMP3_CSR_COMP3OUTSEL_0 (0x1U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2497 | #define COMP3_CSR_COMP3OUTSEL_1 (0x2U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2498 | #define COMP3_CSR_COMP3OUTSEL_2 (0x4U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2499 | #define COMP3_CSR_COMP3OUTSEL_3 (0x8U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2500 | #define COMP3_CSR_COMP3POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2501 | #define COMP3_CSR_COMP3POL_Msk (0x1U << COMP3_CSR_COMP3POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2502 | #define COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk /*!< COMP3 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2503 | #define COMP3_CSR_COMP3HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2504 | #define COMP3_CSR_COMP3HYST_Msk (0x3U << COMP3_CSR_COMP3HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2505 | #define COMP3_CSR_COMP3HYST COMP3_CSR_COMP3HYST_Msk /*!< COMP3 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2506 | #define COMP3_CSR_COMP3HYST_0 (0x1U << COMP3_CSR_COMP3HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2507 | #define COMP3_CSR_COMP3HYST_1 (0x2U << COMP3_CSR_COMP3HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2508 | #define COMP3_CSR_COMP3BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2509 | #define COMP3_CSR_COMP3BLANKING_Msk (0x3U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2510 | #define COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk /*!< COMP3 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2511 | #define COMP3_CSR_COMP3BLANKING_0 (0x1U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2512 | #define COMP3_CSR_COMP3BLANKING_1 (0x2U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2513 | #define COMP3_CSR_COMP3BLANKING_2 (0x4U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2514 | #define COMP3_CSR_COMP3OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2515 | #define COMP3_CSR_COMP3OUT_Msk (0x1U << COMP3_CSR_COMP3OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2516 | #define COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk /*!< COMP3 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2517 | #define COMP3_CSR_COMP3LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2518 | #define COMP3_CSR_COMP3LOCK_Msk (0x1U << COMP3_CSR_COMP3LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2519 | #define COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk /*!< COMP3 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2520 | |
| AnnaBridge | 163:e59c8e839560 | 2521 | /********************** Bit definition for COMP4_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2522 | #define COMP4_CSR_COMP4EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2523 | #define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2524 | #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2525 | #define COMP4_CSR_COMP4MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2526 | #define COMP4_CSR_COMP4MODE_Msk (0x3U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2527 | #define COMP4_CSR_COMP4MODE COMP4_CSR_COMP4MODE_Msk /*!< COMP4 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2528 | #define COMP4_CSR_COMP4MODE_0 (0x1U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2529 | #define COMP4_CSR_COMP4MODE_1 (0x2U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2530 | #define COMP4_CSR_COMP4INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2531 | #define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2532 | #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2533 | #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2534 | #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 2535 | #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 2536 | #define COMP4_CSR_COMP4NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2537 | #define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2538 | #define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2539 | #define COMP4_CSR_COMP4WNDWEN_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2540 | #define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2541 | #define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2542 | #define COMP4_CSR_COMP4OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2543 | #define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2544 | #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2545 | #define COMP4_CSR_COMP4OUTSEL_0 (0x1U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2546 | #define COMP4_CSR_COMP4OUTSEL_1 (0x2U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2547 | #define COMP4_CSR_COMP4OUTSEL_2 (0x4U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2548 | #define COMP4_CSR_COMP4OUTSEL_3 (0x8U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2549 | #define COMP4_CSR_COMP4POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2550 | #define COMP4_CSR_COMP4POL_Msk (0x1U << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2551 | #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2552 | #define COMP4_CSR_COMP4HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2553 | #define COMP4_CSR_COMP4HYST_Msk (0x3U << COMP4_CSR_COMP4HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2554 | #define COMP4_CSR_COMP4HYST COMP4_CSR_COMP4HYST_Msk /*!< COMP4 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2555 | #define COMP4_CSR_COMP4HYST_0 (0x1U << COMP4_CSR_COMP4HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2556 | #define COMP4_CSR_COMP4HYST_1 (0x2U << COMP4_CSR_COMP4HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2557 | #define COMP4_CSR_COMP4BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2558 | #define COMP4_CSR_COMP4BLANKING_Msk (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2559 | #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2560 | #define COMP4_CSR_COMP4BLANKING_0 (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2561 | #define COMP4_CSR_COMP4BLANKING_1 (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2562 | #define COMP4_CSR_COMP4BLANKING_2 (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2563 | #define COMP4_CSR_COMP4OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2564 | #define COMP4_CSR_COMP4OUT_Msk (0x1U << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2565 | #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2566 | #define COMP4_CSR_COMP4LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2567 | #define COMP4_CSR_COMP4LOCK_Msk (0x1U << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2568 | #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2569 | |
| AnnaBridge | 163:e59c8e839560 | 2570 | /********************** Bit definition for COMP5_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2571 | #define COMP5_CSR_COMP5EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2572 | #define COMP5_CSR_COMP5EN_Msk (0x1U << COMP5_CSR_COMP5EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2573 | #define COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk /*!< COMP5 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2574 | #define COMP5_CSR_COMP5MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2575 | #define COMP5_CSR_COMP5MODE_Msk (0x3U << COMP5_CSR_COMP5MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2576 | #define COMP5_CSR_COMP5MODE COMP5_CSR_COMP5MODE_Msk /*!< COMP5 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2577 | #define COMP5_CSR_COMP5MODE_0 (0x1U << COMP5_CSR_COMP5MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2578 | #define COMP5_CSR_COMP5MODE_1 (0x2U << COMP5_CSR_COMP5MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2579 | #define COMP5_CSR_COMP5INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2580 | #define COMP5_CSR_COMP5INSEL_Msk (0x7U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2581 | #define COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk /*!< COMP5 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2582 | #define COMP5_CSR_COMP5INSEL_0 (0x1U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2583 | #define COMP5_CSR_COMP5INSEL_1 (0x2U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2584 | #define COMP5_CSR_COMP5INSEL_2 (0x4U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2585 | #define COMP5_CSR_COMP5NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2586 | #define COMP5_CSR_COMP5NONINSEL_Msk (0x1U << COMP5_CSR_COMP5NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2587 | #define COMP5_CSR_COMP5NONINSEL COMP5_CSR_COMP5NONINSEL_Msk /*!< COMP5 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2588 | #define COMP5_CSR_COMP5OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2589 | #define COMP5_CSR_COMP5OUTSEL_Msk (0xFU << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2590 | #define COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk /*!< COMP5 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2591 | #define COMP5_CSR_COMP5OUTSEL_0 (0x1U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2592 | #define COMP5_CSR_COMP5OUTSEL_1 (0x2U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2593 | #define COMP5_CSR_COMP5OUTSEL_2 (0x4U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2594 | #define COMP5_CSR_COMP5OUTSEL_3 (0x8U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2595 | #define COMP5_CSR_COMP5POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2596 | #define COMP5_CSR_COMP5POL_Msk (0x1U << COMP5_CSR_COMP5POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2597 | #define COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk /*!< COMP5 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2598 | #define COMP5_CSR_COMP5HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2599 | #define COMP5_CSR_COMP5HYST_Msk (0x3U << COMP5_CSR_COMP5HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2600 | #define COMP5_CSR_COMP5HYST COMP5_CSR_COMP5HYST_Msk /*!< COMP5 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2601 | #define COMP5_CSR_COMP5HYST_0 (0x1U << COMP5_CSR_COMP5HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2602 | #define COMP5_CSR_COMP5HYST_1 (0x2U << COMP5_CSR_COMP5HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2603 | #define COMP5_CSR_COMP5BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2604 | #define COMP5_CSR_COMP5BLANKING_Msk (0x3U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2605 | #define COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk /*!< COMP5 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2606 | #define COMP5_CSR_COMP5BLANKING_0 (0x1U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2607 | #define COMP5_CSR_COMP5BLANKING_1 (0x2U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2608 | #define COMP5_CSR_COMP5BLANKING_2 (0x4U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2609 | #define COMP5_CSR_COMP5OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2610 | #define COMP5_CSR_COMP5OUT_Msk (0x1U << COMP5_CSR_COMP5OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2611 | #define COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk /*!< COMP5 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2612 | #define COMP5_CSR_COMP5LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2613 | #define COMP5_CSR_COMP5LOCK_Msk (0x1U << COMP5_CSR_COMP5LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2614 | #define COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk /*!< COMP5 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2615 | |
| AnnaBridge | 163:e59c8e839560 | 2616 | /********************** Bit definition for COMP6_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2617 | #define COMP6_CSR_COMP6EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2618 | #define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2619 | #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2620 | #define COMP6_CSR_COMP6MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2621 | #define COMP6_CSR_COMP6MODE_Msk (0x3U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2622 | #define COMP6_CSR_COMP6MODE COMP6_CSR_COMP6MODE_Msk /*!< COMP6 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2623 | #define COMP6_CSR_COMP6MODE_0 (0x1U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2624 | #define COMP6_CSR_COMP6MODE_1 (0x2U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2625 | #define COMP6_CSR_COMP6INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2626 | #define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2627 | #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2628 | #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2629 | #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 2630 | #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 2631 | #define COMP6_CSR_COMP6NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2632 | #define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2633 | #define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2634 | #define COMP6_CSR_COMP6WNDWEN_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2635 | #define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2636 | #define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2637 | #define COMP6_CSR_COMP6OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2638 | #define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2639 | #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2640 | #define COMP6_CSR_COMP6OUTSEL_0 (0x1U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2641 | #define COMP6_CSR_COMP6OUTSEL_1 (0x2U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2642 | #define COMP6_CSR_COMP6OUTSEL_2 (0x4U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2643 | #define COMP6_CSR_COMP6OUTSEL_3 (0x8U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2644 | #define COMP6_CSR_COMP6POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2645 | #define COMP6_CSR_COMP6POL_Msk (0x1U << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2646 | #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2647 | #define COMP6_CSR_COMP6HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2648 | #define COMP6_CSR_COMP6HYST_Msk (0x3U << COMP6_CSR_COMP6HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2649 | #define COMP6_CSR_COMP6HYST COMP6_CSR_COMP6HYST_Msk /*!< COMP6 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2650 | #define COMP6_CSR_COMP6HYST_0 (0x1U << COMP6_CSR_COMP6HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2651 | #define COMP6_CSR_COMP6HYST_1 (0x2U << COMP6_CSR_COMP6HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2652 | #define COMP6_CSR_COMP6BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2653 | #define COMP6_CSR_COMP6BLANKING_Msk (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2654 | #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2655 | #define COMP6_CSR_COMP6BLANKING_0 (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2656 | #define COMP6_CSR_COMP6BLANKING_1 (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2657 | #define COMP6_CSR_COMP6BLANKING_2 (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2658 | #define COMP6_CSR_COMP6OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2659 | #define COMP6_CSR_COMP6OUT_Msk (0x1U << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2660 | #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2661 | #define COMP6_CSR_COMP6LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2662 | #define COMP6_CSR_COMP6LOCK_Msk (0x1U << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2663 | #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2664 | |
| AnnaBridge | 163:e59c8e839560 | 2665 | /********************** Bit definition for COMP7_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2666 | #define COMP7_CSR_COMP7EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2667 | #define COMP7_CSR_COMP7EN_Msk (0x1U << COMP7_CSR_COMP7EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2668 | #define COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk /*!< COMP7 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2669 | #define COMP7_CSR_COMP7MODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2670 | #define COMP7_CSR_COMP7MODE_Msk (0x3U << COMP7_CSR_COMP7MODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2671 | #define COMP7_CSR_COMP7MODE COMP7_CSR_COMP7MODE_Msk /*!< COMP7 power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2672 | #define COMP7_CSR_COMP7MODE_0 (0x1U << COMP7_CSR_COMP7MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2673 | #define COMP7_CSR_COMP7MODE_1 (0x2U << COMP7_CSR_COMP7MODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2674 | #define COMP7_CSR_COMP7INSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2675 | #define COMP7_CSR_COMP7INSEL_Msk (0x7U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2676 | #define COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk /*!< COMP7 inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2677 | #define COMP7_CSR_COMP7INSEL_0 (0x1U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 2678 | #define COMP7_CSR_COMP7INSEL_1 (0x2U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2679 | #define COMP7_CSR_COMP7INSEL_2 (0x4U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2680 | #define COMP7_CSR_COMP7NONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2681 | #define COMP7_CSR_COMP7NONINSEL_Msk (0x1U << COMP7_CSR_COMP7NONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2682 | #define COMP7_CSR_COMP7NONINSEL COMP7_CSR_COMP7NONINSEL_Msk /*!< COMP7 non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2683 | #define COMP7_CSR_COMP7OUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2684 | #define COMP7_CSR_COMP7OUTSEL_Msk (0xFU << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2685 | #define COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk /*!< COMP7 output select */ |
| AnnaBridge | 163:e59c8e839560 | 2686 | #define COMP7_CSR_COMP7OUTSEL_0 (0x1U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2687 | #define COMP7_CSR_COMP7OUTSEL_1 (0x2U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2688 | #define COMP7_CSR_COMP7OUTSEL_2 (0x4U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2689 | #define COMP7_CSR_COMP7OUTSEL_3 (0x8U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2690 | #define COMP7_CSR_COMP7POL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2691 | #define COMP7_CSR_COMP7POL_Msk (0x1U << COMP7_CSR_COMP7POL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2692 | #define COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk /*!< COMP7 output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2693 | #define COMP7_CSR_COMP7HYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2694 | #define COMP7_CSR_COMP7HYST_Msk (0x3U << COMP7_CSR_COMP7HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2695 | #define COMP7_CSR_COMP7HYST COMP7_CSR_COMP7HYST_Msk /*!< COMP7 hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2696 | #define COMP7_CSR_COMP7HYST_0 (0x1U << COMP7_CSR_COMP7HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2697 | #define COMP7_CSR_COMP7HYST_1 (0x2U << COMP7_CSR_COMP7HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2698 | #define COMP7_CSR_COMP7BLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2699 | #define COMP7_CSR_COMP7BLANKING_Msk (0x3U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2700 | #define COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk /*!< COMP7 blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2701 | #define COMP7_CSR_COMP7BLANKING_0 (0x1U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2702 | #define COMP7_CSR_COMP7BLANKING_1 (0x2U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2703 | #define COMP7_CSR_COMP7BLANKING_2 (0x4U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2704 | #define COMP7_CSR_COMP7OUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2705 | #define COMP7_CSR_COMP7OUT_Msk (0x1U << COMP7_CSR_COMP7OUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2706 | #define COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk /*!< COMP7 output level */ |
| AnnaBridge | 163:e59c8e839560 | 2707 | #define COMP7_CSR_COMP7LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2708 | #define COMP7_CSR_COMP7LOCK_Msk (0x1U << COMP7_CSR_COMP7LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2709 | #define COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk /*!< COMP7 lock */ |
| AnnaBridge | 163:e59c8e839560 | 2710 | |
| AnnaBridge | 163:e59c8e839560 | 2711 | /********************** Bit definition for COMP_CSR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 2712 | #define COMP_CSR_COMPxEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2713 | #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2714 | #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ |
| AnnaBridge | 163:e59c8e839560 | 2715 | #define COMP_CSR_COMPxSW1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2716 | #define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2717 | #define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */ |
| AnnaBridge | 163:e59c8e839560 | 2718 | #define COMP_CSR_COMPxMODE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2719 | #define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2720 | #define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */ |
| AnnaBridge | 163:e59c8e839560 | 2721 | #define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2722 | #define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2723 | #define COMP_CSR_COMPxINSEL_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 2724 | #define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 2725 | #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2726 | #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2727 | #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 2728 | #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 2729 | #define COMP_CSR_COMPxNONINSEL_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2730 | #define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2731 | #define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */ |
| AnnaBridge | 163:e59c8e839560 | 2732 | #define COMP_CSR_COMPxWNDWEN_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2733 | #define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2734 | #define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2735 | #define COMP_CSR_COMPxOUTSEL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 2736 | #define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 163:e59c8e839560 | 2737 | #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ |
| AnnaBridge | 163:e59c8e839560 | 2738 | #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2739 | #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2740 | #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2741 | #define COMP_CSR_COMPxOUTSEL_3 (0x8U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2742 | #define COMP_CSR_COMPxPOL_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 2743 | #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2744 | #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ |
| AnnaBridge | 163:e59c8e839560 | 2745 | #define COMP_CSR_COMPxHYST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 2746 | #define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 2747 | #define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */ |
| AnnaBridge | 163:e59c8e839560 | 2748 | #define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2749 | #define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2750 | #define COMP_CSR_COMPxBLANKING_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2751 | #define COMP_CSR_COMPxBLANKING_Msk (0x3U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 2752 | #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */ |
| AnnaBridge | 163:e59c8e839560 | 2753 | #define COMP_CSR_COMPxBLANKING_0 (0x1U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2754 | #define COMP_CSR_COMPxBLANKING_1 (0x2U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 2755 | #define COMP_CSR_COMPxBLANKING_2 (0x4U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 2756 | #define COMP_CSR_COMPxOUT_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2757 | #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2758 | #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ |
| AnnaBridge | 163:e59c8e839560 | 2759 | #define COMP_CSR_COMPxLOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2760 | #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2761 | #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ |
| AnnaBridge | 163:e59c8e839560 | 2762 | |
| AnnaBridge | 163:e59c8e839560 | 2763 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 2764 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 2765 | /* Operational Amplifier (OPAMP) */ |
| AnnaBridge | 163:e59c8e839560 | 2766 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 2767 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 2768 | /********************* Bit definition for OPAMP1_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2769 | #define OPAMP1_CSR_OPAMP1EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2770 | #define OPAMP1_CSR_OPAMP1EN_Msk (0x1U << OPAMP1_CSR_OPAMP1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2771 | #define OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk /*!< OPAMP1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2772 | #define OPAMP1_CSR_FORCEVP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2773 | #define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2774 | #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ |
| AnnaBridge | 163:e59c8e839560 | 2775 | #define OPAMP1_CSR_VPSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2776 | #define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2777 | #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2778 | #define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2779 | #define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2780 | #define OPAMP1_CSR_VMSEL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 2781 | #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 2782 | #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2783 | #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2784 | #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2785 | #define OPAMP1_CSR_TCMEN_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2786 | #define OPAMP1_CSR_TCMEN_Msk (0x1U << OPAMP1_CSR_TCMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2787 | #define OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2788 | #define OPAMP1_CSR_VMSSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2789 | #define OPAMP1_CSR_VMSSEL_Msk (0x1U << OPAMP1_CSR_VMSSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2790 | #define OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2791 | #define OPAMP1_CSR_VPSSEL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2792 | #define OPAMP1_CSR_VPSSEL_Msk (0x3U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 2793 | #define OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2794 | #define OPAMP1_CSR_VPSSEL_0 (0x1U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2795 | #define OPAMP1_CSR_VPSSEL_1 (0x2U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2796 | #define OPAMP1_CSR_CALON_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 2797 | #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2798 | #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2799 | #define OPAMP1_CSR_CALSEL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 2800 | #define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 2801 | #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 163:e59c8e839560 | 2802 | #define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2803 | #define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2804 | #define OPAMP1_CSR_PGGAIN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2805 | #define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2806 | #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ |
| AnnaBridge | 163:e59c8e839560 | 2807 | #define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2808 | #define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2809 | #define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2810 | #define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2811 | #define OPAMP1_CSR_USERTRIM_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2812 | #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2813 | #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 163:e59c8e839560 | 2814 | #define OPAMP1_CSR_TRIMOFFSETP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 2815 | #define OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 163:e59c8e839560 | 2816 | #define OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2817 | #define OPAMP1_CSR_TRIMOFFSETN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2818 | #define OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2819 | #define OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2820 | #define OPAMP1_CSR_TSTREF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 2821 | #define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2822 | #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
| AnnaBridge | 163:e59c8e839560 | 2823 | #define OPAMP1_CSR_OUTCAL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2824 | #define OPAMP1_CSR_OUTCAL_Msk (0x1U << OPAMP1_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2825 | #define OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| AnnaBridge | 163:e59c8e839560 | 2826 | #define OPAMP1_CSR_LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2827 | #define OPAMP1_CSR_LOCK_Msk (0x1U << OPAMP1_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2828 | #define OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk /*!< OPAMP lock */ |
| AnnaBridge | 163:e59c8e839560 | 2829 | |
| AnnaBridge | 163:e59c8e839560 | 2830 | /********************* Bit definition for OPAMP2_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2831 | #define OPAMP2_CSR_OPAMP2EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2832 | #define OPAMP2_CSR_OPAMP2EN_Msk (0x1U << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2833 | #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2834 | #define OPAMP2_CSR_FORCEVP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2835 | #define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2836 | #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ |
| AnnaBridge | 163:e59c8e839560 | 2837 | #define OPAMP2_CSR_VPSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2838 | #define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2839 | #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2840 | #define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2841 | #define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2842 | #define OPAMP2_CSR_VMSEL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 2843 | #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 2844 | #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2845 | #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2846 | #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2847 | #define OPAMP2_CSR_TCMEN_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2848 | #define OPAMP2_CSR_TCMEN_Msk (0x1U << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2849 | #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2850 | #define OPAMP2_CSR_VMSSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2851 | #define OPAMP2_CSR_VMSSEL_Msk (0x1U << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2852 | #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2853 | #define OPAMP2_CSR_VPSSEL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2854 | #define OPAMP2_CSR_VPSSEL_Msk (0x3U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 2855 | #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2856 | #define OPAMP2_CSR_VPSSEL_0 (0x1U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2857 | #define OPAMP2_CSR_VPSSEL_1 (0x2U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2858 | #define OPAMP2_CSR_CALON_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 2859 | #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2860 | #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2861 | #define OPAMP2_CSR_CALSEL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 2862 | #define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 2863 | #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 163:e59c8e839560 | 2864 | #define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2865 | #define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2866 | #define OPAMP2_CSR_PGGAIN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2867 | #define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2868 | #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ |
| AnnaBridge | 163:e59c8e839560 | 2869 | #define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2870 | #define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2871 | #define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2872 | #define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2873 | #define OPAMP2_CSR_USERTRIM_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2874 | #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2875 | #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 163:e59c8e839560 | 2876 | #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 2877 | #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 163:e59c8e839560 | 2878 | #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2879 | #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2880 | #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2881 | #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2882 | #define OPAMP2_CSR_TSTREF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 2883 | #define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2884 | #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
| AnnaBridge | 163:e59c8e839560 | 2885 | #define OPAMP2_CSR_OUTCAL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2886 | #define OPAMP2_CSR_OUTCAL_Msk (0x1U << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2887 | #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| AnnaBridge | 163:e59c8e839560 | 2888 | #define OPAMP2_CSR_LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2889 | #define OPAMP2_CSR_LOCK_Msk (0x1U << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2890 | #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */ |
| AnnaBridge | 163:e59c8e839560 | 2891 | |
| AnnaBridge | 163:e59c8e839560 | 2892 | /********************* Bit definition for OPAMP3_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2893 | #define OPAMP3_CSR_OPAMP3EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2894 | #define OPAMP3_CSR_OPAMP3EN_Msk (0x1U << OPAMP3_CSR_OPAMP3EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2895 | #define OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk /*!< OPAMP3 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2896 | #define OPAMP3_CSR_FORCEVP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2897 | #define OPAMP3_CSR_FORCEVP_Msk (0x1U << OPAMP3_CSR_FORCEVP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2898 | #define OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ |
| AnnaBridge | 163:e59c8e839560 | 2899 | #define OPAMP3_CSR_VPSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2900 | #define OPAMP3_CSR_VPSEL_Msk (0x3U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2901 | #define OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk /*!< Non inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2902 | #define OPAMP3_CSR_VPSEL_0 (0x1U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2903 | #define OPAMP3_CSR_VPSEL_1 (0x2U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2904 | #define OPAMP3_CSR_VMSEL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 2905 | #define OPAMP3_CSR_VMSEL_Msk (0x3U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 2906 | #define OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2907 | #define OPAMP3_CSR_VMSEL_0 (0x1U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2908 | #define OPAMP3_CSR_VMSEL_1 (0x2U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2909 | #define OPAMP3_CSR_TCMEN_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2910 | #define OPAMP3_CSR_TCMEN_Msk (0x1U << OPAMP3_CSR_TCMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2911 | #define OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2912 | #define OPAMP3_CSR_VMSSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2913 | #define OPAMP3_CSR_VMSSEL_Msk (0x1U << OPAMP3_CSR_VMSSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2914 | #define OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2915 | #define OPAMP3_CSR_VPSSEL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2916 | #define OPAMP3_CSR_VPSSEL_Msk (0x3U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 2917 | #define OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2918 | #define OPAMP3_CSR_VPSSEL_0 (0x1U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2919 | #define OPAMP3_CSR_VPSSEL_1 (0x2U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2920 | #define OPAMP3_CSR_CALON_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 2921 | #define OPAMP3_CSR_CALON_Msk (0x1U << OPAMP3_CSR_CALON_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2922 | #define OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2923 | #define OPAMP3_CSR_CALSEL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 2924 | #define OPAMP3_CSR_CALSEL_Msk (0x3U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 2925 | #define OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 163:e59c8e839560 | 2926 | #define OPAMP3_CSR_CALSEL_0 (0x1U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2927 | #define OPAMP3_CSR_CALSEL_1 (0x2U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2928 | #define OPAMP3_CSR_PGGAIN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2929 | #define OPAMP3_CSR_PGGAIN_Msk (0xFU << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2930 | #define OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ |
| AnnaBridge | 163:e59c8e839560 | 2931 | #define OPAMP3_CSR_PGGAIN_0 (0x1U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2932 | #define OPAMP3_CSR_PGGAIN_1 (0x2U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2933 | #define OPAMP3_CSR_PGGAIN_2 (0x4U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2934 | #define OPAMP3_CSR_PGGAIN_3 (0x8U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2935 | #define OPAMP3_CSR_USERTRIM_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2936 | #define OPAMP3_CSR_USERTRIM_Msk (0x1U << OPAMP3_CSR_USERTRIM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2937 | #define OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 163:e59c8e839560 | 2938 | #define OPAMP3_CSR_TRIMOFFSETP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 2939 | #define OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 163:e59c8e839560 | 2940 | #define OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2941 | #define OPAMP3_CSR_TRIMOFFSETN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 2942 | #define OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2943 | #define OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 2944 | #define OPAMP3_CSR_TSTREF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 2945 | #define OPAMP3_CSR_TSTREF_Msk (0x1U << OPAMP3_CSR_TSTREF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2946 | #define OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
| AnnaBridge | 163:e59c8e839560 | 2947 | #define OPAMP3_CSR_OUTCAL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 2948 | #define OPAMP3_CSR_OUTCAL_Msk (0x1U << OPAMP3_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2949 | #define OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| AnnaBridge | 163:e59c8e839560 | 2950 | #define OPAMP3_CSR_LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 2951 | #define OPAMP3_CSR_LOCK_Msk (0x1U << OPAMP3_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 2952 | #define OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk /*!< OPAMP lock */ |
| AnnaBridge | 163:e59c8e839560 | 2953 | |
| AnnaBridge | 163:e59c8e839560 | 2954 | /********************* Bit definition for OPAMP4_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 2955 | #define OPAMP4_CSR_OPAMP4EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 2956 | #define OPAMP4_CSR_OPAMP4EN_Msk (0x1U << OPAMP4_CSR_OPAMP4EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 2957 | #define OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk /*!< OPAMP4 enable */ |
| AnnaBridge | 163:e59c8e839560 | 2958 | #define OPAMP4_CSR_FORCEVP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 2959 | #define OPAMP4_CSR_FORCEVP_Msk (0x1U << OPAMP4_CSR_FORCEVP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 2960 | #define OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ |
| AnnaBridge | 163:e59c8e839560 | 2961 | #define OPAMP4_CSR_VPSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 2962 | #define OPAMP4_CSR_VPSEL_Msk (0x3U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 2963 | #define OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk /*!< Non inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2964 | #define OPAMP4_CSR_VPSEL_0 (0x1U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 2965 | #define OPAMP4_CSR_VPSEL_1 (0x2U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 2966 | #define OPAMP4_CSR_VMSEL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 2967 | #define OPAMP4_CSR_VMSEL_Msk (0x3U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 2968 | #define OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 2969 | #define OPAMP4_CSR_VMSEL_0 (0x1U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 2970 | #define OPAMP4_CSR_VMSEL_1 (0x2U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 2971 | #define OPAMP4_CSR_TCMEN_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 2972 | #define OPAMP4_CSR_TCMEN_Msk (0x1U << OPAMP4_CSR_TCMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 2973 | #define OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2974 | #define OPAMP4_CSR_VMSSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 2975 | #define OPAMP4_CSR_VMSSEL_Msk (0x1U << OPAMP4_CSR_VMSSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 2976 | #define OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2977 | #define OPAMP4_CSR_VPSSEL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 2978 | #define OPAMP4_CSR_VPSSEL_Msk (0x3U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 2979 | #define OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 2980 | #define OPAMP4_CSR_VPSSEL_0 (0x1U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 2981 | #define OPAMP4_CSR_VPSSEL_1 (0x2U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 2982 | #define OPAMP4_CSR_CALON_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 2983 | #define OPAMP4_CSR_CALON_Msk (0x1U << OPAMP4_CSR_CALON_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 2984 | #define OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 2985 | #define OPAMP4_CSR_CALSEL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 2986 | #define OPAMP4_CSR_CALSEL_Msk (0x3U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 2987 | #define OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 163:e59c8e839560 | 2988 | #define OPAMP4_CSR_CALSEL_0 (0x1U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 2989 | #define OPAMP4_CSR_CALSEL_1 (0x2U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 2990 | #define OPAMP4_CSR_PGGAIN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 2991 | #define OPAMP4_CSR_PGGAIN_Msk (0xFU << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ |
| AnnaBridge | 163:e59c8e839560 | 2992 | #define OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ |
| AnnaBridge | 163:e59c8e839560 | 2993 | #define OPAMP4_CSR_PGGAIN_0 (0x1U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 2994 | #define OPAMP4_CSR_PGGAIN_1 (0x2U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 2995 | #define OPAMP4_CSR_PGGAIN_2 (0x4U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 2996 | #define OPAMP4_CSR_PGGAIN_3 (0x8U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 2997 | #define OPAMP4_CSR_USERTRIM_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 2998 | #define OPAMP4_CSR_USERTRIM_Msk (0x1U << OPAMP4_CSR_USERTRIM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 2999 | #define OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 163:e59c8e839560 | 3000 | #define OPAMP4_CSR_TRIMOFFSETP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 3001 | #define OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 163:e59c8e839560 | 3002 | #define OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 3003 | #define OPAMP4_CSR_TRIMOFFSETN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3004 | #define OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3005 | #define OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 3006 | #define OPAMP4_CSR_TSTREF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3007 | #define OPAMP4_CSR_TSTREF_Msk (0x1U << OPAMP4_CSR_TSTREF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3008 | #define OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
| AnnaBridge | 163:e59c8e839560 | 3009 | #define OPAMP4_CSR_OUTCAL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 3010 | #define OPAMP4_CSR_OUTCAL_Msk (0x1U << OPAMP4_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3011 | #define OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| AnnaBridge | 163:e59c8e839560 | 3012 | #define OPAMP4_CSR_LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 3013 | #define OPAMP4_CSR_LOCK_Msk (0x1U << OPAMP4_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3014 | #define OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk /*!< OPAMP lock */ |
| AnnaBridge | 163:e59c8e839560 | 3015 | |
| AnnaBridge | 163:e59c8e839560 | 3016 | /********************* Bit definition for OPAMPx_CSR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 3017 | #define OPAMP_CSR_OPAMPxEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3018 | #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3019 | #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ |
| AnnaBridge | 163:e59c8e839560 | 3020 | #define OPAMP_CSR_FORCEVP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3021 | #define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3022 | #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ |
| AnnaBridge | 163:e59c8e839560 | 3023 | #define OPAMP_CSR_VPSEL_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3024 | #define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 3025 | #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 3026 | #define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3027 | #define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3028 | #define OPAMP_CSR_VMSEL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3029 | #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 3030 | #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 163:e59c8e839560 | 3031 | #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3032 | #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3033 | #define OPAMP_CSR_TCMEN_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3034 | #define OPAMP_CSR_TCMEN_Msk (0x1U << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3035 | #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 3036 | #define OPAMP_CSR_VMSSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3037 | #define OPAMP_CSR_VMSSEL_Msk (0x1U << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3038 | #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 3039 | #define OPAMP_CSR_VPSSEL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3040 | #define OPAMP_CSR_VPSSEL_Msk (0x3U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 3041 | #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ |
| AnnaBridge | 163:e59c8e839560 | 3042 | #define OPAMP_CSR_VPSSEL_0 (0x1U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3043 | #define OPAMP_CSR_VPSSEL_1 (0x2U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3044 | #define OPAMP_CSR_CALON_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3045 | #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3046 | #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 3047 | #define OPAMP_CSR_CALSEL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3048 | #define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 3049 | #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 163:e59c8e839560 | 3050 | #define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3051 | #define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3052 | #define OPAMP_CSR_PGGAIN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 3053 | #define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ |
| AnnaBridge | 163:e59c8e839560 | 3054 | #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ |
| AnnaBridge | 163:e59c8e839560 | 3055 | #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 3056 | #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3057 | #define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3058 | #define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3059 | #define OPAMP_CSR_USERTRIM_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 3060 | #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 3061 | #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 163:e59c8e839560 | 3062 | #define OPAMP_CSR_TRIMOFFSETP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 3063 | #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 163:e59c8e839560 | 3064 | #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 3065 | #define OPAMP_CSR_TRIMOFFSETN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3066 | #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3067 | #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ |
| AnnaBridge | 163:e59c8e839560 | 3068 | #define OPAMP_CSR_TSTREF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3069 | #define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3070 | #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ |
| AnnaBridge | 163:e59c8e839560 | 3071 | #define OPAMP_CSR_OUTCAL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 3072 | #define OPAMP_CSR_OUTCAL_Msk (0x1U << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3073 | #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ |
| AnnaBridge | 163:e59c8e839560 | 3074 | #define OPAMP_CSR_LOCK_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 3075 | #define OPAMP_CSR_LOCK_Msk (0x1U << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3076 | #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */ |
| AnnaBridge | 163:e59c8e839560 | 3077 | |
| AnnaBridge | 163:e59c8e839560 | 3078 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 3079 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 3080 | /* Controller Area Network (CAN ) */ |
| AnnaBridge | 163:e59c8e839560 | 3081 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 3082 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 3083 | /******************* Bit definition for CAN_MCR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3084 | #define CAN_MCR_INRQ_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3085 | #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3086 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ |
| AnnaBridge | 163:e59c8e839560 | 3087 | #define CAN_MCR_SLEEP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3088 | #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3089 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ |
| AnnaBridge | 163:e59c8e839560 | 3090 | #define CAN_MCR_TXFP_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3091 | #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3092 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ |
| AnnaBridge | 163:e59c8e839560 | 3093 | #define CAN_MCR_RFLM_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3094 | #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3095 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3096 | #define CAN_MCR_NART_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3097 | #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3098 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ |
| AnnaBridge | 163:e59c8e839560 | 3099 | #define CAN_MCR_AWUM_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3100 | #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3101 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3102 | #define CAN_MCR_ABOM_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3103 | #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3104 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ |
| AnnaBridge | 163:e59c8e839560 | 3105 | #define CAN_MCR_TTCM_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3106 | #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3107 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3108 | #define CAN_MCR_RESET_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 3109 | #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3110 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ |
| AnnaBridge | 163:e59c8e839560 | 3111 | |
| AnnaBridge | 163:e59c8e839560 | 3112 | /******************* Bit definition for CAN_MSR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3113 | #define CAN_MSR_INAK_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3114 | #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3115 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ |
| AnnaBridge | 163:e59c8e839560 | 3116 | #define CAN_MSR_SLAK_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3117 | #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3118 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ |
| AnnaBridge | 163:e59c8e839560 | 3119 | #define CAN_MSR_ERRI_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3120 | #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3121 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 3122 | #define CAN_MSR_WKUI_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3123 | #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3124 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 3125 | #define CAN_MSR_SLAKI_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3126 | #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3127 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 3128 | #define CAN_MSR_TXM_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3129 | #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3130 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3131 | #define CAN_MSR_RXM_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3132 | #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3133 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3134 | #define CAN_MSR_SAMP_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3135 | #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3136 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ |
| AnnaBridge | 163:e59c8e839560 | 3137 | #define CAN_MSR_RX_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3138 | #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3139 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ |
| AnnaBridge | 163:e59c8e839560 | 3140 | |
| AnnaBridge | 163:e59c8e839560 | 3141 | /******************* Bit definition for CAN_TSR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3142 | #define CAN_TSR_RQCP0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3143 | #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3144 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ |
| AnnaBridge | 163:e59c8e839560 | 3145 | #define CAN_TSR_TXOK0_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3146 | #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3147 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ |
| AnnaBridge | 163:e59c8e839560 | 3148 | #define CAN_TSR_ALST0_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3149 | #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3150 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ |
| AnnaBridge | 163:e59c8e839560 | 3151 | #define CAN_TSR_TERR0_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3152 | #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3153 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ |
| AnnaBridge | 163:e59c8e839560 | 3154 | #define CAN_TSR_ABRQ0_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3155 | #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3156 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ |
| AnnaBridge | 163:e59c8e839560 | 3157 | #define CAN_TSR_RQCP1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3158 | #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3159 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ |
| AnnaBridge | 163:e59c8e839560 | 3160 | #define CAN_TSR_TXOK1_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3161 | #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3162 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ |
| AnnaBridge | 163:e59c8e839560 | 3163 | #define CAN_TSR_ALST1_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3164 | #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3165 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ |
| AnnaBridge | 163:e59c8e839560 | 3166 | #define CAN_TSR_TERR1_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3167 | #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3168 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ |
| AnnaBridge | 163:e59c8e839560 | 3169 | #define CAN_TSR_ABRQ1_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 3170 | #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3171 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3172 | #define CAN_TSR_RQCP2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3173 | #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3174 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ |
| AnnaBridge | 163:e59c8e839560 | 3175 | #define CAN_TSR_TXOK2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 3176 | #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3177 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3178 | #define CAN_TSR_ALST2_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 3179 | #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 3180 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3181 | #define CAN_TSR_TERR2_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 3182 | #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 3183 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3184 | #define CAN_TSR_ABRQ2_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 3185 | #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 3186 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3187 | #define CAN_TSR_CODE_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3188 | #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3189 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ |
| AnnaBridge | 163:e59c8e839560 | 3190 | |
| AnnaBridge | 163:e59c8e839560 | 3191 | #define CAN_TSR_TME_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 3192 | #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3193 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 3194 | #define CAN_TSR_TME0_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 3195 | #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3196 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ |
| AnnaBridge | 163:e59c8e839560 | 3197 | #define CAN_TSR_TME1_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 3198 | #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3199 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ |
| AnnaBridge | 163:e59c8e839560 | 3200 | #define CAN_TSR_TME2_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 3201 | #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3202 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ |
| AnnaBridge | 163:e59c8e839560 | 3203 | |
| AnnaBridge | 163:e59c8e839560 | 3204 | #define CAN_TSR_LOW_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3205 | #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3206 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 3207 | #define CAN_TSR_LOW0_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3208 | #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3209 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3210 | #define CAN_TSR_LOW1_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 3211 | #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3212 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3213 | #define CAN_TSR_LOW2_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 3214 | #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3215 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3216 | |
| AnnaBridge | 163:e59c8e839560 | 3217 | /******************* Bit definition for CAN_RF0R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3218 | #define CAN_RF0R_FMP0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3219 | #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 3220 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ |
| AnnaBridge | 163:e59c8e839560 | 3221 | #define CAN_RF0R_FULL0_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3222 | #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3223 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ |
| AnnaBridge | 163:e59c8e839560 | 3224 | #define CAN_RF0R_FOVR0_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3225 | #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3226 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ |
| AnnaBridge | 163:e59c8e839560 | 3227 | #define CAN_RF0R_RFOM0_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3228 | #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3229 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ |
| AnnaBridge | 163:e59c8e839560 | 3230 | |
| AnnaBridge | 163:e59c8e839560 | 3231 | /******************* Bit definition for CAN_RF1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3232 | #define CAN_RF1R_FMP1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3233 | #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 3234 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ |
| AnnaBridge | 163:e59c8e839560 | 3235 | #define CAN_RF1R_FULL1_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3236 | #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3237 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ |
| AnnaBridge | 163:e59c8e839560 | 3238 | #define CAN_RF1R_FOVR1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3239 | #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3240 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ |
| AnnaBridge | 163:e59c8e839560 | 3241 | #define CAN_RF1R_RFOM1_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3242 | #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3243 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ |
| AnnaBridge | 163:e59c8e839560 | 3244 | |
| AnnaBridge | 163:e59c8e839560 | 3245 | /******************** Bit definition for CAN_IER register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3246 | #define CAN_IER_TMEIE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3247 | #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3248 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3249 | #define CAN_IER_FMPIE0_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3250 | #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3251 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3252 | #define CAN_IER_FFIE0_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3253 | #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3254 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3255 | #define CAN_IER_FOVIE0_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3256 | #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3257 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3258 | #define CAN_IER_FMPIE1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3259 | #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3260 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3261 | #define CAN_IER_FFIE1_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3262 | #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3263 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3264 | #define CAN_IER_FOVIE1_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3265 | #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3266 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3267 | #define CAN_IER_EWGIE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3268 | #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3269 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3270 | #define CAN_IER_EPVIE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3271 | #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3272 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3273 | #define CAN_IER_BOFIE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3274 | #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3275 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3276 | #define CAN_IER_LECIE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3277 | #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3278 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3279 | #define CAN_IER_ERRIE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 3280 | #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3281 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3282 | #define CAN_IER_WKUIE_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3283 | #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3284 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3285 | #define CAN_IER_SLKIE_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 3286 | #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3287 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 3288 | |
| AnnaBridge | 163:e59c8e839560 | 3289 | /******************** Bit definition for CAN_ESR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3290 | #define CAN_ESR_EWGF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3291 | #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3292 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ |
| AnnaBridge | 163:e59c8e839560 | 3293 | #define CAN_ESR_EPVF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3294 | #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3295 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ |
| AnnaBridge | 163:e59c8e839560 | 3296 | #define CAN_ESR_BOFF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3297 | #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3298 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ |
| AnnaBridge | 163:e59c8e839560 | 3299 | |
| AnnaBridge | 163:e59c8e839560 | 3300 | #define CAN_ESR_LEC_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3301 | #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 3302 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ |
| AnnaBridge | 163:e59c8e839560 | 3303 | #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3304 | #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3305 | #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3306 | |
| AnnaBridge | 163:e59c8e839560 | 3307 | #define CAN_ESR_TEC_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3308 | #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3309 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| AnnaBridge | 163:e59c8e839560 | 3310 | #define CAN_ESR_REC_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3311 | #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3312 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ |
| AnnaBridge | 163:e59c8e839560 | 3313 | |
| AnnaBridge | 163:e59c8e839560 | 3314 | /******************* Bit definition for CAN_BTR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3315 | #define CAN_BTR_BRP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3316 | #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 163:e59c8e839560 | 3317 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 3318 | #define CAN_BTR_TS1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3319 | #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3320 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3321 | #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3322 | #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3323 | #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 3324 | #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 3325 | #define CAN_BTR_TS2_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 3326 | #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 163:e59c8e839560 | 3327 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3328 | #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 3329 | #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 3330 | #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 3331 | #define CAN_BTR_SJW_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3332 | #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3333 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| AnnaBridge | 163:e59c8e839560 | 3334 | #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3335 | #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3336 | #define CAN_BTR_LBKM_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 3337 | #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3338 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| AnnaBridge | 163:e59c8e839560 | 3339 | #define CAN_BTR_SILM_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 3340 | #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3341 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3342 | |
| AnnaBridge | 163:e59c8e839560 | 3343 | /*!<Mailbox registers */ |
| AnnaBridge | 163:e59c8e839560 | 3344 | /****************** Bit definition for CAN_TI0R register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3345 | #define CAN_TI0R_TXRQ_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3346 | #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3347 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 163:e59c8e839560 | 3348 | #define CAN_TI0R_RTR_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3349 | #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3350 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 163:e59c8e839560 | 3351 | #define CAN_TI0R_IDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3352 | #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3353 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 163:e59c8e839560 | 3354 | #define CAN_TI0R_EXID_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3355 | #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 3356 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3357 | #define CAN_TI0R_STID_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3358 | #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 163:e59c8e839560 | 3359 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3360 | |
| AnnaBridge | 163:e59c8e839560 | 3361 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3362 | #define CAN_TDT0R_DLC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3363 | #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 3364 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 163:e59c8e839560 | 3365 | #define CAN_TDT0R_TGT_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3366 | #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3367 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 163:e59c8e839560 | 3368 | #define CAN_TDT0R_TIME_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3369 | #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3370 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 163:e59c8e839560 | 3371 | |
| AnnaBridge | 163:e59c8e839560 | 3372 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3373 | #define CAN_TDL0R_DATA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3374 | #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3375 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3376 | #define CAN_TDL0R_DATA1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3377 | #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3378 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3379 | #define CAN_TDL0R_DATA2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3380 | #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3381 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3382 | #define CAN_TDL0R_DATA3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3383 | #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3384 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3385 | |
| AnnaBridge | 163:e59c8e839560 | 3386 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3387 | #define CAN_TDH0R_DATA4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3388 | #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3389 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3390 | #define CAN_TDH0R_DATA5_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3391 | #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3392 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3393 | #define CAN_TDH0R_DATA6_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3394 | #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3395 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3396 | #define CAN_TDH0R_DATA7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3397 | #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3398 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3399 | |
| AnnaBridge | 163:e59c8e839560 | 3400 | /******************* Bit definition for CAN_TI1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3401 | #define CAN_TI1R_TXRQ_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3402 | #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3403 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 163:e59c8e839560 | 3404 | #define CAN_TI1R_RTR_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3405 | #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3406 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 163:e59c8e839560 | 3407 | #define CAN_TI1R_IDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3408 | #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3409 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 163:e59c8e839560 | 3410 | #define CAN_TI1R_EXID_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3411 | #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 3412 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3413 | #define CAN_TI1R_STID_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3414 | #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 163:e59c8e839560 | 3415 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3416 | |
| AnnaBridge | 163:e59c8e839560 | 3417 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3418 | #define CAN_TDT1R_DLC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3419 | #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 3420 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 163:e59c8e839560 | 3421 | #define CAN_TDT1R_TGT_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3422 | #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3423 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 163:e59c8e839560 | 3424 | #define CAN_TDT1R_TIME_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3425 | #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3426 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 163:e59c8e839560 | 3427 | |
| AnnaBridge | 163:e59c8e839560 | 3428 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3429 | #define CAN_TDL1R_DATA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3430 | #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3431 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3432 | #define CAN_TDL1R_DATA1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3433 | #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3434 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3435 | #define CAN_TDL1R_DATA2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3436 | #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3437 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3438 | #define CAN_TDL1R_DATA3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3439 | #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3440 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3441 | |
| AnnaBridge | 163:e59c8e839560 | 3442 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3443 | #define CAN_TDH1R_DATA4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3444 | #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3445 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3446 | #define CAN_TDH1R_DATA5_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3447 | #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3448 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3449 | #define CAN_TDH1R_DATA6_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3450 | #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3451 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3452 | #define CAN_TDH1R_DATA7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3453 | #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3454 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3455 | |
| AnnaBridge | 163:e59c8e839560 | 3456 | /******************* Bit definition for CAN_TI2R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3457 | #define CAN_TI2R_TXRQ_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3458 | #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3459 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 163:e59c8e839560 | 3460 | #define CAN_TI2R_RTR_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3461 | #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3462 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 163:e59c8e839560 | 3463 | #define CAN_TI2R_IDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3464 | #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3465 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 163:e59c8e839560 | 3466 | #define CAN_TI2R_EXID_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3467 | #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 3468 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3469 | #define CAN_TI2R_STID_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3470 | #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 163:e59c8e839560 | 3471 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3472 | |
| AnnaBridge | 163:e59c8e839560 | 3473 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3474 | #define CAN_TDT2R_DLC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3475 | #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 3476 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 163:e59c8e839560 | 3477 | #define CAN_TDT2R_TGT_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3478 | #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3479 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 163:e59c8e839560 | 3480 | #define CAN_TDT2R_TIME_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3481 | #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3482 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 163:e59c8e839560 | 3483 | |
| AnnaBridge | 163:e59c8e839560 | 3484 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3485 | #define CAN_TDL2R_DATA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3486 | #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3487 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3488 | #define CAN_TDL2R_DATA1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3489 | #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3490 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3491 | #define CAN_TDL2R_DATA2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3492 | #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3493 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3494 | #define CAN_TDL2R_DATA3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3495 | #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3496 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3497 | |
| AnnaBridge | 163:e59c8e839560 | 3498 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3499 | #define CAN_TDH2R_DATA4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3500 | #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3501 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3502 | #define CAN_TDH2R_DATA5_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3503 | #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3504 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3505 | #define CAN_TDH2R_DATA6_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3506 | #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3507 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3508 | #define CAN_TDH2R_DATA7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3509 | #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3510 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3511 | |
| AnnaBridge | 163:e59c8e839560 | 3512 | /******************* Bit definition for CAN_RI0R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3513 | #define CAN_RI0R_RTR_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3514 | #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3515 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 163:e59c8e839560 | 3516 | #define CAN_RI0R_IDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3517 | #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3518 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 163:e59c8e839560 | 3519 | #define CAN_RI0R_EXID_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3520 | #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 3521 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3522 | #define CAN_RI0R_STID_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3523 | #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 163:e59c8e839560 | 3524 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3525 | |
| AnnaBridge | 163:e59c8e839560 | 3526 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3527 | #define CAN_RDT0R_DLC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3528 | #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 3529 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 163:e59c8e839560 | 3530 | #define CAN_RDT0R_FMI_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3531 | #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3532 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 163:e59c8e839560 | 3533 | #define CAN_RDT0R_TIME_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3534 | #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3535 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 163:e59c8e839560 | 3536 | |
| AnnaBridge | 163:e59c8e839560 | 3537 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3538 | #define CAN_RDL0R_DATA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3539 | #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3540 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3541 | #define CAN_RDL0R_DATA1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3542 | #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3543 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3544 | #define CAN_RDL0R_DATA2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3545 | #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3546 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3547 | #define CAN_RDL0R_DATA3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3548 | #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3549 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3550 | |
| AnnaBridge | 163:e59c8e839560 | 3551 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3552 | #define CAN_RDH0R_DATA4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3553 | #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3554 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3555 | #define CAN_RDH0R_DATA5_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3556 | #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3557 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3558 | #define CAN_RDH0R_DATA6_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3559 | #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3560 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3561 | #define CAN_RDH0R_DATA7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3562 | #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3563 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3564 | |
| AnnaBridge | 163:e59c8e839560 | 3565 | /******************* Bit definition for CAN_RI1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3566 | #define CAN_RI1R_RTR_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3567 | #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3568 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 163:e59c8e839560 | 3569 | #define CAN_RI1R_IDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3570 | #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3571 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 163:e59c8e839560 | 3572 | #define CAN_RI1R_EXID_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3573 | #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 3574 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3575 | #define CAN_RI1R_STID_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3576 | #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 163:e59c8e839560 | 3577 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 163:e59c8e839560 | 3578 | |
| AnnaBridge | 163:e59c8e839560 | 3579 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3580 | #define CAN_RDT1R_DLC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3581 | #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 3582 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 163:e59c8e839560 | 3583 | #define CAN_RDT1R_FMI_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3584 | #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3585 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 163:e59c8e839560 | 3586 | #define CAN_RDT1R_TIME_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3587 | #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3588 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 163:e59c8e839560 | 3589 | |
| AnnaBridge | 163:e59c8e839560 | 3590 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3591 | #define CAN_RDL1R_DATA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3592 | #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3593 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3594 | #define CAN_RDL1R_DATA1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3595 | #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3596 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3597 | #define CAN_RDL1R_DATA2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3598 | #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3599 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3600 | #define CAN_RDL1R_DATA3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3601 | #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3602 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3603 | |
| AnnaBridge | 163:e59c8e839560 | 3604 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 3605 | #define CAN_RDH1R_DATA4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3606 | #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 3607 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3608 | #define CAN_RDH1R_DATA5_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3609 | #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 3610 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3611 | #define CAN_RDH1R_DATA6_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3612 | #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3613 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3614 | #define CAN_RDH1R_DATA7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3615 | #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3616 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3617 | |
| AnnaBridge | 163:e59c8e839560 | 3618 | /*!<CAN filter registers */ |
| AnnaBridge | 163:e59c8e839560 | 3619 | /******************* Bit definition for CAN_FMR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 3620 | #define CAN_FMR_FINIT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3621 | #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3622 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3623 | |
| AnnaBridge | 163:e59c8e839560 | 3624 | /******************* Bit definition for CAN_FM1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3625 | #define CAN_FM1R_FBM_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3626 | #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 163:e59c8e839560 | 3627 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ |
| AnnaBridge | 163:e59c8e839560 | 3628 | #define CAN_FM1R_FBM0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3629 | #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3630 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3631 | #define CAN_FM1R_FBM1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3632 | #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3633 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3634 | #define CAN_FM1R_FBM2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3635 | #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3636 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3637 | #define CAN_FM1R_FBM3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3638 | #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3639 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3640 | #define CAN_FM1R_FBM4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3641 | #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3642 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3643 | #define CAN_FM1R_FBM5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3644 | #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3645 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3646 | #define CAN_FM1R_FBM6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3647 | #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3648 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3649 | #define CAN_FM1R_FBM7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3650 | #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3651 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3652 | #define CAN_FM1R_FBM8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3653 | #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3654 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 3655 | #define CAN_FM1R_FBM9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3656 | #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3657 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 3658 | #define CAN_FM1R_FBM10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3659 | #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3660 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 3661 | #define CAN_FM1R_FBM11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3662 | #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3663 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 3664 | #define CAN_FM1R_FBM12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3665 | #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3666 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 3667 | #define CAN_FM1R_FBM13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3668 | #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3669 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 3670 | |
| AnnaBridge | 163:e59c8e839560 | 3671 | /******************* Bit definition for CAN_FS1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3672 | #define CAN_FS1R_FSC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3673 | #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 163:e59c8e839560 | 3674 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 3675 | #define CAN_FS1R_FSC0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3676 | #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3677 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3678 | #define CAN_FS1R_FSC1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3679 | #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3680 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3681 | #define CAN_FS1R_FSC2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3682 | #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3683 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3684 | #define CAN_FS1R_FSC3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3685 | #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3686 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3687 | #define CAN_FS1R_FSC4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3688 | #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3689 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3690 | #define CAN_FS1R_FSC5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3691 | #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3692 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3693 | #define CAN_FS1R_FSC6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3694 | #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3695 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3696 | #define CAN_FS1R_FSC7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3697 | #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3698 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3699 | #define CAN_FS1R_FSC8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3700 | #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3701 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 3702 | #define CAN_FS1R_FSC9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3703 | #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3704 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 3705 | #define CAN_FS1R_FSC10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3706 | #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3707 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 3708 | #define CAN_FS1R_FSC11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3709 | #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3710 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 3711 | #define CAN_FS1R_FSC12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3712 | #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3713 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 3714 | #define CAN_FS1R_FSC13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3715 | #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3716 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 3717 | |
| AnnaBridge | 163:e59c8e839560 | 3718 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3719 | #define CAN_FFA1R_FFA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3720 | #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 163:e59c8e839560 | 3721 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ |
| AnnaBridge | 163:e59c8e839560 | 3722 | #define CAN_FFA1R_FFA0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3723 | #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3724 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3725 | #define CAN_FFA1R_FFA1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3726 | #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3727 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3728 | #define CAN_FFA1R_FFA2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3729 | #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3730 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3731 | #define CAN_FFA1R_FFA3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3732 | #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3733 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3734 | #define CAN_FFA1R_FFA4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3735 | #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3736 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3737 | #define CAN_FFA1R_FFA5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3738 | #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3739 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3740 | #define CAN_FFA1R_FFA6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3741 | #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3742 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3743 | #define CAN_FFA1R_FFA7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3744 | #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3745 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3746 | #define CAN_FFA1R_FFA8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3747 | #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3748 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */ |
| AnnaBridge | 163:e59c8e839560 | 3749 | #define CAN_FFA1R_FFA9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3750 | #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3751 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */ |
| AnnaBridge | 163:e59c8e839560 | 3752 | #define CAN_FFA1R_FFA10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3753 | #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3754 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */ |
| AnnaBridge | 163:e59c8e839560 | 3755 | #define CAN_FFA1R_FFA11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3756 | #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3757 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */ |
| AnnaBridge | 163:e59c8e839560 | 3758 | #define CAN_FFA1R_FFA12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3759 | #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3760 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */ |
| AnnaBridge | 163:e59c8e839560 | 3761 | #define CAN_FFA1R_FFA13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3762 | #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3763 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */ |
| AnnaBridge | 163:e59c8e839560 | 3764 | |
| AnnaBridge | 163:e59c8e839560 | 3765 | /******************* Bit definition for CAN_FA1R register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3766 | #define CAN_FA1R_FACT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3767 | #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 163:e59c8e839560 | 3768 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ |
| AnnaBridge | 163:e59c8e839560 | 3769 | #define CAN_FA1R_FACT0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3770 | #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3771 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3772 | #define CAN_FA1R_FACT1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3773 | #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3774 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3775 | #define CAN_FA1R_FACT2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3776 | #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3777 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3778 | #define CAN_FA1R_FACT3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3779 | #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3780 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3781 | #define CAN_FA1R_FACT4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3782 | #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3783 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3784 | #define CAN_FA1R_FACT5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3785 | #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3786 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3787 | #define CAN_FA1R_FACT6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3788 | #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3789 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3790 | #define CAN_FA1R_FACT7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3791 | #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3792 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3793 | #define CAN_FA1R_FACT8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3794 | #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3795 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3796 | #define CAN_FA1R_FACT9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3797 | #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3798 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3799 | #define CAN_FA1R_FACT10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3800 | #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3801 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3802 | #define CAN_FA1R_FACT11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3803 | #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3804 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3805 | #define CAN_FA1R_FACT12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3806 | #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3807 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3808 | #define CAN_FA1R_FACT13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3809 | #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3810 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */ |
| AnnaBridge | 163:e59c8e839560 | 3811 | |
| AnnaBridge | 163:e59c8e839560 | 3812 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3813 | #define CAN_F0R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3814 | #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3815 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3816 | #define CAN_F0R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3817 | #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3818 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3819 | #define CAN_F0R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3820 | #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3821 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3822 | #define CAN_F0R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3823 | #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3824 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3825 | #define CAN_F0R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3826 | #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3827 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3828 | #define CAN_F0R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3829 | #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3830 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3831 | #define CAN_F0R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3832 | #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3833 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3834 | #define CAN_F0R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3835 | #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3836 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3837 | #define CAN_F0R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3838 | #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3839 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 3840 | #define CAN_F0R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3841 | #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3842 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 3843 | #define CAN_F0R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3844 | #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3845 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 3846 | #define CAN_F0R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3847 | #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3848 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 3849 | #define CAN_F0R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3850 | #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3851 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 3852 | #define CAN_F0R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3853 | #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3854 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 3855 | #define CAN_F0R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 3856 | #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 3857 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 3858 | #define CAN_F0R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 3859 | #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3860 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 3861 | #define CAN_F0R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3862 | #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3863 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 3864 | #define CAN_F0R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 3865 | #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3866 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 3867 | #define CAN_F0R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 3868 | #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 3869 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 3870 | #define CAN_F0R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 3871 | #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 3872 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 3873 | #define CAN_F0R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 3874 | #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 3875 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 3876 | #define CAN_F0R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3877 | #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 3878 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 3879 | #define CAN_F0R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 3880 | #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 3881 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 3882 | #define CAN_F0R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 3883 | #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 3884 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 3885 | #define CAN_F0R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3886 | #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3887 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 3888 | #define CAN_F0R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 3889 | #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3890 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 3891 | #define CAN_F0R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 3892 | #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3893 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 3894 | #define CAN_F0R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 3895 | #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3896 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 3897 | #define CAN_F0R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 3898 | #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3899 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 3900 | #define CAN_F0R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3901 | #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3902 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 3903 | #define CAN_F0R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 3904 | #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3905 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 3906 | #define CAN_F0R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 3907 | #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3908 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 3909 | |
| AnnaBridge | 163:e59c8e839560 | 3910 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 3911 | #define CAN_F1R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 3912 | #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 3913 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 3914 | #define CAN_F1R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 3915 | #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 3916 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 3917 | #define CAN_F1R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 3918 | #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 3919 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 3920 | #define CAN_F1R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 3921 | #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 3922 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 3923 | #define CAN_F1R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 3924 | #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 3925 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 3926 | #define CAN_F1R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 3927 | #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 3928 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 3929 | #define CAN_F1R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 3930 | #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 3931 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 3932 | #define CAN_F1R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 3933 | #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 3934 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 3935 | #define CAN_F1R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 3936 | #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 3937 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 3938 | #define CAN_F1R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 3939 | #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 3940 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 3941 | #define CAN_F1R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 3942 | #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 3943 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 3944 | #define CAN_F1R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 3945 | #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 3946 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 3947 | #define CAN_F1R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 3948 | #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 3949 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 3950 | #define CAN_F1R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 3951 | #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 3952 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 3953 | #define CAN_F1R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 3954 | #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 3955 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 3956 | #define CAN_F1R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 3957 | #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 3958 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 3959 | #define CAN_F1R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 3960 | #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 3961 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 3962 | #define CAN_F1R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 3963 | #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 3964 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 3965 | #define CAN_F1R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 3966 | #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 3967 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 3968 | #define CAN_F1R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 3969 | #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 3970 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 3971 | #define CAN_F1R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 3972 | #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 3973 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 3974 | #define CAN_F1R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 3975 | #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 3976 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 3977 | #define CAN_F1R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 3978 | #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 3979 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 3980 | #define CAN_F1R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 3981 | #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 3982 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 3983 | #define CAN_F1R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 3984 | #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3985 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 3986 | #define CAN_F1R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 3987 | #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3988 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 3989 | #define CAN_F1R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 3990 | #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3991 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 3992 | #define CAN_F1R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 3993 | #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3994 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 3995 | #define CAN_F1R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 3996 | #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 3997 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 3998 | #define CAN_F1R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 3999 | #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4000 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4001 | #define CAN_F1R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4002 | #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4003 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4004 | #define CAN_F1R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4005 | #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4006 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4007 | |
| AnnaBridge | 163:e59c8e839560 | 4008 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4009 | #define CAN_F2R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4010 | #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4011 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4012 | #define CAN_F2R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4013 | #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4014 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4015 | #define CAN_F2R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4016 | #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4017 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4018 | #define CAN_F2R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4019 | #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4020 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4021 | #define CAN_F2R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4022 | #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4023 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4024 | #define CAN_F2R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4025 | #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4026 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4027 | #define CAN_F2R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4028 | #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4029 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4030 | #define CAN_F2R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4031 | #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4032 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4033 | #define CAN_F2R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4034 | #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4035 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4036 | #define CAN_F2R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4037 | #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4038 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4039 | #define CAN_F2R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4040 | #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4041 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4042 | #define CAN_F2R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4043 | #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4044 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4045 | #define CAN_F2R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4046 | #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4047 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4048 | #define CAN_F2R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4049 | #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4050 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4051 | #define CAN_F2R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4052 | #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4053 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4054 | #define CAN_F2R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4055 | #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4056 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4057 | #define CAN_F2R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4058 | #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4059 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4060 | #define CAN_F2R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4061 | #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4062 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4063 | #define CAN_F2R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4064 | #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4065 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4066 | #define CAN_F2R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4067 | #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4068 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4069 | #define CAN_F2R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4070 | #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4071 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4072 | #define CAN_F2R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4073 | #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4074 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4075 | #define CAN_F2R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4076 | #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4077 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4078 | #define CAN_F2R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4079 | #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4080 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4081 | #define CAN_F2R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4082 | #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4083 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4084 | #define CAN_F2R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4085 | #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4086 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4087 | #define CAN_F2R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4088 | #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4089 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4090 | #define CAN_F2R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4091 | #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4092 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4093 | #define CAN_F2R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4094 | #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4095 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4096 | #define CAN_F2R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4097 | #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4098 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4099 | #define CAN_F2R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4100 | #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4101 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4102 | #define CAN_F2R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4103 | #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4104 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4105 | |
| AnnaBridge | 163:e59c8e839560 | 4106 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4107 | #define CAN_F3R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4108 | #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4109 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4110 | #define CAN_F3R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4111 | #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4112 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4113 | #define CAN_F3R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4114 | #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4115 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4116 | #define CAN_F3R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4117 | #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4118 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4119 | #define CAN_F3R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4120 | #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4121 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4122 | #define CAN_F3R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4123 | #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4124 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4125 | #define CAN_F3R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4126 | #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4127 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4128 | #define CAN_F3R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4129 | #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4130 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4131 | #define CAN_F3R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4132 | #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4133 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4134 | #define CAN_F3R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4135 | #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4136 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4137 | #define CAN_F3R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4138 | #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4139 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4140 | #define CAN_F3R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4141 | #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4142 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4143 | #define CAN_F3R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4144 | #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4145 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4146 | #define CAN_F3R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4147 | #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4148 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4149 | #define CAN_F3R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4150 | #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4151 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4152 | #define CAN_F3R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4153 | #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4154 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4155 | #define CAN_F3R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4156 | #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4157 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4158 | #define CAN_F3R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4159 | #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4160 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4161 | #define CAN_F3R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4162 | #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4163 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4164 | #define CAN_F3R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4165 | #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4166 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4167 | #define CAN_F3R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4168 | #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4169 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4170 | #define CAN_F3R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4171 | #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4172 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4173 | #define CAN_F3R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4174 | #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4175 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4176 | #define CAN_F3R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4177 | #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4178 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4179 | #define CAN_F3R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4180 | #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4181 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4182 | #define CAN_F3R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4183 | #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4184 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4185 | #define CAN_F3R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4186 | #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4187 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4188 | #define CAN_F3R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4189 | #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4190 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4191 | #define CAN_F3R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4192 | #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4193 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4194 | #define CAN_F3R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4195 | #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4196 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4197 | #define CAN_F3R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4198 | #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4199 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4200 | #define CAN_F3R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4201 | #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4202 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4203 | |
| AnnaBridge | 163:e59c8e839560 | 4204 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4205 | #define CAN_F4R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4206 | #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4207 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4208 | #define CAN_F4R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4209 | #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4210 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4211 | #define CAN_F4R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4212 | #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4213 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4214 | #define CAN_F4R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4215 | #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4216 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4217 | #define CAN_F4R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4218 | #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4219 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4220 | #define CAN_F4R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4221 | #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4222 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4223 | #define CAN_F4R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4224 | #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4225 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4226 | #define CAN_F4R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4227 | #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4228 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4229 | #define CAN_F4R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4230 | #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4231 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4232 | #define CAN_F4R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4233 | #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4234 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4235 | #define CAN_F4R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4236 | #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4237 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4238 | #define CAN_F4R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4239 | #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4240 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4241 | #define CAN_F4R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4242 | #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4243 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4244 | #define CAN_F4R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4245 | #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4246 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4247 | #define CAN_F4R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4248 | #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4249 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4250 | #define CAN_F4R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4251 | #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4252 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4253 | #define CAN_F4R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4254 | #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4255 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4256 | #define CAN_F4R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4257 | #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4258 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4259 | #define CAN_F4R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4260 | #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4261 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4262 | #define CAN_F4R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4263 | #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4264 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4265 | #define CAN_F4R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4266 | #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4267 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4268 | #define CAN_F4R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4269 | #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4270 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4271 | #define CAN_F4R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4272 | #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4273 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4274 | #define CAN_F4R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4275 | #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4276 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4277 | #define CAN_F4R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4278 | #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4279 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4280 | #define CAN_F4R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4281 | #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4282 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4283 | #define CAN_F4R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4284 | #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4285 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4286 | #define CAN_F4R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4287 | #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4288 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4289 | #define CAN_F4R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4290 | #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4291 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4292 | #define CAN_F4R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4293 | #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4294 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4295 | #define CAN_F4R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4296 | #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4297 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4298 | #define CAN_F4R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4299 | #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4300 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4301 | |
| AnnaBridge | 163:e59c8e839560 | 4302 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4303 | #define CAN_F5R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4304 | #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4305 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4306 | #define CAN_F5R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4307 | #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4308 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4309 | #define CAN_F5R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4310 | #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4311 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4312 | #define CAN_F5R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4313 | #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4314 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4315 | #define CAN_F5R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4316 | #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4317 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4318 | #define CAN_F5R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4319 | #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4320 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4321 | #define CAN_F5R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4322 | #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4323 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4324 | #define CAN_F5R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4325 | #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4326 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4327 | #define CAN_F5R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4328 | #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4329 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4330 | #define CAN_F5R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4331 | #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4332 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4333 | #define CAN_F5R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4334 | #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4335 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4336 | #define CAN_F5R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4337 | #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4338 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4339 | #define CAN_F5R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4340 | #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4341 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4342 | #define CAN_F5R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4343 | #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4344 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4345 | #define CAN_F5R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4346 | #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4347 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4348 | #define CAN_F5R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4349 | #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4350 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4351 | #define CAN_F5R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4352 | #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4353 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4354 | #define CAN_F5R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4355 | #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4356 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4357 | #define CAN_F5R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4358 | #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4359 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4360 | #define CAN_F5R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4361 | #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4362 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4363 | #define CAN_F5R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4364 | #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4365 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4366 | #define CAN_F5R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4367 | #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4368 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4369 | #define CAN_F5R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4370 | #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4371 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4372 | #define CAN_F5R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4373 | #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4374 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4375 | #define CAN_F5R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4376 | #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4377 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4378 | #define CAN_F5R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4379 | #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4380 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4381 | #define CAN_F5R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4382 | #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4383 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4384 | #define CAN_F5R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4385 | #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4386 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4387 | #define CAN_F5R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4388 | #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4389 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4390 | #define CAN_F5R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4391 | #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4392 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4393 | #define CAN_F5R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4394 | #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4395 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4396 | #define CAN_F5R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4397 | #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4398 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4399 | |
| AnnaBridge | 163:e59c8e839560 | 4400 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4401 | #define CAN_F6R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4402 | #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4403 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4404 | #define CAN_F6R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4405 | #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4406 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4407 | #define CAN_F6R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4408 | #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4409 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4410 | #define CAN_F6R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4411 | #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4412 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4413 | #define CAN_F6R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4414 | #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4415 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4416 | #define CAN_F6R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4417 | #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4418 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4419 | #define CAN_F6R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4420 | #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4421 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4422 | #define CAN_F6R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4423 | #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4424 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4425 | #define CAN_F6R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4426 | #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4427 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4428 | #define CAN_F6R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4429 | #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4430 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4431 | #define CAN_F6R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4432 | #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4433 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4434 | #define CAN_F6R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4435 | #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4436 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4437 | #define CAN_F6R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4438 | #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4439 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4440 | #define CAN_F6R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4441 | #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4442 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4443 | #define CAN_F6R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4444 | #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4445 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4446 | #define CAN_F6R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4447 | #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4448 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4449 | #define CAN_F6R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4450 | #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4451 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4452 | #define CAN_F6R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4453 | #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4454 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4455 | #define CAN_F6R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4456 | #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4457 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4458 | #define CAN_F6R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4459 | #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4460 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4461 | #define CAN_F6R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4462 | #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4463 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4464 | #define CAN_F6R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4465 | #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4466 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4467 | #define CAN_F6R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4468 | #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4469 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4470 | #define CAN_F6R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4471 | #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4472 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4473 | #define CAN_F6R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4474 | #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4475 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4476 | #define CAN_F6R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4477 | #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4478 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4479 | #define CAN_F6R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4480 | #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4481 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4482 | #define CAN_F6R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4483 | #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4484 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4485 | #define CAN_F6R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4486 | #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4487 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4488 | #define CAN_F6R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4489 | #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4490 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4491 | #define CAN_F6R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4492 | #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4493 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4494 | #define CAN_F6R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4495 | #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4496 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4497 | |
| AnnaBridge | 163:e59c8e839560 | 4498 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4499 | #define CAN_F7R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4500 | #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4501 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4502 | #define CAN_F7R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4503 | #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4504 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4505 | #define CAN_F7R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4506 | #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4507 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4508 | #define CAN_F7R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4509 | #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4510 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4511 | #define CAN_F7R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4512 | #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4513 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4514 | #define CAN_F7R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4515 | #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4516 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4517 | #define CAN_F7R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4518 | #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4519 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4520 | #define CAN_F7R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4521 | #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4522 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4523 | #define CAN_F7R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4524 | #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4525 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4526 | #define CAN_F7R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4527 | #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4528 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4529 | #define CAN_F7R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4530 | #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4531 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4532 | #define CAN_F7R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4533 | #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4534 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4535 | #define CAN_F7R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4536 | #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4537 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4538 | #define CAN_F7R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4539 | #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4540 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4541 | #define CAN_F7R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4542 | #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4543 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4544 | #define CAN_F7R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4545 | #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4546 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4547 | #define CAN_F7R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4548 | #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4549 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4550 | #define CAN_F7R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4551 | #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4552 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4553 | #define CAN_F7R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4554 | #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4555 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4556 | #define CAN_F7R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4557 | #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4558 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4559 | #define CAN_F7R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4560 | #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4561 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4562 | #define CAN_F7R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4563 | #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4564 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4565 | #define CAN_F7R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4566 | #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4567 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4568 | #define CAN_F7R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4569 | #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4570 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4571 | #define CAN_F7R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4572 | #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4573 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4574 | #define CAN_F7R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4575 | #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4576 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4577 | #define CAN_F7R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4578 | #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4579 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4580 | #define CAN_F7R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4581 | #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4582 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4583 | #define CAN_F7R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4584 | #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4585 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4586 | #define CAN_F7R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4587 | #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4588 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4589 | #define CAN_F7R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4590 | #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4591 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4592 | #define CAN_F7R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4593 | #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4594 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4595 | |
| AnnaBridge | 163:e59c8e839560 | 4596 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4597 | #define CAN_F8R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4598 | #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4599 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4600 | #define CAN_F8R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4601 | #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4602 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4603 | #define CAN_F8R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4604 | #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4605 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4606 | #define CAN_F8R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4607 | #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4608 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4609 | #define CAN_F8R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4610 | #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4611 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4612 | #define CAN_F8R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4613 | #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4614 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4615 | #define CAN_F8R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4616 | #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4617 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4618 | #define CAN_F8R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4619 | #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4620 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4621 | #define CAN_F8R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4622 | #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4623 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4624 | #define CAN_F8R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4625 | #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4626 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4627 | #define CAN_F8R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4628 | #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4629 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4630 | #define CAN_F8R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4631 | #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4632 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4633 | #define CAN_F8R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4634 | #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4635 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4636 | #define CAN_F8R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4637 | #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4638 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4639 | #define CAN_F8R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4640 | #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4641 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4642 | #define CAN_F8R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4643 | #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4644 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4645 | #define CAN_F8R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4646 | #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4647 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4648 | #define CAN_F8R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4649 | #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4650 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4651 | #define CAN_F8R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4652 | #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4653 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4654 | #define CAN_F8R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4655 | #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4656 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4657 | #define CAN_F8R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4658 | #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4659 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4660 | #define CAN_F8R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4661 | #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4662 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4663 | #define CAN_F8R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4664 | #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4665 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4666 | #define CAN_F8R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4667 | #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4668 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4669 | #define CAN_F8R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4670 | #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4671 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4672 | #define CAN_F8R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4673 | #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4674 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4675 | #define CAN_F8R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4676 | #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4677 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4678 | #define CAN_F8R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4679 | #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4680 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4681 | #define CAN_F8R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4682 | #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4683 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4684 | #define CAN_F8R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4685 | #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4686 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4687 | #define CAN_F8R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4688 | #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4689 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4690 | #define CAN_F8R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4691 | #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4692 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4693 | |
| AnnaBridge | 163:e59c8e839560 | 4694 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 4695 | #define CAN_F9R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4696 | #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4697 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4698 | #define CAN_F9R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4699 | #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4700 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4701 | #define CAN_F9R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4702 | #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4703 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4704 | #define CAN_F9R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4705 | #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4706 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4707 | #define CAN_F9R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4708 | #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4709 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4710 | #define CAN_F9R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4711 | #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4712 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4713 | #define CAN_F9R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4714 | #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4715 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4716 | #define CAN_F9R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4717 | #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4718 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4719 | #define CAN_F9R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4720 | #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4721 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4722 | #define CAN_F9R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4723 | #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4724 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4725 | #define CAN_F9R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4726 | #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4727 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4728 | #define CAN_F9R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4729 | #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4730 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4731 | #define CAN_F9R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4732 | #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4733 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4734 | #define CAN_F9R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4735 | #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4736 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4737 | #define CAN_F9R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4738 | #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4739 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4740 | #define CAN_F9R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4741 | #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4742 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4743 | #define CAN_F9R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4744 | #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4745 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4746 | #define CAN_F9R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4747 | #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4748 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4749 | #define CAN_F9R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4750 | #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4751 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4752 | #define CAN_F9R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4753 | #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4754 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4755 | #define CAN_F9R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4756 | #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4757 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4758 | #define CAN_F9R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4759 | #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4760 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4761 | #define CAN_F9R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4762 | #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4763 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4764 | #define CAN_F9R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4765 | #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4766 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4767 | #define CAN_F9R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4768 | #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4769 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4770 | #define CAN_F9R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4771 | #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4772 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4773 | #define CAN_F9R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4774 | #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4775 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4776 | #define CAN_F9R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4777 | #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4778 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4779 | #define CAN_F9R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4780 | #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4781 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4782 | #define CAN_F9R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4783 | #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4784 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4785 | #define CAN_F9R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4786 | #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4787 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4788 | #define CAN_F9R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4789 | #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4790 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4791 | |
| AnnaBridge | 163:e59c8e839560 | 4792 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 4793 | #define CAN_F10R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4794 | #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4795 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4796 | #define CAN_F10R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4797 | #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4798 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4799 | #define CAN_F10R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4800 | #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4801 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4802 | #define CAN_F10R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4803 | #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4804 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4805 | #define CAN_F10R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4806 | #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4807 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4808 | #define CAN_F10R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4809 | #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4810 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4811 | #define CAN_F10R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4812 | #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4813 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4814 | #define CAN_F10R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4815 | #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4816 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4817 | #define CAN_F10R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4818 | #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4819 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4820 | #define CAN_F10R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4821 | #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4822 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4823 | #define CAN_F10R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4824 | #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4825 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4826 | #define CAN_F10R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4827 | #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4828 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4829 | #define CAN_F10R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4830 | #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4831 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4832 | #define CAN_F10R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4833 | #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4834 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4835 | #define CAN_F10R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4836 | #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4837 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4838 | #define CAN_F10R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4839 | #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4840 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4841 | #define CAN_F10R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4842 | #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4843 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4844 | #define CAN_F10R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4845 | #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4846 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4847 | #define CAN_F10R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4848 | #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4849 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4850 | #define CAN_F10R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4851 | #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4852 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4853 | #define CAN_F10R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4854 | #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4855 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4856 | #define CAN_F10R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4857 | #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4858 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4859 | #define CAN_F10R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4860 | #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4861 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4862 | #define CAN_F10R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4863 | #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4864 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4865 | #define CAN_F10R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4866 | #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4867 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4868 | #define CAN_F10R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4869 | #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4870 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4871 | #define CAN_F10R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4872 | #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4873 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4874 | #define CAN_F10R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4875 | #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4876 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4877 | #define CAN_F10R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4878 | #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4879 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4880 | #define CAN_F10R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4881 | #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4882 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4883 | #define CAN_F10R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4884 | #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4885 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4886 | #define CAN_F10R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4887 | #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4888 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4889 | |
| AnnaBridge | 163:e59c8e839560 | 4890 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 4891 | #define CAN_F11R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4892 | #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4893 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4894 | #define CAN_F11R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4895 | #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4896 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4897 | #define CAN_F11R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4898 | #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4899 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4900 | #define CAN_F11R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4901 | #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 4902 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 4903 | #define CAN_F11R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 4904 | #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 4905 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 4906 | #define CAN_F11R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 4907 | #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 4908 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 4909 | #define CAN_F11R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 4910 | #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 4911 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 4912 | #define CAN_F11R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 4913 | #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 4914 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 4915 | #define CAN_F11R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 4916 | #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 4917 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 4918 | #define CAN_F11R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 4919 | #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 4920 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 4921 | #define CAN_F11R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 4922 | #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 4923 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 4924 | #define CAN_F11R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 4925 | #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 4926 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 4927 | #define CAN_F11R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 4928 | #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 4929 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 4930 | #define CAN_F11R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 4931 | #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 4932 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 4933 | #define CAN_F11R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 4934 | #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 4935 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 4936 | #define CAN_F11R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 4937 | #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 4938 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 4939 | #define CAN_F11R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 4940 | #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 4941 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 4942 | #define CAN_F11R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 4943 | #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 4944 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 4945 | #define CAN_F11R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 4946 | #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 4947 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 4948 | #define CAN_F11R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 4949 | #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 4950 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 4951 | #define CAN_F11R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 4952 | #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 4953 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 4954 | #define CAN_F11R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 4955 | #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 4956 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 4957 | #define CAN_F11R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 4958 | #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 4959 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 4960 | #define CAN_F11R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 4961 | #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 4962 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 4963 | #define CAN_F11R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 4964 | #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4965 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 4966 | #define CAN_F11R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 4967 | #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4968 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 4969 | #define CAN_F11R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 4970 | #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4971 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 4972 | #define CAN_F11R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 4973 | #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4974 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 4975 | #define CAN_F11R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 4976 | #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4977 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 4978 | #define CAN_F11R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 4979 | #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4980 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 4981 | #define CAN_F11R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 4982 | #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4983 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 4984 | #define CAN_F11R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 4985 | #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 4986 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 4987 | |
| AnnaBridge | 163:e59c8e839560 | 4988 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 4989 | #define CAN_F12R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 4990 | #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 4991 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 4992 | #define CAN_F12R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 4993 | #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 4994 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 4995 | #define CAN_F12R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 4996 | #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 4997 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 4998 | #define CAN_F12R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 4999 | #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5000 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5001 | #define CAN_F12R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5002 | #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5003 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5004 | #define CAN_F12R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5005 | #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5006 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5007 | #define CAN_F12R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5008 | #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5009 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5010 | #define CAN_F12R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5011 | #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5012 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5013 | #define CAN_F12R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5014 | #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5015 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5016 | #define CAN_F12R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5017 | #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5018 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5019 | #define CAN_F12R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5020 | #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5021 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5022 | #define CAN_F12R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5023 | #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5024 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5025 | #define CAN_F12R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5026 | #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5027 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5028 | #define CAN_F12R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5029 | #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5030 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5031 | #define CAN_F12R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5032 | #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5033 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5034 | #define CAN_F12R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5035 | #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5036 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5037 | #define CAN_F12R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5038 | #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5039 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5040 | #define CAN_F12R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5041 | #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5042 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5043 | #define CAN_F12R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5044 | #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5045 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5046 | #define CAN_F12R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5047 | #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5048 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5049 | #define CAN_F12R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5050 | #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5051 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5052 | #define CAN_F12R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5053 | #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5054 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5055 | #define CAN_F12R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5056 | #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5057 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5058 | #define CAN_F12R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5059 | #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5060 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5061 | #define CAN_F12R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5062 | #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5063 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5064 | #define CAN_F12R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5065 | #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5066 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5067 | #define CAN_F12R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5068 | #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5069 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5070 | #define CAN_F12R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5071 | #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5072 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5073 | #define CAN_F12R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5074 | #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5075 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5076 | #define CAN_F12R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5077 | #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5078 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5079 | #define CAN_F12R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5080 | #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5081 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5082 | #define CAN_F12R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5083 | #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5084 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5085 | |
| AnnaBridge | 163:e59c8e839560 | 5086 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 5087 | #define CAN_F13R1_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5088 | #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5089 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5090 | #define CAN_F13R1_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5091 | #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5092 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5093 | #define CAN_F13R1_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5094 | #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5095 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5096 | #define CAN_F13R1_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5097 | #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5098 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5099 | #define CAN_F13R1_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5100 | #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5101 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5102 | #define CAN_F13R1_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5103 | #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5104 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5105 | #define CAN_F13R1_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5106 | #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5107 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5108 | #define CAN_F13R1_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5109 | #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5110 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5111 | #define CAN_F13R1_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5112 | #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5113 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5114 | #define CAN_F13R1_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5115 | #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5116 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5117 | #define CAN_F13R1_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5118 | #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5119 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5120 | #define CAN_F13R1_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5121 | #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5122 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5123 | #define CAN_F13R1_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5124 | #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5125 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5126 | #define CAN_F13R1_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5127 | #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5128 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5129 | #define CAN_F13R1_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5130 | #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5131 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5132 | #define CAN_F13R1_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5133 | #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5134 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5135 | #define CAN_F13R1_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5136 | #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5137 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5138 | #define CAN_F13R1_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5139 | #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5140 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5141 | #define CAN_F13R1_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5142 | #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5143 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5144 | #define CAN_F13R1_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5145 | #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5146 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5147 | #define CAN_F13R1_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5148 | #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5149 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5150 | #define CAN_F13R1_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5151 | #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5152 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5153 | #define CAN_F13R1_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5154 | #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5155 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5156 | #define CAN_F13R1_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5157 | #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5158 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5159 | #define CAN_F13R1_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5160 | #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5161 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5162 | #define CAN_F13R1_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5163 | #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5164 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5165 | #define CAN_F13R1_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5166 | #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5167 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5168 | #define CAN_F13R1_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5169 | #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5170 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5171 | #define CAN_F13R1_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5172 | #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5173 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5174 | #define CAN_F13R1_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5175 | #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5176 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5177 | #define CAN_F13R1_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5178 | #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5179 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5180 | #define CAN_F13R1_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5181 | #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5182 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5183 | |
| AnnaBridge | 163:e59c8e839560 | 5184 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5185 | #define CAN_F0R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5186 | #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5187 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5188 | #define CAN_F0R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5189 | #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5190 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5191 | #define CAN_F0R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5192 | #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5193 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5194 | #define CAN_F0R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5195 | #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5196 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5197 | #define CAN_F0R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5198 | #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5199 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5200 | #define CAN_F0R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5201 | #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5202 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5203 | #define CAN_F0R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5204 | #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5205 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5206 | #define CAN_F0R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5207 | #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5208 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5209 | #define CAN_F0R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5210 | #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5211 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5212 | #define CAN_F0R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5213 | #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5214 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5215 | #define CAN_F0R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5216 | #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5217 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5218 | #define CAN_F0R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5219 | #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5220 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5221 | #define CAN_F0R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5222 | #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5223 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5224 | #define CAN_F0R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5225 | #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5226 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5227 | #define CAN_F0R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5228 | #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5229 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5230 | #define CAN_F0R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5231 | #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5232 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5233 | #define CAN_F0R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5234 | #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5235 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5236 | #define CAN_F0R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5237 | #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5238 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5239 | #define CAN_F0R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5240 | #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5241 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5242 | #define CAN_F0R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5243 | #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5244 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5245 | #define CAN_F0R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5246 | #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5247 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5248 | #define CAN_F0R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5249 | #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5250 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5251 | #define CAN_F0R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5252 | #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5253 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5254 | #define CAN_F0R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5255 | #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5256 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5257 | #define CAN_F0R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5258 | #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5259 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5260 | #define CAN_F0R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5261 | #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5262 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5263 | #define CAN_F0R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5264 | #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5265 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5266 | #define CAN_F0R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5267 | #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5268 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5269 | #define CAN_F0R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5270 | #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5271 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5272 | #define CAN_F0R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5273 | #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5274 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5275 | #define CAN_F0R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5276 | #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5277 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5278 | #define CAN_F0R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5279 | #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5280 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5281 | |
| AnnaBridge | 163:e59c8e839560 | 5282 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5283 | #define CAN_F1R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5284 | #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5285 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5286 | #define CAN_F1R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5287 | #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5288 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5289 | #define CAN_F1R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5290 | #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5291 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5292 | #define CAN_F1R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5293 | #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5294 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5295 | #define CAN_F1R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5296 | #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5297 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5298 | #define CAN_F1R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5299 | #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5300 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5301 | #define CAN_F1R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5302 | #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5303 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5304 | #define CAN_F1R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5305 | #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5306 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5307 | #define CAN_F1R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5308 | #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5309 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5310 | #define CAN_F1R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5311 | #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5312 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5313 | #define CAN_F1R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5314 | #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5315 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5316 | #define CAN_F1R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5317 | #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5318 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5319 | #define CAN_F1R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5320 | #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5321 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5322 | #define CAN_F1R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5323 | #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5324 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5325 | #define CAN_F1R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5326 | #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5327 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5328 | #define CAN_F1R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5329 | #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5330 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5331 | #define CAN_F1R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5332 | #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5333 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5334 | #define CAN_F1R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5335 | #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5336 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5337 | #define CAN_F1R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5338 | #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5339 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5340 | #define CAN_F1R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5341 | #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5342 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5343 | #define CAN_F1R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5344 | #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5345 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5346 | #define CAN_F1R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5347 | #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5348 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5349 | #define CAN_F1R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5350 | #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5351 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5352 | #define CAN_F1R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5353 | #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5354 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5355 | #define CAN_F1R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5356 | #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5357 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5358 | #define CAN_F1R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5359 | #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5360 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5361 | #define CAN_F1R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5362 | #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5363 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5364 | #define CAN_F1R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5365 | #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5366 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5367 | #define CAN_F1R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5368 | #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5369 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5370 | #define CAN_F1R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5371 | #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5372 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5373 | #define CAN_F1R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5374 | #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5375 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5376 | #define CAN_F1R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5377 | #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5378 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5379 | |
| AnnaBridge | 163:e59c8e839560 | 5380 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5381 | #define CAN_F2R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5382 | #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5383 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5384 | #define CAN_F2R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5385 | #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5386 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5387 | #define CAN_F2R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5388 | #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5389 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5390 | #define CAN_F2R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5391 | #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5392 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5393 | #define CAN_F2R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5394 | #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5395 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5396 | #define CAN_F2R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5397 | #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5398 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5399 | #define CAN_F2R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5400 | #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5401 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5402 | #define CAN_F2R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5403 | #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5404 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5405 | #define CAN_F2R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5406 | #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5407 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5408 | #define CAN_F2R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5409 | #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5410 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5411 | #define CAN_F2R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5412 | #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5413 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5414 | #define CAN_F2R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5415 | #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5416 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5417 | #define CAN_F2R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5418 | #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5419 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5420 | #define CAN_F2R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5421 | #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5422 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5423 | #define CAN_F2R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5424 | #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5425 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5426 | #define CAN_F2R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5427 | #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5428 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5429 | #define CAN_F2R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5430 | #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5431 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5432 | #define CAN_F2R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5433 | #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5434 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5435 | #define CAN_F2R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5436 | #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5437 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5438 | #define CAN_F2R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5439 | #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5440 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5441 | #define CAN_F2R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5442 | #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5443 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5444 | #define CAN_F2R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5445 | #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5446 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5447 | #define CAN_F2R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5448 | #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5449 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5450 | #define CAN_F2R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5451 | #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5452 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5453 | #define CAN_F2R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5454 | #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5455 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5456 | #define CAN_F2R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5457 | #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5458 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5459 | #define CAN_F2R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5460 | #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5461 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5462 | #define CAN_F2R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5463 | #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5464 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5465 | #define CAN_F2R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5466 | #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5467 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5468 | #define CAN_F2R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5469 | #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5470 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5471 | #define CAN_F2R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5472 | #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5473 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5474 | #define CAN_F2R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5475 | #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5476 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5477 | |
| AnnaBridge | 163:e59c8e839560 | 5478 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5479 | #define CAN_F3R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5480 | #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5481 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5482 | #define CAN_F3R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5483 | #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5484 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5485 | #define CAN_F3R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5486 | #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5487 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5488 | #define CAN_F3R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5489 | #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5490 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5491 | #define CAN_F3R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5492 | #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5493 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5494 | #define CAN_F3R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5495 | #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5496 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5497 | #define CAN_F3R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5498 | #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5499 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5500 | #define CAN_F3R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5501 | #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5502 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5503 | #define CAN_F3R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5504 | #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5505 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5506 | #define CAN_F3R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5507 | #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5508 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5509 | #define CAN_F3R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5510 | #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5511 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5512 | #define CAN_F3R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5513 | #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5514 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5515 | #define CAN_F3R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5516 | #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5517 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5518 | #define CAN_F3R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5519 | #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5520 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5521 | #define CAN_F3R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5522 | #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5523 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5524 | #define CAN_F3R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5525 | #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5526 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5527 | #define CAN_F3R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5528 | #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5529 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5530 | #define CAN_F3R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5531 | #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5532 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5533 | #define CAN_F3R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5534 | #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5535 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5536 | #define CAN_F3R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5537 | #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5538 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5539 | #define CAN_F3R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5540 | #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5541 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5542 | #define CAN_F3R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5543 | #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5544 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5545 | #define CAN_F3R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5546 | #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5547 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5548 | #define CAN_F3R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5549 | #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5550 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5551 | #define CAN_F3R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5552 | #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5553 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5554 | #define CAN_F3R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5555 | #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5556 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5557 | #define CAN_F3R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5558 | #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5559 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5560 | #define CAN_F3R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5561 | #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5562 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5563 | #define CAN_F3R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5564 | #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5565 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5566 | #define CAN_F3R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5567 | #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5568 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5569 | #define CAN_F3R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5570 | #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5571 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5572 | #define CAN_F3R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5573 | #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5574 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5575 | |
| AnnaBridge | 163:e59c8e839560 | 5576 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5577 | #define CAN_F4R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5578 | #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5579 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5580 | #define CAN_F4R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5581 | #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5582 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5583 | #define CAN_F4R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5584 | #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5585 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5586 | #define CAN_F4R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5587 | #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5588 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5589 | #define CAN_F4R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5590 | #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5591 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5592 | #define CAN_F4R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5593 | #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5594 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5595 | #define CAN_F4R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5596 | #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5597 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5598 | #define CAN_F4R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5599 | #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5600 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5601 | #define CAN_F4R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5602 | #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5603 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5604 | #define CAN_F4R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5605 | #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5606 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5607 | #define CAN_F4R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5608 | #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5609 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5610 | #define CAN_F4R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5611 | #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5612 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5613 | #define CAN_F4R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5614 | #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5615 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5616 | #define CAN_F4R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5617 | #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5618 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5619 | #define CAN_F4R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5620 | #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5621 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5622 | #define CAN_F4R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5623 | #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5624 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5625 | #define CAN_F4R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5626 | #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5627 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5628 | #define CAN_F4R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5629 | #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5630 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5631 | #define CAN_F4R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5632 | #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5633 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5634 | #define CAN_F4R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5635 | #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5636 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5637 | #define CAN_F4R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5638 | #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5639 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5640 | #define CAN_F4R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5641 | #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5642 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5643 | #define CAN_F4R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5644 | #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5645 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5646 | #define CAN_F4R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5647 | #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5648 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5649 | #define CAN_F4R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5650 | #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5651 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5652 | #define CAN_F4R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5653 | #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5654 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5655 | #define CAN_F4R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5656 | #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5657 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5658 | #define CAN_F4R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5659 | #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5660 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5661 | #define CAN_F4R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5662 | #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5663 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5664 | #define CAN_F4R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5665 | #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5666 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5667 | #define CAN_F4R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5668 | #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5669 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5670 | #define CAN_F4R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5671 | #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5672 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5673 | |
| AnnaBridge | 163:e59c8e839560 | 5674 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5675 | #define CAN_F5R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5676 | #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5677 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5678 | #define CAN_F5R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5679 | #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5680 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5681 | #define CAN_F5R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5682 | #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5683 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5684 | #define CAN_F5R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5685 | #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5686 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5687 | #define CAN_F5R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5688 | #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5689 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5690 | #define CAN_F5R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5691 | #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5692 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5693 | #define CAN_F5R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5694 | #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5695 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5696 | #define CAN_F5R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5697 | #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5698 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5699 | #define CAN_F5R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5700 | #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5701 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5702 | #define CAN_F5R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5703 | #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5704 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5705 | #define CAN_F5R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5706 | #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5707 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5708 | #define CAN_F5R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5709 | #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5710 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5711 | #define CAN_F5R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5712 | #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5713 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5714 | #define CAN_F5R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5715 | #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5716 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5717 | #define CAN_F5R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5718 | #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5719 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5720 | #define CAN_F5R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5721 | #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5722 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5723 | #define CAN_F5R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5724 | #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5725 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5726 | #define CAN_F5R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5727 | #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5728 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5729 | #define CAN_F5R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5730 | #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5731 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5732 | #define CAN_F5R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5733 | #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5734 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5735 | #define CAN_F5R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5736 | #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5737 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5738 | #define CAN_F5R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5739 | #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5740 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5741 | #define CAN_F5R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5742 | #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5743 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5744 | #define CAN_F5R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5745 | #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5746 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5747 | #define CAN_F5R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5748 | #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5749 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5750 | #define CAN_F5R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5751 | #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5752 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5753 | #define CAN_F5R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5754 | #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5755 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5756 | #define CAN_F5R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5757 | #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5758 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5759 | #define CAN_F5R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5760 | #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5761 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5762 | #define CAN_F5R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5763 | #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5764 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5765 | #define CAN_F5R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5766 | #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5767 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5768 | #define CAN_F5R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5769 | #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5770 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5771 | |
| AnnaBridge | 163:e59c8e839560 | 5772 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5773 | #define CAN_F6R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5774 | #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5775 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5776 | #define CAN_F6R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5777 | #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5778 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5779 | #define CAN_F6R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5780 | #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5781 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5782 | #define CAN_F6R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5783 | #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5784 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5785 | #define CAN_F6R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5786 | #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5787 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5788 | #define CAN_F6R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5789 | #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5790 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5791 | #define CAN_F6R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5792 | #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5793 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5794 | #define CAN_F6R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5795 | #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5796 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5797 | #define CAN_F6R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5798 | #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5799 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5800 | #define CAN_F6R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5801 | #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5802 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5803 | #define CAN_F6R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5804 | #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5805 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5806 | #define CAN_F6R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5807 | #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5808 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5809 | #define CAN_F6R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5810 | #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5811 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5812 | #define CAN_F6R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5813 | #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5814 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5815 | #define CAN_F6R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5816 | #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5817 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5818 | #define CAN_F6R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5819 | #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5820 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5821 | #define CAN_F6R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5822 | #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5823 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5824 | #define CAN_F6R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5825 | #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5826 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5827 | #define CAN_F6R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5828 | #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5829 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5830 | #define CAN_F6R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5831 | #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5832 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5833 | #define CAN_F6R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5834 | #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5835 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5836 | #define CAN_F6R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5837 | #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5838 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5839 | #define CAN_F6R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5840 | #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5841 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5842 | #define CAN_F6R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5843 | #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5844 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5845 | #define CAN_F6R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5846 | #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5847 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5848 | #define CAN_F6R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5849 | #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5850 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5851 | #define CAN_F6R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5852 | #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5853 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5854 | #define CAN_F6R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5855 | #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5856 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5857 | #define CAN_F6R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5858 | #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5859 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5860 | #define CAN_F6R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5861 | #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5862 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5863 | #define CAN_F6R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5864 | #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5865 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5866 | #define CAN_F6R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5867 | #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5868 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5869 | |
| AnnaBridge | 163:e59c8e839560 | 5870 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5871 | #define CAN_F7R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5872 | #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5873 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5874 | #define CAN_F7R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5875 | #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5876 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5877 | #define CAN_F7R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5878 | #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5879 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5880 | #define CAN_F7R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5881 | #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5882 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5883 | #define CAN_F7R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5884 | #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5885 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5886 | #define CAN_F7R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5887 | #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5888 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5889 | #define CAN_F7R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5890 | #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5891 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5892 | #define CAN_F7R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5893 | #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5894 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5895 | #define CAN_F7R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5896 | #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5897 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5898 | #define CAN_F7R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5899 | #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5900 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5901 | #define CAN_F7R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 5902 | #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 5903 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 5904 | #define CAN_F7R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 5905 | #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 5906 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 5907 | #define CAN_F7R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 5908 | #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 5909 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 5910 | #define CAN_F7R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 5911 | #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 5912 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 5913 | #define CAN_F7R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 5914 | #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 5915 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 5916 | #define CAN_F7R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 5917 | #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 5918 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 5919 | #define CAN_F7R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 5920 | #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 5921 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 5922 | #define CAN_F7R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 5923 | #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 5924 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 5925 | #define CAN_F7R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 5926 | #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 5927 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 5928 | #define CAN_F7R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 5929 | #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 5930 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 5931 | #define CAN_F7R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 5932 | #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 5933 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 5934 | #define CAN_F7R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 5935 | #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 5936 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 5937 | #define CAN_F7R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 5938 | #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 5939 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 5940 | #define CAN_F7R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 5941 | #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 5942 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 5943 | #define CAN_F7R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 5944 | #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5945 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 5946 | #define CAN_F7R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 5947 | #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5948 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 5949 | #define CAN_F7R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 5950 | #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5951 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 5952 | #define CAN_F7R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 5953 | #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5954 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 5955 | #define CAN_F7R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 5956 | #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5957 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 5958 | #define CAN_F7R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 5959 | #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5960 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 5961 | #define CAN_F7R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 5962 | #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5963 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 5964 | #define CAN_F7R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 5965 | #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 5966 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 5967 | |
| AnnaBridge | 163:e59c8e839560 | 5968 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 5969 | #define CAN_F8R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 5970 | #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 5971 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5972 | #define CAN_F8R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 5973 | #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 5974 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5975 | #define CAN_F8R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 5976 | #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 5977 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 5978 | #define CAN_F8R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 5979 | #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 5980 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 5981 | #define CAN_F8R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 5982 | #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 5983 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 5984 | #define CAN_F8R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 5985 | #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 5986 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 5987 | #define CAN_F8R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 5988 | #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 5989 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 5990 | #define CAN_F8R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 5991 | #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 5992 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 5993 | #define CAN_F8R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 5994 | #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 5995 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 5996 | #define CAN_F8R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 5997 | #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 5998 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 5999 | #define CAN_F8R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6000 | #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6001 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6002 | #define CAN_F8R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6003 | #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6004 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6005 | #define CAN_F8R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6006 | #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6007 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6008 | #define CAN_F8R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6009 | #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6010 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6011 | #define CAN_F8R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6012 | #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6013 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6014 | #define CAN_F8R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6015 | #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6016 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6017 | #define CAN_F8R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6018 | #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6019 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6020 | #define CAN_F8R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6021 | #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6022 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6023 | #define CAN_F8R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6024 | #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6025 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6026 | #define CAN_F8R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6027 | #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6028 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6029 | #define CAN_F8R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6030 | #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6031 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6032 | #define CAN_F8R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6033 | #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6034 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6035 | #define CAN_F8R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6036 | #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6037 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6038 | #define CAN_F8R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6039 | #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6040 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6041 | #define CAN_F8R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6042 | #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6043 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6044 | #define CAN_F8R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6045 | #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6046 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6047 | #define CAN_F8R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6048 | #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6049 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6050 | #define CAN_F8R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6051 | #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6052 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6053 | #define CAN_F8R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6054 | #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6055 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6056 | #define CAN_F8R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6057 | #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6058 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6059 | #define CAN_F8R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6060 | #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6061 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6062 | #define CAN_F8R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6063 | #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6064 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6065 | |
| AnnaBridge | 163:e59c8e839560 | 6066 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 6067 | #define CAN_F9R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6068 | #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6069 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 6070 | #define CAN_F9R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6071 | #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6072 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 6073 | #define CAN_F9R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6074 | #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6075 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 6076 | #define CAN_F9R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6077 | #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6078 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 6079 | #define CAN_F9R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6080 | #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6081 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 6082 | #define CAN_F9R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6083 | #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6084 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 6085 | #define CAN_F9R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6086 | #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6087 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 6088 | #define CAN_F9R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6089 | #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6090 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 6091 | #define CAN_F9R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6092 | #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6093 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 6094 | #define CAN_F9R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6095 | #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6096 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 6097 | #define CAN_F9R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6098 | #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6099 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6100 | #define CAN_F9R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6101 | #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6102 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6103 | #define CAN_F9R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6104 | #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6105 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6106 | #define CAN_F9R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6107 | #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6108 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6109 | #define CAN_F9R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6110 | #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6111 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6112 | #define CAN_F9R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6113 | #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6114 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6115 | #define CAN_F9R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6116 | #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6117 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6118 | #define CAN_F9R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6119 | #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6120 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6121 | #define CAN_F9R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6122 | #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6123 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6124 | #define CAN_F9R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6125 | #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6126 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6127 | #define CAN_F9R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6128 | #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6129 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6130 | #define CAN_F9R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6131 | #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6132 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6133 | #define CAN_F9R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6134 | #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6135 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6136 | #define CAN_F9R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6137 | #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6138 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6139 | #define CAN_F9R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6140 | #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6141 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6142 | #define CAN_F9R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6143 | #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6144 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6145 | #define CAN_F9R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6146 | #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6147 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6148 | #define CAN_F9R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6149 | #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6150 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6151 | #define CAN_F9R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6152 | #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6153 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6154 | #define CAN_F9R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6155 | #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6156 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6157 | #define CAN_F9R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6158 | #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6159 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6160 | #define CAN_F9R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6161 | #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6162 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6163 | |
| AnnaBridge | 163:e59c8e839560 | 6164 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6165 | #define CAN_F10R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6166 | #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6167 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 6168 | #define CAN_F10R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6169 | #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6170 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 6171 | #define CAN_F10R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6172 | #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6173 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 6174 | #define CAN_F10R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6175 | #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6176 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 6177 | #define CAN_F10R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6178 | #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6179 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 6180 | #define CAN_F10R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6181 | #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6182 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 6183 | #define CAN_F10R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6184 | #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6185 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 6186 | #define CAN_F10R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6187 | #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6188 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 6189 | #define CAN_F10R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6190 | #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6191 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 6192 | #define CAN_F10R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6193 | #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6194 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 6195 | #define CAN_F10R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6196 | #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6197 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6198 | #define CAN_F10R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6199 | #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6200 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6201 | #define CAN_F10R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6202 | #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6203 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6204 | #define CAN_F10R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6205 | #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6206 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6207 | #define CAN_F10R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6208 | #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6209 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6210 | #define CAN_F10R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6211 | #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6212 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6213 | #define CAN_F10R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6214 | #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6215 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6216 | #define CAN_F10R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6217 | #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6218 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6219 | #define CAN_F10R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6220 | #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6221 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6222 | #define CAN_F10R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6223 | #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6224 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6225 | #define CAN_F10R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6226 | #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6227 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6228 | #define CAN_F10R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6229 | #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6230 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6231 | #define CAN_F10R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6232 | #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6233 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6234 | #define CAN_F10R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6235 | #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6236 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6237 | #define CAN_F10R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6238 | #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6239 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6240 | #define CAN_F10R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6241 | #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6242 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6243 | #define CAN_F10R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6244 | #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6245 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6246 | #define CAN_F10R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6247 | #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6248 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6249 | #define CAN_F10R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6250 | #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6251 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6252 | #define CAN_F10R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6253 | #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6254 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6255 | #define CAN_F10R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6256 | #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6257 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6258 | #define CAN_F10R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6259 | #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6260 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6261 | |
| AnnaBridge | 163:e59c8e839560 | 6262 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6263 | #define CAN_F11R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6264 | #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6265 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 6266 | #define CAN_F11R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6267 | #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6268 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 6269 | #define CAN_F11R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6270 | #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6271 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 6272 | #define CAN_F11R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6273 | #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6274 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 6275 | #define CAN_F11R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6276 | #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6277 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 6278 | #define CAN_F11R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6279 | #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6280 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 6281 | #define CAN_F11R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6282 | #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6283 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 6284 | #define CAN_F11R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6285 | #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6286 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 6287 | #define CAN_F11R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6288 | #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6289 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 6290 | #define CAN_F11R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6291 | #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6292 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 6293 | #define CAN_F11R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6294 | #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6295 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6296 | #define CAN_F11R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6297 | #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6298 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6299 | #define CAN_F11R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6300 | #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6301 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6302 | #define CAN_F11R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6303 | #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6304 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6305 | #define CAN_F11R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6306 | #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6307 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6308 | #define CAN_F11R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6309 | #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6310 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6311 | #define CAN_F11R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6312 | #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6313 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6314 | #define CAN_F11R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6315 | #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6316 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6317 | #define CAN_F11R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6318 | #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6319 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6320 | #define CAN_F11R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6321 | #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6322 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6323 | #define CAN_F11R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6324 | #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6325 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6326 | #define CAN_F11R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6327 | #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6328 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6329 | #define CAN_F11R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6330 | #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6331 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6332 | #define CAN_F11R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6333 | #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6334 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6335 | #define CAN_F11R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6336 | #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6337 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6338 | #define CAN_F11R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6339 | #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6340 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6341 | #define CAN_F11R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6342 | #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6343 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6344 | #define CAN_F11R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6345 | #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6346 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6347 | #define CAN_F11R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6348 | #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6349 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6350 | #define CAN_F11R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6351 | #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6352 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6353 | #define CAN_F11R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6354 | #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6355 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6356 | #define CAN_F11R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6357 | #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6358 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6359 | |
| AnnaBridge | 163:e59c8e839560 | 6360 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6361 | #define CAN_F12R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6362 | #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6363 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 6364 | #define CAN_F12R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6365 | #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6366 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 6367 | #define CAN_F12R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6368 | #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6369 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 6370 | #define CAN_F12R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6371 | #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6372 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 6373 | #define CAN_F12R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6374 | #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6375 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 6376 | #define CAN_F12R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6377 | #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6378 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 6379 | #define CAN_F12R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6380 | #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6381 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 6382 | #define CAN_F12R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6383 | #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6384 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 6385 | #define CAN_F12R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6386 | #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6387 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 6388 | #define CAN_F12R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6389 | #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6390 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 6391 | #define CAN_F12R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6392 | #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6393 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6394 | #define CAN_F12R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6395 | #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6396 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6397 | #define CAN_F12R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6398 | #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6399 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6400 | #define CAN_F12R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6401 | #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6402 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6403 | #define CAN_F12R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6404 | #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6405 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6406 | #define CAN_F12R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6407 | #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6408 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6409 | #define CAN_F12R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6410 | #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6411 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6412 | #define CAN_F12R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6413 | #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6414 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6415 | #define CAN_F12R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6416 | #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6417 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6418 | #define CAN_F12R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6419 | #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6420 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6421 | #define CAN_F12R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6422 | #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6423 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6424 | #define CAN_F12R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6425 | #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6426 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6427 | #define CAN_F12R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6428 | #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6429 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6430 | #define CAN_F12R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6431 | #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6432 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6433 | #define CAN_F12R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6434 | #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6435 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6436 | #define CAN_F12R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6437 | #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6438 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6439 | #define CAN_F12R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6440 | #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6441 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6442 | #define CAN_F12R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6443 | #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6444 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6445 | #define CAN_F12R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6446 | #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6447 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6448 | #define CAN_F12R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6449 | #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6450 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6451 | #define CAN_F12R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6452 | #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6453 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6454 | #define CAN_F12R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6455 | #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6456 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6457 | |
| AnnaBridge | 163:e59c8e839560 | 6458 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6459 | #define CAN_F13R2_FB0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6460 | #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6461 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 6462 | #define CAN_F13R2_FB1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6463 | #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6464 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 6465 | #define CAN_F13R2_FB2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6466 | #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6467 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 6468 | #define CAN_F13R2_FB3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6469 | #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6470 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 6471 | #define CAN_F13R2_FB4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6472 | #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6473 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 163:e59c8e839560 | 6474 | #define CAN_F13R2_FB5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6475 | #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6476 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 163:e59c8e839560 | 6477 | #define CAN_F13R2_FB6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6478 | #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6479 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 163:e59c8e839560 | 6480 | #define CAN_F13R2_FB7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6481 | #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6482 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 163:e59c8e839560 | 6483 | #define CAN_F13R2_FB8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6484 | #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6485 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 163:e59c8e839560 | 6486 | #define CAN_F13R2_FB9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6487 | #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6488 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 163:e59c8e839560 | 6489 | #define CAN_F13R2_FB10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6490 | #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6491 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 163:e59c8e839560 | 6492 | #define CAN_F13R2_FB11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6493 | #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6494 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 163:e59c8e839560 | 6495 | #define CAN_F13R2_FB12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6496 | #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6497 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 163:e59c8e839560 | 6498 | #define CAN_F13R2_FB13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6499 | #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6500 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 163:e59c8e839560 | 6501 | #define CAN_F13R2_FB14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6502 | #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6503 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 163:e59c8e839560 | 6504 | #define CAN_F13R2_FB15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6505 | #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6506 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 163:e59c8e839560 | 6507 | #define CAN_F13R2_FB16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6508 | #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6509 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 163:e59c8e839560 | 6510 | #define CAN_F13R2_FB17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6511 | #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6512 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 163:e59c8e839560 | 6513 | #define CAN_F13R2_FB18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6514 | #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6515 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 163:e59c8e839560 | 6516 | #define CAN_F13R2_FB19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6517 | #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6518 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 163:e59c8e839560 | 6519 | #define CAN_F13R2_FB20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6520 | #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6521 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 163:e59c8e839560 | 6522 | #define CAN_F13R2_FB21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6523 | #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6524 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 163:e59c8e839560 | 6525 | #define CAN_F13R2_FB22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6526 | #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6527 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 163:e59c8e839560 | 6528 | #define CAN_F13R2_FB23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6529 | #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6530 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 163:e59c8e839560 | 6531 | #define CAN_F13R2_FB24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6532 | #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6533 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 163:e59c8e839560 | 6534 | #define CAN_F13R2_FB25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6535 | #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6536 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 163:e59c8e839560 | 6537 | #define CAN_F13R2_FB26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6538 | #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6539 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 163:e59c8e839560 | 6540 | #define CAN_F13R2_FB27_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6541 | #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6542 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 163:e59c8e839560 | 6543 | #define CAN_F13R2_FB28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6544 | #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6545 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 163:e59c8e839560 | 6546 | #define CAN_F13R2_FB29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6547 | #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6548 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 163:e59c8e839560 | 6549 | #define CAN_F13R2_FB30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 6550 | #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6551 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 163:e59c8e839560 | 6552 | #define CAN_F13R2_FB31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 6553 | #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6554 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 163:e59c8e839560 | 6555 | |
| AnnaBridge | 163:e59c8e839560 | 6556 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6557 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6558 | /* CRC calculation unit (CRC) */ |
| AnnaBridge | 163:e59c8e839560 | 6559 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6560 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6561 | /******************* Bit definition for CRC_DR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 6562 | #define CRC_DR_DR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6563 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 6564 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| AnnaBridge | 163:e59c8e839560 | 6565 | |
| AnnaBridge | 163:e59c8e839560 | 6566 | /******************* Bit definition for CRC_IDR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6567 | #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ |
| AnnaBridge | 163:e59c8e839560 | 6568 | |
| AnnaBridge | 163:e59c8e839560 | 6569 | /******************** Bit definition for CRC_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6570 | #define CRC_CR_RESET_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6571 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6572 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ |
| AnnaBridge | 163:e59c8e839560 | 6573 | #define CRC_CR_POLYSIZE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6574 | #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 163:e59c8e839560 | 6575 | #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ |
| AnnaBridge | 163:e59c8e839560 | 6576 | #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6577 | #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6578 | #define CRC_CR_REV_IN_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6579 | #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 6580 | #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ |
| AnnaBridge | 163:e59c8e839560 | 6581 | #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6582 | #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6583 | #define CRC_CR_REV_OUT_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6584 | #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6585 | #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ |
| AnnaBridge | 163:e59c8e839560 | 6586 | |
| AnnaBridge | 163:e59c8e839560 | 6587 | /******************* Bit definition for CRC_INIT register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 6588 | #define CRC_INIT_INIT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6589 | #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 6590 | #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ |
| AnnaBridge | 163:e59c8e839560 | 6591 | |
| AnnaBridge | 163:e59c8e839560 | 6592 | /******************* Bit definition for CRC_POL register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6593 | #define CRC_POL_POL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6594 | #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 6595 | #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ |
| AnnaBridge | 163:e59c8e839560 | 6596 | |
| AnnaBridge | 163:e59c8e839560 | 6597 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6598 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6599 | /* Digital to Analog Converter (DAC) */ |
| AnnaBridge | 163:e59c8e839560 | 6600 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6601 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6602 | |
| AnnaBridge | 163:e59c8e839560 | 6603 | /* |
| AnnaBridge | 163:e59c8e839560 | 6604 | * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| AnnaBridge | 163:e59c8e839560 | 6605 | */ |
| AnnaBridge | 163:e59c8e839560 | 6606 | #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */ |
| AnnaBridge | 163:e59c8e839560 | 6607 | |
| AnnaBridge | 163:e59c8e839560 | 6608 | |
| AnnaBridge | 163:e59c8e839560 | 6609 | /******************** Bit definition for DAC_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6610 | #define DAC_CR_EN1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6611 | #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6612 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 6613 | #define DAC_CR_BOFF1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6614 | #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6615 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ |
| AnnaBridge | 163:e59c8e839560 | 6616 | #define DAC_CR_TEN1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6617 | #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6618 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ |
| AnnaBridge | 163:e59c8e839560 | 6619 | |
| AnnaBridge | 163:e59c8e839560 | 6620 | #define DAC_CR_TSEL1_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6621 | #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 163:e59c8e839560 | 6622 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| AnnaBridge | 163:e59c8e839560 | 6623 | #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6624 | #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6625 | #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6626 | |
| AnnaBridge | 163:e59c8e839560 | 6627 | #define DAC_CR_WAVE1_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6628 | #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 6629 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| AnnaBridge | 163:e59c8e839560 | 6630 | #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6631 | #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6632 | |
| AnnaBridge | 163:e59c8e839560 | 6633 | #define DAC_CR_MAMP1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6634 | #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 6635 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| AnnaBridge | 163:e59c8e839560 | 6636 | #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6637 | #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6638 | #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6639 | #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6640 | |
| AnnaBridge | 163:e59c8e839560 | 6641 | #define DAC_CR_DMAEN1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6642 | #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6643 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ |
| AnnaBridge | 163:e59c8e839560 | 6644 | #define DAC_CR_DMAUDRIE1_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6645 | #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6646 | #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */ |
| AnnaBridge | 163:e59c8e839560 | 6647 | #define DAC_CR_EN2_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6648 | #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6649 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 6650 | #define DAC_CR_BOFF2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6651 | #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6652 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ |
| AnnaBridge | 163:e59c8e839560 | 6653 | #define DAC_CR_TEN2_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6654 | #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6655 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ |
| AnnaBridge | 163:e59c8e839560 | 6656 | |
| AnnaBridge | 163:e59c8e839560 | 6657 | #define DAC_CR_TSEL2_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6658 | #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
| AnnaBridge | 163:e59c8e839560 | 6659 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| AnnaBridge | 163:e59c8e839560 | 6660 | #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6661 | #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6662 | #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6663 | |
| AnnaBridge | 163:e59c8e839560 | 6664 | #define DAC_CR_WAVE2_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6665 | #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 6666 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| AnnaBridge | 163:e59c8e839560 | 6667 | #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6668 | #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6669 | |
| AnnaBridge | 163:e59c8e839560 | 6670 | #define DAC_CR_MAMP2_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6671 | #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6672 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| AnnaBridge | 163:e59c8e839560 | 6673 | #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6674 | #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6675 | #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6676 | #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6677 | |
| AnnaBridge | 163:e59c8e839560 | 6678 | #define DAC_CR_DMAEN2_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 6679 | #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6680 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ |
| AnnaBridge | 163:e59c8e839560 | 6681 | #define DAC_CR_DMAUDRIE2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6682 | #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6683 | #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */ |
| AnnaBridge | 163:e59c8e839560 | 6684 | |
| AnnaBridge | 163:e59c8e839560 | 6685 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6686 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6687 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6688 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ |
| AnnaBridge | 163:e59c8e839560 | 6689 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6690 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6691 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ |
| AnnaBridge | 163:e59c8e839560 | 6692 | |
| AnnaBridge | 163:e59c8e839560 | 6693 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6694 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6695 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6696 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6697 | |
| AnnaBridge | 163:e59c8e839560 | 6698 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6699 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6700 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 163:e59c8e839560 | 6701 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6702 | |
| AnnaBridge | 163:e59c8e839560 | 6703 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6704 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6705 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 6706 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6707 | |
| AnnaBridge | 163:e59c8e839560 | 6708 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6709 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6710 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6711 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6712 | |
| AnnaBridge | 163:e59c8e839560 | 6713 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6714 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6715 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 163:e59c8e839560 | 6716 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6717 | |
| AnnaBridge | 163:e59c8e839560 | 6718 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6719 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6720 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 6721 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6722 | |
| AnnaBridge | 163:e59c8e839560 | 6723 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6724 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6725 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6726 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6727 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6728 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 6729 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6730 | |
| AnnaBridge | 163:e59c8e839560 | 6731 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6732 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6733 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 163:e59c8e839560 | 6734 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6735 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6736 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
| AnnaBridge | 163:e59c8e839560 | 6737 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6738 | |
| AnnaBridge | 163:e59c8e839560 | 6739 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 6740 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6741 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 6742 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6743 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6744 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 6745 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
| AnnaBridge | 163:e59c8e839560 | 6746 | |
| AnnaBridge | 163:e59c8e839560 | 6747 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 6748 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6749 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6750 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ |
| AnnaBridge | 163:e59c8e839560 | 6751 | |
| AnnaBridge | 163:e59c8e839560 | 6752 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 6753 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6754 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6755 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ |
| AnnaBridge | 163:e59c8e839560 | 6756 | |
| AnnaBridge | 163:e59c8e839560 | 6757 | /******************** Bit definition for DAC_SR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6758 | #define DAC_SR_DMAUDR1_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6759 | #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6760 | #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 6761 | #define DAC_SR_DMAUDR2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 6762 | #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6763 | #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 6764 | |
| AnnaBridge | 163:e59c8e839560 | 6765 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6766 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6767 | /* Debug MCU (DBGMCU) */ |
| AnnaBridge | 163:e59c8e839560 | 6768 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6769 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6770 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| AnnaBridge | 163:e59c8e839560 | 6771 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6772 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 6773 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk |
| AnnaBridge | 163:e59c8e839560 | 6774 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6775 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 6776 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk |
| AnnaBridge | 163:e59c8e839560 | 6777 | |
| AnnaBridge | 163:e59c8e839560 | 6778 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 6779 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6780 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6781 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6782 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6783 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6784 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6785 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6786 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6787 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk |
| AnnaBridge | 163:e59c8e839560 | 6788 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6789 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6790 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk |
| AnnaBridge | 163:e59c8e839560 | 6791 | |
| AnnaBridge | 163:e59c8e839560 | 6792 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6793 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 6794 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk |
| AnnaBridge | 163:e59c8e839560 | 6795 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6796 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6797 | |
| AnnaBridge | 163:e59c8e839560 | 6798 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
| AnnaBridge | 163:e59c8e839560 | 6799 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6800 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6801 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6802 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6803 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6804 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6805 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6806 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6807 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6808 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6809 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6810 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6811 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6812 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6813 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6814 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6815 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6816 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6817 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6818 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6819 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6820 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6821 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6822 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6823 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6824 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6825 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 163:e59c8e839560 | 6826 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6827 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6828 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 163:e59c8e839560 | 6829 | #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6830 | #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6831 | #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6832 | |
| AnnaBridge | 163:e59c8e839560 | 6833 | /******************** Bit definition for DBGMCU_APB2_FZ register ************/ |
| AnnaBridge | 163:e59c8e839560 | 6834 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6835 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6836 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6837 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6838 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6839 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6840 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6841 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6842 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6843 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6844 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6845 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6846 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6847 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6848 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk |
| AnnaBridge | 163:e59c8e839560 | 6849 | |
| AnnaBridge | 163:e59c8e839560 | 6850 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6851 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6852 | /* DMA Controller (DMA) */ |
| AnnaBridge | 163:e59c8e839560 | 6853 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 6854 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 6855 | /******************* Bit definition for DMA_ISR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 6856 | #define DMA_ISR_GIF1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6857 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6858 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6859 | #define DMA_ISR_TCIF1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6860 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6861 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6862 | #define DMA_ISR_HTIF1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6863 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6864 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6865 | #define DMA_ISR_TEIF1_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6866 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6867 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6868 | #define DMA_ISR_GIF2_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6869 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6870 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6871 | #define DMA_ISR_TCIF2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6872 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6873 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6874 | #define DMA_ISR_HTIF2_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6875 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6876 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6877 | #define DMA_ISR_TEIF2_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6878 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6879 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6880 | #define DMA_ISR_GIF3_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6881 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6882 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6883 | #define DMA_ISR_TCIF3_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6884 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6885 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6886 | #define DMA_ISR_HTIF3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6887 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6888 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6889 | #define DMA_ISR_TEIF3_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6890 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6891 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6892 | #define DMA_ISR_GIF4_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6893 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6894 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6895 | #define DMA_ISR_TCIF4_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6896 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6897 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6898 | #define DMA_ISR_HTIF4_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6899 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6900 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6901 | #define DMA_ISR_TEIF4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6902 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6903 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6904 | #define DMA_ISR_GIF5_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6905 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6906 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6907 | #define DMA_ISR_TCIF5_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6908 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6909 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6910 | #define DMA_ISR_HTIF5_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6911 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6912 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6913 | #define DMA_ISR_TEIF5_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 6914 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 6915 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6916 | #define DMA_ISR_GIF6_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 6917 | #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 6918 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6919 | #define DMA_ISR_TCIF6_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 6920 | #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 6921 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6922 | #define DMA_ISR_HTIF6_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 6923 | #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 6924 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6925 | #define DMA_ISR_TEIF6_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 6926 | #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 6927 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6928 | #define DMA_ISR_GIF7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 6929 | #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6930 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 6931 | #define DMA_ISR_TCIF7_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 6932 | #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6933 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
| AnnaBridge | 163:e59c8e839560 | 6934 | #define DMA_ISR_HTIF7_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 6935 | #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6936 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
| AnnaBridge | 163:e59c8e839560 | 6937 | #define DMA_ISR_TEIF7_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 6938 | #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 6939 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 6940 | |
| AnnaBridge | 163:e59c8e839560 | 6941 | /******************* Bit definition for DMA_IFCR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 6942 | #define DMA_IFCR_CGIF1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 6943 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 6944 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 6945 | #define DMA_IFCR_CTCIF1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 6946 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 6947 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 6948 | #define DMA_IFCR_CHTIF1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 6949 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 6950 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 6951 | #define DMA_IFCR_CTEIF1_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 6952 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 6953 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 6954 | #define DMA_IFCR_CGIF2_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 6955 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 6956 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 6957 | #define DMA_IFCR_CTCIF2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 6958 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 6959 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 6960 | #define DMA_IFCR_CHTIF2_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 6961 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 6962 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 6963 | #define DMA_IFCR_CTEIF2_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 6964 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 6965 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 6966 | #define DMA_IFCR_CGIF3_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 6967 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 6968 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 6969 | #define DMA_IFCR_CTCIF3_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 6970 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 6971 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 6972 | #define DMA_IFCR_CHTIF3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 6973 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 6974 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 6975 | #define DMA_IFCR_CTEIF3_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 6976 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 6977 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 6978 | #define DMA_IFCR_CGIF4_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 6979 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 6980 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 6981 | #define DMA_IFCR_CTCIF4_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 6982 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 6983 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 6984 | #define DMA_IFCR_CHTIF4_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 6985 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 6986 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 6987 | #define DMA_IFCR_CTEIF4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 6988 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 6989 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 6990 | #define DMA_IFCR_CGIF5_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 6991 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 6992 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 6993 | #define DMA_IFCR_CTCIF5_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 6994 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 6995 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 6996 | #define DMA_IFCR_CHTIF5_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 6997 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 6998 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 6999 | #define DMA_IFCR_CTEIF5_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7000 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7001 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 7002 | #define DMA_IFCR_CGIF6_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7003 | #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7004 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 7005 | #define DMA_IFCR_CTCIF6_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7006 | #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7007 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 7008 | #define DMA_IFCR_CHTIF6_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7009 | #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7010 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 7011 | #define DMA_IFCR_CTEIF6_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 7012 | #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 7013 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 7014 | #define DMA_IFCR_CGIF7_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 7015 | #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7016 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 7017 | #define DMA_IFCR_CTCIF7_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 7018 | #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7019 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
| AnnaBridge | 163:e59c8e839560 | 7020 | #define DMA_IFCR_CHTIF7_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 7021 | #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7022 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
| AnnaBridge | 163:e59c8e839560 | 7023 | #define DMA_IFCR_CTEIF7_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 7024 | #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7025 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
| AnnaBridge | 163:e59c8e839560 | 7026 | |
| AnnaBridge | 163:e59c8e839560 | 7027 | /******************* Bit definition for DMA_CCR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 7028 | #define DMA_CCR_EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7029 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7030 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| AnnaBridge | 163:e59c8e839560 | 7031 | #define DMA_CCR_TCIE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7032 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7033 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 7034 | #define DMA_CCR_HTIE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7035 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7036 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 7037 | #define DMA_CCR_TEIE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7038 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7039 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 7040 | #define DMA_CCR_DIR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7041 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7042 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
| AnnaBridge | 163:e59c8e839560 | 7043 | #define DMA_CCR_CIRC_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7044 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7045 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
| AnnaBridge | 163:e59c8e839560 | 7046 | #define DMA_CCR_PINC_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7047 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7048 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| AnnaBridge | 163:e59c8e839560 | 7049 | #define DMA_CCR_MINC_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7050 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7051 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| AnnaBridge | 163:e59c8e839560 | 7052 | |
| AnnaBridge | 163:e59c8e839560 | 7053 | #define DMA_CCR_PSIZE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7054 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 7055 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| AnnaBridge | 163:e59c8e839560 | 7056 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7057 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7058 | |
| AnnaBridge | 163:e59c8e839560 | 7059 | #define DMA_CCR_MSIZE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7060 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 7061 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| AnnaBridge | 163:e59c8e839560 | 7062 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7063 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7064 | |
| AnnaBridge | 163:e59c8e839560 | 7065 | #define DMA_CCR_PL_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7066 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 7067 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ |
| AnnaBridge | 163:e59c8e839560 | 7068 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7069 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7070 | |
| AnnaBridge | 163:e59c8e839560 | 7071 | #define DMA_CCR_MEM2MEM_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7072 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7073 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| AnnaBridge | 163:e59c8e839560 | 7074 | |
| AnnaBridge | 163:e59c8e839560 | 7075 | /****************** Bit definition for DMA_CNDTR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7076 | #define DMA_CNDTR_NDT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7077 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 7078 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
| AnnaBridge | 163:e59c8e839560 | 7079 | |
| AnnaBridge | 163:e59c8e839560 | 7080 | /****************** Bit definition for DMA_CPAR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 7081 | #define DMA_CPAR_PA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7082 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 7083 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
| AnnaBridge | 163:e59c8e839560 | 7084 | |
| AnnaBridge | 163:e59c8e839560 | 7085 | /****************** Bit definition for DMA_CMAR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 7086 | #define DMA_CMAR_MA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7087 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 7088 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 163:e59c8e839560 | 7089 | |
| AnnaBridge | 163:e59c8e839560 | 7090 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 7091 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 7092 | /* External Interrupt/Event Controller (EXTI) */ |
| AnnaBridge | 163:e59c8e839560 | 7093 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 7094 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 7095 | /******************* Bit definition for EXTI_IMR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7096 | #define EXTI_IMR_MR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7097 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7098 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7099 | #define EXTI_IMR_MR1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7100 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7101 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7102 | #define EXTI_IMR_MR2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7103 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7104 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7105 | #define EXTI_IMR_MR3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7106 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7107 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7108 | #define EXTI_IMR_MR4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7109 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7110 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7111 | #define EXTI_IMR_MR5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7112 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7113 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7114 | #define EXTI_IMR_MR6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7115 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7116 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7117 | #define EXTI_IMR_MR7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7118 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7119 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7120 | #define EXTI_IMR_MR8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7121 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7122 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7123 | #define EXTI_IMR_MR9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7124 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7125 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7126 | #define EXTI_IMR_MR10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7127 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7128 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7129 | #define EXTI_IMR_MR11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7130 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7131 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7132 | #define EXTI_IMR_MR12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7133 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7134 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7135 | #define EXTI_IMR_MR13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7136 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7137 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7138 | #define EXTI_IMR_MR14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7139 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7140 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7141 | #define EXTI_IMR_MR15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7142 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7143 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7144 | #define EXTI_IMR_MR16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7145 | #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7146 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7147 | #define EXTI_IMR_MR17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7148 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7149 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7150 | #define EXTI_IMR_MR18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7151 | #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7152 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7153 | #define EXTI_IMR_MR19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7154 | #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7155 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7156 | #define EXTI_IMR_MR20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7157 | #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7158 | #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7159 | #define EXTI_IMR_MR21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7160 | #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7161 | #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7162 | #define EXTI_IMR_MR22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7163 | #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7164 | #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7165 | #define EXTI_IMR_MR23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 7166 | #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 7167 | #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ |
| AnnaBridge | 163:e59c8e839560 | 7168 | #define EXTI_IMR_MR24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 7169 | #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7170 | #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */ |
| AnnaBridge | 163:e59c8e839560 | 7171 | #define EXTI_IMR_MR25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 7172 | #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7173 | #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ |
| AnnaBridge | 163:e59c8e839560 | 7174 | #define EXTI_IMR_MR26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 7175 | #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7176 | #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */ |
| AnnaBridge | 163:e59c8e839560 | 7177 | #define EXTI_IMR_MR28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 7178 | #define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7179 | #define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */ |
| AnnaBridge | 163:e59c8e839560 | 7180 | #define EXTI_IMR_MR29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7181 | #define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7182 | #define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7183 | #define EXTI_IMR_MR30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7184 | #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7185 | #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7186 | #define EXTI_IMR_MR31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7187 | #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7188 | #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7189 | |
| AnnaBridge | 163:e59c8e839560 | 7190 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7191 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
| AnnaBridge | 163:e59c8e839560 | 7192 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
| AnnaBridge | 163:e59c8e839560 | 7193 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
| AnnaBridge | 163:e59c8e839560 | 7194 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
| AnnaBridge | 163:e59c8e839560 | 7195 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
| AnnaBridge | 163:e59c8e839560 | 7196 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
| AnnaBridge | 163:e59c8e839560 | 7197 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
| AnnaBridge | 163:e59c8e839560 | 7198 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
| AnnaBridge | 163:e59c8e839560 | 7199 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
| AnnaBridge | 163:e59c8e839560 | 7200 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
| AnnaBridge | 163:e59c8e839560 | 7201 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
| AnnaBridge | 163:e59c8e839560 | 7202 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
| AnnaBridge | 163:e59c8e839560 | 7203 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
| AnnaBridge | 163:e59c8e839560 | 7204 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
| AnnaBridge | 163:e59c8e839560 | 7205 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
| AnnaBridge | 163:e59c8e839560 | 7206 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
| AnnaBridge | 163:e59c8e839560 | 7207 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
| AnnaBridge | 163:e59c8e839560 | 7208 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| AnnaBridge | 163:e59c8e839560 | 7209 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
| AnnaBridge | 163:e59c8e839560 | 7210 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| AnnaBridge | 163:e59c8e839560 | 7211 | #define EXTI_IMR_IM20 EXTI_IMR_MR20 |
| AnnaBridge | 163:e59c8e839560 | 7212 | #define EXTI_IMR_IM21 EXTI_IMR_MR21 |
| AnnaBridge | 163:e59c8e839560 | 7213 | #define EXTI_IMR_IM22 EXTI_IMR_MR22 |
| AnnaBridge | 163:e59c8e839560 | 7214 | #define EXTI_IMR_IM23 EXTI_IMR_MR23 |
| AnnaBridge | 163:e59c8e839560 | 7215 | #define EXTI_IMR_IM24 EXTI_IMR_MR24 |
| AnnaBridge | 163:e59c8e839560 | 7216 | #define EXTI_IMR_IM25 EXTI_IMR_MR25 |
| AnnaBridge | 163:e59c8e839560 | 7217 | #define EXTI_IMR_IM26 EXTI_IMR_MR26 |
| AnnaBridge | 163:e59c8e839560 | 7218 | #if defined(EXTI_IMR_MR27) |
| AnnaBridge | 163:e59c8e839560 | 7219 | #define EXTI_IMR_IM27 EXTI_IMR_MR27 |
| AnnaBridge | 163:e59c8e839560 | 7220 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7221 | #define EXTI_IMR_IM28 EXTI_IMR_MR28 |
| AnnaBridge | 163:e59c8e839560 | 7222 | #define EXTI_IMR_IM29 EXTI_IMR_MR29 |
| AnnaBridge | 163:e59c8e839560 | 7223 | #define EXTI_IMR_IM30 EXTI_IMR_MR30 |
| AnnaBridge | 163:e59c8e839560 | 7224 | #define EXTI_IMR_IM31 EXTI_IMR_MR31 |
| AnnaBridge | 163:e59c8e839560 | 7225 | |
| AnnaBridge | 163:e59c8e839560 | 7226 | #define EXTI_IMR_IM_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7227 | #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 7228 | #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
| AnnaBridge | 163:e59c8e839560 | 7229 | |
| AnnaBridge | 163:e59c8e839560 | 7230 | /******************* Bit definition for EXTI_EMR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7231 | #define EXTI_EMR_MR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7232 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7233 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7234 | #define EXTI_EMR_MR1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7235 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7236 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7237 | #define EXTI_EMR_MR2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7238 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7239 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7240 | #define EXTI_EMR_MR3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7241 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7242 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7243 | #define EXTI_EMR_MR4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7244 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7245 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7246 | #define EXTI_EMR_MR5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7247 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7248 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7249 | #define EXTI_EMR_MR6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7250 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7251 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7252 | #define EXTI_EMR_MR7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7253 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7254 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7255 | #define EXTI_EMR_MR8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7256 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7257 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7258 | #define EXTI_EMR_MR9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7259 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7260 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7261 | #define EXTI_EMR_MR10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7262 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7263 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7264 | #define EXTI_EMR_MR11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7265 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7266 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7267 | #define EXTI_EMR_MR12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7268 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7269 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7270 | #define EXTI_EMR_MR13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7271 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7272 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7273 | #define EXTI_EMR_MR14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7274 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7275 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7276 | #define EXTI_EMR_MR15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7277 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7278 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7279 | #define EXTI_EMR_MR16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7280 | #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7281 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7282 | #define EXTI_EMR_MR17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7283 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7284 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7285 | #define EXTI_EMR_MR18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7286 | #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7287 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7288 | #define EXTI_EMR_MR19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7289 | #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7290 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7291 | #define EXTI_EMR_MR20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7292 | #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7293 | #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7294 | #define EXTI_EMR_MR21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7295 | #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7296 | #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7297 | #define EXTI_EMR_MR22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7298 | #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7299 | #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7300 | #define EXTI_EMR_MR23_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 7301 | #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 7302 | #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ |
| AnnaBridge | 163:e59c8e839560 | 7303 | #define EXTI_EMR_MR24_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 7304 | #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7305 | #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */ |
| AnnaBridge | 163:e59c8e839560 | 7306 | #define EXTI_EMR_MR25_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 7307 | #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7308 | #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ |
| AnnaBridge | 163:e59c8e839560 | 7309 | #define EXTI_EMR_MR26_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 7310 | #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7311 | #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */ |
| AnnaBridge | 163:e59c8e839560 | 7312 | #define EXTI_EMR_MR28_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 7313 | #define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7314 | #define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */ |
| AnnaBridge | 163:e59c8e839560 | 7315 | #define EXTI_EMR_MR29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7316 | #define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7317 | #define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7318 | #define EXTI_EMR_MR30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7319 | #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7320 | #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7321 | #define EXTI_EMR_MR31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7322 | #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7323 | #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7324 | |
| AnnaBridge | 163:e59c8e839560 | 7325 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7326 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| AnnaBridge | 163:e59c8e839560 | 7327 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| AnnaBridge | 163:e59c8e839560 | 7328 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| AnnaBridge | 163:e59c8e839560 | 7329 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| AnnaBridge | 163:e59c8e839560 | 7330 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| AnnaBridge | 163:e59c8e839560 | 7331 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| AnnaBridge | 163:e59c8e839560 | 7332 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| AnnaBridge | 163:e59c8e839560 | 7333 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| AnnaBridge | 163:e59c8e839560 | 7334 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| AnnaBridge | 163:e59c8e839560 | 7335 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| AnnaBridge | 163:e59c8e839560 | 7336 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| AnnaBridge | 163:e59c8e839560 | 7337 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| AnnaBridge | 163:e59c8e839560 | 7338 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| AnnaBridge | 163:e59c8e839560 | 7339 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| AnnaBridge | 163:e59c8e839560 | 7340 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| AnnaBridge | 163:e59c8e839560 | 7341 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| AnnaBridge | 163:e59c8e839560 | 7342 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| AnnaBridge | 163:e59c8e839560 | 7343 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| AnnaBridge | 163:e59c8e839560 | 7344 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
| AnnaBridge | 163:e59c8e839560 | 7345 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| AnnaBridge | 163:e59c8e839560 | 7346 | #define EXTI_EMR_EM20 EXTI_EMR_MR20 |
| AnnaBridge | 163:e59c8e839560 | 7347 | #define EXTI_EMR_EM21 EXTI_EMR_MR21 |
| AnnaBridge | 163:e59c8e839560 | 7348 | #define EXTI_EMR_EM22 EXTI_EMR_MR22 |
| AnnaBridge | 163:e59c8e839560 | 7349 | #define EXTI_EMR_EM23 EXTI_EMR_MR23 |
| AnnaBridge | 163:e59c8e839560 | 7350 | #define EXTI_EMR_EM24 EXTI_EMR_MR24 |
| AnnaBridge | 163:e59c8e839560 | 7351 | #define EXTI_EMR_EM25 EXTI_EMR_MR25 |
| AnnaBridge | 163:e59c8e839560 | 7352 | #define EXTI_EMR_EM26 EXTI_EMR_MR26 |
| AnnaBridge | 163:e59c8e839560 | 7353 | #if defined(EXTI_EMR_MR27) |
| AnnaBridge | 163:e59c8e839560 | 7354 | #define EXTI_EMR_EM27 EXTI_EMR_MR27 |
| AnnaBridge | 163:e59c8e839560 | 7355 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7356 | #define EXTI_EMR_EM28 EXTI_EMR_MR28 |
| AnnaBridge | 163:e59c8e839560 | 7357 | #define EXTI_EMR_EM29 EXTI_EMR_MR29 |
| AnnaBridge | 163:e59c8e839560 | 7358 | #define EXTI_EMR_EM30 EXTI_EMR_MR30 |
| AnnaBridge | 163:e59c8e839560 | 7359 | #define EXTI_EMR_EM31 EXTI_EMR_MR31 |
| AnnaBridge | 163:e59c8e839560 | 7360 | |
| AnnaBridge | 163:e59c8e839560 | 7361 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7362 | #define EXTI_RTSR_TR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7363 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7364 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7365 | #define EXTI_RTSR_TR1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7366 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7367 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7368 | #define EXTI_RTSR_TR2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7369 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7370 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7371 | #define EXTI_RTSR_TR3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7372 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7373 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7374 | #define EXTI_RTSR_TR4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7375 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7376 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7377 | #define EXTI_RTSR_TR5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7378 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7379 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7380 | #define EXTI_RTSR_TR6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7381 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7382 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7383 | #define EXTI_RTSR_TR7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7384 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7385 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7386 | #define EXTI_RTSR_TR8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7387 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7388 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7389 | #define EXTI_RTSR_TR9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7390 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7391 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7392 | #define EXTI_RTSR_TR10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7393 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7394 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7395 | #define EXTI_RTSR_TR11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7396 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7397 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7398 | #define EXTI_RTSR_TR12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7399 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7400 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7401 | #define EXTI_RTSR_TR13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7402 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7403 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7404 | #define EXTI_RTSR_TR14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7405 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7406 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7407 | #define EXTI_RTSR_TR15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7408 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7409 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7410 | #define EXTI_RTSR_TR16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7411 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7412 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7413 | #define EXTI_RTSR_TR17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7414 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7415 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7416 | #define EXTI_RTSR_TR18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7417 | #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7418 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7419 | #define EXTI_RTSR_TR19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7420 | #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7421 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7422 | #define EXTI_RTSR_TR20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7423 | #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7424 | #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7425 | #define EXTI_RTSR_TR21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7426 | #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7427 | #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7428 | #define EXTI_RTSR_TR22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7429 | #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7430 | #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7431 | #define EXTI_RTSR_TR29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7432 | #define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7433 | #define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7434 | #define EXTI_RTSR_TR30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7435 | #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7436 | #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7437 | #define EXTI_RTSR_TR31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7438 | #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7439 | #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7440 | |
| AnnaBridge | 163:e59c8e839560 | 7441 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7442 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
| AnnaBridge | 163:e59c8e839560 | 7443 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
| AnnaBridge | 163:e59c8e839560 | 7444 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
| AnnaBridge | 163:e59c8e839560 | 7445 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
| AnnaBridge | 163:e59c8e839560 | 7446 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
| AnnaBridge | 163:e59c8e839560 | 7447 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
| AnnaBridge | 163:e59c8e839560 | 7448 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
| AnnaBridge | 163:e59c8e839560 | 7449 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
| AnnaBridge | 163:e59c8e839560 | 7450 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
| AnnaBridge | 163:e59c8e839560 | 7451 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
| AnnaBridge | 163:e59c8e839560 | 7452 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
| AnnaBridge | 163:e59c8e839560 | 7453 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
| AnnaBridge | 163:e59c8e839560 | 7454 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
| AnnaBridge | 163:e59c8e839560 | 7455 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
| AnnaBridge | 163:e59c8e839560 | 7456 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
| AnnaBridge | 163:e59c8e839560 | 7457 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
| AnnaBridge | 163:e59c8e839560 | 7458 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
| AnnaBridge | 163:e59c8e839560 | 7459 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
| AnnaBridge | 163:e59c8e839560 | 7460 | #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 |
| AnnaBridge | 163:e59c8e839560 | 7461 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
| AnnaBridge | 163:e59c8e839560 | 7462 | #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 |
| AnnaBridge | 163:e59c8e839560 | 7463 | #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 |
| AnnaBridge | 163:e59c8e839560 | 7464 | #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 |
| AnnaBridge | 163:e59c8e839560 | 7465 | #if defined(EXTI_RTSR_TR23) |
| AnnaBridge | 163:e59c8e839560 | 7466 | #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 |
| AnnaBridge | 163:e59c8e839560 | 7467 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7468 | #if defined(EXTI_RTSR_TR24) |
| AnnaBridge | 163:e59c8e839560 | 7469 | #define EXTI_RTSR_RT24 EXTI_RTSR_TR24 |
| AnnaBridge | 163:e59c8e839560 | 7470 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7471 | #if defined(EXTI_RTSR_TR25) |
| AnnaBridge | 163:e59c8e839560 | 7472 | #define EXTI_RTSR_RT25 EXTI_RTSR_TR25 |
| AnnaBridge | 163:e59c8e839560 | 7473 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7474 | #if defined(EXTI_RTSR_TR26) |
| AnnaBridge | 163:e59c8e839560 | 7475 | #define EXTI_RTSR_RT26 EXTI_RTSR_TR26 |
| AnnaBridge | 163:e59c8e839560 | 7476 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7477 | #if defined(EXTI_RTSR_TR27) |
| AnnaBridge | 163:e59c8e839560 | 7478 | #define EXTI_RTSR_RT27 EXTI_RTSR_TR27 |
| AnnaBridge | 163:e59c8e839560 | 7479 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7480 | #if defined(EXTI_RTSR_TR28) |
| AnnaBridge | 163:e59c8e839560 | 7481 | #define EXTI_RTSR_RT28 EXTI_RTSR_TR28 |
| AnnaBridge | 163:e59c8e839560 | 7482 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7483 | #define EXTI_RTSR_RT29 EXTI_RTSR_TR29 |
| AnnaBridge | 163:e59c8e839560 | 7484 | #define EXTI_RTSR_RT30 EXTI_RTSR_TR30 |
| AnnaBridge | 163:e59c8e839560 | 7485 | #define EXTI_RTSR_RT31 EXTI_RTSR_TR31 |
| AnnaBridge | 163:e59c8e839560 | 7486 | |
| AnnaBridge | 163:e59c8e839560 | 7487 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7488 | #define EXTI_FTSR_TR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7489 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7490 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7491 | #define EXTI_FTSR_TR1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7492 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7493 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7494 | #define EXTI_FTSR_TR2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7495 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7496 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7497 | #define EXTI_FTSR_TR3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7498 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7499 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7500 | #define EXTI_FTSR_TR4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7501 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7502 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7503 | #define EXTI_FTSR_TR5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7504 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7505 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7506 | #define EXTI_FTSR_TR6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7507 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7508 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7509 | #define EXTI_FTSR_TR7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7510 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7511 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7512 | #define EXTI_FTSR_TR8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7513 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7514 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7515 | #define EXTI_FTSR_TR9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7516 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7517 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7518 | #define EXTI_FTSR_TR10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7519 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7520 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7521 | #define EXTI_FTSR_TR11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7522 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7523 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7524 | #define EXTI_FTSR_TR12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7525 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7526 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7527 | #define EXTI_FTSR_TR13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7528 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7529 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7530 | #define EXTI_FTSR_TR14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7531 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7532 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7533 | #define EXTI_FTSR_TR15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7534 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7535 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7536 | #define EXTI_FTSR_TR16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7537 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7538 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7539 | #define EXTI_FTSR_TR17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7540 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7541 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7542 | #define EXTI_FTSR_TR18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7543 | #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7544 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7545 | #define EXTI_FTSR_TR19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7546 | #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7547 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7548 | #define EXTI_FTSR_TR20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7549 | #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7550 | #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7551 | #define EXTI_FTSR_TR21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7552 | #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7553 | #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7554 | #define EXTI_FTSR_TR22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7555 | #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7556 | #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7557 | #define EXTI_FTSR_TR29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7558 | #define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7559 | #define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7560 | #define EXTI_FTSR_TR30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7561 | #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7562 | #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7563 | #define EXTI_FTSR_TR31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7564 | #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7565 | #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7566 | |
| AnnaBridge | 163:e59c8e839560 | 7567 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7568 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
| AnnaBridge | 163:e59c8e839560 | 7569 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
| AnnaBridge | 163:e59c8e839560 | 7570 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
| AnnaBridge | 163:e59c8e839560 | 7571 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
| AnnaBridge | 163:e59c8e839560 | 7572 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
| AnnaBridge | 163:e59c8e839560 | 7573 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
| AnnaBridge | 163:e59c8e839560 | 7574 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
| AnnaBridge | 163:e59c8e839560 | 7575 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
| AnnaBridge | 163:e59c8e839560 | 7576 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
| AnnaBridge | 163:e59c8e839560 | 7577 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
| AnnaBridge | 163:e59c8e839560 | 7578 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
| AnnaBridge | 163:e59c8e839560 | 7579 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
| AnnaBridge | 163:e59c8e839560 | 7580 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
| AnnaBridge | 163:e59c8e839560 | 7581 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
| AnnaBridge | 163:e59c8e839560 | 7582 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
| AnnaBridge | 163:e59c8e839560 | 7583 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
| AnnaBridge | 163:e59c8e839560 | 7584 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
| AnnaBridge | 163:e59c8e839560 | 7585 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
| AnnaBridge | 163:e59c8e839560 | 7586 | #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 |
| AnnaBridge | 163:e59c8e839560 | 7587 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
| AnnaBridge | 163:e59c8e839560 | 7588 | #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 |
| AnnaBridge | 163:e59c8e839560 | 7589 | #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 |
| AnnaBridge | 163:e59c8e839560 | 7590 | #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 |
| AnnaBridge | 163:e59c8e839560 | 7591 | #if defined(EXTI_FTSR_TR23) |
| AnnaBridge | 163:e59c8e839560 | 7592 | #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 |
| AnnaBridge | 163:e59c8e839560 | 7593 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7594 | #if defined(EXTI_FTSR_TR24) |
| AnnaBridge | 163:e59c8e839560 | 7595 | #define EXTI_FTSR_FT24 EXTI_FTSR_TR24 |
| AnnaBridge | 163:e59c8e839560 | 7596 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7597 | #if defined(EXTI_FTSR_TR25) |
| AnnaBridge | 163:e59c8e839560 | 7598 | #define EXTI_FTSR_FT25 EXTI_FTSR_TR25 |
| AnnaBridge | 163:e59c8e839560 | 7599 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7600 | #if defined(EXTI_FTSR_TR26) |
| AnnaBridge | 163:e59c8e839560 | 7601 | #define EXTI_FTSR_FT26 EXTI_FTSR_TR26 |
| AnnaBridge | 163:e59c8e839560 | 7602 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7603 | #if defined(EXTI_FTSR_TR27) |
| AnnaBridge | 163:e59c8e839560 | 7604 | #define EXTI_FTSR_FT27 EXTI_FTSR_TR27 |
| AnnaBridge | 163:e59c8e839560 | 7605 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7606 | #if defined(EXTI_FTSR_TR28) |
| AnnaBridge | 163:e59c8e839560 | 7607 | #define EXTI_FTSR_FT28 EXTI_FTSR_TR28 |
| AnnaBridge | 163:e59c8e839560 | 7608 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7609 | #define EXTI_FTSR_FT29 EXTI_FTSR_TR29 |
| AnnaBridge | 163:e59c8e839560 | 7610 | #define EXTI_FTSR_FT30 EXTI_FTSR_TR30 |
| AnnaBridge | 163:e59c8e839560 | 7611 | #define EXTI_FTSR_FT31 EXTI_FTSR_TR31 |
| AnnaBridge | 163:e59c8e839560 | 7612 | |
| AnnaBridge | 163:e59c8e839560 | 7613 | /****************** Bit definition for EXTI_SWIER register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 7614 | #define EXTI_SWIER_SWIER0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7615 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7616 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7617 | #define EXTI_SWIER_SWIER1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7618 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7619 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7620 | #define EXTI_SWIER_SWIER2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7621 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7622 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7623 | #define EXTI_SWIER_SWIER3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7624 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7625 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7626 | #define EXTI_SWIER_SWIER4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7627 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7628 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7629 | #define EXTI_SWIER_SWIER5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7630 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7631 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7632 | #define EXTI_SWIER_SWIER6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7633 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7634 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7635 | #define EXTI_SWIER_SWIER7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7636 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7637 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7638 | #define EXTI_SWIER_SWIER8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7639 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7640 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7641 | #define EXTI_SWIER_SWIER9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7642 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7643 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7644 | #define EXTI_SWIER_SWIER10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7645 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7646 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7647 | #define EXTI_SWIER_SWIER11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7648 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7649 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7650 | #define EXTI_SWIER_SWIER12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7651 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7652 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7653 | #define EXTI_SWIER_SWIER13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7654 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7655 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7656 | #define EXTI_SWIER_SWIER14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7657 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7658 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7659 | #define EXTI_SWIER_SWIER15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7660 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7661 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7662 | #define EXTI_SWIER_SWIER16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7663 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7664 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7665 | #define EXTI_SWIER_SWIER17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7666 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7667 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7668 | #define EXTI_SWIER_SWIER18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7669 | #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7670 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7671 | #define EXTI_SWIER_SWIER19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7672 | #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7673 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7674 | #define EXTI_SWIER_SWIER20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7675 | #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7676 | #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7677 | #define EXTI_SWIER_SWIER21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7678 | #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7679 | #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7680 | #define EXTI_SWIER_SWIER22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7681 | #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7682 | #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7683 | #define EXTI_SWIER_SWIER29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7684 | #define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7685 | #define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7686 | #define EXTI_SWIER_SWIER30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7687 | #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7688 | #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7689 | #define EXTI_SWIER_SWIER31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7690 | #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7691 | #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7692 | |
| AnnaBridge | 163:e59c8e839560 | 7693 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7694 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
| AnnaBridge | 163:e59c8e839560 | 7695 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
| AnnaBridge | 163:e59c8e839560 | 7696 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
| AnnaBridge | 163:e59c8e839560 | 7697 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
| AnnaBridge | 163:e59c8e839560 | 7698 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
| AnnaBridge | 163:e59c8e839560 | 7699 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
| AnnaBridge | 163:e59c8e839560 | 7700 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
| AnnaBridge | 163:e59c8e839560 | 7701 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
| AnnaBridge | 163:e59c8e839560 | 7702 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
| AnnaBridge | 163:e59c8e839560 | 7703 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
| AnnaBridge | 163:e59c8e839560 | 7704 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
| AnnaBridge | 163:e59c8e839560 | 7705 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
| AnnaBridge | 163:e59c8e839560 | 7706 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
| AnnaBridge | 163:e59c8e839560 | 7707 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
| AnnaBridge | 163:e59c8e839560 | 7708 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
| AnnaBridge | 163:e59c8e839560 | 7709 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
| AnnaBridge | 163:e59c8e839560 | 7710 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
| AnnaBridge | 163:e59c8e839560 | 7711 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
| AnnaBridge | 163:e59c8e839560 | 7712 | #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 |
| AnnaBridge | 163:e59c8e839560 | 7713 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
| AnnaBridge | 163:e59c8e839560 | 7714 | #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 |
| AnnaBridge | 163:e59c8e839560 | 7715 | #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 |
| AnnaBridge | 163:e59c8e839560 | 7716 | #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 |
| AnnaBridge | 163:e59c8e839560 | 7717 | #if defined(EXTI_SWIER_SWIER23) |
| AnnaBridge | 163:e59c8e839560 | 7718 | #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 |
| AnnaBridge | 163:e59c8e839560 | 7719 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7720 | #if defined(EXTI_SWIER_SWIER24) |
| AnnaBridge | 163:e59c8e839560 | 7721 | #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24 |
| AnnaBridge | 163:e59c8e839560 | 7722 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7723 | #if defined(EXTI_SWIER_SWIER25) |
| AnnaBridge | 163:e59c8e839560 | 7724 | #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25 |
| AnnaBridge | 163:e59c8e839560 | 7725 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7726 | #if defined(EXTI_SWIER_SWIER26) |
| AnnaBridge | 163:e59c8e839560 | 7727 | #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26 |
| AnnaBridge | 163:e59c8e839560 | 7728 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7729 | #if defined(EXTI_SWIER_SWIER27) |
| AnnaBridge | 163:e59c8e839560 | 7730 | #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27 |
| AnnaBridge | 163:e59c8e839560 | 7731 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7732 | #if defined(EXTI_SWIER_SWIER28) |
| AnnaBridge | 163:e59c8e839560 | 7733 | #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28 |
| AnnaBridge | 163:e59c8e839560 | 7734 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7735 | #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29 |
| AnnaBridge | 163:e59c8e839560 | 7736 | #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30 |
| AnnaBridge | 163:e59c8e839560 | 7737 | #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 |
| AnnaBridge | 163:e59c8e839560 | 7738 | |
| AnnaBridge | 163:e59c8e839560 | 7739 | /******************* Bit definition for EXTI_PR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 7740 | #define EXTI_PR_PR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7741 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7742 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7743 | #define EXTI_PR_PR1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7744 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7745 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
| AnnaBridge | 163:e59c8e839560 | 7746 | #define EXTI_PR_PR2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7747 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7748 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
| AnnaBridge | 163:e59c8e839560 | 7749 | #define EXTI_PR_PR3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7750 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7751 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
| AnnaBridge | 163:e59c8e839560 | 7752 | #define EXTI_PR_PR4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 7753 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 7754 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
| AnnaBridge | 163:e59c8e839560 | 7755 | #define EXTI_PR_PR5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 7756 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 7757 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
| AnnaBridge | 163:e59c8e839560 | 7758 | #define EXTI_PR_PR6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 7759 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 7760 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
| AnnaBridge | 163:e59c8e839560 | 7761 | #define EXTI_PR_PR7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 7762 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 7763 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
| AnnaBridge | 163:e59c8e839560 | 7764 | #define EXTI_PR_PR8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 7765 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 7766 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
| AnnaBridge | 163:e59c8e839560 | 7767 | #define EXTI_PR_PR9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 7768 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 7769 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
| AnnaBridge | 163:e59c8e839560 | 7770 | #define EXTI_PR_PR10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 7771 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 7772 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
| AnnaBridge | 163:e59c8e839560 | 7773 | #define EXTI_PR_PR11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 7774 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 7775 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
| AnnaBridge | 163:e59c8e839560 | 7776 | #define EXTI_PR_PR12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 7777 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 7778 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
| AnnaBridge | 163:e59c8e839560 | 7779 | #define EXTI_PR_PR13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 7780 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 7781 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
| AnnaBridge | 163:e59c8e839560 | 7782 | #define EXTI_PR_PR14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 7783 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 7784 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
| AnnaBridge | 163:e59c8e839560 | 7785 | #define EXTI_PR_PR15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 7786 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 7787 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
| AnnaBridge | 163:e59c8e839560 | 7788 | #define EXTI_PR_PR16_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 7789 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 7790 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
| AnnaBridge | 163:e59c8e839560 | 7791 | #define EXTI_PR_PR17_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 7792 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 7793 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
| AnnaBridge | 163:e59c8e839560 | 7794 | #define EXTI_PR_PR18_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 7795 | #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 7796 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
| AnnaBridge | 163:e59c8e839560 | 7797 | #define EXTI_PR_PR19_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 7798 | #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 7799 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
| AnnaBridge | 163:e59c8e839560 | 7800 | #define EXTI_PR_PR20_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 7801 | #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 7802 | #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ |
| AnnaBridge | 163:e59c8e839560 | 7803 | #define EXTI_PR_PR21_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 7804 | #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 7805 | #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ |
| AnnaBridge | 163:e59c8e839560 | 7806 | #define EXTI_PR_PR22_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 7807 | #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 7808 | #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ |
| AnnaBridge | 163:e59c8e839560 | 7809 | #define EXTI_PR_PR29_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 7810 | #define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7811 | #define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */ |
| AnnaBridge | 163:e59c8e839560 | 7812 | #define EXTI_PR_PR30_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 7813 | #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7814 | #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */ |
| AnnaBridge | 163:e59c8e839560 | 7815 | #define EXTI_PR_PR31_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 7816 | #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 7817 | #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */ |
| AnnaBridge | 163:e59c8e839560 | 7818 | |
| AnnaBridge | 163:e59c8e839560 | 7819 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7820 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
| AnnaBridge | 163:e59c8e839560 | 7821 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
| AnnaBridge | 163:e59c8e839560 | 7822 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
| AnnaBridge | 163:e59c8e839560 | 7823 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
| AnnaBridge | 163:e59c8e839560 | 7824 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
| AnnaBridge | 163:e59c8e839560 | 7825 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
| AnnaBridge | 163:e59c8e839560 | 7826 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
| AnnaBridge | 163:e59c8e839560 | 7827 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
| AnnaBridge | 163:e59c8e839560 | 7828 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
| AnnaBridge | 163:e59c8e839560 | 7829 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
| AnnaBridge | 163:e59c8e839560 | 7830 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
| AnnaBridge | 163:e59c8e839560 | 7831 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
| AnnaBridge | 163:e59c8e839560 | 7832 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
| AnnaBridge | 163:e59c8e839560 | 7833 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
| AnnaBridge | 163:e59c8e839560 | 7834 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
| AnnaBridge | 163:e59c8e839560 | 7835 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
| AnnaBridge | 163:e59c8e839560 | 7836 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
| AnnaBridge | 163:e59c8e839560 | 7837 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
| AnnaBridge | 163:e59c8e839560 | 7838 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
| AnnaBridge | 163:e59c8e839560 | 7839 | #define EXTI_PR_PIF18 EXTI_PR_PR18 |
| AnnaBridge | 163:e59c8e839560 | 7840 | #define EXTI_PR_PIF19 EXTI_PR_PR19 |
| AnnaBridge | 163:e59c8e839560 | 7841 | #define EXTI_PR_PIF20 EXTI_PR_PR20 |
| AnnaBridge | 163:e59c8e839560 | 7842 | #define EXTI_PR_PIF21 EXTI_PR_PR21 |
| AnnaBridge | 163:e59c8e839560 | 7843 | #define EXTI_PR_PIF22 EXTI_PR_PR22 |
| AnnaBridge | 163:e59c8e839560 | 7844 | #if defined(EXTI_PR_PR23) |
| AnnaBridge | 163:e59c8e839560 | 7845 | #define EXTI_PR_PIF23 EXTI_PR_PR23 |
| AnnaBridge | 163:e59c8e839560 | 7846 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7847 | #if defined(EXTI_PR_PR24) |
| AnnaBridge | 163:e59c8e839560 | 7848 | #define EXTI_PR_PIF24 EXTI_PR_PR24 |
| AnnaBridge | 163:e59c8e839560 | 7849 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7850 | #if defined(EXTI_PR_PR25) |
| AnnaBridge | 163:e59c8e839560 | 7851 | #define EXTI_PR_PIF25 EXTI_PR_PR25 |
| AnnaBridge | 163:e59c8e839560 | 7852 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7853 | #if defined(EXTI_PR_PR26) |
| AnnaBridge | 163:e59c8e839560 | 7854 | #define EXTI_PR_PIF26 EXTI_PR_PR26 |
| AnnaBridge | 163:e59c8e839560 | 7855 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7856 | #if defined(EXTI_PR_PR27) |
| AnnaBridge | 163:e59c8e839560 | 7857 | #define EXTI_PR_PIF27 EXTI_PR_PR27 |
| AnnaBridge | 163:e59c8e839560 | 7858 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7859 | #if defined(EXTI_PR_PR28) |
| AnnaBridge | 163:e59c8e839560 | 7860 | #define EXTI_PR_PIF28 EXTI_PR_PR28 |
| AnnaBridge | 163:e59c8e839560 | 7861 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7862 | #define EXTI_PR_PIF29 EXTI_PR_PR29 |
| AnnaBridge | 163:e59c8e839560 | 7863 | #define EXTI_PR_PIF30 EXTI_PR_PR30 |
| AnnaBridge | 163:e59c8e839560 | 7864 | #define EXTI_PR_PIF31 EXTI_PR_PR31 |
| AnnaBridge | 163:e59c8e839560 | 7865 | |
| AnnaBridge | 163:e59c8e839560 | 7866 | #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */ |
| AnnaBridge | 163:e59c8e839560 | 7867 | |
| AnnaBridge | 163:e59c8e839560 | 7868 | /******************* Bit definition for EXTI_IMR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 7869 | #define EXTI_IMR2_MR32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7870 | #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7871 | #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7872 | #define EXTI_IMR2_MR33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7873 | #define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7874 | #define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7875 | #define EXTI_IMR2_MR34_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7876 | #define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7877 | #define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */ |
| AnnaBridge | 163:e59c8e839560 | 7878 | #define EXTI_IMR2_MR35_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7879 | #define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7880 | #define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */ |
| AnnaBridge | 163:e59c8e839560 | 7881 | |
| AnnaBridge | 163:e59c8e839560 | 7882 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7883 | |
| AnnaBridge | 163:e59c8e839560 | 7884 | #define EXTI_IMR2_IM32 EXTI_IMR2_MR32 |
| AnnaBridge | 163:e59c8e839560 | 7885 | #define EXTI_IMR2_IM33 EXTI_IMR2_MR33 |
| AnnaBridge | 163:e59c8e839560 | 7886 | #define EXTI_IMR2_IM34 EXTI_IMR2_MR34 |
| AnnaBridge | 163:e59c8e839560 | 7887 | #define EXTI_IMR2_IM35 EXTI_IMR2_MR35 |
| AnnaBridge | 163:e59c8e839560 | 7888 | |
| AnnaBridge | 163:e59c8e839560 | 7889 | #define EXTI_IMR2_IM_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7890 | #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 7891 | #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk |
| AnnaBridge | 163:e59c8e839560 | 7892 | |
| AnnaBridge | 163:e59c8e839560 | 7893 | /******************* Bit definition for EXTI_EMR2 ****************************/ |
| AnnaBridge | 163:e59c8e839560 | 7894 | #define EXTI_EMR2_MR32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7895 | #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7896 | #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7897 | #define EXTI_EMR2_MR33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7898 | #define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7899 | #define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7900 | #define EXTI_EMR2_MR34_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 7901 | #define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 7902 | #define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */ |
| AnnaBridge | 163:e59c8e839560 | 7903 | #define EXTI_EMR2_MR35_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 7904 | #define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 7905 | #define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */ |
| AnnaBridge | 163:e59c8e839560 | 7906 | |
| AnnaBridge | 163:e59c8e839560 | 7907 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7908 | #define EXTI_EMR2_EM32 EXTI_EMR2_MR32 |
| AnnaBridge | 163:e59c8e839560 | 7909 | #define EXTI_EMR2_EM33 EXTI_EMR2_MR33 |
| AnnaBridge | 163:e59c8e839560 | 7910 | #define EXTI_EMR2_EM34 EXTI_EMR2_MR34 |
| AnnaBridge | 163:e59c8e839560 | 7911 | #define EXTI_EMR2_EM35 EXTI_EMR2_MR35 |
| AnnaBridge | 163:e59c8e839560 | 7912 | |
| AnnaBridge | 168:b9e159c1930a | 7913 | #define EXTI_EMR2_EM_Pos (0U) |
| AnnaBridge | 168:b9e159c1930a | 7914 | #define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 168:b9e159c1930a | 7915 | #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk |
| AnnaBridge | 168:b9e159c1930a | 7916 | |
| AnnaBridge | 163:e59c8e839560 | 7917 | /****************** Bit definition for EXTI_RTSR2 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 7918 | #define EXTI_RTSR2_TR32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7919 | #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7920 | #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7921 | #define EXTI_RTSR2_TR33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7922 | #define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7923 | #define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7924 | |
| AnnaBridge | 163:e59c8e839560 | 7925 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7926 | #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32 |
| AnnaBridge | 163:e59c8e839560 | 7927 | #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33 |
| AnnaBridge | 163:e59c8e839560 | 7928 | #if defined(EXTI_RTSR2_TR34) |
| AnnaBridge | 163:e59c8e839560 | 7929 | #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34 |
| AnnaBridge | 163:e59c8e839560 | 7930 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7931 | #if defined(EXTI_RTSR2_TR35) |
| AnnaBridge | 163:e59c8e839560 | 7932 | #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35 |
| AnnaBridge | 163:e59c8e839560 | 7933 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7934 | |
| AnnaBridge | 163:e59c8e839560 | 7935 | /****************** Bit definition for EXTI_FTSR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 7936 | #define EXTI_FTSR2_TR32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7937 | #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7938 | #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7939 | #define EXTI_FTSR2_TR33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7940 | #define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7941 | #define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7942 | |
| AnnaBridge | 163:e59c8e839560 | 7943 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7944 | #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32 |
| AnnaBridge | 163:e59c8e839560 | 7945 | #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33 |
| AnnaBridge | 163:e59c8e839560 | 7946 | #if defined(EXTI_FTSR2_TR34) |
| AnnaBridge | 163:e59c8e839560 | 7947 | #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34 |
| AnnaBridge | 163:e59c8e839560 | 7948 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7949 | #if defined(EXTI_FTSR2_TR35) |
| AnnaBridge | 163:e59c8e839560 | 7950 | #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35 |
| AnnaBridge | 163:e59c8e839560 | 7951 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7952 | |
| AnnaBridge | 163:e59c8e839560 | 7953 | /****************** Bit definition for EXTI_SWIER2 register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 7954 | #define EXTI_SWIER2_SWIER32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7955 | #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7956 | #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7957 | #define EXTI_SWIER2_SWIER33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7958 | #define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7959 | #define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7960 | |
| AnnaBridge | 163:e59c8e839560 | 7961 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7962 | #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32 |
| AnnaBridge | 163:e59c8e839560 | 7963 | #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33 |
| AnnaBridge | 163:e59c8e839560 | 7964 | #if defined(EXTI_SWIER2_SWIER34) |
| AnnaBridge | 163:e59c8e839560 | 7965 | #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34 |
| AnnaBridge | 163:e59c8e839560 | 7966 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7967 | #if defined(EXTI_SWIER2_SWIER35) |
| AnnaBridge | 163:e59c8e839560 | 7968 | #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35 |
| AnnaBridge | 163:e59c8e839560 | 7969 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7970 | |
| AnnaBridge | 163:e59c8e839560 | 7971 | /******************* Bit definition for EXTI_PR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 7972 | #define EXTI_PR2_PR32_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7973 | #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 7974 | #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */ |
| AnnaBridge | 163:e59c8e839560 | 7975 | #define EXTI_PR2_PR33_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 7976 | #define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 7977 | #define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */ |
| AnnaBridge | 163:e59c8e839560 | 7978 | |
| AnnaBridge | 163:e59c8e839560 | 7979 | /* References Defines */ |
| AnnaBridge | 163:e59c8e839560 | 7980 | #define EXTI_PR2_PIF32 EXTI_PR2_PR32 |
| AnnaBridge | 163:e59c8e839560 | 7981 | #define EXTI_PR2_PIF33 EXTI_PR2_PR33 |
| AnnaBridge | 163:e59c8e839560 | 7982 | #if defined(EXTI_PR2_PR34) |
| AnnaBridge | 163:e59c8e839560 | 7983 | #define EXTI_PR2_PIF34 EXTI_PR2_PR34 |
| AnnaBridge | 163:e59c8e839560 | 7984 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7985 | #if defined(EXTI_PR2_PR35) |
| AnnaBridge | 163:e59c8e839560 | 7986 | #define EXTI_PR2_PIF35 EXTI_PR2_PR35 |
| AnnaBridge | 163:e59c8e839560 | 7987 | #endif |
| AnnaBridge | 163:e59c8e839560 | 7988 | |
| AnnaBridge | 163:e59c8e839560 | 7989 | |
| AnnaBridge | 163:e59c8e839560 | 7990 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 7991 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 7992 | /* FLASH */ |
| AnnaBridge | 163:e59c8e839560 | 7993 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 7994 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 7995 | /******************* Bit definition for FLASH_ACR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 7996 | #define FLASH_ACR_LATENCY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 7997 | #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 7998 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ |
| AnnaBridge | 163:e59c8e839560 | 7999 | #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8000 | #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8001 | #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8002 | |
| AnnaBridge | 163:e59c8e839560 | 8003 | #define FLASH_ACR_HLFCYA_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8004 | #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8005 | #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ |
| AnnaBridge | 163:e59c8e839560 | 8006 | #define FLASH_ACR_PRFTBE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8007 | #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8008 | #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ |
| AnnaBridge | 163:e59c8e839560 | 8009 | #define FLASH_ACR_PRFTBS_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8010 | #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8011 | #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ |
| AnnaBridge | 163:e59c8e839560 | 8012 | |
| AnnaBridge | 163:e59c8e839560 | 8013 | /****************** Bit definition for FLASH_KEYR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8014 | #define FLASH_KEYR_FKEYR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8015 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 8016 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
| AnnaBridge | 163:e59c8e839560 | 8017 | |
| AnnaBridge | 163:e59c8e839560 | 8018 | #define RDP_KEY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8019 | #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */ |
| AnnaBridge | 163:e59c8e839560 | 8020 | #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ |
| AnnaBridge | 163:e59c8e839560 | 8021 | #define FLASH_KEY1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8022 | #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
| AnnaBridge | 163:e59c8e839560 | 8023 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ |
| AnnaBridge | 163:e59c8e839560 | 8024 | #define FLASH_KEY2_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8025 | #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
| AnnaBridge | 163:e59c8e839560 | 8026 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ |
| AnnaBridge | 163:e59c8e839560 | 8027 | |
| AnnaBridge | 163:e59c8e839560 | 8028 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 8029 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8030 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 8031 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
| AnnaBridge | 163:e59c8e839560 | 8032 | |
| AnnaBridge | 163:e59c8e839560 | 8033 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
| AnnaBridge | 163:e59c8e839560 | 8034 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
| AnnaBridge | 163:e59c8e839560 | 8035 | |
| AnnaBridge | 163:e59c8e839560 | 8036 | /****************** Bit definition for FLASH_SR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8037 | #define FLASH_SR_BSY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8038 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8039 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
| AnnaBridge | 163:e59c8e839560 | 8040 | #define FLASH_SR_PGERR_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8041 | #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8042 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
| AnnaBridge | 163:e59c8e839560 | 8043 | #define FLASH_SR_WRPERR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8044 | #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8045 | #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */ |
| AnnaBridge | 163:e59c8e839560 | 8046 | #define FLASH_SR_EOP_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8047 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8048 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
| AnnaBridge | 163:e59c8e839560 | 8049 | |
| AnnaBridge | 163:e59c8e839560 | 8050 | /******************* Bit definition for FLASH_CR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8051 | #define FLASH_CR_PG_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8052 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8053 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
| AnnaBridge | 163:e59c8e839560 | 8054 | #define FLASH_CR_PER_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8055 | #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8056 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
| AnnaBridge | 163:e59c8e839560 | 8057 | #define FLASH_CR_MER_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8058 | #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8059 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
| AnnaBridge | 163:e59c8e839560 | 8060 | #define FLASH_CR_OPTPG_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8061 | #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8062 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
| AnnaBridge | 163:e59c8e839560 | 8063 | #define FLASH_CR_OPTER_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8064 | #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8065 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
| AnnaBridge | 163:e59c8e839560 | 8066 | #define FLASH_CR_STRT_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8067 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8068 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
| AnnaBridge | 163:e59c8e839560 | 8069 | #define FLASH_CR_LOCK_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 8070 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8071 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
| AnnaBridge | 163:e59c8e839560 | 8072 | #define FLASH_CR_OPTWRE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8073 | #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8074 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
| AnnaBridge | 163:e59c8e839560 | 8075 | #define FLASH_CR_ERRIE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8076 | #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8077 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 8078 | #define FLASH_CR_EOPIE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8079 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8080 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8081 | #define FLASH_CR_OBL_LAUNCH_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8082 | #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8083 | #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */ |
| AnnaBridge | 163:e59c8e839560 | 8084 | |
| AnnaBridge | 163:e59c8e839560 | 8085 | /******************* Bit definition for FLASH_AR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8086 | #define FLASH_AR_FAR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8087 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 8088 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
| AnnaBridge | 163:e59c8e839560 | 8089 | |
| AnnaBridge | 163:e59c8e839560 | 8090 | /****************** Bit definition for FLASH_OBR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8091 | #define FLASH_OBR_OPTERR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8092 | #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8093 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
| AnnaBridge | 163:e59c8e839560 | 8094 | #define FLASH_OBR_RDPRT_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8095 | #define FLASH_OBR_RDPRT_Msk (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 163:e59c8e839560 | 8096 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ |
| AnnaBridge | 163:e59c8e839560 | 8097 | #define FLASH_OBR_RDPRT_1 (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8098 | #define FLASH_OBR_RDPRT_2 (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 163:e59c8e839560 | 8099 | |
| AnnaBridge | 163:e59c8e839560 | 8100 | #define FLASH_OBR_USER_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8101 | #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ |
| AnnaBridge | 163:e59c8e839560 | 8102 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8103 | #define FLASH_OBR_IWDG_SW_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8104 | #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8105 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
| AnnaBridge | 163:e59c8e839560 | 8106 | #define FLASH_OBR_nRST_STOP_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8107 | #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8108 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 8109 | #define FLASH_OBR_nRST_STDBY_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8110 | #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8111 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
| AnnaBridge | 163:e59c8e839560 | 8112 | #define FLASH_OBR_nBOOT1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8113 | #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8114 | #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ |
| AnnaBridge | 163:e59c8e839560 | 8115 | #define FLASH_OBR_VDDA_MONITOR_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8116 | #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8117 | #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */ |
| AnnaBridge | 163:e59c8e839560 | 8118 | #define FLASH_OBR_SRAM_PE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8119 | #define FLASH_OBR_SRAM_PE_Msk (0x1U << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8120 | #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */ |
| AnnaBridge | 163:e59c8e839560 | 8121 | #define FLASH_OBR_DATA0_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8122 | #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8123 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
| AnnaBridge | 163:e59c8e839560 | 8124 | #define FLASH_OBR_DATA1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8125 | #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8126 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
| AnnaBridge | 163:e59c8e839560 | 8127 | |
| AnnaBridge | 163:e59c8e839560 | 8128 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 8129 | #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW |
| AnnaBridge | 163:e59c8e839560 | 8130 | |
| AnnaBridge | 163:e59c8e839560 | 8131 | /****************** Bit definition for FLASH_WRPR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8132 | #define FLASH_WRPR_WRP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8133 | #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 8134 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
| AnnaBridge | 163:e59c8e839560 | 8135 | |
| AnnaBridge | 163:e59c8e839560 | 8136 | /*----------------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 8137 | |
| AnnaBridge | 163:e59c8e839560 | 8138 | /****************** Bit definition for OB_RDP register **********************/ |
| AnnaBridge | 163:e59c8e839560 | 8139 | #define OB_RDP_RDP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8140 | #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8141 | #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ |
| AnnaBridge | 163:e59c8e839560 | 8142 | #define OB_RDP_nRDP_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8143 | #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 8144 | #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
| AnnaBridge | 163:e59c8e839560 | 8145 | |
| AnnaBridge | 163:e59c8e839560 | 8146 | /****************** Bit definition for OB_USER register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8147 | #define OB_USER_USER_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8148 | #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8149 | #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ |
| AnnaBridge | 163:e59c8e839560 | 8150 | #define OB_USER_nUSER_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8151 | #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8152 | #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ |
| AnnaBridge | 163:e59c8e839560 | 8153 | |
| AnnaBridge | 163:e59c8e839560 | 8154 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8155 | #define OB_WRP0_WRP0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8156 | #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8157 | #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8158 | #define OB_WRP0_nWRP0_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8159 | #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 8160 | #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8161 | |
| AnnaBridge | 163:e59c8e839560 | 8162 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8163 | #define OB_WRP1_WRP1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8164 | #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8165 | #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8166 | #define OB_WRP1_nWRP1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8167 | #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8168 | #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8169 | |
| AnnaBridge | 163:e59c8e839560 | 8170 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8171 | #define OB_WRP2_WRP2_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8172 | #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8173 | #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8174 | #define OB_WRP2_nWRP2_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8175 | #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 8176 | #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8177 | |
| AnnaBridge | 163:e59c8e839560 | 8178 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8179 | #define OB_WRP3_WRP3_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8180 | #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8181 | #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8182 | #define OB_WRP3_nWRP3_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8183 | #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8184 | #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8185 | |
| AnnaBridge | 163:e59c8e839560 | 8186 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8187 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8188 | /* General Purpose I/O (GPIO) */ |
| AnnaBridge | 163:e59c8e839560 | 8189 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8190 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8191 | /******************* Bit definition for GPIO_MODER register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 8192 | #define GPIO_MODER_MODER0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8193 | #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 8194 | #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8195 | #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8196 | #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8197 | #define GPIO_MODER_MODER1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8198 | #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 8199 | #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8200 | #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8201 | #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8202 | #define GPIO_MODER_MODER2_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8203 | #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 8204 | #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8205 | #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8206 | #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8207 | #define GPIO_MODER_MODER3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8208 | #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 8209 | #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8210 | #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8211 | #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8212 | #define GPIO_MODER_MODER4_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8213 | #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 8214 | #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8215 | #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8216 | #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8217 | #define GPIO_MODER_MODER5_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8218 | #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 8219 | #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8220 | #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8221 | #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8222 | #define GPIO_MODER_MODER6_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8223 | #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 8224 | #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8225 | #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8226 | #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8227 | #define GPIO_MODER_MODER7_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8228 | #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 8229 | #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8230 | #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8231 | #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8232 | #define GPIO_MODER_MODER8_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8233 | #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 8234 | #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk |
| AnnaBridge | 163:e59c8e839560 | 8235 | #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8236 | #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 8237 | #define GPIO_MODER_MODER9_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 8238 | #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8239 | #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk |
| AnnaBridge | 163:e59c8e839560 | 8240 | #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 8241 | #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 8242 | #define GPIO_MODER_MODER10_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8243 | #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 8244 | #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk |
| AnnaBridge | 163:e59c8e839560 | 8245 | #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 8246 | #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 8247 | #define GPIO_MODER_MODER11_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 8248 | #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8249 | #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk |
| AnnaBridge | 163:e59c8e839560 | 8250 | #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 8251 | #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 8252 | #define GPIO_MODER_MODER12_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8253 | #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8254 | #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk |
| AnnaBridge | 163:e59c8e839560 | 8255 | #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8256 | #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8257 | #define GPIO_MODER_MODER13_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 8258 | #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8259 | #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk |
| AnnaBridge | 163:e59c8e839560 | 8260 | #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8261 | #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8262 | #define GPIO_MODER_MODER14_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8263 | #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8264 | #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk |
| AnnaBridge | 163:e59c8e839560 | 8265 | #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8266 | #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8267 | #define GPIO_MODER_MODER15_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 8268 | #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8269 | #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk |
| AnnaBridge | 163:e59c8e839560 | 8270 | #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8271 | #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8272 | |
| AnnaBridge | 163:e59c8e839560 | 8273 | /****************** Bit definition for GPIO_OTYPER register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 8274 | #define GPIO_OTYPER_OT_0 (0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 8275 | #define GPIO_OTYPER_OT_1 (0x00000002U) |
| AnnaBridge | 163:e59c8e839560 | 8276 | #define GPIO_OTYPER_OT_2 (0x00000004U) |
| AnnaBridge | 163:e59c8e839560 | 8277 | #define GPIO_OTYPER_OT_3 (0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 8278 | #define GPIO_OTYPER_OT_4 (0x00000010U) |
| AnnaBridge | 163:e59c8e839560 | 8279 | #define GPIO_OTYPER_OT_5 (0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 8280 | #define GPIO_OTYPER_OT_6 (0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 8281 | #define GPIO_OTYPER_OT_7 (0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 8282 | #define GPIO_OTYPER_OT_8 (0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 8283 | #define GPIO_OTYPER_OT_9 (0x00000200U) |
| AnnaBridge | 163:e59c8e839560 | 8284 | #define GPIO_OTYPER_OT_10 (0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 8285 | #define GPIO_OTYPER_OT_11 (0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 8286 | #define GPIO_OTYPER_OT_12 (0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 8287 | #define GPIO_OTYPER_OT_13 (0x00002000U) |
| AnnaBridge | 163:e59c8e839560 | 8288 | #define GPIO_OTYPER_OT_14 (0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 8289 | #define GPIO_OTYPER_OT_15 (0x00008000U) |
| AnnaBridge | 163:e59c8e839560 | 8290 | |
| AnnaBridge | 163:e59c8e839560 | 8291 | /**************** Bit definition for GPIO_OSPEEDR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8292 | #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8293 | #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 8294 | #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8295 | #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8296 | #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8297 | #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8298 | #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 8299 | #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8300 | #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8301 | #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8302 | #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8303 | #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 8304 | #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8305 | #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8306 | #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8307 | #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8308 | #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 8309 | #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8310 | #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8311 | #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8312 | #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8313 | #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 8314 | #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8315 | #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8316 | #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8317 | #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8318 | #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 8319 | #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8320 | #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8321 | #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8322 | #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8323 | #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 8324 | #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8325 | #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8326 | #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8327 | #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8328 | #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 8329 | #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8330 | #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8331 | #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8332 | #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8333 | #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 8334 | #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk |
| AnnaBridge | 163:e59c8e839560 | 8335 | #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8336 | #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 8337 | #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 8338 | #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8339 | #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk |
| AnnaBridge | 163:e59c8e839560 | 8340 | #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 8341 | #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 8342 | #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8343 | #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 8344 | #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk |
| AnnaBridge | 163:e59c8e839560 | 8345 | #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 8346 | #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 8347 | #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 8348 | #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8349 | #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk |
| AnnaBridge | 163:e59c8e839560 | 8350 | #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 8351 | #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 8352 | #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8353 | #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8354 | #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk |
| AnnaBridge | 163:e59c8e839560 | 8355 | #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8356 | #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8357 | #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 8358 | #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8359 | #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk |
| AnnaBridge | 163:e59c8e839560 | 8360 | #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8361 | #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8362 | #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8363 | #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8364 | #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk |
| AnnaBridge | 163:e59c8e839560 | 8365 | #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8366 | #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8367 | #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 8368 | #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8369 | #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk |
| AnnaBridge | 163:e59c8e839560 | 8370 | #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8371 | #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8372 | |
| AnnaBridge | 163:e59c8e839560 | 8373 | /******************* Bit definition for GPIO_PUPDR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8374 | #define GPIO_PUPDR_PUPDR0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8375 | #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 8376 | #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8377 | #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8378 | #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8379 | #define GPIO_PUPDR_PUPDR1_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8380 | #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 8381 | #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8382 | #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8383 | #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8384 | #define GPIO_PUPDR_PUPDR2_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8385 | #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 8386 | #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8387 | #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8388 | #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8389 | #define GPIO_PUPDR_PUPDR3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8390 | #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 163:e59c8e839560 | 8391 | #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8392 | #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8393 | #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8394 | #define GPIO_PUPDR_PUPDR4_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8395 | #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 8396 | #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8397 | #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8398 | #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8399 | #define GPIO_PUPDR_PUPDR5_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8400 | #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 8401 | #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8402 | #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8403 | #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8404 | #define GPIO_PUPDR_PUPDR6_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8405 | #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 8406 | #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8407 | #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8408 | #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8409 | #define GPIO_PUPDR_PUPDR7_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8410 | #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 163:e59c8e839560 | 8411 | #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8412 | #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8413 | #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8414 | #define GPIO_PUPDR_PUPDR8_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8415 | #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 8416 | #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk |
| AnnaBridge | 163:e59c8e839560 | 8417 | #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8418 | #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 8419 | #define GPIO_PUPDR_PUPDR9_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 8420 | #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8421 | #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk |
| AnnaBridge | 163:e59c8e839560 | 8422 | #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 8423 | #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 8424 | #define GPIO_PUPDR_PUPDR10_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8425 | #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 8426 | #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk |
| AnnaBridge | 163:e59c8e839560 | 8427 | #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 8428 | #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 8429 | #define GPIO_PUPDR_PUPDR11_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 8430 | #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8431 | #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk |
| AnnaBridge | 163:e59c8e839560 | 8432 | #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 8433 | #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 8434 | #define GPIO_PUPDR_PUPDR12_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8435 | #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8436 | #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk |
| AnnaBridge | 163:e59c8e839560 | 8437 | #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8438 | #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8439 | #define GPIO_PUPDR_PUPDR13_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 8440 | #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8441 | #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk |
| AnnaBridge | 163:e59c8e839560 | 8442 | #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8443 | #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8444 | #define GPIO_PUPDR_PUPDR14_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8445 | #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8446 | #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk |
| AnnaBridge | 163:e59c8e839560 | 8447 | #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8448 | #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8449 | #define GPIO_PUPDR_PUPDR15_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 8450 | #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8451 | #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk |
| AnnaBridge | 163:e59c8e839560 | 8452 | #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8453 | #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8454 | |
| AnnaBridge | 163:e59c8e839560 | 8455 | /******************* Bit definition for GPIO_IDR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8456 | #define GPIO_IDR_0 (0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 8457 | #define GPIO_IDR_1 (0x00000002U) |
| AnnaBridge | 163:e59c8e839560 | 8458 | #define GPIO_IDR_2 (0x00000004U) |
| AnnaBridge | 163:e59c8e839560 | 8459 | #define GPIO_IDR_3 (0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 8460 | #define GPIO_IDR_4 (0x00000010U) |
| AnnaBridge | 163:e59c8e839560 | 8461 | #define GPIO_IDR_5 (0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 8462 | #define GPIO_IDR_6 (0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 8463 | #define GPIO_IDR_7 (0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 8464 | #define GPIO_IDR_8 (0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 8465 | #define GPIO_IDR_9 (0x00000200U) |
| AnnaBridge | 163:e59c8e839560 | 8466 | #define GPIO_IDR_10 (0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 8467 | #define GPIO_IDR_11 (0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 8468 | #define GPIO_IDR_12 (0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 8469 | #define GPIO_IDR_13 (0x00002000U) |
| AnnaBridge | 163:e59c8e839560 | 8470 | #define GPIO_IDR_14 (0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 8471 | #define GPIO_IDR_15 (0x00008000U) |
| AnnaBridge | 163:e59c8e839560 | 8472 | |
| AnnaBridge | 163:e59c8e839560 | 8473 | /****************** Bit definition for GPIO_ODR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8474 | #define GPIO_ODR_0 (0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 8475 | #define GPIO_ODR_1 (0x00000002U) |
| AnnaBridge | 163:e59c8e839560 | 8476 | #define GPIO_ODR_2 (0x00000004U) |
| AnnaBridge | 163:e59c8e839560 | 8477 | #define GPIO_ODR_3 (0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 8478 | #define GPIO_ODR_4 (0x00000010U) |
| AnnaBridge | 163:e59c8e839560 | 8479 | #define GPIO_ODR_5 (0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 8480 | #define GPIO_ODR_6 (0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 8481 | #define GPIO_ODR_7 (0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 8482 | #define GPIO_ODR_8 (0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 8483 | #define GPIO_ODR_9 (0x00000200U) |
| AnnaBridge | 163:e59c8e839560 | 8484 | #define GPIO_ODR_10 (0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 8485 | #define GPIO_ODR_11 (0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 8486 | #define GPIO_ODR_12 (0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 8487 | #define GPIO_ODR_13 (0x00002000U) |
| AnnaBridge | 163:e59c8e839560 | 8488 | #define GPIO_ODR_14 (0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 8489 | #define GPIO_ODR_15 (0x00008000U) |
| AnnaBridge | 163:e59c8e839560 | 8490 | |
| AnnaBridge | 163:e59c8e839560 | 8491 | /****************** Bit definition for GPIO_BSRR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8492 | #define GPIO_BSRR_BS_0 (0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 8493 | #define GPIO_BSRR_BS_1 (0x00000002U) |
| AnnaBridge | 163:e59c8e839560 | 8494 | #define GPIO_BSRR_BS_2 (0x00000004U) |
| AnnaBridge | 163:e59c8e839560 | 8495 | #define GPIO_BSRR_BS_3 (0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 8496 | #define GPIO_BSRR_BS_4 (0x00000010U) |
| AnnaBridge | 163:e59c8e839560 | 8497 | #define GPIO_BSRR_BS_5 (0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 8498 | #define GPIO_BSRR_BS_6 (0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 8499 | #define GPIO_BSRR_BS_7 (0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 8500 | #define GPIO_BSRR_BS_8 (0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 8501 | #define GPIO_BSRR_BS_9 (0x00000200U) |
| AnnaBridge | 163:e59c8e839560 | 8502 | #define GPIO_BSRR_BS_10 (0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 8503 | #define GPIO_BSRR_BS_11 (0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 8504 | #define GPIO_BSRR_BS_12 (0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 8505 | #define GPIO_BSRR_BS_13 (0x00002000U) |
| AnnaBridge | 163:e59c8e839560 | 8506 | #define GPIO_BSRR_BS_14 (0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 8507 | #define GPIO_BSRR_BS_15 (0x00008000U) |
| AnnaBridge | 163:e59c8e839560 | 8508 | #define GPIO_BSRR_BR_0 (0x00010000U) |
| AnnaBridge | 163:e59c8e839560 | 8509 | #define GPIO_BSRR_BR_1 (0x00020000U) |
| AnnaBridge | 163:e59c8e839560 | 8510 | #define GPIO_BSRR_BR_2 (0x00040000U) |
| AnnaBridge | 163:e59c8e839560 | 8511 | #define GPIO_BSRR_BR_3 (0x00080000U) |
| AnnaBridge | 163:e59c8e839560 | 8512 | #define GPIO_BSRR_BR_4 (0x00100000U) |
| AnnaBridge | 163:e59c8e839560 | 8513 | #define GPIO_BSRR_BR_5 (0x00200000U) |
| AnnaBridge | 163:e59c8e839560 | 8514 | #define GPIO_BSRR_BR_6 (0x00400000U) |
| AnnaBridge | 163:e59c8e839560 | 8515 | #define GPIO_BSRR_BR_7 (0x00800000U) |
| AnnaBridge | 163:e59c8e839560 | 8516 | #define GPIO_BSRR_BR_8 (0x01000000U) |
| AnnaBridge | 163:e59c8e839560 | 8517 | #define GPIO_BSRR_BR_9 (0x02000000U) |
| AnnaBridge | 163:e59c8e839560 | 8518 | #define GPIO_BSRR_BR_10 (0x04000000U) |
| AnnaBridge | 163:e59c8e839560 | 8519 | #define GPIO_BSRR_BR_11 (0x08000000U) |
| AnnaBridge | 163:e59c8e839560 | 8520 | #define GPIO_BSRR_BR_12 (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 8521 | #define GPIO_BSRR_BR_13 (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 8522 | #define GPIO_BSRR_BR_14 (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 8523 | #define GPIO_BSRR_BR_15 (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 8524 | |
| AnnaBridge | 163:e59c8e839560 | 8525 | /****************** Bit definition for GPIO_LCKR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8526 | #define GPIO_LCKR_LCK0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8527 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8528 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8529 | #define GPIO_LCKR_LCK1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8530 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8531 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8532 | #define GPIO_LCKR_LCK2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8533 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8534 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8535 | #define GPIO_LCKR_LCK3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8536 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8537 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8538 | #define GPIO_LCKR_LCK4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8539 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8540 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8541 | #define GPIO_LCKR_LCK5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8542 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8543 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8544 | #define GPIO_LCKR_LCK6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8545 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8546 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8547 | #define GPIO_LCKR_LCK7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 8548 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8549 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8550 | #define GPIO_LCKR_LCK8_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8551 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8552 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| AnnaBridge | 163:e59c8e839560 | 8553 | #define GPIO_LCKR_LCK9_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8554 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8555 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| AnnaBridge | 163:e59c8e839560 | 8556 | #define GPIO_LCKR_LCK10_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8557 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8558 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| AnnaBridge | 163:e59c8e839560 | 8559 | #define GPIO_LCKR_LCK11_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 8560 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8561 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| AnnaBridge | 163:e59c8e839560 | 8562 | #define GPIO_LCKR_LCK12_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8563 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8564 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| AnnaBridge | 163:e59c8e839560 | 8565 | #define GPIO_LCKR_LCK13_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8566 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8567 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| AnnaBridge | 163:e59c8e839560 | 8568 | #define GPIO_LCKR_LCK14_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8569 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8570 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| AnnaBridge | 163:e59c8e839560 | 8571 | #define GPIO_LCKR_LCK15_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8572 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8573 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| AnnaBridge | 163:e59c8e839560 | 8574 | #define GPIO_LCKR_LCKK_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8575 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8576 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| AnnaBridge | 163:e59c8e839560 | 8577 | |
| AnnaBridge | 163:e59c8e839560 | 8578 | /****************** Bit definition for GPIO_AFRL register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8579 | #define GPIO_AFRL_AFRL0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8580 | #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 8581 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8582 | #define GPIO_AFRL_AFRL1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8583 | #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 8584 | #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8585 | #define GPIO_AFRL_AFRL2_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8586 | #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 8587 | #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8588 | #define GPIO_AFRL_AFRL3_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8589 | #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 8590 | #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8591 | #define GPIO_AFRL_AFRL4_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8592 | #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8593 | #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8594 | #define GPIO_AFRL_AFRL5_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8595 | #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8596 | #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8597 | #define GPIO_AFRL_AFRL6_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8598 | #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8599 | #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8600 | #define GPIO_AFRL_AFRL7_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8601 | #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8602 | #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8603 | |
| AnnaBridge | 163:e59c8e839560 | 8604 | /****************** Bit definition for GPIO_AFRH register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8605 | #define GPIO_AFRH_AFRH0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8606 | #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 8607 | #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk |
| AnnaBridge | 163:e59c8e839560 | 8608 | #define GPIO_AFRH_AFRH1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8609 | #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 8610 | #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk |
| AnnaBridge | 163:e59c8e839560 | 8611 | #define GPIO_AFRH_AFRH2_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8612 | #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 8613 | #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk |
| AnnaBridge | 163:e59c8e839560 | 8614 | #define GPIO_AFRH_AFRH3_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8615 | #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 8616 | #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk |
| AnnaBridge | 163:e59c8e839560 | 8617 | #define GPIO_AFRH_AFRH4_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8618 | #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8619 | #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk |
| AnnaBridge | 163:e59c8e839560 | 8620 | #define GPIO_AFRH_AFRH5_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8621 | #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8622 | #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk |
| AnnaBridge | 163:e59c8e839560 | 8623 | #define GPIO_AFRH_AFRH6_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8624 | #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8625 | #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk |
| AnnaBridge | 163:e59c8e839560 | 8626 | #define GPIO_AFRH_AFRH7_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8627 | #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8628 | #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk |
| AnnaBridge | 163:e59c8e839560 | 8629 | |
| AnnaBridge | 163:e59c8e839560 | 8630 | /****************** Bit definition for GPIO_BRR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8631 | #define GPIO_BRR_BR_0 (0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 8632 | #define GPIO_BRR_BR_1 (0x00000002U) |
| AnnaBridge | 163:e59c8e839560 | 8633 | #define GPIO_BRR_BR_2 (0x00000004U) |
| AnnaBridge | 163:e59c8e839560 | 8634 | #define GPIO_BRR_BR_3 (0x00000008U) |
| AnnaBridge | 163:e59c8e839560 | 8635 | #define GPIO_BRR_BR_4 (0x00000010U) |
| AnnaBridge | 163:e59c8e839560 | 8636 | #define GPIO_BRR_BR_5 (0x00000020U) |
| AnnaBridge | 163:e59c8e839560 | 8637 | #define GPIO_BRR_BR_6 (0x00000040U) |
| AnnaBridge | 163:e59c8e839560 | 8638 | #define GPIO_BRR_BR_7 (0x00000080U) |
| AnnaBridge | 163:e59c8e839560 | 8639 | #define GPIO_BRR_BR_8 (0x00000100U) |
| AnnaBridge | 163:e59c8e839560 | 8640 | #define GPIO_BRR_BR_9 (0x00000200U) |
| AnnaBridge | 163:e59c8e839560 | 8641 | #define GPIO_BRR_BR_10 (0x00000400U) |
| AnnaBridge | 163:e59c8e839560 | 8642 | #define GPIO_BRR_BR_11 (0x00000800U) |
| AnnaBridge | 163:e59c8e839560 | 8643 | #define GPIO_BRR_BR_12 (0x00001000U) |
| AnnaBridge | 163:e59c8e839560 | 8644 | #define GPIO_BRR_BR_13 (0x00002000U) |
| AnnaBridge | 163:e59c8e839560 | 8645 | #define GPIO_BRR_BR_14 (0x00004000U) |
| AnnaBridge | 163:e59c8e839560 | 8646 | #define GPIO_BRR_BR_15 (0x00008000U) |
| AnnaBridge | 163:e59c8e839560 | 8647 | |
| AnnaBridge | 163:e59c8e839560 | 8648 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8649 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8650 | /* Inter-integrated Circuit Interface (I2C) */ |
| AnnaBridge | 163:e59c8e839560 | 8651 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8652 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8653 | /******************* Bit definition for I2C_CR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8654 | #define I2C_CR1_PE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8655 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8656 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ |
| AnnaBridge | 163:e59c8e839560 | 8657 | #define I2C_CR1_TXIE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8658 | #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8659 | #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8660 | #define I2C_CR1_RXIE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8661 | #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8662 | #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8663 | #define I2C_CR1_ADDRIE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8664 | #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8665 | #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8666 | #define I2C_CR1_NACKIE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8667 | #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8668 | #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8669 | #define I2C_CR1_STOPIE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8670 | #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8671 | #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8672 | #define I2C_CR1_TCIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8673 | #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8674 | #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8675 | #define I2C_CR1_ERRIE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 8676 | #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8677 | #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 8678 | #define I2C_CR1_DNF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8679 | #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 8680 | #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ |
| AnnaBridge | 163:e59c8e839560 | 8681 | #define I2C_CR1_ANFOFF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8682 | #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8683 | #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ |
| AnnaBridge | 163:e59c8e839560 | 8684 | #define I2C_CR1_SWRST_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8685 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8686 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ |
| AnnaBridge | 163:e59c8e839560 | 8687 | #define I2C_CR1_TXDMAEN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8688 | #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8689 | #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ |
| AnnaBridge | 163:e59c8e839560 | 8690 | #define I2C_CR1_RXDMAEN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8691 | #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8692 | #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ |
| AnnaBridge | 163:e59c8e839560 | 8693 | #define I2C_CR1_SBC_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8694 | #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8695 | #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ |
| AnnaBridge | 163:e59c8e839560 | 8696 | #define I2C_CR1_NOSTRETCH_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 8697 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 8698 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ |
| AnnaBridge | 163:e59c8e839560 | 8699 | #define I2C_CR1_WUPEN_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 8700 | #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 8701 | #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ |
| AnnaBridge | 163:e59c8e839560 | 8702 | #define I2C_CR1_GCEN_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 8703 | #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 8704 | #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ |
| AnnaBridge | 163:e59c8e839560 | 8705 | #define I2C_CR1_SMBHEN_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8706 | #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 8707 | #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ |
| AnnaBridge | 163:e59c8e839560 | 8708 | #define I2C_CR1_SMBDEN_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 8709 | #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 8710 | #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ |
| AnnaBridge | 163:e59c8e839560 | 8711 | #define I2C_CR1_ALERTEN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 8712 | #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 8713 | #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ |
| AnnaBridge | 163:e59c8e839560 | 8714 | #define I2C_CR1_PECEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 8715 | #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 8716 | #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ |
| AnnaBridge | 163:e59c8e839560 | 8717 | |
| AnnaBridge | 163:e59c8e839560 | 8718 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 8719 | #define I2C_CR1_DFN I2C_CR1_DNF |
| AnnaBridge | 163:e59c8e839560 | 8720 | |
| AnnaBridge | 163:e59c8e839560 | 8721 | /****************** Bit definition for I2C_CR2 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8722 | #define I2C_CR2_SADD_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8723 | #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 163:e59c8e839560 | 8724 | #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8725 | #define I2C_CR2_RD_WRN_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8726 | #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8727 | #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8728 | #define I2C_CR2_ADD10_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 8729 | #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8730 | #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8731 | #define I2C_CR2_HEAD10R_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8732 | #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8733 | #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8734 | #define I2C_CR2_START_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8735 | #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8736 | #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ |
| AnnaBridge | 163:e59c8e839560 | 8737 | #define I2C_CR2_STOP_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 8738 | #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 8739 | #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8740 | #define I2C_CR2_NACK_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8741 | #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8742 | #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8743 | #define I2C_CR2_NBYTES_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8744 | #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8745 | #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ |
| AnnaBridge | 163:e59c8e839560 | 8746 | #define I2C_CR2_RELOAD_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 8747 | #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8748 | #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ |
| AnnaBridge | 163:e59c8e839560 | 8749 | #define I2C_CR2_AUTOEND_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 8750 | #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8751 | #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8752 | #define I2C_CR2_PECBYTE_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 8753 | #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8754 | #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ |
| AnnaBridge | 163:e59c8e839560 | 8755 | |
| AnnaBridge | 163:e59c8e839560 | 8756 | /******************* Bit definition for I2C_OAR1 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 8757 | #define I2C_OAR1_OA1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8758 | #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 163:e59c8e839560 | 8759 | #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ |
| AnnaBridge | 163:e59c8e839560 | 8760 | #define I2C_OAR1_OA1MODE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8761 | #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8762 | #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ |
| AnnaBridge | 163:e59c8e839560 | 8763 | #define I2C_OAR1_OA1EN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8764 | #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8765 | #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 8766 | |
| AnnaBridge | 163:e59c8e839560 | 8767 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8768 | #define I2C_OAR2_OA2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8769 | #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ |
| AnnaBridge | 163:e59c8e839560 | 8770 | #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ |
| AnnaBridge | 163:e59c8e839560 | 8771 | #define I2C_OAR2_OA2MSK_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8772 | #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 163:e59c8e839560 | 8773 | #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ |
| AnnaBridge | 163:e59c8e839560 | 8774 | #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ |
| AnnaBridge | 163:e59c8e839560 | 8775 | #define I2C_OAR2_OA2MASK01_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8776 | #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8777 | #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8778 | #define I2C_OAR2_OA2MASK02_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8779 | #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8780 | #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8781 | #define I2C_OAR2_OA2MASK03_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8782 | #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 8783 | #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8784 | #define I2C_OAR2_OA2MASK04_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8785 | #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8786 | #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8787 | #define I2C_OAR2_OA2MASK05_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8788 | #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ |
| AnnaBridge | 163:e59c8e839560 | 8789 | #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8790 | #define I2C_OAR2_OA2MASK06_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8791 | #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 8792 | #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ |
| AnnaBridge | 163:e59c8e839560 | 8793 | #define I2C_OAR2_OA2MASK07_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8794 | #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 163:e59c8e839560 | 8795 | #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ |
| AnnaBridge | 163:e59c8e839560 | 8796 | #define I2C_OAR2_OA2EN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8797 | #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8798 | #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 8799 | |
| AnnaBridge | 163:e59c8e839560 | 8800 | /******************* Bit definition for I2C_TIMINGR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 8801 | #define I2C_TIMINGR_SCLL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8802 | #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8803 | #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8804 | #define I2C_TIMINGR_SCLH_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8805 | #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 8806 | #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8807 | #define I2C_TIMINGR_SDADEL_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8808 | #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8809 | #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ |
| AnnaBridge | 163:e59c8e839560 | 8810 | #define I2C_TIMINGR_SCLDEL_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 8811 | #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 8812 | #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ |
| AnnaBridge | 163:e59c8e839560 | 8813 | #define I2C_TIMINGR_PRESC_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 8814 | #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8815 | #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 8816 | |
| AnnaBridge | 163:e59c8e839560 | 8817 | /******************* Bit definition for I2C_TIMEOUTR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 8818 | #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8819 | #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 8820 | #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ |
| AnnaBridge | 163:e59c8e839560 | 8821 | #define I2C_TIMEOUTR_TIDLE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8822 | #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8823 | #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ |
| AnnaBridge | 163:e59c8e839560 | 8824 | #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8825 | #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8826 | #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ |
| AnnaBridge | 163:e59c8e839560 | 8827 | #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8828 | #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8829 | #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ |
| AnnaBridge | 163:e59c8e839560 | 8830 | #define I2C_TIMEOUTR_TEXTEN_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 8831 | #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 8832 | #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ |
| AnnaBridge | 163:e59c8e839560 | 8833 | |
| AnnaBridge | 163:e59c8e839560 | 8834 | /****************** Bit definition for I2C_ISR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8835 | #define I2C_ISR_TXE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8836 | #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8837 | #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ |
| AnnaBridge | 163:e59c8e839560 | 8838 | #define I2C_ISR_TXIS_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8839 | #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8840 | #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ |
| AnnaBridge | 163:e59c8e839560 | 8841 | #define I2C_ISR_RXNE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8842 | #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8843 | #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ |
| AnnaBridge | 163:e59c8e839560 | 8844 | #define I2C_ISR_ADDR_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8845 | #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8846 | #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ |
| AnnaBridge | 163:e59c8e839560 | 8847 | #define I2C_ISR_NACKF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8848 | #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8849 | #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ |
| AnnaBridge | 163:e59c8e839560 | 8850 | #define I2C_ISR_STOPF_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8851 | #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8852 | #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ |
| AnnaBridge | 163:e59c8e839560 | 8853 | #define I2C_ISR_TC_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 8854 | #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8855 | #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8856 | #define I2C_ISR_TCR_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 8857 | #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 8858 | #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ |
| AnnaBridge | 163:e59c8e839560 | 8859 | #define I2C_ISR_BERR_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8860 | #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8861 | #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ |
| AnnaBridge | 163:e59c8e839560 | 8862 | #define I2C_ISR_ARLO_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8863 | #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8864 | #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ |
| AnnaBridge | 163:e59c8e839560 | 8865 | #define I2C_ISR_OVR_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8866 | #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8867 | #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ |
| AnnaBridge | 163:e59c8e839560 | 8868 | #define I2C_ISR_PECERR_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 8869 | #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8870 | #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ |
| AnnaBridge | 163:e59c8e839560 | 8871 | #define I2C_ISR_TIMEOUT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8872 | #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8873 | #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ |
| AnnaBridge | 163:e59c8e839560 | 8874 | #define I2C_ISR_ALERT_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8875 | #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8876 | #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ |
| AnnaBridge | 163:e59c8e839560 | 8877 | #define I2C_ISR_BUSY_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 8878 | #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 8879 | #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ |
| AnnaBridge | 163:e59c8e839560 | 8880 | #define I2C_ISR_DIR_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 8881 | #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 8882 | #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8883 | #define I2C_ISR_ADDCODE_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 8884 | #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ |
| AnnaBridge | 163:e59c8e839560 | 8885 | #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ |
| AnnaBridge | 163:e59c8e839560 | 8886 | |
| AnnaBridge | 163:e59c8e839560 | 8887 | /****************** Bit definition for I2C_ICR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8888 | #define I2C_ICR_ADDRCF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8889 | #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8890 | #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8891 | #define I2C_ICR_NACKCF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8892 | #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8893 | #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8894 | #define I2C_ICR_STOPCF_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8895 | #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8896 | #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8897 | #define I2C_ICR_BERRCF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 8898 | #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 8899 | #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8900 | #define I2C_ICR_ARLOCF_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 8901 | #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 8902 | #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8903 | #define I2C_ICR_OVRCF_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 8904 | #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 8905 | #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8906 | #define I2C_ICR_PECCF_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 8907 | #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 8908 | #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8909 | #define I2C_ICR_TIMOUTCF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 8910 | #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 8911 | #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8912 | #define I2C_ICR_ALERTCF_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 8913 | #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 8914 | #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ |
| AnnaBridge | 163:e59c8e839560 | 8915 | |
| AnnaBridge | 163:e59c8e839560 | 8916 | /****************** Bit definition for I2C_PECR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8917 | #define I2C_PECR_PEC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8918 | #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8919 | #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ |
| AnnaBridge | 163:e59c8e839560 | 8920 | |
| AnnaBridge | 163:e59c8e839560 | 8921 | /****************** Bit definition for I2C_RXDR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8922 | #define I2C_RXDR_RXDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8923 | #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8924 | #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ |
| AnnaBridge | 163:e59c8e839560 | 8925 | |
| AnnaBridge | 163:e59c8e839560 | 8926 | /****************** Bit definition for I2C_TXDR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 8927 | #define I2C_TXDR_TXDATA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8928 | #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 8929 | #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ |
| AnnaBridge | 163:e59c8e839560 | 8930 | |
| AnnaBridge | 163:e59c8e839560 | 8931 | |
| AnnaBridge | 163:e59c8e839560 | 8932 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8933 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8934 | /* Independent WATCHDOG (IWDG) */ |
| AnnaBridge | 163:e59c8e839560 | 8935 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8936 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8937 | /******************* Bit definition for IWDG_KR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8938 | #define IWDG_KR_KEY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8939 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 8940 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
| AnnaBridge | 163:e59c8e839560 | 8941 | |
| AnnaBridge | 163:e59c8e839560 | 8942 | /******************* Bit definition for IWDG_PR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8943 | #define IWDG_PR_PR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8944 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 8945 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
| AnnaBridge | 163:e59c8e839560 | 8946 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8947 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8948 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8949 | |
| AnnaBridge | 163:e59c8e839560 | 8950 | /******************* Bit definition for IWDG_RLR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 8951 | #define IWDG_RLR_RL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8952 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 8953 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
| AnnaBridge | 163:e59c8e839560 | 8954 | |
| AnnaBridge | 163:e59c8e839560 | 8955 | /******************* Bit definition for IWDG_SR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8956 | #define IWDG_SR_PVU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8957 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8958 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
| AnnaBridge | 163:e59c8e839560 | 8959 | #define IWDG_SR_RVU_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8960 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8961 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
| AnnaBridge | 163:e59c8e839560 | 8962 | #define IWDG_SR_WVU_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8963 | #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8964 | #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ |
| AnnaBridge | 163:e59c8e839560 | 8965 | |
| AnnaBridge | 163:e59c8e839560 | 8966 | /******************* Bit definition for IWDG_KR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8967 | #define IWDG_WINR_WIN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8968 | #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 163:e59c8e839560 | 8969 | #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ |
| AnnaBridge | 163:e59c8e839560 | 8970 | |
| AnnaBridge | 163:e59c8e839560 | 8971 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8972 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8973 | /* Power Control */ |
| AnnaBridge | 163:e59c8e839560 | 8974 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 8975 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 8976 | #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ |
| AnnaBridge | 163:e59c8e839560 | 8977 | /******************** Bit definition for PWR_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 8978 | #define PWR_CR_LPDS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 8979 | #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 8980 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ |
| AnnaBridge | 163:e59c8e839560 | 8981 | #define PWR_CR_PDDS_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 8982 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 8983 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
| AnnaBridge | 163:e59c8e839560 | 8984 | #define PWR_CR_CWUF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 8985 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 8986 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
| AnnaBridge | 163:e59c8e839560 | 8987 | #define PWR_CR_CSBF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 8988 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 8989 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
| AnnaBridge | 163:e59c8e839560 | 8990 | #define PWR_CR_PVDE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 8991 | #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 8992 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
| AnnaBridge | 163:e59c8e839560 | 8993 | |
| AnnaBridge | 163:e59c8e839560 | 8994 | #define PWR_CR_PLS_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 8995 | #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 163:e59c8e839560 | 8996 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 8997 | #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 8998 | #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 8999 | #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9000 | |
| AnnaBridge | 163:e59c8e839560 | 9001 | /*!< PVD level configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9002 | #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ |
| AnnaBridge | 163:e59c8e839560 | 9003 | #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ |
| AnnaBridge | 163:e59c8e839560 | 9004 | #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9005 | #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ |
| AnnaBridge | 163:e59c8e839560 | 9006 | #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9007 | #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ |
| AnnaBridge | 163:e59c8e839560 | 9008 | #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ |
| AnnaBridge | 163:e59c8e839560 | 9009 | #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ |
| AnnaBridge | 163:e59c8e839560 | 9010 | |
| AnnaBridge | 163:e59c8e839560 | 9011 | #define PWR_CR_DBP_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9012 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9013 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
| AnnaBridge | 163:e59c8e839560 | 9014 | |
| AnnaBridge | 163:e59c8e839560 | 9015 | /******************* Bit definition for PWR_CSR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 9016 | #define PWR_CSR_WUF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9017 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9018 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
| AnnaBridge | 163:e59c8e839560 | 9019 | #define PWR_CSR_SBF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9020 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9021 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
| AnnaBridge | 163:e59c8e839560 | 9022 | #define PWR_CSR_PVDO_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9023 | #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9024 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
| AnnaBridge | 163:e59c8e839560 | 9025 | #define PWR_CSR_VREFINTRDYF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 9026 | #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9027 | #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ |
| AnnaBridge | 163:e59c8e839560 | 9028 | |
| AnnaBridge | 163:e59c8e839560 | 9029 | #define PWR_CSR_EWUP1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9030 | #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9031 | #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ |
| AnnaBridge | 163:e59c8e839560 | 9032 | #define PWR_CSR_EWUP2_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9033 | #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9034 | #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9035 | #define PWR_CSR_EWUP3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 9036 | #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9037 | #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ |
| AnnaBridge | 163:e59c8e839560 | 9038 | |
| AnnaBridge | 163:e59c8e839560 | 9039 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 9040 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 9041 | /* Reset and Clock Control */ |
| AnnaBridge | 163:e59c8e839560 | 9042 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 9043 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 9044 | /******************** Bit definition for RCC_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 9045 | #define RCC_CR_HSION_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9046 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9047 | #define RCC_CR_HSION RCC_CR_HSION_Msk |
| AnnaBridge | 163:e59c8e839560 | 9048 | #define RCC_CR_HSIRDY_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9049 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9050 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk |
| AnnaBridge | 163:e59c8e839560 | 9051 | |
| AnnaBridge | 163:e59c8e839560 | 9052 | #define RCC_CR_HSITRIM_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 9053 | #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
| AnnaBridge | 163:e59c8e839560 | 9054 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk |
| AnnaBridge | 163:e59c8e839560 | 9055 | #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9056 | #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9057 | #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9058 | #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9059 | #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9060 | |
| AnnaBridge | 163:e59c8e839560 | 9061 | #define RCC_CR_HSICAL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9062 | #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 9063 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk |
| AnnaBridge | 163:e59c8e839560 | 9064 | #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9065 | #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9066 | #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9067 | #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9068 | #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9069 | #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9070 | #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9071 | #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9072 | |
| AnnaBridge | 163:e59c8e839560 | 9073 | #define RCC_CR_HSEON_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9074 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9075 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk |
| AnnaBridge | 163:e59c8e839560 | 9076 | #define RCC_CR_HSERDY_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9077 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9078 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk |
| AnnaBridge | 163:e59c8e839560 | 9079 | #define RCC_CR_HSEBYP_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9080 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9081 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk |
| AnnaBridge | 163:e59c8e839560 | 9082 | #define RCC_CR_CSSON_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9083 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9084 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk |
| AnnaBridge | 163:e59c8e839560 | 9085 | #define RCC_CR_PLLON_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 9086 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9087 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk |
| AnnaBridge | 163:e59c8e839560 | 9088 | #define RCC_CR_PLLRDY_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 9089 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9090 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk |
| AnnaBridge | 163:e59c8e839560 | 9091 | |
| AnnaBridge | 163:e59c8e839560 | 9092 | /******************** Bit definition for RCC_CFGR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9093 | /*!< SW configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9094 | #define RCC_CFGR_SW_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9095 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 9096 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
| AnnaBridge | 163:e59c8e839560 | 9097 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9098 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9099 | |
| AnnaBridge | 163:e59c8e839560 | 9100 | #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9101 | #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9102 | #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9103 | |
| AnnaBridge | 163:e59c8e839560 | 9104 | /*!< SWS configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9105 | #define RCC_CFGR_SWS_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9106 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 9107 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| AnnaBridge | 163:e59c8e839560 | 9108 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9109 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9110 | |
| AnnaBridge | 163:e59c8e839560 | 9111 | #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9112 | #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9113 | #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ |
| AnnaBridge | 163:e59c8e839560 | 9114 | |
| AnnaBridge | 163:e59c8e839560 | 9115 | /*!< HPRE configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9116 | #define RCC_CFGR_HPRE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9117 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 9118 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 9119 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9120 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9121 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9122 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9123 | |
| AnnaBridge | 163:e59c8e839560 | 9124 | #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ |
| AnnaBridge | 163:e59c8e839560 | 9125 | #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9126 | #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9127 | #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9128 | #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9129 | #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ |
| AnnaBridge | 163:e59c8e839560 | 9130 | #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ |
| AnnaBridge | 163:e59c8e839560 | 9131 | #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ |
| AnnaBridge | 163:e59c8e839560 | 9132 | #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ |
| AnnaBridge | 163:e59c8e839560 | 9133 | |
| AnnaBridge | 163:e59c8e839560 | 9134 | /*!< PPRE1 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9135 | #define RCC_CFGR_PPRE1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9136 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 163:e59c8e839560 | 9137 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 9138 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9139 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9140 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9141 | |
| AnnaBridge | 163:e59c8e839560 | 9142 | #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ |
| AnnaBridge | 163:e59c8e839560 | 9143 | #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9144 | #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9145 | #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9146 | #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9147 | |
| AnnaBridge | 163:e59c8e839560 | 9148 | /*!< PPRE2 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9149 | #define RCC_CFGR_PPRE2_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9150 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
| AnnaBridge | 163:e59c8e839560 | 9151 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 9152 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9153 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9154 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9155 | |
| AnnaBridge | 163:e59c8e839560 | 9156 | #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ |
| AnnaBridge | 163:e59c8e839560 | 9157 | #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9158 | #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9159 | #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9160 | #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9161 | |
| AnnaBridge | 163:e59c8e839560 | 9162 | #define RCC_CFGR_PLLSRC_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9163 | #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9164 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9165 | #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9166 | #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9167 | |
| AnnaBridge | 163:e59c8e839560 | 9168 | #define RCC_CFGR_PLLXTPRE_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9169 | #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9170 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ |
| AnnaBridge | 163:e59c8e839560 | 9171 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ |
| AnnaBridge | 163:e59c8e839560 | 9172 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ |
| AnnaBridge | 163:e59c8e839560 | 9173 | |
| AnnaBridge | 163:e59c8e839560 | 9174 | /*!< PLLMUL configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9175 | #define RCC_CFGR_PLLMUL_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9176 | #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 9177 | #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
| AnnaBridge | 163:e59c8e839560 | 9178 | #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9179 | #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9180 | #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9181 | #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9182 | |
| AnnaBridge | 163:e59c8e839560 | 9183 | #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ |
| AnnaBridge | 163:e59c8e839560 | 9184 | #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ |
| AnnaBridge | 163:e59c8e839560 | 9185 | #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ |
| AnnaBridge | 163:e59c8e839560 | 9186 | #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ |
| AnnaBridge | 163:e59c8e839560 | 9187 | #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ |
| AnnaBridge | 163:e59c8e839560 | 9188 | #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ |
| AnnaBridge | 163:e59c8e839560 | 9189 | #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ |
| AnnaBridge | 163:e59c8e839560 | 9190 | #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ |
| AnnaBridge | 163:e59c8e839560 | 9191 | #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ |
| AnnaBridge | 163:e59c8e839560 | 9192 | #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ |
| AnnaBridge | 163:e59c8e839560 | 9193 | #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ |
| AnnaBridge | 163:e59c8e839560 | 9194 | #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ |
| AnnaBridge | 163:e59c8e839560 | 9195 | #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ |
| AnnaBridge | 163:e59c8e839560 | 9196 | #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ |
| AnnaBridge | 163:e59c8e839560 | 9197 | #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ |
| AnnaBridge | 163:e59c8e839560 | 9198 | |
| AnnaBridge | 163:e59c8e839560 | 9199 | /*!< USB configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9200 | #define RCC_CFGR_USBPRE_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9201 | #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9202 | #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 9203 | |
| AnnaBridge | 163:e59c8e839560 | 9204 | #define RCC_CFGR_USBPRE_DIV1_5 (0x00000000U) /*!< USB prescaler is PLL clock divided by 1.5 */ |
| AnnaBridge | 163:e59c8e839560 | 9205 | #define RCC_CFGR_USBPRE_DIV1 (0x00400000U) /*!< USB prescaler is PLL clock divided by 1 */ |
| AnnaBridge | 163:e59c8e839560 | 9206 | |
| AnnaBridge | 163:e59c8e839560 | 9207 | /*!< I2S configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9208 | #define RCC_CFGR_I2SSRC_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9209 | #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9210 | #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk /*!< I2S external clock source selection */ |
| AnnaBridge | 163:e59c8e839560 | 9211 | |
| AnnaBridge | 163:e59c8e839560 | 9212 | #define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U) /*!< System clock selected as I2S clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9213 | #define RCC_CFGR_I2SSRC_EXT (0x00800000U) /*!< External clock selected as I2S clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9214 | |
| AnnaBridge | 163:e59c8e839560 | 9215 | /*!< MCO configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9216 | #define RCC_CFGR_MCO_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 9217 | #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9218 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
| AnnaBridge | 163:e59c8e839560 | 9219 | #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9220 | #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9221 | #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9222 | |
| AnnaBridge | 163:e59c8e839560 | 9223 | #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ |
| AnnaBridge | 163:e59c8e839560 | 9224 | #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9225 | #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9226 | #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9227 | #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9228 | #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9229 | #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ |
| AnnaBridge | 163:e59c8e839560 | 9230 | |
| AnnaBridge | 163:e59c8e839560 | 9231 | #define RCC_CFGR_MCOF_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9232 | #define RCC_CFGR_MCOF_Msk (0x1U << RCC_CFGR_MCOF_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9233 | #define RCC_CFGR_MCOF RCC_CFGR_MCOF_Msk /*!< Microcontroller Clock Output Flag */ |
| AnnaBridge | 163:e59c8e839560 | 9234 | /* Reference defines */ |
| AnnaBridge | 163:e59c8e839560 | 9235 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO |
| AnnaBridge | 163:e59c8e839560 | 9236 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 |
| AnnaBridge | 163:e59c8e839560 | 9237 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 |
| AnnaBridge | 163:e59c8e839560 | 9238 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 |
| AnnaBridge | 163:e59c8e839560 | 9239 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK |
| AnnaBridge | 163:e59c8e839560 | 9240 | #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI |
| AnnaBridge | 163:e59c8e839560 | 9241 | #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE |
| AnnaBridge | 163:e59c8e839560 | 9242 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK |
| AnnaBridge | 163:e59c8e839560 | 9243 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI |
| AnnaBridge | 163:e59c8e839560 | 9244 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE |
| AnnaBridge | 163:e59c8e839560 | 9245 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL |
| AnnaBridge | 163:e59c8e839560 | 9246 | |
| AnnaBridge | 163:e59c8e839560 | 9247 | /********************* Bit definition for RCC_CIR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 9248 | #define RCC_CIR_LSIRDYF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9249 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9250 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9251 | #define RCC_CIR_LSERDYF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9252 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9253 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9254 | #define RCC_CIR_HSIRDYF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9255 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9256 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9257 | #define RCC_CIR_HSERDYF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 9258 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9259 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9260 | #define RCC_CIR_PLLRDYF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9261 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9262 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9263 | #define RCC_CIR_CSSF_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 9264 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9265 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 9266 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9267 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9268 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 9269 | #define RCC_CIR_LSERDYIE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9270 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9271 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 9272 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 9273 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9274 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 9275 | #define RCC_CIR_HSERDYIE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9276 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9277 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 9278 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9279 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9280 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 9281 | #define RCC_CIR_LSIRDYC_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9282 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9283 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9284 | #define RCC_CIR_LSERDYC_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9285 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9286 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9287 | #define RCC_CIR_HSIRDYC_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9288 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9289 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9290 | #define RCC_CIR_HSERDYC_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9291 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9292 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9293 | #define RCC_CIR_PLLRDYC_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9294 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9295 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9296 | #define RCC_CIR_CSSC_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9297 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9298 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
| AnnaBridge | 163:e59c8e839560 | 9299 | |
| AnnaBridge | 163:e59c8e839560 | 9300 | /****************** Bit definition for RCC_APB2RSTR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 9301 | #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9302 | #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9303 | #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ |
| AnnaBridge | 163:e59c8e839560 | 9304 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9305 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9306 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9307 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9308 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9309 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9310 | #define RCC_APB2RSTR_TIM8RST_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 9311 | #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9312 | #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9313 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9314 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9315 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9316 | #define RCC_APB2RSTR_TIM15RST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9317 | #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9318 | #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9319 | #define RCC_APB2RSTR_TIM16RST_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9320 | #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9321 | #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9322 | #define RCC_APB2RSTR_TIM17RST_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9323 | #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9324 | #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9325 | |
| AnnaBridge | 163:e59c8e839560 | 9326 | /****************** Bit definition for RCC_APB1RSTR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9327 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9328 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9329 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9330 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9331 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9332 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9333 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9334 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9335 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9336 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9337 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9338 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9339 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9340 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9341 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9342 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9343 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9344 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
| AnnaBridge | 163:e59c8e839560 | 9345 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9346 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9347 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9348 | #define RCC_APB1RSTR_SPI3RST_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 9349 | #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9350 | #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI3 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9351 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9352 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9353 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9354 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9355 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9356 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9357 | #define RCC_APB1RSTR_UART4RST_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9358 | #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9359 | #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9360 | #define RCC_APB1RSTR_UART5RST_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9361 | #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9362 | #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9363 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 9364 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9365 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9366 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9367 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9368 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9369 | #define RCC_APB1RSTR_USBRST_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9370 | #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9371 | #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ |
| AnnaBridge | 163:e59c8e839560 | 9372 | #define RCC_APB1RSTR_CANRST_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 9373 | #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9374 | #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ |
| AnnaBridge | 163:e59c8e839560 | 9375 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9376 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9377 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ |
| AnnaBridge | 163:e59c8e839560 | 9378 | #define RCC_APB1RSTR_DAC1RST_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 9379 | #define RCC_APB1RSTR_DAC1RST_Msk (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9380 | #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9381 | |
| AnnaBridge | 163:e59c8e839560 | 9382 | /****************** Bit definition for RCC_AHBENR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9383 | #define RCC_AHBENR_DMA1EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9384 | #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9385 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9386 | #define RCC_AHBENR_DMA2EN_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9387 | #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9388 | #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9389 | #define RCC_AHBENR_SRAMEN_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9390 | #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9391 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9392 | #define RCC_AHBENR_FLITFEN_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9393 | #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9394 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9395 | #define RCC_AHBENR_CRCEN_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 9396 | #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9397 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9398 | #define RCC_AHBENR_GPIOAEN_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9399 | #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9400 | #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9401 | #define RCC_AHBENR_GPIOBEN_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9402 | #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9403 | #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9404 | #define RCC_AHBENR_GPIOCEN_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9405 | #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9406 | #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9407 | #define RCC_AHBENR_GPIODEN_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9408 | #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9409 | #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9410 | #define RCC_AHBENR_GPIOEEN_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 9411 | #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9412 | #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIOE clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9413 | #define RCC_AHBENR_GPIOFEN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9414 | #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9415 | #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9416 | #define RCC_AHBENR_TSCEN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 9417 | #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9418 | #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9419 | #define RCC_AHBENR_ADC12EN_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9420 | #define RCC_AHBENR_ADC12EN_Msk (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9421 | #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9422 | #define RCC_AHBENR_ADC34EN_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 9423 | #define RCC_AHBENR_ADC34EN_Msk (0x1U << RCC_AHBENR_ADC34EN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9424 | #define RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk /*!< ADC3/ ADC4 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9425 | |
| AnnaBridge | 163:e59c8e839560 | 9426 | /***************** Bit definition for RCC_APB2ENR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9427 | #define RCC_APB2ENR_SYSCFGEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9428 | #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9429 | #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9430 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9431 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9432 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9433 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9434 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9435 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9436 | #define RCC_APB2ENR_TIM8EN_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 9437 | #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9438 | #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9439 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9440 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9441 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9442 | #define RCC_APB2ENR_TIM15EN_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9443 | #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9444 | #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9445 | #define RCC_APB2ENR_TIM16EN_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9446 | #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9447 | #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9448 | #define RCC_APB2ENR_TIM17EN_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9449 | #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9450 | #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9451 | |
| AnnaBridge | 163:e59c8e839560 | 9452 | /****************** Bit definition for RCC_APB1ENR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9453 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9454 | #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9455 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9456 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9457 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9458 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9459 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9460 | #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9461 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9462 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9463 | #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9464 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9465 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9466 | #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9467 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9468 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9469 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9470 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9471 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9472 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9473 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9474 | #define RCC_APB1ENR_SPI3EN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 9475 | #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9476 | #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9477 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9478 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9479 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9480 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9481 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9482 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9483 | #define RCC_APB1ENR_UART4EN_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9484 | #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9485 | #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9486 | #define RCC_APB1ENR_UART5EN_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9487 | #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9488 | #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9489 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 9490 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9491 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9492 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9493 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9494 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9495 | #define RCC_APB1ENR_USBEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9496 | #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9497 | #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9498 | #define RCC_APB1ENR_CANEN_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 9499 | #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9500 | #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9501 | #define RCC_APB1ENR_PWREN_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9502 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9503 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9504 | #define RCC_APB1ENR_DAC1EN_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 9505 | #define RCC_APB1ENR_DAC1EN_Msk (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9506 | #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9507 | |
| AnnaBridge | 163:e59c8e839560 | 9508 | /******************** Bit definition for RCC_BDCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9509 | #define RCC_BDCR_LSE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9510 | #define RCC_BDCR_LSE_Msk (0x7U << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 9511 | #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9512 | #define RCC_BDCR_LSEON_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9513 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9514 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
| AnnaBridge | 163:e59c8e839560 | 9515 | #define RCC_BDCR_LSERDY_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9516 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9517 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
| AnnaBridge | 163:e59c8e839560 | 9518 | #define RCC_BDCR_LSEBYP_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 9519 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9520 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
| AnnaBridge | 163:e59c8e839560 | 9521 | |
| AnnaBridge | 163:e59c8e839560 | 9522 | #define RCC_BDCR_LSEDRV_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 9523 | #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 163:e59c8e839560 | 9524 | #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ |
| AnnaBridge | 163:e59c8e839560 | 9525 | #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9526 | #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9527 | |
| AnnaBridge | 163:e59c8e839560 | 9528 | #define RCC_BDCR_RTCSEL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9529 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 9530 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
| AnnaBridge | 163:e59c8e839560 | 9531 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9532 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9533 | |
| AnnaBridge | 163:e59c8e839560 | 9534 | /*!< RTC configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9535 | #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ |
| AnnaBridge | 163:e59c8e839560 | 9536 | #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ |
| AnnaBridge | 163:e59c8e839560 | 9537 | #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ |
| AnnaBridge | 163:e59c8e839560 | 9538 | #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
| AnnaBridge | 163:e59c8e839560 | 9539 | |
| AnnaBridge | 163:e59c8e839560 | 9540 | #define RCC_BDCR_RTCEN_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 9541 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9542 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 9543 | #define RCC_BDCR_BDRST_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9544 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9545 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ |
| AnnaBridge | 163:e59c8e839560 | 9546 | |
| AnnaBridge | 163:e59c8e839560 | 9547 | /******************** Bit definition for RCC_CSR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 9548 | #define RCC_CSR_LSION_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9549 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9550 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
| AnnaBridge | 163:e59c8e839560 | 9551 | #define RCC_CSR_LSIRDY_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 9552 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9553 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
| AnnaBridge | 163:e59c8e839560 | 9554 | #define RCC_CSR_V18PWRRSTF_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9555 | #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9556 | #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9557 | #define RCC_CSR_RMVF_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 9558 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9559 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9560 | #define RCC_CSR_OBLRSTF_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 9561 | #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9562 | #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9563 | #define RCC_CSR_PINRSTF_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 9564 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9565 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9566 | #define RCC_CSR_PORRSTF_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 9567 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9568 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9569 | #define RCC_CSR_SFTRSTF_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9570 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9571 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9572 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 9573 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9574 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9575 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 9576 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9577 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9578 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 9579 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9580 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
| AnnaBridge | 163:e59c8e839560 | 9581 | |
| AnnaBridge | 163:e59c8e839560 | 9582 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 9583 | #define RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF |
| AnnaBridge | 163:e59c8e839560 | 9584 | |
| AnnaBridge | 163:e59c8e839560 | 9585 | /******************* Bit definition for RCC_AHBRSTR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 9586 | #define RCC_AHBRSTR_GPIOARST_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9587 | #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9588 | #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ |
| AnnaBridge | 163:e59c8e839560 | 9589 | #define RCC_AHBRSTR_GPIOBRST_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9590 | #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9591 | #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ |
| AnnaBridge | 163:e59c8e839560 | 9592 | #define RCC_AHBRSTR_GPIOCRST_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9593 | #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9594 | #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ |
| AnnaBridge | 163:e59c8e839560 | 9595 | #define RCC_AHBRSTR_GPIODRST_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9596 | #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9597 | #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ |
| AnnaBridge | 163:e59c8e839560 | 9598 | #define RCC_AHBRSTR_GPIOERST_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 9599 | #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9600 | #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */ |
| AnnaBridge | 163:e59c8e839560 | 9601 | #define RCC_AHBRSTR_GPIOFRST_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9602 | #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9603 | #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ |
| AnnaBridge | 163:e59c8e839560 | 9604 | #define RCC_AHBRSTR_TSCRST_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 9605 | #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9606 | #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ |
| AnnaBridge | 163:e59c8e839560 | 9607 | #define RCC_AHBRSTR_ADC12RST_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 9608 | #define RCC_AHBRSTR_ADC12RST_Msk (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9609 | #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9610 | #define RCC_AHBRSTR_ADC34RST_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 9611 | #define RCC_AHBRSTR_ADC34RST_Msk (0x1U << RCC_AHBRSTR_ADC34RST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 9612 | #define RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk /*!< ADC3 & ADC4 reset */ |
| AnnaBridge | 163:e59c8e839560 | 9613 | |
| AnnaBridge | 163:e59c8e839560 | 9614 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9615 | /*!< PREDIV configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9616 | #define RCC_CFGR2_PREDIV_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9617 | #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 9618 | #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9619 | #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9620 | #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9621 | #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9622 | #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9623 | |
| AnnaBridge | 163:e59c8e839560 | 9624 | #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ |
| AnnaBridge | 163:e59c8e839560 | 9625 | #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9626 | #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ |
| AnnaBridge | 163:e59c8e839560 | 9627 | #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9628 | #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ |
| AnnaBridge | 163:e59c8e839560 | 9629 | #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ |
| AnnaBridge | 163:e59c8e839560 | 9630 | #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ |
| AnnaBridge | 163:e59c8e839560 | 9631 | #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9632 | #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ |
| AnnaBridge | 163:e59c8e839560 | 9633 | #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ |
| AnnaBridge | 163:e59c8e839560 | 9634 | #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ |
| AnnaBridge | 163:e59c8e839560 | 9635 | #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ |
| AnnaBridge | 163:e59c8e839560 | 9636 | #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ |
| AnnaBridge | 163:e59c8e839560 | 9637 | #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ |
| AnnaBridge | 163:e59c8e839560 | 9638 | #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ |
| AnnaBridge | 163:e59c8e839560 | 9639 | #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9640 | |
| AnnaBridge | 163:e59c8e839560 | 9641 | /*!< ADCPRE12 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9642 | #define RCC_CFGR2_ADCPRE12_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9643 | #define RCC_CFGR2_ADCPRE12_Msk (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */ |
| AnnaBridge | 163:e59c8e839560 | 9644 | #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9645 | #define RCC_CFGR2_ADCPRE12_0 (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9646 | #define RCC_CFGR2_ADCPRE12_1 (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9647 | #define RCC_CFGR2_ADCPRE12_2 (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9648 | #define RCC_CFGR2_ADCPRE12_3 (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9649 | #define RCC_CFGR2_ADCPRE12_4 (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9650 | |
| AnnaBridge | 163:e59c8e839560 | 9651 | #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
| AnnaBridge | 163:e59c8e839560 | 9652 | #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */ |
| AnnaBridge | 163:e59c8e839560 | 9653 | #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9654 | #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9655 | #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */ |
| AnnaBridge | 163:e59c8e839560 | 9656 | #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9657 | #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */ |
| AnnaBridge | 163:e59c8e839560 | 9658 | #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */ |
| AnnaBridge | 163:e59c8e839560 | 9659 | #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9660 | #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */ |
| AnnaBridge | 163:e59c8e839560 | 9661 | #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */ |
| AnnaBridge | 163:e59c8e839560 | 9662 | #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */ |
| AnnaBridge | 163:e59c8e839560 | 9663 | #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */ |
| AnnaBridge | 163:e59c8e839560 | 9664 | |
| AnnaBridge | 163:e59c8e839560 | 9665 | /*!< ADCPRE34 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9666 | #define RCC_CFGR2_ADCPRE34_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9667 | #define RCC_CFGR2_ADCPRE34_Msk (0x1FU << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00003E00 */ |
| AnnaBridge | 163:e59c8e839560 | 9668 | #define RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk /*!< ADCPRE34[13:5] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9669 | #define RCC_CFGR2_ADCPRE34_0 (0x01U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9670 | #define RCC_CFGR2_ADCPRE34_1 (0x02U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9671 | #define RCC_CFGR2_ADCPRE34_2 (0x04U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9672 | #define RCC_CFGR2_ADCPRE34_3 (0x08U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9673 | #define RCC_CFGR2_ADCPRE34_4 (0x10U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9674 | |
| AnnaBridge | 163:e59c8e839560 | 9675 | #define RCC_CFGR2_ADCPRE34_NO (0x00000000U) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ |
| AnnaBridge | 163:e59c8e839560 | 9676 | #define RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U) /*!< ADC34 PLL clock divided by 1 */ |
| AnnaBridge | 163:e59c8e839560 | 9677 | #define RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U) /*!< ADC34 PLL clock divided by 2 */ |
| AnnaBridge | 163:e59c8e839560 | 9678 | #define RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U) /*!< ADC34 PLL clock divided by 4 */ |
| AnnaBridge | 163:e59c8e839560 | 9679 | #define RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U) /*!< ADC34 PLL clock divided by 6 */ |
| AnnaBridge | 163:e59c8e839560 | 9680 | #define RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U) /*!< ADC34 PLL clock divided by 8 */ |
| AnnaBridge | 163:e59c8e839560 | 9681 | #define RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U) /*!< ADC34 PLL clock divided by 10 */ |
| AnnaBridge | 163:e59c8e839560 | 9682 | #define RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U) /*!< ADC34 PLL clock divided by 12 */ |
| AnnaBridge | 163:e59c8e839560 | 9683 | #define RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U) /*!< ADC34 PLL clock divided by 16 */ |
| AnnaBridge | 163:e59c8e839560 | 9684 | #define RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U) /*!< ADC34 PLL clock divided by 32 */ |
| AnnaBridge | 163:e59c8e839560 | 9685 | #define RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U) /*!< ADC34 PLL clock divided by 64 */ |
| AnnaBridge | 163:e59c8e839560 | 9686 | #define RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U) /*!< ADC34 PLL clock divided by 128 */ |
| AnnaBridge | 163:e59c8e839560 | 9687 | #define RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U) /*!< ADC34 PLL clock divided by 256 */ |
| AnnaBridge | 163:e59c8e839560 | 9688 | |
| AnnaBridge | 163:e59c8e839560 | 9689 | /******************* Bit definition for RCC_CFGR3 register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9690 | #define RCC_CFGR3_USART1SW_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9691 | #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 9692 | #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9693 | #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9694 | #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9695 | |
| AnnaBridge | 163:e59c8e839560 | 9696 | #define RCC_CFGR3_USART1SW_PCLK2 (0x00000000U) /*!< PCLK2 clock used as USART1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9697 | #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9698 | #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9699 | #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9700 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 9701 | #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2 |
| AnnaBridge | 163:e59c8e839560 | 9702 | |
| AnnaBridge | 163:e59c8e839560 | 9703 | #define RCC_CFGR3_I2CSW_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9704 | #define RCC_CFGR3_I2CSW_Msk (0x3U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 9705 | #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9706 | #define RCC_CFGR3_I2C1SW_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9707 | #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9708 | #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9709 | #define RCC_CFGR3_I2C2SW_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9710 | #define RCC_CFGR3_I2C2SW_Msk (0x1U << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9711 | #define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk /*!< I2C2SW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9712 | |
| AnnaBridge | 163:e59c8e839560 | 9713 | #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9714 | #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9715 | #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9716 | #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9717 | #define RCC_CFGR3_I2C2SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9718 | #define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9719 | #define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9720 | #define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk /*!< System clock selected as I2C2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9721 | #define RCC_CFGR3_TIMSW_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9722 | #define RCC_CFGR3_TIMSW_Msk (0x3U << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 9723 | #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9724 | #define RCC_CFGR3_TIM1SW_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9725 | #define RCC_CFGR3_TIM1SW_Msk (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9726 | #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9727 | #define RCC_CFGR3_TIM8SW_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9728 | #define RCC_CFGR3_TIM8SW_Msk (0x1U << RCC_CFGR3_TIM8SW_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9729 | #define RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk /*!< TIM8SW bits */ |
| AnnaBridge | 163:e59c8e839560 | 9730 | #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9731 | #define RCC_CFGR3_TIM1SW_PLL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9732 | #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9733 | #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9734 | #define RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM8 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9735 | #define RCC_CFGR3_TIM8SW_PLL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9736 | #define RCC_CFGR3_TIM8SW_PLL_Msk (0x1U << RCC_CFGR3_TIM8SW_PLL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9737 | #define RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk /*!< PLL clock used as TIM8 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9738 | |
| AnnaBridge | 163:e59c8e839560 | 9739 | #define RCC_CFGR3_USART2SW_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9740 | #define RCC_CFGR3_USART2SW_Msk (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 163:e59c8e839560 | 9741 | #define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk /*!< USART2SW[1:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9742 | #define RCC_CFGR3_USART2SW_0 (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9743 | #define RCC_CFGR3_USART2SW_1 (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9744 | |
| AnnaBridge | 163:e59c8e839560 | 9745 | #define RCC_CFGR3_USART2SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9746 | #define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U) /*!< System clock selected as USART2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9747 | #define RCC_CFGR3_USART2SW_LSE (0x00020000U) /*!< LSE oscillator clock used as USART2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9748 | #define RCC_CFGR3_USART2SW_HSI (0x00030000U) /*!< HSI oscillator clock used as USART2 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9749 | |
| AnnaBridge | 163:e59c8e839560 | 9750 | #define RCC_CFGR3_USART3SW_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 9751 | #define RCC_CFGR3_USART3SW_Msk (0x3U << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 163:e59c8e839560 | 9752 | #define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk /*!< USART3SW[1:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9753 | #define RCC_CFGR3_USART3SW_0 (0x1U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9754 | #define RCC_CFGR3_USART3SW_1 (0x2U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9755 | |
| AnnaBridge | 163:e59c8e839560 | 9756 | #define RCC_CFGR3_USART3SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9757 | #define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U) /*!< System clock selected as USART3 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9758 | #define RCC_CFGR3_USART3SW_LSE (0x00080000U) /*!< LSE oscillator clock used as USART3 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9759 | #define RCC_CFGR3_USART3SW_HSI (0x000C0000U) /*!< HSI oscillator clock used as USART3 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9760 | |
| AnnaBridge | 163:e59c8e839560 | 9761 | #define RCC_CFGR3_UART4SW_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9762 | #define RCC_CFGR3_UART4SW_Msk (0x3U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 9763 | #define RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk /*!< UART4SW[1:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9764 | #define RCC_CFGR3_UART4SW_0 (0x1U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9765 | #define RCC_CFGR3_UART4SW_1 (0x2U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9766 | |
| AnnaBridge | 163:e59c8e839560 | 9767 | #define RCC_CFGR3_UART4SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART4 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9768 | #define RCC_CFGR3_UART4SW_SYSCLK (0x00100000U) /*!< System clock selected as UART4 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9769 | #define RCC_CFGR3_UART4SW_LSE (0x00200000U) /*!< LSE oscillator clock used as UART4 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9770 | #define RCC_CFGR3_UART4SW_HSI (0x00300000U) /*!< HSI oscillator clock used as UART4 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9771 | |
| AnnaBridge | 163:e59c8e839560 | 9772 | #define RCC_CFGR3_UART5SW_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9773 | #define RCC_CFGR3_UART5SW_Msk (0x3U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 9774 | #define RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk /*!< UART5SW[1:0] bits */ |
| AnnaBridge | 163:e59c8e839560 | 9775 | #define RCC_CFGR3_UART5SW_0 (0x1U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9776 | #define RCC_CFGR3_UART5SW_1 (0x2U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9777 | |
| AnnaBridge | 163:e59c8e839560 | 9778 | #define RCC_CFGR3_UART5SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART5 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9779 | #define RCC_CFGR3_UART5SW_SYSCLK (0x00400000U) /*!< System clock selected as UART5 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9780 | #define RCC_CFGR3_UART5SW_LSE (0x00800000U) /*!< LSE oscillator clock used as UART5 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9781 | #define RCC_CFGR3_UART5SW_HSI (0x00C00000U) /*!< HSI oscillator clock used as UART5 clock source */ |
| AnnaBridge | 163:e59c8e839560 | 9782 | |
| AnnaBridge | 163:e59c8e839560 | 9783 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 9784 | #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2 |
| AnnaBridge | 163:e59c8e839560 | 9785 | #define RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2 |
| AnnaBridge | 163:e59c8e839560 | 9786 | |
| AnnaBridge | 163:e59c8e839560 | 9787 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 9788 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 9789 | /* Real-Time Clock (RTC) */ |
| AnnaBridge | 163:e59c8e839560 | 9790 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 9791 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 9792 | /* |
| AnnaBridge | 163:e59c8e839560 | 9793 | * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| AnnaBridge | 163:e59c8e839560 | 9794 | */ |
| AnnaBridge | 163:e59c8e839560 | 9795 | #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ |
| AnnaBridge | 163:e59c8e839560 | 9796 | #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ |
| AnnaBridge | 163:e59c8e839560 | 9797 | #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */ |
| AnnaBridge | 163:e59c8e839560 | 9798 | #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ |
| AnnaBridge | 163:e59c8e839560 | 9799 | #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ |
| AnnaBridge | 163:e59c8e839560 | 9800 | |
| AnnaBridge | 163:e59c8e839560 | 9801 | /******************** Bits definition for RTC_TR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 9802 | #define RTC_TR_PM_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 9803 | #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9804 | #define RTC_TR_PM RTC_TR_PM_Msk |
| AnnaBridge | 163:e59c8e839560 | 9805 | #define RTC_TR_HT_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9806 | #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 9807 | #define RTC_TR_HT RTC_TR_HT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9808 | #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9809 | #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9810 | #define RTC_TR_HU_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9811 | #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 9812 | #define RTC_TR_HU RTC_TR_HU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9813 | #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9814 | #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9815 | #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9816 | #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9817 | #define RTC_TR_MNT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9818 | #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 9819 | #define RTC_TR_MNT RTC_TR_MNT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9820 | #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9821 | #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9822 | #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9823 | #define RTC_TR_MNU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9824 | #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 9825 | #define RTC_TR_MNU RTC_TR_MNU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9826 | #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9827 | #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9828 | #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9829 | #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9830 | #define RTC_TR_ST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9831 | #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 9832 | #define RTC_TR_ST RTC_TR_ST_Msk |
| AnnaBridge | 163:e59c8e839560 | 9833 | #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9834 | #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9835 | #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9836 | #define RTC_TR_SU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9837 | #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 9838 | #define RTC_TR_SU RTC_TR_SU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9839 | #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9840 | #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9841 | #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9842 | #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9843 | |
| AnnaBridge | 163:e59c8e839560 | 9844 | /******************** Bits definition for RTC_DR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 9845 | #define RTC_DR_YT_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9846 | #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 9847 | #define RTC_DR_YT RTC_DR_YT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9848 | #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9849 | #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9850 | #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9851 | #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9852 | #define RTC_DR_YU_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9853 | #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 9854 | #define RTC_DR_YU RTC_DR_YU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9855 | #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9856 | #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9857 | #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 9858 | #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9859 | #define RTC_DR_WDU_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 9860 | #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 163:e59c8e839560 | 9861 | #define RTC_DR_WDU RTC_DR_WDU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9862 | #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9863 | #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9864 | #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9865 | #define RTC_DR_MT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9866 | #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9867 | #define RTC_DR_MT RTC_DR_MT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9868 | #define RTC_DR_MU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9869 | #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 9870 | #define RTC_DR_MU RTC_DR_MU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9871 | #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9872 | #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9873 | #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9874 | #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9875 | #define RTC_DR_DT_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9876 | #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 9877 | #define RTC_DR_DT RTC_DR_DT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9878 | #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9879 | #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9880 | #define RTC_DR_DU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9881 | #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 9882 | #define RTC_DR_DU RTC_DR_DU_Msk |
| AnnaBridge | 163:e59c8e839560 | 9883 | #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9884 | #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9885 | #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9886 | #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9887 | |
| AnnaBridge | 163:e59c8e839560 | 9888 | /******************** Bits definition for RTC_CR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 9889 | #define RTC_CR_COE_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 9890 | #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 9891 | #define RTC_CR_COE RTC_CR_COE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9892 | #define RTC_CR_OSEL_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 9893 | #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 163:e59c8e839560 | 9894 | #define RTC_CR_OSEL RTC_CR_OSEL_Msk |
| AnnaBridge | 163:e59c8e839560 | 9895 | #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 9896 | #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 9897 | #define RTC_CR_POL_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 9898 | #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 9899 | #define RTC_CR_POL RTC_CR_POL_Msk |
| AnnaBridge | 163:e59c8e839560 | 9900 | #define RTC_CR_COSEL_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 9901 | #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 9902 | #define RTC_CR_COSEL RTC_CR_COSEL_Msk |
| AnnaBridge | 168:b9e159c1930a | 9903 | #define RTC_CR_BKP_Pos (18U) |
| AnnaBridge | 168:b9e159c1930a | 9904 | #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 168:b9e159c1930a | 9905 | #define RTC_CR_BKP RTC_CR_BKP_Msk |
| AnnaBridge | 163:e59c8e839560 | 9906 | #define RTC_CR_SUB1H_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 9907 | #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 9908 | #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
| AnnaBridge | 163:e59c8e839560 | 9909 | #define RTC_CR_ADD1H_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9910 | #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9911 | #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
| AnnaBridge | 163:e59c8e839560 | 9912 | #define RTC_CR_TSIE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 9913 | #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9914 | #define RTC_CR_TSIE RTC_CR_TSIE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9915 | #define RTC_CR_WUTIE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9916 | #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9917 | #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9918 | #define RTC_CR_ALRBIE_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 9919 | #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9920 | #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9921 | #define RTC_CR_ALRAIE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9922 | #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9923 | #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9924 | #define RTC_CR_TSE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9925 | #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9926 | #define RTC_CR_TSE RTC_CR_TSE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9927 | #define RTC_CR_WUTE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 9928 | #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9929 | #define RTC_CR_WUTE RTC_CR_WUTE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9930 | #define RTC_CR_ALRBE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9931 | #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9932 | #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9933 | #define RTC_CR_ALRAE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9934 | #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9935 | #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9936 | #define RTC_CR_FMT_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 9937 | #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9938 | #define RTC_CR_FMT RTC_CR_FMT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9939 | #define RTC_CR_BYPSHAD_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9940 | #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9941 | #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
| AnnaBridge | 163:e59c8e839560 | 9942 | #define RTC_CR_REFCKON_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9943 | #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9944 | #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
| AnnaBridge | 163:e59c8e839560 | 9945 | #define RTC_CR_TSEDGE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 9946 | #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 9947 | #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
| AnnaBridge | 163:e59c8e839560 | 9948 | #define RTC_CR_WUCKSEL_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 9949 | #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 163:e59c8e839560 | 9950 | #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
| AnnaBridge | 163:e59c8e839560 | 9951 | #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 9952 | #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 9953 | #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 9954 | |
| AnnaBridge | 168:b9e159c1930a | 9955 | /* Legacy defines */ |
| AnnaBridge | 168:b9e159c1930a | 9956 | #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos |
| AnnaBridge | 168:b9e159c1930a | 9957 | #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk |
| AnnaBridge | 168:b9e159c1930a | 9958 | #define RTC_CR_BCK RTC_CR_BKP |
| AnnaBridge | 168:b9e159c1930a | 9959 | |
| AnnaBridge | 163:e59c8e839560 | 9960 | /******************** Bits definition for RTC_ISR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 9961 | #define RTC_ISR_RECALPF_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 9962 | #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 9963 | #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9964 | #define RTC_ISR_TAMP3F_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 9965 | #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 9966 | #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk |
| AnnaBridge | 163:e59c8e839560 | 9967 | #define RTC_ISR_TAMP2F_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 9968 | #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 9969 | #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk |
| AnnaBridge | 163:e59c8e839560 | 9970 | #define RTC_ISR_TAMP1F_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 9971 | #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 9972 | #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk |
| AnnaBridge | 163:e59c8e839560 | 9973 | #define RTC_ISR_TSOVF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 9974 | #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 9975 | #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9976 | #define RTC_ISR_TSF_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 9977 | #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 9978 | #define RTC_ISR_TSF RTC_ISR_TSF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9979 | #define RTC_ISR_WUTF_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 9980 | #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 9981 | #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9982 | #define RTC_ISR_ALRBF_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 9983 | #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 9984 | #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9985 | #define RTC_ISR_ALRAF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 9986 | #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 9987 | #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9988 | #define RTC_ISR_INIT_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 9989 | #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 9990 | #define RTC_ISR_INIT RTC_ISR_INIT_Msk |
| AnnaBridge | 163:e59c8e839560 | 9991 | #define RTC_ISR_INITF_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 9992 | #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 9993 | #define RTC_ISR_INITF RTC_ISR_INITF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9994 | #define RTC_ISR_RSF_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 9995 | #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 9996 | #define RTC_ISR_RSF RTC_ISR_RSF_Msk |
| AnnaBridge | 163:e59c8e839560 | 9997 | #define RTC_ISR_INITS_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 9998 | #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 9999 | #define RTC_ISR_INITS RTC_ISR_INITS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10000 | #define RTC_ISR_SHPF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10001 | #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10002 | #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk |
| AnnaBridge | 163:e59c8e839560 | 10003 | #define RTC_ISR_WUTWF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10004 | #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10005 | #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk |
| AnnaBridge | 163:e59c8e839560 | 10006 | #define RTC_ISR_ALRBWF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10007 | #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10008 | #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk |
| AnnaBridge | 163:e59c8e839560 | 10009 | #define RTC_ISR_ALRAWF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10010 | #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10011 | #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk |
| AnnaBridge | 163:e59c8e839560 | 10012 | |
| AnnaBridge | 163:e59c8e839560 | 10013 | /******************** Bits definition for RTC_PRER register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10014 | #define RTC_PRER_PREDIV_A_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 10015 | #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 10016 | #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
| AnnaBridge | 163:e59c8e839560 | 10017 | #define RTC_PRER_PREDIV_S_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10018 | #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 163:e59c8e839560 | 10019 | #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
| AnnaBridge | 163:e59c8e839560 | 10020 | |
| AnnaBridge | 163:e59c8e839560 | 10021 | /******************** Bits definition for RTC_WUTR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10022 | #define RTC_WUTR_WUT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10023 | #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10024 | #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10025 | |
| AnnaBridge | 163:e59c8e839560 | 10026 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10027 | #define RTC_ALRMAR_MSK4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 10028 | #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10029 | #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
| AnnaBridge | 163:e59c8e839560 | 10030 | #define RTC_ALRMAR_WDSEL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 10031 | #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10032 | #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
| AnnaBridge | 163:e59c8e839560 | 10033 | #define RTC_ALRMAR_DT_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 10034 | #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10035 | #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10036 | #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10037 | #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10038 | #define RTC_ALRMAR_DU_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 10039 | #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10040 | #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10041 | #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10042 | #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10043 | #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10044 | #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10045 | #define RTC_ALRMAR_MSK3_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 10046 | #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 10047 | #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
| AnnaBridge | 163:e59c8e839560 | 10048 | #define RTC_ALRMAR_PM_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10049 | #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10050 | #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
| AnnaBridge | 163:e59c8e839560 | 10051 | #define RTC_ALRMAR_HT_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 10052 | #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 10053 | #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10054 | #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 10055 | #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 10056 | #define RTC_ALRMAR_HU_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 10057 | #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 10058 | #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10059 | #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 10060 | #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 10061 | #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 10062 | #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 10063 | #define RTC_ALRMAR_MSK2_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 10064 | #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10065 | #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
| AnnaBridge | 163:e59c8e839560 | 10066 | #define RTC_ALRMAR_MNT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10067 | #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 10068 | #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10069 | #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10070 | #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10071 | #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10072 | #define RTC_ALRMAR_MNU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10073 | #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10074 | #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10075 | #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10076 | #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10077 | #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10078 | #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10079 | #define RTC_ALRMAR_MSK1_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10080 | #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10081 | #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
| AnnaBridge | 163:e59c8e839560 | 10082 | #define RTC_ALRMAR_ST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10083 | #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 10084 | #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
| AnnaBridge | 163:e59c8e839560 | 10085 | #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10086 | #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10087 | #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10088 | #define RTC_ALRMAR_SU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10089 | #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10090 | #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10091 | #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10092 | #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10093 | #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10094 | #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10095 | |
| AnnaBridge | 163:e59c8e839560 | 10096 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10097 | #define RTC_ALRMBR_MSK4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 10098 | #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10099 | #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
| AnnaBridge | 163:e59c8e839560 | 10100 | #define RTC_ALRMBR_WDSEL_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 10101 | #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10102 | #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
| AnnaBridge | 163:e59c8e839560 | 10103 | #define RTC_ALRMBR_DT_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 10104 | #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10105 | #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10106 | #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10107 | #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10108 | #define RTC_ALRMBR_DU_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 10109 | #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10110 | #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10111 | #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10112 | #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10113 | #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10114 | #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10115 | #define RTC_ALRMBR_MSK3_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 10116 | #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 10117 | #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
| AnnaBridge | 163:e59c8e839560 | 10118 | #define RTC_ALRMBR_PM_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10119 | #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10120 | #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
| AnnaBridge | 163:e59c8e839560 | 10121 | #define RTC_ALRMBR_HT_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 10122 | #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 10123 | #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10124 | #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 10125 | #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 10126 | #define RTC_ALRMBR_HU_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 10127 | #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 10128 | #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10129 | #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 10130 | #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 10131 | #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 10132 | #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 10133 | #define RTC_ALRMBR_MSK2_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 10134 | #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10135 | #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
| AnnaBridge | 163:e59c8e839560 | 10136 | #define RTC_ALRMBR_MNT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10137 | #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 10138 | #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10139 | #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10140 | #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10141 | #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10142 | #define RTC_ALRMBR_MNU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10143 | #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10144 | #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10145 | #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10146 | #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10147 | #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10148 | #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10149 | #define RTC_ALRMBR_MSK1_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10150 | #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10151 | #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
| AnnaBridge | 163:e59c8e839560 | 10152 | #define RTC_ALRMBR_ST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10153 | #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 10154 | #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
| AnnaBridge | 163:e59c8e839560 | 10155 | #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10156 | #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10157 | #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10158 | #define RTC_ALRMBR_SU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10159 | #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10160 | #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10161 | #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10162 | #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10163 | #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10164 | #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10165 | |
| AnnaBridge | 163:e59c8e839560 | 10166 | /******************** Bits definition for RTC_WPR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 10167 | #define RTC_WPR_KEY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10168 | #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 10169 | #define RTC_WPR_KEY RTC_WPR_KEY_Msk |
| AnnaBridge | 163:e59c8e839560 | 10170 | |
| AnnaBridge | 163:e59c8e839560 | 10171 | /******************** Bits definition for RTC_SSR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 10172 | #define RTC_SSR_SS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10173 | #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10174 | #define RTC_SSR_SS RTC_SSR_SS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10175 | |
| AnnaBridge | 163:e59c8e839560 | 10176 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10177 | #define RTC_SHIFTR_SUBFS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10178 | #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 163:e59c8e839560 | 10179 | #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10180 | #define RTC_SHIFTR_ADD1S_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 10181 | #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10182 | #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
| AnnaBridge | 163:e59c8e839560 | 10183 | |
| AnnaBridge | 163:e59c8e839560 | 10184 | /******************** Bits definition for RTC_TSTR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10185 | #define RTC_TSTR_PM_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10186 | #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10187 | #define RTC_TSTR_PM RTC_TSTR_PM_Msk |
| AnnaBridge | 163:e59c8e839560 | 10188 | #define RTC_TSTR_HT_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 10189 | #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 10190 | #define RTC_TSTR_HT RTC_TSTR_HT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10191 | #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 10192 | #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 10193 | #define RTC_TSTR_HU_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 10194 | #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 10195 | #define RTC_TSTR_HU RTC_TSTR_HU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10196 | #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 10197 | #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 10198 | #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 10199 | #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 10200 | #define RTC_TSTR_MNT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10201 | #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 10202 | #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10203 | #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10204 | #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10205 | #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10206 | #define RTC_TSTR_MNU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10207 | #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10208 | #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10209 | #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10210 | #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10211 | #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10212 | #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10213 | #define RTC_TSTR_ST_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10214 | #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 10215 | #define RTC_TSTR_ST RTC_TSTR_ST_Msk |
| AnnaBridge | 163:e59c8e839560 | 10216 | #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10217 | #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10218 | #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10219 | #define RTC_TSTR_SU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10220 | #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10221 | #define RTC_TSTR_SU RTC_TSTR_SU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10222 | #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10223 | #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10224 | #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10225 | #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10226 | |
| AnnaBridge | 163:e59c8e839560 | 10227 | /******************** Bits definition for RTC_TSDR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10228 | #define RTC_TSDR_WDU_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10229 | #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 163:e59c8e839560 | 10230 | #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10231 | #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10232 | #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10233 | #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10234 | #define RTC_TSDR_MT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10235 | #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10236 | #define RTC_TSDR_MT RTC_TSDR_MT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10237 | #define RTC_TSDR_MU_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10238 | #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10239 | #define RTC_TSDR_MU RTC_TSDR_MU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10240 | #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10241 | #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10242 | #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10243 | #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10244 | #define RTC_TSDR_DT_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10245 | #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 10246 | #define RTC_TSDR_DT RTC_TSDR_DT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10247 | #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10248 | #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10249 | #define RTC_TSDR_DU_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10250 | #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10251 | #define RTC_TSDR_DU RTC_TSDR_DU_Msk |
| AnnaBridge | 163:e59c8e839560 | 10252 | #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10253 | #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10254 | #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10255 | #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10256 | |
| AnnaBridge | 163:e59c8e839560 | 10257 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10258 | #define RTC_TSSSR_SS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10259 | #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10260 | #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10261 | |
| AnnaBridge | 163:e59c8e839560 | 10262 | /******************** Bits definition for RTC_CAL register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10263 | #define RTC_CALR_CALP_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 10264 | #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10265 | #define RTC_CALR_CALP RTC_CALR_CALP_Msk |
| AnnaBridge | 163:e59c8e839560 | 10266 | #define RTC_CALR_CALW8_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 10267 | #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10268 | #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
| AnnaBridge | 163:e59c8e839560 | 10269 | #define RTC_CALR_CALW16_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10270 | #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10271 | #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
| AnnaBridge | 163:e59c8e839560 | 10272 | #define RTC_CALR_CALM_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10273 | #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 163:e59c8e839560 | 10274 | #define RTC_CALR_CALM RTC_CALR_CALM_Msk |
| AnnaBridge | 163:e59c8e839560 | 10275 | #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10276 | #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10277 | #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10278 | #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10279 | #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10280 | #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10281 | #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10282 | #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10283 | #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10284 | |
| AnnaBridge | 163:e59c8e839560 | 10285 | /******************** Bits definition for RTC_TAFCR register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10286 | #define RTC_TAFCR_PC15MODE_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 10287 | #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 10288 | #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10289 | #define RTC_TAFCR_PC15VALUE_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10290 | #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10291 | #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10292 | #define RTC_TAFCR_PC14MODE_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 10293 | #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 10294 | #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10295 | #define RTC_TAFCR_PC14VALUE_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 10296 | #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 10297 | #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10298 | #define RTC_TAFCR_PC13MODE_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 10299 | #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 10300 | #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10301 | #define RTC_TAFCR_PC13VALUE_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 10302 | #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 10303 | #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10304 | #define RTC_TAFCR_TAMPPUDIS_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 10305 | #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10306 | #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10307 | #define RTC_TAFCR_TAMPPRCH_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10308 | #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 163:e59c8e839560 | 10309 | #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk |
| AnnaBridge | 163:e59c8e839560 | 10310 | #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10311 | #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10312 | #define RTC_TAFCR_TAMPFLT_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 10313 | #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 163:e59c8e839560 | 10314 | #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk |
| AnnaBridge | 163:e59c8e839560 | 10315 | #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10316 | #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10317 | #define RTC_TAFCR_TAMPFREQ_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10318 | #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 163:e59c8e839560 | 10319 | #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk |
| AnnaBridge | 163:e59c8e839560 | 10320 | #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10321 | #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10322 | #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10323 | #define RTC_TAFCR_TAMPTS_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10324 | #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10325 | #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10326 | #define RTC_TAFCR_TAMP3TRG_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10327 | #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10328 | #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk |
| AnnaBridge | 163:e59c8e839560 | 10329 | #define RTC_TAFCR_TAMP3E_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 10330 | #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10331 | #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk |
| AnnaBridge | 163:e59c8e839560 | 10332 | #define RTC_TAFCR_TAMP2TRG_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10333 | #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10334 | #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk |
| AnnaBridge | 163:e59c8e839560 | 10335 | #define RTC_TAFCR_TAMP2E_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10336 | #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10337 | #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk |
| AnnaBridge | 163:e59c8e839560 | 10338 | #define RTC_TAFCR_TAMPIE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10339 | #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10340 | #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk |
| AnnaBridge | 163:e59c8e839560 | 10341 | #define RTC_TAFCR_TAMP1TRG_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10342 | #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10343 | #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk |
| AnnaBridge | 163:e59c8e839560 | 10344 | #define RTC_TAFCR_TAMP1E_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10345 | #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10346 | #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk |
| AnnaBridge | 163:e59c8e839560 | 10347 | |
| AnnaBridge | 163:e59c8e839560 | 10348 | /* Reference defines */ |
| AnnaBridge | 163:e59c8e839560 | 10349 | #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE |
| AnnaBridge | 163:e59c8e839560 | 10350 | |
| AnnaBridge | 163:e59c8e839560 | 10351 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| AnnaBridge | 163:e59c8e839560 | 10352 | #define RTC_ALRMASSR_MASKSS_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 10353 | #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10354 | #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10355 | #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10356 | #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10357 | #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10358 | #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10359 | #define RTC_ALRMASSR_SS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10360 | #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 163:e59c8e839560 | 10361 | #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10362 | |
| AnnaBridge | 163:e59c8e839560 | 10363 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| AnnaBridge | 163:e59c8e839560 | 10364 | #define RTC_ALRMBSSR_MASKSS_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 10365 | #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10366 | #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10367 | #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10368 | #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10369 | #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10370 | #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10371 | #define RTC_ALRMBSSR_SS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10372 | #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 163:e59c8e839560 | 10373 | #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
| AnnaBridge | 163:e59c8e839560 | 10374 | |
| AnnaBridge | 163:e59c8e839560 | 10375 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10376 | #define RTC_BKP0R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10377 | #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10378 | #define RTC_BKP0R RTC_BKP0R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10379 | |
| AnnaBridge | 163:e59c8e839560 | 10380 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10381 | #define RTC_BKP1R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10382 | #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10383 | #define RTC_BKP1R RTC_BKP1R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10384 | |
| AnnaBridge | 163:e59c8e839560 | 10385 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10386 | #define RTC_BKP2R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10387 | #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10388 | #define RTC_BKP2R RTC_BKP2R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10389 | |
| AnnaBridge | 163:e59c8e839560 | 10390 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10391 | #define RTC_BKP3R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10392 | #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10393 | #define RTC_BKP3R RTC_BKP3R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10394 | |
| AnnaBridge | 163:e59c8e839560 | 10395 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10396 | #define RTC_BKP4R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10397 | #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10398 | #define RTC_BKP4R RTC_BKP4R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10399 | |
| AnnaBridge | 163:e59c8e839560 | 10400 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10401 | #define RTC_BKP5R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10402 | #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10403 | #define RTC_BKP5R RTC_BKP5R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10404 | |
| AnnaBridge | 163:e59c8e839560 | 10405 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10406 | #define RTC_BKP6R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10407 | #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10408 | #define RTC_BKP6R RTC_BKP6R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10409 | |
| AnnaBridge | 163:e59c8e839560 | 10410 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10411 | #define RTC_BKP7R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10412 | #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10413 | #define RTC_BKP7R RTC_BKP7R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10414 | |
| AnnaBridge | 163:e59c8e839560 | 10415 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10416 | #define RTC_BKP8R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10417 | #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10418 | #define RTC_BKP8R RTC_BKP8R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10419 | |
| AnnaBridge | 163:e59c8e839560 | 10420 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10421 | #define RTC_BKP9R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10422 | #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10423 | #define RTC_BKP9R RTC_BKP9R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10424 | |
| AnnaBridge | 163:e59c8e839560 | 10425 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10426 | #define RTC_BKP10R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10427 | #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10428 | #define RTC_BKP10R RTC_BKP10R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10429 | |
| AnnaBridge | 163:e59c8e839560 | 10430 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10431 | #define RTC_BKP11R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10432 | #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10433 | #define RTC_BKP11R RTC_BKP11R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10434 | |
| AnnaBridge | 163:e59c8e839560 | 10435 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10436 | #define RTC_BKP12R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10437 | #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10438 | #define RTC_BKP12R RTC_BKP12R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10439 | |
| AnnaBridge | 163:e59c8e839560 | 10440 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10441 | #define RTC_BKP13R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10442 | #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10443 | #define RTC_BKP13R RTC_BKP13R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10444 | |
| AnnaBridge | 163:e59c8e839560 | 10445 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10446 | #define RTC_BKP14R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10447 | #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10448 | #define RTC_BKP14R RTC_BKP14R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10449 | |
| AnnaBridge | 163:e59c8e839560 | 10450 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10451 | #define RTC_BKP15R_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10452 | #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10453 | #define RTC_BKP15R RTC_BKP15R_Msk |
| AnnaBridge | 163:e59c8e839560 | 10454 | |
| AnnaBridge | 163:e59c8e839560 | 10455 | /******************** Number of backup registers ******************************/ |
| AnnaBridge | 163:e59c8e839560 | 10456 | #define RTC_BKP_NUMBER 16 |
| AnnaBridge | 163:e59c8e839560 | 10457 | |
| AnnaBridge | 163:e59c8e839560 | 10458 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10459 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10460 | /* Serial Peripheral Interface (SPI) */ |
| AnnaBridge | 163:e59c8e839560 | 10461 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10462 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10463 | |
| AnnaBridge | 163:e59c8e839560 | 10464 | /* |
| AnnaBridge | 163:e59c8e839560 | 10465 | * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
| AnnaBridge | 163:e59c8e839560 | 10466 | */ |
| AnnaBridge | 163:e59c8e839560 | 10467 | #define SPI_I2S_SUPPORT /*!< I2S support */ |
| AnnaBridge | 163:e59c8e839560 | 10468 | #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ |
| AnnaBridge | 163:e59c8e839560 | 10469 | |
| AnnaBridge | 163:e59c8e839560 | 10470 | /******************* Bit definition for SPI_CR1 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 10471 | #define SPI_CR1_CPHA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10472 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10473 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
| AnnaBridge | 163:e59c8e839560 | 10474 | #define SPI_CR1_CPOL_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10475 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10476 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 10477 | #define SPI_CR1_MSTR_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10478 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10479 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
| AnnaBridge | 163:e59c8e839560 | 10480 | #define SPI_CR1_BR_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10481 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 163:e59c8e839560 | 10482 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
| AnnaBridge | 163:e59c8e839560 | 10483 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10484 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10485 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10486 | #define SPI_CR1_SPE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10487 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10488 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10489 | #define SPI_CR1_LSBFIRST_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10490 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10491 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
| AnnaBridge | 163:e59c8e839560 | 10492 | #define SPI_CR1_SSI_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10493 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10494 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
| AnnaBridge | 163:e59c8e839560 | 10495 | #define SPI_CR1_SSM_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 10496 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10497 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
| AnnaBridge | 163:e59c8e839560 | 10498 | #define SPI_CR1_RXONLY_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 10499 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10500 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
| AnnaBridge | 163:e59c8e839560 | 10501 | #define SPI_CR1_CRCL_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 10502 | #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10503 | #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ |
| AnnaBridge | 163:e59c8e839560 | 10504 | #define SPI_CR1_CRCNEXT_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10505 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10506 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
| AnnaBridge | 163:e59c8e839560 | 10507 | #define SPI_CR1_CRCEN_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10508 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10509 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
| AnnaBridge | 163:e59c8e839560 | 10510 | #define SPI_CR1_BIDIOE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 10511 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10512 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
| AnnaBridge | 163:e59c8e839560 | 10513 | #define SPI_CR1_BIDIMODE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 10514 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 10515 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 10516 | |
| AnnaBridge | 163:e59c8e839560 | 10517 | /******************* Bit definition for SPI_CR2 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 10518 | #define SPI_CR2_RXDMAEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10519 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10520 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10521 | #define SPI_CR2_TXDMAEN_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10522 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10523 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10524 | #define SPI_CR2_SSOE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10525 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10526 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10527 | #define SPI_CR2_NSSP_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10528 | #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10529 | #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10530 | #define SPI_CR2_FRF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10531 | #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10532 | #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10533 | #define SPI_CR2_ERRIE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 10534 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10535 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10536 | #define SPI_CR2_RXNEIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10537 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10538 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10539 | #define SPI_CR2_TXEIE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10540 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10541 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10542 | #define SPI_CR2_DS_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10543 | #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10544 | #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ |
| AnnaBridge | 163:e59c8e839560 | 10545 | #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10546 | #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10547 | #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10548 | #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10549 | #define SPI_CR2_FRXTH_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10550 | #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10551 | #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ |
| AnnaBridge | 163:e59c8e839560 | 10552 | #define SPI_CR2_LDMARX_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10553 | #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10554 | #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ |
| AnnaBridge | 163:e59c8e839560 | 10555 | #define SPI_CR2_LDMATX_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 10556 | #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10557 | #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ |
| AnnaBridge | 163:e59c8e839560 | 10558 | |
| AnnaBridge | 163:e59c8e839560 | 10559 | /******************** Bit definition for SPI_SR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 10560 | #define SPI_SR_RXNE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10561 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10562 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
| AnnaBridge | 163:e59c8e839560 | 10563 | #define SPI_SR_TXE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10564 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10565 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
| AnnaBridge | 163:e59c8e839560 | 10566 | #define SPI_SR_CHSIDE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10567 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10568 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
| AnnaBridge | 163:e59c8e839560 | 10569 | #define SPI_SR_UDR_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10570 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10571 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 10572 | #define SPI_SR_CRCERR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10573 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10574 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
| AnnaBridge | 163:e59c8e839560 | 10575 | #define SPI_SR_MODF_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 10576 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10577 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
| AnnaBridge | 163:e59c8e839560 | 10578 | #define SPI_SR_OVR_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10579 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10580 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
| AnnaBridge | 163:e59c8e839560 | 10581 | #define SPI_SR_BSY_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10582 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10583 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
| AnnaBridge | 163:e59c8e839560 | 10584 | #define SPI_SR_FRE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10585 | #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10586 | #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ |
| AnnaBridge | 163:e59c8e839560 | 10587 | #define SPI_SR_FRLVL_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 10588 | #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 163:e59c8e839560 | 10589 | #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ |
| AnnaBridge | 163:e59c8e839560 | 10590 | #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10591 | #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10592 | #define SPI_SR_FTLVL_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 10593 | #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 163:e59c8e839560 | 10594 | #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ |
| AnnaBridge | 163:e59c8e839560 | 10595 | #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10596 | #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10597 | |
| AnnaBridge | 163:e59c8e839560 | 10598 | /******************** Bit definition for SPI_DR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 10599 | #define SPI_DR_DR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10600 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10601 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
| AnnaBridge | 163:e59c8e839560 | 10602 | |
| AnnaBridge | 163:e59c8e839560 | 10603 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 10604 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10605 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10606 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
| AnnaBridge | 163:e59c8e839560 | 10607 | |
| AnnaBridge | 163:e59c8e839560 | 10608 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 10609 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10610 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10611 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
| AnnaBridge | 163:e59c8e839560 | 10612 | |
| AnnaBridge | 163:e59c8e839560 | 10613 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 10614 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10615 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 10616 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
| AnnaBridge | 163:e59c8e839560 | 10617 | |
| AnnaBridge | 163:e59c8e839560 | 10618 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10619 | #define SPI_I2SCFGR_CHLEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10620 | #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10621 | #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ |
| AnnaBridge | 163:e59c8e839560 | 10622 | #define SPI_I2SCFGR_DATLEN_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10623 | #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 163:e59c8e839560 | 10624 | #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
| AnnaBridge | 163:e59c8e839560 | 10625 | #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10626 | #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10627 | #define SPI_I2SCFGR_CKPOL_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10628 | #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10629 | #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ |
| AnnaBridge | 163:e59c8e839560 | 10630 | #define SPI_I2SCFGR_I2SSTD_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10631 | #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 163:e59c8e839560 | 10632 | #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
| AnnaBridge | 163:e59c8e839560 | 10633 | #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10634 | #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10635 | #define SPI_I2SCFGR_PCMSYNC_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10636 | #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10637 | #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ |
| AnnaBridge | 163:e59c8e839560 | 10638 | #define SPI_I2SCFGR_I2SCFG_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10639 | #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 10640 | #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
| AnnaBridge | 163:e59c8e839560 | 10641 | #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10642 | #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10643 | #define SPI_I2SCFGR_I2SE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 10644 | #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 10645 | #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10646 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 10647 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10648 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ |
| AnnaBridge | 163:e59c8e839560 | 10649 | |
| AnnaBridge | 163:e59c8e839560 | 10650 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 10651 | #define SPI_I2SPR_I2SDIV_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10652 | #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 10653 | #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 10654 | #define SPI_I2SPR_ODD_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10655 | #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10656 | #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 10657 | #define SPI_I2SPR_MCKOE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 10658 | #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 10659 | #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10660 | |
| AnnaBridge | 163:e59c8e839560 | 10661 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10662 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10663 | /* System Configuration(SYSCFG) */ |
| AnnaBridge | 163:e59c8e839560 | 10664 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10665 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10666 | /***************** Bit definition for SYSCFG_CFGR1 register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10667 | #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10668 | #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 10669 | #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ |
| AnnaBridge | 163:e59c8e839560 | 10670 | #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 10671 | #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 10672 | #define SYSCFG_CFGR1_USB_IT_RMP_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 10673 | #define SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1U << SYSCFG_CFGR1_USB_IT_RMP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10674 | #define SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk /*!< USB interrupt remap */ |
| AnnaBridge | 163:e59c8e839560 | 10675 | #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10676 | #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10677 | #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */ |
| AnnaBridge | 163:e59c8e839560 | 10678 | #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10679 | #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10680 | #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */ |
| AnnaBridge | 163:e59c8e839560 | 10681 | #define SYSCFG_CFGR1_DMA_RMP_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10682 | #define SYSCFG_CFGR1_DMA_RMP_Msk (0x79U << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00007900 */ |
| AnnaBridge | 163:e59c8e839560 | 10683 | #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ |
| AnnaBridge | 163:e59c8e839560 | 10684 | #define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10685 | #define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10686 | #define SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk /*!< ADC2 and ADC4 DMA remap */ |
| AnnaBridge | 163:e59c8e839560 | 10687 | #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 10688 | #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 10689 | #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ |
| AnnaBridge | 163:e59c8e839560 | 10690 | #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10691 | #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 10692 | #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ |
| AnnaBridge | 163:e59c8e839560 | 10693 | #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 10694 | #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 10695 | #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */ |
| AnnaBridge | 163:e59c8e839560 | 10696 | #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 10697 | #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 10698 | #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */ |
| AnnaBridge | 163:e59c8e839560 | 10699 | #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 10700 | #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 10701 | #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10702 | #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 10703 | #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 10704 | #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10705 | #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 10706 | #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 10707 | #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10708 | #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 10709 | #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 10710 | #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10711 | #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 10712 | #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 10713 | #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10714 | #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 10715 | #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 10716 | #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ |
| AnnaBridge | 163:e59c8e839560 | 10717 | #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10718 | #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 10719 | #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */ |
| AnnaBridge | 163:e59c8e839560 | 10720 | #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10721 | #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 10722 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10723 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 10724 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 163:e59c8e839560 | 10725 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 10726 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 10727 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 163:e59c8e839560 | 10728 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM4_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 10729 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM4_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_TIM4_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 163:e59c8e839560 | 10730 | #define SYSCFG_CFGR1_ENCODER_MODE_TIM4 SYSCFG_CFGR1_ENCODER_MODE_TIM4_Msk /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 163:e59c8e839560 | 10731 | #define SYSCFG_CFGR1_FPU_IE_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 10732 | #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10733 | #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 10734 | #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10735 | #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10736 | #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10737 | #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10738 | #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10739 | #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 10740 | |
| AnnaBridge | 163:e59c8e839560 | 10741 | /***************** Bit definition for SYSCFG_RCR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 10742 | #define SYSCFG_RCR_PAGE0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10743 | #define SYSCFG_RCR_PAGE0_Msk (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10744 | #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */ |
| AnnaBridge | 163:e59c8e839560 | 10745 | #define SYSCFG_RCR_PAGE1_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10746 | #define SYSCFG_RCR_PAGE1_Msk (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10747 | #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */ |
| AnnaBridge | 163:e59c8e839560 | 10748 | #define SYSCFG_RCR_PAGE2_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10749 | #define SYSCFG_RCR_PAGE2_Msk (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10750 | #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */ |
| AnnaBridge | 163:e59c8e839560 | 10751 | #define SYSCFG_RCR_PAGE3_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 10752 | #define SYSCFG_RCR_PAGE3_Msk (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 10753 | #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */ |
| AnnaBridge | 163:e59c8e839560 | 10754 | #define SYSCFG_RCR_PAGE4_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10755 | #define SYSCFG_RCR_PAGE4_Msk (0x1U << SYSCFG_RCR_PAGE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10756 | #define SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk /*!< ICODE SRAM Write protection page 4 */ |
| AnnaBridge | 163:e59c8e839560 | 10757 | #define SYSCFG_RCR_PAGE5_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 10758 | #define SYSCFG_RCR_PAGE5_Msk (0x1U << SYSCFG_RCR_PAGE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 10759 | #define SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk /*!< ICODE SRAM Write protection page 5 */ |
| AnnaBridge | 163:e59c8e839560 | 10760 | #define SYSCFG_RCR_PAGE6_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 10761 | #define SYSCFG_RCR_PAGE6_Msk (0x1U << SYSCFG_RCR_PAGE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 10762 | #define SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk /*!< ICODE SRAM Write protection page 6 */ |
| AnnaBridge | 163:e59c8e839560 | 10763 | #define SYSCFG_RCR_PAGE7_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 10764 | #define SYSCFG_RCR_PAGE7_Msk (0x1U << SYSCFG_RCR_PAGE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 10765 | #define SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk /*!< ICODE SRAM Write protection page 7 */ |
| AnnaBridge | 163:e59c8e839560 | 10766 | |
| AnnaBridge | 163:e59c8e839560 | 10767 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10768 | #define SYSCFG_EXTICR1_EXTI0_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10769 | #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10770 | #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10771 | #define SYSCFG_EXTICR1_EXTI1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10772 | #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 10773 | #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10774 | #define SYSCFG_EXTICR1_EXTI2_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10775 | #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10776 | #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10777 | #define SYSCFG_EXTICR1_EXTI3_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10778 | #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 10779 | #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10780 | |
| AnnaBridge | 163:e59c8e839560 | 10781 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10782 | * @brief EXTI0 configuration |
| AnnaBridge | 163:e59c8e839560 | 10783 | */ |
| AnnaBridge | 163:e59c8e839560 | 10784 | #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10785 | #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10786 | #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10787 | #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10788 | #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10789 | #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10790 | |
| AnnaBridge | 163:e59c8e839560 | 10791 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10792 | * @brief EXTI1 configuration |
| AnnaBridge | 163:e59c8e839560 | 10793 | */ |
| AnnaBridge | 163:e59c8e839560 | 10794 | #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10795 | #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10796 | #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10797 | #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10798 | #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10799 | #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10800 | |
| AnnaBridge | 163:e59c8e839560 | 10801 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10802 | * @brief EXTI2 configuration |
| AnnaBridge | 163:e59c8e839560 | 10803 | */ |
| AnnaBridge | 163:e59c8e839560 | 10804 | #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10805 | #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10806 | #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10807 | #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10808 | #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10809 | #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10810 | |
| AnnaBridge | 163:e59c8e839560 | 10811 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10812 | * @brief EXTI3 configuration |
| AnnaBridge | 163:e59c8e839560 | 10813 | */ |
| AnnaBridge | 163:e59c8e839560 | 10814 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10815 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10816 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10817 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10818 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10819 | |
| AnnaBridge | 163:e59c8e839560 | 10820 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10821 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10822 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10823 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10824 | #define SYSCFG_EXTICR2_EXTI5_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10825 | #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 10826 | #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10827 | #define SYSCFG_EXTICR2_EXTI6_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10828 | #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10829 | #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10830 | #define SYSCFG_EXTICR2_EXTI7_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10831 | #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 10832 | #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10833 | |
| AnnaBridge | 163:e59c8e839560 | 10834 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10835 | * @brief EXTI4 configuration |
| AnnaBridge | 163:e59c8e839560 | 10836 | */ |
| AnnaBridge | 163:e59c8e839560 | 10837 | #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10838 | #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10839 | #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10840 | #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10841 | #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10842 | #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10843 | |
| AnnaBridge | 163:e59c8e839560 | 10844 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10845 | * @brief EXTI5 configuration |
| AnnaBridge | 163:e59c8e839560 | 10846 | */ |
| AnnaBridge | 163:e59c8e839560 | 10847 | #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10848 | #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10849 | #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10850 | #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10851 | #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10852 | #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10853 | |
| AnnaBridge | 163:e59c8e839560 | 10854 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10855 | * @brief EXTI6 configuration |
| AnnaBridge | 163:e59c8e839560 | 10856 | */ |
| AnnaBridge | 163:e59c8e839560 | 10857 | #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10858 | #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10859 | #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10860 | #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10861 | #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10862 | #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10863 | |
| AnnaBridge | 163:e59c8e839560 | 10864 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10865 | * @brief EXTI7 configuration |
| AnnaBridge | 163:e59c8e839560 | 10866 | */ |
| AnnaBridge | 163:e59c8e839560 | 10867 | #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10868 | #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10869 | #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10870 | #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10871 | #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10872 | |
| AnnaBridge | 163:e59c8e839560 | 10873 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| AnnaBridge | 163:e59c8e839560 | 10874 | #define SYSCFG_EXTICR3_EXTI8_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10875 | #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10876 | #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10877 | #define SYSCFG_EXTICR3_EXTI9_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10878 | #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 10879 | #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10880 | #define SYSCFG_EXTICR3_EXTI10_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10881 | #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10882 | #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10883 | #define SYSCFG_EXTICR3_EXTI11_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10884 | #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 10885 | #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10886 | |
| AnnaBridge | 163:e59c8e839560 | 10887 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10888 | * @brief EXTI8 configuration |
| AnnaBridge | 163:e59c8e839560 | 10889 | */ |
| AnnaBridge | 163:e59c8e839560 | 10890 | #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10891 | #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10892 | #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10893 | #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10894 | #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10895 | |
| AnnaBridge | 163:e59c8e839560 | 10896 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10897 | * @brief EXTI9 configuration |
| AnnaBridge | 163:e59c8e839560 | 10898 | */ |
| AnnaBridge | 163:e59c8e839560 | 10899 | #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10900 | #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10901 | #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10902 | #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10903 | #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10904 | #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10905 | |
| AnnaBridge | 163:e59c8e839560 | 10906 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10907 | * @brief EXTI10 configuration |
| AnnaBridge | 163:e59c8e839560 | 10908 | */ |
| AnnaBridge | 163:e59c8e839560 | 10909 | #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10910 | #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10911 | #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10912 | #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10913 | #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10914 | #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10915 | |
| AnnaBridge | 163:e59c8e839560 | 10916 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10917 | * @brief EXTI11 configuration |
| AnnaBridge | 163:e59c8e839560 | 10918 | */ |
| AnnaBridge | 163:e59c8e839560 | 10919 | #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10920 | #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10921 | #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10922 | #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10923 | #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10924 | |
| AnnaBridge | 163:e59c8e839560 | 10925 | /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 10926 | #define SYSCFG_EXTICR4_EXTI12_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10927 | #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 10928 | #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10929 | #define SYSCFG_EXTICR4_EXTI13_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10930 | #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 10931 | #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10932 | #define SYSCFG_EXTICR4_EXTI14_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10933 | #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 10934 | #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10935 | #define SYSCFG_EXTICR4_EXTI15_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 10936 | #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 10937 | #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
| AnnaBridge | 163:e59c8e839560 | 10938 | |
| AnnaBridge | 163:e59c8e839560 | 10939 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10940 | * @brief EXTI12 configuration |
| AnnaBridge | 163:e59c8e839560 | 10941 | */ |
| AnnaBridge | 163:e59c8e839560 | 10942 | #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10943 | #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10944 | #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10945 | #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10946 | #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10947 | |
| AnnaBridge | 163:e59c8e839560 | 10948 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10949 | * @brief EXTI13 configuration |
| AnnaBridge | 163:e59c8e839560 | 10950 | */ |
| AnnaBridge | 163:e59c8e839560 | 10951 | #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10952 | #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10953 | #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10954 | #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10955 | #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10956 | |
| AnnaBridge | 163:e59c8e839560 | 10957 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10958 | * @brief EXTI14 configuration |
| AnnaBridge | 163:e59c8e839560 | 10959 | */ |
| AnnaBridge | 163:e59c8e839560 | 10960 | #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10961 | #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10962 | #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10963 | #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10964 | #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10965 | |
| AnnaBridge | 163:e59c8e839560 | 10966 | /*!<* |
| AnnaBridge | 163:e59c8e839560 | 10967 | * @brief EXTI15 configuration |
| AnnaBridge | 163:e59c8e839560 | 10968 | */ |
| AnnaBridge | 163:e59c8e839560 | 10969 | #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10970 | #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10971 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10972 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10973 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
| AnnaBridge | 163:e59c8e839560 | 10974 | |
| AnnaBridge | 163:e59c8e839560 | 10975 | /***************** Bit definition for SYSCFG_CFGR2 register ****************/ |
| AnnaBridge | 163:e59c8e839560 | 10976 | #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10977 | #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 10978 | #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */ |
| AnnaBridge | 163:e59c8e839560 | 10979 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 10980 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 10981 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */ |
| AnnaBridge | 163:e59c8e839560 | 10982 | #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 10983 | #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 10984 | #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */ |
| AnnaBridge | 163:e59c8e839560 | 10985 | #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 10986 | #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 10987 | #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */ |
| AnnaBridge | 163:e59c8e839560 | 10988 | #define SYSCFG_CFGR2_SRAM_PE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 10989 | #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 10990 | #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */ |
| AnnaBridge | 163:e59c8e839560 | 10991 | |
| AnnaBridge | 163:e59c8e839560 | 10992 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10993 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10994 | /* TIM */ |
| AnnaBridge | 163:e59c8e839560 | 10995 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 10996 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 10997 | /******************* Bit definition for TIM_CR1 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 10998 | #define TIM_CR1_CEN_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 10999 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11000 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
| AnnaBridge | 163:e59c8e839560 | 11001 | #define TIM_CR1_UDIS_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11002 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11003 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
| AnnaBridge | 163:e59c8e839560 | 11004 | #define TIM_CR1_URS_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11005 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11006 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
| AnnaBridge | 163:e59c8e839560 | 11007 | #define TIM_CR1_OPM_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11008 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11009 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
| AnnaBridge | 163:e59c8e839560 | 11010 | #define TIM_CR1_DIR_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11011 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11012 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
| AnnaBridge | 163:e59c8e839560 | 11013 | |
| AnnaBridge | 163:e59c8e839560 | 11014 | #define TIM_CR1_CMS_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11015 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 163:e59c8e839560 | 11016 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11017 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11018 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11019 | |
| AnnaBridge | 163:e59c8e839560 | 11020 | #define TIM_CR1_ARPE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11021 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11022 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11023 | |
| AnnaBridge | 163:e59c8e839560 | 11024 | #define TIM_CR1_CKD_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11025 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 11026 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
| AnnaBridge | 163:e59c8e839560 | 11027 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11028 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11029 | |
| AnnaBridge | 163:e59c8e839560 | 11030 | #define TIM_CR1_UIFREMAP_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11031 | #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11032 | #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ |
| AnnaBridge | 163:e59c8e839560 | 11033 | |
| AnnaBridge | 163:e59c8e839560 | 11034 | /******************* Bit definition for TIM_CR2 register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11035 | #define TIM_CR2_CCPC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11036 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11037 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
| AnnaBridge | 163:e59c8e839560 | 11038 | #define TIM_CR2_CCUS_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11039 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11040 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
| AnnaBridge | 163:e59c8e839560 | 11041 | #define TIM_CR2_CCDS_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11042 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11043 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
| AnnaBridge | 163:e59c8e839560 | 11044 | |
| AnnaBridge | 163:e59c8e839560 | 11045 | #define TIM_CR2_MMS_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11046 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 11047 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11048 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11049 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11050 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11051 | |
| AnnaBridge | 163:e59c8e839560 | 11052 | #define TIM_CR2_TI1S_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11053 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11054 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
| AnnaBridge | 163:e59c8e839560 | 11055 | #define TIM_CR2_OIS1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11056 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11057 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11058 | #define TIM_CR2_OIS1N_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11059 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11060 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
| AnnaBridge | 163:e59c8e839560 | 11061 | #define TIM_CR2_OIS2_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11062 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11063 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11064 | #define TIM_CR2_OIS2N_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11065 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11066 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
| AnnaBridge | 163:e59c8e839560 | 11067 | #define TIM_CR2_OIS3_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11068 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11069 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11070 | #define TIM_CR2_OIS3N_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11071 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11072 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
| AnnaBridge | 163:e59c8e839560 | 11073 | #define TIM_CR2_OIS4_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11074 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11075 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11076 | |
| AnnaBridge | 163:e59c8e839560 | 11077 | #define TIM_CR2_OIS5_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11078 | #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11079 | #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11080 | #define TIM_CR2_OIS6_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 11081 | #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 11082 | #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */ |
| AnnaBridge | 163:e59c8e839560 | 11083 | |
| AnnaBridge | 163:e59c8e839560 | 11084 | #define TIM_CR2_MMS2_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 11085 | #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 11086 | #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11087 | #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 11088 | #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 11089 | #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 11090 | #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 11091 | |
| AnnaBridge | 163:e59c8e839560 | 11092 | /******************* Bit definition for TIM_SMCR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11093 | #define TIM_SMCR_SMS_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11094 | #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ |
| AnnaBridge | 163:e59c8e839560 | 11095 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11096 | #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 11097 | #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11098 | #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11099 | #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11100 | |
| AnnaBridge | 163:e59c8e839560 | 11101 | #define TIM_SMCR_OCCS_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11102 | #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11103 | #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ |
| AnnaBridge | 163:e59c8e839560 | 11104 | |
| AnnaBridge | 163:e59c8e839560 | 11105 | #define TIM_SMCR_TS_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11106 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 163:e59c8e839560 | 11107 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11108 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11109 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11110 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11111 | |
| AnnaBridge | 163:e59c8e839560 | 11112 | #define TIM_SMCR_MSM_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11113 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11114 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
| AnnaBridge | 163:e59c8e839560 | 11115 | |
| AnnaBridge | 163:e59c8e839560 | 11116 | #define TIM_SMCR_ETF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11117 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 163:e59c8e839560 | 11118 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
| AnnaBridge | 163:e59c8e839560 | 11119 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11120 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11121 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11122 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11123 | |
| AnnaBridge | 163:e59c8e839560 | 11124 | #define TIM_SMCR_ETPS_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11125 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 11126 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11127 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11128 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11129 | |
| AnnaBridge | 163:e59c8e839560 | 11130 | #define TIM_SMCR_ECE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11131 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11132 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
| AnnaBridge | 163:e59c8e839560 | 11133 | #define TIM_SMCR_ETP_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11134 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11135 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11136 | |
| AnnaBridge | 163:e59c8e839560 | 11137 | /******************* Bit definition for TIM_DIER register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11138 | #define TIM_DIER_UIE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11139 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11140 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11141 | #define TIM_DIER_CC1IE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11142 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11143 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11144 | #define TIM_DIER_CC2IE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11145 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11146 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11147 | #define TIM_DIER_CC3IE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11148 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11149 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11150 | #define TIM_DIER_CC4IE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11151 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11152 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11153 | #define TIM_DIER_COMIE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11154 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11155 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11156 | #define TIM_DIER_TIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11157 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11158 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11159 | #define TIM_DIER_BIE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11160 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11161 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11162 | #define TIM_DIER_UDE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11163 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11164 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11165 | #define TIM_DIER_CC1DE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11166 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11167 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11168 | #define TIM_DIER_CC2DE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11169 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11170 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11171 | #define TIM_DIER_CC3DE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11172 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11173 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11174 | #define TIM_DIER_CC4DE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11175 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11176 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11177 | #define TIM_DIER_COMDE_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11178 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11179 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11180 | #define TIM_DIER_TDE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11181 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11182 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
| AnnaBridge | 163:e59c8e839560 | 11183 | |
| AnnaBridge | 163:e59c8e839560 | 11184 | /******************** Bit definition for TIM_SR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11185 | #define TIM_SR_UIF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11186 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11187 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11188 | #define TIM_SR_CC1IF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11189 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11190 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11191 | #define TIM_SR_CC2IF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11192 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11193 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11194 | #define TIM_SR_CC3IF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11195 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11196 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11197 | #define TIM_SR_CC4IF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11198 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11199 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11200 | #define TIM_SR_COMIF_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11201 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11202 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11203 | #define TIM_SR_TIF_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11204 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11205 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11206 | #define TIM_SR_BIF_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11207 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11208 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11209 | #define TIM_SR_B2IF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11210 | #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11211 | #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11212 | #define TIM_SR_CC1OF_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11213 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11214 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11215 | #define TIM_SR_CC2OF_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11216 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11217 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11218 | #define TIM_SR_CC3OF_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11219 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11220 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11221 | #define TIM_SR_CC4OF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11222 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11223 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11224 | #define TIM_SR_CC5IF_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11225 | #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11226 | #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11227 | #define TIM_SR_CC6IF_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 11228 | #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 11229 | #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 11230 | |
| AnnaBridge | 163:e59c8e839560 | 11231 | /******************* Bit definition for TIM_EGR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11232 | #define TIM_EGR_UG_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11233 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11234 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11235 | #define TIM_EGR_CC1G_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11236 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11237 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11238 | #define TIM_EGR_CC2G_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11239 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11240 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11241 | #define TIM_EGR_CC3G_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11242 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11243 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11244 | #define TIM_EGR_CC4G_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11245 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11246 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11247 | #define TIM_EGR_COMG_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11248 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11249 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11250 | #define TIM_EGR_TG_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11251 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11252 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11253 | #define TIM_EGR_BG_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11254 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11255 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11256 | #define TIM_EGR_B2G_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11257 | #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11258 | #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */ |
| AnnaBridge | 163:e59c8e839560 | 11259 | |
| AnnaBridge | 163:e59c8e839560 | 11260 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11261 | #define TIM_CCMR1_CC1S_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11262 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 11263 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11264 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11265 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11266 | |
| AnnaBridge | 163:e59c8e839560 | 11267 | #define TIM_CCMR1_OC1FE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11268 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11269 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11270 | #define TIM_CCMR1_OC1PE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11271 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11272 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11273 | |
| AnnaBridge | 163:e59c8e839560 | 11274 | #define TIM_CCMR1_OC1M_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11275 | #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 163:e59c8e839560 | 11276 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11277 | #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 11278 | #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11279 | #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11280 | #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11281 | |
| AnnaBridge | 163:e59c8e839560 | 11282 | #define TIM_CCMR1_OC1CE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11283 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11284 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11285 | |
| AnnaBridge | 163:e59c8e839560 | 11286 | #define TIM_CCMR1_CC2S_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11287 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 11288 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11289 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11290 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11291 | |
| AnnaBridge | 163:e59c8e839560 | 11292 | #define TIM_CCMR1_OC2FE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11293 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11294 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11295 | #define TIM_CCMR1_OC2PE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11296 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11297 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11298 | |
| AnnaBridge | 163:e59c8e839560 | 11299 | #define TIM_CCMR1_OC2M_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11300 | #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 163:e59c8e839560 | 11301 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11302 | #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 11303 | #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11304 | #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11305 | #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11306 | |
| AnnaBridge | 163:e59c8e839560 | 11307 | #define TIM_CCMR1_OC2CE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11308 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11309 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11310 | |
| AnnaBridge | 163:e59c8e839560 | 11311 | /*----------------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 11312 | |
| AnnaBridge | 163:e59c8e839560 | 11313 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11314 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 11315 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11316 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11317 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11318 | |
| AnnaBridge | 163:e59c8e839560 | 11319 | #define TIM_CCMR1_IC1F_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11320 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 11321 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| AnnaBridge | 163:e59c8e839560 | 11322 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11323 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11324 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11325 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11326 | |
| AnnaBridge | 163:e59c8e839560 | 11327 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11328 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 11329 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11330 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11331 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11332 | |
| AnnaBridge | 163:e59c8e839560 | 11333 | #define TIM_CCMR1_IC2F_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11334 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 11335 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| AnnaBridge | 163:e59c8e839560 | 11336 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11337 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11338 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11339 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11340 | |
| AnnaBridge | 163:e59c8e839560 | 11341 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11342 | #define TIM_CCMR2_CC3S_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11343 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 11344 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11345 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11346 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11347 | |
| AnnaBridge | 163:e59c8e839560 | 11348 | #define TIM_CCMR2_OC3FE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11349 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11350 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11351 | #define TIM_CCMR2_OC3PE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11352 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11353 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11354 | |
| AnnaBridge | 163:e59c8e839560 | 11355 | #define TIM_CCMR2_OC3M_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11356 | #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 163:e59c8e839560 | 11357 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11358 | #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 11359 | #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11360 | #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11361 | #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11362 | |
| AnnaBridge | 163:e59c8e839560 | 11363 | #define TIM_CCMR2_OC3CE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11364 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11365 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11366 | |
| AnnaBridge | 163:e59c8e839560 | 11367 | #define TIM_CCMR2_CC4S_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11368 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 11369 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 11370 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11371 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11372 | |
| AnnaBridge | 163:e59c8e839560 | 11373 | #define TIM_CCMR2_OC4FE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11374 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11375 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11376 | #define TIM_CCMR2_OC4PE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11377 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11378 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11379 | |
| AnnaBridge | 163:e59c8e839560 | 11380 | #define TIM_CCMR2_OC4M_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11381 | #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 163:e59c8e839560 | 11382 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11383 | #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */ |
| AnnaBridge | 163:e59c8e839560 | 11384 | #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11385 | #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11386 | #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11387 | |
| AnnaBridge | 163:e59c8e839560 | 11388 | #define TIM_CCMR2_OC4CE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11389 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11390 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11391 | |
| AnnaBridge | 163:e59c8e839560 | 11392 | /*----------------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 11393 | |
| AnnaBridge | 163:e59c8e839560 | 11394 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11395 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 163:e59c8e839560 | 11396 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11397 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11398 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11399 | |
| AnnaBridge | 163:e59c8e839560 | 11400 | #define TIM_CCMR2_IC3F_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11401 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 163:e59c8e839560 | 11402 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| AnnaBridge | 163:e59c8e839560 | 11403 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11404 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11405 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11406 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11407 | |
| AnnaBridge | 163:e59c8e839560 | 11408 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11409 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 163:e59c8e839560 | 11410 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11411 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11412 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11413 | |
| AnnaBridge | 163:e59c8e839560 | 11414 | #define TIM_CCMR2_IC4F_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11415 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 163:e59c8e839560 | 11416 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| AnnaBridge | 163:e59c8e839560 | 11417 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11418 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11419 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11420 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11421 | |
| AnnaBridge | 163:e59c8e839560 | 11422 | /******************* Bit definition for TIM_CCER register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11423 | #define TIM_CCER_CC1E_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11424 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11425 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11426 | #define TIM_CCER_CC1P_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11427 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11428 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11429 | #define TIM_CCER_CC1NE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11430 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11431 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11432 | #define TIM_CCER_CC1NP_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11433 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11434 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11435 | #define TIM_CCER_CC2E_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11436 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11437 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11438 | #define TIM_CCER_CC2P_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11439 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11440 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11441 | #define TIM_CCER_CC2NE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11442 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11443 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11444 | #define TIM_CCER_CC2NP_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11445 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11446 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11447 | #define TIM_CCER_CC3E_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11448 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11449 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11450 | #define TIM_CCER_CC3P_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11451 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11452 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11453 | #define TIM_CCER_CC3NE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11454 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11455 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11456 | #define TIM_CCER_CC3NP_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11457 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11458 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11459 | #define TIM_CCER_CC4E_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11460 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11461 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11462 | #define TIM_CCER_CC4P_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11463 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11464 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11465 | #define TIM_CCER_CC4NP_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11466 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11467 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11468 | #define TIM_CCER_CC5E_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11469 | #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11470 | #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11471 | #define TIM_CCER_CC5P_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 11472 | #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 11473 | #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11474 | #define TIM_CCER_CC6E_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 11475 | #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 11476 | #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11477 | #define TIM_CCER_CC6P_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 11478 | #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 11479 | #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11480 | |
| AnnaBridge | 163:e59c8e839560 | 11481 | /******************* Bit definition for TIM_CNT register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11482 | #define TIM_CNT_CNT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11483 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11484 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
| AnnaBridge | 163:e59c8e839560 | 11485 | #define TIM_CNT_UIFCPY_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 11486 | #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11487 | #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */ |
| AnnaBridge | 163:e59c8e839560 | 11488 | |
| AnnaBridge | 163:e59c8e839560 | 11489 | /******************* Bit definition for TIM_PSC register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11490 | #define TIM_PSC_PSC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11491 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11492 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
| AnnaBridge | 163:e59c8e839560 | 11493 | |
| AnnaBridge | 163:e59c8e839560 | 11494 | /******************* Bit definition for TIM_ARR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11495 | #define TIM_ARR_ARR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11496 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11497 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
| AnnaBridge | 163:e59c8e839560 | 11498 | |
| AnnaBridge | 163:e59c8e839560 | 11499 | /******************* Bit definition for TIM_RCR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11500 | #define TIM_RCR_REP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11501 | #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11502 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
| AnnaBridge | 163:e59c8e839560 | 11503 | |
| AnnaBridge | 163:e59c8e839560 | 11504 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11505 | #define TIM_CCR1_CCR1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11506 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11507 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11508 | |
| AnnaBridge | 163:e59c8e839560 | 11509 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11510 | #define TIM_CCR2_CCR2_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11511 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11512 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11513 | |
| AnnaBridge | 163:e59c8e839560 | 11514 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11515 | #define TIM_CCR3_CCR3_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11516 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11517 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11518 | |
| AnnaBridge | 163:e59c8e839560 | 11519 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11520 | #define TIM_CCR4_CCR4_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11521 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11522 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11523 | |
| AnnaBridge | 163:e59c8e839560 | 11524 | /******************* Bit definition for TIM_CCR5 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11525 | #define TIM_CCR5_CCR5_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11526 | #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11527 | #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11528 | #define TIM_CCR5_GC5C1_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 11529 | #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11530 | #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ |
| AnnaBridge | 163:e59c8e839560 | 11531 | #define TIM_CCR5_GC5C2_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 11532 | #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11533 | #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ |
| AnnaBridge | 163:e59c8e839560 | 11534 | #define TIM_CCR5_GC5C3_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 11535 | #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11536 | #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ |
| AnnaBridge | 163:e59c8e839560 | 11537 | |
| AnnaBridge | 163:e59c8e839560 | 11538 | /******************* Bit definition for TIM_CCR6 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11539 | #define TIM_CCR6_CCR6_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11540 | #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11541 | #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ |
| AnnaBridge | 163:e59c8e839560 | 11542 | |
| AnnaBridge | 163:e59c8e839560 | 11543 | /******************* Bit definition for TIM_BDTR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11544 | #define TIM_BDTR_DTG_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11545 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 11546 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| AnnaBridge | 163:e59c8e839560 | 11547 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11548 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11549 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11550 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11551 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11552 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11553 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11554 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11555 | |
| AnnaBridge | 163:e59c8e839560 | 11556 | #define TIM_BDTR_LOCK_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11557 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 163:e59c8e839560 | 11558 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
| AnnaBridge | 163:e59c8e839560 | 11559 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11560 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11561 | |
| AnnaBridge | 163:e59c8e839560 | 11562 | #define TIM_BDTR_OSSI_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11563 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11564 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
| AnnaBridge | 163:e59c8e839560 | 11565 | #define TIM_BDTR_OSSR_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11566 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11567 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
| AnnaBridge | 163:e59c8e839560 | 11568 | #define TIM_BDTR_BKE_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11569 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11570 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */ |
| AnnaBridge | 163:e59c8e839560 | 11571 | #define TIM_BDTR_BKP_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11572 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11573 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */ |
| AnnaBridge | 163:e59c8e839560 | 11574 | #define TIM_BDTR_AOE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11575 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11576 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11577 | #define TIM_BDTR_MOE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11578 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11579 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
| AnnaBridge | 163:e59c8e839560 | 11580 | |
| AnnaBridge | 163:e59c8e839560 | 11581 | #define TIM_BDTR_BKF_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11582 | #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 11583 | #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */ |
| AnnaBridge | 163:e59c8e839560 | 11584 | #define TIM_BDTR_BK2F_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 11585 | #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 163:e59c8e839560 | 11586 | #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */ |
| AnnaBridge | 163:e59c8e839560 | 11587 | |
| AnnaBridge | 163:e59c8e839560 | 11588 | #define TIM_BDTR_BK2E_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 11589 | #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11590 | #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */ |
| AnnaBridge | 163:e59c8e839560 | 11591 | #define TIM_BDTR_BK2P_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 11592 | #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11593 | #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */ |
| AnnaBridge | 163:e59c8e839560 | 11594 | |
| AnnaBridge | 163:e59c8e839560 | 11595 | /******************* Bit definition for TIM_DCR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11596 | #define TIM_DCR_DBA_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11597 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 163:e59c8e839560 | 11598 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
| AnnaBridge | 163:e59c8e839560 | 11599 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11600 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11601 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11602 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11603 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11604 | |
| AnnaBridge | 163:e59c8e839560 | 11605 | #define TIM_DCR_DBL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11606 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 163:e59c8e839560 | 11607 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
| AnnaBridge | 163:e59c8e839560 | 11608 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11609 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11610 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11611 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11612 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11613 | |
| AnnaBridge | 163:e59c8e839560 | 11614 | /******************* Bit definition for TIM_DMAR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11615 | #define TIM_DMAR_DMAB_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11616 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 163:e59c8e839560 | 11617 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
| AnnaBridge | 163:e59c8e839560 | 11618 | |
| AnnaBridge | 163:e59c8e839560 | 11619 | /******************* Bit definition for TIM16_OR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 11620 | #define TIM16_OR_TI1_RMP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11621 | #define TIM16_OR_TI1_RMP_Msk (0x3U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 163:e59c8e839560 | 11622 | #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ |
| AnnaBridge | 163:e59c8e839560 | 11623 | #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11624 | #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11625 | |
| AnnaBridge | 163:e59c8e839560 | 11626 | /******************* Bit definition for TIM1_OR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 11627 | #define TIM1_OR_ETR_RMP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11628 | #define TIM1_OR_ETR_RMP_Msk (0xFU << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 11629 | #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ |
| AnnaBridge | 163:e59c8e839560 | 11630 | #define TIM1_OR_ETR_RMP_0 (0x1U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11631 | #define TIM1_OR_ETR_RMP_1 (0x2U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11632 | #define TIM1_OR_ETR_RMP_2 (0x4U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11633 | #define TIM1_OR_ETR_RMP_3 (0x8U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11634 | |
| AnnaBridge | 163:e59c8e839560 | 11635 | /******************* Bit definition for TIM8_OR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 11636 | #define TIM8_OR_ETR_RMP_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11637 | #define TIM8_OR_ETR_RMP_Msk (0xFU << TIM8_OR_ETR_RMP_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 11638 | #define TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */ |
| AnnaBridge | 163:e59c8e839560 | 11639 | #define TIM8_OR_ETR_RMP_0 (0x1U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11640 | #define TIM8_OR_ETR_RMP_1 (0x2U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11641 | #define TIM8_OR_ETR_RMP_2 (0x4U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11642 | #define TIM8_OR_ETR_RMP_3 (0x8U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11643 | |
| AnnaBridge | 163:e59c8e839560 | 11644 | /****************** Bit definition for TIM_CCMR3 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 11645 | #define TIM_CCMR3_OC5FE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11646 | #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11647 | #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11648 | #define TIM_CCMR3_OC5PE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11649 | #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11650 | #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11651 | |
| AnnaBridge | 163:e59c8e839560 | 11652 | #define TIM_CCMR3_OC5M_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11653 | #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 163:e59c8e839560 | 11654 | #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11655 | #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11656 | #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11657 | #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11658 | #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11659 | |
| AnnaBridge | 163:e59c8e839560 | 11660 | #define TIM_CCMR3_OC5CE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11661 | #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11662 | #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11663 | |
| AnnaBridge | 163:e59c8e839560 | 11664 | #define TIM_CCMR3_OC6FE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11665 | #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11666 | #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ |
| AnnaBridge | 163:e59c8e839560 | 11667 | #define TIM_CCMR3_OC6PE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11668 | #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11669 | #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ |
| AnnaBridge | 163:e59c8e839560 | 11670 | |
| AnnaBridge | 163:e59c8e839560 | 11671 | #define TIM_CCMR3_OC6M_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11672 | #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 163:e59c8e839560 | 11673 | #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 11674 | #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11675 | #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11676 | #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11677 | #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11678 | |
| AnnaBridge | 163:e59c8e839560 | 11679 | #define TIM_CCMR3_OC6CE_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11680 | #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11681 | #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11682 | |
| AnnaBridge | 163:e59c8e839560 | 11683 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 11684 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 11685 | /* Touch Sensing Controller (TSC) */ |
| AnnaBridge | 163:e59c8e839560 | 11686 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 11687 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 11688 | /******************* Bit definition for TSC_CR register *********************/ |
| AnnaBridge | 163:e59c8e839560 | 11689 | #define TSC_CR_TSCE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11690 | #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11691 | #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ |
| AnnaBridge | 163:e59c8e839560 | 11692 | #define TSC_CR_START_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11693 | #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11694 | #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ |
| AnnaBridge | 163:e59c8e839560 | 11695 | #define TSC_CR_AM_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11696 | #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11697 | #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ |
| AnnaBridge | 163:e59c8e839560 | 11698 | #define TSC_CR_SYNCPOL_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11699 | #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11700 | #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ |
| AnnaBridge | 163:e59c8e839560 | 11701 | #define TSC_CR_IODEF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11702 | #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11703 | #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ |
| AnnaBridge | 163:e59c8e839560 | 11704 | |
| AnnaBridge | 163:e59c8e839560 | 11705 | #define TSC_CR_MCV_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11706 | #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 163:e59c8e839560 | 11707 | #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ |
| AnnaBridge | 163:e59c8e839560 | 11708 | #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11709 | #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11710 | #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11711 | |
| AnnaBridge | 163:e59c8e839560 | 11712 | #define TSC_CR_PGPSC_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11713 | #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 163:e59c8e839560 | 11714 | #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ |
| AnnaBridge | 163:e59c8e839560 | 11715 | #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11716 | #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11717 | #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11718 | |
| AnnaBridge | 163:e59c8e839560 | 11719 | #define TSC_CR_SSPSC_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11720 | #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11721 | #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ |
| AnnaBridge | 163:e59c8e839560 | 11722 | #define TSC_CR_SSE_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11723 | #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11724 | #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ |
| AnnaBridge | 163:e59c8e839560 | 11725 | |
| AnnaBridge | 163:e59c8e839560 | 11726 | #define TSC_CR_SSD_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 11727 | #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ |
| AnnaBridge | 163:e59c8e839560 | 11728 | #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ |
| AnnaBridge | 163:e59c8e839560 | 11729 | #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 11730 | #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 11731 | #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 11732 | #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 11733 | #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 11734 | #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 11735 | #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 11736 | |
| AnnaBridge | 163:e59c8e839560 | 11737 | #define TSC_CR_CTPL_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 11738 | #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11739 | #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ |
| AnnaBridge | 163:e59c8e839560 | 11740 | #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11741 | #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11742 | #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11743 | #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11744 | |
| AnnaBridge | 163:e59c8e839560 | 11745 | #define TSC_CR_CTPH_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 11746 | #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11747 | #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ |
| AnnaBridge | 163:e59c8e839560 | 11748 | #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11749 | #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11750 | #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11751 | #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11752 | |
| AnnaBridge | 163:e59c8e839560 | 11753 | /******************* Bit definition for TSC_IER register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11754 | #define TSC_IER_EOAIE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11755 | #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11756 | #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11757 | #define TSC_IER_MCEIE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11758 | #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11759 | #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 11760 | |
| AnnaBridge | 163:e59c8e839560 | 11761 | /******************* Bit definition for TSC_ICR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11762 | #define TSC_ICR_EOAIC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11763 | #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11764 | #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 11765 | #define TSC_ICR_MCEIC_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11766 | #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11767 | #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ |
| AnnaBridge | 163:e59c8e839560 | 11768 | |
| AnnaBridge | 163:e59c8e839560 | 11769 | /******************* Bit definition for TSC_ISR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 11770 | #define TSC_ISR_EOAF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11771 | #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11772 | #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ |
| AnnaBridge | 163:e59c8e839560 | 11773 | #define TSC_ISR_MCEF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11774 | #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11775 | #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ |
| AnnaBridge | 163:e59c8e839560 | 11776 | |
| AnnaBridge | 163:e59c8e839560 | 11777 | /******************* Bit definition for TSC_IOHCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 11778 | #define TSC_IOHCR_G1_IO1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11779 | #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11780 | #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11781 | #define TSC_IOHCR_G1_IO2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11782 | #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11783 | #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11784 | #define TSC_IOHCR_G1_IO3_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11785 | #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11786 | #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11787 | #define TSC_IOHCR_G1_IO4_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11788 | #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11789 | #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11790 | #define TSC_IOHCR_G2_IO1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11791 | #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11792 | #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11793 | #define TSC_IOHCR_G2_IO2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11794 | #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11795 | #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11796 | #define TSC_IOHCR_G2_IO3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11797 | #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11798 | #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11799 | #define TSC_IOHCR_G2_IO4_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11800 | #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11801 | #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11802 | #define TSC_IOHCR_G3_IO1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11803 | #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11804 | #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11805 | #define TSC_IOHCR_G3_IO2_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11806 | #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11807 | #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11808 | #define TSC_IOHCR_G3_IO3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11809 | #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11810 | #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11811 | #define TSC_IOHCR_G3_IO4_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11812 | #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11813 | #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11814 | #define TSC_IOHCR_G4_IO1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11815 | #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11816 | #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11817 | #define TSC_IOHCR_G4_IO2_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11818 | #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11819 | #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11820 | #define TSC_IOHCR_G4_IO3_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11821 | #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11822 | #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11823 | #define TSC_IOHCR_G4_IO4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11824 | #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11825 | #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11826 | #define TSC_IOHCR_G5_IO1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11827 | #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11828 | #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11829 | #define TSC_IOHCR_G5_IO2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 11830 | #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 11831 | #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11832 | #define TSC_IOHCR_G5_IO3_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 11833 | #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 11834 | #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11835 | #define TSC_IOHCR_G5_IO4_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 11836 | #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 11837 | #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11838 | #define TSC_IOHCR_G6_IO1_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 11839 | #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 11840 | #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11841 | #define TSC_IOHCR_G6_IO2_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 11842 | #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 11843 | #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11844 | #define TSC_IOHCR_G6_IO3_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 11845 | #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 11846 | #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11847 | #define TSC_IOHCR_G6_IO4_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 11848 | #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 11849 | #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11850 | #define TSC_IOHCR_G7_IO1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 11851 | #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11852 | #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11853 | #define TSC_IOHCR_G7_IO2_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 11854 | #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11855 | #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11856 | #define TSC_IOHCR_G7_IO3_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 11857 | #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11858 | #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11859 | #define TSC_IOHCR_G7_IO4_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 11860 | #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11861 | #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11862 | #define TSC_IOHCR_G8_IO1_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 11863 | #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11864 | #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11865 | #define TSC_IOHCR_G8_IO2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 11866 | #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11867 | #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11868 | #define TSC_IOHCR_G8_IO3_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 11869 | #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11870 | #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11871 | #define TSC_IOHCR_G8_IO4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 11872 | #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11873 | #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 163:e59c8e839560 | 11874 | |
| AnnaBridge | 163:e59c8e839560 | 11875 | /******************* Bit definition for TSC_IOASCR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 11876 | #define TSC_IOASCR_G1_IO1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11877 | #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11878 | #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11879 | #define TSC_IOASCR_G1_IO2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11880 | #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11881 | #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11882 | #define TSC_IOASCR_G1_IO3_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11883 | #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11884 | #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11885 | #define TSC_IOASCR_G1_IO4_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11886 | #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11887 | #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11888 | #define TSC_IOASCR_G2_IO1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11889 | #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11890 | #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11891 | #define TSC_IOASCR_G2_IO2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11892 | #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11893 | #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11894 | #define TSC_IOASCR_G2_IO3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11895 | #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11896 | #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11897 | #define TSC_IOASCR_G2_IO4_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11898 | #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11899 | #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11900 | #define TSC_IOASCR_G3_IO1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11901 | #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 11902 | #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11903 | #define TSC_IOASCR_G3_IO2_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 11904 | #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 11905 | #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11906 | #define TSC_IOASCR_G3_IO3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 11907 | #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 11908 | #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11909 | #define TSC_IOASCR_G3_IO4_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 11910 | #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 11911 | #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11912 | #define TSC_IOASCR_G4_IO1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 11913 | #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 11914 | #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11915 | #define TSC_IOASCR_G4_IO2_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 11916 | #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 11917 | #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11918 | #define TSC_IOASCR_G4_IO3_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 11919 | #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 11920 | #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11921 | #define TSC_IOASCR_G4_IO4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 11922 | #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 11923 | #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11924 | #define TSC_IOASCR_G5_IO1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 11925 | #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 11926 | #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11927 | #define TSC_IOASCR_G5_IO2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 11928 | #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 11929 | #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11930 | #define TSC_IOASCR_G5_IO3_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 11931 | #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 11932 | #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11933 | #define TSC_IOASCR_G5_IO4_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 11934 | #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 11935 | #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11936 | #define TSC_IOASCR_G6_IO1_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 11937 | #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 11938 | #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11939 | #define TSC_IOASCR_G6_IO2_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 11940 | #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 11941 | #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11942 | #define TSC_IOASCR_G6_IO3_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 11943 | #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 11944 | #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11945 | #define TSC_IOASCR_G6_IO4_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 11946 | #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 11947 | #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11948 | #define TSC_IOASCR_G7_IO1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 11949 | #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11950 | #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11951 | #define TSC_IOASCR_G7_IO2_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 11952 | #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11953 | #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11954 | #define TSC_IOASCR_G7_IO3_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 11955 | #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11956 | #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11957 | #define TSC_IOASCR_G7_IO4_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 11958 | #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11959 | #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11960 | #define TSC_IOASCR_G8_IO1_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 11961 | #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11962 | #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11963 | #define TSC_IOASCR_G8_IO2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 11964 | #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11965 | #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11966 | #define TSC_IOASCR_G8_IO3_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 11967 | #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11968 | #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11969 | #define TSC_IOASCR_G8_IO4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 11970 | #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 11971 | #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ |
| AnnaBridge | 163:e59c8e839560 | 11972 | |
| AnnaBridge | 163:e59c8e839560 | 11973 | /******************* Bit definition for TSC_IOSCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 11974 | #define TSC_IOSCR_G1_IO1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 11975 | #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 11976 | #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11977 | #define TSC_IOSCR_G1_IO2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 11978 | #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 11979 | #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11980 | #define TSC_IOSCR_G1_IO3_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 11981 | #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 11982 | #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11983 | #define TSC_IOSCR_G1_IO4_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 11984 | #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 11985 | #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11986 | #define TSC_IOSCR_G2_IO1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 11987 | #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 11988 | #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11989 | #define TSC_IOSCR_G2_IO2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 11990 | #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 11991 | #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11992 | #define TSC_IOSCR_G2_IO3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 11993 | #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 11994 | #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11995 | #define TSC_IOSCR_G2_IO4_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 11996 | #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 11997 | #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 11998 | #define TSC_IOSCR_G3_IO1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 11999 | #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12000 | #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12001 | #define TSC_IOSCR_G3_IO2_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12002 | #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12003 | #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12004 | #define TSC_IOSCR_G3_IO3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12005 | #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12006 | #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12007 | #define TSC_IOSCR_G3_IO4_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12008 | #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12009 | #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12010 | #define TSC_IOSCR_G4_IO1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12011 | #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12012 | #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12013 | #define TSC_IOSCR_G4_IO2_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 12014 | #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 12015 | #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12016 | #define TSC_IOSCR_G4_IO3_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12017 | #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12018 | #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12019 | #define TSC_IOSCR_G4_IO4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12020 | #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12021 | #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12022 | #define TSC_IOSCR_G5_IO1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12023 | #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12024 | #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12025 | #define TSC_IOSCR_G5_IO2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12026 | #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12027 | #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12028 | #define TSC_IOSCR_G5_IO3_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 12029 | #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12030 | #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12031 | #define TSC_IOSCR_G5_IO4_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 12032 | #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12033 | #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12034 | #define TSC_IOSCR_G6_IO1_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12035 | #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12036 | #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12037 | #define TSC_IOSCR_G6_IO2_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12038 | #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12039 | #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12040 | #define TSC_IOSCR_G6_IO3_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 12041 | #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12042 | #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12043 | #define TSC_IOSCR_G6_IO4_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 12044 | #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 12045 | #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12046 | #define TSC_IOSCR_G7_IO1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 12047 | #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12048 | #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12049 | #define TSC_IOSCR_G7_IO2_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 12050 | #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12051 | #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12052 | #define TSC_IOSCR_G7_IO3_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 12053 | #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12054 | #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12055 | #define TSC_IOSCR_G7_IO4_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 12056 | #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12057 | #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12058 | #define TSC_IOSCR_G8_IO1_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 12059 | #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12060 | #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12061 | #define TSC_IOSCR_G8_IO2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 12062 | #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12063 | #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12064 | #define TSC_IOSCR_G8_IO3_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 12065 | #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12066 | #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12067 | #define TSC_IOSCR_G8_IO4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 12068 | #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12069 | #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ |
| AnnaBridge | 163:e59c8e839560 | 12070 | |
| AnnaBridge | 163:e59c8e839560 | 12071 | /******************* Bit definition for TSC_IOCCR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12072 | #define TSC_IOCCR_G1_IO1_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12073 | #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12074 | #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12075 | #define TSC_IOCCR_G1_IO2_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12076 | #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12077 | #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12078 | #define TSC_IOCCR_G1_IO3_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12079 | #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12080 | #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12081 | #define TSC_IOCCR_G1_IO4_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12082 | #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12083 | #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12084 | #define TSC_IOCCR_G2_IO1_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12085 | #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12086 | #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12087 | #define TSC_IOCCR_G2_IO2_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12088 | #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12089 | #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12090 | #define TSC_IOCCR_G2_IO3_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12091 | #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12092 | #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12093 | #define TSC_IOCCR_G2_IO4_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12094 | #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12095 | #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12096 | #define TSC_IOCCR_G3_IO1_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12097 | #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12098 | #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12099 | #define TSC_IOCCR_G3_IO2_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12100 | #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12101 | #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12102 | #define TSC_IOCCR_G3_IO3_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12103 | #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12104 | #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12105 | #define TSC_IOCCR_G3_IO4_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12106 | #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12107 | #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12108 | #define TSC_IOCCR_G4_IO1_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12109 | #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12110 | #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12111 | #define TSC_IOCCR_G4_IO2_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 12112 | #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 12113 | #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12114 | #define TSC_IOCCR_G4_IO3_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12115 | #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12116 | #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12117 | #define TSC_IOCCR_G4_IO4_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12118 | #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12119 | #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12120 | #define TSC_IOCCR_G5_IO1_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12121 | #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12122 | #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12123 | #define TSC_IOCCR_G5_IO2_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12124 | #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12125 | #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12126 | #define TSC_IOCCR_G5_IO3_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 12127 | #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12128 | #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12129 | #define TSC_IOCCR_G5_IO4_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 12130 | #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12131 | #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12132 | #define TSC_IOCCR_G6_IO1_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12133 | #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12134 | #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12135 | #define TSC_IOCCR_G6_IO2_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12136 | #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12137 | #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12138 | #define TSC_IOCCR_G6_IO3_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 12139 | #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12140 | #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12141 | #define TSC_IOCCR_G6_IO4_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 12142 | #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 12143 | #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12144 | #define TSC_IOCCR_G7_IO1_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 12145 | #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12146 | #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12147 | #define TSC_IOCCR_G7_IO2_Pos (25U) |
| AnnaBridge | 163:e59c8e839560 | 12148 | #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12149 | #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12150 | #define TSC_IOCCR_G7_IO3_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 12151 | #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12152 | #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12153 | #define TSC_IOCCR_G7_IO4_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 12154 | #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12155 | #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12156 | #define TSC_IOCCR_G8_IO1_Pos (28U) |
| AnnaBridge | 163:e59c8e839560 | 12157 | #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12158 | #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12159 | #define TSC_IOCCR_G8_IO2_Pos (29U) |
| AnnaBridge | 163:e59c8e839560 | 12160 | #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12161 | #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12162 | #define TSC_IOCCR_G8_IO3_Pos (30U) |
| AnnaBridge | 163:e59c8e839560 | 12163 | #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12164 | #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12165 | #define TSC_IOCCR_G8_IO4_Pos (31U) |
| AnnaBridge | 163:e59c8e839560 | 12166 | #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12167 | #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ |
| AnnaBridge | 163:e59c8e839560 | 12168 | |
| AnnaBridge | 163:e59c8e839560 | 12169 | /******************* Bit definition for TSC_IOGCSR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 12170 | #define TSC_IOGCSR_G1E_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12171 | #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12172 | #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12173 | #define TSC_IOGCSR_G2E_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12174 | #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12175 | #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12176 | #define TSC_IOGCSR_G3E_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12177 | #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12178 | #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12179 | #define TSC_IOGCSR_G4E_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12180 | #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12181 | #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12182 | #define TSC_IOGCSR_G5E_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12183 | #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12184 | #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12185 | #define TSC_IOGCSR_G6E_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12186 | #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12187 | #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12188 | #define TSC_IOGCSR_G7E_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12189 | #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12190 | #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12191 | #define TSC_IOGCSR_G8E_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12192 | #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12193 | #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ |
| AnnaBridge | 163:e59c8e839560 | 12194 | #define TSC_IOGCSR_G1S_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12195 | #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12196 | #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ |
| AnnaBridge | 163:e59c8e839560 | 12197 | #define TSC_IOGCSR_G2S_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12198 | #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12199 | #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ |
| AnnaBridge | 163:e59c8e839560 | 12200 | #define TSC_IOGCSR_G3S_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 12201 | #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12202 | #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ |
| AnnaBridge | 163:e59c8e839560 | 12203 | #define TSC_IOGCSR_G4S_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 12204 | #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12205 | #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ |
| AnnaBridge | 163:e59c8e839560 | 12206 | #define TSC_IOGCSR_G5S_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12207 | #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12208 | #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ |
| AnnaBridge | 163:e59c8e839560 | 12209 | #define TSC_IOGCSR_G6S_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12210 | #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12211 | #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ |
| AnnaBridge | 163:e59c8e839560 | 12212 | #define TSC_IOGCSR_G7S_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 12213 | #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12214 | #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ |
| AnnaBridge | 163:e59c8e839560 | 12215 | #define TSC_IOGCSR_G8S_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 12216 | #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 12217 | #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ |
| AnnaBridge | 163:e59c8e839560 | 12218 | |
| AnnaBridge | 163:e59c8e839560 | 12219 | /******************* Bit definition for TSC_IOGXCR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 12220 | #define TSC_IOGXCR_CNT_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12221 | #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 163:e59c8e839560 | 12222 | #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ |
| AnnaBridge | 163:e59c8e839560 | 12223 | |
| AnnaBridge | 163:e59c8e839560 | 12224 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12225 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12226 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ |
| AnnaBridge | 163:e59c8e839560 | 12227 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12228 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12229 | /****************** Bit definition for USART_CR1 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12230 | #define USART_CR1_UE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12231 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12232 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12233 | #define USART_CR1_UESM_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12234 | #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12235 | #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ |
| AnnaBridge | 163:e59c8e839560 | 12236 | #define USART_CR1_RE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12237 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12238 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12239 | #define USART_CR1_TE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12240 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12241 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12242 | #define USART_CR1_IDLEIE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12243 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12244 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12245 | #define USART_CR1_RXNEIE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12246 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12247 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12248 | #define USART_CR1_TCIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12249 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12250 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12251 | #define USART_CR1_TXEIE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12252 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12253 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12254 | #define USART_CR1_PEIE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12255 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12256 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12257 | #define USART_CR1_PS_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12258 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12259 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
| AnnaBridge | 163:e59c8e839560 | 12260 | #define USART_CR1_PCE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12261 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12262 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12263 | #define USART_CR1_WAKE_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12264 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12265 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ |
| AnnaBridge | 163:e59c8e839560 | 12266 | #define USART_CR1_M_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12267 | #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12268 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
| AnnaBridge | 163:e59c8e839560 | 12269 | #define USART_CR1_M0_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12270 | #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12271 | #define USART_CR1_M0 USART_CR1_M0_Msk /*!< SmartCard Word length */ |
| AnnaBridge | 163:e59c8e839560 | 12272 | #define USART_CR1_MME_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 12273 | #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 12274 | #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12275 | #define USART_CR1_CMIE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12276 | #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12277 | #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 12278 | #define USART_CR1_OVER8_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12279 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12280 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ |
| AnnaBridge | 163:e59c8e839560 | 12281 | #define USART_CR1_DEDT_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12282 | #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 163:e59c8e839560 | 12283 | #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ |
| AnnaBridge | 163:e59c8e839560 | 12284 | #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12285 | #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12286 | #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12287 | #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12288 | #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12289 | #define USART_CR1_DEAT_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12290 | #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ |
| AnnaBridge | 163:e59c8e839560 | 12291 | #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ |
| AnnaBridge | 163:e59c8e839560 | 12292 | #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12293 | #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12294 | #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 12295 | #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12296 | #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12297 | #define USART_CR1_RTOIE_Pos (26U) |
| AnnaBridge | 163:e59c8e839560 | 12298 | #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12299 | #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 12300 | #define USART_CR1_EOBIE_Pos (27U) |
| AnnaBridge | 163:e59c8e839560 | 12301 | #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12302 | #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 12303 | |
| AnnaBridge | 163:e59c8e839560 | 12304 | /****************** Bit definition for USART_CR2 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12305 | #define USART_CR2_ADDM7_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12306 | #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12307 | #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ |
| AnnaBridge | 163:e59c8e839560 | 12308 | #define USART_CR2_LBDL_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12309 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12310 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
| AnnaBridge | 163:e59c8e839560 | 12311 | #define USART_CR2_LBDIE_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12312 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12313 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12314 | #define USART_CR2_LBCL_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12315 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12316 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
| AnnaBridge | 163:e59c8e839560 | 12317 | #define USART_CR2_CPHA_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12318 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12319 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
| AnnaBridge | 163:e59c8e839560 | 12320 | #define USART_CR2_CPOL_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12321 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12322 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
| AnnaBridge | 163:e59c8e839560 | 12323 | #define USART_CR2_CLKEN_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12324 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12325 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12326 | #define USART_CR2_STOP_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12327 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 163:e59c8e839560 | 12328 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
| AnnaBridge | 163:e59c8e839560 | 12329 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12330 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 12331 | #define USART_CR2_LINEN_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12332 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12333 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 12334 | #define USART_CR2_SWAP_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12335 | #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12336 | #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ |
| AnnaBridge | 163:e59c8e839560 | 12337 | #define USART_CR2_RXINV_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12338 | #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12339 | #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ |
| AnnaBridge | 163:e59c8e839560 | 12340 | #define USART_CR2_TXINV_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12341 | #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12342 | #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ |
| AnnaBridge | 163:e59c8e839560 | 12343 | #define USART_CR2_DATAINV_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 12344 | #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12345 | #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ |
| AnnaBridge | 163:e59c8e839560 | 12346 | #define USART_CR2_MSBFIRST_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 12347 | #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12348 | #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ |
| AnnaBridge | 163:e59c8e839560 | 12349 | #define USART_CR2_ABREN_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12350 | #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12351 | #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ |
| AnnaBridge | 163:e59c8e839560 | 12352 | #define USART_CR2_ABRMODE_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12353 | #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 163:e59c8e839560 | 12354 | #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ |
| AnnaBridge | 163:e59c8e839560 | 12355 | #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12356 | #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12357 | #define USART_CR2_RTOEN_Pos (23U) |
| AnnaBridge | 163:e59c8e839560 | 12358 | #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 163:e59c8e839560 | 12359 | #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ |
| AnnaBridge | 163:e59c8e839560 | 12360 | #define USART_CR2_ADD_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 12361 | #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12362 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
| AnnaBridge | 163:e59c8e839560 | 12363 | |
| AnnaBridge | 163:e59c8e839560 | 12364 | /****************** Bit definition for USART_CR3 register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12365 | #define USART_CR3_EIE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12366 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12367 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12368 | #define USART_CR3_IREN_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12369 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12370 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12371 | #define USART_CR3_IRLP_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12372 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12373 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
| AnnaBridge | 163:e59c8e839560 | 12374 | #define USART_CR3_HDSEL_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12375 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12376 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
| AnnaBridge | 163:e59c8e839560 | 12377 | #define USART_CR3_NACK_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12378 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12379 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ |
| AnnaBridge | 163:e59c8e839560 | 12380 | #define USART_CR3_SCEN_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12381 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12382 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ |
| AnnaBridge | 163:e59c8e839560 | 12383 | #define USART_CR3_DMAR_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12384 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12385 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
| AnnaBridge | 163:e59c8e839560 | 12386 | #define USART_CR3_DMAT_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12387 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12388 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
| AnnaBridge | 163:e59c8e839560 | 12389 | #define USART_CR3_RTSE_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12390 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12391 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12392 | #define USART_CR3_CTSE_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12393 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12394 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12395 | #define USART_CR3_CTSIE_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12396 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12397 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12398 | #define USART_CR3_ONEBIT_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12399 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12400 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ |
| AnnaBridge | 163:e59c8e839560 | 12401 | #define USART_CR3_OVRDIS_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12402 | #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12403 | #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ |
| AnnaBridge | 163:e59c8e839560 | 12404 | #define USART_CR3_DDRE_Pos (13U) |
| AnnaBridge | 163:e59c8e839560 | 12405 | #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 163:e59c8e839560 | 12406 | #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ |
| AnnaBridge | 163:e59c8e839560 | 12407 | #define USART_CR3_DEM_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12408 | #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12409 | #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ |
| AnnaBridge | 163:e59c8e839560 | 12410 | #define USART_CR3_DEP_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12411 | #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12412 | #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ |
| AnnaBridge | 163:e59c8e839560 | 12413 | #define USART_CR3_SCARCNT_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12414 | #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 163:e59c8e839560 | 12415 | #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ |
| AnnaBridge | 163:e59c8e839560 | 12416 | #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12417 | #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12418 | #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12419 | #define USART_CR3_WUS_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12420 | #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 163:e59c8e839560 | 12421 | #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ |
| AnnaBridge | 163:e59c8e839560 | 12422 | #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12423 | #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12424 | #define USART_CR3_WUFIE_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 12425 | #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12426 | #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 12427 | |
| AnnaBridge | 163:e59c8e839560 | 12428 | /****************** Bit definition for USART_BRR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12429 | #define USART_BRR_DIV_FRACTION_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12430 | #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 163:e59c8e839560 | 12431 | #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ |
| AnnaBridge | 163:e59c8e839560 | 12432 | #define USART_BRR_DIV_MANTISSA_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12433 | #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 163:e59c8e839560 | 12434 | #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ |
| AnnaBridge | 163:e59c8e839560 | 12435 | |
| AnnaBridge | 163:e59c8e839560 | 12436 | /****************** Bit definition for USART_GTPR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12437 | #define USART_GTPR_PSC_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12438 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 163:e59c8e839560 | 12439 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
| AnnaBridge | 163:e59c8e839560 | 12440 | #define USART_GTPR_GT_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12441 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 163:e59c8e839560 | 12442 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ |
| AnnaBridge | 163:e59c8e839560 | 12443 | |
| AnnaBridge | 163:e59c8e839560 | 12444 | |
| AnnaBridge | 163:e59c8e839560 | 12445 | /******************* Bit definition for USART_RTOR register *****************/ |
| AnnaBridge | 163:e59c8e839560 | 12446 | #define USART_RTOR_RTO_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12447 | #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ |
| AnnaBridge | 163:e59c8e839560 | 12448 | #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ |
| AnnaBridge | 163:e59c8e839560 | 12449 | #define USART_RTOR_BLEN_Pos (24U) |
| AnnaBridge | 163:e59c8e839560 | 12450 | #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 163:e59c8e839560 | 12451 | #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ |
| AnnaBridge | 163:e59c8e839560 | 12452 | |
| AnnaBridge | 163:e59c8e839560 | 12453 | /******************* Bit definition for USART_RQR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12454 | #define USART_RQR_ABRRQ_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12455 | #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12456 | #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ |
| AnnaBridge | 163:e59c8e839560 | 12457 | #define USART_RQR_SBKRQ_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12458 | #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12459 | #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ |
| AnnaBridge | 163:e59c8e839560 | 12460 | #define USART_RQR_MMRQ_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12461 | #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12462 | #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ |
| AnnaBridge | 163:e59c8e839560 | 12463 | #define USART_RQR_RXFRQ_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12464 | #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12465 | #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ |
| AnnaBridge | 163:e59c8e839560 | 12466 | #define USART_RQR_TXFRQ_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12467 | #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12468 | #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ |
| AnnaBridge | 163:e59c8e839560 | 12469 | |
| AnnaBridge | 163:e59c8e839560 | 12470 | /******************* Bit definition for USART_ISR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12471 | #define USART_ISR_PE_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12472 | #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12473 | #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ |
| AnnaBridge | 163:e59c8e839560 | 12474 | #define USART_ISR_FE_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12475 | #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12476 | #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ |
| AnnaBridge | 163:e59c8e839560 | 12477 | #define USART_ISR_NE_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12478 | #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12479 | #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12480 | #define USART_ISR_ORE_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12481 | #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12482 | #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ |
| AnnaBridge | 163:e59c8e839560 | 12483 | #define USART_ISR_IDLE_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12484 | #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12485 | #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ |
| AnnaBridge | 163:e59c8e839560 | 12486 | #define USART_ISR_RXNE_Pos (5U) |
| AnnaBridge | 163:e59c8e839560 | 12487 | #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12488 | #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ |
| AnnaBridge | 163:e59c8e839560 | 12489 | #define USART_ISR_TC_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12490 | #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12491 | #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ |
| AnnaBridge | 163:e59c8e839560 | 12492 | #define USART_ISR_TXE_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12493 | #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12494 | #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ |
| AnnaBridge | 163:e59c8e839560 | 12495 | #define USART_ISR_LBDF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12496 | #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12497 | #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12498 | #define USART_ISR_CTSIF_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12499 | #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12500 | #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ |
| AnnaBridge | 163:e59c8e839560 | 12501 | #define USART_ISR_CTS_Pos (10U) |
| AnnaBridge | 163:e59c8e839560 | 12502 | #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 163:e59c8e839560 | 12503 | #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ |
| AnnaBridge | 163:e59c8e839560 | 12504 | #define USART_ISR_RTOF_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12505 | #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12506 | #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ |
| AnnaBridge | 163:e59c8e839560 | 12507 | #define USART_ISR_EOBF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12508 | #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12509 | #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12510 | #define USART_ISR_ABRE_Pos (14U) |
| AnnaBridge | 163:e59c8e839560 | 12511 | #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 163:e59c8e839560 | 12512 | #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ |
| AnnaBridge | 163:e59c8e839560 | 12513 | #define USART_ISR_ABRF_Pos (15U) |
| AnnaBridge | 163:e59c8e839560 | 12514 | #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 163:e59c8e839560 | 12515 | #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12516 | #define USART_ISR_BUSY_Pos (16U) |
| AnnaBridge | 163:e59c8e839560 | 12517 | #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 163:e59c8e839560 | 12518 | #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12519 | #define USART_ISR_CMF_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12520 | #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12521 | #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12522 | #define USART_ISR_SBKF_Pos (18U) |
| AnnaBridge | 163:e59c8e839560 | 12523 | #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 163:e59c8e839560 | 12524 | #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12525 | #define USART_ISR_RWU_Pos (19U) |
| AnnaBridge | 163:e59c8e839560 | 12526 | #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 163:e59c8e839560 | 12527 | #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12528 | #define USART_ISR_WUF_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12529 | #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12530 | #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12531 | #define USART_ISR_TEACK_Pos (21U) |
| AnnaBridge | 163:e59c8e839560 | 12532 | #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 163:e59c8e839560 | 12533 | #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12534 | #define USART_ISR_REACK_Pos (22U) |
| AnnaBridge | 163:e59c8e839560 | 12535 | #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 163:e59c8e839560 | 12536 | #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12537 | |
| AnnaBridge | 163:e59c8e839560 | 12538 | /******************* Bit definition for USART_ICR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12539 | #define USART_ICR_PECF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12540 | #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12541 | #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12542 | #define USART_ICR_FECF_Pos (1U) |
| AnnaBridge | 163:e59c8e839560 | 12543 | #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12544 | #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12545 | #define USART_ICR_NCF_Pos (2U) |
| AnnaBridge | 163:e59c8e839560 | 12546 | #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12547 | #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12548 | #define USART_ICR_ORECF_Pos (3U) |
| AnnaBridge | 163:e59c8e839560 | 12549 | #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12550 | #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12551 | #define USART_ICR_IDLECF_Pos (4U) |
| AnnaBridge | 163:e59c8e839560 | 12552 | #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12553 | #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12554 | #define USART_ICR_TCCF_Pos (6U) |
| AnnaBridge | 163:e59c8e839560 | 12555 | #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12556 | #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12557 | #define USART_ICR_LBDCF_Pos (8U) |
| AnnaBridge | 163:e59c8e839560 | 12558 | #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12559 | #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12560 | #define USART_ICR_CTSCF_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12561 | #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12562 | #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12563 | #define USART_ICR_RTOCF_Pos (11U) |
| AnnaBridge | 163:e59c8e839560 | 12564 | #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 163:e59c8e839560 | 12565 | #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12566 | #define USART_ICR_EOBCF_Pos (12U) |
| AnnaBridge | 163:e59c8e839560 | 12567 | #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 163:e59c8e839560 | 12568 | #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12569 | #define USART_ICR_CMCF_Pos (17U) |
| AnnaBridge | 163:e59c8e839560 | 12570 | #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 163:e59c8e839560 | 12571 | #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12572 | #define USART_ICR_WUCF_Pos (20U) |
| AnnaBridge | 163:e59c8e839560 | 12573 | #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 163:e59c8e839560 | 12574 | #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12575 | |
| AnnaBridge | 163:e59c8e839560 | 12576 | /******************* Bit definition for USART_RDR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12577 | #define USART_RDR_RDR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12578 | #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 163:e59c8e839560 | 12579 | #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ |
| AnnaBridge | 163:e59c8e839560 | 12580 | |
| AnnaBridge | 163:e59c8e839560 | 12581 | /******************* Bit definition for USART_TDR register ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12582 | #define USART_TDR_TDR_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12583 | #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 163:e59c8e839560 | 12584 | #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ |
| AnnaBridge | 163:e59c8e839560 | 12585 | |
| AnnaBridge | 163:e59c8e839560 | 12586 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12587 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12588 | /* USB Device General registers */ |
| AnnaBridge | 163:e59c8e839560 | 12589 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12590 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12591 | #define USB_CNTR (USB_BASE + 0x40U) /*!< Control register */ |
| AnnaBridge | 163:e59c8e839560 | 12592 | #define USB_ISTR (USB_BASE + 0x44U) /*!< Interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 12593 | #define USB_FNR (USB_BASE + 0x48U) /*!< Frame number register */ |
| AnnaBridge | 163:e59c8e839560 | 12594 | #define USB_DADDR (USB_BASE + 0x4CU) /*!< Device address register */ |
| AnnaBridge | 163:e59c8e839560 | 12595 | #define USB_BTABLE (USB_BASE + 0x50U) /*!< Buffer Table address register */ |
| AnnaBridge | 163:e59c8e839560 | 12596 | |
| AnnaBridge | 163:e59c8e839560 | 12597 | /**************************** ISTR interrupt events *************************/ |
| AnnaBridge | 163:e59c8e839560 | 12598 | #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12599 | #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12600 | #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12601 | #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12602 | #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12603 | #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12604 | #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12605 | #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12606 | #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12607 | #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ |
| AnnaBridge | 163:e59c8e839560 | 12608 | |
| AnnaBridge | 163:e59c8e839560 | 12609 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12610 | #define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR |
| AnnaBridge | 163:e59c8e839560 | 12611 | |
| AnnaBridge | 163:e59c8e839560 | 12612 | #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ |
| AnnaBridge | 163:e59c8e839560 | 12613 | #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ |
| AnnaBridge | 163:e59c8e839560 | 12614 | #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ |
| AnnaBridge | 163:e59c8e839560 | 12615 | #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ |
| AnnaBridge | 163:e59c8e839560 | 12616 | #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ |
| AnnaBridge | 163:e59c8e839560 | 12617 | #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ |
| AnnaBridge | 163:e59c8e839560 | 12618 | #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ |
| AnnaBridge | 163:e59c8e839560 | 12619 | #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ |
| AnnaBridge | 163:e59c8e839560 | 12620 | |
| AnnaBridge | 163:e59c8e839560 | 12621 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12622 | #define USB_CLR_PMAOVRM USB_CLR_PMAOVR |
| AnnaBridge | 163:e59c8e839560 | 12623 | |
| AnnaBridge | 163:e59c8e839560 | 12624 | /************************* CNTR control register bits definitions ***********/ |
| AnnaBridge | 163:e59c8e839560 | 12625 | #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12626 | #define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12627 | #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12628 | #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12629 | #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12630 | #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12631 | #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12632 | #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12633 | #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ |
| AnnaBridge | 163:e59c8e839560 | 12634 | #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ |
| AnnaBridge | 163:e59c8e839560 | 12635 | #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ |
| AnnaBridge | 163:e59c8e839560 | 12636 | #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ |
| AnnaBridge | 163:e59c8e839560 | 12637 | #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ |
| AnnaBridge | 163:e59c8e839560 | 12638 | |
| AnnaBridge | 163:e59c8e839560 | 12639 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12640 | #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR |
| AnnaBridge | 163:e59c8e839560 | 12641 | #define USB_CNTR_LP_MODE USB_CNTR_LPMODE |
| AnnaBridge | 163:e59c8e839560 | 12642 | |
| AnnaBridge | 163:e59c8e839560 | 12643 | /******************** FNR Frame Number Register bit definitions ************/ |
| AnnaBridge | 163:e59c8e839560 | 12644 | #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ |
| AnnaBridge | 163:e59c8e839560 | 12645 | #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ |
| AnnaBridge | 163:e59c8e839560 | 12646 | #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ |
| AnnaBridge | 163:e59c8e839560 | 12647 | #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ |
| AnnaBridge | 163:e59c8e839560 | 12648 | #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ |
| AnnaBridge | 163:e59c8e839560 | 12649 | |
| AnnaBridge | 163:e59c8e839560 | 12650 | /******************** DADDR Device ADDRess bit definitions ****************/ |
| AnnaBridge | 163:e59c8e839560 | 12651 | #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ |
| AnnaBridge | 163:e59c8e839560 | 12652 | #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ |
| AnnaBridge | 163:e59c8e839560 | 12653 | |
| AnnaBridge | 163:e59c8e839560 | 12654 | /****************************** Endpoint register *************************/ |
| AnnaBridge | 163:e59c8e839560 | 12655 | #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12656 | #define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12657 | #define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12658 | #define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12659 | #define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12660 | #define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12661 | #define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12662 | #define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */ |
| AnnaBridge | 163:e59c8e839560 | 12663 | /* bit positions */ |
| AnnaBridge | 163:e59c8e839560 | 12664 | #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ |
| AnnaBridge | 163:e59c8e839560 | 12665 | #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ |
| AnnaBridge | 163:e59c8e839560 | 12666 | #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ |
| AnnaBridge | 163:e59c8e839560 | 12667 | #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ |
| AnnaBridge | 163:e59c8e839560 | 12668 | #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ |
| AnnaBridge | 163:e59c8e839560 | 12669 | #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ |
| AnnaBridge | 163:e59c8e839560 | 12670 | #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ |
| AnnaBridge | 163:e59c8e839560 | 12671 | #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ |
| AnnaBridge | 163:e59c8e839560 | 12672 | #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ |
| AnnaBridge | 163:e59c8e839560 | 12673 | #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ |
| AnnaBridge | 163:e59c8e839560 | 12674 | |
| AnnaBridge | 163:e59c8e839560 | 12675 | /* EndPoint REGister MASK (no toggle fields) */ |
| AnnaBridge | 163:e59c8e839560 | 12676 | #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| AnnaBridge | 163:e59c8e839560 | 12677 | /*!< EP_TYPE[1:0] EndPoint TYPE */ |
| AnnaBridge | 163:e59c8e839560 | 12678 | #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ |
| AnnaBridge | 163:e59c8e839560 | 12679 | #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ |
| AnnaBridge | 163:e59c8e839560 | 12680 | #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ |
| AnnaBridge | 163:e59c8e839560 | 12681 | #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ |
| AnnaBridge | 163:e59c8e839560 | 12682 | #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ |
| AnnaBridge | 163:e59c8e839560 | 12683 | #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12684 | |
| AnnaBridge | 163:e59c8e839560 | 12685 | #define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ |
| AnnaBridge | 163:e59c8e839560 | 12686 | /*!< STAT_TX[1:0] STATus for TX transfer */ |
| AnnaBridge | 163:e59c8e839560 | 12687 | #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ |
| AnnaBridge | 163:e59c8e839560 | 12688 | #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ |
| AnnaBridge | 163:e59c8e839560 | 12689 | #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ |
| AnnaBridge | 163:e59c8e839560 | 12690 | #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ |
| AnnaBridge | 163:e59c8e839560 | 12691 | #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ |
| AnnaBridge | 163:e59c8e839560 | 12692 | #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ |
| AnnaBridge | 163:e59c8e839560 | 12693 | #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12694 | /*!< STAT_RX[1:0] STATus for RX transfer */ |
| AnnaBridge | 163:e59c8e839560 | 12695 | #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ |
| AnnaBridge | 163:e59c8e839560 | 12696 | #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ |
| AnnaBridge | 163:e59c8e839560 | 12697 | #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ |
| AnnaBridge | 163:e59c8e839560 | 12698 | #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ |
| AnnaBridge | 163:e59c8e839560 | 12699 | #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ |
| AnnaBridge | 163:e59c8e839560 | 12700 | #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ |
| AnnaBridge | 163:e59c8e839560 | 12701 | #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12702 | |
| AnnaBridge | 163:e59c8e839560 | 12703 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12704 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12705 | /* Window WATCHDOG */ |
| AnnaBridge | 163:e59c8e839560 | 12706 | /* */ |
| AnnaBridge | 163:e59c8e839560 | 12707 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 12708 | /******************* Bit definition for WWDG_CR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 12709 | #define WWDG_CR_T_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12710 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 163:e59c8e839560 | 12711 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| AnnaBridge | 163:e59c8e839560 | 12712 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12713 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12714 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12715 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12716 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12717 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12718 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12719 | |
| AnnaBridge | 163:e59c8e839560 | 12720 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12721 | #define WWDG_CR_T0 WWDG_CR_T_0 |
| AnnaBridge | 163:e59c8e839560 | 12722 | #define WWDG_CR_T1 WWDG_CR_T_1 |
| AnnaBridge | 163:e59c8e839560 | 12723 | #define WWDG_CR_T2 WWDG_CR_T_2 |
| AnnaBridge | 163:e59c8e839560 | 12724 | #define WWDG_CR_T3 WWDG_CR_T_3 |
| AnnaBridge | 163:e59c8e839560 | 12725 | #define WWDG_CR_T4 WWDG_CR_T_4 |
| AnnaBridge | 163:e59c8e839560 | 12726 | #define WWDG_CR_T5 WWDG_CR_T_5 |
| AnnaBridge | 163:e59c8e839560 | 12727 | #define WWDG_CR_T6 WWDG_CR_T_6 |
| AnnaBridge | 163:e59c8e839560 | 12728 | |
| AnnaBridge | 163:e59c8e839560 | 12729 | #define WWDG_CR_WDGA_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12730 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12731 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ |
| AnnaBridge | 163:e59c8e839560 | 12732 | |
| AnnaBridge | 163:e59c8e839560 | 12733 | /******************* Bit definition for WWDG_CFR register *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12734 | #define WWDG_CFR_W_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12735 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 163:e59c8e839560 | 12736 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
| AnnaBridge | 163:e59c8e839560 | 12737 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12738 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 163:e59c8e839560 | 12739 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 163:e59c8e839560 | 12740 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 163:e59c8e839560 | 12741 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 163:e59c8e839560 | 12742 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 163:e59c8e839560 | 12743 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 163:e59c8e839560 | 12744 | |
| AnnaBridge | 163:e59c8e839560 | 12745 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12746 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
| AnnaBridge | 163:e59c8e839560 | 12747 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
| AnnaBridge | 163:e59c8e839560 | 12748 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
| AnnaBridge | 163:e59c8e839560 | 12749 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
| AnnaBridge | 163:e59c8e839560 | 12750 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
| AnnaBridge | 163:e59c8e839560 | 12751 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
| AnnaBridge | 163:e59c8e839560 | 12752 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
| AnnaBridge | 163:e59c8e839560 | 12753 | |
| AnnaBridge | 163:e59c8e839560 | 12754 | #define WWDG_CFR_WDGTB_Pos (7U) |
| AnnaBridge | 163:e59c8e839560 | 12755 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
| AnnaBridge | 163:e59c8e839560 | 12756 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
| AnnaBridge | 163:e59c8e839560 | 12757 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 163:e59c8e839560 | 12758 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 163:e59c8e839560 | 12759 | |
| AnnaBridge | 163:e59c8e839560 | 12760 | /* Legacy defines */ |
| AnnaBridge | 163:e59c8e839560 | 12761 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
| AnnaBridge | 163:e59c8e839560 | 12762 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
| AnnaBridge | 163:e59c8e839560 | 12763 | |
| AnnaBridge | 163:e59c8e839560 | 12764 | #define WWDG_CFR_EWI_Pos (9U) |
| AnnaBridge | 163:e59c8e839560 | 12765 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 163:e59c8e839560 | 12766 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 12767 | |
| AnnaBridge | 163:e59c8e839560 | 12768 | /******************* Bit definition for WWDG_SR register ********************/ |
| AnnaBridge | 163:e59c8e839560 | 12769 | #define WWDG_SR_EWIF_Pos (0U) |
| AnnaBridge | 163:e59c8e839560 | 12770 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 163:e59c8e839560 | 12771 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ |
| AnnaBridge | 163:e59c8e839560 | 12772 | |
| AnnaBridge | 163:e59c8e839560 | 12773 | /** |
| AnnaBridge | 163:e59c8e839560 | 12774 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12775 | */ |
| AnnaBridge | 163:e59c8e839560 | 12776 | |
| AnnaBridge | 163:e59c8e839560 | 12777 | /** |
| AnnaBridge | 163:e59c8e839560 | 12778 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12779 | */ |
| AnnaBridge | 163:e59c8e839560 | 12780 | |
| AnnaBridge | 163:e59c8e839560 | 12781 | /** @addtogroup Exported_macros |
| AnnaBridge | 163:e59c8e839560 | 12782 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12783 | */ |
| AnnaBridge | 163:e59c8e839560 | 12784 | |
| AnnaBridge | 163:e59c8e839560 | 12785 | /****************************** ADC Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12786 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12787 | ((INSTANCE) == ADC2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12788 | ((INSTANCE) == ADC3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12789 | ((INSTANCE) == ADC4)) |
| AnnaBridge | 163:e59c8e839560 | 12790 | |
| AnnaBridge | 163:e59c8e839560 | 12791 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12792 | ((INSTANCE) == ADC3)) |
| AnnaBridge | 163:e59c8e839560 | 12793 | |
| AnnaBridge | 163:e59c8e839560 | 12794 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \ |
| AnnaBridge | 163:e59c8e839560 | 12795 | ((INSTANCE) == ADC34_COMMON)) |
| AnnaBridge | 163:e59c8e839560 | 12796 | |
| AnnaBridge | 163:e59c8e839560 | 12797 | /****************************** CAN Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12798 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN) |
| AnnaBridge | 163:e59c8e839560 | 12799 | |
| AnnaBridge | 163:e59c8e839560 | 12800 | /****************************** COMP Instances ********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12801 | #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12802 | ((INSTANCE) == COMP2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12803 | ((INSTANCE) == COMP3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12804 | ((INSTANCE) == COMP4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12805 | ((INSTANCE) == COMP5) || \ |
| AnnaBridge | 163:e59c8e839560 | 12806 | ((INSTANCE) == COMP6) || \ |
| AnnaBridge | 163:e59c8e839560 | 12807 | ((INSTANCE) == COMP7)) |
| AnnaBridge | 163:e59c8e839560 | 12808 | |
| AnnaBridge | 163:e59c8e839560 | 12809 | #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \ |
| AnnaBridge | 163:e59c8e839560 | 12810 | ((COMMON_INSTANCE) == COMP34_COMMON) || \ |
| AnnaBridge | 163:e59c8e839560 | 12811 | ((COMMON_INSTANCE) == COMP56_COMMON)) |
| AnnaBridge | 163:e59c8e839560 | 12812 | |
| AnnaBridge | 163:e59c8e839560 | 12813 | /******************** COMP Instances with switch on DAC1 Channel1 output ******/ |
| AnnaBridge | 163:e59c8e839560 | 12814 | #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1) |
| AnnaBridge | 163:e59c8e839560 | 12815 | |
| AnnaBridge | 163:e59c8e839560 | 12816 | /******************** COMP Instances with window mode capability **************/ |
| AnnaBridge | 163:e59c8e839560 | 12817 | #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12818 | ((INSTANCE) == COMP4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12819 | ((INSTANCE) == COMP6)) |
| AnnaBridge | 163:e59c8e839560 | 12820 | |
| AnnaBridge | 163:e59c8e839560 | 12821 | /****************************** CRC Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12822 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| AnnaBridge | 163:e59c8e839560 | 12823 | |
| AnnaBridge | 163:e59c8e839560 | 12824 | /****************************** DAC Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12825 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| AnnaBridge | 163:e59c8e839560 | 12826 | |
| AnnaBridge | 163:e59c8e839560 | 12827 | #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \ |
| AnnaBridge | 163:e59c8e839560 | 12828 | ((((INSTANCE) == DAC1) && \ |
| AnnaBridge | 163:e59c8e839560 | 12829 | (((CHANNEL) == DAC_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12830 | ((CHANNEL) == DAC_CHANNEL_2)))) |
| AnnaBridge | 163:e59c8e839560 | 12831 | |
| AnnaBridge | 163:e59c8e839560 | 12832 | /****************************** DMA Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12833 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12834 | ((INSTANCE) == DMA1_Channel2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12835 | ((INSTANCE) == DMA1_Channel3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12836 | ((INSTANCE) == DMA1_Channel4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12837 | ((INSTANCE) == DMA1_Channel5) || \ |
| AnnaBridge | 163:e59c8e839560 | 12838 | ((INSTANCE) == DMA1_Channel6) || \ |
| AnnaBridge | 163:e59c8e839560 | 12839 | ((INSTANCE) == DMA1_Channel7) || \ |
| AnnaBridge | 163:e59c8e839560 | 12840 | ((INSTANCE) == DMA2_Channel1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12841 | ((INSTANCE) == DMA2_Channel2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12842 | ((INSTANCE) == DMA2_Channel3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12843 | ((INSTANCE) == DMA2_Channel4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12844 | ((INSTANCE) == DMA2_Channel5)) |
| AnnaBridge | 163:e59c8e839560 | 12845 | |
| AnnaBridge | 163:e59c8e839560 | 12846 | /****************************** GPIO Instances ********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12847 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| AnnaBridge | 163:e59c8e839560 | 12848 | ((INSTANCE) == GPIOB) || \ |
| AnnaBridge | 163:e59c8e839560 | 12849 | ((INSTANCE) == GPIOC) || \ |
| AnnaBridge | 163:e59c8e839560 | 12850 | ((INSTANCE) == GPIOD) || \ |
| AnnaBridge | 163:e59c8e839560 | 12851 | ((INSTANCE) == GPIOE) || \ |
| AnnaBridge | 163:e59c8e839560 | 12852 | ((INSTANCE) == GPIOF)) |
| AnnaBridge | 163:e59c8e839560 | 12853 | |
| AnnaBridge | 163:e59c8e839560 | 12854 | #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| AnnaBridge | 163:e59c8e839560 | 12855 | ((INSTANCE) == GPIOB) || \ |
| AnnaBridge | 163:e59c8e839560 | 12856 | ((INSTANCE) == GPIOC) || \ |
| AnnaBridge | 163:e59c8e839560 | 12857 | ((INSTANCE) == GPIOD) || \ |
| AnnaBridge | 163:e59c8e839560 | 12858 | ((INSTANCE) == GPIOE) || \ |
| AnnaBridge | 163:e59c8e839560 | 12859 | ((INSTANCE) == GPIOF)) |
| AnnaBridge | 163:e59c8e839560 | 12860 | |
| AnnaBridge | 163:e59c8e839560 | 12861 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| AnnaBridge | 163:e59c8e839560 | 12862 | ((INSTANCE) == GPIOB) || \ |
| AnnaBridge | 163:e59c8e839560 | 12863 | ((INSTANCE) == GPIOD)) |
| AnnaBridge | 163:e59c8e839560 | 12864 | |
| AnnaBridge | 163:e59c8e839560 | 12865 | /****************************** I2C Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12866 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12867 | ((INSTANCE) == I2C2)) |
| AnnaBridge | 163:e59c8e839560 | 12868 | |
| AnnaBridge | 163:e59c8e839560 | 12869 | /****************** I2C Instances : wakeup capability from stop modes *********/ |
| AnnaBridge | 163:e59c8e839560 | 12870 | #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| AnnaBridge | 163:e59c8e839560 | 12871 | |
| AnnaBridge | 163:e59c8e839560 | 12872 | /****************************** I2S Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12873 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12874 | ((INSTANCE) == SPI3)) |
| AnnaBridge | 163:e59c8e839560 | 12875 | #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \ |
| AnnaBridge | 163:e59c8e839560 | 12876 | ((INSTANCE) == I2S3ext)) |
| AnnaBridge | 163:e59c8e839560 | 12877 | |
| AnnaBridge | 163:e59c8e839560 | 12878 | /****************************** OPAMP Instances *******************************/ |
| AnnaBridge | 163:e59c8e839560 | 12879 | #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12880 | ((INSTANCE) == OPAMP2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12881 | ((INSTANCE) == OPAMP3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12882 | ((INSTANCE) == OPAMP4)) |
| AnnaBridge | 163:e59c8e839560 | 12883 | |
| AnnaBridge | 163:e59c8e839560 | 12884 | /****************************** IWDG Instances ********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12885 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| AnnaBridge | 163:e59c8e839560 | 12886 | |
| AnnaBridge | 163:e59c8e839560 | 12887 | /****************************** RTC Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12888 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| AnnaBridge | 163:e59c8e839560 | 12889 | |
| AnnaBridge | 163:e59c8e839560 | 12890 | /****************************** SMBUS Instances *******************************/ |
| AnnaBridge | 163:e59c8e839560 | 12891 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12892 | ((INSTANCE) == I2C2)) |
| AnnaBridge | 163:e59c8e839560 | 12893 | |
| AnnaBridge | 163:e59c8e839560 | 12894 | /****************************** SPI Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 12895 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12896 | ((INSTANCE) == SPI2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12897 | ((INSTANCE) == SPI3)) |
| AnnaBridge | 163:e59c8e839560 | 12898 | |
| AnnaBridge | 163:e59c8e839560 | 12899 | /******************* TIM Instances : All supported instances ******************/ |
| AnnaBridge | 163:e59c8e839560 | 12900 | #define IS_TIM_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12901 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12902 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12903 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12904 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12905 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 163:e59c8e839560 | 12906 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 163:e59c8e839560 | 12907 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 12908 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 12909 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 12910 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 12911 | |
| AnnaBridge | 163:e59c8e839560 | 12912 | /******************* TIM Instances : at least 1 capture/compare channel *******/ |
| AnnaBridge | 163:e59c8e839560 | 12913 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12914 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12915 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12916 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12917 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12918 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 12919 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 12920 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 12921 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 12922 | |
| AnnaBridge | 163:e59c8e839560 | 12923 | /****************** TIM Instances : at least 2 capture/compare channels *******/ |
| AnnaBridge | 163:e59c8e839560 | 12924 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12925 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12926 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12927 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12928 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12929 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 12930 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 12931 | |
| AnnaBridge | 163:e59c8e839560 | 12932 | /****************** TIM Instances : at least 3 capture/compare channels *******/ |
| AnnaBridge | 163:e59c8e839560 | 12933 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12934 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12935 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12936 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12937 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12938 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12939 | |
| AnnaBridge | 163:e59c8e839560 | 12940 | /****************** TIM Instances : at least 4 capture/compare channels *******/ |
| AnnaBridge | 163:e59c8e839560 | 12941 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12942 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12943 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12944 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12945 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12946 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12947 | |
| AnnaBridge | 163:e59c8e839560 | 12948 | /****************** TIM Instances : at least 5 capture/compare channels *******/ |
| AnnaBridge | 163:e59c8e839560 | 12949 | #define IS_TIM_CC5_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12950 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12951 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12952 | |
| AnnaBridge | 163:e59c8e839560 | 12953 | /****************** TIM Instances : at least 6 capture/compare channels *******/ |
| AnnaBridge | 163:e59c8e839560 | 12954 | #define IS_TIM_CC6_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12955 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12956 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12957 | |
| AnnaBridge | 163:e59c8e839560 | 12958 | /************************** TIM Instances : Advanced-control timers ***********/ |
| AnnaBridge | 163:e59c8e839560 | 12959 | |
| AnnaBridge | 163:e59c8e839560 | 12960 | /****************** TIM Instances : Advanced timer instances *******************/ |
| AnnaBridge | 163:e59c8e839560 | 12961 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12962 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12963 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12964 | |
| AnnaBridge | 163:e59c8e839560 | 12965 | /****************** TIM Instances : supporting clock selection ****************/ |
| AnnaBridge | 163:e59c8e839560 | 12966 | #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12967 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12968 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12969 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12970 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12971 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 12972 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 12973 | |
| AnnaBridge | 163:e59c8e839560 | 12974 | /****************** TIM Instances : supporting external clock mode 1 for ETRF input */ |
| AnnaBridge | 163:e59c8e839560 | 12975 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12976 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12977 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12978 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12979 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12980 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12981 | |
| AnnaBridge | 163:e59c8e839560 | 12982 | /****************** TIM Instances : supporting external clock mode 2 **********/ |
| AnnaBridge | 163:e59c8e839560 | 12983 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12984 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12985 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12986 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12987 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12988 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 12989 | |
| AnnaBridge | 163:e59c8e839560 | 12990 | /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ |
| AnnaBridge | 163:e59c8e839560 | 12991 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 12992 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 12993 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 12994 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 12995 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 12996 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 12997 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 12998 | |
| AnnaBridge | 163:e59c8e839560 | 12999 | /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ |
| AnnaBridge | 163:e59c8e839560 | 13000 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13001 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13002 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13003 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13004 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13005 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13006 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 13007 | |
| AnnaBridge | 163:e59c8e839560 | 13008 | /****************** TIM Instances : supporting OCxREF clear *******************/ |
| AnnaBridge | 163:e59c8e839560 | 13009 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13010 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13011 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13012 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13013 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13014 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13015 | |
| AnnaBridge | 163:e59c8e839560 | 13016 | /****************** TIM Instances : supporting encoder interface **************/ |
| AnnaBridge | 163:e59c8e839560 | 13017 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13018 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13019 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13020 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13021 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13022 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13023 | |
| AnnaBridge | 163:e59c8e839560 | 13024 | /****************** TIM Instances : supporting Hall interface *****************/ |
| AnnaBridge | 163:e59c8e839560 | 13025 | #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13026 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13027 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13028 | |
| AnnaBridge | 163:e59c8e839560 | 13029 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13030 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13031 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13032 | |
| AnnaBridge | 163:e59c8e839560 | 13033 | /**************** TIM Instances : external trigger input available ************/ |
| AnnaBridge | 163:e59c8e839560 | 13034 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13035 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13036 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13037 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13038 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13039 | |
| AnnaBridge | 163:e59c8e839560 | 13040 | /****************** TIM Instances : supporting input XOR function *************/ |
| AnnaBridge | 163:e59c8e839560 | 13041 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13042 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13043 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13044 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13045 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13046 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13047 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 13048 | |
| AnnaBridge | 163:e59c8e839560 | 13049 | /****************** TIM Instances : supporting master mode ********************/ |
| AnnaBridge | 163:e59c8e839560 | 13050 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13051 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13052 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13053 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13054 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13055 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 163:e59c8e839560 | 13056 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 163:e59c8e839560 | 13057 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13058 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 13059 | |
| AnnaBridge | 163:e59c8e839560 | 13060 | /****************** TIM Instances : supporting slave mode *********************/ |
| AnnaBridge | 163:e59c8e839560 | 13061 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13062 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13063 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13064 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13065 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13066 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13067 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 13068 | |
| AnnaBridge | 163:e59c8e839560 | 13069 | /****************** TIM Instances : supporting synchronization ****************/ |
| AnnaBridge | 163:e59c8e839560 | 13070 | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13071 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13072 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13073 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13074 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13075 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 163:e59c8e839560 | 13076 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 163:e59c8e839560 | 13077 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13078 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 163:e59c8e839560 | 13079 | |
| AnnaBridge | 163:e59c8e839560 | 13080 | /****************** TIM Instances : supporting 32 bits counter ****************/ |
| AnnaBridge | 163:e59c8e839560 | 13081 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13082 | ((INSTANCE) == TIM2) |
| AnnaBridge | 163:e59c8e839560 | 13083 | |
| AnnaBridge | 163:e59c8e839560 | 13084 | /****************** TIM Instances : supporting DMA burst **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13085 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13086 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13087 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13088 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13089 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13090 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13091 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13092 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13093 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13094 | |
| AnnaBridge | 163:e59c8e839560 | 13095 | /****************** TIM Instances : supporting the break function *************/ |
| AnnaBridge | 163:e59c8e839560 | 13096 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13097 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13098 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13099 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13100 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13101 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13102 | |
| AnnaBridge | 163:e59c8e839560 | 13103 | /****************** TIM Instances : supporting input/output channel(s) ********/ |
| AnnaBridge | 163:e59c8e839560 | 13104 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| AnnaBridge | 163:e59c8e839560 | 13105 | ((((INSTANCE) == TIM1) && \ |
| AnnaBridge | 163:e59c8e839560 | 13106 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13107 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13108 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13109 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13110 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| AnnaBridge | 163:e59c8e839560 | 13111 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| AnnaBridge | 163:e59c8e839560 | 13112 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13113 | (((INSTANCE) == TIM2) && \ |
| AnnaBridge | 163:e59c8e839560 | 13114 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13115 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13116 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13117 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 163:e59c8e839560 | 13118 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13119 | (((INSTANCE) == TIM3) && \ |
| AnnaBridge | 163:e59c8e839560 | 13120 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13121 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13122 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13123 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 163:e59c8e839560 | 13124 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13125 | (((INSTANCE) == TIM4) && \ |
| AnnaBridge | 163:e59c8e839560 | 13126 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13127 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13128 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13129 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 163:e59c8e839560 | 13130 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13131 | (((INSTANCE) == TIM8) && \ |
| AnnaBridge | 163:e59c8e839560 | 13132 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13133 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13134 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13135 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13136 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| AnnaBridge | 163:e59c8e839560 | 13137 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| AnnaBridge | 163:e59c8e839560 | 13138 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13139 | (((INSTANCE) == TIM15) && \ |
| AnnaBridge | 163:e59c8e839560 | 13140 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13141 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| AnnaBridge | 163:e59c8e839560 | 13142 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13143 | (((INSTANCE) == TIM16) && \ |
| AnnaBridge | 163:e59c8e839560 | 13144 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| AnnaBridge | 163:e59c8e839560 | 13145 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13146 | (((INSTANCE) == TIM17) && \ |
| AnnaBridge | 163:e59c8e839560 | 13147 | (((CHANNEL) == TIM_CHANNEL_1)))) |
| AnnaBridge | 163:e59c8e839560 | 13148 | |
| AnnaBridge | 163:e59c8e839560 | 13149 | /****************** TIM Instances : supporting complementary output(s) ********/ |
| AnnaBridge | 163:e59c8e839560 | 13150 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| AnnaBridge | 163:e59c8e839560 | 13151 | ((((INSTANCE) == TIM1) && \ |
| AnnaBridge | 163:e59c8e839560 | 13152 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13153 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13154 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| AnnaBridge | 163:e59c8e839560 | 13155 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13156 | (((INSTANCE) == TIM8) && \ |
| AnnaBridge | 163:e59c8e839560 | 13157 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13158 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13159 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| AnnaBridge | 163:e59c8e839560 | 13160 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13161 | (((INSTANCE) == TIM15) && \ |
| AnnaBridge | 163:e59c8e839560 | 13162 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| AnnaBridge | 163:e59c8e839560 | 13163 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13164 | (((INSTANCE) == TIM16) && \ |
| AnnaBridge | 163:e59c8e839560 | 13165 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| AnnaBridge | 163:e59c8e839560 | 13166 | || \ |
| AnnaBridge | 163:e59c8e839560 | 13167 | (((INSTANCE) == TIM17) && \ |
| AnnaBridge | 163:e59c8e839560 | 13168 | ((CHANNEL) == TIM_CHANNEL_1))) |
| AnnaBridge | 163:e59c8e839560 | 13169 | |
| AnnaBridge | 163:e59c8e839560 | 13170 | /****************** TIM Instances : supporting counting mode selection ********/ |
| AnnaBridge | 163:e59c8e839560 | 13171 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13172 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13173 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13174 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13175 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13176 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13177 | |
| AnnaBridge | 163:e59c8e839560 | 13178 | /****************** TIM Instances : supporting repetition counter *************/ |
| AnnaBridge | 163:e59c8e839560 | 13179 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13180 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13181 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13182 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13183 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13184 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13185 | |
| AnnaBridge | 163:e59c8e839560 | 13186 | /****************** TIM Instances : supporting clock division *****************/ |
| AnnaBridge | 163:e59c8e839560 | 13187 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13188 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13189 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13190 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13191 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13192 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13193 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13194 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13195 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13196 | |
| AnnaBridge | 163:e59c8e839560 | 13197 | /****************** TIM Instances : supporting 2 break inputs *****************/ |
| AnnaBridge | 163:e59c8e839560 | 13198 | #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13199 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13200 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13201 | |
| AnnaBridge | 163:e59c8e839560 | 13202 | /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ |
| AnnaBridge | 163:e59c8e839560 | 13203 | #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13204 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13205 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13206 | |
| AnnaBridge | 163:e59c8e839560 | 13207 | /****************** TIM Instances : supporting DMA generation on Update events*/ |
| AnnaBridge | 163:e59c8e839560 | 13208 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13209 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13210 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13211 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13212 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13213 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 163:e59c8e839560 | 13214 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 163:e59c8e839560 | 13215 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13216 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13217 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13218 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13219 | |
| AnnaBridge | 163:e59c8e839560 | 13220 | /****************** TIM Instances : supporting DMA generation on Capture/Compare events */ |
| AnnaBridge | 163:e59c8e839560 | 13221 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13222 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13223 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13224 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13225 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13226 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13227 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13228 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13229 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13230 | |
| AnnaBridge | 163:e59c8e839560 | 13231 | /****************** TIM Instances : supporting commutation event generation ***/ |
| AnnaBridge | 163:e59c8e839560 | 13232 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13233 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13234 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13235 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 163:e59c8e839560 | 13236 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 163:e59c8e839560 | 13237 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 163:e59c8e839560 | 13238 | |
| AnnaBridge | 163:e59c8e839560 | 13239 | /****************** TIM Instances : supporting remapping capability ***********/ |
| AnnaBridge | 163:e59c8e839560 | 13240 | #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ |
| AnnaBridge | 163:e59c8e839560 | 13241 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13242 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 163:e59c8e839560 | 13243 | ((INSTANCE) == TIM16)) |
| AnnaBridge | 163:e59c8e839560 | 13244 | |
| AnnaBridge | 163:e59c8e839560 | 13245 | /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ |
| AnnaBridge | 163:e59c8e839560 | 13246 | #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \ |
| AnnaBridge | 163:e59c8e839560 | 13247 | (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13248 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 163:e59c8e839560 | 13249 | |
| AnnaBridge | 163:e59c8e839560 | 13250 | /****************************** TSC Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 13251 | #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) |
| AnnaBridge | 163:e59c8e839560 | 13252 | |
| AnnaBridge | 163:e59c8e839560 | 13253 | /******************** USART Instances : Synchronous mode **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13254 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13255 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13256 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13257 | |
| AnnaBridge | 163:e59c8e839560 | 13258 | /****************** USART Instances : Auto Baud Rate detection ****************/ |
| AnnaBridge | 163:e59c8e839560 | 13259 | #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13260 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13261 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13262 | |
| AnnaBridge | 163:e59c8e839560 | 13263 | /******************** UART Instances : Asynchronous mode **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13264 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13265 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13266 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13267 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13268 | ((INSTANCE) == UART5)) |
| AnnaBridge | 163:e59c8e839560 | 13269 | |
| AnnaBridge | 163:e59c8e839560 | 13270 | /******************** UART Instances : Half-Duplex mode **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13271 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13272 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13273 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13274 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13275 | ((INSTANCE) == UART5)) |
| AnnaBridge | 163:e59c8e839560 | 13276 | |
| AnnaBridge | 163:e59c8e839560 | 13277 | /******************** UART Instances : LIN mode **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13278 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13279 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13280 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13281 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13282 | ((INSTANCE) == UART5)) |
| AnnaBridge | 163:e59c8e839560 | 13283 | |
| AnnaBridge | 163:e59c8e839560 | 13284 | /******************** UART Instances : Wake-up from Stop mode **********************/ |
| AnnaBridge | 163:e59c8e839560 | 13285 | #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13286 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13287 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13288 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13289 | ((INSTANCE) == UART5)) |
| AnnaBridge | 163:e59c8e839560 | 13290 | |
| AnnaBridge | 163:e59c8e839560 | 13291 | /****************** UART Instances : Hardware Flow control ********************/ |
| AnnaBridge | 163:e59c8e839560 | 13292 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13293 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13294 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13295 | |
| AnnaBridge | 163:e59c8e839560 | 13296 | /****************** UART Instances : Auto Baud Rate detection *****************/ |
| AnnaBridge | 163:e59c8e839560 | 13297 | #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13298 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13299 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13300 | |
| AnnaBridge | 163:e59c8e839560 | 13301 | /****************** UART Instances : Driver Enable ****************************/ |
| AnnaBridge | 163:e59c8e839560 | 13302 | #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13303 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13304 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13305 | |
| AnnaBridge | 163:e59c8e839560 | 13306 | /********************* UART Instances : Smard card mode ***********************/ |
| AnnaBridge | 163:e59c8e839560 | 13307 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13308 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13309 | ((INSTANCE) == USART3)) |
| AnnaBridge | 163:e59c8e839560 | 13310 | |
| AnnaBridge | 163:e59c8e839560 | 13311 | /*********************** UART Instances : IRDA mode ***************************/ |
| AnnaBridge | 163:e59c8e839560 | 13312 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 163:e59c8e839560 | 13313 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 163:e59c8e839560 | 13314 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 163:e59c8e839560 | 13315 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 163:e59c8e839560 | 13316 | ((INSTANCE) == UART5)) |
| AnnaBridge | 163:e59c8e839560 | 13317 | |
| AnnaBridge | 163:e59c8e839560 | 13318 | /******************** UART Instances : Support of continuous communication using DMA ****/ |
| AnnaBridge | 163:e59c8e839560 | 13319 | #define IS_UART_DMA_INSTANCE(INSTANCE) (1) |
| AnnaBridge | 163:e59c8e839560 | 13320 | |
| AnnaBridge | 163:e59c8e839560 | 13321 | /****************************** USB Instances *********************************/ |
| AnnaBridge | 163:e59c8e839560 | 13322 | #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| AnnaBridge | 163:e59c8e839560 | 13323 | |
| AnnaBridge | 163:e59c8e839560 | 13324 | /****************************** WWDG Instances ********************************/ |
| AnnaBridge | 163:e59c8e839560 | 13325 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| AnnaBridge | 163:e59c8e839560 | 13326 | |
| AnnaBridge | 163:e59c8e839560 | 13327 | /** |
| AnnaBridge | 163:e59c8e839560 | 13328 | * @} |
| AnnaBridge | 163:e59c8e839560 | 13329 | */ |
| AnnaBridge | 163:e59c8e839560 | 13330 | |
| AnnaBridge | 163:e59c8e839560 | 13331 | |
| AnnaBridge | 163:e59c8e839560 | 13332 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 13333 | /* For a painless codes migration between the STM32F3xx device product */ |
| AnnaBridge | 163:e59c8e839560 | 13334 | /* lines, the aliases defined below are put in place to overcome the */ |
| AnnaBridge | 163:e59c8e839560 | 13335 | /* differences in the interrupt handlers and IRQn definitions. */ |
| AnnaBridge | 163:e59c8e839560 | 13336 | /* No need to update developed interrupt code when moving across */ |
| AnnaBridge | 163:e59c8e839560 | 13337 | /* product lines within the same STM32F3 Family */ |
| AnnaBridge | 163:e59c8e839560 | 13338 | /******************************************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 13339 | |
| AnnaBridge | 163:e59c8e839560 | 13340 | /* Aliases for __IRQn */ |
| AnnaBridge | 163:e59c8e839560 | 13341 | #define ADC1_IRQn ADC1_2_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13342 | #define SDADC1_IRQn ADC4_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13343 | #define COMP1_2_IRQn COMP1_2_3_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13344 | #define COMP2_IRQn COMP1_2_3_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13345 | #define COMP_IRQn COMP1_2_3_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13346 | #define COMP4_6_IRQn COMP4_5_6_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13347 | #define TIM15_IRQn TIM1_BRK_TIM15_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13348 | #define TIM18_DAC2_IRQn TIM1_CC_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13349 | #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13350 | #define TIM16_IRQn TIM1_UP_TIM16_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13351 | #define TIM6_DAC1_IRQn TIM6_DAC_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13352 | #define TIM7_DAC2_IRQn TIM7_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13353 | #define TIM12_IRQn TIM8_BRK_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13354 | #define TIM14_IRQn TIM8_TRG_COM_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13355 | #define TIM13_IRQn TIM8_UP_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13356 | #define CEC_IRQn USBWakeUp_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13357 | #define USBWakeUp_IRQn USBWakeUp_RMP_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13358 | #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13359 | #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn |
| AnnaBridge | 163:e59c8e839560 | 13360 | |
| AnnaBridge | 163:e59c8e839560 | 13361 | |
| AnnaBridge | 163:e59c8e839560 | 13362 | /* Aliases for __IRQHandler */ |
| AnnaBridge | 163:e59c8e839560 | 13363 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13364 | #define SDADC1_IRQHandler ADC4_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13365 | #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13366 | #define COMP2_IRQHandler COMP1_2_3_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13367 | #define COMP_IRQHandler COMP1_2_3_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13368 | #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13369 | #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13370 | #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13371 | #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13372 | #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13373 | #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13374 | #define TIM7_DAC2_IRQHandler TIM7_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13375 | #define TIM12_IRQHandler TIM8_BRK_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13376 | #define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13377 | #define TIM13_IRQHandler TIM8_UP_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13378 | #define CEC_IRQHandler USBWakeUp_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13379 | #define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13380 | #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13381 | #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler |
| AnnaBridge | 163:e59c8e839560 | 13382 | |
| AnnaBridge | 163:e59c8e839560 | 13383 | |
| AnnaBridge | 163:e59c8e839560 | 13384 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 13385 | } |
| AnnaBridge | 163:e59c8e839560 | 13386 | #endif /* __cplusplus */ |
| AnnaBridge | 163:e59c8e839560 | 13387 | |
| AnnaBridge | 163:e59c8e839560 | 13388 | #endif /* __STM32F303xC_H */ |
| AnnaBridge | 163:e59c8e839560 | 13389 | |
| AnnaBridge | 163:e59c8e839560 | 13390 | /** |
| AnnaBridge | 163:e59c8e839560 | 13391 | * @} |
| AnnaBridge | 163:e59c8e839560 | 13392 | */ |
| AnnaBridge | 163:e59c8e839560 | 13393 | |
| AnnaBridge | 163:e59c8e839560 | 13394 | /** |
| AnnaBridge | 163:e59c8e839560 | 13395 | * @} |
| AnnaBridge | 163:e59c8e839560 | 13396 | */ |
| AnnaBridge | 163:e59c8e839560 | 13397 | |
| AnnaBridge | 163:e59c8e839560 | 13398 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
