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mbed library sources

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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

Diff: targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c

Revision:
610:813dcc80987e
Parent:
573:ad23fe03a082
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c	Fri Aug 14 12:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c	Fri Aug 14 13:15:17 2015 +0100
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    12-May-2015
+  * @version V1.0.1
+  * @date    25-June-2015
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
@@ -26,7 +26,7 @@
         function according to the following table.
     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programing manual for details in how to configure priority. 
+    (#) please refer to programming manual for details in how to configure priority. 
       
      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
          The pending IRQ priority will be managed only by the sub priority.
@@ -297,15 +297,15 @@
     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
     
     MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = (MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                (MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                (MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                (MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                (MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                (MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                (MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                (MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                (MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
   }
   else
   {