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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.h@84:f54042cbc282, 2014-02-03 (annotated)

Committer:: mbed_official
Date:: Mon Feb 03 09:30:05 2014 +0000
Revision:: 84:f54042cbc282
Parent:: 70:c1fbde68b492

Synchronized with git revision bbbd8699601c42149ccf0c37bc42bb6856ccc4c6



Full URL: https://github.com/mbedmicro/mbed/commit/bbbd8699601c42149ccf0c37bc42bb6856ccc4c6/



[NUCLEO_L152RE/F030_R8] SPI, I2C, Ticker, PWM updates

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	52:a51c77007319	1	/**
mbed_official	52:a51c77007319	2	******************************************************************************
mbed_official	52:a51c77007319	3	* @file stm32f10x_fsmc.h
mbed_official	52:a51c77007319	4	* @author MCD Application Team
mbed_official	84:f54042cbc282	5	* @version V3.6.1
mbed_official	84:f54042cbc282	6	* @date 05-March-2012
mbed_official	52:a51c77007319	7	* @brief This file contains all the functions prototypes for the FSMC firmware
mbed_official	52:a51c77007319	8	* library.
mbed_official	70:c1fbde68b492	9	*******************************************************************************
mbed_official	70:c1fbde68b492	10	* Copyright (c) 2014, STMicroelectronics
mbed_official	70:c1fbde68b492	11	* All rights reserved.
mbed_official	70:c1fbde68b492	12	*
mbed_official	70:c1fbde68b492	13	* Redistribution and use in source and binary forms, with or without
mbed_official	70:c1fbde68b492	14	* modification, are permitted provided that the following conditions are met:
mbed_official	70:c1fbde68b492	15	*
mbed_official	70:c1fbde68b492	16	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	70:c1fbde68b492	17	* this list of conditions and the following disclaimer.
mbed_official	70:c1fbde68b492	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	70:c1fbde68b492	19	* this list of conditions and the following disclaimer in the documentation
mbed_official	70:c1fbde68b492	20	* and/or other materials provided with the distribution.
mbed_official	70:c1fbde68b492	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	70:c1fbde68b492	22	* may be used to endorse or promote products derived from this software
mbed_official	70:c1fbde68b492	23	* without specific prior written permission.
mbed_official	70:c1fbde68b492	24	*
mbed_official	70:c1fbde68b492	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	70:c1fbde68b492	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	70:c1fbde68b492	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	70:c1fbde68b492	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	70:c1fbde68b492	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	70:c1fbde68b492	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	70:c1fbde68b492	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	70:c1fbde68b492	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	70:c1fbde68b492	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	70:c1fbde68b492	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	70:c1fbde68b492	35	*******************************************************************************
mbed_official	70:c1fbde68b492	36	*/
mbed_official	52:a51c77007319	37
mbed_official	52:a51c77007319	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	52:a51c77007319	39	#ifndef __STM32F10x_FSMC_H
mbed_official	52:a51c77007319	40	#define __STM32F10x_FSMC_H
mbed_official	52:a51c77007319	41
mbed_official	52:a51c77007319	42	#ifdef __cplusplus
mbed_official	52:a51c77007319	43	extern "C" {
mbed_official	52:a51c77007319	44	#endif
mbed_official	52:a51c77007319	45
mbed_official	52:a51c77007319	46	/* Includes ------------------------------------------------------------------*/
mbed_official	52:a51c77007319	47	#include "stm32f10x.h"
mbed_official	52:a51c77007319	48
mbed_official	52:a51c77007319	49	/** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official	52:a51c77007319	50	* @{
mbed_official	52:a51c77007319	51	*/
mbed_official	52:a51c77007319	52
mbed_official	52:a51c77007319	53	/** @addtogroup FSMC
mbed_official	52:a51c77007319	54	* @{
mbed_official	52:a51c77007319	55	*/
mbed_official	52:a51c77007319	56
mbed_official	52:a51c77007319	57	/** @defgroup FSMC_Exported_Types
mbed_official	52:a51c77007319	58	* @{
mbed_official	52:a51c77007319	59	*/
mbed_official	52:a51c77007319	60
mbed_official	52:a51c77007319	61	/**
mbed_official	52:a51c77007319	62	* @brief Timing parameters For NOR/SRAM Banks
mbed_official	52:a51c77007319	63	*/
mbed_official	52:a51c77007319	64
mbed_official	52:a51c77007319	65	typedef struct
mbed_official	52:a51c77007319	66	{
mbed_official	52:a51c77007319	67	uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	52:a51c77007319	68	the duration of the address setup time.
mbed_official	52:a51c77007319	69	This parameter can be a value between 0 and 0xF.
mbed_official	52:a51c77007319	70	@note: It is not used with synchronous NOR Flash memories. */
mbed_official	52:a51c77007319	71
mbed_official	52:a51c77007319	72	uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	52:a51c77007319	73	the duration of the address hold time.
mbed_official	52:a51c77007319	74	This parameter can be a value between 0 and 0xF.
mbed_official	52:a51c77007319	75	@note: It is not used with synchronous NOR Flash memories.*/
mbed_official	52:a51c77007319	76
mbed_official	52:a51c77007319	77	uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	52:a51c77007319	78	the duration of the data setup time.
mbed_official	52:a51c77007319	79	This parameter can be a value between 0 and 0xFF.
mbed_official	52:a51c77007319	80	@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
mbed_official	52:a51c77007319	81
mbed_official	52:a51c77007319	82	uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	52:a51c77007319	83	the duration of the bus turnaround.
mbed_official	52:a51c77007319	84	This parameter can be a value between 0 and 0xF.
mbed_official	52:a51c77007319	85	@note: It is only used for multiplexed NOR Flash memories. */
mbed_official	52:a51c77007319	86
mbed_official	52:a51c77007319	87	uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
mbed_official	52:a51c77007319	88	This parameter can be a value between 1 and 0xF.
mbed_official	52:a51c77007319	89	@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
mbed_official	52:a51c77007319	90
mbed_official	52:a51c77007319	91	uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	52:a51c77007319	92	to the memory before getting the first data.
mbed_official	52:a51c77007319	93	The value of this parameter depends on the memory type as shown below:
mbed_official	52:a51c77007319	94	- It must be set to 0 in case of a CRAM
mbed_official	52:a51c77007319	95	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	52:a51c77007319	96	- It may assume a value between 0 and 0xF in NOR Flash memories
mbed_official	52:a51c77007319	97	with synchronous burst mode enable */
mbed_official	52:a51c77007319	98
mbed_official	52:a51c77007319	99	uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	52:a51c77007319	100	This parameter can be a value of @ref FSMC_Access_Mode */
mbed_official	52:a51c77007319	101	}FSMC_NORSRAMTimingInitTypeDef;
mbed_official	52:a51c77007319	102
mbed_official	52:a51c77007319	103	/**
mbed_official	52:a51c77007319	104	* @brief FSMC NOR/SRAM Init structure definition
mbed_official	52:a51c77007319	105	*/
mbed_official	52:a51c77007319	106
mbed_official	52:a51c77007319	107	typedef struct
mbed_official	52:a51c77007319	108	{
mbed_official	52:a51c77007319	109	uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
mbed_official	52:a51c77007319	110	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
mbed_official	52:a51c77007319	111
mbed_official	52:a51c77007319	112	uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	52:a51c77007319	113	multiplexed on the databus or not.
mbed_official	52:a51c77007319	114	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
mbed_official	52:a51c77007319	115
mbed_official	52:a51c77007319	116	uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	52:a51c77007319	117	the corresponding memory bank.
mbed_official	52:a51c77007319	118	This parameter can be a value of @ref FSMC_Memory_Type */
mbed_official	52:a51c77007319	119
mbed_official	52:a51c77007319	120	uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	52:a51c77007319	121	This parameter can be a value of @ref FSMC_Data_Width */
mbed_official	52:a51c77007319	122
mbed_official	52:a51c77007319	123	uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	52:a51c77007319	124	valid only with synchronous burst Flash memories.
mbed_official	52:a51c77007319	125	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
mbed_official	52:a51c77007319	126
mbed_official	52:a51c77007319	127	uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	52:a51c77007319	128	valid only with asynchronous Flash memories.
mbed_official	52:a51c77007319	129	This parameter can be a value of @ref FSMC_AsynchronousWait */
mbed_official	52:a51c77007319	130
mbed_official	52:a51c77007319	131	uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	52:a51c77007319	132	the Flash memory in burst mode.
mbed_official	52:a51c77007319	133	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
mbed_official	52:a51c77007319	134
mbed_official	52:a51c77007319	135	uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	52:a51c77007319	136	memory, valid only when accessing Flash memories in burst mode.
mbed_official	52:a51c77007319	137	This parameter can be a value of @ref FSMC_Wrap_Mode */
mbed_official	52:a51c77007319	138
mbed_official	52:a51c77007319	139	uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	52:a51c77007319	140	clock cycle before the wait state or during the wait state,
mbed_official	52:a51c77007319	141	valid only when accessing memories in burst mode.
mbed_official	52:a51c77007319	142	This parameter can be a value of @ref FSMC_Wait_Timing */
mbed_official	52:a51c77007319	143
mbed_official	52:a51c77007319	144	uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
mbed_official	52:a51c77007319	145	This parameter can be a value of @ref FSMC_Write_Operation */
mbed_official	52:a51c77007319	146
mbed_official	52:a51c77007319	147	uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
mbed_official	52:a51c77007319	148	signal, valid for Flash memory access in burst mode.
mbed_official	52:a51c77007319	149	This parameter can be a value of @ref FSMC_Wait_Signal */
mbed_official	52:a51c77007319	150
mbed_official	52:a51c77007319	151	uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	52:a51c77007319	152	This parameter can be a value of @ref FSMC_Extended_Mode */
mbed_official	52:a51c77007319	153
mbed_official	52:a51c77007319	154	uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	52:a51c77007319	155	This parameter can be a value of @ref FSMC_Write_Burst */
mbed_official	52:a51c77007319	156
mbed_official	52:a51c77007319	157	FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /!< Timing Parameters for write and read access if the ExtendedMode is not used/
mbed_official	52:a51c77007319	158
mbed_official	52:a51c77007319	159	FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /!< Timing Parameters for write access if the ExtendedMode is used/
mbed_official	52:a51c77007319	160	}FSMC_NORSRAMInitTypeDef;
mbed_official	52:a51c77007319	161
mbed_official	52:a51c77007319	162	/**
mbed_official	52:a51c77007319	163	* @brief Timing parameters For FSMC NAND and PCCARD Banks
mbed_official	52:a51c77007319	164	*/
mbed_official	52:a51c77007319	165
mbed_official	52:a51c77007319	166	typedef struct
mbed_official	52:a51c77007319	167	{
mbed_official	52:a51c77007319	168	uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	52:a51c77007319	169	the command assertion for NAND-Flash read or write access
mbed_official	52:a51c77007319	170	to common/Attribute or I/O memory space (depending on
mbed_official	52:a51c77007319	171	the memory space timing to be configured).
mbed_official	52:a51c77007319	172	This parameter can be a value between 0 and 0xFF.*/
mbed_official	52:a51c77007319	173
mbed_official	52:a51c77007319	174	uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	52:a51c77007319	175	command for NAND-Flash read or write access to
mbed_official	52:a51c77007319	176	common/Attribute or I/O memory space (depending on the
mbed_official	52:a51c77007319	177	memory space timing to be configured).
mbed_official	52:a51c77007319	178	This parameter can be a number between 0x00 and 0xFF */
mbed_official	52:a51c77007319	179
mbed_official	52:a51c77007319	180	uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	52:a51c77007319	181	(and data for write access) after the command deassertion
mbed_official	52:a51c77007319	182	for NAND-Flash read or write access to common/Attribute
mbed_official	52:a51c77007319	183	or I/O memory space (depending on the memory space timing
mbed_official	52:a51c77007319	184	to be configured).
mbed_official	52:a51c77007319	185	This parameter can be a number between 0x00 and 0xFF */
mbed_official	52:a51c77007319	186
mbed_official	52:a51c77007319	187	uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	52:a51c77007319	188	databus is kept in HiZ after the start of a NAND-Flash
mbed_official	52:a51c77007319	189	write access to common/Attribute or I/O memory space (depending
mbed_official	52:a51c77007319	190	on the memory space timing to be configured).
mbed_official	52:a51c77007319	191	This parameter can be a number between 0x00 and 0xFF */
mbed_official	52:a51c77007319	192	}FSMC_NAND_PCCARDTimingInitTypeDef;
mbed_official	52:a51c77007319	193
mbed_official	52:a51c77007319	194	/**
mbed_official	52:a51c77007319	195	* @brief FSMC NAND Init structure definition
mbed_official	52:a51c77007319	196	*/
mbed_official	52:a51c77007319	197
mbed_official	52:a51c77007319	198	typedef struct
mbed_official	52:a51c77007319	199	{
mbed_official	52:a51c77007319	200	uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
mbed_official	52:a51c77007319	201	This parameter can be a value of @ref FSMC_NAND_Bank */
mbed_official	52:a51c77007319	202
mbed_official	52:a51c77007319	203	uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
mbed_official	52:a51c77007319	204	This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official	52:a51c77007319	205
mbed_official	52:a51c77007319	206	uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	52:a51c77007319	207	This parameter can be any value of @ref FSMC_Data_Width */
mbed_official	52:a51c77007319	208
mbed_official	52:a51c77007319	209	uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
mbed_official	52:a51c77007319	210	This parameter can be any value of @ref FSMC_ECC */
mbed_official	52:a51c77007319	211
mbed_official	52:a51c77007319	212	uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	52:a51c77007319	213	This parameter can be any value of @ref FSMC_ECC_Page_Size */
mbed_official	52:a51c77007319	214
mbed_official	52:a51c77007319	215	uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	52:a51c77007319	216	delay between CLE low and RE low.
mbed_official	52:a51c77007319	217	This parameter can be a value between 0 and 0xFF. */
mbed_official	52:a51c77007319	218
mbed_official	52:a51c77007319	219	uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	52:a51c77007319	220	delay between ALE low and RE low.
mbed_official	52:a51c77007319	221	This parameter can be a number between 0x0 and 0xFF */
mbed_official	52:a51c77007319	222
mbed_official	52:a51c77007319	223	FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /!< FSMC Common Space Timing /
mbed_official	52:a51c77007319	224
mbed_official	52:a51c77007319	225	FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /!< FSMC Attribute Space Timing /
mbed_official	52:a51c77007319	226	}FSMC_NANDInitTypeDef;
mbed_official	52:a51c77007319	227
mbed_official	52:a51c77007319	228	/**
mbed_official	52:a51c77007319	229	* @brief FSMC PCCARD Init structure definition
mbed_official	52:a51c77007319	230	*/
mbed_official	52:a51c77007319	231
mbed_official	52:a51c77007319	232	typedef struct
mbed_official	52:a51c77007319	233	{
mbed_official	52:a51c77007319	234	uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
mbed_official	52:a51c77007319	235	This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official	52:a51c77007319	236
mbed_official	52:a51c77007319	237	uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	52:a51c77007319	238	delay between CLE low and RE low.
mbed_official	52:a51c77007319	239	This parameter can be a value between 0 and 0xFF. */
mbed_official	52:a51c77007319	240
mbed_official	52:a51c77007319	241	uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	52:a51c77007319	242	delay between ALE low and RE low.
mbed_official	52:a51c77007319	243	This parameter can be a number between 0x0 and 0xFF */
mbed_official	52:a51c77007319	244
mbed_official	52:a51c77007319	245
mbed_official	52:a51c77007319	246	FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /!< FSMC Common Space Timing /
mbed_official	52:a51c77007319	247
mbed_official	52:a51c77007319	248	FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /!< FSMC Attribute Space Timing /
mbed_official	52:a51c77007319	249
mbed_official	52:a51c77007319	250	FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /!< FSMC IO Space Timing /
mbed_official	52:a51c77007319	251	}FSMC_PCCARDInitTypeDef;
mbed_official	52:a51c77007319	252
mbed_official	52:a51c77007319	253	/**
mbed_official	52:a51c77007319	254	* @}
mbed_official	52:a51c77007319	255	*/
mbed_official	52:a51c77007319	256
mbed_official	52:a51c77007319	257	/** @defgroup FSMC_Exported_Constants
mbed_official	52:a51c77007319	258	* @{
mbed_official	52:a51c77007319	259	*/
mbed_official	52:a51c77007319	260
mbed_official	52:a51c77007319	261	/** @defgroup FSMC_NORSRAM_Bank
mbed_official	52:a51c77007319	262	* @{
mbed_official	52:a51c77007319	263	*/
mbed_official	52:a51c77007319	264	#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	265	#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
mbed_official	52:a51c77007319	266	#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
mbed_official	52:a51c77007319	267	#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
mbed_official	52:a51c77007319	268	/**
mbed_official	52:a51c77007319	269	* @}
mbed_official	52:a51c77007319	270	*/
mbed_official	52:a51c77007319	271
mbed_official	52:a51c77007319	272	/** @defgroup FSMC_NAND_Bank
mbed_official	52:a51c77007319	273	* @{
mbed_official	52:a51c77007319	274	*/
mbed_official	52:a51c77007319	275	#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
mbed_official	52:a51c77007319	276	#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
mbed_official	52:a51c77007319	277	/**
mbed_official	52:a51c77007319	278	* @}
mbed_official	52:a51c77007319	279	*/
mbed_official	52:a51c77007319	280
mbed_official	52:a51c77007319	281	/** @defgroup FSMC_PCCARD_Bank
mbed_official	52:a51c77007319	282	* @{
mbed_official	52:a51c77007319	283	*/
mbed_official	52:a51c77007319	284	#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
mbed_official	52:a51c77007319	285	/**
mbed_official	52:a51c77007319	286	* @}
mbed_official	52:a51c77007319	287	*/
mbed_official	52:a51c77007319	288
mbed_official	52:a51c77007319	289	#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) \|\| \
mbed_official	52:a51c77007319	290	((BANK) == FSMC_Bank1_NORSRAM2) \|\| \
mbed_official	52:a51c77007319	291	((BANK) == FSMC_Bank1_NORSRAM3) \|\| \
mbed_official	52:a51c77007319	292	((BANK) == FSMC_Bank1_NORSRAM4))
mbed_official	52:a51c77007319	293
mbed_official	52:a51c77007319	294	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \
mbed_official	52:a51c77007319	295	((BANK) == FSMC_Bank3_NAND))
mbed_official	52:a51c77007319	296
mbed_official	52:a51c77007319	297	#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \
mbed_official	52:a51c77007319	298	((BANK) == FSMC_Bank3_NAND) \|\| \
mbed_official	52:a51c77007319	299	((BANK) == FSMC_Bank4_PCCARD))
mbed_official	52:a51c77007319	300
mbed_official	52:a51c77007319	301	#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \
mbed_official	52:a51c77007319	302	((BANK) == FSMC_Bank3_NAND) \|\| \
mbed_official	52:a51c77007319	303	((BANK) == FSMC_Bank4_PCCARD))
mbed_official	52:a51c77007319	304
mbed_official	52:a51c77007319	305	/** @defgroup NOR_SRAM_Controller
mbed_official	52:a51c77007319	306	* @{
mbed_official	52:a51c77007319	307	*/
mbed_official	52:a51c77007319	308
mbed_official	52:a51c77007319	309	/** @defgroup FSMC_Data_Address_Bus_Multiplexing
mbed_official	52:a51c77007319	310	* @{
mbed_official	52:a51c77007319	311	*/
mbed_official	52:a51c77007319	312
mbed_official	52:a51c77007319	313	#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	314	#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
mbed_official	52:a51c77007319	315	#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) \|\| \
mbed_official	52:a51c77007319	316	((MUX) == FSMC_DataAddressMux_Enable))
mbed_official	52:a51c77007319	317
mbed_official	52:a51c77007319	318	/**
mbed_official	52:a51c77007319	319	* @}
mbed_official	52:a51c77007319	320	*/
mbed_official	52:a51c77007319	321
mbed_official	52:a51c77007319	322	/** @defgroup FSMC_Memory_Type
mbed_official	52:a51c77007319	323	* @{
mbed_official	52:a51c77007319	324	*/
mbed_official	52:a51c77007319	325
mbed_official	52:a51c77007319	326	#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	327	#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
mbed_official	52:a51c77007319	328	#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
mbed_official	52:a51c77007319	329	#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) \|\| \
mbed_official	52:a51c77007319	330	((MEMORY) == FSMC_MemoryType_PSRAM)\|\| \
mbed_official	52:a51c77007319	331	((MEMORY) == FSMC_MemoryType_NOR))
mbed_official	52:a51c77007319	332
mbed_official	52:a51c77007319	333	/**
mbed_official	52:a51c77007319	334	* @}
mbed_official	52:a51c77007319	335	*/
mbed_official	52:a51c77007319	336
mbed_official	52:a51c77007319	337	/** @defgroup FSMC_Data_Width
mbed_official	52:a51c77007319	338	* @{
mbed_official	52:a51c77007319	339	*/
mbed_official	52:a51c77007319	340
mbed_official	52:a51c77007319	341	#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	342	#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
mbed_official	52:a51c77007319	343	#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) \|\| \
mbed_official	52:a51c77007319	344	((WIDTH) == FSMC_MemoryDataWidth_16b))
mbed_official	52:a51c77007319	345
mbed_official	52:a51c77007319	346	/**
mbed_official	52:a51c77007319	347	* @}
mbed_official	52:a51c77007319	348	*/
mbed_official	52:a51c77007319	349
mbed_official	52:a51c77007319	350	/** @defgroup FSMC_Burst_Access_Mode
mbed_official	52:a51c77007319	351	* @{
mbed_official	52:a51c77007319	352	*/
mbed_official	52:a51c77007319	353
mbed_official	52:a51c77007319	354	#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	355	#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
mbed_official	52:a51c77007319	356	#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) \|\| \
mbed_official	52:a51c77007319	357	((STATE) == FSMC_BurstAccessMode_Enable))
mbed_official	52:a51c77007319	358	/**
mbed_official	52:a51c77007319	359	* @}
mbed_official	52:a51c77007319	360	*/
mbed_official	52:a51c77007319	361
mbed_official	52:a51c77007319	362	/** @defgroup FSMC_AsynchronousWait
mbed_official	52:a51c77007319	363	* @{
mbed_official	52:a51c77007319	364	*/
mbed_official	52:a51c77007319	365	#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	366	#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
mbed_official	52:a51c77007319	367	#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) \|\| \
mbed_official	52:a51c77007319	368	((STATE) == FSMC_AsynchronousWait_Enable))
mbed_official	52:a51c77007319	369
mbed_official	52:a51c77007319	370	/**
mbed_official	52:a51c77007319	371	* @}
mbed_official	52:a51c77007319	372	*/
mbed_official	52:a51c77007319	373
mbed_official	52:a51c77007319	374	/** @defgroup FSMC_Wait_Signal_Polarity
mbed_official	52:a51c77007319	375	* @{
mbed_official	52:a51c77007319	376	*/
mbed_official	52:a51c77007319	377
mbed_official	52:a51c77007319	378	#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	379	#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
mbed_official	52:a51c77007319	380	#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) \|\| \
mbed_official	52:a51c77007319	381	((POLARITY) == FSMC_WaitSignalPolarity_High))
mbed_official	52:a51c77007319	382
mbed_official	52:a51c77007319	383	/**
mbed_official	52:a51c77007319	384	* @}
mbed_official	52:a51c77007319	385	*/
mbed_official	52:a51c77007319	386
mbed_official	52:a51c77007319	387	/** @defgroup FSMC_Wrap_Mode
mbed_official	52:a51c77007319	388	* @{
mbed_official	52:a51c77007319	389	*/
mbed_official	52:a51c77007319	390
mbed_official	52:a51c77007319	391	#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	392	#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
mbed_official	52:a51c77007319	393	#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) \|\| \
mbed_official	52:a51c77007319	394	((MODE) == FSMC_WrapMode_Enable))
mbed_official	52:a51c77007319	395
mbed_official	52:a51c77007319	396	/**
mbed_official	52:a51c77007319	397	* @}
mbed_official	52:a51c77007319	398	*/
mbed_official	52:a51c77007319	399
mbed_official	52:a51c77007319	400	/** @defgroup FSMC_Wait_Timing
mbed_official	52:a51c77007319	401	* @{
mbed_official	52:a51c77007319	402	*/
mbed_official	52:a51c77007319	403
mbed_official	52:a51c77007319	404	#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	405	#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
mbed_official	52:a51c77007319	406	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) \|\| \
mbed_official	52:a51c77007319	407	((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
mbed_official	52:a51c77007319	408
mbed_official	52:a51c77007319	409	/**
mbed_official	52:a51c77007319	410	* @}
mbed_official	52:a51c77007319	411	*/
mbed_official	52:a51c77007319	412
mbed_official	52:a51c77007319	413	/** @defgroup FSMC_Write_Operation
mbed_official	52:a51c77007319	414	* @{
mbed_official	52:a51c77007319	415	*/
mbed_official	52:a51c77007319	416
mbed_official	52:a51c77007319	417	#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	418	#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
mbed_official	52:a51c77007319	419	#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) \|\| \
mbed_official	52:a51c77007319	420	((OPERATION) == FSMC_WriteOperation_Enable))
mbed_official	52:a51c77007319	421
mbed_official	52:a51c77007319	422	/**
mbed_official	52:a51c77007319	423	* @}
mbed_official	52:a51c77007319	424	*/
mbed_official	52:a51c77007319	425
mbed_official	52:a51c77007319	426	/** @defgroup FSMC_Wait_Signal
mbed_official	52:a51c77007319	427	* @{
mbed_official	52:a51c77007319	428	*/
mbed_official	52:a51c77007319	429
mbed_official	52:a51c77007319	430	#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	431	#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
mbed_official	52:a51c77007319	432	#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) \|\| \
mbed_official	52:a51c77007319	433	((SIGNAL) == FSMC_WaitSignal_Enable))
mbed_official	52:a51c77007319	434	/**
mbed_official	52:a51c77007319	435	* @}
mbed_official	52:a51c77007319	436	*/
mbed_official	52:a51c77007319	437
mbed_official	52:a51c77007319	438	/** @defgroup FSMC_Extended_Mode
mbed_official	52:a51c77007319	439	* @{
mbed_official	52:a51c77007319	440	*/
mbed_official	52:a51c77007319	441
mbed_official	52:a51c77007319	442	#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	443	#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
mbed_official	52:a51c77007319	444
mbed_official	52:a51c77007319	445	#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) \|\| \
mbed_official	52:a51c77007319	446	((MODE) == FSMC_ExtendedMode_Enable))
mbed_official	52:a51c77007319	447
mbed_official	52:a51c77007319	448	/**
mbed_official	52:a51c77007319	449	* @}
mbed_official	52:a51c77007319	450	*/
mbed_official	52:a51c77007319	451
mbed_official	52:a51c77007319	452	/** @defgroup FSMC_Write_Burst
mbed_official	52:a51c77007319	453	* @{
mbed_official	52:a51c77007319	454	*/
mbed_official	52:a51c77007319	455
mbed_official	52:a51c77007319	456	#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	457	#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
mbed_official	52:a51c77007319	458	#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) \|\| \
mbed_official	52:a51c77007319	459	((BURST) == FSMC_WriteBurst_Enable))
mbed_official	52:a51c77007319	460	/**
mbed_official	52:a51c77007319	461	* @}
mbed_official	52:a51c77007319	462	*/
mbed_official	52:a51c77007319	463
mbed_official	52:a51c77007319	464	/** @defgroup FSMC_Address_Setup_Time
mbed_official	52:a51c77007319	465	* @{
mbed_official	52:a51c77007319	466	*/
mbed_official	52:a51c77007319	467
mbed_official	52:a51c77007319	468	#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
mbed_official	52:a51c77007319	469
mbed_official	52:a51c77007319	470	/**
mbed_official	52:a51c77007319	471	* @}
mbed_official	52:a51c77007319	472	*/
mbed_official	52:a51c77007319	473
mbed_official	52:a51c77007319	474	/** @defgroup FSMC_Address_Hold_Time
mbed_official	52:a51c77007319	475	* @{
mbed_official	52:a51c77007319	476	*/
mbed_official	52:a51c77007319	477
mbed_official	52:a51c77007319	478	#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
mbed_official	52:a51c77007319	479
mbed_official	52:a51c77007319	480	/**
mbed_official	52:a51c77007319	481	* @}
mbed_official	52:a51c77007319	482	*/
mbed_official	52:a51c77007319	483
mbed_official	52:a51c77007319	484	/** @defgroup FSMC_Data_Setup_Time
mbed_official	52:a51c77007319	485	* @{
mbed_official	52:a51c77007319	486	*/
mbed_official	52:a51c77007319	487
mbed_official	52:a51c77007319	488	#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
mbed_official	52:a51c77007319	489
mbed_official	52:a51c77007319	490	/**
mbed_official	52:a51c77007319	491	* @}
mbed_official	52:a51c77007319	492	*/
mbed_official	52:a51c77007319	493
mbed_official	52:a51c77007319	494	/** @defgroup FSMC_Bus_Turn_around_Duration
mbed_official	52:a51c77007319	495	* @{
mbed_official	52:a51c77007319	496	*/
mbed_official	52:a51c77007319	497
mbed_official	52:a51c77007319	498	#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
mbed_official	52:a51c77007319	499
mbed_official	52:a51c77007319	500	/**
mbed_official	52:a51c77007319	501	* @}
mbed_official	52:a51c77007319	502	*/
mbed_official	52:a51c77007319	503
mbed_official	52:a51c77007319	504	/** @defgroup FSMC_CLK_Division
mbed_official	52:a51c77007319	505	* @{
mbed_official	52:a51c77007319	506	*/
mbed_official	52:a51c77007319	507
mbed_official	52:a51c77007319	508	#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
mbed_official	52:a51c77007319	509
mbed_official	52:a51c77007319	510	/**
mbed_official	52:a51c77007319	511	* @}
mbed_official	52:a51c77007319	512	*/
mbed_official	52:a51c77007319	513
mbed_official	52:a51c77007319	514	/** @defgroup FSMC_Data_Latency
mbed_official	52:a51c77007319	515	* @{
mbed_official	52:a51c77007319	516	*/
mbed_official	52:a51c77007319	517
mbed_official	52:a51c77007319	518	#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
mbed_official	52:a51c77007319	519
mbed_official	52:a51c77007319	520	/**
mbed_official	52:a51c77007319	521	* @}
mbed_official	52:a51c77007319	522	*/
mbed_official	52:a51c77007319	523
mbed_official	52:a51c77007319	524	/** @defgroup FSMC_Access_Mode
mbed_official	52:a51c77007319	525	* @{
mbed_official	52:a51c77007319	526	*/
mbed_official	52:a51c77007319	527
mbed_official	52:a51c77007319	528	#define FSMC_AccessMode_A ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	529	#define FSMC_AccessMode_B ((uint32_t)0x10000000)
mbed_official	52:a51c77007319	530	#define FSMC_AccessMode_C ((uint32_t)0x20000000)
mbed_official	52:a51c77007319	531	#define FSMC_AccessMode_D ((uint32_t)0x30000000)
mbed_official	52:a51c77007319	532	#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) \|\| \
mbed_official	52:a51c77007319	533	((MODE) == FSMC_AccessMode_B) \|\| \
mbed_official	52:a51c77007319	534	((MODE) == FSMC_AccessMode_C) \|\| \
mbed_official	52:a51c77007319	535	((MODE) == FSMC_AccessMode_D))
mbed_official	52:a51c77007319	536
mbed_official	52:a51c77007319	537	/**
mbed_official	52:a51c77007319	538	* @}
mbed_official	52:a51c77007319	539	*/
mbed_official	52:a51c77007319	540
mbed_official	52:a51c77007319	541	/**
mbed_official	52:a51c77007319	542	* @}
mbed_official	52:a51c77007319	543	*/
mbed_official	52:a51c77007319	544
mbed_official	52:a51c77007319	545	/** @defgroup NAND_PCCARD_Controller
mbed_official	52:a51c77007319	546	* @{
mbed_official	52:a51c77007319	547	*/
mbed_official	52:a51c77007319	548
mbed_official	52:a51c77007319	549	/** @defgroup FSMC_Wait_feature
mbed_official	52:a51c77007319	550	* @{
mbed_official	52:a51c77007319	551	*/
mbed_official	52:a51c77007319	552
mbed_official	52:a51c77007319	553	#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	554	#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
mbed_official	52:a51c77007319	555	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) \|\| \
mbed_official	52:a51c77007319	556	((FEATURE) == FSMC_Waitfeature_Enable))
mbed_official	52:a51c77007319	557
mbed_official	52:a51c77007319	558	/**
mbed_official	52:a51c77007319	559	* @}
mbed_official	52:a51c77007319	560	*/
mbed_official	52:a51c77007319	561
mbed_official	52:a51c77007319	562
mbed_official	52:a51c77007319	563	/** @defgroup FSMC_ECC
mbed_official	52:a51c77007319	564	* @{
mbed_official	52:a51c77007319	565	*/
mbed_official	52:a51c77007319	566
mbed_official	52:a51c77007319	567	#define FSMC_ECC_Disable ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	568	#define FSMC_ECC_Enable ((uint32_t)0x00000040)
mbed_official	52:a51c77007319	569	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) \|\| \
mbed_official	52:a51c77007319	570	((STATE) == FSMC_ECC_Enable))
mbed_official	52:a51c77007319	571
mbed_official	52:a51c77007319	572	/**
mbed_official	52:a51c77007319	573	* @}
mbed_official	52:a51c77007319	574	*/
mbed_official	52:a51c77007319	575
mbed_official	52:a51c77007319	576	/** @defgroup FSMC_ECC_Page_Size
mbed_official	52:a51c77007319	577	* @{
mbed_official	52:a51c77007319	578	*/
mbed_official	52:a51c77007319	579
mbed_official	52:a51c77007319	580	#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
mbed_official	52:a51c77007319	581	#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
mbed_official	52:a51c77007319	582	#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
mbed_official	52:a51c77007319	583	#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
mbed_official	52:a51c77007319	584	#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
mbed_official	52:a51c77007319	585	#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
mbed_official	52:a51c77007319	586	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) \|\| \
mbed_official	52:a51c77007319	587	((SIZE) == FSMC_ECCPageSize_512Bytes) \|\| \
mbed_official	52:a51c77007319	588	((SIZE) == FSMC_ECCPageSize_1024Bytes) \|\| \
mbed_official	52:a51c77007319	589	((SIZE) == FSMC_ECCPageSize_2048Bytes) \|\| \
mbed_official	52:a51c77007319	590	((SIZE) == FSMC_ECCPageSize_4096Bytes) \|\| \
mbed_official	52:a51c77007319	591	((SIZE) == FSMC_ECCPageSize_8192Bytes))
mbed_official	52:a51c77007319	592
mbed_official	52:a51c77007319	593	/**
mbed_official	52:a51c77007319	594	* @}
mbed_official	52:a51c77007319	595	*/
mbed_official	52:a51c77007319	596
mbed_official	52:a51c77007319	597	/** @defgroup FSMC_TCLR_Setup_Time
mbed_official	52:a51c77007319	598	* @{
mbed_official	52:a51c77007319	599	*/
mbed_official	52:a51c77007319	600
mbed_official	52:a51c77007319	601	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	602
mbed_official	52:a51c77007319	603	/**
mbed_official	52:a51c77007319	604	* @}
mbed_official	52:a51c77007319	605	*/
mbed_official	52:a51c77007319	606
mbed_official	52:a51c77007319	607	/** @defgroup FSMC_TAR_Setup_Time
mbed_official	52:a51c77007319	608	* @{
mbed_official	52:a51c77007319	609	*/
mbed_official	52:a51c77007319	610
mbed_official	52:a51c77007319	611	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	612
mbed_official	52:a51c77007319	613	/**
mbed_official	52:a51c77007319	614	* @}
mbed_official	52:a51c77007319	615	*/
mbed_official	52:a51c77007319	616
mbed_official	52:a51c77007319	617	/** @defgroup FSMC_Setup_Time
mbed_official	52:a51c77007319	618	* @{
mbed_official	52:a51c77007319	619	*/
mbed_official	52:a51c77007319	620
mbed_official	52:a51c77007319	621	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	622
mbed_official	52:a51c77007319	623	/**
mbed_official	52:a51c77007319	624	* @}
mbed_official	52:a51c77007319	625	*/
mbed_official	52:a51c77007319	626
mbed_official	52:a51c77007319	627	/** @defgroup FSMC_Wait_Setup_Time
mbed_official	52:a51c77007319	628	* @{
mbed_official	52:a51c77007319	629	*/
mbed_official	52:a51c77007319	630
mbed_official	52:a51c77007319	631	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	632
mbed_official	52:a51c77007319	633	/**
mbed_official	52:a51c77007319	634	* @}
mbed_official	52:a51c77007319	635	*/
mbed_official	52:a51c77007319	636
mbed_official	52:a51c77007319	637	/** @defgroup FSMC_Hold_Setup_Time
mbed_official	52:a51c77007319	638	* @{
mbed_official	52:a51c77007319	639	*/
mbed_official	52:a51c77007319	640
mbed_official	52:a51c77007319	641	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	642
mbed_official	52:a51c77007319	643	/**
mbed_official	52:a51c77007319	644	* @}
mbed_official	52:a51c77007319	645	*/
mbed_official	52:a51c77007319	646
mbed_official	52:a51c77007319	647	/** @defgroup FSMC_HiZ_Setup_Time
mbed_official	52:a51c77007319	648	* @{
mbed_official	52:a51c77007319	649	*/
mbed_official	52:a51c77007319	650
mbed_official	52:a51c77007319	651	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
mbed_official	52:a51c77007319	652
mbed_official	52:a51c77007319	653	/**
mbed_official	52:a51c77007319	654	* @}
mbed_official	52:a51c77007319	655	*/
mbed_official	52:a51c77007319	656
mbed_official	52:a51c77007319	657	/** @defgroup FSMC_Interrupt_sources
mbed_official	52:a51c77007319	658	* @{
mbed_official	52:a51c77007319	659	*/
mbed_official	52:a51c77007319	660
mbed_official	52:a51c77007319	661	#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
mbed_official	52:a51c77007319	662	#define FSMC_IT_Level ((uint32_t)0x00000010)
mbed_official	52:a51c77007319	663	#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
mbed_official	52:a51c77007319	664	#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	52:a51c77007319	665	#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) \|\| \
mbed_official	52:a51c77007319	666	((IT) == FSMC_IT_Level) \|\| \
mbed_official	52:a51c77007319	667	((IT) == FSMC_IT_FallingEdge))
mbed_official	52:a51c77007319	668	/**
mbed_official	52:a51c77007319	669	* @}
mbed_official	52:a51c77007319	670	*/
mbed_official	52:a51c77007319	671
mbed_official	52:a51c77007319	672	/** @defgroup FSMC_Flags
mbed_official	52:a51c77007319	673	* @{
mbed_official	52:a51c77007319	674	*/
mbed_official	52:a51c77007319	675
mbed_official	52:a51c77007319	676	#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
mbed_official	52:a51c77007319	677	#define FSMC_FLAG_Level ((uint32_t)0x00000002)
mbed_official	52:a51c77007319	678	#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
mbed_official	52:a51c77007319	679	#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	52:a51c77007319	680	#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) \|\| \
mbed_official	52:a51c77007319	681	((FLAG) == FSMC_FLAG_Level) \|\| \
mbed_official	52:a51c77007319	682	((FLAG) == FSMC_FLAG_FallingEdge) \|\| \
mbed_official	52:a51c77007319	683	((FLAG) == FSMC_FLAG_FEMPT))
mbed_official	52:a51c77007319	684
mbed_official	52:a51c77007319	685	#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	52:a51c77007319	686
mbed_official	52:a51c77007319	687	/**
mbed_official	52:a51c77007319	688	* @}
mbed_official	52:a51c77007319	689	*/
mbed_official	52:a51c77007319	690
mbed_official	52:a51c77007319	691	/**
mbed_official	52:a51c77007319	692	* @}
mbed_official	52:a51c77007319	693	*/
mbed_official	52:a51c77007319	694
mbed_official	52:a51c77007319	695	/**
mbed_official	52:a51c77007319	696	* @}
mbed_official	52:a51c77007319	697	*/
mbed_official	52:a51c77007319	698
mbed_official	52:a51c77007319	699	/** @defgroup FSMC_Exported_Macros
mbed_official	52:a51c77007319	700	* @{
mbed_official	52:a51c77007319	701	*/
mbed_official	52:a51c77007319	702
mbed_official	52:a51c77007319	703	/**
mbed_official	52:a51c77007319	704	* @}
mbed_official	52:a51c77007319	705	*/
mbed_official	52:a51c77007319	706
mbed_official	52:a51c77007319	707	/** @defgroup FSMC_Exported_Functions
mbed_official	52:a51c77007319	708	* @{
mbed_official	52:a51c77007319	709	*/
mbed_official	52:a51c77007319	710
mbed_official	52:a51c77007319	711	void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
mbed_official	52:a51c77007319	712	void FSMC_NANDDeInit(uint32_t FSMC_Bank);
mbed_official	52:a51c77007319	713	void FSMC_PCCARDDeInit(void);
mbed_official	52:a51c77007319	714	void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official	52:a51c77007319	715	void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official	52:a51c77007319	716	void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official	52:a51c77007319	717	void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official	52:a51c77007319	718	void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official	52:a51c77007319	719	void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official	52:a51c77007319	720	void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official	52:a51c77007319	721	void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official	52:a51c77007319	722	void FSMC_PCCARDCmd(FunctionalState NewState);
mbed_official	52:a51c77007319	723	void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official	52:a51c77007319	724	uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
mbed_official	52:a51c77007319	725	void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
mbed_official	52:a51c77007319	726	FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official	52:a51c77007319	727	void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official	52:a51c77007319	728	ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official	52:a51c77007319	729	void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official	52:a51c77007319	730
mbed_official	52:a51c77007319	731	#ifdef __cplusplus
mbed_official	52:a51c77007319	732	}
mbed_official	52:a51c77007319	733	#endif
mbed_official	52:a51c77007319	734
mbed_official	52:a51c77007319	735	#endif /__STM32F10x_FSMC_H /
mbed_official	52:a51c77007319	736	/**
mbed_official	52:a51c77007319	737	* @}
mbed_official	52:a51c77007319	738	*/
mbed_official	52:a51c77007319	739
mbed_official	52:a51c77007319	740	/**
mbed_official	52:a51c77007319	741	* @}
mbed_official	52:a51c77007319	742	*/
mbed_official	52:a51c77007319	743
mbed_official	52:a51c77007319	744	/**
mbed_official	52:a51c77007319	745	* @}
mbed_official	52:a51c77007319	746	*/
mbed_official	52:a51c77007319	747
mbed_official	84:f54042cbc282	748	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/