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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@605:ded2017be6ab, 2015-08-13 (annotated)

Committer:
mbed_official
Date:
Thu Aug 13 11:30:09 2015 +0100
Revision:
605:ded2017be6ab
Parent:
245:b4dea936db71 
Synchronized with git revision 163a66abdd17c224129f0199f6ed2f3c626cacab



Full URL: https://github.com/mbedmicro/mbed/commit/163a66abdd17c224129f0199f6ed2f3c626cacab/



STMF4 - pwmout_api.c freq fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 103:9b881da47c92 1
mbed_official 103:9b881da47c92 2 /****************************************************************************************************//**
mbed_official 103:9b881da47c92 3 * @file LPC15xx.h
mbed_official 103:9b881da47c92 4 *
mbed_official 103:9b881da47c92 5 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
mbed_official 103:9b881da47c92 6 * LPC15xx from .
mbed_official 103:9b881da47c92 7 *
mbed_official 103:9b881da47c92 8 * @version V0.3
mbed_official 103:9b881da47c92 9 * @date 17. July 2013
mbed_official 103:9b881da47c92 10 *
mbed_official 103:9b881da47c92 11 * @note Generated with SVDConv V2.80
mbed_official 103:9b881da47c92 12 * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
mbed_official 103:9b881da47c92 13 *
mbed_official 103:9b881da47c92 14 * modified by Keil
mbed_official 103:9b881da47c92 15 * modified by ytsuboi
mbed_official 103:9b881da47c92 16 *******************************************************************************************************/
mbed_official 103:9b881da47c92 17
mbed_official 103:9b881da47c92 18
mbed_official 103:9b881da47c92 19
mbed_official 103:9b881da47c92 20 /** @addtogroup (null)
mbed_official 103:9b881da47c92 21 * @{
mbed_official 103:9b881da47c92 22 */
mbed_official 103:9b881da47c92 23
mbed_official 103:9b881da47c92 24 /** @addtogroup LPC15xx
mbed_official 103:9b881da47c92 25 * @{
mbed_official 103:9b881da47c92 26 */
mbed_official 103:9b881da47c92 27
mbed_official 103:9b881da47c92 28 #ifndef LPC15XX_H
mbed_official 103:9b881da47c92 29 #define LPC15XX_H
mbed_official 103:9b881da47c92 30
mbed_official 103:9b881da47c92 31 #ifdef __cplusplus
mbed_official 103:9b881da47c92 32 extern "C" {
mbed_official 103:9b881da47c92 33 #endif
mbed_official 103:9b881da47c92 34
mbed_official 103:9b881da47c92 35
mbed_official 103:9b881da47c92 36 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 103:9b881da47c92 37
mbed_official 103:9b881da47c92 38 typedef enum {
mbed_official 103:9b881da47c92 39 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
mbed_official 103:9b881da47c92 40 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
mbed_official 103:9b881da47c92 41 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official 103:9b881da47c92 42 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
mbed_official 103:9b881da47c92 43 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
mbed_official 103:9b881da47c92 44 and No Match */
mbed_official 103:9b881da47c92 45 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
mbed_official 103:9b881da47c92 46 related Fault */
mbed_official 103:9b881da47c92 47 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
mbed_official 103:9b881da47c92 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
mbed_official 103:9b881da47c92 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
mbed_official 103:9b881da47c92 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
mbed_official 103:9b881da47c92 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
mbed_official 103:9b881da47c92 52 /* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
mbed_official 103:9b881da47c92 53 WDT_IRQn = 0, /*!< 0 WDT */
mbed_official 103:9b881da47c92 54 BOD_IRQn = 1, /*!< 1 BOD */
mbed_official 103:9b881da47c92 55 FLASH_IRQn = 2, /*!< 2 FLASH */
mbed_official 103:9b881da47c92 56 EE_IRQn = 3, /*!< 3 EE */
mbed_official 103:9b881da47c92 57 DMA_IRQn = 4, /*!< 4 DMA */
mbed_official 103:9b881da47c92 58 GINT0_IRQn = 5, /*!< 5 GINT0 */
mbed_official 103:9b881da47c92 59 GINT1_IRQn = 6, /*!< 6 GINT1 */
mbed_official 103:9b881da47c92 60 PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */
mbed_official 103:9b881da47c92 61 PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */
mbed_official 103:9b881da47c92 62 PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */
mbed_official 103:9b881da47c92 63 PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */
mbed_official 103:9b881da47c92 64 PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */
mbed_official 103:9b881da47c92 65 PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */
mbed_official 103:9b881da47c92 66 PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */
mbed_official 103:9b881da47c92 67 PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */
mbed_official 103:9b881da47c92 68 RIT_IRQn = 15, /*!< 15 RIT */
mbed_official 103:9b881da47c92 69 SCT0_IRQn = 16, /*!< 16 SCT0 */
mbed_official 103:9b881da47c92 70 SCT1_IRQn = 17, /*!< 17 SCT1 */
mbed_official 103:9b881da47c92 71 SCT2_IRQn = 18, /*!< 18 SCT2 */
mbed_official 103:9b881da47c92 72 SCT3_IRQn = 19, /*!< 19 SCT3 */
mbed_official 103:9b881da47c92 73 MRT_IRQn = 20, /*!< 20 MRT */
mbed_official 103:9b881da47c92 74 UART0_IRQn = 21, /*!< 21 UART0 */
mbed_official 103:9b881da47c92 75 UART1_IRQn = 22, /*!< 22 UART1 */
mbed_official 103:9b881da47c92 76 UART2_IRQn = 23, /*!< 23 UART2 */
mbed_official 103:9b881da47c92 77 I2C0_IRQn = 24, /*!< 24 I2C0 */
mbed_official 103:9b881da47c92 78 SPI0_IRQn = 25, /*!< 25 SPI0 */
mbed_official 103:9b881da47c92 79 SPI1_IRQn = 26, /*!< 26 SPI1 */
mbed_official 103:9b881da47c92 80 C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */
mbed_official 103:9b881da47c92 81 USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */
mbed_official 103:9b881da47c92 82 USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */
mbed_official 103:9b881da47c92 83 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
mbed_official 103:9b881da47c92 84 ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */
mbed_official 103:9b881da47c92 85 ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */
mbed_official 103:9b881da47c92 86 ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */
mbed_official 103:9b881da47c92 87 ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */
mbed_official 103:9b881da47c92 88 ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */
mbed_official 103:9b881da47c92 89 ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */
mbed_official 103:9b881da47c92 90 ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */
mbed_official 103:9b881da47c92 91 ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */
mbed_official 103:9b881da47c92 92 DAC_IRQn = 39, /*!< 39 DAC */
mbed_official 103:9b881da47c92 93 CMP0_IRQn = 40, /*!< 40 CMP0 */
mbed_official 103:9b881da47c92 94 CMP1_IRQn = 41, /*!< 41 CMP1 */
mbed_official 103:9b881da47c92 95 CMP2_IRQn = 42, /*!< 42 CMP2 */
mbed_official 103:9b881da47c92 96 CMP3_IRQn = 43, /*!< 43 CMP3 */
mbed_official 103:9b881da47c92 97 QEI_IRQn = 44, /*!< 44 QEI */
mbed_official 103:9b881da47c92 98 RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */
mbed_official 103:9b881da47c92 99 RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */
mbed_official 103:9b881da47c92 100 } IRQn_Type;
mbed_official 103:9b881da47c92 101
mbed_official 103:9b881da47c92 102
mbed_official 103:9b881da47c92 103 /** @addtogroup Configuration_of_CMSIS
mbed_official 103:9b881da47c92 104 * @{
mbed_official 103:9b881da47c92 105 */
mbed_official 103:9b881da47c92 106
mbed_official 103:9b881da47c92 107
mbed_official 103:9b881da47c92 108 /* ================================================================================ */
mbed_official 103:9b881da47c92 109 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 103:9b881da47c92 110 /* ================================================================================ */
mbed_official 103:9b881da47c92 111
mbed_official 103:9b881da47c92 112 /* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
mbed_official 103:9b881da47c92 113 #define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
mbed_official 103:9b881da47c92 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 103:9b881da47c92 115 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
mbed_official 103:9b881da47c92 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 103:9b881da47c92 117 /** @} */ /* End of group Configuration_of_CMSIS */
mbed_official 103:9b881da47c92 118
mbed_official 103:9b881da47c92 119 #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
mbed_official 103:9b881da47c92 120 #include "system_LPC15xx.h" /*!< LPC15xx System */
mbed_official 103:9b881da47c92 121
mbed_official 103:9b881da47c92 122
mbed_official 103:9b881da47c92 123 /* ================================================================================ */
mbed_official 103:9b881da47c92 124 /* ================ Device Specific Peripheral Section ================ */
mbed_official 103:9b881da47c92 125 /* ================================================================================ */
mbed_official 103:9b881da47c92 126
mbed_official 103:9b881da47c92 127
mbed_official 103:9b881da47c92 128 /** @addtogroup Device_Peripheral_Registers
mbed_official 103:9b881da47c92 129 * @{
mbed_official 103:9b881da47c92 130 */
mbed_official 103:9b881da47c92 131
mbed_official 103:9b881da47c92 132
mbed_official 103:9b881da47c92 133 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 103:9b881da47c92 134 #if defined(__CC_ARM)
mbed_official 103:9b881da47c92 135 #pragma push
mbed_official 103:9b881da47c92 136 #pragma anon_unions
mbed_official 103:9b881da47c92 137 #elif defined(__ICCARM__)
mbed_official 103:9b881da47c92 138 #pragma language=extended
mbed_official 103:9b881da47c92 139 #elif defined(__GNUC__)
mbed_official 103:9b881da47c92 140 /* anonymous unions are enabled by default */
mbed_official 103:9b881da47c92 141 #elif defined(__TMS470__)
mbed_official 103:9b881da47c92 142 /* anonymous unions are enabled by default */
mbed_official 103:9b881da47c92 143 #elif defined(__TASKING__)
mbed_official 103:9b881da47c92 144 #pragma warning 586
mbed_official 103:9b881da47c92 145 #else
mbed_official 103:9b881da47c92 146 #warning Not supported compiler type
mbed_official 103:9b881da47c92 147 #endif
mbed_official 103:9b881da47c92 148
mbed_official 103:9b881da47c92 149
mbed_official 103:9b881da47c92 150
mbed_official 103:9b881da47c92 151 /* ================================================================================ */
mbed_official 103:9b881da47c92 152 /* ================ GPIO_PORT ================ */
mbed_official 103:9b881da47c92 153 /* ================================================================================ */
mbed_official 103:9b881da47c92 154
mbed_official 103:9b881da47c92 155
mbed_official 103:9b881da47c92 156 /**
mbed_official 103:9b881da47c92 157 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
mbed_official 103:9b881da47c92 158 */
mbed_official 103:9b881da47c92 159
mbed_official 103:9b881da47c92 160 typedef struct { /*!< GPIO_PORT Structure */
mbed_official 103:9b881da47c92 161 __IO uint8_t B[76]; /*!< Byte pin registers */
mbed_official 605:ded2017be6ab 162 __I uint32_t RESERVED0[1005];
mbed_official 103:9b881da47c92 163 __IO uint32_t W[76]; /*!< Word pin registers */
mbed_official 605:ded2017be6ab 164 __I uint32_t RESERVED1[948];
mbed_official 103:9b881da47c92 165 __IO uint32_t DIR[3]; /*!< Port Direction registers */
mbed_official 103:9b881da47c92 166 __I uint32_t RESERVED2[29];
mbed_official 103:9b881da47c92 167 __IO uint32_t MASK[3]; /*!< Port Mask register */
mbed_official 103:9b881da47c92 168 __I uint32_t RESERVED3[29];
mbed_official 103:9b881da47c92 169 __IO uint32_t PIN[3]; /*!< Port pin register */
mbed_official 103:9b881da47c92 170 __I uint32_t RESERVED4[29];
mbed_official 103:9b881da47c92 171 __IO uint32_t MPIN[3]; /*!< Masked port register */
mbed_official 103:9b881da47c92 172 __I uint32_t RESERVED5[29];
mbed_official 103:9b881da47c92 173 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
mbed_official 103:9b881da47c92 174 __I uint32_t RESERVED6[29];
mbed_official 103:9b881da47c92 175 __O uint32_t CLR[3]; /*!< Clear port */
mbed_official 103:9b881da47c92 176 __I uint32_t RESERVED7[29];
mbed_official 103:9b881da47c92 177 __O uint32_t NOT[3]; /*!< Toggle port */
mbed_official 103:9b881da47c92 178 } LPC_GPIO_PORT_Type;
mbed_official 103:9b881da47c92 179
mbed_official 103:9b881da47c92 180
mbed_official 103:9b881da47c92 181 /* ================================================================================ */
mbed_official 103:9b881da47c92 182 /* ================ DMA ================ */
mbed_official 103:9b881da47c92 183 /* ================================================================================ */
mbed_official 103:9b881da47c92 184
mbed_official 103:9b881da47c92 185
mbed_official 103:9b881da47c92 186 /**
mbed_official 103:9b881da47c92 187 * @brief DMA controller (DMA)
mbed_official 103:9b881da47c92 188 */
mbed_official 103:9b881da47c92 189
mbed_official 103:9b881da47c92 190 typedef struct { /*!< DMA Structure */
mbed_official 103:9b881da47c92 191 __IO uint32_t CTRL; /*!< DMA control. */
mbed_official 103:9b881da47c92 192 __I uint32_t INTSTAT; /*!< Interrupt status. */
mbed_official 103:9b881da47c92 193 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
mbed_official 103:9b881da47c92 194 __I uint32_t RESERVED0[5];
mbed_official 103:9b881da47c92 195 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
mbed_official 103:9b881da47c92 196 __I uint32_t RESERVED1;
mbed_official 103:9b881da47c92 197 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
mbed_official 103:9b881da47c92 198 __I uint32_t RESERVED2;
mbed_official 103:9b881da47c92 199 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
mbed_official 103:9b881da47c92 200 __I uint32_t RESERVED3;
mbed_official 103:9b881da47c92 201 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
mbed_official 103:9b881da47c92 202 __I uint32_t RESERVED4;
mbed_official 103:9b881da47c92 203 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
mbed_official 103:9b881da47c92 204 __I uint32_t RESERVED5;
mbed_official 103:9b881da47c92 205 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
mbed_official 103:9b881da47c92 206 __I uint32_t RESERVED6;
mbed_official 103:9b881da47c92 207 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
mbed_official 103:9b881da47c92 208 __I uint32_t RESERVED7;
mbed_official 103:9b881da47c92 209 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
mbed_official 103:9b881da47c92 210 __I uint32_t RESERVED8;
mbed_official 103:9b881da47c92 211 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
mbed_official 103:9b881da47c92 212 __I uint32_t RESERVED9;
mbed_official 103:9b881da47c92 213 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
mbed_official 103:9b881da47c92 214 __I uint32_t RESERVED10;
mbed_official 103:9b881da47c92 215 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
mbed_official 103:9b881da47c92 216 __I uint32_t RESERVED11;
mbed_official 103:9b881da47c92 217 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
mbed_official 103:9b881da47c92 218 __I uint32_t RESERVED12[225];
mbed_official 103:9b881da47c92 219 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 220 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 221 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 222 __I uint32_t RESERVED13;
mbed_official 103:9b881da47c92 223 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 224 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 225 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 226 __I uint32_t RESERVED14;
mbed_official 103:9b881da47c92 227 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 228 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 229 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 230 __I uint32_t RESERVED15;
mbed_official 103:9b881da47c92 231 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 232 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 233 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 234 __I uint32_t RESERVED16;
mbed_official 103:9b881da47c92 235 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 236 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 237 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 238 __I uint32_t RESERVED17;
mbed_official 103:9b881da47c92 239 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 240 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 241 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 242 __I uint32_t RESERVED18;
mbed_official 103:9b881da47c92 243 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 244 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 245 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 246 __I uint32_t RESERVED19;
mbed_official 103:9b881da47c92 247 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 248 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 249 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 250 __I uint32_t RESERVED20;
mbed_official 103:9b881da47c92 251 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 252 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 253 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 254 __I uint32_t RESERVED21;
mbed_official 103:9b881da47c92 255 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 256 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 257 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 258 __I uint32_t RESERVED22;
mbed_official 103:9b881da47c92 259 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 260 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 261 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 262 __I uint32_t RESERVED23;
mbed_official 103:9b881da47c92 263 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 264 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 265 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 266 __I uint32_t RESERVED24;
mbed_official 103:9b881da47c92 267 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 268 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 269 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 270 __I uint32_t RESERVED25;
mbed_official 103:9b881da47c92 271 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 272 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 273 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 274 __I uint32_t RESERVED26;
mbed_official 103:9b881da47c92 275 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 276 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 277 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 278 __I uint32_t RESERVED27;
mbed_official 103:9b881da47c92 279 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 280 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 281 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 282 __I uint32_t RESERVED28;
mbed_official 103:9b881da47c92 283 __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 284 __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 285 __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 286 __I uint32_t RESERVED29;
mbed_official 103:9b881da47c92 287 __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 288 __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */
mbed_official 103:9b881da47c92 289 __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */
mbed_official 103:9b881da47c92 290 } LPC_DMA_Type;
mbed_official 103:9b881da47c92 291
mbed_official 103:9b881da47c92 292
mbed_official 103:9b881da47c92 293 /* ================================================================================ */
mbed_official 103:9b881da47c92 294 /* ================ USB ================ */
mbed_official 103:9b881da47c92 295 /* ================================================================================ */
mbed_official 103:9b881da47c92 296
mbed_official 103:9b881da47c92 297
mbed_official 103:9b881da47c92 298 /**
mbed_official 103:9b881da47c92 299 * @brief USB device controller (USB)
mbed_official 103:9b881da47c92 300 */
mbed_official 103:9b881da47c92 301
mbed_official 103:9b881da47c92 302 typedef struct { /*!< USB Structure */
mbed_official 103:9b881da47c92 303 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
mbed_official 103:9b881da47c92 304 __IO uint32_t INFO; /*!< USB Info register */
mbed_official 103:9b881da47c92 305 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
mbed_official 103:9b881da47c92 306 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
mbed_official 103:9b881da47c92 307 __IO uint32_t LPM; /*!< Link Power Management register */
mbed_official 103:9b881da47c92 308 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
mbed_official 103:9b881da47c92 309 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
mbed_official 103:9b881da47c92 310 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
mbed_official 103:9b881da47c92 311 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
mbed_official 103:9b881da47c92 312 __IO uint32_t INTEN; /*!< USB interrupt enable register */
mbed_official 103:9b881da47c92 313 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
mbed_official 103:9b881da47c92 314 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
mbed_official 103:9b881da47c92 315 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 316 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
mbed_official 103:9b881da47c92 317 } LPC_USB_Type;
mbed_official 103:9b881da47c92 318
mbed_official 103:9b881da47c92 319
mbed_official 103:9b881da47c92 320 /* ================================================================================ */
mbed_official 103:9b881da47c92 321 /* ================ CRC ================ */
mbed_official 103:9b881da47c92 322 /* ================================================================================ */
mbed_official 103:9b881da47c92 323
mbed_official 103:9b881da47c92 324
mbed_official 103:9b881da47c92 325 /**
mbed_official 103:9b881da47c92 326 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
mbed_official 103:9b881da47c92 327 */
mbed_official 103:9b881da47c92 328
mbed_official 103:9b881da47c92 329 typedef struct { /*!< CRC Structure */
mbed_official 103:9b881da47c92 330 __IO uint32_t MODE; /*!< CRC mode register */
mbed_official 103:9b881da47c92 331 __IO uint32_t SEED; /*!< CRC seed register */
mbed_official 103:9b881da47c92 332
mbed_official 103:9b881da47c92 333 union {
mbed_official 103:9b881da47c92 334 __O uint32_t WR_DATA; /*!< CRC data register */
mbed_official 103:9b881da47c92 335 __I uint32_t SUM; /*!< CRC checksum register */
mbed_official 103:9b881da47c92 336 };
mbed_official 103:9b881da47c92 337 } LPC_CRC_Type;
mbed_official 103:9b881da47c92 338
mbed_official 103:9b881da47c92 339
mbed_official 103:9b881da47c92 340 /* ================================================================================ */
mbed_official 103:9b881da47c92 341 /* ================ SCT0 ================ */
mbed_official 103:9b881da47c92 342 /* ================================================================================ */
mbed_official 103:9b881da47c92 343
mbed_official 103:9b881da47c92 344
mbed_official 103:9b881da47c92 345 /**
mbed_official 103:9b881da47c92 346 * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
mbed_official 103:9b881da47c92 347 */
mbed_official 103:9b881da47c92 348
mbed_official 103:9b881da47c92 349 typedef struct { /*!< SCT0 Structure */
mbed_official 103:9b881da47c92 350 __IO uint32_t CONFIG; /*!< SCT configuration register */
mbed_official 103:9b881da47c92 351 __IO uint32_t CTRL; /*!< SCT control register */
mbed_official 103:9b881da47c92 352 __IO uint32_t LIMIT; /*!< SCT limit register */
mbed_official 103:9b881da47c92 353 __IO uint32_t HALT; /*!< SCT halt condition register */
mbed_official 103:9b881da47c92 354 __IO uint32_t STOP; /*!< SCT stop condition register */
mbed_official 103:9b881da47c92 355 __IO uint32_t START; /*!< SCT start condition register */
mbed_official 103:9b881da47c92 356 __IO uint32_t DITHER; /*!< SCT dither condition register */
mbed_official 103:9b881da47c92 357 __I uint32_t RESERVED0[9];
mbed_official 103:9b881da47c92 358 __IO uint32_t COUNT; /*!< SCT counter register */
mbed_official 103:9b881da47c92 359 __IO uint32_t STATE; /*!< SCT state register */
mbed_official 103:9b881da47c92 360 __I uint32_t INPUT; /*!< SCT input register */
mbed_official 103:9b881da47c92 361 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
mbed_official 103:9b881da47c92 362 __IO uint32_t OUTPUT; /*!< SCT output register */
mbed_official 103:9b881da47c92 363 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
mbed_official 103:9b881da47c92 364 __IO uint32_t RES; /*!< SCT conflict resolution register */
mbed_official 103:9b881da47c92 365 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
mbed_official 103:9b881da47c92 366 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
mbed_official 103:9b881da47c92 367 __I uint32_t RESERVED1[35];
mbed_official 103:9b881da47c92 368 __IO uint32_t EVEN; /*!< SCT event enable register */
mbed_official 103:9b881da47c92 369 __IO uint32_t EVFLAG; /*!< SCT event flag register */
mbed_official 103:9b881da47c92 370 __IO uint32_t CONEN; /*!< SCT conflict enable register */
mbed_official 103:9b881da47c92 371 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
mbed_official 103:9b881da47c92 372
mbed_official 103:9b881da47c92 373 union {
mbed_official 103:9b881da47c92 374 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 375 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 376 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 377 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 378 };
mbed_official 103:9b881da47c92 379
mbed_official 103:9b881da47c92 380 union {
mbed_official 103:9b881da47c92 381 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 382 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 383 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 384 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 385 };
mbed_official 103:9b881da47c92 386
mbed_official 103:9b881da47c92 387 union {
mbed_official 103:9b881da47c92 388 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 389 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 390 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 391 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 392 };
mbed_official 103:9b881da47c92 393
mbed_official 103:9b881da47c92 394 union {
mbed_official 103:9b881da47c92 395 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 396 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 397 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 398 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 399 };
mbed_official 103:9b881da47c92 400
mbed_official 103:9b881da47c92 401 union {
mbed_official 103:9b881da47c92 402 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 403 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 404 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 405 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 406 };
mbed_official 103:9b881da47c92 407
mbed_official 103:9b881da47c92 408 union {
mbed_official 103:9b881da47c92 409 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 410 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 411 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 412 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 413 };
mbed_official 103:9b881da47c92 414
mbed_official 103:9b881da47c92 415 union {
mbed_official 103:9b881da47c92 416 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 417 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 418 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 419 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 420 };
mbed_official 103:9b881da47c92 421
mbed_official 103:9b881da47c92 422 union {
mbed_official 103:9b881da47c92 423 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 424 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 425 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 426 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 427 };
mbed_official 103:9b881da47c92 428
mbed_official 103:9b881da47c92 429 union {
mbed_official 103:9b881da47c92 430 __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 431 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 432 __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 433 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 434 };
mbed_official 103:9b881da47c92 435
mbed_official 103:9b881da47c92 436 union {
mbed_official 103:9b881da47c92 437 __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 438 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 439 __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 440 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 441 };
mbed_official 103:9b881da47c92 442
mbed_official 103:9b881da47c92 443 union {
mbed_official 103:9b881da47c92 444 __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 445 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 446 __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 447 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 448 };
mbed_official 103:9b881da47c92 449
mbed_official 103:9b881da47c92 450 union {
mbed_official 103:9b881da47c92 451 __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 452 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 453 __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 454 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 455 };
mbed_official 103:9b881da47c92 456
mbed_official 103:9b881da47c92 457 union {
mbed_official 103:9b881da47c92 458 __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 459 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 460 __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 461 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 462 };
mbed_official 103:9b881da47c92 463
mbed_official 103:9b881da47c92 464 union {
mbed_official 103:9b881da47c92 465 __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 466 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 467 __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 468 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 469 };
mbed_official 103:9b881da47c92 470
mbed_official 103:9b881da47c92 471 union {
mbed_official 103:9b881da47c92 472 __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 473 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 474 __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 475 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 476 };
mbed_official 103:9b881da47c92 477
mbed_official 103:9b881da47c92 478 union {
mbed_official 103:9b881da47c92 479 __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
mbed_official 103:9b881da47c92 480 to REGMODE15 = 0 */
mbed_official 103:9b881da47c92 481 __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
mbed_official 103:9b881da47c92 482 REGMODE15 = 1 */
mbed_official 103:9b881da47c92 483 };
mbed_official 103:9b881da47c92 484 __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 485 0 to 5. */
mbed_official 103:9b881da47c92 486 __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 487 0 to 5. */
mbed_official 103:9b881da47c92 488 __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 489 0 to 5. */
mbed_official 103:9b881da47c92 490 __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 491 0 to 5. */
mbed_official 103:9b881da47c92 492 __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 493 0 to 5. */
mbed_official 103:9b881da47c92 494 __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
mbed_official 103:9b881da47c92 495 0 to 5. */
mbed_official 103:9b881da47c92 496 __I uint32_t RESERVED2[42];
mbed_official 103:9b881da47c92 497
mbed_official 103:9b881da47c92 498 union {
mbed_official 103:9b881da47c92 499 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 500 = 1 */
mbed_official 103:9b881da47c92 501 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 502 = 0 */
mbed_official 103:9b881da47c92 503 };
mbed_official 103:9b881da47c92 504
mbed_official 103:9b881da47c92 505 union {
mbed_official 103:9b881da47c92 506 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 507 = 0 */
mbed_official 103:9b881da47c92 508 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 509 = 1 */
mbed_official 103:9b881da47c92 510 };
mbed_official 103:9b881da47c92 511
mbed_official 103:9b881da47c92 512 union {
mbed_official 103:9b881da47c92 513 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 514 = 0 */
mbed_official 103:9b881da47c92 515 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 516 = 1 */
mbed_official 103:9b881da47c92 517 };
mbed_official 103:9b881da47c92 518
mbed_official 103:9b881da47c92 519 union {
mbed_official 103:9b881da47c92 520 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 521 = 1 */
mbed_official 103:9b881da47c92 522 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 523 = 0 */
mbed_official 103:9b881da47c92 524 };
mbed_official 103:9b881da47c92 525
mbed_official 103:9b881da47c92 526 union {
mbed_official 103:9b881da47c92 527 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 528 = 1 */
mbed_official 103:9b881da47c92 529 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 530 = 0 */
mbed_official 103:9b881da47c92 531 };
mbed_official 103:9b881da47c92 532
mbed_official 103:9b881da47c92 533 union {
mbed_official 103:9b881da47c92 534 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 535 = 1 */
mbed_official 103:9b881da47c92 536 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 537 = 0 */
mbed_official 103:9b881da47c92 538 };
mbed_official 103:9b881da47c92 539
mbed_official 103:9b881da47c92 540 union {
mbed_official 103:9b881da47c92 541 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 542 = 0 */
mbed_official 103:9b881da47c92 543 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 544 = 1 */
mbed_official 103:9b881da47c92 545 };
mbed_official 103:9b881da47c92 546
mbed_official 103:9b881da47c92 547 union {
mbed_official 103:9b881da47c92 548 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 549 = 0 */
mbed_official 103:9b881da47c92 550 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 551 = 1 */
mbed_official 103:9b881da47c92 552 };
mbed_official 103:9b881da47c92 553
mbed_official 103:9b881da47c92 554 union {
mbed_official 103:9b881da47c92 555 __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 556 = 1 */
mbed_official 103:9b881da47c92 557 __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 558 = 0 */
mbed_official 103:9b881da47c92 559 };
mbed_official 103:9b881da47c92 560
mbed_official 103:9b881da47c92 561 union {
mbed_official 103:9b881da47c92 562 __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 563 = 1 */
mbed_official 103:9b881da47c92 564 __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 565 = 0 */
mbed_official 103:9b881da47c92 566 };
mbed_official 103:9b881da47c92 567
mbed_official 103:9b881da47c92 568 union {
mbed_official 103:9b881da47c92 569 __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 570 = 1 */
mbed_official 103:9b881da47c92 571 __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 572 = 0 */
mbed_official 103:9b881da47c92 573 };
mbed_official 103:9b881da47c92 574
mbed_official 103:9b881da47c92 575 union {
mbed_official 103:9b881da47c92 576 __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 577 = 1 */
mbed_official 103:9b881da47c92 578 __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 579 = 0 */
mbed_official 103:9b881da47c92 580 };
mbed_official 103:9b881da47c92 581
mbed_official 103:9b881da47c92 582 union {
mbed_official 103:9b881da47c92 583 __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 584 = 0 */
mbed_official 103:9b881da47c92 585 __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 586 = 1 */
mbed_official 103:9b881da47c92 587 };
mbed_official 103:9b881da47c92 588
mbed_official 103:9b881da47c92 589 union {
mbed_official 103:9b881da47c92 590 __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 591 = 0 */
mbed_official 103:9b881da47c92 592 __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 593 = 1 */
mbed_official 103:9b881da47c92 594 };
mbed_official 103:9b881da47c92 595
mbed_official 103:9b881da47c92 596 union {
mbed_official 103:9b881da47c92 597 __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 598 = 1 */
mbed_official 103:9b881da47c92 599 __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 600 = 0 */
mbed_official 103:9b881da47c92 601 };
mbed_official 103:9b881da47c92 602
mbed_official 103:9b881da47c92 603 union {
mbed_official 103:9b881da47c92 604 __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
mbed_official 103:9b881da47c92 605 = 1 */
mbed_official 103:9b881da47c92 606 __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
mbed_official 103:9b881da47c92 607 = 0 */
mbed_official 103:9b881da47c92 608 };
mbed_official 103:9b881da47c92 609 __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 610 registers 0 to 5. */
mbed_official 103:9b881da47c92 611 __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 612 registers 0 to 5. */
mbed_official 103:9b881da47c92 613 __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 614 registers 0 to 5. */
mbed_official 103:9b881da47c92 615 __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 616 registers 0 to 5. */
mbed_official 103:9b881da47c92 617 __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 618 registers 0 to 5. */
mbed_official 103:9b881da47c92 619 __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
mbed_official 103:9b881da47c92 620 registers 0 to 5. */
mbed_official 103:9b881da47c92 621 __I uint32_t RESERVED3[42];
mbed_official 103:9b881da47c92 622 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 623 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 624 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 625 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 626 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 627 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 628 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 629 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 630 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 631 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 632 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 633 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 634 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 635 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 636 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 637 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 638 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 639 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 640 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 641 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 642 __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 643 __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 644 __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 645 __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 646 __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 647 __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 648 __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 649 __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 650 __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 651 __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 652 __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 653 __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 654 __I uint32_t RESERVED4[96];
mbed_official 103:9b881da47c92 655 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 656 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 657 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 658 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 659 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 660 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 661 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 662 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 663 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 664 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 665 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 666 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 667 __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 668 __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 669 __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 670 __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 671 __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 672 __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 673 __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 674 __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 675 } LPC_SCT0_Type;
mbed_official 103:9b881da47c92 676
mbed_official 103:9b881da47c92 677
mbed_official 103:9b881da47c92 678 /* ================================================================================ */
mbed_official 103:9b881da47c92 679 /* ================ SCT2 ================ */
mbed_official 103:9b881da47c92 680 /* ================================================================================ */
mbed_official 103:9b881da47c92 681
mbed_official 103:9b881da47c92 682
mbed_official 103:9b881da47c92 683 /**
mbed_official 103:9b881da47c92 684 * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
mbed_official 103:9b881da47c92 685 */
mbed_official 103:9b881da47c92 686
mbed_official 103:9b881da47c92 687 typedef struct { /*!< SCT2 Structure */
mbed_official 103:9b881da47c92 688 __IO uint32_t CONFIG; /*!< SCT configuration register */
mbed_official 103:9b881da47c92 689 __IO uint32_t CTRL; /*!< SCT control register */
mbed_official 103:9b881da47c92 690 __IO uint32_t LIMIT; /*!< SCT limit register */
mbed_official 103:9b881da47c92 691 __IO uint32_t HALT; /*!< SCT halt condition register */
mbed_official 103:9b881da47c92 692 __IO uint32_t STOP; /*!< SCT stop condition register */
mbed_official 103:9b881da47c92 693 __IO uint32_t START; /*!< SCT start condition register */
mbed_official 103:9b881da47c92 694 __I uint32_t RESERVED0[10];
mbed_official 103:9b881da47c92 695 __IO uint32_t COUNT; /*!< SCT counter register */
mbed_official 103:9b881da47c92 696 __IO uint32_t STATE; /*!< SCT state register */
mbed_official 103:9b881da47c92 697 __I uint32_t INPUT; /*!< SCT input register */
mbed_official 103:9b881da47c92 698 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
mbed_official 103:9b881da47c92 699 __IO uint32_t OUTPUT; /*!< SCT output register */
mbed_official 103:9b881da47c92 700 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
mbed_official 103:9b881da47c92 701 __IO uint32_t RES; /*!< SCT conflict resolution register */
mbed_official 103:9b881da47c92 702 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
mbed_official 103:9b881da47c92 703 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
mbed_official 103:9b881da47c92 704 __I uint32_t RESERVED1[35];
mbed_official 103:9b881da47c92 705 __IO uint32_t EVEN; /*!< SCT event enable register */
mbed_official 103:9b881da47c92 706 __IO uint32_t EVFLAG; /*!< SCT event flag register */
mbed_official 103:9b881da47c92 707 __IO uint32_t CONEN; /*!< SCT conflict enable register */
mbed_official 103:9b881da47c92 708 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
mbed_official 103:9b881da47c92 709
mbed_official 103:9b881da47c92 710 union {
mbed_official 103:9b881da47c92 711 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 712 = 1 */
mbed_official 103:9b881da47c92 713 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 714 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 715 };
mbed_official 103:9b881da47c92 716
mbed_official 103:9b881da47c92 717 union {
mbed_official 103:9b881da47c92 718 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 719 = 1 */
mbed_official 103:9b881da47c92 720 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 721 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 722 };
mbed_official 103:9b881da47c92 723
mbed_official 103:9b881da47c92 724 union {
mbed_official 103:9b881da47c92 725 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 726 = 1 */
mbed_official 103:9b881da47c92 727 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 728 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 729 };
mbed_official 103:9b881da47c92 730
mbed_official 103:9b881da47c92 731 union {
mbed_official 103:9b881da47c92 732 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 733 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 734 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 735 = 1 */
mbed_official 103:9b881da47c92 736 };
mbed_official 103:9b881da47c92 737
mbed_official 103:9b881da47c92 738 union {
mbed_official 103:9b881da47c92 739 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 740 = 1 */
mbed_official 103:9b881da47c92 741 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 742 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 743 };
mbed_official 103:9b881da47c92 744
mbed_official 103:9b881da47c92 745 union {
mbed_official 103:9b881da47c92 746 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 747 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 748 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 749 = 1 */
mbed_official 103:9b881da47c92 750 };
mbed_official 103:9b881da47c92 751
mbed_official 103:9b881da47c92 752 union {
mbed_official 103:9b881da47c92 753 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 754 = 1 */
mbed_official 103:9b881da47c92 755 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 756 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 757 };
mbed_official 103:9b881da47c92 758
mbed_official 103:9b881da47c92 759 union {
mbed_official 103:9b881da47c92 760 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
mbed_official 103:9b881da47c92 761 = 1 */
mbed_official 103:9b881da47c92 762 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
mbed_official 103:9b881da47c92 763 REGMODE7 = 0 */
mbed_official 103:9b881da47c92 764 };
mbed_official 103:9b881da47c92 765 __I uint32_t RESERVED2[56];
mbed_official 103:9b881da47c92 766
mbed_official 103:9b881da47c92 767 union {
mbed_official 103:9b881da47c92 768 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 769 = 1 */
mbed_official 103:9b881da47c92 770 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 771 = 0 */
mbed_official 103:9b881da47c92 772 };
mbed_official 103:9b881da47c92 773
mbed_official 103:9b881da47c92 774 union {
mbed_official 103:9b881da47c92 775 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 776 = 1 */
mbed_official 103:9b881da47c92 777 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 778 = 0 */
mbed_official 103:9b881da47c92 779 };
mbed_official 103:9b881da47c92 780
mbed_official 103:9b881da47c92 781 union {
mbed_official 103:9b881da47c92 782 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 783 = 1 */
mbed_official 103:9b881da47c92 784 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 785 = 0 */
mbed_official 103:9b881da47c92 786 };
mbed_official 103:9b881da47c92 787
mbed_official 103:9b881da47c92 788 union {
mbed_official 103:9b881da47c92 789 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 790 = 0 */
mbed_official 103:9b881da47c92 791 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 792 = 1 */
mbed_official 103:9b881da47c92 793 };
mbed_official 103:9b881da47c92 794
mbed_official 103:9b881da47c92 795 union {
mbed_official 103:9b881da47c92 796 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 797 = 1 */
mbed_official 103:9b881da47c92 798 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 799 = 0 */
mbed_official 103:9b881da47c92 800 };
mbed_official 103:9b881da47c92 801
mbed_official 103:9b881da47c92 802 union {
mbed_official 103:9b881da47c92 803 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 804 = 0 */
mbed_official 103:9b881da47c92 805 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 806 = 1 */
mbed_official 103:9b881da47c92 807 };
mbed_official 103:9b881da47c92 808
mbed_official 103:9b881da47c92 809 union {
mbed_official 103:9b881da47c92 810 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 811 = 1 */
mbed_official 103:9b881da47c92 812 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 813 = 0 */
mbed_official 103:9b881da47c92 814 };
mbed_official 103:9b881da47c92 815
mbed_official 103:9b881da47c92 816 union {
mbed_official 103:9b881da47c92 817 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
mbed_official 103:9b881da47c92 818 = 1 */
mbed_official 103:9b881da47c92 819 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
mbed_official 103:9b881da47c92 820 = 0 */
mbed_official 103:9b881da47c92 821 };
mbed_official 103:9b881da47c92 822 __I uint32_t RESERVED3[56];
mbed_official 103:9b881da47c92 823 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 824 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 825 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 826 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 827 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 828 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 829 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 830 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 831 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 832 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 833 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 834 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 835 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 836 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 837 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 838 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 839 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 840 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 841 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
mbed_official 103:9b881da47c92 842 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
mbed_official 103:9b881da47c92 843 __I uint32_t RESERVED4[108];
mbed_official 103:9b881da47c92 844 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 845 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 846 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 847 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 848 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 849 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 850 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 851 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 852 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 853 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 854 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
mbed_official 103:9b881da47c92 855 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
mbed_official 103:9b881da47c92 856 } LPC_SCT2_Type;
mbed_official 103:9b881da47c92 857
mbed_official 103:9b881da47c92 858
mbed_official 103:9b881da47c92 859 /* ================================================================================ */
mbed_official 103:9b881da47c92 860 /* ================ ADC0 ================ */
mbed_official 103:9b881da47c92 861 /* ================================================================================ */
mbed_official 103:9b881da47c92 862
mbed_official 103:9b881da47c92 863
mbed_official 103:9b881da47c92 864 /**
mbed_official 103:9b881da47c92 865 * @brief 12-bit ADC controller ADC0/1 (ADC0)
mbed_official 103:9b881da47c92 866 */
mbed_official 103:9b881da47c92 867
mbed_official 103:9b881da47c92 868 typedef struct { /*!< ADC0 Structure */
mbed_official 103:9b881da47c92 869 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
mbed_official 103:9b881da47c92 870 bits for each sequence and the A/D power-down bit. */
mbed_official 103:9b881da47c92 871 __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
mbed_official 103:9b881da47c92 872 internal source for various channels */
mbed_official 103:9b881da47c92 873 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
mbed_official 103:9b881da47c92 874 and channel selection for conversion sequence-A. Also specifies
mbed_official 103:9b881da47c92 875 interrupt mode for sequence-A. */
mbed_official 103:9b881da47c92 876 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
mbed_official 103:9b881da47c92 877 and channel selection for conversion sequence-B. Also specifies
mbed_official 103:9b881da47c92 878 interrupt mode for sequence-B. */
mbed_official 103:9b881da47c92 879 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
mbed_official 103:9b881da47c92 880 the result of the most recent A/D conversion performed under
mbed_official 103:9b881da47c92 881 sequence-A */
mbed_official 103:9b881da47c92 882 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
mbed_official 103:9b881da47c92 883 the result of the most recent A/D conversion performed under
mbed_official 103:9b881da47c92 884 sequence-B */
mbed_official 103:9b881da47c92 885 __I uint32_t RESERVED0[2];
mbed_official 103:9b881da47c92 886 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
mbed_official 103:9b881da47c92 887 of the most recent conversion completed on channel 0. */
mbed_official 103:9b881da47c92 888 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
mbed_official 103:9b881da47c92 889 level for automatic threshold comparison for any channels linked
mbed_official 103:9b881da47c92 890 to threshold pair 0. */
mbed_official 103:9b881da47c92 891 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
mbed_official 103:9b881da47c92 892 level for automatic threshold comparison for any channels linked
mbed_official 103:9b881da47c92 893 to threshold pair 1. */
mbed_official 103:9b881da47c92 894 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
mbed_official 103:9b881da47c92 895 level for automatic threshold comparison for any channels linked
mbed_official 103:9b881da47c92 896 to threshold pair 0. */
mbed_official 103:9b881da47c92 897 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
mbed_official 103:9b881da47c92 898 level for automatic threshold comparison for any channels linked
mbed_official 103:9b881da47c92 899 to threshold pair 1. */
mbed_official 103:9b881da47c92 900 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
mbed_official 103:9b881da47c92 901 threshold compare registers are to be used for each channel */
mbed_official 103:9b881da47c92 902 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
mbed_official 103:9b881da47c92 903 bits that enable the sequence-A, sequence-B, threshold compare
mbed_official 103:9b881da47c92 904 and data overrun interrupts to be generated. */
mbed_official 103:9b881da47c92 905 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
mbed_official 103:9b881da47c92 906 and the individual component overrun and threshold-compare flags.
mbed_official 103:9b881da47c92 907 (The overrun bits replicate information stored in the result
mbed_official 103:9b881da47c92 908 registers). */
mbed_official 103:9b881da47c92 909 __IO uint32_t TRM; /*!< ADC trim register. */
mbed_official 103:9b881da47c92 910 } LPC_ADC0_Type;
mbed_official 103:9b881da47c92 911
mbed_official 103:9b881da47c92 912
mbed_official 103:9b881da47c92 913 /* ================================================================================ */
mbed_official 103:9b881da47c92 914 /* ================ DAC ================ */
mbed_official 103:9b881da47c92 915 /* ================================================================================ */
mbed_official 103:9b881da47c92 916
mbed_official 103:9b881da47c92 917
mbed_official 103:9b881da47c92 918 /**
mbed_official 103:9b881da47c92 919 * @brief 12-bit DAC Modification (DAC)
mbed_official 103:9b881da47c92 920 */
mbed_official 103:9b881da47c92 921
mbed_official 103:9b881da47c92 922 typedef struct { /*!< DAC Structure */
mbed_official 103:9b881da47c92 923 __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
mbed_official 103:9b881da47c92 924 value to be converted to analog. */
mbed_official 103:9b881da47c92 925 __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
mbed_official 103:9b881da47c92 926 DAC operation and the interrupt/dma request flag. */
mbed_official 103:9b881da47c92 927 __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
mbed_official 103:9b881da47c92 928 value for the internal DAC DMA/Interrupt timer. */
mbed_official 103:9b881da47c92 929 } LPC_DAC_Type;
mbed_official 103:9b881da47c92 930
mbed_official 103:9b881da47c92 931
mbed_official 103:9b881da47c92 932 /* ================================================================================ */
mbed_official 103:9b881da47c92 933 /* ================ ACMP ================ */
mbed_official 103:9b881da47c92 934 /* ================================================================================ */
mbed_official 103:9b881da47c92 935
mbed_official 103:9b881da47c92 936
mbed_official 103:9b881da47c92 937 /**
mbed_official 103:9b881da47c92 938 * @brief Analog comparators ACMP0/1/2/3 (ACMP)
mbed_official 103:9b881da47c92 939 */
mbed_official 103:9b881da47c92 940
mbed_official 103:9b881da47c92 941 typedef struct { /*!< ACMP Structure */
mbed_official 103:9b881da47c92 942 __IO uint32_t CTRL; /*!< Comparator block control register */
mbed_official 103:9b881da47c92 943 __IO uint32_t CMP0; /*!< Comparator 0 source control */
mbed_official 103:9b881da47c92 944 __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */
mbed_official 103:9b881da47c92 945 __IO uint32_t CMP1; /*!< Comparator 1 source control */
mbed_official 103:9b881da47c92 946 __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */
mbed_official 103:9b881da47c92 947 __IO uint32_t CMP2; /*!< Comparator 2 source control */
mbed_official 103:9b881da47c92 948 __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */
mbed_official 103:9b881da47c92 949 __IO uint32_t CMP3; /*!< Comparator 3 source control */
mbed_official 103:9b881da47c92 950 __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */
mbed_official 103:9b881da47c92 951 } LPC_ACMP_Type;
mbed_official 103:9b881da47c92 952
mbed_official 103:9b881da47c92 953
mbed_official 103:9b881da47c92 954 /* ================================================================================ */
mbed_official 103:9b881da47c92 955 /* ================ INMUX ================ */
mbed_official 103:9b881da47c92 956 /* ================================================================================ */
mbed_official 103:9b881da47c92 957
mbed_official 103:9b881da47c92 958
mbed_official 103:9b881da47c92 959 /**
mbed_official 103:9b881da47c92 960 * @brief Input multiplexing (INMUX) (INMUX)
mbed_official 103:9b881da47c92 961 */
mbed_official 103:9b881da47c92 962
mbed_official 103:9b881da47c92 963 typedef struct { /*!< INMUX Structure */
mbed_official 103:9b881da47c92 964 __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */
mbed_official 103:9b881da47c92 965 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 966 __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */
mbed_official 103:9b881da47c92 967 __I uint32_t RESERVED1;
mbed_official 103:9b881da47c92 968 __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */
mbed_official 103:9b881da47c92 969 __I uint32_t RESERVED2[5];
mbed_official 103:9b881da47c92 970 __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */
mbed_official 103:9b881da47c92 971 __I uint32_t RESERVED3[21];
mbed_official 103:9b881da47c92 972 __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */
mbed_official 103:9b881da47c92 973 __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */
mbed_official 103:9b881da47c92 974 __I uint32_t RESERVED4[14];
mbed_official 103:9b881da47c92 975 __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
mbed_official 103:9b881da47c92 976 clock */
mbed_official 103:9b881da47c92 977 __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */
mbed_official 103:9b881da47c92 978 } LPC_INMUX_Type;
mbed_official 103:9b881da47c92 979
mbed_official 103:9b881da47c92 980
mbed_official 103:9b881da47c92 981 /* ================================================================================ */
mbed_official 103:9b881da47c92 982 /* ================ RTC ================ */
mbed_official 103:9b881da47c92 983 /* ================================================================================ */
mbed_official 103:9b881da47c92 984
mbed_official 103:9b881da47c92 985
mbed_official 103:9b881da47c92 986 /**
mbed_official 103:9b881da47c92 987 * @brief Real-Time Clock (RTC) (RTC)
mbed_official 103:9b881da47c92 988 */
mbed_official 103:9b881da47c92 989
mbed_official 103:9b881da47c92 990 typedef struct { /*!< RTC Structure */
mbed_official 103:9b881da47c92 991 __IO uint32_t CTRL; /*!< RTC control register */
mbed_official 103:9b881da47c92 992 __IO uint32_t MATCH; /*!< RTC match register */
mbed_official 103:9b881da47c92 993 __IO uint32_t COUNT; /*!< RTC counter register */
mbed_official 103:9b881da47c92 994 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
mbed_official 103:9b881da47c92 995 } LPC_RTC_Type;
mbed_official 103:9b881da47c92 996
mbed_official 103:9b881da47c92 997
mbed_official 103:9b881da47c92 998 /* ================================================================================ */
mbed_official 103:9b881da47c92 999 /* ================ WWDT ================ */
mbed_official 103:9b881da47c92 1000 /* ================================================================================ */
mbed_official 103:9b881da47c92 1001
mbed_official 103:9b881da47c92 1002
mbed_official 103:9b881da47c92 1003 /**
mbed_official 103:9b881da47c92 1004 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
mbed_official 103:9b881da47c92 1005 */
mbed_official 103:9b881da47c92 1006
mbed_official 103:9b881da47c92 1007 typedef struct { /*!< WWDT Structure */
mbed_official 103:9b881da47c92 1008 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
mbed_official 103:9b881da47c92 1009 and status of the Watchdog Timer. */
mbed_official 103:9b881da47c92 1010 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
mbed_official 103:9b881da47c92 1011 the time-out value. */
mbed_official 103:9b881da47c92 1012 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
mbed_official 103:9b881da47c92 1013 to this register reloads the Watchdog timer with the value contained
mbed_official 103:9b881da47c92 1014 in WDTC. */
mbed_official 103:9b881da47c92 1015 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
mbed_official 103:9b881da47c92 1016 the current value of the Watchdog timer. */
mbed_official 103:9b881da47c92 1017 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 1018 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
mbed_official 103:9b881da47c92 1019 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
mbed_official 103:9b881da47c92 1020 } LPC_WWDT_Type;
mbed_official 103:9b881da47c92 1021
mbed_official 103:9b881da47c92 1022
mbed_official 103:9b881da47c92 1023 /* ================================================================================ */
mbed_official 103:9b881da47c92 1024 /* ================ SWM ================ */
mbed_official 103:9b881da47c92 1025 /* ================================================================================ */
mbed_official 103:9b881da47c92 1026
mbed_official 103:9b881da47c92 1027
mbed_official 103:9b881da47c92 1028 /**
mbed_official 103:9b881da47c92 1029 * @brief Switch Matrix (SWM) (SWM)
mbed_official 103:9b881da47c92 1030 */
mbed_official 103:9b881da47c92 1031
mbed_official 103:9b881da47c92 1032 typedef struct { /*!< SWM Structure */
mbed_official 103:9b881da47c92 1033 union {
mbed_official 103:9b881da47c92 1034 __IO uint32_t PINASSIGN[16];
mbed_official 103:9b881da47c92 1035 struct {
mbed_official 103:9b881da47c92 1036 __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
mbed_official 103:9b881da47c92 1037 U0_RTS, U0_CTS. */
mbed_official 103:9b881da47c92 1038 __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
mbed_official 103:9b881da47c92 1039 U1_RXD, U1_RTS. */
mbed_official 103:9b881da47c92 1040 __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
mbed_official 103:9b881da47c92 1041 U2_TXD, U2_RXD. */
mbed_official 103:9b881da47c92 1042 __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */
mbed_official 103:9b881da47c92 1043 __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */
mbed_official 103:9b881da47c92 1044 __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */
mbed_official 103:9b881da47c92 1045 __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */
mbed_official 103:9b881da47c92 1046 __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */
mbed_official 103:9b881da47c92 1047 __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */
mbed_official 103:9b881da47c92 1048 __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */
mbed_official 103:9b881da47c92 1049 __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */
mbed_official 103:9b881da47c92 1050 __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */
mbed_official 103:9b881da47c92 1051 __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */
mbed_official 103:9b881da47c92 1052 __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
mbed_official 103:9b881da47c92 1053 __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
mbed_official 103:9b881da47c92 1054 __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
mbed_official 103:9b881da47c92 1055 };
mbed_official 103:9b881da47c92 1056 };
mbed_official 103:9b881da47c92 1057 __I uint32_t RESERVED0[96];
mbed_official 103:9b881da47c92 1058 __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
mbed_official 103:9b881da47c92 1059 __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
mbed_official 103:9b881da47c92 1060 } LPC_SWM_Type;
mbed_official 103:9b881da47c92 1061
mbed_official 103:9b881da47c92 1062
mbed_official 103:9b881da47c92 1063 /* ================================================================================ */
mbed_official 103:9b881da47c92 1064 /* ================ PMU ================ */
mbed_official 103:9b881da47c92 1065 /* ================================================================================ */
mbed_official 103:9b881da47c92 1066
mbed_official 103:9b881da47c92 1067
mbed_official 103:9b881da47c92 1068 /**
mbed_official 103:9b881da47c92 1069 * @brief Power Management Unit (PMU) (PMU)
mbed_official 103:9b881da47c92 1070 */
mbed_official 103:9b881da47c92 1071
mbed_official 103:9b881da47c92 1072 typedef struct { /*!< PMU Structure */
mbed_official 103:9b881da47c92 1073 __IO uint32_t PCON; /*!< Power control register */
mbed_official 103:9b881da47c92 1074 __IO uint32_t GPREG0; /*!< General purpose register 0 */
mbed_official 103:9b881da47c92 1075 __IO uint32_t GPREG1; /*!< General purpose register 0 */
mbed_official 103:9b881da47c92 1076 __IO uint32_t GPREG2; /*!< General purpose register 0 */
mbed_official 103:9b881da47c92 1077 __IO uint32_t GPREG3; /*!< General purpose register 0 */
mbed_official 103:9b881da47c92 1078 __IO uint32_t DPDCTRL; /*!< Deep power-down control register */
mbed_official 103:9b881da47c92 1079 } LPC_PMU_Type;
mbed_official 103:9b881da47c92 1080
mbed_official 103:9b881da47c92 1081
mbed_official 103:9b881da47c92 1082 /* ================================================================================ */
mbed_official 103:9b881da47c92 1083 /* ================ USART0 ================ */
mbed_official 103:9b881da47c92 1084 /* ================================================================================ */
mbed_official 103:9b881da47c92 1085
mbed_official 103:9b881da47c92 1086
mbed_official 103:9b881da47c92 1087 /**
mbed_official 103:9b881da47c92 1088 * @brief USART0 (USART0)
mbed_official 103:9b881da47c92 1089 */
mbed_official 103:9b881da47c92 1090
mbed_official 103:9b881da47c92 1091 typedef struct { /*!< USART0 Structure */
mbed_official 103:9b881da47c92 1092 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
mbed_official 103:9b881da47c92 1093 that typically are not changed during operation. */
mbed_official 103:9b881da47c92 1094 __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
mbed_official 103:9b881da47c92 1095 likely to change during operation. */
mbed_official 103:9b881da47c92 1096 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
mbed_official 103:9b881da47c92 1097 here. Writing ones clears some bits in the register. Some bits
mbed_official 103:9b881da47c92 1098 can be cleared by writing a 1 to them. */
mbed_official 103:9b881da47c92 1099 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
mbed_official 103:9b881da47c92 1100 interrupt enable bit for each potential USART interrupt. A complete
mbed_official 103:9b881da47c92 1101 value may be read from this register. Writing a 1 to any implemented
mbed_official 103:9b881da47c92 1102 bit position causes that bit to be set. */
mbed_official 103:9b881da47c92 1103 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
mbed_official 103:9b881da47c92 1104 of bits in the INTENSET register. Writing a 1 to any implemented
mbed_official 103:9b881da47c92 1105 bit position causes the corresponding bit to be cleared. */
mbed_official 103:9b881da47c92 1106 __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */
mbed_official 103:9b881da47c92 1107 __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
mbed_official 103:9b881da47c92 1108 received with the current USART receive status. Allows DMA or
mbed_official 103:9b881da47c92 1109 software to recover incoming data and status together. */
mbed_official 103:9b881da47c92 1110 __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */
mbed_official 103:9b881da47c92 1111 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
mbed_official 103:9b881da47c92 1112 value. */
mbed_official 103:9b881da47c92 1113 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
mbed_official 103:9b881da47c92 1114 enabled. */
mbed_official 103:9b881da47c92 1115 } LPC_USART0_Type;
mbed_official 103:9b881da47c92 1116
mbed_official 103:9b881da47c92 1117
mbed_official 103:9b881da47c92 1118 /* ================================================================================ */
mbed_official 103:9b881da47c92 1119 /* ================ SPI0 ================ */
mbed_official 103:9b881da47c92 1120 /* ================================================================================ */
mbed_official 103:9b881da47c92 1121
mbed_official 103:9b881da47c92 1122
mbed_official 103:9b881da47c92 1123 /**
mbed_official 103:9b881da47c92 1124 * @brief SPI0 (SPI0)
mbed_official 103:9b881da47c92 1125 */
mbed_official 103:9b881da47c92 1126
mbed_official 103:9b881da47c92 1127 typedef struct { /*!< SPI0 Structure */
mbed_official 103:9b881da47c92 1128 __IO uint32_t CFG; /*!< SPI Configuration register */
mbed_official 103:9b881da47c92 1129 __IO uint32_t DLY; /*!< SPI Delay register */
mbed_official 103:9b881da47c92 1130 __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
mbed_official 103:9b881da47c92 1131 to that bit position */
mbed_official 103:9b881da47c92 1132 __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
mbed_official 103:9b881da47c92 1133 from this register. Writing a 1 to any implemented bit position
mbed_official 103:9b881da47c92 1134 causes that bit to be set. */
mbed_official 103:9b881da47c92 1135 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
mbed_official 103:9b881da47c92 1136 position causes the corresponding bit in INTENSET to be cleared. */
mbed_official 103:9b881da47c92 1137 __I uint32_t RXDAT; /*!< SPI Receive Data */
mbed_official 103:9b881da47c92 1138 __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */
mbed_official 103:9b881da47c92 1139 __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */
mbed_official 103:9b881da47c92 1140 __IO uint32_t TXCTL; /*!< SPI Transmit Control */
mbed_official 103:9b881da47c92 1141 __IO uint32_t DIV; /*!< SPI clock Divider */
mbed_official 103:9b881da47c92 1142 __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
mbed_official 103:9b881da47c92 1143 } LPC_SPI0_Type;
mbed_official 103:9b881da47c92 1144
mbed_official 103:9b881da47c92 1145
mbed_official 103:9b881da47c92 1146 /* ================================================================================ */
mbed_official 103:9b881da47c92 1147 /* ================ I2C0 ================ */
mbed_official 103:9b881da47c92 1148 /* ================================================================================ */
mbed_official 103:9b881da47c92 1149
mbed_official 103:9b881da47c92 1150
mbed_official 103:9b881da47c92 1151 /**
mbed_official 103:9b881da47c92 1152 * @brief I2C-bus interface (I2C0)
mbed_official 103:9b881da47c92 1153 */
mbed_official 103:9b881da47c92 1154
mbed_official 103:9b881da47c92 1155 typedef struct { /*!< I2C0 Structure */
mbed_official 103:9b881da47c92 1156 __IO uint32_t CFG; /*!< Configuration for shared functions. */
mbed_official 103:9b881da47c92 1157 __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
mbed_official 103:9b881da47c92 1158 __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
mbed_official 103:9b881da47c92 1159 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
mbed_official 103:9b881da47c92 1160 __IO uint32_t TIMEOUT; /*!< Time-out value register. */
mbed_official 103:9b881da47c92 1161 __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
mbed_official 103:9b881da47c92 1162 what time increments are used for the MSTTIME and SLVTIME registers. */
mbed_official 103:9b881da47c92 1163 __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
mbed_official 103:9b881da47c92 1164 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 1165 __IO uint32_t MSTCTL; /*!< Master control register. */
mbed_official 103:9b881da47c92 1166 __IO uint32_t MSTTIME; /*!< Master timing configuration. */
mbed_official 103:9b881da47c92 1167 __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
mbed_official 103:9b881da47c92 1168 __I uint32_t RESERVED1[5];
mbed_official 103:9b881da47c92 1169 __IO uint32_t SLVCTL; /*!< Slave control register. */
mbed_official 103:9b881da47c92 1170 __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
mbed_official 103:9b881da47c92 1171 __IO uint32_t SLVADR0; /*!< Slave address 0. */
mbed_official 103:9b881da47c92 1172 __IO uint32_t SLVADR1; /*!< Slave address 0. */
mbed_official 103:9b881da47c92 1173 __IO uint32_t SLVADR2; /*!< Slave address 0. */
mbed_official 103:9b881da47c92 1174 __IO uint32_t SLVADR3; /*!< Slave address 0. */
mbed_official 103:9b881da47c92 1175 __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
mbed_official 103:9b881da47c92 1176 __I uint32_t RESERVED2[9];
mbed_official 103:9b881da47c92 1177 __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
mbed_official 103:9b881da47c92 1178 } LPC_I2C0_Type;
mbed_official 103:9b881da47c92 1179
mbed_official 103:9b881da47c92 1180
mbed_official 103:9b881da47c92 1181 /* ================================================================================ */
mbed_official 103:9b881da47c92 1182 /* ================ QEI ================ */
mbed_official 103:9b881da47c92 1183 /* ================================================================================ */
mbed_official 103:9b881da47c92 1184
mbed_official 103:9b881da47c92 1185
mbed_official 103:9b881da47c92 1186 /**
mbed_official 103:9b881da47c92 1187 * @brief Quadrature Encoder Interface (QEI) (QEI)
mbed_official 103:9b881da47c92 1188 */
mbed_official 103:9b881da47c92 1189
mbed_official 103:9b881da47c92 1190 typedef struct { /*!< QEI Structure */
mbed_official 103:9b881da47c92 1191 __O uint32_t CON; /*!< Control register */
mbed_official 103:9b881da47c92 1192 __I uint32_t STAT; /*!< Encoder status register */
mbed_official 103:9b881da47c92 1193 __IO uint32_t CONF; /*!< Configuration register */
mbed_official 103:9b881da47c92 1194 __I uint32_t POS; /*!< Position register */
mbed_official 103:9b881da47c92 1195 __IO uint32_t MAXPOS; /*!< Maximum position register */
mbed_official 103:9b881da47c92 1196 __IO uint32_t CMPOS0; /*!< position compare register 0 */
mbed_official 103:9b881da47c92 1197 __IO uint32_t CMPOS1; /*!< position compare register 1 */
mbed_official 103:9b881da47c92 1198 __IO uint32_t CMPOS2; /*!< position compare register 2 */
mbed_official 103:9b881da47c92 1199 __I uint32_t INXCNT; /*!< Index count register */
mbed_official 103:9b881da47c92 1200 __IO uint32_t INXCMP0; /*!< Index compare register 0 */
mbed_official 103:9b881da47c92 1201 __IO uint32_t LOAD; /*!< Velocity timer reload register */
mbed_official 103:9b881da47c92 1202 __I uint32_t TIME; /*!< Velocity timer register */
mbed_official 103:9b881da47c92 1203 __I uint32_t VEL; /*!< Velocity counter register */
mbed_official 103:9b881da47c92 1204 __I uint32_t CAP; /*!< Velocity capture register */
mbed_official 103:9b881da47c92 1205 __IO uint32_t VELCOMP; /*!< Velocity compare register */
mbed_official 103:9b881da47c92 1206 __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
mbed_official 103:9b881da47c92 1207 __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
mbed_official 103:9b881da47c92 1208 __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
mbed_official 103:9b881da47c92 1209 __IO uint32_t WINDOW; /*!< Index acceptance window register */
mbed_official 103:9b881da47c92 1210 __IO uint32_t INXCMP1; /*!< Index compare register 1 */
mbed_official 103:9b881da47c92 1211 __IO uint32_t INXCMP2; /*!< Index compare register 2 */
mbed_official 103:9b881da47c92 1212 __I uint32_t RESERVED0[993];
mbed_official 103:9b881da47c92 1213 __O uint32_t IEC; /*!< Interrupt enable clear register */
mbed_official 103:9b881da47c92 1214 __O uint32_t IES; /*!< Interrupt enable set register */
mbed_official 103:9b881da47c92 1215 __I uint32_t INTSTAT; /*!< Interrupt status register */
mbed_official 103:9b881da47c92 1216 __O uint32_t IE; /*!< Interrupt enable clear register */
mbed_official 103:9b881da47c92 1217 __O uint32_t CLR; /*!< Interrupt status clear register */
mbed_official 103:9b881da47c92 1218 __O uint32_t SET; /*!< Interrupt status set register */
mbed_official 103:9b881da47c92 1219 } LPC_QEI_Type;
mbed_official 103:9b881da47c92 1220
mbed_official 103:9b881da47c92 1221
mbed_official 103:9b881da47c92 1222 /* ================================================================================ */
mbed_official 103:9b881da47c92 1223 /* ================ SYSCON ================ */
mbed_official 103:9b881da47c92 1224 /* ================================================================================ */
mbed_official 103:9b881da47c92 1225
mbed_official 103:9b881da47c92 1226
mbed_official 103:9b881da47c92 1227 /**
mbed_official 103:9b881da47c92 1228 * @brief System configuration (SYSCON) (SYSCON)
mbed_official 103:9b881da47c92 1229 */
mbed_official 103:9b881da47c92 1230
mbed_official 103:9b881da47c92 1231 typedef struct { /*!< SYSCON Structure */
mbed_official 103:9b881da47c92 1232 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
mbed_official 103:9b881da47c92 1233 __I uint32_t RESERVED0[4];
mbed_official 103:9b881da47c92 1234 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
mbed_official 103:9b881da47c92 1235 __I uint32_t RESERVED1;
mbed_official 103:9b881da47c92 1236 __IO uint32_t NMISRC; /*!< NMI Source Control */
mbed_official 103:9b881da47c92 1237 __I uint32_t RESERVED2[8];
mbed_official 103:9b881da47c92 1238 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
mbed_official 103:9b881da47c92 1239 __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
mbed_official 103:9b881da47c92 1240 __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
mbed_official 103:9b881da47c92 1241 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
mbed_official 103:9b881da47c92 1242 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
mbed_official 103:9b881da47c92 1243 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */
mbed_official 103:9b881da47c92 1244 __I uint32_t RESERVED3[10];
mbed_official 103:9b881da47c92 1245 __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */
mbed_official 103:9b881da47c92 1246 __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */
mbed_official 103:9b881da47c92 1247 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
mbed_official 103:9b881da47c92 1248 __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */
mbed_official 103:9b881da47c92 1249 __I uint32_t RESERVED4;
mbed_official 103:9b881da47c92 1250 __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */
mbed_official 103:9b881da47c92 1251 __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */
mbed_official 103:9b881da47c92 1252 __I uint32_t RESERVED5;
mbed_official 103:9b881da47c92 1253 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
mbed_official 103:9b881da47c92 1254 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
mbed_official 103:9b881da47c92 1255 __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */
mbed_official 103:9b881da47c92 1256 __I uint32_t RESERVED6[5];
mbed_official 103:9b881da47c92 1257 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
mbed_official 103:9b881da47c92 1258 __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */
mbed_official 103:9b881da47c92 1259 __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */
mbed_official 103:9b881da47c92 1260 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
mbed_official 103:9b881da47c92 1261 __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
mbed_official 103:9b881da47c92 1262 baud rate generator. */
mbed_official 103:9b881da47c92 1263 __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
mbed_official 103:9b881da47c92 1264 filter */
mbed_official 103:9b881da47c92 1265 __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */
mbed_official 103:9b881da47c92 1266 __I uint32_t RESERVED7[4];
mbed_official 103:9b881da47c92 1267 __IO uint32_t USBCLKDIV; /*!< USB clock divider */
mbed_official 103:9b881da47c92 1268 __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
mbed_official 103:9b881da47c92 1269 __I uint32_t RESERVED8;
mbed_official 103:9b881da47c92 1270 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
mbed_official 103:9b881da47c92 1271 __I uint32_t RESERVED9[11];
mbed_official 103:9b881da47c92 1272 __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */
mbed_official 103:9b881da47c92 1273 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
mbed_official 103:9b881da47c92 1274 __IO uint32_t USBCLKST; /*!< USB clock status */
mbed_official 103:9b881da47c92 1275 __I uint32_t RESERVED10[19];
mbed_official 103:9b881da47c92 1276 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
mbed_official 103:9b881da47c92 1277 __I uint32_t RESERVED11;
mbed_official 103:9b881da47c92 1278 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
mbed_official 103:9b881da47c92 1279 __I uint32_t RESERVED12;
mbed_official 103:9b881da47c92 1280 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */
mbed_official 103:9b881da47c92 1281 __I uint32_t RESERVED13;
mbed_official 103:9b881da47c92 1282 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
mbed_official 103:9b881da47c92 1283 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
mbed_official 103:9b881da47c92 1284 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
mbed_official 103:9b881da47c92 1285 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
mbed_official 103:9b881da47c92 1286 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */
mbed_official 103:9b881da47c92 1287 __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */
mbed_official 103:9b881da47c92 1288 __I uint32_t RESERVED14[21];
mbed_official 103:9b881da47c92 1289 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
mbed_official 103:9b881da47c92 1290 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
mbed_official 103:9b881da47c92 1291 __I uint32_t RESERVED15[3];
mbed_official 103:9b881da47c92 1292 __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */
mbed_official 103:9b881da47c92 1293 __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */
mbed_official 103:9b881da47c92 1294 } LPC_SYSCON_Type;
mbed_official 103:9b881da47c92 1295
mbed_official 103:9b881da47c92 1296
mbed_official 103:9b881da47c92 1297 /* ================================================================================ */
mbed_official 103:9b881da47c92 1298 /* ================ MRT ================ */
mbed_official 103:9b881da47c92 1299 /* ================================================================================ */
mbed_official 103:9b881da47c92 1300
mbed_official 103:9b881da47c92 1301
mbed_official 103:9b881da47c92 1302 /**
mbed_official 103:9b881da47c92 1303 * @brief Multi-Rate Timer (MRT) (MRT)
mbed_official 103:9b881da47c92 1304 */
mbed_official 103:9b881da47c92 1305
mbed_official 103:9b881da47c92 1306 typedef struct { /*!< MRT Structure */
mbed_official 103:9b881da47c92 1307 __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
mbed_official 103:9b881da47c92 1308 the TIMER0 register. */
mbed_official 103:9b881da47c92 1309 __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
mbed_official 103:9b881da47c92 1310 __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */
mbed_official 103:9b881da47c92 1311 __IO uint32_t STAT0; /*!< MRT0 Status register. */
mbed_official 103:9b881da47c92 1312 __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
mbed_official 103:9b881da47c92 1313 the TIMER0 register. */
mbed_official 103:9b881da47c92 1314 __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
mbed_official 103:9b881da47c92 1315 __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */
mbed_official 103:9b881da47c92 1316 __IO uint32_t STAT1; /*!< MRT0 Status register. */
mbed_official 103:9b881da47c92 1317 __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
mbed_official 103:9b881da47c92 1318 the TIMER0 register. */
mbed_official 103:9b881da47c92 1319 __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
mbed_official 103:9b881da47c92 1320 __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */
mbed_official 103:9b881da47c92 1321 __IO uint32_t STAT2; /*!< MRT0 Status register. */
mbed_official 103:9b881da47c92 1322 __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
mbed_official 103:9b881da47c92 1323 the TIMER0 register. */
mbed_official 103:9b881da47c92 1324 __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
mbed_official 103:9b881da47c92 1325 __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */
mbed_official 103:9b881da47c92 1326 __IO uint32_t STAT3; /*!< MRT0 Status register. */
mbed_official 103:9b881da47c92 1327 __I uint32_t RESERVED0[45];
mbed_official 103:9b881da47c92 1328 __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
mbed_official 103:9b881da47c92 1329 first idle channel. */
mbed_official 103:9b881da47c92 1330 __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */
mbed_official 103:9b881da47c92 1331 } LPC_MRT_Type;
mbed_official 103:9b881da47c92 1332
mbed_official 103:9b881da47c92 1333
mbed_official 103:9b881da47c92 1334 /* ================================================================================ */
mbed_official 103:9b881da47c92 1335 /* ================ PINT ================ */
mbed_official 103:9b881da47c92 1336 /* ================================================================================ */
mbed_official 103:9b881da47c92 1337
mbed_official 103:9b881da47c92 1338
mbed_official 103:9b881da47c92 1339 /**
mbed_official 103:9b881da47c92 1340 * @brief Pin interruptand pattern match (PINT) (PINT)
mbed_official 103:9b881da47c92 1341 */
mbed_official 103:9b881da47c92 1342
mbed_official 103:9b881da47c92 1343 typedef struct { /*!< PINT Structure */
mbed_official 103:9b881da47c92 1344 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
mbed_official 103:9b881da47c92 1345 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
mbed_official 103:9b881da47c92 1346 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
mbed_official 103:9b881da47c92 1347 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
mbed_official 103:9b881da47c92 1348 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
mbed_official 103:9b881da47c92 1349 register */
mbed_official 103:9b881da47c92 1350 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
mbed_official 103:9b881da47c92 1351 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
mbed_official 103:9b881da47c92 1352 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
mbed_official 103:9b881da47c92 1353 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
mbed_official 103:9b881da47c92 1354 __IO uint32_t IST; /*!< Pin interrupt status register */
mbed_official 103:9b881da47c92 1355 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
mbed_official 103:9b881da47c92 1356 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
mbed_official 103:9b881da47c92 1357 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
mbed_official 103:9b881da47c92 1358 } LPC_PINT_Type;
mbed_official 103:9b881da47c92 1359
mbed_official 103:9b881da47c92 1360
mbed_official 103:9b881da47c92 1361 /* ================================================================================ */
mbed_official 103:9b881da47c92 1362 /* ================ GINT0 ================ */
mbed_official 103:9b881da47c92 1363 /* ================================================================================ */
mbed_official 103:9b881da47c92 1364
mbed_official 103:9b881da47c92 1365
mbed_official 103:9b881da47c92 1366 /**
mbed_official 103:9b881da47c92 1367 * @brief Group interrupt 0/1 (GINT0/1) (GINT0)
mbed_official 103:9b881da47c92 1368 */
mbed_official 103:9b881da47c92 1369
mbed_official 103:9b881da47c92 1370 typedef struct { /*!< GINT0 Structure */
mbed_official 103:9b881da47c92 1371 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
mbed_official 103:9b881da47c92 1372 __I uint32_t RESERVED0[7];
mbed_official 103:9b881da47c92 1373 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
mbed_official 103:9b881da47c92 1374 __I uint32_t RESERVED1[5];
mbed_official 103:9b881da47c92 1375 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */
mbed_official 103:9b881da47c92 1376 } LPC_GINT0_Type;
mbed_official 103:9b881da47c92 1377
mbed_official 103:9b881da47c92 1378
mbed_official 103:9b881da47c92 1379 /* ================================================================================ */
mbed_official 103:9b881da47c92 1380 /* ================ RIT ================ */
mbed_official 103:9b881da47c92 1381 /* ================================================================================ */
mbed_official 103:9b881da47c92 1382
mbed_official 103:9b881da47c92 1383
mbed_official 103:9b881da47c92 1384 /**
mbed_official 103:9b881da47c92 1385 * @brief Repetitive Interrupt Timer (RIT) (RIT)
mbed_official 103:9b881da47c92 1386 */
mbed_official 103:9b881da47c92 1387
mbed_official 103:9b881da47c92 1388 typedef struct { /*!< RIT Structure */
mbed_official 103:9b881da47c92 1389 __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
mbed_official 103:9b881da47c92 1390 value. */
mbed_official 103:9b881da47c92 1391 __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
mbed_official 103:9b881da47c92 1392 value. A 1 written to any bit will force a compare on the corresponding
mbed_official 103:9b881da47c92 1393 bit of the counter and compare register. */
mbed_official 103:9b881da47c92 1394 __IO uint32_t CTRL; /*!< Control register. */
mbed_official 103:9b881da47c92 1395 __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */
mbed_official 103:9b881da47c92 1396 __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
mbed_official 103:9b881da47c92 1397 value. */
mbed_official 103:9b881da47c92 1398 __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
mbed_official 103:9b881da47c92 1399 value. A 1 written to any bit will force a compare on the corresponding
mbed_official 103:9b881da47c92 1400 bit of the counter and compare register. */
mbed_official 103:9b881da47c92 1401 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 1402 __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */
mbed_official 103:9b881da47c92 1403 } LPC_RIT_Type;
mbed_official 103:9b881da47c92 1404
mbed_official 103:9b881da47c92 1405
mbed_official 103:9b881da47c92 1406 /* ================================================================================ */
mbed_official 103:9b881da47c92 1407 /* ================ SCTIPU ================ */
mbed_official 103:9b881da47c92 1408 /* ================================================================================ */
mbed_official 103:9b881da47c92 1409
mbed_official 103:9b881da47c92 1410
mbed_official 103:9b881da47c92 1411 /**
mbed_official 103:9b881da47c92 1412 * @brief SCT Input Processing Unit (IPU) (SCTIPU)
mbed_official 103:9b881da47c92 1413 */
mbed_official 103:9b881da47c92 1414
mbed_official 103:9b881da47c92 1415 typedef struct { /*!< SCTIPU Structure */
mbed_official 103:9b881da47c92 1416 __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
mbed_official 103:9b881da47c92 1417 latch/sample-enable mux selects, and sample overrride bits for
mbed_official 103:9b881da47c92 1418 the SAMPLE module. */
mbed_official 103:9b881da47c92 1419 __I uint32_t RESERVED0[7];
mbed_official 103:9b881da47c92 1420 __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
mbed_official 103:9b881da47c92 1421 to ORed Abort Output 0. */
mbed_official 103:9b881da47c92 1422 __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
mbed_official 103:9b881da47c92 1423 input source caused abort output 0. */
mbed_official 103:9b881da47c92 1424 __I uint32_t RESERVED1[6];
mbed_official 103:9b881da47c92 1425 __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
mbed_official 103:9b881da47c92 1426 to ORed Abort Output 0. */
mbed_official 103:9b881da47c92 1427 __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
mbed_official 103:9b881da47c92 1428 input source caused abort output 0. */
mbed_official 103:9b881da47c92 1429 __I uint32_t RESERVED2[6];
mbed_official 103:9b881da47c92 1430 __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
mbed_official 103:9b881da47c92 1431 to ORed Abort Output 0. */
mbed_official 103:9b881da47c92 1432 __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
mbed_official 103:9b881da47c92 1433 input source caused abort output 0. */
mbed_official 103:9b881da47c92 1434 __I uint32_t RESERVED3[6];
mbed_official 103:9b881da47c92 1435 __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
mbed_official 103:9b881da47c92 1436 to ORed Abort Output 0. */
mbed_official 103:9b881da47c92 1437 __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
mbed_official 103:9b881da47c92 1438 input source caused abort output 0. */
mbed_official 103:9b881da47c92 1439 } LPC_SCTIPU_Type;
mbed_official 103:9b881da47c92 1440
mbed_official 103:9b881da47c92 1441
mbed_official 103:9b881da47c92 1442 /* ================================================================================ */
mbed_official 103:9b881da47c92 1443 /* ================ FLASHCTRL ================ */
mbed_official 103:9b881da47c92 1444 /* ================================================================================ */
mbed_official 103:9b881da47c92 1445
mbed_official 103:9b881da47c92 1446
mbed_official 103:9b881da47c92 1447 /**
mbed_official 103:9b881da47c92 1448 * @brief Flash controller (FLASHCTRL)
mbed_official 103:9b881da47c92 1449 */
mbed_official 103:9b881da47c92 1450
mbed_official 103:9b881da47c92 1451 typedef struct { /*!< FLASHCTRL Structure */
mbed_official 103:9b881da47c92 1452 __I uint32_t RESERVED0[8];
mbed_official 103:9b881da47c92 1453 __IO uint32_t FMSSTART; /*!< Signature start address register */
mbed_official 103:9b881da47c92 1454 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
mbed_official 103:9b881da47c92 1455 __I uint32_t RESERVED1;
mbed_official 103:9b881da47c92 1456 __I uint32_t FMSW0; /*!< Signature word */
mbed_official 103:9b881da47c92 1457 } LPC_FLASHCTRL_Type;
mbed_official 103:9b881da47c92 1458
mbed_official 103:9b881da47c92 1459
mbed_official 103:9b881da47c92 1460 /* ================================================================================ */
mbed_official 103:9b881da47c92 1461 /* ================ C_CAN0 ================ */
mbed_official 103:9b881da47c92 1462 /* ================================================================================ */
mbed_official 103:9b881da47c92 1463
mbed_official 103:9b881da47c92 1464
mbed_official 103:9b881da47c92 1465 /**
mbed_official 103:9b881da47c92 1466 * @brief Controller Area Network C_CAN0 (C_CAN0)
mbed_official 103:9b881da47c92 1467 */
mbed_official 103:9b881da47c92 1468
mbed_official 103:9b881da47c92 1469 typedef struct { /*!< C_CAN0 Structure */
mbed_official 103:9b881da47c92 1470 __IO uint32_t CANCNTL; /*!< CAN control */
mbed_official 103:9b881da47c92 1471 __IO uint32_t CANSTAT; /*!< Status register */
mbed_official 103:9b881da47c92 1472 __I uint32_t CANEC; /*!< Error counter */
mbed_official 103:9b881da47c92 1473 __IO uint32_t CANBT; /*!< Bit timing register */
mbed_official 103:9b881da47c92 1474 __I uint32_t CANINT; /*!< Interrupt register */
mbed_official 103:9b881da47c92 1475 __IO uint32_t CANTEST; /*!< Test register */
mbed_official 103:9b881da47c92 1476 __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */
mbed_official 103:9b881da47c92 1477 __I uint32_t RESERVED0;
mbed_official 103:9b881da47c92 1478 __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */
mbed_official 103:9b881da47c92 1479
mbed_official 103:9b881da47c92 1480 union {
mbed_official 103:9b881da47c92 1481 __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
mbed_official 103:9b881da47c92 1482 __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
mbed_official 103:9b881da47c92 1483 };
mbed_official 103:9b881da47c92 1484 __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */
mbed_official 103:9b881da47c92 1485 __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */
mbed_official 103:9b881da47c92 1486 __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */
mbed_official 103:9b881da47c92 1487 __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */
mbed_official 103:9b881da47c92 1488 __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */
mbed_official 103:9b881da47c92 1489 __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */
mbed_official 103:9b881da47c92 1490 __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */
mbed_official 103:9b881da47c92 1491 __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */
mbed_official 103:9b881da47c92 1492 __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */
mbed_official 103:9b881da47c92 1493 __I uint32_t RESERVED1[13];
mbed_official 103:9b881da47c92 1494 __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */
mbed_official 103:9b881da47c92 1495
mbed_official 103:9b881da47c92 1496 union {
mbed_official 103:9b881da47c92 1497 __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
mbed_official 103:9b881da47c92 1498 __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
mbed_official 103:9b881da47c92 1499 };
mbed_official 103:9b881da47c92 1500 __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */
mbed_official 103:9b881da47c92 1501 __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */
mbed_official 103:9b881da47c92 1502 __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
mbed_official 103:9b881da47c92 1503 __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
mbed_official 103:9b881da47c92 1504 __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
mbed_official 245:b4dea936db71 1505 __IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
mbed_official 245:b4dea936db71 1506 __IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
mbed_official 245:b4dea936db71 1507 __IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
mbed_official 245:b4dea936db71 1508 __IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
mbed_official 245:b4dea936db71 1509 __I uint32_t RESERVED2[21];
mbed_official 103:9b881da47c92 1510 __I uint32_t CANTXREQ1; /*!< Transmission request 1 */
mbed_official 103:9b881da47c92 1511 __I uint32_t CANTXREQ2; /*!< Transmission request 2 */
mbed_official 103:9b881da47c92 1512 __I uint32_t RESERVED3[6];
mbed_official 103:9b881da47c92 1513 __I uint32_t CANND1; /*!< New data 1 */
mbed_official 103:9b881da47c92 1514 __I uint32_t CANND2; /*!< New data 2 */
mbed_official 103:9b881da47c92 1515 __I uint32_t RESERVED4[6];
mbed_official 103:9b881da47c92 1516 __I uint32_t CANIR1; /*!< Interrupt pending 1 */
mbed_official 103:9b881da47c92 1517 __I uint32_t CANIR2; /*!< Interrupt pending 2 */
mbed_official 103:9b881da47c92 1518 __I uint32_t RESERVED5[6];
mbed_official 103:9b881da47c92 1519 __I uint32_t CANMSGV1; /*!< Message valid 1 */
mbed_official 103:9b881da47c92 1520 __I uint32_t CANMSGV2; /*!< Message valid 2 */
mbed_official 103:9b881da47c92 1521 __I uint32_t RESERVED6[6];
mbed_official 103:9b881da47c92 1522 __IO uint32_t CANCLKDIV; /*!< Can clock divider register */
mbed_official 103:9b881da47c92 1523 } LPC_C_CAN0_Type;
mbed_official 103:9b881da47c92 1524
mbed_official 103:9b881da47c92 1525
mbed_official 103:9b881da47c92 1526 /* ================================================================================ */
mbed_official 103:9b881da47c92 1527 /* ================ IOCON ================ */
mbed_official 103:9b881da47c92 1528 /* ================================================================================ */
mbed_official 103:9b881da47c92 1529
mbed_official 103:9b881da47c92 1530
mbed_official 103:9b881da47c92 1531 /**
mbed_official 103:9b881da47c92 1532 * @brief I/O pin configuration (IOCON) (IOCON)
mbed_official 103:9b881da47c92 1533 */
mbed_official 103:9b881da47c92 1534
mbed_official 103:9b881da47c92 1535 typedef struct { /*!< IOCON Structure */
mbed_official 103:9b881da47c92 1536 __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1537 __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1538 __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1539 __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1540 __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1541 __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1542 __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1543 __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1544 __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1545 __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1546 __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1547 __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1548 __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1549 __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1550 __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1551 __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1552 __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1553 __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1554 __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1555 __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1556 __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1557 __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
mbed_official 103:9b881da47c92 1558 __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
mbed_official 103:9b881da47c92 1559 the I2C-bus SCL function. */
mbed_official 103:9b881da47c92 1560 __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
mbed_official 103:9b881da47c92 1561 the I2C-bus SCL function. */
mbed_official 103:9b881da47c92 1562 __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1563 __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1564 __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1565 __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1566 __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1567 __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1568 __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1569 __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
mbed_official 103:9b881da47c92 1570 __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1571 __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1572 __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1573 __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1574 __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1575 __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1576 __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1577 __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1578 __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1579 __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1580 __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1581 __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1582 __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1583 __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1584 __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1585 __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1586 __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1587 __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1588 __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1589 __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1590 __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1591 __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1592 __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1593 __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1594 __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1595 __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1596 __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1597 __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1598 __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1599 __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1600 __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1601 __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
mbed_official 103:9b881da47c92 1602 __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1603 __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1604 __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1605 __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1606 __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1607 __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1608 __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1609 __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1610 __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1611 __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1612 __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1613 __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
mbed_official 103:9b881da47c92 1614 } LPC_IOCON_Type;
mbed_official 103:9b881da47c92 1615
mbed_official 103:9b881da47c92 1616
mbed_official 103:9b881da47c92 1617 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 103:9b881da47c92 1618 #if defined(__CC_ARM)
mbed_official 103:9b881da47c92 1619 #pragma pop
mbed_official 103:9b881da47c92 1620 #elif defined(__ICCARM__)
mbed_official 103:9b881da47c92 1621 /* leave anonymous unions enabled */
mbed_official 103:9b881da47c92 1622 #elif defined(__GNUC__)
mbed_official 103:9b881da47c92 1623 /* anonymous unions are enabled by default */
mbed_official 103:9b881da47c92 1624 #elif defined(__TMS470__)
mbed_official 103:9b881da47c92 1625 /* anonymous unions are enabled by default */
mbed_official 103:9b881da47c92 1626 #elif defined(__TASKING__)
mbed_official 103:9b881da47c92 1627 #pragma warning restore
mbed_official 103:9b881da47c92 1628 #else
mbed_official 103:9b881da47c92 1629 #warning Not supported compiler type
mbed_official 103:9b881da47c92 1630 #endif
mbed_official 103:9b881da47c92 1631
mbed_official 103:9b881da47c92 1632
mbed_official 103:9b881da47c92 1633
mbed_official 103:9b881da47c92 1634
mbed_official 103:9b881da47c92 1635 /* ================================================================================ */
mbed_official 103:9b881da47c92 1636 /* ================ Peripheral memory map ================ */
mbed_official 103:9b881da47c92 1637 /* ================================================================================ */
mbed_official 103:9b881da47c92 1638
mbed_official 103:9b881da47c92 1639 #define LPC_GPIO_PORT_BASE 0x1C000000UL
mbed_official 103:9b881da47c92 1640 #define LPC_DMA_BASE 0x1C004000UL
mbed_official 103:9b881da47c92 1641 #define LPC_USB_BASE 0x1C00C000UL
mbed_official 103:9b881da47c92 1642 #define LPC_CRC_BASE 0x1C010000UL
mbed_official 103:9b881da47c92 1643 #define LPC_SCT0_BASE 0x1C018000UL
mbed_official 103:9b881da47c92 1644 #define LPC_SCT1_BASE 0x1C01C000UL
mbed_official 103:9b881da47c92 1645 #define LPC_SCT2_BASE 0x1C020000UL
mbed_official 103:9b881da47c92 1646 #define LPC_SCT3_BASE 0x1C024000UL
mbed_official 103:9b881da47c92 1647 #define LPC_ADC0_BASE 0x40000000UL
mbed_official 103:9b881da47c92 1648 #define LPC_DAC_BASE 0x40004000UL
mbed_official 103:9b881da47c92 1649 #define LPC_ACMP_BASE 0x40008000UL
mbed_official 103:9b881da47c92 1650 #define LPC_INMUX_BASE 0x40014000UL
mbed_official 103:9b881da47c92 1651 #define LPC_RTC_BASE 0x40028000UL
mbed_official 103:9b881da47c92 1652 #define LPC_WWDT_BASE 0x4002C000UL
mbed_official 103:9b881da47c92 1653 #define LPC_SWM_BASE 0x40038000UL
mbed_official 103:9b881da47c92 1654 #define LPC_PMU_BASE 0x4003C000UL
mbed_official 103:9b881da47c92 1655 #define LPC_USART0_BASE 0x40040000UL
mbed_official 103:9b881da47c92 1656 #define LPC_USART1_BASE 0x40044000UL
mbed_official 103:9b881da47c92 1657 #define LPC_SPI0_BASE 0x40048000UL
mbed_official 103:9b881da47c92 1658 #define LPC_SPI1_BASE 0x4004C000UL
mbed_official 103:9b881da47c92 1659 #define LPC_I2C0_BASE 0x40050000UL
mbed_official 103:9b881da47c92 1660 #define LPC_QEI_BASE 0x40058000UL
mbed_official 103:9b881da47c92 1661 #define LPC_SYSCON_BASE 0x40074000UL
mbed_official 103:9b881da47c92 1662 #define LPC_ADC1_BASE 0x40080000UL
mbed_official 103:9b881da47c92 1663 #define LPC_MRT_BASE 0x400A0000UL
mbed_official 103:9b881da47c92 1664 #define LPC_PINT_BASE 0x400A4000UL
mbed_official 103:9b881da47c92 1665 #define LPC_GINT0_BASE 0x400A8000UL
mbed_official 103:9b881da47c92 1666 #define LPC_GINT1_BASE 0x400AC000UL
mbed_official 103:9b881da47c92 1667 #define LPC_RIT_BASE 0x400B4000UL
mbed_official 103:9b881da47c92 1668 #define LPC_SCTIPU_BASE 0x400B8000UL
mbed_official 103:9b881da47c92 1669 #define LPC_FLASHCTRL_BASE 0x400BC000UL
mbed_official 103:9b881da47c92 1670 #define LPC_USART2_BASE 0x400C0000UL
mbed_official 103:9b881da47c92 1671 #define LPC_C_CAN0_BASE 0x400F0000UL
mbed_official 103:9b881da47c92 1672 #define LPC_IOCON_BASE 0x400F8000UL
mbed_official 103:9b881da47c92 1673
mbed_official 103:9b881da47c92 1674
mbed_official 103:9b881da47c92 1675 /* ================================================================================ */
mbed_official 103:9b881da47c92 1676 /* ================ Peripheral declaration ================ */
mbed_official 103:9b881da47c92 1677 /* ================================================================================ */
mbed_official 103:9b881da47c92 1678
mbed_official 103:9b881da47c92 1679 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
mbed_official 103:9b881da47c92 1680 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
mbed_official 103:9b881da47c92 1681 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
mbed_official 103:9b881da47c92 1682 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
mbed_official 103:9b881da47c92 1683 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
mbed_official 103:9b881da47c92 1684 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
mbed_official 103:9b881da47c92 1685 #define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
mbed_official 103:9b881da47c92 1686 #define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
mbed_official 103:9b881da47c92 1687 #define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
mbed_official 103:9b881da47c92 1688 #define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
mbed_official 103:9b881da47c92 1689 #define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
mbed_official 103:9b881da47c92 1690 #define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
mbed_official 103:9b881da47c92 1691 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
mbed_official 103:9b881da47c92 1692 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
mbed_official 103:9b881da47c92 1693 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
mbed_official 103:9b881da47c92 1694 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
mbed_official 103:9b881da47c92 1695 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
mbed_official 103:9b881da47c92 1696 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
mbed_official 103:9b881da47c92 1697 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
mbed_official 103:9b881da47c92 1698 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
mbed_official 103:9b881da47c92 1699 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
mbed_official 103:9b881da47c92 1700 #define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
mbed_official 103:9b881da47c92 1701 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
mbed_official 103:9b881da47c92 1702 #define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
mbed_official 103:9b881da47c92 1703 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
mbed_official 103:9b881da47c92 1704 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
mbed_official 103:9b881da47c92 1705 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
mbed_official 103:9b881da47c92 1706 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
mbed_official 103:9b881da47c92 1707 #define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
mbed_official 103:9b881da47c92 1708 #define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
mbed_official 103:9b881da47c92 1709 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
mbed_official 103:9b881da47c92 1710 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
mbed_official 103:9b881da47c92 1711 #define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
mbed_official 103:9b881da47c92 1712 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
mbed_official 103:9b881da47c92 1713
mbed_official 103:9b881da47c92 1714
mbed_official 103:9b881da47c92 1715 /** @} */ /* End of group Device_Peripheral_Registers */
mbed_official 103:9b881da47c92 1716 /** @} */ /* End of group LPC15xx */
mbed_official 103:9b881da47c92 1717 /** @} */ /* End of group (null) */
mbed_official 103:9b881da47c92 1718
mbed_official 103:9b881da47c92 1719 #ifdef __cplusplus
mbed_official 103:9b881da47c92 1720 }
mbed_official 103:9b881da47c92 1721 #endif
mbed_official 103:9b881da47c92 1722
mbed_official 103:9b881da47c92 1723
mbed_official 103:9b881da47c92 1724 #endif /* LPC15XX_H */
mbed_official 103:9b881da47c92 1725