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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.c@70:c1fbde68b492, 2014-01-07 (annotated)

Committer:
mbed_official
Date:
Tue Jan 07 11:00:05 2014 +0000
Revision:
70:c1fbde68b492
Parent:
52:a51c77007319
Child:
84:f54042cbc282
Synchronized with git revision 3f438a307904431f2782db3c8fa49946b9fc1d85



Full URL: https://github.com/mbedmicro/mbed/commit/3f438a307904431f2782db3c8fa49946b9fc1d85/



[NUCLEO_F103RB] license text changed + sleep hal updated

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 52:a51c77007319 1 /**
mbed_official 52:a51c77007319 2 ******************************************************************************
mbed_official 52:a51c77007319 3 * @file stm32f10x_fsmc.c
mbed_official 52:a51c77007319 4 * @author MCD Application Team
mbed_official 52:a51c77007319 5 * @version V3.5.0
mbed_official 52:a51c77007319 6 * @date 11-March-2011
mbed_official 52:a51c77007319 7 * @brief This file provides all the FSMC firmware functions.
mbed_official 70:c1fbde68b492 8 *******************************************************************************
mbed_official 70:c1fbde68b492 9 * Copyright (c) 2014, STMicroelectronics
mbed_official 70:c1fbde68b492 10 * All rights reserved.
mbed_official 70:c1fbde68b492 11 *
mbed_official 70:c1fbde68b492 12 * Redistribution and use in source and binary forms, with or without
mbed_official 70:c1fbde68b492 13 * modification, are permitted provided that the following conditions are met:
mbed_official 70:c1fbde68b492 14 *
mbed_official 70:c1fbde68b492 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 70:c1fbde68b492 16 * this list of conditions and the following disclaimer.
mbed_official 70:c1fbde68b492 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 70:c1fbde68b492 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 70:c1fbde68b492 19 * and/or other materials provided with the distribution.
mbed_official 70:c1fbde68b492 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 70:c1fbde68b492 21 * may be used to endorse or promote products derived from this software
mbed_official 70:c1fbde68b492 22 * without specific prior written permission.
mbed_official 70:c1fbde68b492 23 *
mbed_official 70:c1fbde68b492 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 70:c1fbde68b492 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 70:c1fbde68b492 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 70:c1fbde68b492 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 70:c1fbde68b492 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 70:c1fbde68b492 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 70:c1fbde68b492 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 70:c1fbde68b492 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 70:c1fbde68b492 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 70:c1fbde68b492 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 70:c1fbde68b492 34 *******************************************************************************
mbed_official 70:c1fbde68b492 35 */
mbed_official 52:a51c77007319 36
mbed_official 52:a51c77007319 37 /* Includes ------------------------------------------------------------------*/
mbed_official 52:a51c77007319 38 #include "stm32f10x_fsmc.h"
mbed_official 52:a51c77007319 39 #include "stm32f10x_rcc.h"
mbed_official 52:a51c77007319 40
mbed_official 52:a51c77007319 41 /** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official 52:a51c77007319 42 * @{
mbed_official 52:a51c77007319 43 */
mbed_official 52:a51c77007319 44
mbed_official 52:a51c77007319 45 /** @defgroup FSMC
mbed_official 52:a51c77007319 46 * @brief FSMC driver modules
mbed_official 52:a51c77007319 47 * @{
mbed_official 52:a51c77007319 48 */
mbed_official 52:a51c77007319 49
mbed_official 52:a51c77007319 50 /** @defgroup FSMC_Private_TypesDefinitions
mbed_official 52:a51c77007319 51 * @{
mbed_official 52:a51c77007319 52 */
mbed_official 52:a51c77007319 53 /**
mbed_official 52:a51c77007319 54 * @}
mbed_official 52:a51c77007319 55 */
mbed_official 52:a51c77007319 56
mbed_official 52:a51c77007319 57 /** @defgroup FSMC_Private_Defines
mbed_official 52:a51c77007319 58 * @{
mbed_official 52:a51c77007319 59 */
mbed_official 52:a51c77007319 60
mbed_official 52:a51c77007319 61 /* --------------------- FSMC registers bit mask ---------------------------- */
mbed_official 52:a51c77007319 62
mbed_official 52:a51c77007319 63 /* FSMC BCRx Mask */
mbed_official 52:a51c77007319 64 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
mbed_official 52:a51c77007319 65 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
mbed_official 52:a51c77007319 66 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 67
mbed_official 52:a51c77007319 68 /* FSMC PCRx Mask */
mbed_official 52:a51c77007319 69 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
mbed_official 52:a51c77007319 70 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
mbed_official 52:a51c77007319 71 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
mbed_official 52:a51c77007319 72 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
mbed_official 52:a51c77007319 73 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
mbed_official 52:a51c77007319 74 /**
mbed_official 52:a51c77007319 75 * @}
mbed_official 52:a51c77007319 76 */
mbed_official 52:a51c77007319 77
mbed_official 52:a51c77007319 78 /** @defgroup FSMC_Private_Macros
mbed_official 52:a51c77007319 79 * @{
mbed_official 52:a51c77007319 80 */
mbed_official 52:a51c77007319 81
mbed_official 52:a51c77007319 82 /**
mbed_official 52:a51c77007319 83 * @}
mbed_official 52:a51c77007319 84 */
mbed_official 52:a51c77007319 85
mbed_official 52:a51c77007319 86 /** @defgroup FSMC_Private_Variables
mbed_official 52:a51c77007319 87 * @{
mbed_official 52:a51c77007319 88 */
mbed_official 52:a51c77007319 89
mbed_official 52:a51c77007319 90 /**
mbed_official 52:a51c77007319 91 * @}
mbed_official 52:a51c77007319 92 */
mbed_official 52:a51c77007319 93
mbed_official 52:a51c77007319 94 /** @defgroup FSMC_Private_FunctionPrototypes
mbed_official 52:a51c77007319 95 * @{
mbed_official 52:a51c77007319 96 */
mbed_official 52:a51c77007319 97
mbed_official 52:a51c77007319 98 /**
mbed_official 52:a51c77007319 99 * @}
mbed_official 52:a51c77007319 100 */
mbed_official 52:a51c77007319 101
mbed_official 52:a51c77007319 102 /** @defgroup FSMC_Private_Functions
mbed_official 52:a51c77007319 103 * @{
mbed_official 52:a51c77007319 104 */
mbed_official 52:a51c77007319 105
mbed_official 52:a51c77007319 106 /**
mbed_official 52:a51c77007319 107 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
mbed_official 52:a51c77007319 108 * reset values.
mbed_official 52:a51c77007319 109 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 110 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 111 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 52:a51c77007319 112 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 52:a51c77007319 113 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 52:a51c77007319 114 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 52:a51c77007319 115 * @retval None
mbed_official 52:a51c77007319 116 */
mbed_official 52:a51c77007319 117 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 118 {
mbed_official 52:a51c77007319 119 /* Check the parameter */
mbed_official 52:a51c77007319 120 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 121
mbed_official 52:a51c77007319 122 /* FSMC_Bank1_NORSRAM1 */
mbed_official 52:a51c77007319 123 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
mbed_official 52:a51c77007319 124 {
mbed_official 52:a51c77007319 125 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
mbed_official 52:a51c77007319 126 }
mbed_official 52:a51c77007319 127 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
mbed_official 52:a51c77007319 128 else
mbed_official 52:a51c77007319 129 {
mbed_official 52:a51c77007319 130 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
mbed_official 52:a51c77007319 131 }
mbed_official 52:a51c77007319 132 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 133 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 134 }
mbed_official 52:a51c77007319 135
mbed_official 52:a51c77007319 136 /**
mbed_official 52:a51c77007319 137 * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
mbed_official 52:a51c77007319 138 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 139 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 140 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 141 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 142 * @retval None
mbed_official 52:a51c77007319 143 */
mbed_official 52:a51c77007319 144 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 145 {
mbed_official 52:a51c77007319 146 /* Check the parameter */
mbed_official 52:a51c77007319 147 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 148
mbed_official 52:a51c77007319 149 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 150 {
mbed_official 52:a51c77007319 151 /* Set the FSMC_Bank2 registers to their reset values */
mbed_official 52:a51c77007319 152 FSMC_Bank2->PCR2 = 0x00000018;
mbed_official 52:a51c77007319 153 FSMC_Bank2->SR2 = 0x00000040;
mbed_official 52:a51c77007319 154 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 155 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 156 }
mbed_official 52:a51c77007319 157 /* FSMC_Bank3_NAND */
mbed_official 52:a51c77007319 158 else
mbed_official 52:a51c77007319 159 {
mbed_official 52:a51c77007319 160 /* Set the FSMC_Bank3 registers to their reset values */
mbed_official 52:a51c77007319 161 FSMC_Bank3->PCR3 = 0x00000018;
mbed_official 52:a51c77007319 162 FSMC_Bank3->SR3 = 0x00000040;
mbed_official 52:a51c77007319 163 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 164 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 165 }
mbed_official 52:a51c77007319 166 }
mbed_official 52:a51c77007319 167
mbed_official 52:a51c77007319 168 /**
mbed_official 52:a51c77007319 169 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
mbed_official 52:a51c77007319 170 * @param None
mbed_official 52:a51c77007319 171 * @retval None
mbed_official 52:a51c77007319 172 */
mbed_official 52:a51c77007319 173 void FSMC_PCCARDDeInit(void)
mbed_official 52:a51c77007319 174 {
mbed_official 52:a51c77007319 175 /* Set the FSMC_Bank4 registers to their reset values */
mbed_official 52:a51c77007319 176 FSMC_Bank4->PCR4 = 0x00000018;
mbed_official 52:a51c77007319 177 FSMC_Bank4->SR4 = 0x00000000;
mbed_official 52:a51c77007319 178 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 179 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 180 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
mbed_official 52:a51c77007319 181 }
mbed_official 52:a51c77007319 182
mbed_official 52:a51c77007319 183 /**
mbed_official 52:a51c77007319 184 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
mbed_official 52:a51c77007319 185 * parameters in the FSMC_NORSRAMInitStruct.
mbed_official 52:a51c77007319 186 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 52:a51c77007319 187 * structure that contains the configuration information for
mbed_official 52:a51c77007319 188 * the FSMC NOR/SRAM specified Banks.
mbed_official 52:a51c77007319 189 * @retval None
mbed_official 52:a51c77007319 190 */
mbed_official 52:a51c77007319 191 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 52:a51c77007319 192 {
mbed_official 52:a51c77007319 193 /* Check the parameters */
mbed_official 52:a51c77007319 194 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
mbed_official 52:a51c77007319 195 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
mbed_official 52:a51c77007319 196 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
mbed_official 52:a51c77007319 197 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
mbed_official 52:a51c77007319 198 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
mbed_official 52:a51c77007319 199 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
mbed_official 52:a51c77007319 200 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
mbed_official 52:a51c77007319 201 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
mbed_official 52:a51c77007319 202 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
mbed_official 52:a51c77007319 203 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
mbed_official 52:a51c77007319 204 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
mbed_official 52:a51c77007319 205 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
mbed_official 52:a51c77007319 206 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
mbed_official 52:a51c77007319 207 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 52:a51c77007319 208 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 52:a51c77007319 209 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
mbed_official 52:a51c77007319 210 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
mbed_official 52:a51c77007319 211 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
mbed_official 52:a51c77007319 212 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
mbed_official 52:a51c77007319 213 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
mbed_official 52:a51c77007319 214
mbed_official 52:a51c77007319 215 /* Bank1 NOR/SRAM control register configuration */
mbed_official 52:a51c77007319 216 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 52:a51c77007319 217 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
mbed_official 52:a51c77007319 218 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
mbed_official 52:a51c77007319 219 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
mbed_official 52:a51c77007319 220 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
mbed_official 52:a51c77007319 221 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
mbed_official 52:a51c77007319 222 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
mbed_official 52:a51c77007319 223 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
mbed_official 52:a51c77007319 224 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
mbed_official 52:a51c77007319 225 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
mbed_official 52:a51c77007319 226 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
mbed_official 52:a51c77007319 227 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
mbed_official 52:a51c77007319 228 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
mbed_official 52:a51c77007319 229
mbed_official 52:a51c77007319 230 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
mbed_official 52:a51c77007319 231 {
mbed_official 52:a51c77007319 232 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
mbed_official 52:a51c77007319 233 }
mbed_official 52:a51c77007319 234
mbed_official 52:a51c77007319 235 /* Bank1 NOR/SRAM timing register configuration */
mbed_official 52:a51c77007319 236 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
mbed_official 52:a51c77007319 237 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 52:a51c77007319 238 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
mbed_official 52:a51c77007319 239 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 52:a51c77007319 240 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
mbed_official 52:a51c77007319 241 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 52:a51c77007319 242 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 52:a51c77007319 243 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
mbed_official 52:a51c77007319 244
mbed_official 52:a51c77007319 245
mbed_official 52:a51c77007319 246 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
mbed_official 52:a51c77007319 247 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
mbed_official 52:a51c77007319 248 {
mbed_official 52:a51c77007319 249 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 52:a51c77007319 250 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 52:a51c77007319 251 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
mbed_official 52:a51c77007319 252 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
mbed_official 52:a51c77007319 253 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
mbed_official 52:a51c77007319 254 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
mbed_official 52:a51c77007319 255 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 52:a51c77007319 256 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 52:a51c77007319 257 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
mbed_official 52:a51c77007319 258 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 52:a51c77007319 259 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 52:a51c77007319 260 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 52:a51c77007319 261 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
mbed_official 52:a51c77007319 262 }
mbed_official 52:a51c77007319 263 else
mbed_official 52:a51c77007319 264 {
mbed_official 52:a51c77007319 265 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
mbed_official 52:a51c77007319 266 }
mbed_official 52:a51c77007319 267 }
mbed_official 52:a51c77007319 268
mbed_official 52:a51c77007319 269 /**
mbed_official 52:a51c77007319 270 * @brief Initializes the FSMC NAND Banks according to the specified
mbed_official 52:a51c77007319 271 * parameters in the FSMC_NANDInitStruct.
mbed_official 52:a51c77007319 272 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
mbed_official 52:a51c77007319 273 * structure that contains the configuration information for the FSMC
mbed_official 52:a51c77007319 274 * NAND specified Banks.
mbed_official 52:a51c77007319 275 * @retval None
mbed_official 52:a51c77007319 276 */
mbed_official 52:a51c77007319 277 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
mbed_official 52:a51c77007319 278 {
mbed_official 52:a51c77007319 279 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
mbed_official 52:a51c77007319 280
mbed_official 52:a51c77007319 281 /* Check the parameters */
mbed_official 52:a51c77007319 282 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
mbed_official 52:a51c77007319 283 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
mbed_official 52:a51c77007319 284 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
mbed_official 52:a51c77007319 285 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
mbed_official 52:a51c77007319 286 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
mbed_official 52:a51c77007319 287 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
mbed_official 52:a51c77007319 288 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
mbed_official 52:a51c77007319 289 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 290 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 291 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 292 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 293 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 294 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 295 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 296 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 297
mbed_official 52:a51c77007319 298 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
mbed_official 52:a51c77007319 299 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
mbed_official 52:a51c77007319 300 PCR_MemoryType_NAND |
mbed_official 52:a51c77007319 301 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
mbed_official 52:a51c77007319 302 FSMC_NANDInitStruct->FSMC_ECC |
mbed_official 52:a51c77007319 303 FSMC_NANDInitStruct->FSMC_ECCPageSize |
mbed_official 52:a51c77007319 304 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
mbed_official 52:a51c77007319 305 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
mbed_official 52:a51c77007319 306
mbed_official 52:a51c77007319 307 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 308 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 309 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 310 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 311 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 312
mbed_official 52:a51c77007319 313 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 314 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 315 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 316 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 317 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 318
mbed_official 52:a51c77007319 319 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 320 {
mbed_official 52:a51c77007319 321 /* FSMC_Bank2_NAND registers configuration */
mbed_official 52:a51c77007319 322 FSMC_Bank2->PCR2 = tmppcr;
mbed_official 52:a51c77007319 323 FSMC_Bank2->PMEM2 = tmppmem;
mbed_official 52:a51c77007319 324 FSMC_Bank2->PATT2 = tmppatt;
mbed_official 52:a51c77007319 325 }
mbed_official 52:a51c77007319 326 else
mbed_official 52:a51c77007319 327 {
mbed_official 52:a51c77007319 328 /* FSMC_Bank3_NAND registers configuration */
mbed_official 52:a51c77007319 329 FSMC_Bank3->PCR3 = tmppcr;
mbed_official 52:a51c77007319 330 FSMC_Bank3->PMEM3 = tmppmem;
mbed_official 52:a51c77007319 331 FSMC_Bank3->PATT3 = tmppatt;
mbed_official 52:a51c77007319 332 }
mbed_official 52:a51c77007319 333 }
mbed_official 52:a51c77007319 334
mbed_official 52:a51c77007319 335 /**
mbed_official 52:a51c77007319 336 * @brief Initializes the FSMC PCCARD Bank according to the specified
mbed_official 52:a51c77007319 337 * parameters in the FSMC_PCCARDInitStruct.
mbed_official 52:a51c77007319 338 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
mbed_official 52:a51c77007319 339 * structure that contains the configuration information for the FSMC
mbed_official 52:a51c77007319 340 * PCCARD Bank.
mbed_official 52:a51c77007319 341 * @retval None
mbed_official 52:a51c77007319 342 */
mbed_official 52:a51c77007319 343 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
mbed_official 52:a51c77007319 344 {
mbed_official 52:a51c77007319 345 /* Check the parameters */
mbed_official 52:a51c77007319 346 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
mbed_official 52:a51c77007319 347 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
mbed_official 52:a51c77007319 348 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
mbed_official 52:a51c77007319 349
mbed_official 52:a51c77007319 350 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 351 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 352 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 353 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 354
mbed_official 52:a51c77007319 355 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 356 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 357 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 358 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 359 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
mbed_official 52:a51c77007319 360 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
mbed_official 52:a51c77007319 361 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
mbed_official 52:a51c77007319 362 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
mbed_official 52:a51c77007319 363
mbed_official 52:a51c77007319 364 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
mbed_official 52:a51c77007319 365 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
mbed_official 52:a51c77007319 366 FSMC_MemoryDataWidth_16b |
mbed_official 52:a51c77007319 367 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
mbed_official 52:a51c77007319 368 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
mbed_official 52:a51c77007319 369
mbed_official 52:a51c77007319 370 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 371 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 372 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 373 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 374 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 375
mbed_official 52:a51c77007319 376 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 377 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 378 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 379 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 380 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 381
mbed_official 52:a51c77007319 382 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
mbed_official 52:a51c77007319 383 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
mbed_official 52:a51c77007319 384 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
mbed_official 52:a51c77007319 385 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
mbed_official 52:a51c77007319 386 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
mbed_official 52:a51c77007319 387 }
mbed_official 52:a51c77007319 388
mbed_official 52:a51c77007319 389 /**
mbed_official 52:a51c77007319 390 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
mbed_official 52:a51c77007319 391 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 52:a51c77007319 392 * structure which will be initialized.
mbed_official 52:a51c77007319 393 * @retval None
mbed_official 52:a51c77007319 394 */
mbed_official 52:a51c77007319 395 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 52:a51c77007319 396 {
mbed_official 52:a51c77007319 397 /* Reset NOR/SRAM Init structure parameters values */
mbed_official 52:a51c77007319 398 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
mbed_official 52:a51c77007319 399 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
mbed_official 52:a51c77007319 400 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official 52:a51c77007319 401 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 52:a51c77007319 402 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official 52:a51c77007319 403 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official 52:a51c77007319 404 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official 52:a51c77007319 405 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official 52:a51c77007319 406 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official 52:a51c77007319 407 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official 52:a51c77007319 408 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
mbed_official 52:a51c77007319 409 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official 52:a51c77007319 410 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official 52:a51c77007319 411 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 52:a51c77007319 412 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 52:a51c77007319 413 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 52:a51c77007319 414 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 52:a51c77007319 415 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 52:a51c77007319 416 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 52:a51c77007319 417 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 52:a51c77007319 418 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 52:a51c77007319 419 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 52:a51c77007319 420 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 52:a51c77007319 421 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 52:a51c77007319 422 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 52:a51c77007319 423 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 52:a51c77007319 424 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 52:a51c77007319 425 }
mbed_official 52:a51c77007319 426
mbed_official 52:a51c77007319 427 /**
mbed_official 52:a51c77007319 428 * @brief Fills each FSMC_NANDInitStruct member with its default value.
mbed_official 52:a51c77007319 429 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
mbed_official 52:a51c77007319 430 * structure which will be initialized.
mbed_official 52:a51c77007319 431 * @retval None
mbed_official 52:a51c77007319 432 */
mbed_official 52:a51c77007319 433 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
mbed_official 52:a51c77007319 434 {
mbed_official 52:a51c77007319 435 /* Reset NAND Init structure parameters values */
mbed_official 52:a51c77007319 436 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
mbed_official 52:a51c77007319 437 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
mbed_official 52:a51c77007319 438 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 52:a51c77007319 439 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
mbed_official 52:a51c77007319 440 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
mbed_official 52:a51c77007319 441 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
mbed_official 52:a51c77007319 442 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
mbed_official 52:a51c77007319 443 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 444 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 445 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 446 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 447 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 448 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 449 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 450 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 451 }
mbed_official 52:a51c77007319 452
mbed_official 52:a51c77007319 453 /**
mbed_official 52:a51c77007319 454 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
mbed_official 52:a51c77007319 455 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
mbed_official 52:a51c77007319 456 * structure which will be initialized.
mbed_official 52:a51c77007319 457 * @retval None
mbed_official 52:a51c77007319 458 */
mbed_official 52:a51c77007319 459 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
mbed_official 52:a51c77007319 460 {
mbed_official 52:a51c77007319 461 /* Reset PCCARD Init structure parameters values */
mbed_official 52:a51c77007319 462 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
mbed_official 52:a51c77007319 463 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
mbed_official 52:a51c77007319 464 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
mbed_official 52:a51c77007319 465 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 466 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 467 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 468 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 469 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 470 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 471 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 472 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 473 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
mbed_official 52:a51c77007319 474 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
mbed_official 52:a51c77007319 475 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
mbed_official 52:a51c77007319 476 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
mbed_official 52:a51c77007319 477 }
mbed_official 52:a51c77007319 478
mbed_official 52:a51c77007319 479 /**
mbed_official 52:a51c77007319 480 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
mbed_official 52:a51c77007319 481 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 482 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 483 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 52:a51c77007319 484 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 52:a51c77007319 485 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 52:a51c77007319 486 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 52:a51c77007319 487 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 488 * @retval None
mbed_official 52:a51c77007319 489 */
mbed_official 52:a51c77007319 490 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 491 {
mbed_official 52:a51c77007319 492 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 493 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 494
mbed_official 52:a51c77007319 495 if (NewState != DISABLE)
mbed_official 52:a51c77007319 496 {
mbed_official 52:a51c77007319 497 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
mbed_official 52:a51c77007319 498 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
mbed_official 52:a51c77007319 499 }
mbed_official 52:a51c77007319 500 else
mbed_official 52:a51c77007319 501 {
mbed_official 52:a51c77007319 502 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
mbed_official 52:a51c77007319 503 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
mbed_official 52:a51c77007319 504 }
mbed_official 52:a51c77007319 505 }
mbed_official 52:a51c77007319 506
mbed_official 52:a51c77007319 507 /**
mbed_official 52:a51c77007319 508 * @brief Enables or disables the specified NAND Memory Bank.
mbed_official 52:a51c77007319 509 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 510 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 511 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 512 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 513 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 514 * @retval None
mbed_official 52:a51c77007319 515 */
mbed_official 52:a51c77007319 516 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 517 {
mbed_official 52:a51c77007319 518 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 519 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 520
mbed_official 52:a51c77007319 521 if (NewState != DISABLE)
mbed_official 52:a51c77007319 522 {
mbed_official 52:a51c77007319 523 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
mbed_official 52:a51c77007319 524 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 525 {
mbed_official 52:a51c77007319 526 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 527 }
mbed_official 52:a51c77007319 528 else
mbed_official 52:a51c77007319 529 {
mbed_official 52:a51c77007319 530 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 531 }
mbed_official 52:a51c77007319 532 }
mbed_official 52:a51c77007319 533 else
mbed_official 52:a51c77007319 534 {
mbed_official 52:a51c77007319 535 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
mbed_official 52:a51c77007319 536 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 537 {
mbed_official 52:a51c77007319 538 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 539 }
mbed_official 52:a51c77007319 540 else
mbed_official 52:a51c77007319 541 {
mbed_official 52:a51c77007319 542 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 543 }
mbed_official 52:a51c77007319 544 }
mbed_official 52:a51c77007319 545 }
mbed_official 52:a51c77007319 546
mbed_official 52:a51c77007319 547 /**
mbed_official 52:a51c77007319 548 * @brief Enables or disables the PCCARD Memory Bank.
mbed_official 52:a51c77007319 549 * @param NewState: new state of the PCCARD Memory Bank.
mbed_official 52:a51c77007319 550 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 551 * @retval None
mbed_official 52:a51c77007319 552 */
mbed_official 52:a51c77007319 553 void FSMC_PCCARDCmd(FunctionalState NewState)
mbed_official 52:a51c77007319 554 {
mbed_official 52:a51c77007319 555 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 556
mbed_official 52:a51c77007319 557 if (NewState != DISABLE)
mbed_official 52:a51c77007319 558 {
mbed_official 52:a51c77007319 559 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
mbed_official 52:a51c77007319 560 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
mbed_official 52:a51c77007319 561 }
mbed_official 52:a51c77007319 562 else
mbed_official 52:a51c77007319 563 {
mbed_official 52:a51c77007319 564 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
mbed_official 52:a51c77007319 565 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
mbed_official 52:a51c77007319 566 }
mbed_official 52:a51c77007319 567 }
mbed_official 52:a51c77007319 568
mbed_official 52:a51c77007319 569 /**
mbed_official 52:a51c77007319 570 * @brief Enables or disables the FSMC NAND ECC feature.
mbed_official 52:a51c77007319 571 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 572 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 573 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 574 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 575 * @param NewState: new state of the FSMC NAND ECC feature.
mbed_official 52:a51c77007319 576 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 577 * @retval None
mbed_official 52:a51c77007319 578 */
mbed_official 52:a51c77007319 579 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 52:a51c77007319 580 {
mbed_official 52:a51c77007319 581 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 582 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 583
mbed_official 52:a51c77007319 584 if (NewState != DISABLE)
mbed_official 52:a51c77007319 585 {
mbed_official 52:a51c77007319 586 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
mbed_official 52:a51c77007319 587 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 588 {
mbed_official 52:a51c77007319 589 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
mbed_official 52:a51c77007319 590 }
mbed_official 52:a51c77007319 591 else
mbed_official 52:a51c77007319 592 {
mbed_official 52:a51c77007319 593 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
mbed_official 52:a51c77007319 594 }
mbed_official 52:a51c77007319 595 }
mbed_official 52:a51c77007319 596 else
mbed_official 52:a51c77007319 597 {
mbed_official 52:a51c77007319 598 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
mbed_official 52:a51c77007319 599 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 600 {
mbed_official 52:a51c77007319 601 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
mbed_official 52:a51c77007319 602 }
mbed_official 52:a51c77007319 603 else
mbed_official 52:a51c77007319 604 {
mbed_official 52:a51c77007319 605 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
mbed_official 52:a51c77007319 606 }
mbed_official 52:a51c77007319 607 }
mbed_official 52:a51c77007319 608 }
mbed_official 52:a51c77007319 609
mbed_official 52:a51c77007319 610 /**
mbed_official 52:a51c77007319 611 * @brief Returns the error correction code register value.
mbed_official 52:a51c77007319 612 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 613 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 614 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 615 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 616 * @retval The Error Correction Code (ECC) value.
mbed_official 52:a51c77007319 617 */
mbed_official 52:a51c77007319 618 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
mbed_official 52:a51c77007319 619 {
mbed_official 52:a51c77007319 620 uint32_t eccval = 0x00000000;
mbed_official 52:a51c77007319 621
mbed_official 52:a51c77007319 622 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 623 {
mbed_official 52:a51c77007319 624 /* Get the ECCR2 register value */
mbed_official 52:a51c77007319 625 eccval = FSMC_Bank2->ECCR2;
mbed_official 52:a51c77007319 626 }
mbed_official 52:a51c77007319 627 else
mbed_official 52:a51c77007319 628 {
mbed_official 52:a51c77007319 629 /* Get the ECCR3 register value */
mbed_official 52:a51c77007319 630 eccval = FSMC_Bank3->ECCR3;
mbed_official 52:a51c77007319 631 }
mbed_official 52:a51c77007319 632 /* Return the error correction code value */
mbed_official 52:a51c77007319 633 return(eccval);
mbed_official 52:a51c77007319 634 }
mbed_official 52:a51c77007319 635
mbed_official 52:a51c77007319 636 /**
mbed_official 52:a51c77007319 637 * @brief Enables or disables the specified FSMC interrupts.
mbed_official 52:a51c77007319 638 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 639 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 640 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 641 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 642 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 643 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
mbed_official 52:a51c77007319 644 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 645 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 646 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 647 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 648 * @param NewState: new state of the specified FSMC interrupts.
mbed_official 52:a51c77007319 649 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 650 * @retval None
mbed_official 52:a51c77007319 651 */
mbed_official 52:a51c77007319 652 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
mbed_official 52:a51c77007319 653 {
mbed_official 52:a51c77007319 654 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 655 assert_param(IS_FSMC_IT(FSMC_IT));
mbed_official 52:a51c77007319 656 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 657
mbed_official 52:a51c77007319 658 if (NewState != DISABLE)
mbed_official 52:a51c77007319 659 {
mbed_official 52:a51c77007319 660 /* Enable the selected FSMC_Bank2 interrupts */
mbed_official 52:a51c77007319 661 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 662 {
mbed_official 52:a51c77007319 663 FSMC_Bank2->SR2 |= FSMC_IT;
mbed_official 52:a51c77007319 664 }
mbed_official 52:a51c77007319 665 /* Enable the selected FSMC_Bank3 interrupts */
mbed_official 52:a51c77007319 666 else if (FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 667 {
mbed_official 52:a51c77007319 668 FSMC_Bank3->SR3 |= FSMC_IT;
mbed_official 52:a51c77007319 669 }
mbed_official 52:a51c77007319 670 /* Enable the selected FSMC_Bank4 interrupts */
mbed_official 52:a51c77007319 671 else
mbed_official 52:a51c77007319 672 {
mbed_official 52:a51c77007319 673 FSMC_Bank4->SR4 |= FSMC_IT;
mbed_official 52:a51c77007319 674 }
mbed_official 52:a51c77007319 675 }
mbed_official 52:a51c77007319 676 else
mbed_official 52:a51c77007319 677 {
mbed_official 52:a51c77007319 678 /* Disable the selected FSMC_Bank2 interrupts */
mbed_official 52:a51c77007319 679 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 680 {
mbed_official 52:a51c77007319 681
mbed_official 52:a51c77007319 682 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 683 }
mbed_official 52:a51c77007319 684 /* Disable the selected FSMC_Bank3 interrupts */
mbed_official 52:a51c77007319 685 else if (FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 686 {
mbed_official 52:a51c77007319 687 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 688 }
mbed_official 52:a51c77007319 689 /* Disable the selected FSMC_Bank4 interrupts */
mbed_official 52:a51c77007319 690 else
mbed_official 52:a51c77007319 691 {
mbed_official 52:a51c77007319 692 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
mbed_official 52:a51c77007319 693 }
mbed_official 52:a51c77007319 694 }
mbed_official 52:a51c77007319 695 }
mbed_official 52:a51c77007319 696
mbed_official 52:a51c77007319 697 /**
mbed_official 52:a51c77007319 698 * @brief Checks whether the specified FSMC flag is set or not.
mbed_official 52:a51c77007319 699 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 700 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 701 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 702 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 703 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 704 * @param FSMC_FLAG: specifies the flag to check.
mbed_official 52:a51c77007319 705 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 706 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
mbed_official 52:a51c77007319 707 * @arg FSMC_FLAG_Level: Level detection Flag.
mbed_official 52:a51c77007319 708 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
mbed_official 52:a51c77007319 709 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
mbed_official 52:a51c77007319 710 * @retval The new state of FSMC_FLAG (SET or RESET).
mbed_official 52:a51c77007319 711 */
mbed_official 52:a51c77007319 712 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
mbed_official 52:a51c77007319 713 {
mbed_official 52:a51c77007319 714 FlagStatus bitstatus = RESET;
mbed_official 52:a51c77007319 715 uint32_t tmpsr = 0x00000000;
mbed_official 52:a51c77007319 716
mbed_official 52:a51c77007319 717 /* Check the parameters */
mbed_official 52:a51c77007319 718 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 719 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
mbed_official 52:a51c77007319 720
mbed_official 52:a51c77007319 721 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 722 {
mbed_official 52:a51c77007319 723 tmpsr = FSMC_Bank2->SR2;
mbed_official 52:a51c77007319 724 }
mbed_official 52:a51c77007319 725 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 726 {
mbed_official 52:a51c77007319 727 tmpsr = FSMC_Bank3->SR3;
mbed_official 52:a51c77007319 728 }
mbed_official 52:a51c77007319 729 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 730 else
mbed_official 52:a51c77007319 731 {
mbed_official 52:a51c77007319 732 tmpsr = FSMC_Bank4->SR4;
mbed_official 52:a51c77007319 733 }
mbed_official 52:a51c77007319 734
mbed_official 52:a51c77007319 735 /* Get the flag status */
mbed_official 52:a51c77007319 736 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
mbed_official 52:a51c77007319 737 {
mbed_official 52:a51c77007319 738 bitstatus = SET;
mbed_official 52:a51c77007319 739 }
mbed_official 52:a51c77007319 740 else
mbed_official 52:a51c77007319 741 {
mbed_official 52:a51c77007319 742 bitstatus = RESET;
mbed_official 52:a51c77007319 743 }
mbed_official 52:a51c77007319 744 /* Return the flag status */
mbed_official 52:a51c77007319 745 return bitstatus;
mbed_official 52:a51c77007319 746 }
mbed_official 52:a51c77007319 747
mbed_official 52:a51c77007319 748 /**
mbed_official 52:a51c77007319 749 * @brief Clears the FSMC's pending flags.
mbed_official 52:a51c77007319 750 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 751 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 752 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 753 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 754 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 755 * @param FSMC_FLAG: specifies the flag to clear.
mbed_official 52:a51c77007319 756 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 757 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
mbed_official 52:a51c77007319 758 * @arg FSMC_FLAG_Level: Level detection Flag.
mbed_official 52:a51c77007319 759 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
mbed_official 52:a51c77007319 760 * @retval None
mbed_official 52:a51c77007319 761 */
mbed_official 52:a51c77007319 762 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
mbed_official 52:a51c77007319 763 {
mbed_official 52:a51c77007319 764 /* Check the parameters */
mbed_official 52:a51c77007319 765 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 766 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
mbed_official 52:a51c77007319 767
mbed_official 52:a51c77007319 768 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 769 {
mbed_official 52:a51c77007319 770 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 771 }
mbed_official 52:a51c77007319 772 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 773 {
mbed_official 52:a51c77007319 774 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 775 }
mbed_official 52:a51c77007319 776 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 777 else
mbed_official 52:a51c77007319 778 {
mbed_official 52:a51c77007319 779 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
mbed_official 52:a51c77007319 780 }
mbed_official 52:a51c77007319 781 }
mbed_official 52:a51c77007319 782
mbed_official 52:a51c77007319 783 /**
mbed_official 52:a51c77007319 784 * @brief Checks whether the specified FSMC interrupt has occurred or not.
mbed_official 52:a51c77007319 785 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 786 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 787 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 788 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 789 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 790 * @param FSMC_IT: specifies the FSMC interrupt source to check.
mbed_official 52:a51c77007319 791 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 792 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 793 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 794 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 795 * @retval The new state of FSMC_IT (SET or RESET).
mbed_official 52:a51c77007319 796 */
mbed_official 52:a51c77007319 797 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
mbed_official 52:a51c77007319 798 {
mbed_official 52:a51c77007319 799 ITStatus bitstatus = RESET;
mbed_official 52:a51c77007319 800 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
mbed_official 52:a51c77007319 801
mbed_official 52:a51c77007319 802 /* Check the parameters */
mbed_official 52:a51c77007319 803 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 804 assert_param(IS_FSMC_GET_IT(FSMC_IT));
mbed_official 52:a51c77007319 805
mbed_official 52:a51c77007319 806 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 807 {
mbed_official 52:a51c77007319 808 tmpsr = FSMC_Bank2->SR2;
mbed_official 52:a51c77007319 809 }
mbed_official 52:a51c77007319 810 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 811 {
mbed_official 52:a51c77007319 812 tmpsr = FSMC_Bank3->SR3;
mbed_official 52:a51c77007319 813 }
mbed_official 52:a51c77007319 814 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 815 else
mbed_official 52:a51c77007319 816 {
mbed_official 52:a51c77007319 817 tmpsr = FSMC_Bank4->SR4;
mbed_official 52:a51c77007319 818 }
mbed_official 52:a51c77007319 819
mbed_official 52:a51c77007319 820 itstatus = tmpsr & FSMC_IT;
mbed_official 52:a51c77007319 821
mbed_official 52:a51c77007319 822 itenable = tmpsr & (FSMC_IT >> 3);
mbed_official 52:a51c77007319 823 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
mbed_official 52:a51c77007319 824 {
mbed_official 52:a51c77007319 825 bitstatus = SET;
mbed_official 52:a51c77007319 826 }
mbed_official 52:a51c77007319 827 else
mbed_official 52:a51c77007319 828 {
mbed_official 52:a51c77007319 829 bitstatus = RESET;
mbed_official 52:a51c77007319 830 }
mbed_official 52:a51c77007319 831 return bitstatus;
mbed_official 52:a51c77007319 832 }
mbed_official 52:a51c77007319 833
mbed_official 52:a51c77007319 834 /**
mbed_official 52:a51c77007319 835 * @brief Clears the FSMC's interrupt pending bits.
mbed_official 52:a51c77007319 836 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 52:a51c77007319 837 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 838 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
mbed_official 52:a51c77007319 839 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
mbed_official 52:a51c77007319 840 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
mbed_official 52:a51c77007319 841 * @param FSMC_IT: specifies the interrupt pending bit to clear.
mbed_official 52:a51c77007319 842 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 843 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
mbed_official 52:a51c77007319 844 * @arg FSMC_IT_Level: Level edge detection interrupt.
mbed_official 52:a51c77007319 845 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
mbed_official 52:a51c77007319 846 * @retval None
mbed_official 52:a51c77007319 847 */
mbed_official 52:a51c77007319 848 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
mbed_official 52:a51c77007319 849 {
mbed_official 52:a51c77007319 850 /* Check the parameters */
mbed_official 52:a51c77007319 851 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
mbed_official 52:a51c77007319 852 assert_param(IS_FSMC_IT(FSMC_IT));
mbed_official 52:a51c77007319 853
mbed_official 52:a51c77007319 854 if(FSMC_Bank == FSMC_Bank2_NAND)
mbed_official 52:a51c77007319 855 {
mbed_official 52:a51c77007319 856 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 857 }
mbed_official 52:a51c77007319 858 else if(FSMC_Bank == FSMC_Bank3_NAND)
mbed_official 52:a51c77007319 859 {
mbed_official 52:a51c77007319 860 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 861 }
mbed_official 52:a51c77007319 862 /* FSMC_Bank4_PCCARD*/
mbed_official 52:a51c77007319 863 else
mbed_official 52:a51c77007319 864 {
mbed_official 52:a51c77007319 865 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
mbed_official 52:a51c77007319 866 }
mbed_official 52:a51c77007319 867 }
mbed_official 52:a51c77007319 868
mbed_official 52:a51c77007319 869 /**
mbed_official 52:a51c77007319 870 * @}
mbed_official 52:a51c77007319 871 */
mbed_official 52:a51c77007319 872
mbed_official 52:a51c77007319 873 /**
mbed_official 52:a51c77007319 874 * @}
mbed_official 52:a51c77007319 875 */
mbed_official 52:a51c77007319 876
mbed_official 52:a51c77007319 877 /**
mbed_official 52:a51c77007319 878 * @}
mbed_official 52:a51c77007319 879 */
mbed_official 52:a51c77007319 880
mbed_official 52:a51c77007319 881 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/