mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:: mbed_official
Date:: Thu Aug 20 10:45:13 2015 +0100
Revision:: 613:bc40b8d2aec4
Parent:: 553:063b9f2f393c

Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade

Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/

Nordic: update application start address in GCC linker script

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	553:063b9f2f393c	1	/**
mbed_official	553:063b9f2f393c	2	******************************************************************************
mbed_official	553:063b9f2f393c	3	* @file system_stm32f4xx.c
mbed_official	553:063b9f2f393c	4	* @author MCD Application Team
mbed_official	613:bc40b8d2aec4	5	* @version V2.3.2
mbed_official	613:bc40b8d2aec4	6	* @date 26-June-2015
mbed_official	553:063b9f2f393c	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official	553:063b9f2f393c	8	*
mbed_official	553:063b9f2f393c	9	* This file provides two functions and one global variable to be called from
mbed_official	553:063b9f2f393c	10	* user application:
mbed_official	553:063b9f2f393c	11	* - SystemInit(): This function is called at startup just after reset and
mbed_official	553:063b9f2f393c	12	* before branch to main program. This call is made inside
mbed_official	553:063b9f2f393c	13	* the "startup_stm32f4xx.s" file.
mbed_official	553:063b9f2f393c	14	*
mbed_official	553:063b9f2f393c	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	553:063b9f2f393c	16	* by the user application to setup the SysTick
mbed_official	553:063b9f2f393c	17	* timer or configure other parameters.
mbed_official	553:063b9f2f393c	18	*
mbed_official	553:063b9f2f393c	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	553:063b9f2f393c	20	* be called whenever the core clock is changed
mbed_official	553:063b9f2f393c	21	* during program execution.
mbed_official	553:063b9f2f393c	22	*
mbed_official	553:063b9f2f393c	23	* This file configures the system clock as follows:
mbed_official	553:063b9f2f393c	24	*-----------------------------------------------------------------------------
mbed_official	553:063b9f2f393c	25	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
mbed_official	553:063b9f2f393c	26	* \| (external 8 MHz clock) \| (internal 16 MHz)
mbed_official	553:063b9f2f393c	27	* \| 2- PLL_HSE_XTAL \|
mbed_official	553:063b9f2f393c	28	* \| (external 8 MHz xtal) \|
mbed_official	553:063b9f2f393c	29	*-----------------------------------------------------------------------------
mbed_official	613:bc40b8d2aec4	30	* SYSCLK(MHz) \| 180 \| 180
mbed_official	553:063b9f2f393c	31	*-----------------------------------------------------------------------------
mbed_official	613:bc40b8d2aec4	32	* AHBCLK (MHz) \| 180 \| 180
mbed_official	553:063b9f2f393c	33	*-----------------------------------------------------------------------------
mbed_official	613:bc40b8d2aec4	34	* APB1CLK (MHz) \| 45 \| 45
mbed_official	553:063b9f2f393c	35	*-----------------------------------------------------------------------------
mbed_official	613:bc40b8d2aec4	36	* APB2CLK (MHz) \| 90 \| 90
mbed_official	553:063b9f2f393c	37	*-----------------------------------------------------------------------------
mbed_official	553:063b9f2f393c	38	* USB capable (48 MHz precise clock) \| YES \| NO
mbed_official	553:063b9f2f393c	39	*-----------------------------------------------------------------------------
mbed_official	553:063b9f2f393c	40	******************************************************************************
mbed_official	553:063b9f2f393c	41	* @attention
mbed_official	553:063b9f2f393c	42	*
mbed_official	553:063b9f2f393c	43	* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
mbed_official	553:063b9f2f393c	44	*
mbed_official	553:063b9f2f393c	45	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	553:063b9f2f393c	46	* are permitted provided that the following conditions are met:
mbed_official	553:063b9f2f393c	47	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	553:063b9f2f393c	48	* this list of conditions and the following disclaimer.
mbed_official	553:063b9f2f393c	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	553:063b9f2f393c	50	* this list of conditions and the following disclaimer in the documentation
mbed_official	553:063b9f2f393c	51	* and/or other materials provided with the distribution.
mbed_official	553:063b9f2f393c	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	553:063b9f2f393c	53	* may be used to endorse or promote products derived from this software
mbed_official	553:063b9f2f393c	54	* without specific prior written permission.
mbed_official	553:063b9f2f393c	55	*
mbed_official	553:063b9f2f393c	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	553:063b9f2f393c	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	553:063b9f2f393c	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	553:063b9f2f393c	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	553:063b9f2f393c	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	553:063b9f2f393c	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	553:063b9f2f393c	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	553:063b9f2f393c	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	553:063b9f2f393c	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	553:063b9f2f393c	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	553:063b9f2f393c	66	*
mbed_official	553:063b9f2f393c	67	******************************************************************************
mbed_official	553:063b9f2f393c	68	*/
mbed_official	553:063b9f2f393c	69
mbed_official	553:063b9f2f393c	70	/** @addtogroup CMSIS
mbed_official	553:063b9f2f393c	71	* @{
mbed_official	553:063b9f2f393c	72	*/
mbed_official	553:063b9f2f393c	73
mbed_official	553:063b9f2f393c	74	/** @addtogroup stm32f4xx_system
mbed_official	553:063b9f2f393c	75	* @{
mbed_official	553:063b9f2f393c	76	*/
mbed_official	553:063b9f2f393c	77
mbed_official	553:063b9f2f393c	78	/** @addtogroup STM32F4xx_System_Private_Includes
mbed_official	553:063b9f2f393c	79	* @{
mbed_official	553:063b9f2f393c	80	*/
mbed_official	553:063b9f2f393c	81
mbed_official	553:063b9f2f393c	82
mbed_official	553:063b9f2f393c	83	#include "stm32f4xx.h"
mbed_official	553:063b9f2f393c	84	#include "hal_tick.h"
mbed_official	553:063b9f2f393c	85
mbed_official	553:063b9f2f393c	86	#if !defined (HSE_VALUE)
mbed_official	553:063b9f2f393c	87	#define HSE_VALUE ((uint32_t)8000000) /!< Default value of the External oscillator in Hz /
mbed_official	553:063b9f2f393c	88	#endif /* HSE_VALUE */
mbed_official	553:063b9f2f393c	89
mbed_official	553:063b9f2f393c	90	#if !defined (HSI_VALUE)
mbed_official	553:063b9f2f393c	91	#define HSI_VALUE ((uint32_t)16000000) /!< Value of the Internal oscillator in Hz/
mbed_official	553:063b9f2f393c	92	#endif /* HSI_VALUE */
mbed_official	553:063b9f2f393c	93
mbed_official	553:063b9f2f393c	94	/**
mbed_official	553:063b9f2f393c	95	* @}
mbed_official	553:063b9f2f393c	96	*/
mbed_official	553:063b9f2f393c	97
mbed_official	553:063b9f2f393c	98	/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official	553:063b9f2f393c	99	* @{
mbed_official	553:063b9f2f393c	100	*/
mbed_official	553:063b9f2f393c	101
mbed_official	553:063b9f2f393c	102	/**
mbed_official	553:063b9f2f393c	103	* @}
mbed_official	553:063b9f2f393c	104	*/
mbed_official	553:063b9f2f393c	105
mbed_official	553:063b9f2f393c	106	/** @addtogroup STM32F4xx_System_Private_Defines
mbed_official	553:063b9f2f393c	107	* @{
mbed_official	553:063b9f2f393c	108	*/
mbed_official	553:063b9f2f393c	109
mbed_official	553:063b9f2f393c	110	/*********************** Miscellaneous Configuration **********************/
mbed_official	553:063b9f2f393c	111	/!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory /
mbed_official	613:bc40b8d2aec4	112	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
mbed_official	613:bc40b8d2aec4	113	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	553:063b9f2f393c	114	/* #define DATA_IN_ExtSRAM */
mbed_official	613:bc40b8d2aec4	115	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx */
mbed_official	553:063b9f2f393c	116
mbed_official	613:bc40b8d2aec4	117	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
mbed_official	613:bc40b8d2aec4	118	defined(STM32F446xx)
mbed_official	553:063b9f2f393c	119	/* #define DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	120	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	553:063b9f2f393c	121
mbed_official	553:063b9f2f393c	122	#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official	553:063b9f2f393c	123	#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official	553:063b9f2f393c	124	#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	125
mbed_official	553:063b9f2f393c	126	/*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official	553:063b9f2f393c	127	Internal SRAM. */
mbed_official	553:063b9f2f393c	128	/* #define VECT_TAB_SRAM */
mbed_official	553:063b9f2f393c	129	#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official	553:063b9f2f393c	130	This value must be a multiple of 0x200. */
mbed_official	553:063b9f2f393c	131	/******************************************************************************/
mbed_official	553:063b9f2f393c	132
mbed_official	553:063b9f2f393c	133	/**
mbed_official	553:063b9f2f393c	134	* @}
mbed_official	553:063b9f2f393c	135	*/
mbed_official	553:063b9f2f393c	136
mbed_official	553:063b9f2f393c	137	/** @addtogroup STM32F4xx_System_Private_Macros
mbed_official	553:063b9f2f393c	138	* @{
mbed_official	553:063b9f2f393c	139	*/
mbed_official	553:063b9f2f393c	140
mbed_official	553:063b9f2f393c	141	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official	553:063b9f2f393c	142	#define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official	553:063b9f2f393c	143	#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
mbed_official	613:bc40b8d2aec4	144	#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
mbed_official	553:063b9f2f393c	145
mbed_official	553:063b9f2f393c	146	/**
mbed_official	553:063b9f2f393c	147	* @}
mbed_official	553:063b9f2f393c	148	*/
mbed_official	553:063b9f2f393c	149
mbed_official	553:063b9f2f393c	150	/** @addtogroup STM32F4xx_System_Private_Variables
mbed_official	553:063b9f2f393c	151	* @{
mbed_official	553:063b9f2f393c	152	*/
mbed_official	553:063b9f2f393c	153	/* This variable is updated in three ways:
mbed_official	553:063b9f2f393c	154	1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official	553:063b9f2f393c	155	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official	553:063b9f2f393c	156	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official	553:063b9f2f393c	157	Note: If you use this function to configure the system clock; then there
mbed_official	553:063b9f2f393c	158	is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official	553:063b9f2f393c	159	variable is updated automatically.
mbed_official	553:063b9f2f393c	160	*/
mbed_official	613:bc40b8d2aec4	161	uint32_t SystemCoreClock = 16000000;
mbed_official	613:bc40b8d2aec4	162	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	553:063b9f2f393c	163
mbed_official	553:063b9f2f393c	164	/**
mbed_official	553:063b9f2f393c	165	* @}
mbed_official	553:063b9f2f393c	166	*/
mbed_official	553:063b9f2f393c	167
mbed_official	553:063b9f2f393c	168	/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official	553:063b9f2f393c	169	* @{
mbed_official	553:063b9f2f393c	170	*/
mbed_official	553:063b9f2f393c	171
mbed_official	553:063b9f2f393c	172	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
mbed_official	553:063b9f2f393c	173	static void SystemInit_ExtMemCtl(void);
mbed_official	553:063b9f2f393c	174	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	175
mbed_official	553:063b9f2f393c	176	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	553:063b9f2f393c	177	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official	553:063b9f2f393c	178	#endif
mbed_official	553:063b9f2f393c	179
mbed_official	553:063b9f2f393c	180	uint8_t SetSysClock_PLL_HSI(void);
mbed_official	553:063b9f2f393c	181
mbed_official	553:063b9f2f393c	182	/**
mbed_official	553:063b9f2f393c	183	* @}
mbed_official	553:063b9f2f393c	184	*/
mbed_official	553:063b9f2f393c	185
mbed_official	553:063b9f2f393c	186	/** @addtogroup STM32F4xx_System_Private_Functions
mbed_official	553:063b9f2f393c	187	* @{
mbed_official	553:063b9f2f393c	188	*/
mbed_official	553:063b9f2f393c	189
mbed_official	553:063b9f2f393c	190	/**
mbed_official	553:063b9f2f393c	191	* @brief Setup the microcontroller system
mbed_official	553:063b9f2f393c	192	* Initialize the FPU setting, vector table location and External memory
mbed_official	553:063b9f2f393c	193	* configuration.
mbed_official	553:063b9f2f393c	194	* @param None
mbed_official	553:063b9f2f393c	195	* @retval None
mbed_official	553:063b9f2f393c	196	*/
mbed_official	553:063b9f2f393c	197	void SystemInit(void)
mbed_official	553:063b9f2f393c	198	{
mbed_official	553:063b9f2f393c	199	/* FPU settings ------------------------------------------------------------*/
mbed_official	553:063b9f2f393c	200	#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official	553:063b9f2f393c	201	SCB->CPACR \|= ((3UL << 102)\|(3UL << 112)); /* set CP10 and CP11 Full Access */
mbed_official	553:063b9f2f393c	202	#endif
mbed_official	553:063b9f2f393c	203	/* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official	553:063b9f2f393c	204	/* Set HSION bit */
mbed_official	553:063b9f2f393c	205	RCC->CR \|= (uint32_t)0x00000001;
mbed_official	553:063b9f2f393c	206
mbed_official	553:063b9f2f393c	207	/* Reset CFGR register */
mbed_official	553:063b9f2f393c	208	RCC->CFGR = 0x00000000;
mbed_official	553:063b9f2f393c	209
mbed_official	553:063b9f2f393c	210	/* Reset HSEON, CSSON and PLLON bits */
mbed_official	553:063b9f2f393c	211	RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official	553:063b9f2f393c	212
mbed_official	553:063b9f2f393c	213	/* Reset PLLCFGR register */
mbed_official	553:063b9f2f393c	214	RCC->PLLCFGR = 0x24003010;
mbed_official	553:063b9f2f393c	215
mbed_official	553:063b9f2f393c	216	/* Reset HSEBYP bit */
mbed_official	553:063b9f2f393c	217	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	553:063b9f2f393c	218
mbed_official	553:063b9f2f393c	219	/* Disable all interrupts */
mbed_official	553:063b9f2f393c	220	RCC->CIR = 0x00000000;
mbed_official	553:063b9f2f393c	221
mbed_official	553:063b9f2f393c	222	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
mbed_official	553:063b9f2f393c	223	SystemInit_ExtMemCtl();
mbed_official	553:063b9f2f393c	224	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	225
mbed_official	553:063b9f2f393c	226	/* Configure the Vector Table location add offset address ------------------*/
mbed_official	553:063b9f2f393c	227	#ifdef VECT_TAB_SRAM
mbed_official	553:063b9f2f393c	228	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official	553:063b9f2f393c	229	#else
mbed_official	553:063b9f2f393c	230	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official	553:063b9f2f393c	231	#endif
mbed_official	553:063b9f2f393c	232
mbed_official	553:063b9f2f393c	233	/* Configure the Cube driver */
mbed_official	553:063b9f2f393c	234	SystemCoreClock = 18000000; // At this stage the HSI is used as system clock
mbed_official	553:063b9f2f393c	235	HAL_Init();
mbed_official	553:063b9f2f393c	236
mbed_official	553:063b9f2f393c	237	/* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official	553:063b9f2f393c	238	AHB/APBx prescalers and Flash settings */
mbed_official	553:063b9f2f393c	239	SetSysClock();
mbed_official	553:063b9f2f393c	240
mbed_official	553:063b9f2f393c	241	/* Reset the timer to avoid issues after the RAM initialization */
mbed_official	553:063b9f2f393c	242	TIM_MST_RESET_ON;
mbed_official	553:063b9f2f393c	243	TIM_MST_RESET_OFF;
mbed_official	553:063b9f2f393c	244	}
mbed_official	553:063b9f2f393c	245
mbed_official	553:063b9f2f393c	246	/**
mbed_official	553:063b9f2f393c	247	* @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official	553:063b9f2f393c	248	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	553:063b9f2f393c	249	* be used by the user application to setup the SysTick timer or configure
mbed_official	553:063b9f2f393c	250	* other parameters.
mbed_official	553:063b9f2f393c	251	*
mbed_official	553:063b9f2f393c	252	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	553:063b9f2f393c	253	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	553:063b9f2f393c	254	* based on this variable will be incorrect.
mbed_official	553:063b9f2f393c	255	*
mbed_official	553:063b9f2f393c	256	* @note - The system frequency computed by this function is not the real
mbed_official	553:063b9f2f393c	257	* frequency in the chip. It is calculated based on the predefined
mbed_official	553:063b9f2f393c	258	* constant and the selected clock source:
mbed_official	553:063b9f2f393c	259	*
mbed_official	553:063b9f2f393c	260	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	553:063b9f2f393c	261	*
mbed_official	553:063b9f2f393c	262	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	553:063b9f2f393c	263	*
mbed_official	553:063b9f2f393c	264	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	553:063b9f2f393c	265	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	553:063b9f2f393c	266	*
mbed_official	553:063b9f2f393c	267	* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	553:063b9f2f393c	268	* 16 MHz) but the real value may vary depending on the variations
mbed_official	553:063b9f2f393c	269	* in voltage and temperature.
mbed_official	553:063b9f2f393c	270	*
mbed_official	553:063b9f2f393c	271	* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official	553:063b9f2f393c	272	* depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official	553:063b9f2f393c	273	* is same as the real frequency of the crystal used. Otherwise, this function
mbed_official	553:063b9f2f393c	274	* may have wrong result.
mbed_official	553:063b9f2f393c	275	*
mbed_official	553:063b9f2f393c	276	* - The result of this function could be not correct when using fractional
mbed_official	553:063b9f2f393c	277	* value for HSE crystal.
mbed_official	553:063b9f2f393c	278	*
mbed_official	553:063b9f2f393c	279	* @param None
mbed_official	553:063b9f2f393c	280	* @retval None
mbed_official	553:063b9f2f393c	281	*/
mbed_official	553:063b9f2f393c	282	void SystemCoreClockUpdate(void)
mbed_official	553:063b9f2f393c	283	{
mbed_official	553:063b9f2f393c	284	uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official	553:063b9f2f393c	285
mbed_official	553:063b9f2f393c	286	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	553:063b9f2f393c	287	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	553:063b9f2f393c	288
mbed_official	553:063b9f2f393c	289	switch (tmp)
mbed_official	553:063b9f2f393c	290	{
mbed_official	553:063b9f2f393c	291	case 0x00: /* HSI used as system clock source */
mbed_official	553:063b9f2f393c	292	SystemCoreClock = HSI_VALUE;
mbed_official	553:063b9f2f393c	293	break;
mbed_official	553:063b9f2f393c	294	case 0x04: /* HSE used as system clock source */
mbed_official	553:063b9f2f393c	295	SystemCoreClock = HSE_VALUE;
mbed_official	553:063b9f2f393c	296	break;
mbed_official	553:063b9f2f393c	297	case 0x08: /* PLL used as system clock source */
mbed_official	553:063b9f2f393c	298
mbed_official	553:063b9f2f393c	299	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official	553:063b9f2f393c	300	SYSCLK = PLL_VCO / PLL_P
mbed_official	553:063b9f2f393c	301	*/
mbed_official	553:063b9f2f393c	302	pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official	553:063b9f2f393c	303	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	553:063b9f2f393c	304
mbed_official	553:063b9f2f393c	305	if (pllsource != 0)
mbed_official	553:063b9f2f393c	306	{
mbed_official	553:063b9f2f393c	307	/* HSE used as PLL clock source */
mbed_official	553:063b9f2f393c	308	pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official	553:063b9f2f393c	309	}
mbed_official	553:063b9f2f393c	310	else
mbed_official	553:063b9f2f393c	311	{
mbed_official	553:063b9f2f393c	312	/* HSI used as PLL clock source */
mbed_official	553:063b9f2f393c	313	pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official	553:063b9f2f393c	314	}
mbed_official	553:063b9f2f393c	315
mbed_official	553:063b9f2f393c	316	pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official	553:063b9f2f393c	317	SystemCoreClock = pllvco/pllp;
mbed_official	553:063b9f2f393c	318	break;
mbed_official	553:063b9f2f393c	319	default:
mbed_official	553:063b9f2f393c	320	SystemCoreClock = HSI_VALUE;
mbed_official	553:063b9f2f393c	321	break;
mbed_official	553:063b9f2f393c	322	}
mbed_official	553:063b9f2f393c	323	/* Compute HCLK frequency --------------------------------------------------*/
mbed_official	553:063b9f2f393c	324	/* Get HCLK prescaler */
mbed_official	553:063b9f2f393c	325	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	553:063b9f2f393c	326	/* HCLK frequency */
mbed_official	553:063b9f2f393c	327	SystemCoreClock >>= tmp;
mbed_official	553:063b9f2f393c	328	}
mbed_official	553:063b9f2f393c	329
mbed_official	553:063b9f2f393c	330	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
mbed_official	553:063b9f2f393c	331	/**
mbed_official	553:063b9f2f393c	332	* @brief Setup the external memory controller.
mbed_official	553:063b9f2f393c	333	* Called in startup_stm32f4xx.s before jump to main.
mbed_official	553:063b9f2f393c	334	* This function configures the external memories (SRAM/SDRAM)
mbed_official	553:063b9f2f393c	335	* This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official	553:063b9f2f393c	336	* @param None
mbed_official	553:063b9f2f393c	337	* @retval None
mbed_official	553:063b9f2f393c	338	*/
mbed_official	553:063b9f2f393c	339	void SystemInit_ExtMemCtl(void)
mbed_official	553:063b9f2f393c	340	{
mbed_official	613:bc40b8d2aec4	341	__IO uint32_t tmp = 0x00;
mbed_official	553:063b9f2f393c	342	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
mbed_official	553:063b9f2f393c	343	#if defined (DATA_IN_ExtSDRAM)
mbed_official	553:063b9f2f393c	344	register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official	553:063b9f2f393c	345	register uint32_t index;
mbed_official	553:063b9f2f393c	346
mbed_official	613:bc40b8d2aec4	347	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	348	/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
mbed_official	613:bc40b8d2aec4	349	clock */
mbed_official	613:bc40b8d2aec4	350	RCC->AHB1ENR \|= 0x0000007D;
mbed_official	613:bc40b8d2aec4	351	#else
mbed_official	553:063b9f2f393c	352	/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official	553:063b9f2f393c	353	clock */
mbed_official	553:063b9f2f393c	354	RCC->AHB1ENR \|= 0x000001F8;
mbed_official	613:bc40b8d2aec4	355	#endif /* STM32F446xx */
mbed_official	613:bc40b8d2aec4	356	/* Delay after an RCC peripheral clock enabling */
mbed_official	613:bc40b8d2aec4	357	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
mbed_official	553:063b9f2f393c	358
mbed_official	613:bc40b8d2aec4	359	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	360	/* Connect PAx pins to FMC Alternate function */
mbed_official	613:bc40b8d2aec4	361	GPIOA->AFR[0] \|= 0xC0000000;
mbed_official	613:bc40b8d2aec4	362	GPIOA->AFR[1] \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	363	/* Configure PDx pins in Alternate function mode */
mbed_official	613:bc40b8d2aec4	364	GPIOA->MODER \|= 0x00008000;
mbed_official	613:bc40b8d2aec4	365	/* Configure PDx pins speed to 50 MHz */
mbed_official	613:bc40b8d2aec4	366	GPIOA->OSPEEDR \|= 0x00008000;
mbed_official	613:bc40b8d2aec4	367	/* Configure PDx pins Output type to push-pull */
mbed_official	613:bc40b8d2aec4	368	GPIOA->OTYPER \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	369	/* No pull-up, pull-down for PDx pins */
mbed_official	613:bc40b8d2aec4	370	GPIOA->PUPDR \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	371
mbed_official	613:bc40b8d2aec4	372	/* Connect PCx pins to FMC Alternate function */
mbed_official	613:bc40b8d2aec4	373	GPIOC->AFR[0] \|= 0x00CC0000;
mbed_official	613:bc40b8d2aec4	374	GPIOC->AFR[1] \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	375	/* Configure PDx pins in Alternate function mode */
mbed_official	613:bc40b8d2aec4	376	GPIOC->MODER \|= 0x00000A00;
mbed_official	613:bc40b8d2aec4	377	/* Configure PDx pins speed to 50 MHz */
mbed_official	613:bc40b8d2aec4	378	GPIOC->OSPEEDR \|= 0x00000A00;
mbed_official	613:bc40b8d2aec4	379	/* Configure PDx pins Output type to push-pull */
mbed_official	613:bc40b8d2aec4	380	GPIOC->OTYPER \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	381	/* No pull-up, pull-down for PDx pins */
mbed_official	613:bc40b8d2aec4	382	GPIOC->PUPDR \|= 0x00000000;
mbed_official	613:bc40b8d2aec4	383	#endif /* STM32F446xx */
mbed_official	613:bc40b8d2aec4	384
mbed_official	553:063b9f2f393c	385	/* Connect PDx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	386	GPIOD->AFR[0] = 0x000000CC;
mbed_official	553:063b9f2f393c	387	GPIOD->AFR[1] = 0xCC000CCC;
mbed_official	553:063b9f2f393c	388	/* Configure PDx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	389	GPIOD->MODER = 0xA02A000A;
mbed_official	553:063b9f2f393c	390	/* Configure PDx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	391	GPIOD->OSPEEDR = 0xA02A000A;
mbed_official	553:063b9f2f393c	392	/* Configure PDx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	393	GPIOD->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	394	/* No pull-up, pull-down for PDx pins */
mbed_official	553:063b9f2f393c	395	GPIOD->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	396
mbed_official	553:063b9f2f393c	397	/* Connect PEx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	398	GPIOE->AFR[0] = 0xC00000CC;
mbed_official	553:063b9f2f393c	399	GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	400	/* Configure PEx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	401	GPIOE->MODER = 0xAAAA800A;
mbed_official	553:063b9f2f393c	402	/* Configure PEx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	403	GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official	553:063b9f2f393c	404	/* Configure PEx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	405	GPIOE->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	406	/* No pull-up, pull-down for PEx pins */
mbed_official	553:063b9f2f393c	407	GPIOE->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	408
mbed_official	553:063b9f2f393c	409	/* Connect PFx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	410	GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	411	GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	412	/* Configure PFx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	413	GPIOF->MODER = 0xAA800AAA;
mbed_official	553:063b9f2f393c	414	/* Configure PFx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	415	GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official	553:063b9f2f393c	416	/* Configure PFx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	417	GPIOF->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	418	/* No pull-up, pull-down for PFx pins */
mbed_official	553:063b9f2f393c	419	GPIOF->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	420
mbed_official	553:063b9f2f393c	421	/* Connect PGx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	422	GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	423	GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	424	/* Configure PGx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	425	GPIOG->MODER = 0xAAAAAAAA;
mbed_official	553:063b9f2f393c	426	/* Configure PGx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	427	GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official	553:063b9f2f393c	428	/* Configure PGx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	429	GPIOG->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	430	/* No pull-up, pull-down for PGx pins */
mbed_official	553:063b9f2f393c	431	GPIOG->PUPDR = 0x00000000;
mbed_official	613:bc40b8d2aec4	432
mbed_official	613:bc40b8d2aec4	433	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	553:063b9f2f393c	434	/* Connect PHx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	435	GPIOH->AFR[0] = 0x00C0CC00;
mbed_official	553:063b9f2f393c	436	GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	437	/* Configure PHx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	438	GPIOH->MODER = 0xAAAA08A0;
mbed_official	553:063b9f2f393c	439	/* Configure PHx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	440	GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official	553:063b9f2f393c	441	/* Configure PHx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	442	GPIOH->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	443	/* No pull-up, pull-down for PHx pins */
mbed_official	553:063b9f2f393c	444	GPIOH->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	445
mbed_official	553:063b9f2f393c	446	/* Connect PIx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	447	GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	448	GPIOI->AFR[1] = 0x00000CC0;
mbed_official	553:063b9f2f393c	449	/* Configure PIx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	450	GPIOI->MODER = 0x0028AAAA;
mbed_official	553:063b9f2f393c	451	/* Configure PIx pins speed to 50 MHz */
mbed_official	553:063b9f2f393c	452	GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official	553:063b9f2f393c	453	/* Configure PIx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	454	GPIOI->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	455	/* No pull-up, pull-down for PIx pins */
mbed_official	553:063b9f2f393c	456	GPIOI->PUPDR = 0x00000000;
mbed_official	613:bc40b8d2aec4	457	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	553:063b9f2f393c	458
mbed_official	613:bc40b8d2aec4	459	/-- FMC Configuration -------------------------------------------------------/
mbed_official	553:063b9f2f393c	460	/* Enable the FMC interface clock */
mbed_official	553:063b9f2f393c	461	RCC->AHB3ENR \|= 0x00000001;
mbed_official	613:bc40b8d2aec4	462	/* Delay after an RCC peripheral clock enabling */
mbed_official	613:bc40b8d2aec4	463	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official	613:bc40b8d2aec4	464
mbed_official	553:063b9f2f393c	465	/* Configure and enable SDRAM bank1 */
mbed_official	613:bc40b8d2aec4	466	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	467	FMC_Bank5_6->SDCR[0] = 0x00001954;
mbed_official	613:bc40b8d2aec4	468	#else
mbed_official	553:063b9f2f393c	469	FMC_Bank5_6->SDCR[0] = 0x000019E4;
mbed_official	613:bc40b8d2aec4	470	#endif /* STM32F446xx */
mbed_official	553:063b9f2f393c	471	FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official	553:063b9f2f393c	472
mbed_official	553:063b9f2f393c	473	/* SDRAM initialization sequence */
mbed_official	553:063b9f2f393c	474	/* Clock enable command */
mbed_official	553:063b9f2f393c	475	FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official	553:063b9f2f393c	476	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official	553:063b9f2f393c	477	while((tmpreg != 0) && (timeout-- > 0))
mbed_official	553:063b9f2f393c	478	{
mbed_official	553:063b9f2f393c	479	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official	553:063b9f2f393c	480	}
mbed_official	553:063b9f2f393c	481
mbed_official	553:063b9f2f393c	482	/* Delay */
mbed_official	553:063b9f2f393c	483	for (index = 0; index<1000; index++);
mbed_official	553:063b9f2f393c	484
mbed_official	553:063b9f2f393c	485	/* PALL command */
mbed_official	553:063b9f2f393c	486	FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official	553:063b9f2f393c	487	timeout = 0xFFFF;
mbed_official	553:063b9f2f393c	488	while((tmpreg != 0) && (timeout-- > 0))
mbed_official	553:063b9f2f393c	489	{
mbed_official	553:063b9f2f393c	490	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official	553:063b9f2f393c	491	}
mbed_official	553:063b9f2f393c	492
mbed_official	553:063b9f2f393c	493	/* Auto refresh command */
mbed_official	613:bc40b8d2aec4	494	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	495	FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official	613:bc40b8d2aec4	496	#else
mbed_official	553:063b9f2f393c	497	FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official	613:bc40b8d2aec4	498	#endif /* STM32F446xx */
mbed_official	553:063b9f2f393c	499	timeout = 0xFFFF;
mbed_official	553:063b9f2f393c	500	while((tmpreg != 0) && (timeout-- > 0))
mbed_official	553:063b9f2f393c	501	{
mbed_official	553:063b9f2f393c	502	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official	553:063b9f2f393c	503	}
mbed_official	553:063b9f2f393c	504
mbed_official	553:063b9f2f393c	505	/* MRD register program */
mbed_official	613:bc40b8d2aec4	506	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	507	FMC_Bank5_6->SDCMR = 0x00044014;
mbed_official	613:bc40b8d2aec4	508	#else
mbed_official	553:063b9f2f393c	509	FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official	613:bc40b8d2aec4	510	#endif /* STM32F446xx */
mbed_official	553:063b9f2f393c	511	timeout = 0xFFFF;
mbed_official	553:063b9f2f393c	512	while((tmpreg != 0) && (timeout-- > 0))
mbed_official	553:063b9f2f393c	513	{
mbed_official	553:063b9f2f393c	514	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official	553:063b9f2f393c	515	}
mbed_official	553:063b9f2f393c	516
mbed_official	553:063b9f2f393c	517	/* Set refresh count */
mbed_official	553:063b9f2f393c	518	tmpreg = FMC_Bank5_6->SDRTR;
mbed_official	613:bc40b8d2aec4	519	#if defined(STM32F446xx)
mbed_official	613:bc40b8d2aec4	520	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000050C<<1));
mbed_official	613:bc40b8d2aec4	521	#else
mbed_official	553:063b9f2f393c	522	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000027C<<1));
mbed_official	613:bc40b8d2aec4	523	#endif /* STM32F446xx */
mbed_official	553:063b9f2f393c	524
mbed_official	553:063b9f2f393c	525	/* Disable write protection */
mbed_official	553:063b9f2f393c	526	tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official	553:063b9f2f393c	527	FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official	553:063b9f2f393c	528	#endif /* DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	529	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
mbed_official	553:063b9f2f393c	530
mbed_official	613:bc40b8d2aec4	531	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
mbed_official	613:bc40b8d2aec4	532	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	553:063b9f2f393c	533
mbed_official	553:063b9f2f393c	534	#if defined(DATA_IN_ExtSRAM)
mbed_official	553:063b9f2f393c	535	/-- GPIOs Configuration -----------------------------------------------------/
mbed_official	553:063b9f2f393c	536	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official	553:063b9f2f393c	537	RCC->AHB1ENR \|= 0x00000078;
mbed_official	613:bc40b8d2aec4	538	/* Delay after an RCC peripheral clock enabling */
mbed_official	613:bc40b8d2aec4	539	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
mbed_official	553:063b9f2f393c	540
mbed_official	553:063b9f2f393c	541	/* Connect PDx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	542	GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official	553:063b9f2f393c	543	GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	544	/* Configure PDx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	545	GPIOD->MODER = 0xAAAA0A8A;
mbed_official	553:063b9f2f393c	546	/* Configure PDx pins speed to 100 MHz */
mbed_official	553:063b9f2f393c	547	GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official	553:063b9f2f393c	548	/* Configure PDx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	549	GPIOD->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	550	/* No pull-up, pull-down for PDx pins */
mbed_official	553:063b9f2f393c	551	GPIOD->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	552
mbed_official	553:063b9f2f393c	553	/* Connect PEx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	554	GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official	553:063b9f2f393c	555	GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official	553:063b9f2f393c	556	/* Configure PEx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	557	GPIOE->MODER = 0xAAAA828A;
mbed_official	553:063b9f2f393c	558	/* Configure PEx pins speed to 100 MHz */
mbed_official	553:063b9f2f393c	559	GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official	553:063b9f2f393c	560	/* Configure PEx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	561	GPIOE->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	562	/* No pull-up, pull-down for PEx pins */
mbed_official	553:063b9f2f393c	563	GPIOE->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	564
mbed_official	553:063b9f2f393c	565	/* Connect PFx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	566	GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official	553:063b9f2f393c	567	GPIOF->AFR[1] = 0xCCCC0000;
mbed_official	553:063b9f2f393c	568	/* Configure PFx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	569	GPIOF->MODER = 0xAA000AAA;
mbed_official	553:063b9f2f393c	570	/* Configure PFx pins speed to 100 MHz */
mbed_official	553:063b9f2f393c	571	GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official	553:063b9f2f393c	572	/* Configure PFx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	573	GPIOF->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	574	/* No pull-up, pull-down for PFx pins */
mbed_official	553:063b9f2f393c	575	GPIOF->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	576
mbed_official	553:063b9f2f393c	577	/* Connect PGx pins to FMC Alternate function */
mbed_official	553:063b9f2f393c	578	GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official	553:063b9f2f393c	579	GPIOG->AFR[1] = 0x000000C0;
mbed_official	553:063b9f2f393c	580	/* Configure PGx pins in Alternate function mode */
mbed_official	553:063b9f2f393c	581	GPIOG->MODER = 0x00085AAA;
mbed_official	553:063b9f2f393c	582	/* Configure PGx pins speed to 100 MHz */
mbed_official	553:063b9f2f393c	583	GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official	553:063b9f2f393c	584	/* Configure PGx pins Output type to push-pull */
mbed_official	553:063b9f2f393c	585	GPIOG->OTYPER = 0x00000000;
mbed_official	553:063b9f2f393c	586	/* No pull-up, pull-down for PGx pins */
mbed_official	553:063b9f2f393c	587	GPIOG->PUPDR = 0x00000000;
mbed_official	553:063b9f2f393c	588
mbed_official	613:bc40b8d2aec4	589	/-- FMC/FSMC Configuration --------------------------------------------------/
mbed_official	553:063b9f2f393c	590	/* Enable the FMC/FSMC interface clock */
mbed_official	553:063b9f2f393c	591	RCC->AHB3ENR \|= 0x00000001;
mbed_official	613:bc40b8d2aec4	592
mbed_official	613:bc40b8d2aec4	593	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	613:bc40b8d2aec4	594	/* Delay after an RCC peripheral clock enabling */
mbed_official	613:bc40b8d2aec4	595	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official	553:063b9f2f393c	596	/* Configure and enable Bank1_SRAM2 */
mbed_official	553:063b9f2f393c	597	FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official	553:063b9f2f393c	598	FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official	553:063b9f2f393c	599	FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official	613:bc40b8d2aec4	600	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	553:063b9f2f393c	601
mbed_official	553:063b9f2f393c	602	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	613:bc40b8d2aec4	603	/* Delay after an RCC peripheral clock enabling */
mbed_official	613:bc40b8d2aec4	604	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
mbed_official	553:063b9f2f393c	605	/* Configure and enable Bank1_SRAM2 */
mbed_official	553:063b9f2f393c	606	FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official	553:063b9f2f393c	607	FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official	553:063b9f2f393c	608	FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official	553:063b9f2f393c	609	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	553:063b9f2f393c	610
mbed_official	553:063b9f2f393c	611	#endif /* DATA_IN_ExtSRAM */
mbed_official	613:bc40b8d2aec4	612	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	613:bc40b8d2aec4	613	(void)(tmp);
mbed_official	553:063b9f2f393c	614	}
mbed_official	553:063b9f2f393c	615	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
mbed_official	553:063b9f2f393c	616
mbed_official	553:063b9f2f393c	617	/**
mbed_official	553:063b9f2f393c	618	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official	553:063b9f2f393c	619	* AHB/APBx prescalers and Flash settings
mbed_official	553:063b9f2f393c	620	* @note This function should be called only once the RCC clock configuration
mbed_official	553:063b9f2f393c	621	* is reset to the default reset state (done in SystemInit() function).
mbed_official	553:063b9f2f393c	622	* @param None
mbed_official	553:063b9f2f393c	623	* @retval None
mbed_official	553:063b9f2f393c	624	*/
mbed_official	553:063b9f2f393c	625	void SetSysClock(void)
mbed_official	553:063b9f2f393c	626	{
mbed_official	553:063b9f2f393c	627	/* 1- Try to start with HSE and external clock */
mbed_official	553:063b9f2f393c	628	#if USE_PLL_HSE_EXTC != 0
mbed_official	553:063b9f2f393c	629	if (SetSysClock_PLL_HSE(1) == 0)
mbed_official	553:063b9f2f393c	630	#endif
mbed_official	553:063b9f2f393c	631	{
mbed_official	553:063b9f2f393c	632	/* 2- If fail try to start with HSE and external xtal */
mbed_official	553:063b9f2f393c	633	#if USE_PLL_HSE_XTAL != 0
mbed_official	553:063b9f2f393c	634	if (SetSysClock_PLL_HSE(0) == 0)
mbed_official	553:063b9f2f393c	635	#endif
mbed_official	553:063b9f2f393c	636	{
mbed_official	553:063b9f2f393c	637	/* 3- If fail start with HSI clock */
mbed_official	553:063b9f2f393c	638	if (SetSysClock_PLL_HSI() == 0)
mbed_official	553:063b9f2f393c	639	{
mbed_official	553:063b9f2f393c	640	while(1)
mbed_official	553:063b9f2f393c	641	{
mbed_official	553:063b9f2f393c	642	// [TODO] Put something here to tell the user that a problem occured...
mbed_official	553:063b9f2f393c	643	}
mbed_official	553:063b9f2f393c	644	}
mbed_official	553:063b9f2f393c	645	}
mbed_official	553:063b9f2f393c	646	}
mbed_official	553:063b9f2f393c	647
mbed_official	613:bc40b8d2aec4	648	// Output clock on MCO2 pin(PC9) for debugging purpose
mbed_official	613:bc40b8d2aec4	649	#if DEBUG_MCO == 1
mbed_official	613:bc40b8d2aec4	650	HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
mbed_official	613:bc40b8d2aec4	651	#endif
mbed_official	553:063b9f2f393c	652	}
mbed_official	553:063b9f2f393c	653
mbed_official	553:063b9f2f393c	654	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	553:063b9f2f393c	655	/******************************************************************************/
mbed_official	553:063b9f2f393c	656	/* PLL (clocked by HSE) used as System clock source */
mbed_official	553:063b9f2f393c	657	/******************************************************************************/
mbed_official	553:063b9f2f393c	658	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official	553:063b9f2f393c	659	{
mbed_official	553:063b9f2f393c	660	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	553:063b9f2f393c	661	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	613:bc40b8d2aec4	662	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
mbed_official	613:bc40b8d2aec4	663
mbed_official	553:063b9f2f393c	664	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	553:063b9f2f393c	665	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	553:063b9f2f393c	666	regarding system frequency refer to product datasheet. */
mbed_official	613:bc40b8d2aec4	667	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	553:063b9f2f393c	668	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	553:063b9f2f393c	669
mbed_official	613:bc40b8d2aec4	670	// Enable HSE oscillator and activate PLL with HSE as source
mbed_official	553:063b9f2f393c	671	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official	553:063b9f2f393c	672	if (bypass == 0)
mbed_official	553:063b9f2f393c	673	{
mbed_official	613:bc40b8d2aec4	674	RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official	553:063b9f2f393c	675	}
mbed_official	553:063b9f2f393c	676	else
mbed_official	553:063b9f2f393c	677	{
mbed_official	613:bc40b8d2aec4	678	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
mbed_official	553:063b9f2f393c	679	}
mbed_official	613:bc40b8d2aec4	680
mbed_official	553:063b9f2f393c	681	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	553:063b9f2f393c	682	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official	613:bc40b8d2aec4	683	RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official	613:bc40b8d2aec4	684	RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
mbed_official	613:bc40b8d2aec4	685	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
mbed_official	613:bc40b8d2aec4	686	RCC_OscInitStruct.PLL.PLLQ = 7; //
mbed_official	613:bc40b8d2aec4	687	RCC_OscInitStruct.PLL.PLLR = 2; //
mbed_official	553:063b9f2f393c	688	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	553:063b9f2f393c	689	{
mbed_official	553:063b9f2f393c	690	return 0; // FAIL
mbed_official	553:063b9f2f393c	691	}
mbed_official	553:063b9f2f393c	692
mbed_official	613:bc40b8d2aec4	693	// Activate the OverDrive to reach the 180 MHz Frequency
mbed_official	613:bc40b8d2aec4	694	if (HAL_PWREx_ActivateOverDrive() != HAL_OK)
mbed_official	613:bc40b8d2aec4	695	{
mbed_official	613:bc40b8d2aec4	696	return 0; // FAIL
mbed_official	613:bc40b8d2aec4	697	}
mbed_official	613:bc40b8d2aec4	698
mbed_official	613:bc40b8d2aec4	699	// Select PLLSAI output as USB clock source
mbed_official	613:bc40b8d2aec4	700	PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
mbed_official	613:bc40b8d2aec4	701	PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
mbed_official	613:bc40b8d2aec4	702	PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
mbed_official	613:bc40b8d2aec4	703	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
mbed_official	613:bc40b8d2aec4	704	PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP;
mbed_official	613:bc40b8d2aec4	705	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
mbed_official	613:bc40b8d2aec4	706
mbed_official	613:bc40b8d2aec4	707	// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official	613:bc40b8d2aec4	708	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
mbed_official	553:063b9f2f393c	709	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
mbed_official	613:bc40b8d2aec4	710	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
mbed_official	613:bc40b8d2aec4	711	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
mbed_official	613:bc40b8d2aec4	712	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
mbed_official	553:063b9f2f393c	713	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
mbed_official	553:063b9f2f393c	714	{
mbed_official	553:063b9f2f393c	715	return 0; // FAIL
mbed_official	553:063b9f2f393c	716	}
mbed_official	553:063b9f2f393c	717
mbed_official	613:bc40b8d2aec4	718	// Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official	613:bc40b8d2aec4	719	#if DEBUG_MCO == 1
mbed_official	613:bc40b8d2aec4	720	if (bypass == 0)
mbed_official	613:bc40b8d2aec4	721	HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
mbed_official	613:bc40b8d2aec4	722	else
mbed_official	613:bc40b8d2aec4	723	HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
mbed_official	613:bc40b8d2aec4	724	#endif
mbed_official	613:bc40b8d2aec4	725
mbed_official	553:063b9f2f393c	726	return 1; // OK
mbed_official	553:063b9f2f393c	727	}
mbed_official	553:063b9f2f393c	728	#endif
mbed_official	553:063b9f2f393c	729
mbed_official	553:063b9f2f393c	730	/******************************************************************************/
mbed_official	553:063b9f2f393c	731	/* PLL (clocked by HSI) used as System clock source */
mbed_official	553:063b9f2f393c	732	/******************************************************************************/
mbed_official	553:063b9f2f393c	733	uint8_t SetSysClock_PLL_HSI(void)
mbed_official	553:063b9f2f393c	734	{
mbed_official	553:063b9f2f393c	735	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	553:063b9f2f393c	736	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	553:063b9f2f393c	737
mbed_official	553:063b9f2f393c	738	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	553:063b9f2f393c	739	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	553:063b9f2f393c	740	regarding system frequency refer to product datasheet. */
mbed_official	613:bc40b8d2aec4	741	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	613:bc40b8d2aec4	742	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	553:063b9f2f393c	743
mbed_official	613:bc40b8d2aec4	744	// Enable HSI oscillator and activate PLL with HSI as source
mbed_official	553:063b9f2f393c	745	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_HSE;
mbed_official	553:063b9f2f393c	746	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official	553:063b9f2f393c	747	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official	553:063b9f2f393c	748	RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official	553:063b9f2f393c	749	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	553:063b9f2f393c	750	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official	613:bc40b8d2aec4	751	RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official	613:bc40b8d2aec4	752	RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
mbed_official	613:bc40b8d2aec4	753	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
mbed_official	613:bc40b8d2aec4	754	RCC_OscInitStruct.PLL.PLLQ = 7; //
mbed_official	613:bc40b8d2aec4	755	RCC_OscInitStruct.PLL.PLLQ = 6; //
mbed_official	553:063b9f2f393c	756	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	553:063b9f2f393c	757	{
mbed_official	553:063b9f2f393c	758	return 0; // FAIL
mbed_official	553:063b9f2f393c	759	}
mbed_official	553:063b9f2f393c	760
mbed_official	553:063b9f2f393c	761	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	553:063b9f2f393c	762	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	613:bc40b8d2aec4	763	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
mbed_official	613:bc40b8d2aec4	764	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
mbed_official	613:bc40b8d2aec4	765	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
mbed_official	613:bc40b8d2aec4	766	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
mbed_official	613:bc40b8d2aec4	767	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
mbed_official	553:063b9f2f393c	768	{
mbed_official	553:063b9f2f393c	769	return 0; // FAIL
mbed_official	553:063b9f2f393c	770	}
mbed_official	553:063b9f2f393c	771
mbed_official	613:bc40b8d2aec4	772	// Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official	613:bc40b8d2aec4	773	#if DEBUG_MCO == 1
mbed_official	613:bc40b8d2aec4	774	HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official	613:bc40b8d2aec4	775	#endif
mbed_official	553:063b9f2f393c	776
mbed_official	553:063b9f2f393c	777	return 1; // OK
mbed_official	553:063b9f2f393c	778	}
mbed_official	553:063b9f2f393c	779
mbed_official	553:063b9f2f393c	780	/**
mbed_official	553:063b9f2f393c	781	* @}
mbed_official	553:063b9f2f393c	782	*/
mbed_official	553:063b9f2f393c	783
mbed_official	553:063b9f2f393c	784	/**
mbed_official	553:063b9f2f393c	785	* @}
mbed_official	553:063b9f2f393c	786	*/
mbed_official	613:bc40b8d2aec4	787
mbed_official	553:063b9f2f393c	788	/**
mbed_official	553:063b9f2f393c	789	* @}
mbed_official	613:bc40b8d2aec4	790	*/
mbed_official	553:063b9f2f393c	791	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/