mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_TCC2_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_TCC2_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for TCC2 peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
mbed_official 579:53297373a894 7 #define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
mbed_official 579:53297373a894 8 #define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
mbed_official 579:53297373a894 9 #define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
mbed_official 579:53297373a894 10 #define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 11 #define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 12 #define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */
mbed_official 579:53297373a894 13 #define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
mbed_official 579:53297373a894 14 #define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
mbed_official 579:53297373a894 15 #define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
mbed_official 579:53297373a894 16 #define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
mbed_official 579:53297373a894 17 #define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 18 #define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
mbed_official 579:53297373a894 19 #define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
mbed_official 579:53297373a894 20 #define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
mbed_official 579:53297373a894 21 #define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
mbed_official 579:53297373a894 22 #define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
mbed_official 579:53297373a894 23 #define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
mbed_official 579:53297373a894 24 #define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
mbed_official 579:53297373a894 25 #define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
mbed_official 579:53297373a894 26 #define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
mbed_official 579:53297373a894 27 #define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
mbed_official 579:53297373a894 28 #else
mbed_official 579:53297373a894 29 #define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
mbed_official 579:53297373a894 30 #define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
mbed_official 579:53297373a894 31 #define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
mbed_official 579:53297373a894 32 #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
mbed_official 579:53297373a894 33 #define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 34 #define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 35 #define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */
mbed_official 579:53297373a894 36 #define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
mbed_official 579:53297373a894 37 #define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
mbed_official 579:53297373a894 38 #define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
mbed_official 579:53297373a894 39 #define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
mbed_official 579:53297373a894 40 #define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 41 #define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
mbed_official 579:53297373a894 42 #define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
mbed_official 579:53297373a894 43 #define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
mbed_official 579:53297373a894 44 #define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
mbed_official 579:53297373a894 45 #define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
mbed_official 579:53297373a894 46 #define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
mbed_official 579:53297373a894 47 #define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
mbed_official 579:53297373a894 48 #define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
mbed_official 579:53297373a894 49 #define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
mbed_official 579:53297373a894 50 #define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
mbed_official 579:53297373a894 51 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 52
mbed_official 579:53297373a894 53 /* ========== Instance parameters for TCC2 peripheral ========== */
mbed_official 579:53297373a894 54 #define TCC2_CC_NUM 2 // Number of Compare/Capture units
mbed_official 579:53297373a894 55 #define TCC2_DITHERING 0 // Dithering feature implemented
mbed_official 579:53297373a894 56 #define TCC2_DMAC_ID_MC_0 22
mbed_official 579:53297373a894 57 #define TCC2_DMAC_ID_MC_1 23
mbed_official 579:53297373a894 58 #define TCC2_DMAC_ID_MC_LSB 22
mbed_official 579:53297373a894 59 #define TCC2_DMAC_ID_MC_MSB 23
mbed_official 579:53297373a894 60 #define TCC2_DMAC_ID_MC_SIZE 2
mbed_official 579:53297373a894 61 #define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
mbed_official 579:53297373a894 62 #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
mbed_official 579:53297373a894 63 #define TCC2_EXT 0 // Coding of implemented extended features
mbed_official 579:53297373a894 64 #define TCC2_GCLK_ID 27 // Index of Generic Clock
mbed_official 579:53297373a894 65 #define TCC2_OTMX 0 // Output Matrix feature implemented
mbed_official 579:53297373a894 66 #define TCC2_OW_NUM 2 // Number of Output Waveforms
mbed_official 579:53297373a894 67 #define TCC2_PG 0 // Pattern Generation feature implemented
mbed_official 579:53297373a894 68 #define TCC2_SIZE 16
mbed_official 579:53297373a894 69 #define TCC2_SWAP 0 // DTI outputs swap feature implemented
mbed_official 579:53297373a894 70 #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
mbed_official 579:53297373a894 71
mbed_official 579:53297373a894 72 #endif /* _SAMD21_TCC2_INSTANCE_ */