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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_TC5_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_TC5_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for TC5 peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
mbed_official 579:53297373a894 7 #define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
mbed_official 579:53297373a894 8 #define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
mbed_official 579:53297373a894 9 #define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
mbed_official 579:53297373a894 10 #define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
mbed_official 579:53297373a894 11 #define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
mbed_official 579:53297373a894 12 #define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
mbed_official 579:53297373a894 13 #define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
mbed_official 579:53297373a894 14 #define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
mbed_official 579:53297373a894 15 #define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 16 #define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
mbed_official 579:53297373a894 17 #define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
mbed_official 579:53297373a894 18 #define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
mbed_official 579:53297373a894 19 #define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
mbed_official 579:53297373a894 20 #define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
mbed_official 579:53297373a894 21 #define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
mbed_official 579:53297373a894 22 #define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
mbed_official 579:53297373a894 23 #define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
mbed_official 579:53297373a894 24 #define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
mbed_official 579:53297373a894 25 #define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
mbed_official 579:53297373a894 26 #define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
mbed_official 579:53297373a894 27 #else
mbed_official 579:53297373a894 28 #define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
mbed_official 579:53297373a894 29 #define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
mbed_official 579:53297373a894 30 #define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
mbed_official 579:53297373a894 31 #define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
mbed_official 579:53297373a894 32 #define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
mbed_official 579:53297373a894 33 #define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
mbed_official 579:53297373a894 34 #define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
mbed_official 579:53297373a894 35 #define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
mbed_official 579:53297373a894 36 #define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
mbed_official 579:53297373a894 37 #define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 38 #define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
mbed_official 579:53297373a894 39 #define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
mbed_official 579:53297373a894 40 #define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
mbed_official 579:53297373a894 41 #define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
mbed_official 579:53297373a894 42 #define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
mbed_official 579:53297373a894 43 #define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
mbed_official 579:53297373a894 44 #define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
mbed_official 579:53297373a894 45 #define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
mbed_official 579:53297373a894 46 #define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
mbed_official 579:53297373a894 47 #define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
mbed_official 579:53297373a894 48 #define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
mbed_official 579:53297373a894 49 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 50
mbed_official 579:53297373a894 51 /* ========== Instance parameters for TC5 peripheral ========== */
mbed_official 579:53297373a894 52 #define TC5_CC8_NUM 2 // Number of 8-bit Counters
mbed_official 579:53297373a894 53 #define TC5_CC16_NUM 2 // Number of 16-bit Counters
mbed_official 579:53297373a894 54 #define TC5_CC32_NUM 2 // Number of 32-bit Counters
mbed_official 579:53297373a894 55 #define TC5_DITHERING_EXT 0 // Dithering feature implemented
mbed_official 579:53297373a894 56 #define TC5_DMAC_ID_MC_0 31
mbed_official 579:53297373a894 57 #define TC5_DMAC_ID_MC_1 32
mbed_official 579:53297373a894 58 #define TC5_DMAC_ID_MC_LSB 31
mbed_official 579:53297373a894 59 #define TC5_DMAC_ID_MC_MSB 32
mbed_official 579:53297373a894 60 #define TC5_DMAC_ID_MC_SIZE 2
mbed_official 579:53297373a894 61 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
mbed_official 579:53297373a894 62 #define TC5_GCLK_ID 28 // Index of Generic Clock
mbed_official 579:53297373a894 63 #define TC5_MASTER 0
mbed_official 579:53297373a894 64 #define TC5_OW_NUM 2 // Number of Output Waveforms
mbed_official 579:53297373a894 65 #define TC5_PERIOD_EXT 0 // Period feature implemented
mbed_official 579:53297373a894 66 #define TC5_SHADOW_EXT 0 // Shadow feature implemented
mbed_official 579:53297373a894 67
mbed_official 579:53297373a894 68 #endif /* _SAMD21_TC5_INSTANCE_ */