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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_SERCOM0_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_SERCOM0_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for SERCOM0 peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 11 | #define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 12 | #define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */ |
| mbed_official | 579:53297373a894 | 15 | #define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */ |
| mbed_official | 579:53297373a894 | 16 | #define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ |
| mbed_official | 579:53297373a894 | 17 | #define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ |
| mbed_official | 579:53297373a894 | 18 | #define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ |
| mbed_official | 579:53297373a894 | 19 | #define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 20 | #define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 21 | #define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 22 | #define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ |
| mbed_official | 579:53297373a894 | 23 | #define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ |
| mbed_official | 579:53297373a894 | 24 | #define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */ |
| mbed_official | 579:53297373a894 | 25 | #define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */ |
| mbed_official | 579:53297373a894 | 26 | #define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */ |
| mbed_official | 579:53297373a894 | 27 | #define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */ |
| mbed_official | 579:53297373a894 | 28 | #define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ |
| mbed_official | 579:53297373a894 | 29 | #define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 30 | #define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 31 | #define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 32 | #define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */ |
| mbed_official | 579:53297373a894 | 33 | #define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ |
| mbed_official | 579:53297373a894 | 34 | #define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */ |
| mbed_official | 579:53297373a894 | 35 | #define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */ |
| mbed_official | 579:53297373a894 | 36 | #define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ |
| mbed_official | 579:53297373a894 | 37 | #define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */ |
| mbed_official | 579:53297373a894 | 38 | #define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */ |
| mbed_official | 579:53297373a894 | 39 | #define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ |
| mbed_official | 579:53297373a894 | 40 | #define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ |
| mbed_official | 579:53297373a894 | 41 | #define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 42 | #define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 43 | #define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 44 | #define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */ |
| mbed_official | 579:53297373a894 | 45 | #define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ |
| mbed_official | 579:53297373a894 | 46 | #define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */ |
| mbed_official | 579:53297373a894 | 47 | #define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ |
| mbed_official | 579:53297373a894 | 48 | #else |
| mbed_official | 579:53297373a894 | 49 | #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ |
| mbed_official | 579:53297373a894 | 50 | #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ |
| mbed_official | 579:53297373a894 | 51 | #define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ |
| mbed_official | 579:53297373a894 | 52 | #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 53 | #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 54 | #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 55 | #define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ |
| mbed_official | 579:53297373a894 | 56 | #define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ |
| mbed_official | 579:53297373a894 | 57 | #define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */ |
| mbed_official | 579:53297373a894 | 58 | #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */ |
| mbed_official | 579:53297373a894 | 59 | #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ |
| mbed_official | 579:53297373a894 | 60 | #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ |
| mbed_official | 579:53297373a894 | 61 | #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ |
| mbed_official | 579:53297373a894 | 62 | #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 63 | #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 64 | #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 65 | #define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ |
| mbed_official | 579:53297373a894 | 66 | #define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ |
| mbed_official | 579:53297373a894 | 67 | #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */ |
| mbed_official | 579:53297373a894 | 68 | #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */ |
| mbed_official | 579:53297373a894 | 69 | #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */ |
| mbed_official | 579:53297373a894 | 70 | #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */ |
| mbed_official | 579:53297373a894 | 71 | #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ |
| mbed_official | 579:53297373a894 | 72 | #define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 73 | #define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 74 | #define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 75 | #define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */ |
| mbed_official | 579:53297373a894 | 76 | #define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ |
| mbed_official | 579:53297373a894 | 77 | #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */ |
| mbed_official | 579:53297373a894 | 78 | #define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */ |
| mbed_official | 579:53297373a894 | 79 | #define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ |
| mbed_official | 579:53297373a894 | 80 | #define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */ |
| mbed_official | 579:53297373a894 | 81 | #define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */ |
| mbed_official | 579:53297373a894 | 82 | #define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ |
| mbed_official | 579:53297373a894 | 83 | #define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ |
| mbed_official | 579:53297373a894 | 84 | #define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 85 | #define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 86 | #define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 87 | #define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */ |
| mbed_official | 579:53297373a894 | 88 | #define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ |
| mbed_official | 579:53297373a894 | 89 | #define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */ |
| mbed_official | 579:53297373a894 | 90 | #define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ |
| mbed_official | 579:53297373a894 | 91 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 92 | |
| mbed_official | 579:53297373a894 | 93 | /* ========== Instance parameters for SERCOM0 peripheral ========== */ |
| mbed_official | 579:53297373a894 | 94 | #define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger |
| mbed_official | 579:53297373a894 | 95 | #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger |
| mbed_official | 579:53297373a894 | 96 | #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core |
| mbed_official | 579:53297373a894 | 97 | #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout |
| mbed_official | 579:53297373a894 | 98 | #define SERCOM0_INT_MSB 6 |
| mbed_official | 579:53297373a894 | 99 | |
| mbed_official | 579:53297373a894 | 100 | #endif /* _SAMD21_SERCOM0_INSTANCE_ */ |
