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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_NVMCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_NVMCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for NVMCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 11 | #define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 12 | #define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ |
| mbed_official | 579:53297373a894 | 15 | #else |
| mbed_official | 579:53297373a894 | 16 | #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ |
| mbed_official | 579:53297373a894 | 17 | #define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ |
| mbed_official | 579:53297373a894 | 18 | #define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ |
| mbed_official | 579:53297373a894 | 19 | #define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 20 | #define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 21 | #define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 22 | #define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ |
| mbed_official | 579:53297373a894 | 23 | #define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ |
| mbed_official | 579:53297373a894 | 24 | #define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ |
| mbed_official | 579:53297373a894 | 25 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 26 | |
| mbed_official | 579:53297373a894 | 27 | /* ========== Instance parameters for NVMCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 28 | #define NVMCTRL_AUX0_ADDRESS 0x00804000 |
| mbed_official | 579:53297373a894 | 29 | #define NVMCTRL_AUX1_ADDRESS 0x00806000 |
| mbed_official | 579:53297373a894 | 30 | #define NVMCTRL_AUX2_ADDRESS 0x00808000 |
| mbed_official | 579:53297373a894 | 31 | #define NVMCTRL_AUX3_ADDRESS 0x0080A000 |
| mbed_official | 579:53297373a894 | 32 | #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register |
| mbed_official | 579:53297373a894 | 33 | #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF |
| mbed_official | 579:53297373a894 | 34 | #define NVMCTRL_FLASH_SIZE 262144 |
| mbed_official | 579:53297373a894 | 35 | #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 |
| mbed_official | 579:53297373a894 | 36 | #define NVMCTRL_PAGES 4096 |
| mbed_official | 579:53297373a894 | 37 | #define NVMCTRL_PAGE_HW 32 |
| mbed_official | 579:53297373a894 | 38 | #define NVMCTRL_PAGE_SIZE 64 |
| mbed_official | 579:53297373a894 | 39 | #define NVMCTRL_PAGE_W 16 |
| mbed_official | 579:53297373a894 | 40 | #define NVMCTRL_PMSB 3 |
| mbed_official | 579:53297373a894 | 41 | #define NVMCTRL_PSZ_BITS 6 |
| mbed_official | 579:53297373a894 | 42 | #define NVMCTRL_ROW_PAGES 4 |
| mbed_official | 579:53297373a894 | 43 | #define NVMCTRL_ROW_SIZE 256 |
| mbed_official | 579:53297373a894 | 44 | #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 |
| mbed_official | 579:53297373a894 | 45 | #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 |
| mbed_official | 579:53297373a894 | 46 | #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 |
| mbed_official | 579:53297373a894 | 47 | #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF |
| mbed_official | 579:53297373a894 | 48 | |
| mbed_official | 579:53297373a894 | 49 | #endif /* _SAMD21_NVMCTRL_INSTANCE_ */ |
