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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_GCLK_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_GCLK_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for GCLK peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ |
| mbed_official | 579:53297373a894 | 11 | #else |
| mbed_official | 579:53297373a894 | 12 | #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ |
| mbed_official | 579:53297373a894 | 15 | #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ |
| mbed_official | 579:53297373a894 | 16 | #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ |
| mbed_official | 579:53297373a894 | 17 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 18 | |
| mbed_official | 579:53297373a894 | 19 | /* ========== Instance parameters for GCLK peripheral ========== */ |
| mbed_official | 579:53297373a894 | 20 | #define GCLK_GENDIV_BITS 16 |
| mbed_official | 579:53297373a894 | 21 | #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators |
| mbed_official | 579:53297373a894 | 22 | #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 |
| mbed_official | 579:53297373a894 | 23 | #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 |
| mbed_official | 579:53297373a894 | 24 | #define GCLK_NUM 37 // Number of Generic Clock Users |
| mbed_official | 579:53297373a894 | 25 | #define GCLK_SOURCE_DFLL48M 7 |
| mbed_official | 579:53297373a894 | 26 | #define GCLK_SOURCE_FDPLL 8 |
| mbed_official | 579:53297373a894 | 27 | #define GCLK_SOURCE_GCLKGEN1 2 |
| mbed_official | 579:53297373a894 | 28 | #define GCLK_SOURCE_GCLKIN 1 |
| mbed_official | 579:53297373a894 | 29 | #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources |
| mbed_official | 579:53297373a894 | 30 | #define GCLK_SOURCE_OSCULP32K 3 |
| mbed_official | 579:53297373a894 | 31 | #define GCLK_SOURCE_OSC8M 6 |
| mbed_official | 579:53297373a894 | 32 | #define GCLK_SOURCE_OSC32K 4 |
| mbed_official | 579:53297373a894 | 33 | #define GCLK_SOURCE_XOSC 0 |
| mbed_official | 579:53297373a894 | 34 | #define GCLK_SOURCE_XOSC32K 5 |
| mbed_official | 579:53297373a894 | 35 | |
| mbed_official | 579:53297373a894 | 36 | #endif /* _SAMD21_GCLK_INSTANCE_ */ |
