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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_DSU_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_DSU_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for DSU peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
mbed_official 579:53297373a894 7 #define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
mbed_official 579:53297373a894 8 #define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
mbed_official 579:53297373a894 9 #define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
mbed_official 579:53297373a894 10 #define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
mbed_official 579:53297373a894 11 #define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
mbed_official 579:53297373a894 12 #define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
mbed_official 579:53297373a894 13 #define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
mbed_official 579:53297373a894 14 #define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
mbed_official 579:53297373a894 15 #define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
mbed_official 579:53297373a894 16 #define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
mbed_official 579:53297373a894 17 #define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
mbed_official 579:53297373a894 18 #define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
mbed_official 579:53297373a894 19 #define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
mbed_official 579:53297373a894 20 #define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
mbed_official 579:53297373a894 21 #define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
mbed_official 579:53297373a894 22 #define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
mbed_official 579:53297373a894 23 #define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
mbed_official 579:53297373a894 24 #define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
mbed_official 579:53297373a894 25 #define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
mbed_official 579:53297373a894 26 #define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
mbed_official 579:53297373a894 27 #define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
mbed_official 579:53297373a894 28 #else
mbed_official 579:53297373a894 29 #define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
mbed_official 579:53297373a894 30 #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
mbed_official 579:53297373a894 31 #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
mbed_official 579:53297373a894 32 #define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
mbed_official 579:53297373a894 33 #define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
mbed_official 579:53297373a894 34 #define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
mbed_official 579:53297373a894 35 #define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
mbed_official 579:53297373a894 36 #define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
mbed_official 579:53297373a894 37 #define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
mbed_official 579:53297373a894 38 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
mbed_official 579:53297373a894 39 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
mbed_official 579:53297373a894 40 #define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
mbed_official 579:53297373a894 41 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
mbed_official 579:53297373a894 42 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
mbed_official 579:53297373a894 43 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
mbed_official 579:53297373a894 44 #define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
mbed_official 579:53297373a894 45 #define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
mbed_official 579:53297373a894 46 #define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
mbed_official 579:53297373a894 47 #define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
mbed_official 579:53297373a894 48 #define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
mbed_official 579:53297373a894 49 #define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
mbed_official 579:53297373a894 50 #define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
mbed_official 579:53297373a894 51 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 52
mbed_official 579:53297373a894 53 /* ========== Instance parameters for DSU peripheral ========== */
mbed_official 579:53297373a894 54 #define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #endif /* _SAMD21_DSU_INSTANCE_ */