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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_DMAC_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_DMAC_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for DMAC peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
mbed_official 579:53297373a894 7 #define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
mbed_official 579:53297373a894 8 #define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
mbed_official 579:53297373a894 9 #define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
mbed_official 579:53297373a894 10 #define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
mbed_official 579:53297373a894 11 #define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
mbed_official 579:53297373a894 12 #define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */
mbed_official 579:53297373a894 13 #define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
mbed_official 579:53297373a894 14 #define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
mbed_official 579:53297373a894 15 #define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
mbed_official 579:53297373a894 16 #define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
mbed_official 579:53297373a894 17 #define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
mbed_official 579:53297373a894 18 #define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
mbed_official 579:53297373a894 19 #define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
mbed_official 579:53297373a894 20 #define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
mbed_official 579:53297373a894 21 #define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
mbed_official 579:53297373a894 22 #define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
mbed_official 579:53297373a894 23 #define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
mbed_official 579:53297373a894 24 #define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
mbed_official 579:53297373a894 25 #define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
mbed_official 579:53297373a894 26 #define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
mbed_official 579:53297373a894 27 #define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 28 #define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
mbed_official 579:53297373a894 29 #else
mbed_official 579:53297373a894 30 #define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
mbed_official 579:53297373a894 31 #define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
mbed_official 579:53297373a894 32 #define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
mbed_official 579:53297373a894 33 #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
mbed_official 579:53297373a894 34 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
mbed_official 579:53297373a894 35 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
mbed_official 579:53297373a894 36 #define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
mbed_official 579:53297373a894 37 #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
mbed_official 579:53297373a894 38 #define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
mbed_official 579:53297373a894 39 #define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
mbed_official 579:53297373a894 40 #define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
mbed_official 579:53297373a894 41 #define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
mbed_official 579:53297373a894 42 #define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
mbed_official 579:53297373a894 43 #define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
mbed_official 579:53297373a894 44 #define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
mbed_official 579:53297373a894 45 #define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
mbed_official 579:53297373a894 46 #define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
mbed_official 579:53297373a894 47 #define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
mbed_official 579:53297373a894 48 #define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
mbed_official 579:53297373a894 49 #define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
mbed_official 579:53297373a894 50 #define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
mbed_official 579:53297373a894 51 #define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 52 #define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
mbed_official 579:53297373a894 53 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 54
mbed_official 579:53297373a894 55 /* ========== Instance parameters for DMAC peripheral ========== */
mbed_official 579:53297373a894 56 #define DMAC_CH_BITS 4 // Number of bits to select channel
mbed_official 579:53297373a894 57 #define DMAC_CH_NUM 12 // Number of channels
mbed_official 579:53297373a894 58 #define DMAC_CLK_AHB_ID 5 // AHB clock index
mbed_official 579:53297373a894 59 #define DMAC_EVIN_NUM 4 // Number of input events
mbed_official 579:53297373a894 60 #define DMAC_EVOUT_NUM 4 // Number of output events
mbed_official 579:53297373a894 61 #define DMAC_LVL_BITS 2 // Number of bit to select level priority
mbed_official 579:53297373a894 62 #define DMAC_LVL_NUM 4 // Enable priority level number
mbed_official 579:53297373a894 63 #define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
mbed_official 579:53297373a894 64 #define DMAC_TRIG_NUM 45 // Number of peripheral triggers
mbed_official 579:53297373a894 65
mbed_official 579:53297373a894 66 #endif /* _SAMD21_DMAC_INSTANCE_ */