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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_WDT_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_WDT_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR WDT */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_WDT Watchdog Timer */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define WDT_U2203
mbed_official 579:53297373a894 11 #define REV_WDT 0x200
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint8_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 18 uint8_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 579:53297373a894 19 uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
mbed_official 579:53297373a894 20 uint8_t :4; /*!< bit: 3.. 6 Reserved */
mbed_official 579:53297373a894 21 uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
mbed_official 579:53297373a894 22 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 23 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 24 } WDT_CTRL_Type;
mbed_official 579:53297373a894 25 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 26
mbed_official 579:53297373a894 27 #define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
mbed_official 579:53297373a894 28 #define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */
mbed_official 579:53297373a894 29
mbed_official 579:53297373a894 30 #define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
mbed_official 579:53297373a894 31 #define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos)
mbed_official 579:53297373a894 32 #define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
mbed_official 579:53297373a894 33 #define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos)
mbed_official 579:53297373a894 34 #define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
mbed_official 579:53297373a894 35 #define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos)
mbed_official 579:53297373a894 36 #define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */
mbed_official 579:53297373a894 37
mbed_official 579:53297373a894 38 /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
mbed_official 579:53297373a894 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 40 typedef union {
mbed_official 579:53297373a894 41 struct {
mbed_official 579:53297373a894 42 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
mbed_official 579:53297373a894 43 uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
mbed_official 579:53297373a894 44 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 45 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 46 } WDT_CONFIG_Type;
mbed_official 579:53297373a894 47 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 48
mbed_official 579:53297373a894 49 #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
mbed_official 579:53297373a894 50 #define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */
mbed_official 579:53297373a894 51
mbed_official 579:53297373a894 52 #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
mbed_official 579:53297373a894 53 #define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 54 #define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
mbed_official 579:53297373a894 55 #define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
mbed_official 579:53297373a894 56 #define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
mbed_official 579:53297373a894 57 #define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
mbed_official 579:53297373a894 58 #define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
mbed_official 579:53297373a894 59 #define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
mbed_official 579:53297373a894 60 #define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
mbed_official 579:53297373a894 61 #define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
mbed_official 579:53297373a894 62 #define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
mbed_official 579:53297373a894 63 #define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
mbed_official 579:53297373a894 64 #define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
mbed_official 579:53297373a894 65 #define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
mbed_official 579:53297373a894 66 #define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
mbed_official 579:53297373a894 67 #define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 68 #define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 69 #define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 70 #define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 71 #define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 72 #define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 73 #define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 74 #define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 75 #define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 76 #define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 77 #define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 78 #define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
mbed_official 579:53297373a894 79 #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
mbed_official 579:53297373a894 80 #define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 81 #define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
mbed_official 579:53297373a894 82 #define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
mbed_official 579:53297373a894 83 #define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
mbed_official 579:53297373a894 84 #define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
mbed_official 579:53297373a894 85 #define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
mbed_official 579:53297373a894 86 #define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
mbed_official 579:53297373a894 87 #define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
mbed_official 579:53297373a894 88 #define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
mbed_official 579:53297373a894 89 #define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
mbed_official 579:53297373a894 90 #define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
mbed_official 579:53297373a894 91 #define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
mbed_official 579:53297373a894 92 #define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
mbed_official 579:53297373a894 93 #define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
mbed_official 579:53297373a894 94 #define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 95 #define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 96 #define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 97 #define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 98 #define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 99 #define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 100 #define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 101 #define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 102 #define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 103 #define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 104 #define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 105 #define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
mbed_official 579:53297373a894 106 #define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */
mbed_official 579:53297373a894 107
mbed_official 579:53297373a894 108 /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
mbed_official 579:53297373a894 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 110 typedef union {
mbed_official 579:53297373a894 111 struct {
mbed_official 579:53297373a894 112 uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
mbed_official 579:53297373a894 113 uint8_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 579:53297373a894 114 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 115 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 116 } WDT_EWCTRL_Type;
mbed_official 579:53297373a894 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 118
mbed_official 579:53297373a894 119 #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
mbed_official 579:53297373a894 120 #define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
mbed_official 579:53297373a894 121
mbed_official 579:53297373a894 122 #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
mbed_official 579:53297373a894 123 #define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 124 #define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
mbed_official 579:53297373a894 125 #define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
mbed_official 579:53297373a894 126 #define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
mbed_official 579:53297373a894 127 #define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
mbed_official 579:53297373a894 128 #define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */
mbed_official 579:53297373a894 129 #define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */
mbed_official 579:53297373a894 130 #define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */
mbed_official 579:53297373a894 131 #define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */
mbed_official 579:53297373a894 132 #define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */
mbed_official 579:53297373a894 133 #define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */
mbed_official 579:53297373a894 134 #define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */
mbed_official 579:53297373a894 135 #define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */
mbed_official 579:53297373a894 136 #define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */
mbed_official 579:53297373a894 137 #define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 138 #define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 139 #define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 140 #define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 141 #define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 142 #define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 143 #define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 144 #define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 145 #define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 146 #define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 147 #define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 148 #define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
mbed_official 579:53297373a894 149 #define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */
mbed_official 579:53297373a894 150
mbed_official 579:53297373a894 151 /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 153 typedef union {
mbed_official 579:53297373a894 154 struct {
mbed_official 579:53297373a894 155 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
mbed_official 579:53297373a894 156 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 579:53297373a894 157 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 158 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 159 } WDT_INTENCLR_Type;
mbed_official 579:53297373a894 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 161
mbed_official 579:53297373a894 162 #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 163 #define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 164
mbed_official 579:53297373a894 165 #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
mbed_official 579:53297373a894 166 #define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos)
mbed_official 579:53297373a894 167 #define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */
mbed_official 579:53297373a894 168
mbed_official 579:53297373a894 169 /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 171 typedef union {
mbed_official 579:53297373a894 172 struct {
mbed_official 579:53297373a894 173 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
mbed_official 579:53297373a894 174 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 579:53297373a894 175 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 176 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 177 } WDT_INTENSET_Type;
mbed_official 579:53297373a894 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 179
mbed_official 579:53297373a894 180 #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 181 #define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 182
mbed_official 579:53297373a894 183 #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
mbed_official 579:53297373a894 184 #define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos)
mbed_official 579:53297373a894 185 #define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */
mbed_official 579:53297373a894 186
mbed_official 579:53297373a894 187 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 188 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 189 typedef union {
mbed_official 579:53297373a894 190 struct {
mbed_official 579:53297373a894 191 uint8_t EW:1; /*!< bit: 0 Early Warning */
mbed_official 579:53297373a894 192 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 579:53297373a894 193 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 194 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 195 } WDT_INTFLAG_Type;
mbed_official 579:53297373a894 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 197
mbed_official 579:53297373a894 198 #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 199 #define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 200
mbed_official 579:53297373a894 201 #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
mbed_official 579:53297373a894 202 #define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos)
mbed_official 579:53297373a894 203 #define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */
mbed_official 579:53297373a894 204
mbed_official 579:53297373a894 205 /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
mbed_official 579:53297373a894 206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 207 typedef union {
mbed_official 579:53297373a894 208 struct {
mbed_official 579:53297373a894 209 uint8_t :7; /*!< bit: 0.. 6 Reserved */
mbed_official 579:53297373a894 210 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
mbed_official 579:53297373a894 211 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 212 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 213 } WDT_STATUS_Type;
mbed_official 579:53297373a894 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 215
mbed_official 579:53297373a894 216 #define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
mbed_official 579:53297373a894 217 #define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */
mbed_official 579:53297373a894 218
mbed_official 579:53297373a894 219 #define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
mbed_official 579:53297373a894 220 #define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
mbed_official 579:53297373a894 221 #define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */
mbed_official 579:53297373a894 222
mbed_official 579:53297373a894 223 /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
mbed_official 579:53297373a894 224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 225 typedef union {
mbed_official 579:53297373a894 226 struct {
mbed_official 579:53297373a894 227 uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
mbed_official 579:53297373a894 228 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 229 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 230 } WDT_CLEAR_Type;
mbed_official 579:53297373a894 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 232
mbed_official 579:53297373a894 233 #define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
mbed_official 579:53297373a894 234 #define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */
mbed_official 579:53297373a894 235
mbed_official 579:53297373a894 236 #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
mbed_official 579:53297373a894 237 #define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
mbed_official 579:53297373a894 238 #define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
mbed_official 579:53297373a894 239 #define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
mbed_official 579:53297373a894 240 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
mbed_official 579:53297373a894 241 #define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
mbed_official 579:53297373a894 242
mbed_official 579:53297373a894 243 /** \brief WDT hardware registers */
mbed_official 579:53297373a894 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 245 typedef struct {
mbed_official 579:53297373a894 246 __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
mbed_official 579:53297373a894 247 __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
mbed_official 579:53297373a894 248 __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
mbed_official 579:53297373a894 249 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 250 __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 251 __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 252 __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 253 __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
mbed_official 579:53297373a894 254 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
mbed_official 579:53297373a894 255 } Wdt;
mbed_official 579:53297373a894 256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 257
mbed_official 579:53297373a894 258 /*@}*/
mbed_official 579:53297373a894 259
mbed_official 579:53297373a894 260 #endif /* _SAMD21_WDT_COMPONENT_ */