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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_TC_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_TC_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR TC */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_TC Basic Timer Counter */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define TC_U2212
mbed_official 579:53297373a894 11 #define REV_TC 0x121
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 579:53297373a894 18 uint16_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 579:53297373a894 19 uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
mbed_official 579:53297373a894 20 uint16_t :1; /*!< bit: 4 Reserved */
mbed_official 579:53297373a894 21 uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
mbed_official 579:53297373a894 22 uint16_t :1; /*!< bit: 7 Reserved */
mbed_official 579:53297373a894 23 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
mbed_official 579:53297373a894 24 uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
mbed_official 579:53297373a894 25 uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
mbed_official 579:53297373a894 26 uint16_t :2; /*!< bit: 14..15 Reserved */
mbed_official 579:53297373a894 27 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 28 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 29 } TC_CTRLA_Type;
mbed_official 579:53297373a894 30 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 31
mbed_official 579:53297373a894 32 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
mbed_official 579:53297373a894 33 #define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */
mbed_official 579:53297373a894 34
mbed_official 579:53297373a894 35 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
mbed_official 579:53297373a894 36 #define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos)
mbed_official 579:53297373a894 37 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
mbed_official 579:53297373a894 38 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
mbed_official 579:53297373a894 39 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
mbed_official 579:53297373a894 40 #define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
mbed_official 579:53297373a894 41 #define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
mbed_official 579:53297373a894 42 #define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
mbed_official 579:53297373a894 43 #define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
mbed_official 579:53297373a894 44 #define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
mbed_official 579:53297373a894 45 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
mbed_official 579:53297373a894 46 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
mbed_official 579:53297373a894 47 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
mbed_official 579:53297373a894 48 #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
mbed_official 579:53297373a894 49 #define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
mbed_official 579:53297373a894 50 #define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
mbed_official 579:53297373a894 51 #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
mbed_official 579:53297373a894 52 #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
mbed_official 579:53297373a894 53 #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
mbed_official 579:53297373a894 54 #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */
mbed_official 579:53297373a894 55 #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
mbed_official 579:53297373a894 56 #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
mbed_official 579:53297373a894 57 #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
mbed_official 579:53297373a894 58 #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
mbed_official 579:53297373a894 59 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
mbed_official 579:53297373a894 60 #define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 61 #define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
mbed_official 579:53297373a894 62 #define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
mbed_official 579:53297373a894 63 #define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
mbed_official 579:53297373a894 64 #define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
mbed_official 579:53297373a894 65 #define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
mbed_official 579:53297373a894 66 #define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
mbed_official 579:53297373a894 67 #define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
mbed_official 579:53297373a894 68 #define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
mbed_official 579:53297373a894 69 #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
mbed_official 579:53297373a894 70 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 71 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 72 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 73 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 74 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 75 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 76 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 77 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
mbed_official 579:53297373a894 78 #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
mbed_official 579:53297373a894 79 #define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
mbed_official 579:53297373a894 80 #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
mbed_official 579:53297373a894 81 #define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 82 #define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
mbed_official 579:53297373a894 83 #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
mbed_official 579:53297373a894 84 #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
mbed_official 579:53297373a894 85 #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
mbed_official 579:53297373a894 86 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 87 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 88 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
mbed_official 579:53297373a894 89 #define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */
mbed_official 579:53297373a894 90
mbed_official 579:53297373a894 91 /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
mbed_official 579:53297373a894 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 93 typedef union {
mbed_official 579:53297373a894 94 struct {
mbed_official 579:53297373a894 95 uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
mbed_official 579:53297373a894 96 uint16_t :9; /*!< bit: 5..13 Reserved */
mbed_official 579:53297373a894 97 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
mbed_official 579:53297373a894 98 uint16_t RREQ:1; /*!< bit: 15 Read Request */
mbed_official 579:53297373a894 99 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 100 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 101 } TC_READREQ_Type;
mbed_official 579:53297373a894 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 103
mbed_official 579:53297373a894 104 #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
mbed_official 579:53297373a894 105 #define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */
mbed_official 579:53297373a894 106
mbed_official 579:53297373a894 107 #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
mbed_official 579:53297373a894 108 #define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
mbed_official 579:53297373a894 109 #define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
mbed_official 579:53297373a894 110 #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
mbed_official 579:53297373a894 111 #define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
mbed_official 579:53297373a894 112 #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
mbed_official 579:53297373a894 113 #define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos)
mbed_official 579:53297373a894 114 #define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */
mbed_official 579:53297373a894 115
mbed_official 579:53297373a894 116 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
mbed_official 579:53297373a894 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 118 typedef union {
mbed_official 579:53297373a894 119 struct {
mbed_official 579:53297373a894 120 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
mbed_official 579:53297373a894 121 uint8_t :1; /*!< bit: 1 Reserved */
mbed_official 579:53297373a894 122 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
mbed_official 579:53297373a894 123 uint8_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 579:53297373a894 124 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
mbed_official 579:53297373a894 125 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 126 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 127 } TC_CTRLBCLR_Type;
mbed_official 579:53297373a894 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 129
mbed_official 579:53297373a894 130 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
mbed_official 579:53297373a894 131 #define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
mbed_official 579:53297373a894 132
mbed_official 579:53297373a894 133 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
mbed_official 579:53297373a894 134 #define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos)
mbed_official 579:53297373a894 135 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
mbed_official 579:53297373a894 136 #define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
mbed_official 579:53297373a894 137 #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
mbed_official 579:53297373a894 138 #define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 139 #define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
mbed_official 579:53297373a894 140 #define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
mbed_official 579:53297373a894 141 #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
mbed_official 579:53297373a894 142 #define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
mbed_official 579:53297373a894 143 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 144 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 145 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
mbed_official 579:53297373a894 146 #define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */
mbed_official 579:53297373a894 147
mbed_official 579:53297373a894 148 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
mbed_official 579:53297373a894 149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 150 typedef union {
mbed_official 579:53297373a894 151 struct {
mbed_official 579:53297373a894 152 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
mbed_official 579:53297373a894 153 uint8_t :1; /*!< bit: 1 Reserved */
mbed_official 579:53297373a894 154 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
mbed_official 579:53297373a894 155 uint8_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 579:53297373a894 156 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
mbed_official 579:53297373a894 157 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 158 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 159 } TC_CTRLBSET_Type;
mbed_official 579:53297373a894 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 161
mbed_official 579:53297373a894 162 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
mbed_official 579:53297373a894 163 #define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */
mbed_official 579:53297373a894 164
mbed_official 579:53297373a894 165 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
mbed_official 579:53297373a894 166 #define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos)
mbed_official 579:53297373a894 167 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
mbed_official 579:53297373a894 168 #define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
mbed_official 579:53297373a894 169 #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
mbed_official 579:53297373a894 170 #define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 171 #define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
mbed_official 579:53297373a894 172 #define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
mbed_official 579:53297373a894 173 #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
mbed_official 579:53297373a894 174 #define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
mbed_official 579:53297373a894 175 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 176 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 177 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
mbed_official 579:53297373a894 178 #define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */
mbed_official 579:53297373a894 179
mbed_official 579:53297373a894 180 /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
mbed_official 579:53297373a894 181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 182 typedef union {
mbed_official 579:53297373a894 183 struct {
mbed_official 579:53297373a894 184 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
mbed_official 579:53297373a894 185 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
mbed_official 579:53297373a894 186 uint8_t :2; /*!< bit: 2.. 3 Reserved */
mbed_official 579:53297373a894 187 uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
mbed_official 579:53297373a894 188 uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
mbed_official 579:53297373a894 189 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 190 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 191 struct {
mbed_official 579:53297373a894 192 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
mbed_official 579:53297373a894 193 uint8_t :2; /*!< bit: 2.. 3 Reserved */
mbed_official 579:53297373a894 194 uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
mbed_official 579:53297373a894 195 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 196 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 197 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 198 } TC_CTRLC_Type;
mbed_official 579:53297373a894 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 200
mbed_official 579:53297373a894 201 #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
mbed_official 579:53297373a894 202 #define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */
mbed_official 579:53297373a894 203
mbed_official 579:53297373a894 204 #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
mbed_official 579:53297373a894 205 #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
mbed_official 579:53297373a894 206 #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
mbed_official 579:53297373a894 207 #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
mbed_official 579:53297373a894 208 #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
mbed_official 579:53297373a894 209 #define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
mbed_official 579:53297373a894 210 #define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
mbed_official 579:53297373a894 211 #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
mbed_official 579:53297373a894 212 #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
mbed_official 579:53297373a894 213 #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
mbed_official 579:53297373a894 214 #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
mbed_official 579:53297373a894 215 #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
mbed_official 579:53297373a894 216 #define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
mbed_official 579:53297373a894 217 #define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
mbed_official 579:53297373a894 218 #define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
mbed_official 579:53297373a894 219
mbed_official 579:53297373a894 220 /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
mbed_official 579:53297373a894 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 222 typedef union {
mbed_official 579:53297373a894 223 struct {
mbed_official 579:53297373a894 224 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
mbed_official 579:53297373a894 225 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 579:53297373a894 226 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 227 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 228 } TC_DBGCTRL_Type;
mbed_official 579:53297373a894 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 230
mbed_official 579:53297373a894 231 #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
mbed_official 579:53297373a894 232 #define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */
mbed_official 579:53297373a894 233
mbed_official 579:53297373a894 234 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
mbed_official 579:53297373a894 235 #define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
mbed_official 579:53297373a894 236 #define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */
mbed_official 579:53297373a894 237
mbed_official 579:53297373a894 238 /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
mbed_official 579:53297373a894 239 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 240 typedef union {
mbed_official 579:53297373a894 241 struct {
mbed_official 579:53297373a894 242 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
mbed_official 579:53297373a894 243 uint16_t :1; /*!< bit: 3 Reserved */
mbed_official 579:53297373a894 244 uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
mbed_official 579:53297373a894 245 uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
mbed_official 579:53297373a894 246 uint16_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 247 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
mbed_official 579:53297373a894 248 uint16_t :3; /*!< bit: 9..11 Reserved */
mbed_official 579:53297373a894 249 uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
mbed_official 579:53297373a894 250 uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
mbed_official 579:53297373a894 251 uint16_t :2; /*!< bit: 14..15 Reserved */
mbed_official 579:53297373a894 252 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 253 struct {
mbed_official 579:53297373a894 254 uint16_t :12; /*!< bit: 0..11 Reserved */
mbed_official 579:53297373a894 255 uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
mbed_official 579:53297373a894 256 uint16_t :2; /*!< bit: 14..15 Reserved */
mbed_official 579:53297373a894 257 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 258 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 259 } TC_EVCTRL_Type;
mbed_official 579:53297373a894 260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 261
mbed_official 579:53297373a894 262 #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
mbed_official 579:53297373a894 263 #define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */
mbed_official 579:53297373a894 264
mbed_official 579:53297373a894 265 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
mbed_official 579:53297373a894 266 #define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 267 #define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
mbed_official 579:53297373a894 268 #define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
mbed_official 579:53297373a894 269 #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
mbed_official 579:53297373a894 270 #define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
mbed_official 579:53297373a894 271 #define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */
mbed_official 579:53297373a894 272 #define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
mbed_official 579:53297373a894 273 #define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
mbed_official 579:53297373a894 274 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 275 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 276 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 277 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 278 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 279 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
mbed_official 579:53297373a894 280 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
mbed_official 579:53297373a894 281 #define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos)
mbed_official 579:53297373a894 282 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
mbed_official 579:53297373a894 283 #define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos)
mbed_official 579:53297373a894 284 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
mbed_official 579:53297373a894 285 #define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos)
mbed_official 579:53297373a894 286 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
mbed_official 579:53297373a894 287 #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
mbed_official 579:53297373a894 288 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
mbed_official 579:53297373a894 289 #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
mbed_official 579:53297373a894 290 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
mbed_official 579:53297373a894 291 #define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
mbed_official 579:53297373a894 292 #define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
mbed_official 579:53297373a894 293 #define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
mbed_official 579:53297373a894 294
mbed_official 579:53297373a894 295 /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 296 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 297 typedef union {
mbed_official 579:53297373a894 298 struct {
mbed_official 579:53297373a894 299 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
mbed_official 579:53297373a894 300 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
mbed_official 579:53297373a894 301 uint8_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 302 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 303 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 304 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 305 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 306 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 307 struct {
mbed_official 579:53297373a894 308 uint8_t :4; /*!< bit: 0.. 3 Reserved */
mbed_official 579:53297373a894 309 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 310 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 311 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 312 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 313 } TC_INTENCLR_Type;
mbed_official 579:53297373a894 314 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 315
mbed_official 579:53297373a894 316 #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 317 #define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 318
mbed_official 579:53297373a894 319 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
mbed_official 579:53297373a894 320 #define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos)
mbed_official 579:53297373a894 321 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
mbed_official 579:53297373a894 322 #define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos)
mbed_official 579:53297373a894 323 #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 324 #define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
mbed_official 579:53297373a894 325 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 326 #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
mbed_official 579:53297373a894 327 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 328 #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
mbed_official 579:53297373a894 329 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 330 #define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
mbed_official 579:53297373a894 331 #define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
mbed_official 579:53297373a894 332 #define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
mbed_official 579:53297373a894 333
mbed_official 579:53297373a894 334 /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 336 typedef union {
mbed_official 579:53297373a894 337 struct {
mbed_official 579:53297373a894 338 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
mbed_official 579:53297373a894 339 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
mbed_official 579:53297373a894 340 uint8_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 341 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 342 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 343 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 344 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 345 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 346 struct {
mbed_official 579:53297373a894 347 uint8_t :4; /*!< bit: 0.. 3 Reserved */
mbed_official 579:53297373a894 348 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 349 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 350 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 351 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 352 } TC_INTENSET_Type;
mbed_official 579:53297373a894 353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 354
mbed_official 579:53297373a894 355 #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 356 #define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 357
mbed_official 579:53297373a894 358 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
mbed_official 579:53297373a894 359 #define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos)
mbed_official 579:53297373a894 360 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
mbed_official 579:53297373a894 361 #define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos)
mbed_official 579:53297373a894 362 #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 363 #define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos)
mbed_official 579:53297373a894 364 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
mbed_official 579:53297373a894 365 #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
mbed_official 579:53297373a894 366 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
mbed_official 579:53297373a894 367 #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
mbed_official 579:53297373a894 368 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
mbed_official 579:53297373a894 369 #define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
mbed_official 579:53297373a894 370 #define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
mbed_official 579:53297373a894 371 #define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
mbed_official 579:53297373a894 372
mbed_official 579:53297373a894 373 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 374 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 375 typedef union {
mbed_official 579:53297373a894 376 struct {
mbed_official 579:53297373a894 377 uint8_t OVF:1; /*!< bit: 0 Overflow */
mbed_official 579:53297373a894 378 uint8_t ERR:1; /*!< bit: 1 Error */
mbed_official 579:53297373a894 379 uint8_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 380 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
mbed_official 579:53297373a894 381 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
mbed_official 579:53297373a894 382 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
mbed_official 579:53297373a894 383 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 384 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 385 struct {
mbed_official 579:53297373a894 386 uint8_t :4; /*!< bit: 0.. 3 Reserved */
mbed_official 579:53297373a894 387 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
mbed_official 579:53297373a894 388 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 579:53297373a894 389 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 390 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 391 } TC_INTFLAG_Type;
mbed_official 579:53297373a894 392 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 393
mbed_official 579:53297373a894 394 #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 395 #define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 396
mbed_official 579:53297373a894 397 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
mbed_official 579:53297373a894 398 #define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos)
mbed_official 579:53297373a894 399 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
mbed_official 579:53297373a894 400 #define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos)
mbed_official 579:53297373a894 401 #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
mbed_official 579:53297373a894 402 #define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
mbed_official 579:53297373a894 403 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
mbed_official 579:53297373a894 404 #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
mbed_official 579:53297373a894 405 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
mbed_official 579:53297373a894 406 #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
mbed_official 579:53297373a894 407 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
mbed_official 579:53297373a894 408 #define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
mbed_official 579:53297373a894 409 #define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
mbed_official 579:53297373a894 410 #define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
mbed_official 579:53297373a894 411
mbed_official 579:53297373a894 412 /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
mbed_official 579:53297373a894 413 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 414 typedef union {
mbed_official 579:53297373a894 415 struct {
mbed_official 579:53297373a894 416 uint8_t :3; /*!< bit: 0.. 2 Reserved */
mbed_official 579:53297373a894 417 uint8_t STOP:1; /*!< bit: 3 Stop */
mbed_official 579:53297373a894 418 uint8_t SLAVE:1; /*!< bit: 4 Slave */
mbed_official 579:53297373a894 419 uint8_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 579:53297373a894 420 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
mbed_official 579:53297373a894 421 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 422 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 423 } TC_STATUS_Type;
mbed_official 579:53297373a894 424 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 425
mbed_official 579:53297373a894 426 #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
mbed_official 579:53297373a894 427 #define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */
mbed_official 579:53297373a894 428
mbed_official 579:53297373a894 429 #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
mbed_official 579:53297373a894 430 #define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos)
mbed_official 579:53297373a894 431 #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
mbed_official 579:53297373a894 432 #define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos)
mbed_official 579:53297373a894 433 #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
mbed_official 579:53297373a894 434 #define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos)
mbed_official 579:53297373a894 435 #define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */
mbed_official 579:53297373a894 436
mbed_official 579:53297373a894 437 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
mbed_official 579:53297373a894 438 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 439 typedef union {
mbed_official 579:53297373a894 440 struct {
mbed_official 579:53297373a894 441 uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
mbed_official 579:53297373a894 442 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 443 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 444 } TC_COUNT16_COUNT_Type;
mbed_official 579:53297373a894 445 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 446
mbed_official 579:53297373a894 447 #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
mbed_official 579:53297373a894 448 #define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
mbed_official 579:53297373a894 449
mbed_official 579:53297373a894 450 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
mbed_official 579:53297373a894 451 #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
mbed_official 579:53297373a894 452 #define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
mbed_official 579:53297373a894 453 #define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
mbed_official 579:53297373a894 454
mbed_official 579:53297373a894 455 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
mbed_official 579:53297373a894 456 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 457 typedef union {
mbed_official 579:53297373a894 458 struct {
mbed_official 579:53297373a894 459 uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
mbed_official 579:53297373a894 460 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 461 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 462 } TC_COUNT32_COUNT_Type;
mbed_official 579:53297373a894 463 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 464
mbed_official 579:53297373a894 465 #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
mbed_official 579:53297373a894 466 #define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
mbed_official 579:53297373a894 467
mbed_official 579:53297373a894 468 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
mbed_official 579:53297373a894 469 #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
mbed_official 579:53297373a894 470 #define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
mbed_official 579:53297373a894 471 #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
mbed_official 579:53297373a894 472
mbed_official 579:53297373a894 473 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
mbed_official 579:53297373a894 474 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 475 typedef union {
mbed_official 579:53297373a894 476 struct {
mbed_official 579:53297373a894 477 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
mbed_official 579:53297373a894 478 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 479 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 480 } TC_COUNT8_COUNT_Type;
mbed_official 579:53297373a894 481 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 482
mbed_official 579:53297373a894 483 #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
mbed_official 579:53297373a894 484 #define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
mbed_official 579:53297373a894 485
mbed_official 579:53297373a894 486 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
mbed_official 579:53297373a894 487 #define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
mbed_official 579:53297373a894 488 #define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
mbed_official 579:53297373a894 489 #define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
mbed_official 579:53297373a894 490
mbed_official 579:53297373a894 491 /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
mbed_official 579:53297373a894 492 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 493 typedef union {
mbed_official 579:53297373a894 494 struct {
mbed_official 579:53297373a894 495 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
mbed_official 579:53297373a894 496 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 497 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 498 } TC_COUNT8_PER_Type;
mbed_official 579:53297373a894 499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 500
mbed_official 579:53297373a894 501 #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
mbed_official 579:53297373a894 502 #define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
mbed_official 579:53297373a894 503
mbed_official 579:53297373a894 504 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
mbed_official 579:53297373a894 505 #define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
mbed_official 579:53297373a894 506 #define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
mbed_official 579:53297373a894 507 #define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
mbed_official 579:53297373a894 508
mbed_official 579:53297373a894 509 /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
mbed_official 579:53297373a894 510 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 511 typedef union {
mbed_official 579:53297373a894 512 struct {
mbed_official 579:53297373a894 513 uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
mbed_official 579:53297373a894 514 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 515 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 516 } TC_COUNT16_CC_Type;
mbed_official 579:53297373a894 517 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 518
mbed_official 579:53297373a894 519 #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
mbed_official 579:53297373a894 520 #define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
mbed_official 579:53297373a894 521
mbed_official 579:53297373a894 522 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
mbed_official 579:53297373a894 523 #define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
mbed_official 579:53297373a894 524 #define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
mbed_official 579:53297373a894 525 #define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
mbed_official 579:53297373a894 526
mbed_official 579:53297373a894 527 /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
mbed_official 579:53297373a894 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 529 typedef union {
mbed_official 579:53297373a894 530 struct {
mbed_official 579:53297373a894 531 uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
mbed_official 579:53297373a894 532 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 533 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 534 } TC_COUNT32_CC_Type;
mbed_official 579:53297373a894 535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 536
mbed_official 579:53297373a894 537 #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
mbed_official 579:53297373a894 538 #define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
mbed_official 579:53297373a894 539
mbed_official 579:53297373a894 540 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
mbed_official 579:53297373a894 541 #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
mbed_official 579:53297373a894 542 #define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
mbed_official 579:53297373a894 543 #define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
mbed_official 579:53297373a894 544
mbed_official 579:53297373a894 545 /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
mbed_official 579:53297373a894 546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 547 typedef union {
mbed_official 579:53297373a894 548 struct {
mbed_official 579:53297373a894 549 uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
mbed_official 579:53297373a894 550 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 551 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 552 } TC_COUNT8_CC_Type;
mbed_official 579:53297373a894 553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 554
mbed_official 579:53297373a894 555 #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
mbed_official 579:53297373a894 556 #define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
mbed_official 579:53297373a894 557
mbed_official 579:53297373a894 558 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
mbed_official 579:53297373a894 559 #define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
mbed_official 579:53297373a894 560 #define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
mbed_official 579:53297373a894 561 #define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
mbed_official 579:53297373a894 562
mbed_official 579:53297373a894 563 /** \brief TC_COUNT8 hardware registers */
mbed_official 579:53297373a894 564 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 565 typedef struct { /* 8-bit Counter Mode */
mbed_official 579:53297373a894 566 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
mbed_official 579:53297373a894 567 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 579:53297373a894 568 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
mbed_official 579:53297373a894 569 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
mbed_official 579:53297373a894 570 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
mbed_official 579:53297373a894 571 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 572 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
mbed_official 579:53297373a894 573 RoReg8 Reserved2[0x1];
mbed_official 579:53297373a894 574 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
mbed_official 579:53297373a894 575 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 576 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 577 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 578 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
mbed_official 579:53297373a894 579 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
mbed_official 579:53297373a894 580 RoReg8 Reserved3[0x3];
mbed_official 579:53297373a894 581 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
mbed_official 579:53297373a894 582 RoReg8 Reserved4[0x3];
mbed_official 579:53297373a894 583 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
mbed_official 579:53297373a894 584 } TcCount8;
mbed_official 579:53297373a894 585 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 586
mbed_official 579:53297373a894 587 /** \brief TC_COUNT16 hardware registers */
mbed_official 579:53297373a894 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 589 typedef struct { /* 16-bit Counter Mode */
mbed_official 579:53297373a894 590 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
mbed_official 579:53297373a894 591 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 579:53297373a894 592 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
mbed_official 579:53297373a894 593 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
mbed_official 579:53297373a894 594 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
mbed_official 579:53297373a894 595 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 596 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
mbed_official 579:53297373a894 597 RoReg8 Reserved2[0x1];
mbed_official 579:53297373a894 598 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
mbed_official 579:53297373a894 599 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 600 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 601 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 602 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
mbed_official 579:53297373a894 603 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
mbed_official 579:53297373a894 604 RoReg8 Reserved3[0x6];
mbed_official 579:53297373a894 605 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
mbed_official 579:53297373a894 606 } TcCount16;
mbed_official 579:53297373a894 607 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 608
mbed_official 579:53297373a894 609 /** \brief TC_COUNT32 hardware registers */
mbed_official 579:53297373a894 610 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 611 typedef struct { /* 32-bit Counter Mode */
mbed_official 579:53297373a894 612 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
mbed_official 579:53297373a894 613 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 579:53297373a894 614 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
mbed_official 579:53297373a894 615 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
mbed_official 579:53297373a894 616 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
mbed_official 579:53297373a894 617 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 618 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
mbed_official 579:53297373a894 619 RoReg8 Reserved2[0x1];
mbed_official 579:53297373a894 620 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
mbed_official 579:53297373a894 621 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 622 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 623 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 624 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
mbed_official 579:53297373a894 625 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
mbed_official 579:53297373a894 626 RoReg8 Reserved3[0x4];
mbed_official 579:53297373a894 627 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
mbed_official 579:53297373a894 628 } TcCount32;
mbed_official 579:53297373a894 629 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 630
mbed_official 579:53297373a894 631 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 632 typedef union {
mbed_official 579:53297373a894 633 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
mbed_official 579:53297373a894 634 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
mbed_official 579:53297373a894 635 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
mbed_official 579:53297373a894 636 } Tc;
mbed_official 579:53297373a894 637 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 638
mbed_official 579:53297373a894 639 /*@}*/
mbed_official 579:53297373a894 640
mbed_official 579:53297373a894 641 #endif /* _SAMD21_TC_COMPONENT_ */