mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_DAC_COMPONENT_
mbed_official 579:53297373a894 2 #define _SAMD21_DAC_COMPONENT_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========================================================================== */
mbed_official 579:53297373a894 5 /** SOFTWARE API DEFINITION FOR DAC */
mbed_official 579:53297373a894 6 /* ========================================================================== */
mbed_official 579:53297373a894 7 /** \addtogroup SAMD21_DAC Digital Analog Converter */
mbed_official 579:53297373a894 8 /*@{*/
mbed_official 579:53297373a894 9
mbed_official 579:53297373a894 10 #define DAC_U2214
mbed_official 579:53297373a894 11 #define REV_DAC 0x110
mbed_official 579:53297373a894 12
mbed_official 579:53297373a894 13 /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
mbed_official 579:53297373a894 14 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 15 typedef union {
mbed_official 579:53297373a894 16 struct {
mbed_official 579:53297373a894 17 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 579:53297373a894 18 uint8_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 579:53297373a894 19 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
mbed_official 579:53297373a894 20 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 579:53297373a894 21 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 22 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 23 } DAC_CTRLA_Type;
mbed_official 579:53297373a894 24 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 25
mbed_official 579:53297373a894 26 #define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
mbed_official 579:53297373a894 27 #define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */
mbed_official 579:53297373a894 28
mbed_official 579:53297373a894 29 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
mbed_official 579:53297373a894 30 #define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos)
mbed_official 579:53297373a894 31 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
mbed_official 579:53297373a894 32 #define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos)
mbed_official 579:53297373a894 33 #define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
mbed_official 579:53297373a894 34 #define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
mbed_official 579:53297373a894 35 #define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */
mbed_official 579:53297373a894 36
mbed_official 579:53297373a894 37 /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
mbed_official 579:53297373a894 38 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 39 typedef union {
mbed_official 579:53297373a894 40 struct {
mbed_official 579:53297373a894 41 uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
mbed_official 579:53297373a894 42 uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
mbed_official 579:53297373a894 43 uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
mbed_official 579:53297373a894 44 uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
mbed_official 579:53297373a894 45 uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
mbed_official 579:53297373a894 46 uint8_t :1; /*!< bit: 5 Reserved */
mbed_official 579:53297373a894 47 uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
mbed_official 579:53297373a894 48 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 49 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 50 } DAC_CTRLB_Type;
mbed_official 579:53297373a894 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 52
mbed_official 579:53297373a894 53 #define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
mbed_official 579:53297373a894 54 #define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
mbed_official 579:53297373a894 57 #define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos)
mbed_official 579:53297373a894 58 #define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
mbed_official 579:53297373a894 59 #define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos)
mbed_official 579:53297373a894 60 #define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
mbed_official 579:53297373a894 61 #define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
mbed_official 579:53297373a894 62 #define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
mbed_official 579:53297373a894 63 #define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos)
mbed_official 579:53297373a894 64 #define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
mbed_official 579:53297373a894 65 #define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
mbed_official 579:53297373a894 66 #define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
mbed_official 579:53297373a894 67 #define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
mbed_official 579:53297373a894 68 #define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
mbed_official 579:53297373a894 69 #define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
mbed_official 579:53297373a894 70 #define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
mbed_official 579:53297373a894 71 #define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
mbed_official 579:53297373a894 72 #define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
mbed_official 579:53297373a894 73 #define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
mbed_official 579:53297373a894 74 #define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
mbed_official 579:53297373a894 75 #define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */
mbed_official 579:53297373a894 76
mbed_official 579:53297373a894 77 /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
mbed_official 579:53297373a894 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 79 typedef union {
mbed_official 579:53297373a894 80 struct {
mbed_official 579:53297373a894 81 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
mbed_official 579:53297373a894 82 uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
mbed_official 579:53297373a894 83 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 579:53297373a894 84 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 85 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 86 } DAC_EVCTRL_Type;
mbed_official 579:53297373a894 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 88
mbed_official 579:53297373a894 89 #define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
mbed_official 579:53297373a894 90 #define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */
mbed_official 579:53297373a894 91
mbed_official 579:53297373a894 92 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
mbed_official 579:53297373a894 93 #define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos)
mbed_official 579:53297373a894 94 #define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
mbed_official 579:53297373a894 95 #define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
mbed_official 579:53297373a894 96 #define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */
mbed_official 579:53297373a894 97
mbed_official 579:53297373a894 98 /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 99 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 100 typedef union {
mbed_official 579:53297373a894 101 struct {
mbed_official 579:53297373a894 102 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
mbed_official 579:53297373a894 103 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
mbed_official 579:53297373a894 104 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 105 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 579:53297373a894 106 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 107 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 108 } DAC_INTENCLR_Type;
mbed_official 579:53297373a894 109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 110
mbed_official 579:53297373a894 111 #define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 112 #define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 113
mbed_official 579:53297373a894 114 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
mbed_official 579:53297373a894 115 #define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
mbed_official 579:53297373a894 116 #define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
mbed_official 579:53297373a894 117 #define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos)
mbed_official 579:53297373a894 118 #define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 119 #define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
mbed_official 579:53297373a894 120 #define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */
mbed_official 579:53297373a894 121
mbed_official 579:53297373a894 122 /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 124 typedef union {
mbed_official 579:53297373a894 125 struct {
mbed_official 579:53297373a894 126 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
mbed_official 579:53297373a894 127 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
mbed_official 579:53297373a894 128 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 129 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 579:53297373a894 130 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 131 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 132 } DAC_INTENSET_Type;
mbed_official 579:53297373a894 133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 134
mbed_official 579:53297373a894 135 #define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 136 #define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 137
mbed_official 579:53297373a894 138 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
mbed_official 579:53297373a894 139 #define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
mbed_official 579:53297373a894 140 #define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
mbed_official 579:53297373a894 141 #define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos)
mbed_official 579:53297373a894 142 #define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
mbed_official 579:53297373a894 143 #define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
mbed_official 579:53297373a894 144 #define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */
mbed_official 579:53297373a894 145
mbed_official 579:53297373a894 146 /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 148 typedef union {
mbed_official 579:53297373a894 149 struct {
mbed_official 579:53297373a894 150 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
mbed_official 579:53297373a894 151 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
mbed_official 579:53297373a894 152 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
mbed_official 579:53297373a894 153 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 579:53297373a894 154 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 155 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 156 } DAC_INTFLAG_Type;
mbed_official 579:53297373a894 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 158
mbed_official 579:53297373a894 159 #define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 160 #define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 161
mbed_official 579:53297373a894 162 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
mbed_official 579:53297373a894 163 #define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
mbed_official 579:53297373a894 164 #define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
mbed_official 579:53297373a894 165 #define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos)
mbed_official 579:53297373a894 166 #define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
mbed_official 579:53297373a894 167 #define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
mbed_official 579:53297373a894 168 #define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */
mbed_official 579:53297373a894 169
mbed_official 579:53297373a894 170 /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
mbed_official 579:53297373a894 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 172 typedef union {
mbed_official 579:53297373a894 173 struct {
mbed_official 579:53297373a894 174 uint8_t :7; /*!< bit: 0.. 6 Reserved */
mbed_official 579:53297373a894 175 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
mbed_official 579:53297373a894 176 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 177 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 178 } DAC_STATUS_Type;
mbed_official 579:53297373a894 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 180
mbed_official 579:53297373a894 181 #define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
mbed_official 579:53297373a894 182 #define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */
mbed_official 579:53297373a894 183
mbed_official 579:53297373a894 184 #define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
mbed_official 579:53297373a894 185 #define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
mbed_official 579:53297373a894 186 #define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */
mbed_official 579:53297373a894 187
mbed_official 579:53297373a894 188 /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
mbed_official 579:53297373a894 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 190 typedef union {
mbed_official 579:53297373a894 191 struct {
mbed_official 579:53297373a894 192 uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
mbed_official 579:53297373a894 193 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 194 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 195 } DAC_DATA_Type;
mbed_official 579:53297373a894 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 197
mbed_official 579:53297373a894 198 #define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
mbed_official 579:53297373a894 199 #define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */
mbed_official 579:53297373a894 200
mbed_official 579:53297373a894 201 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
mbed_official 579:53297373a894 202 #define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
mbed_official 579:53297373a894 203 #define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
mbed_official 579:53297373a894 204 #define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
mbed_official 579:53297373a894 205
mbed_official 579:53297373a894 206 /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
mbed_official 579:53297373a894 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 208 typedef union {
mbed_official 579:53297373a894 209 struct {
mbed_official 579:53297373a894 210 uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
mbed_official 579:53297373a894 211 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 212 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 213 } DAC_DATABUF_Type;
mbed_official 579:53297373a894 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 215
mbed_official 579:53297373a894 216 #define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
mbed_official 579:53297373a894 217 #define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */
mbed_official 579:53297373a894 218
mbed_official 579:53297373a894 219 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
mbed_official 579:53297373a894 220 #define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
mbed_official 579:53297373a894 221 #define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
mbed_official 579:53297373a894 222 #define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
mbed_official 579:53297373a894 223
mbed_official 579:53297373a894 224 /** \brief DAC hardware registers */
mbed_official 579:53297373a894 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 226 typedef struct {
mbed_official 579:53297373a894 227 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
mbed_official 579:53297373a894 228 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
mbed_official 579:53297373a894 229 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
mbed_official 579:53297373a894 230 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 231 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 232 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 233 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 234 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
mbed_official 579:53297373a894 235 __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
mbed_official 579:53297373a894 236 RoReg8 Reserved2[0x2];
mbed_official 579:53297373a894 237 __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
mbed_official 579:53297373a894 238 } Dac;
mbed_official 579:53297373a894 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 240
mbed_official 579:53297373a894 241 /*@}*/
mbed_official 579:53297373a894 242
mbed_official 579:53297373a894 243 #endif /* _SAMD21_DAC_COMPONENT_ */