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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h@624:83778a75d1b4, 2015-09-25 (annotated)

Committer:
mbed_official
Date:
Fri Sep 25 11:45:09 2015 +0100
Revision:
624:83778a75d1b4
Synchronized with git revision b290644b9cdd33d24fc3f629368795b3d9c386fe



Full URL: https://github.com/mbedmicro/mbed/commit/b290644b9cdd33d24fc3f629368795b3d9c386fe/



changes for adding IoT Subsystem for Cortex-M target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 624:83778a75d1b4 1 /**************************************************************************//**
mbed_official 624:83778a75d1b4 2 * @file CMSDK_BEID.h
mbed_official 624:83778a75d1b4 3 * @brief CMSIS Core Peripheral Access Layer Header File for
mbed_official 624:83778a75d1b4 4 * CMSDK_BEID Device
mbed_official 624:83778a75d1b4 5 * @version V3.02
mbed_official 624:83778a75d1b4 6 * @date 15. November 2013
mbed_official 624:83778a75d1b4 7 *
mbed_official 624:83778a75d1b4 8 * @note
mbed_official 624:83778a75d1b4 9 *
mbed_official 624:83778a75d1b4 10 ******************************************************************************/
mbed_official 624:83778a75d1b4 11 /* Copyright (c) 2011 - 2013 ARM LIMITED
mbed_official 624:83778a75d1b4 12
mbed_official 624:83778a75d1b4 13 All rights reserved.
mbed_official 624:83778a75d1b4 14 Redistribution and use in source and binary forms, with or without
mbed_official 624:83778a75d1b4 15 modification, are permitted provided that the following conditions are met:
mbed_official 624:83778a75d1b4 16 - Redistributions of source code must retain the above copyright
mbed_official 624:83778a75d1b4 17 notice, this list of conditions and the following disclaimer.
mbed_official 624:83778a75d1b4 18 - Redistributions in binary form must reproduce the above copyright
mbed_official 624:83778a75d1b4 19 notice, this list of conditions and the following disclaimer in the
mbed_official 624:83778a75d1b4 20 documentation and/or other materials provided with the distribution.
mbed_official 624:83778a75d1b4 21 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 624:83778a75d1b4 22 to endorse or promote products derived from this software without
mbed_official 624:83778a75d1b4 23 specific prior written permission.
mbed_official 624:83778a75d1b4 24 *
mbed_official 624:83778a75d1b4 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 624:83778a75d1b4 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 624:83778a75d1b4 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 624:83778a75d1b4 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 624:83778a75d1b4 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 624:83778a75d1b4 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 624:83778a75d1b4 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 624:83778a75d1b4 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 624:83778a75d1b4 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 624:83778a75d1b4 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 624:83778a75d1b4 35 POSSIBILITY OF SUCH DAMAGE.
mbed_official 624:83778a75d1b4 36 ---------------------------------------------------------------------------*/
mbed_official 624:83778a75d1b4 37
mbed_official 624:83778a75d1b4 38
mbed_official 624:83778a75d1b4 39 #ifndef CMSDK_BEID_H
mbed_official 624:83778a75d1b4 40 #define CMSDK_BEID_H
mbed_official 624:83778a75d1b4 41
mbed_official 624:83778a75d1b4 42 #ifdef __cplusplus
mbed_official 624:83778a75d1b4 43 extern "C" {
mbed_official 624:83778a75d1b4 44 #endif
mbed_official 624:83778a75d1b4 45
mbed_official 624:83778a75d1b4 46
mbed_official 624:83778a75d1b4 47 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 624:83778a75d1b4 48
mbed_official 624:83778a75d1b4 49 typedef enum IRQn
mbed_official 624:83778a75d1b4 50 {
mbed_official 624:83778a75d1b4 51 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
mbed_official 624:83778a75d1b4 52 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
mbed_official 624:83778a75d1b4 53 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
mbed_official 624:83778a75d1b4 54 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
mbed_official 624:83778a75d1b4 55 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
mbed_official 624:83778a75d1b4 56 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
mbed_official 624:83778a75d1b4 57 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
mbed_official 624:83778a75d1b4 58 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
mbed_official 624:83778a75d1b4 59 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
mbed_official 624:83778a75d1b4 60 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
mbed_official 624:83778a75d1b4 61
mbed_official 624:83778a75d1b4 62 /* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */
mbed_official 624:83778a75d1b4 63 UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
mbed_official 624:83778a75d1b4 64 UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
mbed_official 624:83778a75d1b4 65 UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
mbed_official 624:83778a75d1b4 66 UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
mbed_official 624:83778a75d1b4 67 UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
mbed_official 624:83778a75d1b4 68 UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
mbed_official 624:83778a75d1b4 69 UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */
mbed_official 624:83778a75d1b4 70 UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */
mbed_official 624:83778a75d1b4 71 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
mbed_official 624:83778a75d1b4 72 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
mbed_official 624:83778a75d1b4 73 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
mbed_official 624:83778a75d1b4 74 SPI_IRQn = 11, /* SPI Interrupt */
mbed_official 624:83778a75d1b4 75 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
mbed_official 624:83778a75d1b4 76 ETHERNET_IRQn = 13, /* Ethernet Interrupt */
mbed_official 624:83778a75d1b4 77 I2S_IRQn = 14, /* I2S Interrupt */
mbed_official 624:83778a75d1b4 78 TSC_IRQn = 15, /* Touch Screen Interrupt */
mbed_official 624:83778a75d1b4 79 // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
mbed_official 624:83778a75d1b4 80 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
mbed_official 624:83778a75d1b4 81 PORT0_1_IRQn = 17, /* There are 16 pins in total */
mbed_official 624:83778a75d1b4 82 PORT0_2_IRQn = 18,
mbed_official 624:83778a75d1b4 83 PORT0_3_IRQn = 19,
mbed_official 624:83778a75d1b4 84 PORT0_4_IRQn = 20,
mbed_official 624:83778a75d1b4 85 PORT0_5_IRQn = 21,
mbed_official 624:83778a75d1b4 86 PORT0_6_IRQn = 22,
mbed_official 624:83778a75d1b4 87 PORT0_7_IRQn = 23,
mbed_official 624:83778a75d1b4 88 PORT0_8_IRQn = 24,
mbed_official 624:83778a75d1b4 89 PORT0_9_IRQn = 25,
mbed_official 624:83778a75d1b4 90 PORT0_10_IRQn = 26,
mbed_official 624:83778a75d1b4 91 PORT0_11_IRQn = 27,
mbed_official 624:83778a75d1b4 92 PORT0_12_IRQn = 28,
mbed_official 624:83778a75d1b4 93 PORT0_13_IRQn = 29,
mbed_official 624:83778a75d1b4 94 PORT0_14_IRQn = 30,
mbed_official 624:83778a75d1b4 95 PORT0_15_IRQn = 31,
mbed_official 624:83778a75d1b4 96 } IRQn_Type;
mbed_official 624:83778a75d1b4 97
mbed_official 624:83778a75d1b4 98
mbed_official 624:83778a75d1b4 99 /* ================================================================================ */
mbed_official 624:83778a75d1b4 100 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 624:83778a75d1b4 101 /* ================================================================================ */
mbed_official 624:83778a75d1b4 102
mbed_official 624:83778a75d1b4 103 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
mbed_official 624:83778a75d1b4 104 #define __CM3_REV 0x0201 /* Core revision r2p1 */
mbed_official 624:83778a75d1b4 105 #define __MPU_PRESENT 1 /* MPU present or not */
mbed_official 624:83778a75d1b4 106 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
mbed_official 624:83778a75d1b4 107 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official 624:83778a75d1b4 108
mbed_official 624:83778a75d1b4 109 #include <core_cm3.h> /* Processor and core peripherals */
mbed_official 624:83778a75d1b4 110 #include "system_CMSDK_BEID.h" /* System Header */
mbed_official 624:83778a75d1b4 111
mbed_official 624:83778a75d1b4 112
mbed_official 624:83778a75d1b4 113 /* ================================================================================ */
mbed_official 624:83778a75d1b4 114 /* ================ Device Specific Peripheral Section ================ */
mbed_official 624:83778a75d1b4 115 /* ================================================================================ */
mbed_official 624:83778a75d1b4 116
mbed_official 624:83778a75d1b4 117 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 624:83778a75d1b4 118 #if defined ( __CC_ARM )
mbed_official 624:83778a75d1b4 119 #pragma push
mbed_official 624:83778a75d1b4 120 #pragma anon_unions
mbed_official 624:83778a75d1b4 121 #elif defined(__ICCARM__)
mbed_official 624:83778a75d1b4 122 #pragma language=extended
mbed_official 624:83778a75d1b4 123 #elif defined(__GNUC__)
mbed_official 624:83778a75d1b4 124 /* anonymous unions are enabled by default */
mbed_official 624:83778a75d1b4 125 #elif defined(__TMS470__)
mbed_official 624:83778a75d1b4 126 /* anonymous unions are enabled by default */
mbed_official 624:83778a75d1b4 127 #elif defined(__TASKING__)
mbed_official 624:83778a75d1b4 128 #pragma warning 586
mbed_official 624:83778a75d1b4 129 #else
mbed_official 624:83778a75d1b4 130 #warning Not supported compiler type
mbed_official 624:83778a75d1b4 131 #endif
mbed_official 624:83778a75d1b4 132
mbed_official 624:83778a75d1b4 133 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
mbed_official 624:83778a75d1b4 134 typedef struct
mbed_official 624:83778a75d1b4 135 {
mbed_official 624:83778a75d1b4 136 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
mbed_official 624:83778a75d1b4 137 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
mbed_official 624:83778a75d1b4 138 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
mbed_official 624:83778a75d1b4 139 union {
mbed_official 624:83778a75d1b4 140 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 624:83778a75d1b4 141 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 624:83778a75d1b4 142 };
mbed_official 624:83778a75d1b4 143 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
mbed_official 624:83778a75d1b4 144
mbed_official 624:83778a75d1b4 145 } CMSDK_UART_TypeDef;
mbed_official 624:83778a75d1b4 146
mbed_official 624:83778a75d1b4 147 /* CMSDK_UART DATA Register Definitions */
mbed_official 624:83778a75d1b4 148
mbed_official 624:83778a75d1b4 149 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
mbed_official 624:83778a75d1b4 150 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
mbed_official 624:83778a75d1b4 151
mbed_official 624:83778a75d1b4 152 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
mbed_official 624:83778a75d1b4 153 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
mbed_official 624:83778a75d1b4 154
mbed_official 624:83778a75d1b4 155 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
mbed_official 624:83778a75d1b4 156 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
mbed_official 624:83778a75d1b4 157
mbed_official 624:83778a75d1b4 158 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
mbed_official 624:83778a75d1b4 159 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
mbed_official 624:83778a75d1b4 160
mbed_official 624:83778a75d1b4 161 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
mbed_official 624:83778a75d1b4 162 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
mbed_official 624:83778a75d1b4 163
mbed_official 624:83778a75d1b4 164 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
mbed_official 624:83778a75d1b4 165 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
mbed_official 624:83778a75d1b4 166
mbed_official 624:83778a75d1b4 167 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
mbed_official 624:83778a75d1b4 168 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
mbed_official 624:83778a75d1b4 169
mbed_official 624:83778a75d1b4 170 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
mbed_official 624:83778a75d1b4 171 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
mbed_official 624:83778a75d1b4 172
mbed_official 624:83778a75d1b4 173 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
mbed_official 624:83778a75d1b4 174 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
mbed_official 624:83778a75d1b4 175
mbed_official 624:83778a75d1b4 176 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
mbed_official 624:83778a75d1b4 177 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
mbed_official 624:83778a75d1b4 178
mbed_official 624:83778a75d1b4 179 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
mbed_official 624:83778a75d1b4 180 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
mbed_official 624:83778a75d1b4 181
mbed_official 624:83778a75d1b4 182 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
mbed_official 624:83778a75d1b4 183 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
mbed_official 624:83778a75d1b4 184
mbed_official 624:83778a75d1b4 185 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
mbed_official 624:83778a75d1b4 186 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
mbed_official 624:83778a75d1b4 187
mbed_official 624:83778a75d1b4 188 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
mbed_official 624:83778a75d1b4 189 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
mbed_official 624:83778a75d1b4 190
mbed_official 624:83778a75d1b4 191 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
mbed_official 624:83778a75d1b4 192 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
mbed_official 624:83778a75d1b4 193
mbed_official 624:83778a75d1b4 194 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
mbed_official 624:83778a75d1b4 195 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
mbed_official 624:83778a75d1b4 196
mbed_official 624:83778a75d1b4 197 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
mbed_official 624:83778a75d1b4 198 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
mbed_official 624:83778a75d1b4 199
mbed_official 624:83778a75d1b4 200
mbed_official 624:83778a75d1b4 201 /*----------------------------- Timer (TIMER) -------------------------------*/
mbed_official 624:83778a75d1b4 202 typedef struct
mbed_official 624:83778a75d1b4 203 {
mbed_official 624:83778a75d1b4 204 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
mbed_official 624:83778a75d1b4 205 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
mbed_official 624:83778a75d1b4 206 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
mbed_official 624:83778a75d1b4 207 union {
mbed_official 624:83778a75d1b4 208 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 624:83778a75d1b4 209 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 624:83778a75d1b4 210 };
mbed_official 624:83778a75d1b4 211
mbed_official 624:83778a75d1b4 212 } CMSDK_TIMER_TypeDef;
mbed_official 624:83778a75d1b4 213
mbed_official 624:83778a75d1b4 214 /* CMSDK_TIMER CTRL Register Definitions */
mbed_official 624:83778a75d1b4 215
mbed_official 624:83778a75d1b4 216 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
mbed_official 624:83778a75d1b4 217 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
mbed_official 624:83778a75d1b4 218
mbed_official 624:83778a75d1b4 219 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
mbed_official 624:83778a75d1b4 220 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
mbed_official 624:83778a75d1b4 221
mbed_official 624:83778a75d1b4 222 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
mbed_official 624:83778a75d1b4 223 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
mbed_official 624:83778a75d1b4 224
mbed_official 624:83778a75d1b4 225 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
mbed_official 624:83778a75d1b4 226 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
mbed_official 624:83778a75d1b4 227
mbed_official 624:83778a75d1b4 228 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
mbed_official 624:83778a75d1b4 229 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
mbed_official 624:83778a75d1b4 230
mbed_official 624:83778a75d1b4 231 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
mbed_official 624:83778a75d1b4 232 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
mbed_official 624:83778a75d1b4 233
mbed_official 624:83778a75d1b4 234 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
mbed_official 624:83778a75d1b4 235 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
mbed_official 624:83778a75d1b4 236
mbed_official 624:83778a75d1b4 237 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
mbed_official 624:83778a75d1b4 238 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
mbed_official 624:83778a75d1b4 239
mbed_official 624:83778a75d1b4 240
mbed_official 624:83778a75d1b4 241 /*------------- Timer (TIM) --------------------------------------------------*/
mbed_official 624:83778a75d1b4 242 typedef struct
mbed_official 624:83778a75d1b4 243 {
mbed_official 624:83778a75d1b4 244 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
mbed_official 624:83778a75d1b4 245 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
mbed_official 624:83778a75d1b4 246 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
mbed_official 624:83778a75d1b4 247 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
mbed_official 624:83778a75d1b4 248 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
mbed_official 624:83778a75d1b4 249 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
mbed_official 624:83778a75d1b4 250 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
mbed_official 624:83778a75d1b4 251 uint32_t RESERVED0;
mbed_official 624:83778a75d1b4 252 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
mbed_official 624:83778a75d1b4 253 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
mbed_official 624:83778a75d1b4 254 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
mbed_official 624:83778a75d1b4 255 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
mbed_official 624:83778a75d1b4 256 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
mbed_official 624:83778a75d1b4 257 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
mbed_official 624:83778a75d1b4 258 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
mbed_official 624:83778a75d1b4 259 uint32_t RESERVED1[945];
mbed_official 624:83778a75d1b4 260 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
mbed_official 624:83778a75d1b4 261 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
mbed_official 624:83778a75d1b4 262 } CMSDK_DUALTIMER_BOTH_TypeDef;
mbed_official 624:83778a75d1b4 263
mbed_official 624:83778a75d1b4 264 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
mbed_official 624:83778a75d1b4 265 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
mbed_official 624:83778a75d1b4 266
mbed_official 624:83778a75d1b4 267 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
mbed_official 624:83778a75d1b4 268 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
mbed_official 624:83778a75d1b4 269
mbed_official 624:83778a75d1b4 270 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
mbed_official 624:83778a75d1b4 271 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
mbed_official 624:83778a75d1b4 272
mbed_official 624:83778a75d1b4 273 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
mbed_official 624:83778a75d1b4 274 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
mbed_official 624:83778a75d1b4 275
mbed_official 624:83778a75d1b4 276 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 624:83778a75d1b4 277 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 624:83778a75d1b4 278
mbed_official 624:83778a75d1b4 279 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 624:83778a75d1b4 280 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 624:83778a75d1b4 281
mbed_official 624:83778a75d1b4 282 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
mbed_official 624:83778a75d1b4 283 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 624:83778a75d1b4 284
mbed_official 624:83778a75d1b4 285 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 624:83778a75d1b4 286 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 624:83778a75d1b4 287
mbed_official 624:83778a75d1b4 288 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
mbed_official 624:83778a75d1b4 289 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
mbed_official 624:83778a75d1b4 290
mbed_official 624:83778a75d1b4 291 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
mbed_official 624:83778a75d1b4 292 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
mbed_official 624:83778a75d1b4 293
mbed_official 624:83778a75d1b4 294 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
mbed_official 624:83778a75d1b4 295 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
mbed_official 624:83778a75d1b4 296
mbed_official 624:83778a75d1b4 297 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
mbed_official 624:83778a75d1b4 298 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
mbed_official 624:83778a75d1b4 299
mbed_official 624:83778a75d1b4 300 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
mbed_official 624:83778a75d1b4 301 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
mbed_official 624:83778a75d1b4 302
mbed_official 624:83778a75d1b4 303 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
mbed_official 624:83778a75d1b4 304 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
mbed_official 624:83778a75d1b4 305
mbed_official 624:83778a75d1b4 306 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
mbed_official 624:83778a75d1b4 307 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
mbed_official 624:83778a75d1b4 308
mbed_official 624:83778a75d1b4 309 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
mbed_official 624:83778a75d1b4 310 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
mbed_official 624:83778a75d1b4 311
mbed_official 624:83778a75d1b4 312 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 624:83778a75d1b4 313 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 624:83778a75d1b4 314
mbed_official 624:83778a75d1b4 315 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 624:83778a75d1b4 316 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 624:83778a75d1b4 317
mbed_official 624:83778a75d1b4 318 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
mbed_official 624:83778a75d1b4 319 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 624:83778a75d1b4 320
mbed_official 624:83778a75d1b4 321 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 624:83778a75d1b4 322 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 624:83778a75d1b4 323
mbed_official 624:83778a75d1b4 324 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
mbed_official 624:83778a75d1b4 325 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
mbed_official 624:83778a75d1b4 326
mbed_official 624:83778a75d1b4 327 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
mbed_official 624:83778a75d1b4 328 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
mbed_official 624:83778a75d1b4 329
mbed_official 624:83778a75d1b4 330 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
mbed_official 624:83778a75d1b4 331 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
mbed_official 624:83778a75d1b4 332
mbed_official 624:83778a75d1b4 333 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
mbed_official 624:83778a75d1b4 334 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
mbed_official 624:83778a75d1b4 335
mbed_official 624:83778a75d1b4 336
mbed_official 624:83778a75d1b4 337 typedef struct
mbed_official 624:83778a75d1b4 338 {
mbed_official 624:83778a75d1b4 339 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
mbed_official 624:83778a75d1b4 340 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
mbed_official 624:83778a75d1b4 341 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
mbed_official 624:83778a75d1b4 342 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
mbed_official 624:83778a75d1b4 343 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
mbed_official 624:83778a75d1b4 344 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
mbed_official 624:83778a75d1b4 345 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
mbed_official 624:83778a75d1b4 346 } CMSDK_DUALTIMER_SINGLE_TypeDef;
mbed_official 624:83778a75d1b4 347
mbed_official 624:83778a75d1b4 348 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
mbed_official 624:83778a75d1b4 349 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
mbed_official 624:83778a75d1b4 350
mbed_official 624:83778a75d1b4 351 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
mbed_official 624:83778a75d1b4 352 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
mbed_official 624:83778a75d1b4 353
mbed_official 624:83778a75d1b4 354 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
mbed_official 624:83778a75d1b4 355 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
mbed_official 624:83778a75d1b4 356
mbed_official 624:83778a75d1b4 357 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
mbed_official 624:83778a75d1b4 358 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
mbed_official 624:83778a75d1b4 359
mbed_official 624:83778a75d1b4 360 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
mbed_official 624:83778a75d1b4 361 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 624:83778a75d1b4 362
mbed_official 624:83778a75d1b4 363 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 624:83778a75d1b4 364 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 624:83778a75d1b4 365
mbed_official 624:83778a75d1b4 366 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
mbed_official 624:83778a75d1b4 367 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
mbed_official 624:83778a75d1b4 368
mbed_official 624:83778a75d1b4 369 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 624:83778a75d1b4 370 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 624:83778a75d1b4 371
mbed_official 624:83778a75d1b4 372 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
mbed_official 624:83778a75d1b4 373 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
mbed_official 624:83778a75d1b4 374
mbed_official 624:83778a75d1b4 375 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
mbed_official 624:83778a75d1b4 376 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
mbed_official 624:83778a75d1b4 377
mbed_official 624:83778a75d1b4 378 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
mbed_official 624:83778a75d1b4 379 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
mbed_official 624:83778a75d1b4 380
mbed_official 624:83778a75d1b4 381 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
mbed_official 624:83778a75d1b4 382 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
mbed_official 624:83778a75d1b4 383
mbed_official 624:83778a75d1b4 384
mbed_official 624:83778a75d1b4 385 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
mbed_official 624:83778a75d1b4 386 typedef struct
mbed_official 624:83778a75d1b4 387 {
mbed_official 624:83778a75d1b4 388 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
mbed_official 624:83778a75d1b4 389 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
mbed_official 624:83778a75d1b4 390 uint32_t RESERVED0[2];
mbed_official 624:83778a75d1b4 391 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
mbed_official 624:83778a75d1b4 392 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
mbed_official 624:83778a75d1b4 393 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
mbed_official 624:83778a75d1b4 394 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
mbed_official 624:83778a75d1b4 395 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
mbed_official 624:83778a75d1b4 396 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
mbed_official 624:83778a75d1b4 397 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
mbed_official 624:83778a75d1b4 398 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
mbed_official 624:83778a75d1b4 399 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
mbed_official 624:83778a75d1b4 400 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
mbed_official 624:83778a75d1b4 401 union {
mbed_official 624:83778a75d1b4 402 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
mbed_official 624:83778a75d1b4 403 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
mbed_official 624:83778a75d1b4 404 };
mbed_official 624:83778a75d1b4 405 uint32_t RESERVED1[241];
mbed_official 624:83778a75d1b4 406 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
mbed_official 624:83778a75d1b4 407 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
mbed_official 624:83778a75d1b4 408 } CMSDK_GPIO_TypeDef;
mbed_official 624:83778a75d1b4 409
mbed_official 624:83778a75d1b4 410 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
mbed_official 624:83778a75d1b4 411 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
mbed_official 624:83778a75d1b4 412
mbed_official 624:83778a75d1b4 413 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
mbed_official 624:83778a75d1b4 414 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
mbed_official 624:83778a75d1b4 415
mbed_official 624:83778a75d1b4 416 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 624:83778a75d1b4 417 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 624:83778a75d1b4 418
mbed_official 624:83778a75d1b4 419 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 624:83778a75d1b4 420 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 624:83778a75d1b4 421
mbed_official 624:83778a75d1b4 422 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 624:83778a75d1b4 423 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 624:83778a75d1b4 424
mbed_official 624:83778a75d1b4 425 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 624:83778a75d1b4 426 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 624:83778a75d1b4 427
mbed_official 624:83778a75d1b4 428 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 624:83778a75d1b4 429 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 624:83778a75d1b4 430
mbed_official 624:83778a75d1b4 431 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 624:83778a75d1b4 432 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 624:83778a75d1b4 433
mbed_official 624:83778a75d1b4 434 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 624:83778a75d1b4 435 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 624:83778a75d1b4 436
mbed_official 624:83778a75d1b4 437 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 624:83778a75d1b4 438 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 624:83778a75d1b4 439
mbed_official 624:83778a75d1b4 440 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 624:83778a75d1b4 441 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 624:83778a75d1b4 442
mbed_official 624:83778a75d1b4 443 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 624:83778a75d1b4 444 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 624:83778a75d1b4 445
mbed_official 624:83778a75d1b4 446 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
mbed_official 624:83778a75d1b4 447 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
mbed_official 624:83778a75d1b4 448
mbed_official 624:83778a75d1b4 449 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
mbed_official 624:83778a75d1b4 450 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
mbed_official 624:83778a75d1b4 451
mbed_official 624:83778a75d1b4 452 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
mbed_official 624:83778a75d1b4 453 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
mbed_official 624:83778a75d1b4 454
mbed_official 624:83778a75d1b4 455 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
mbed_official 624:83778a75d1b4 456 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
mbed_official 624:83778a75d1b4 457
mbed_official 624:83778a75d1b4 458
mbed_official 624:83778a75d1b4 459 /*------------- System Control (SYSCON) --------------------------------------*/
mbed_official 624:83778a75d1b4 460 typedef struct
mbed_official 624:83778a75d1b4 461 {
mbed_official 624:83778a75d1b4 462 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
mbed_official 624:83778a75d1b4 463 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
mbed_official 624:83778a75d1b4 464 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
mbed_official 624:83778a75d1b4 465 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
mbed_official 624:83778a75d1b4 466 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
mbed_official 624:83778a75d1b4 467 uint32_t RESERVED0[3];
mbed_official 624:83778a75d1b4 468 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
mbed_official 624:83778a75d1b4 469 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
mbed_official 624:83778a75d1b4 470 uint32_t RESERVED1[2];
mbed_official 624:83778a75d1b4 471 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
mbed_official 624:83778a75d1b4 472 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
mbed_official 624:83778a75d1b4 473 uint32_t RESERVED2[2];
mbed_official 624:83778a75d1b4 474 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
mbed_official 624:83778a75d1b4 475 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
mbed_official 624:83778a75d1b4 476 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
mbed_official 624:83778a75d1b4 477 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
mbed_official 624:83778a75d1b4 478 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
mbed_official 624:83778a75d1b4 479 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
mbed_official 624:83778a75d1b4 480 uint32_t RESERVED3[10];
mbed_official 624:83778a75d1b4 481 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
mbed_official 624:83778a75d1b4 482 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
mbed_official 624:83778a75d1b4 483 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
mbed_official 624:83778a75d1b4 484 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
mbed_official 624:83778a75d1b4 485 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
mbed_official 624:83778a75d1b4 486 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
mbed_official 624:83778a75d1b4 487 uint32_t RESERVED4[2];
mbed_official 624:83778a75d1b4 488 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
mbed_official 624:83778a75d1b4 489 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
mbed_official 624:83778a75d1b4 490 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
mbed_official 624:83778a75d1b4 491 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
mbed_official 624:83778a75d1b4 492 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
mbed_official 624:83778a75d1b4 493 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
mbed_official 624:83778a75d1b4 494 uint32_t RESERVED5[2];
mbed_official 624:83778a75d1b4 495 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
mbed_official 624:83778a75d1b4 496 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
mbed_official 624:83778a75d1b4 497 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
mbed_official 624:83778a75d1b4 498 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
mbed_official 624:83778a75d1b4 499 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
mbed_official 624:83778a75d1b4 500 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
mbed_official 624:83778a75d1b4 501 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
mbed_official 624:83778a75d1b4 502 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
mbed_official 624:83778a75d1b4 503 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
mbed_official 624:83778a75d1b4 504 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
mbed_official 624:83778a75d1b4 505 uint32_t RESERVED6[2];
mbed_official 624:83778a75d1b4 506 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
mbed_official 624:83778a75d1b4 507 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
mbed_official 624:83778a75d1b4 508 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
mbed_official 624:83778a75d1b4 509 uint32_t RESERVED7[1];
mbed_official 624:83778a75d1b4 510 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
mbed_official 624:83778a75d1b4 511 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
mbed_official 624:83778a75d1b4 512 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
mbed_official 624:83778a75d1b4 513 } CMSDK_SYSCON_TypeDef;
mbed_official 624:83778a75d1b4 514
mbed_official 624:83778a75d1b4 515 #define CMSDK_SYSCON_REMAP_Pos 0
mbed_official 624:83778a75d1b4 516 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
mbed_official 624:83778a75d1b4 517
mbed_official 624:83778a75d1b4 518 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
mbed_official 624:83778a75d1b4 519 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
mbed_official 624:83778a75d1b4 520
mbed_official 624:83778a75d1b4 521 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
mbed_official 624:83778a75d1b4 522 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
mbed_official 624:83778a75d1b4 523
mbed_official 624:83778a75d1b4 524 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
mbed_official 624:83778a75d1b4 525 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
mbed_official 624:83778a75d1b4 526
mbed_official 624:83778a75d1b4 527 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
mbed_official 624:83778a75d1b4 528 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
mbed_official 624:83778a75d1b4 529
mbed_official 624:83778a75d1b4 530 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
mbed_official 624:83778a75d1b4 531 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
mbed_official 624:83778a75d1b4 532
mbed_official 624:83778a75d1b4 533 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
mbed_official 624:83778a75d1b4 534 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
mbed_official 624:83778a75d1b4 535
mbed_official 624:83778a75d1b4 536 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
mbed_official 624:83778a75d1b4 537 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
mbed_official 624:83778a75d1b4 538
mbed_official 624:83778a75d1b4 539 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
mbed_official 624:83778a75d1b4 540 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
mbed_official 624:83778a75d1b4 541
mbed_official 624:83778a75d1b4 542 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
mbed_official 624:83778a75d1b4 543 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
mbed_official 624:83778a75d1b4 544
mbed_official 624:83778a75d1b4 545
mbed_official 624:83778a75d1b4 546 /*------------- PL230 uDMA (PL230) --------------------------------------*/
mbed_official 624:83778a75d1b4 547 typedef struct
mbed_official 624:83778a75d1b4 548 {
mbed_official 624:83778a75d1b4 549 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
mbed_official 624:83778a75d1b4 550 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
mbed_official 624:83778a75d1b4 551 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
mbed_official 624:83778a75d1b4 552 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
mbed_official 624:83778a75d1b4 553 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
mbed_official 624:83778a75d1b4 554 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
mbed_official 624:83778a75d1b4 555 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
mbed_official 624:83778a75d1b4 556 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
mbed_official 624:83778a75d1b4 557 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
mbed_official 624:83778a75d1b4 558 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
mbed_official 624:83778a75d1b4 559 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
mbed_official 624:83778a75d1b4 560 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
mbed_official 624:83778a75d1b4 561 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
mbed_official 624:83778a75d1b4 562 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
mbed_official 624:83778a75d1b4 563 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
mbed_official 624:83778a75d1b4 564 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
mbed_official 624:83778a75d1b4 565 uint32_t RESERVED0[3];
mbed_official 624:83778a75d1b4 566 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
mbed_official 624:83778a75d1b4 567
mbed_official 624:83778a75d1b4 568 } CMSDK_PL230_TypeDef;
mbed_official 624:83778a75d1b4 569
mbed_official 624:83778a75d1b4 570 #define PL230_DMA_CHNL_BITS 0
mbed_official 624:83778a75d1b4 571
mbed_official 624:83778a75d1b4 572 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
mbed_official 624:83778a75d1b4 573 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
mbed_official 624:83778a75d1b4 574
mbed_official 624:83778a75d1b4 575 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
mbed_official 624:83778a75d1b4 576 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
mbed_official 624:83778a75d1b4 577
mbed_official 624:83778a75d1b4 578 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
mbed_official 624:83778a75d1b4 579 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
mbed_official 624:83778a75d1b4 580
mbed_official 624:83778a75d1b4 581 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
mbed_official 624:83778a75d1b4 582 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
mbed_official 624:83778a75d1b4 583
mbed_official 624:83778a75d1b4 584 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
mbed_official 624:83778a75d1b4 585 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
mbed_official 624:83778a75d1b4 586
mbed_official 624:83778a75d1b4 587 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
mbed_official 624:83778a75d1b4 588 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
mbed_official 624:83778a75d1b4 589
mbed_official 624:83778a75d1b4 590 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
mbed_official 624:83778a75d1b4 591 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
mbed_official 624:83778a75d1b4 592
mbed_official 624:83778a75d1b4 593 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
mbed_official 624:83778a75d1b4 594 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
mbed_official 624:83778a75d1b4 595
mbed_official 624:83778a75d1b4 596 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
mbed_official 624:83778a75d1b4 597 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
mbed_official 624:83778a75d1b4 598
mbed_official 624:83778a75d1b4 599 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
mbed_official 624:83778a75d1b4 600 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
mbed_official 624:83778a75d1b4 601
mbed_official 624:83778a75d1b4 602 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
mbed_official 624:83778a75d1b4 603 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
mbed_official 624:83778a75d1b4 604
mbed_official 624:83778a75d1b4 605 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
mbed_official 624:83778a75d1b4 606 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
mbed_official 624:83778a75d1b4 607
mbed_official 624:83778a75d1b4 608 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
mbed_official 624:83778a75d1b4 609 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
mbed_official 624:83778a75d1b4 610
mbed_official 624:83778a75d1b4 611 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
mbed_official 624:83778a75d1b4 612 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
mbed_official 624:83778a75d1b4 613
mbed_official 624:83778a75d1b4 614 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
mbed_official 624:83778a75d1b4 615 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
mbed_official 624:83778a75d1b4 616
mbed_official 624:83778a75d1b4 617 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
mbed_official 624:83778a75d1b4 618 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
mbed_official 624:83778a75d1b4 619
mbed_official 624:83778a75d1b4 620 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
mbed_official 624:83778a75d1b4 621 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
mbed_official 624:83778a75d1b4 622
mbed_official 624:83778a75d1b4 623 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
mbed_official 624:83778a75d1b4 624 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
mbed_official 624:83778a75d1b4 625
mbed_official 624:83778a75d1b4 626 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
mbed_official 624:83778a75d1b4 627 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
mbed_official 624:83778a75d1b4 628
mbed_official 624:83778a75d1b4 629 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
mbed_official 624:83778a75d1b4 630 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
mbed_official 624:83778a75d1b4 631
mbed_official 624:83778a75d1b4 632 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
mbed_official 624:83778a75d1b4 633 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
mbed_official 624:83778a75d1b4 634
mbed_official 624:83778a75d1b4 635 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
mbed_official 624:83778a75d1b4 636 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
mbed_official 624:83778a75d1b4 637
mbed_official 624:83778a75d1b4 638 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
mbed_official 624:83778a75d1b4 639 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
mbed_official 624:83778a75d1b4 640
mbed_official 624:83778a75d1b4 641
mbed_official 624:83778a75d1b4 642 /*------------------- Watchdog ----------------------------------------------*/
mbed_official 624:83778a75d1b4 643 typedef struct
mbed_official 624:83778a75d1b4 644 {
mbed_official 624:83778a75d1b4 645
mbed_official 624:83778a75d1b4 646 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
mbed_official 624:83778a75d1b4 647 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
mbed_official 624:83778a75d1b4 648 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
mbed_official 624:83778a75d1b4 649 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
mbed_official 624:83778a75d1b4 650 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
mbed_official 624:83778a75d1b4 651 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
mbed_official 624:83778a75d1b4 652 uint32_t RESERVED0[762];
mbed_official 624:83778a75d1b4 653 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
mbed_official 624:83778a75d1b4 654 uint32_t RESERVED1[191];
mbed_official 624:83778a75d1b4 655 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
mbed_official 624:83778a75d1b4 656 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
mbed_official 624:83778a75d1b4 657 }CMSDK_WATCHDOG_TypeDef;
mbed_official 624:83778a75d1b4 658
mbed_official 624:83778a75d1b4 659 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
mbed_official 624:83778a75d1b4 660 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
mbed_official 624:83778a75d1b4 661
mbed_official 624:83778a75d1b4 662 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
mbed_official 624:83778a75d1b4 663 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
mbed_official 624:83778a75d1b4 664
mbed_official 624:83778a75d1b4 665 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
mbed_official 624:83778a75d1b4 666 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
mbed_official 624:83778a75d1b4 667
mbed_official 624:83778a75d1b4 668 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
mbed_official 624:83778a75d1b4 669 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
mbed_official 624:83778a75d1b4 670
mbed_official 624:83778a75d1b4 671 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
mbed_official 624:83778a75d1b4 672 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
mbed_official 624:83778a75d1b4 673
mbed_official 624:83778a75d1b4 674 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
mbed_official 624:83778a75d1b4 675 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
mbed_official 624:83778a75d1b4 676
mbed_official 624:83778a75d1b4 677 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
mbed_official 624:83778a75d1b4 678 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
mbed_official 624:83778a75d1b4 679
mbed_official 624:83778a75d1b4 680 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
mbed_official 624:83778a75d1b4 681 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
mbed_official 624:83778a75d1b4 682
mbed_official 624:83778a75d1b4 683 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
mbed_official 624:83778a75d1b4 684 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
mbed_official 624:83778a75d1b4 685
mbed_official 624:83778a75d1b4 686 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
mbed_official 624:83778a75d1b4 687 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
mbed_official 624:83778a75d1b4 688
mbed_official 624:83778a75d1b4 689
mbed_official 624:83778a75d1b4 690
mbed_official 624:83778a75d1b4 691 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 624:83778a75d1b4 692 #if defined ( __CC_ARM )
mbed_official 624:83778a75d1b4 693 #pragma pop
mbed_official 624:83778a75d1b4 694 #elif defined(__ICCARM__)
mbed_official 624:83778a75d1b4 695 /* leave anonymous unions enabled */
mbed_official 624:83778a75d1b4 696 #elif defined(__GNUC__)
mbed_official 624:83778a75d1b4 697 /* anonymous unions are enabled by default */
mbed_official 624:83778a75d1b4 698 #elif defined(__TMS470__)
mbed_official 624:83778a75d1b4 699 /* anonymous unions are enabled by default */
mbed_official 624:83778a75d1b4 700 #elif defined(__TASKING__)
mbed_official 624:83778a75d1b4 701 #pragma warning restore
mbed_official 624:83778a75d1b4 702 #else
mbed_official 624:83778a75d1b4 703 #warning Not supported compiler type
mbed_official 624:83778a75d1b4 704 #endif
mbed_official 624:83778a75d1b4 705
mbed_official 624:83778a75d1b4 706
mbed_official 624:83778a75d1b4 707
mbed_official 624:83778a75d1b4 708
mbed_official 624:83778a75d1b4 709 /* ================================================================================ */
mbed_official 624:83778a75d1b4 710 /* ================ Peripheral memory map ================ */
mbed_official 624:83778a75d1b4 711 /* ================================================================================ */
mbed_official 624:83778a75d1b4 712
mbed_official 624:83778a75d1b4 713 /* Peripheral and SRAM base address */
mbed_official 624:83778a75d1b4 714 #define CMSDK_FLASH_BASE (0x00000000UL)
mbed_official 624:83778a75d1b4 715 #define CMSDK_SRAM_BASE (0x20000000UL)
mbed_official 624:83778a75d1b4 716 #define CMSDK_PERIPH_BASE (0x40000000UL)
mbed_official 624:83778a75d1b4 717
mbed_official 624:83778a75d1b4 718 #define CMSDK_RAM_BASE (0x20000000UL)
mbed_official 624:83778a75d1b4 719 #define CMSDK_APB_BASE (0x40000000UL)
mbed_official 624:83778a75d1b4 720 #define CMSDK_AHB_BASE (0x40010000UL)
mbed_official 624:83778a75d1b4 721
mbed_official 624:83778a75d1b4 722 /* APB peripherals */
mbed_official 624:83778a75d1b4 723 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
mbed_official 624:83778a75d1b4 724 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
mbed_official 624:83778a75d1b4 725 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
mbed_official 624:83778a75d1b4 726 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
mbed_official 624:83778a75d1b4 727 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
mbed_official 624:83778a75d1b4 728 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL)
mbed_official 624:83778a75d1b4 729 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL)
mbed_official 624:83778a75d1b4 730 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
mbed_official 624:83778a75d1b4 731 #define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
mbed_official 624:83778a75d1b4 732 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
mbed_official 624:83778a75d1b4 733 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
mbed_official 624:83778a75d1b4 734
mbed_official 624:83778a75d1b4 735 /* AHB peripherals */
mbed_official 624:83778a75d1b4 736 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
mbed_official 624:83778a75d1b4 737 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
mbed_official 624:83778a75d1b4 738 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
mbed_official 624:83778a75d1b4 739 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
mbed_official 624:83778a75d1b4 740 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
mbed_official 624:83778a75d1b4 741
mbed_official 624:83778a75d1b4 742
mbed_official 624:83778a75d1b4 743 /* ================================================================================ */
mbed_official 624:83778a75d1b4 744 /* ================ Peripheral declaration ================ */
mbed_official 624:83778a75d1b4 745 /* ================================================================================ */
mbed_official 624:83778a75d1b4 746
mbed_official 624:83778a75d1b4 747 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
mbed_official 624:83778a75d1b4 748 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
mbed_official 624:83778a75d1b4 749 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
mbed_official 624:83778a75d1b4 750 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
mbed_official 624:83778a75d1b4 751 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
mbed_official 624:83778a75d1b4 752 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
mbed_official 624:83778a75d1b4 753 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
mbed_official 624:83778a75d1b4 754 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
mbed_official 624:83778a75d1b4 755 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
mbed_official 624:83778a75d1b4 756 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
mbed_official 624:83778a75d1b4 757 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
mbed_official 624:83778a75d1b4 758 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
mbed_official 624:83778a75d1b4 759 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
mbed_official 624:83778a75d1b4 760 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
mbed_official 624:83778a75d1b4 761 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
mbed_official 624:83778a75d1b4 762 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
mbed_official 624:83778a75d1b4 763
mbed_official 624:83778a75d1b4 764
mbed_official 624:83778a75d1b4 765 #ifdef __cplusplus
mbed_official 624:83778a75d1b4 766 }
mbed_official 624:83778a75d1b4 767 #endif
mbed_official 624:83778a75d1b4 768
mbed_official 624:83778a75d1b4 769 #endif /* CMSDK_BEID_H */