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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_qspi.c@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 610:813dcc80987e 1 /**
mbed_official 610:813dcc80987e 2 ******************************************************************************
mbed_official 610:813dcc80987e 3 * @file stm32l4xx_hal_qspi.c
mbed_official 610:813dcc80987e 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.0
mbed_official 610:813dcc80987e 6 * @date 26-June-2015
mbed_official 610:813dcc80987e 7 * @brief QSPI HAL module driver.
mbed_official 610:813dcc80987e 8 * This file provides firmware functions to manage the following
mbed_official 610:813dcc80987e 9 * functionalities of the QuadSPI interface (QSPI).
mbed_official 610:813dcc80987e 10 * + Initialization and de-initialization functions
mbed_official 610:813dcc80987e 11 * + Indirect functional mode management
mbed_official 610:813dcc80987e 12 * + Memory-mapped functional mode management
mbed_official 610:813dcc80987e 13 * + Auto-polling functional mode management
mbed_official 610:813dcc80987e 14 * + Interrupts and flags management
mbed_official 610:813dcc80987e 15 * + DMA channel configuration for indirect functional mode
mbed_official 610:813dcc80987e 16 * + Errors management and abort functionality
mbed_official 610:813dcc80987e 17 *
mbed_official 610:813dcc80987e 18 *
mbed_official 610:813dcc80987e 19 @verbatim
mbed_official 610:813dcc80987e 20 ===============================================================================
mbed_official 610:813dcc80987e 21 ##### How to use this driver #####
mbed_official 610:813dcc80987e 22 ===============================================================================
mbed_official 610:813dcc80987e 23 [..]
mbed_official 610:813dcc80987e 24 *** Initialization ***
mbed_official 610:813dcc80987e 25 ======================
mbed_official 610:813dcc80987e 26 [..]
mbed_official 610:813dcc80987e 27 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
mbed_official 610:813dcc80987e 28 (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
mbed_official 610:813dcc80987e 29 (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
mbed_official 610:813dcc80987e 30 (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
mbed_official 610:813dcc80987e 31 (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
mbed_official 610:813dcc80987e 32 (++) If interrupt mode is used, enable and configure QuadSPI global
mbed_official 610:813dcc80987e 33 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
mbed_official 610:813dcc80987e 34 (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
mbed_official 610:813dcc80987e 35 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
mbed_official 610:813dcc80987e 36 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
mbed_official 610:813dcc80987e 37 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
mbed_official 610:813dcc80987e 38 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
mbed_official 610:813dcc80987e 39 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
mbed_official 610:813dcc80987e 40
mbed_official 610:813dcc80987e 41 *** Indirect functional mode ***
mbed_official 610:813dcc80987e 42 ================================
mbed_official 610:813dcc80987e 43 [..]
mbed_official 610:813dcc80987e 44 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
mbed_official 610:813dcc80987e 45 functions :
mbed_official 610:813dcc80987e 46 (++) Instruction phase : the mode used and if present the instruction opcode.
mbed_official 610:813dcc80987e 47 (++) Address phase : the mode used and if present the size and the address value.
mbed_official 610:813dcc80987e 48 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
mbed_official 610:813dcc80987e 49 bytes values.
mbed_official 610:813dcc80987e 50 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
mbed_official 610:813dcc80987e 51 (++) Data phase : the mode used and if present the number of bytes.
mbed_official 610:813dcc80987e 52 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
mbed_official 610:813dcc80987e 53 if activated.
mbed_official 610:813dcc80987e 54 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
mbed_official 610:813dcc80987e 55 (#) If no data is required for the command, it is sent directly to the memory :
mbed_official 610:813dcc80987e 56 (++) In polling mode, the output of the function is done when the transfer is complete.
mbed_official 610:813dcc80987e 57 (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
mbed_official 610:813dcc80987e 58 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
mbed_official 610:813dcc80987e 59 HAL_QSPI_Transmit_IT() after the command configuration :
mbed_official 610:813dcc80987e 60 (++) In polling mode, the output of the function is done when the transfer is complete.
mbed_official 610:813dcc80987e 61 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
mbed_official 610:813dcc80987e 62 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
mbed_official 610:813dcc80987e 63 (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
mbed_official 610:813dcc80987e 64 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
mbed_official 610:813dcc80987e 65 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
mbed_official 610:813dcc80987e 66 HAL_QSPI_Receive_IT() after the command configuration :
mbed_official 610:813dcc80987e 67 (++) In polling mode, the output of the function is done when the transfer is complete.
mbed_official 610:813dcc80987e 68 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
mbed_official 610:813dcc80987e 69 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
mbed_official 610:813dcc80987e 70 (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
mbed_official 610:813dcc80987e 71 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
mbed_official 610:813dcc80987e 72
mbed_official 610:813dcc80987e 73 *** Auto-polling functional mode ***
mbed_official 610:813dcc80987e 74 ====================================
mbed_official 610:813dcc80987e 75 [..]
mbed_official 610:813dcc80987e 76 (#) Configure the command sequence and the auto-polling functional mode using the
mbed_official 610:813dcc80987e 77 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
mbed_official 610:813dcc80987e 78 (++) Instruction phase : the mode used and if present the instruction opcode.
mbed_official 610:813dcc80987e 79 (++) Address phase : the mode used and if present the size and the address value.
mbed_official 610:813dcc80987e 80 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
mbed_official 610:813dcc80987e 81 bytes values.
mbed_official 610:813dcc80987e 82 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
mbed_official 610:813dcc80987e 83 (++) Data phase : the mode used.
mbed_official 610:813dcc80987e 84 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
mbed_official 610:813dcc80987e 85 if activated.
mbed_official 610:813dcc80987e 86 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
mbed_official 610:813dcc80987e 87 (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
mbed_official 610:813dcc80987e 88 the polling interval and the automatic stop activation.
mbed_official 610:813dcc80987e 89 (#) After the configuration :
mbed_official 610:813dcc80987e 90 (++) In polling mode, the output of the function is done when the status match is reached. The
mbed_official 610:813dcc80987e 91 automatic stop is activated to avoid an infinite loop.
mbed_official 610:813dcc80987e 92 (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
mbed_official 610:813dcc80987e 93
mbed_official 610:813dcc80987e 94 *** Memory-mapped functional mode ***
mbed_official 610:813dcc80987e 95 =====================================
mbed_official 610:813dcc80987e 96 [..]
mbed_official 610:813dcc80987e 97 (#) Configure the command sequence and the memory-mapped functional mode using the
mbed_official 610:813dcc80987e 98 HAL_QSPI_MemoryMapped() functions :
mbed_official 610:813dcc80987e 99 (++) Instruction phase : the mode used and if present the instruction opcode.
mbed_official 610:813dcc80987e 100 (++) Address phase : the mode used and the size.
mbed_official 610:813dcc80987e 101 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
mbed_official 610:813dcc80987e 102 bytes values.
mbed_official 610:813dcc80987e 103 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
mbed_official 610:813dcc80987e 104 (++) Data phase : the mode used.
mbed_official 610:813dcc80987e 105 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
mbed_official 610:813dcc80987e 106 if activated.
mbed_official 610:813dcc80987e 107 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
mbed_official 610:813dcc80987e 108 (++) The timeout activation and the timeout period.
mbed_official 610:813dcc80987e 109 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
mbed_official 610:813dcc80987e 110 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
mbed_official 610:813dcc80987e 111
mbed_official 610:813dcc80987e 112 *** Errors management and abort functionality ***
mbed_official 610:813dcc80987e 113 ==================================================
mbed_official 610:813dcc80987e 114 [..]
mbed_official 610:813dcc80987e 115 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
mbed_official 610:813dcc80987e 116 (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
mbed_official 610:813dcc80987e 117 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
mbed_official 610:813dcc80987e 118
mbed_official 610:813dcc80987e 119 *** Workarounds linked to Silicon Limitation ***
mbed_official 610:813dcc80987e 120 ====================================================
mbed_official 610:813dcc80987e 121 [..]
mbed_official 610:813dcc80987e 122 (#) Workarounds Implemented inside HAL Driver
mbed_official 610:813dcc80987e 123 (++) Extra data written in the FIFO at the end of a read transfer
mbed_official 610:813dcc80987e 124
mbed_official 610:813dcc80987e 125 @endverbatim
mbed_official 610:813dcc80987e 126 ******************************************************************************
mbed_official 610:813dcc80987e 127 * @attention
mbed_official 610:813dcc80987e 128 *
mbed_official 610:813dcc80987e 129 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 610:813dcc80987e 130 *
mbed_official 610:813dcc80987e 131 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 610:813dcc80987e 132 * are permitted provided that the following conditions are met:
mbed_official 610:813dcc80987e 133 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 610:813dcc80987e 134 * this list of conditions and the following disclaimer.
mbed_official 610:813dcc80987e 135 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 610:813dcc80987e 136 * this list of conditions and the following disclaimer in the documentation
mbed_official 610:813dcc80987e 137 * and/or other materials provided with the distribution.
mbed_official 610:813dcc80987e 138 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 610:813dcc80987e 139 * may be used to endorse or promote products derived from this software
mbed_official 610:813dcc80987e 140 * without specific prior written permission.
mbed_official 610:813dcc80987e 141 *
mbed_official 610:813dcc80987e 142 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 610:813dcc80987e 143 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 610:813dcc80987e 144 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 610:813dcc80987e 145 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 610:813dcc80987e 146 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 610:813dcc80987e 147 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 610:813dcc80987e 148 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 610:813dcc80987e 149 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 610:813dcc80987e 150 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 610:813dcc80987e 151 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 610:813dcc80987e 152 *
mbed_official 610:813dcc80987e 153 ******************************************************************************
mbed_official 610:813dcc80987e 154 */
mbed_official 610:813dcc80987e 155
mbed_official 610:813dcc80987e 156 /* Includes ------------------------------------------------------------------*/
mbed_official 610:813dcc80987e 157 #include "stm32l4xx_hal.h"
mbed_official 610:813dcc80987e 158
mbed_official 610:813dcc80987e 159 /** @addtogroup STM32L4xx_HAL_Driver
mbed_official 610:813dcc80987e 160 * @{
mbed_official 610:813dcc80987e 161 */
mbed_official 610:813dcc80987e 162
mbed_official 610:813dcc80987e 163 /** @defgroup QSPI QSPI
mbed_official 610:813dcc80987e 164 * @brief QSPI HAL module driver
mbed_official 610:813dcc80987e 165 * @{
mbed_official 610:813dcc80987e 166 */
mbed_official 610:813dcc80987e 167 #ifdef HAL_QSPI_MODULE_ENABLED
mbed_official 610:813dcc80987e 168
mbed_official 610:813dcc80987e 169 /* Private typedef -----------------------------------------------------------*/
mbed_official 610:813dcc80987e 170
mbed_official 610:813dcc80987e 171 /* Private define ------------------------------------------------------------*/
mbed_official 610:813dcc80987e 172 /** @defgroup QSPI_Private_Constants QSPI Private Constants
mbed_official 610:813dcc80987e 173 * @{
mbed_official 610:813dcc80987e 174 */
mbed_official 610:813dcc80987e 175 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
mbed_official 610:813dcc80987e 176 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
mbed_official 610:813dcc80987e 177 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
mbed_official 610:813dcc80987e 178 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
mbed_official 610:813dcc80987e 179 /**
mbed_official 610:813dcc80987e 180 * @}
mbed_official 610:813dcc80987e 181 */
mbed_official 610:813dcc80987e 182
mbed_official 610:813dcc80987e 183 /* Private macro -------------------------------------------------------------*/
mbed_official 610:813dcc80987e 184 /** @defgroup QSPI_Private_Macros QSPI Private Macros
mbed_official 610:813dcc80987e 185 * @{
mbed_official 610:813dcc80987e 186 */
mbed_official 610:813dcc80987e 187 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
mbed_official 610:813dcc80987e 188 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
mbed_official 610:813dcc80987e 189 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
mbed_official 610:813dcc80987e 190 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
mbed_official 610:813dcc80987e 191 /**
mbed_official 610:813dcc80987e 192 * @}
mbed_official 610:813dcc80987e 193 */
mbed_official 610:813dcc80987e 194
mbed_official 610:813dcc80987e 195 /* Private variables ---------------------------------------------------------*/
mbed_official 610:813dcc80987e 196
mbed_official 610:813dcc80987e 197 /* Private function prototypes -----------------------------------------------*/
mbed_official 610:813dcc80987e 198 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
mbed_official 610:813dcc80987e 199 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
mbed_official 610:813dcc80987e 200 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
mbed_official 610:813dcc80987e 201 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
mbed_official 610:813dcc80987e 202 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 610:813dcc80987e 203 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
mbed_official 610:813dcc80987e 204 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
mbed_official 610:813dcc80987e 205
mbed_official 610:813dcc80987e 206 /* Exported functions --------------------------------------------------------*/
mbed_official 610:813dcc80987e 207
mbed_official 610:813dcc80987e 208 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
mbed_official 610:813dcc80987e 209 * @{
mbed_official 610:813dcc80987e 210 */
mbed_official 610:813dcc80987e 211
mbed_official 610:813dcc80987e 212 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
mbed_official 610:813dcc80987e 213 * @brief Initialization and Configuration functions
mbed_official 610:813dcc80987e 214 *
mbed_official 610:813dcc80987e 215 @verbatim
mbed_official 610:813dcc80987e 216 ===============================================================================
mbed_official 610:813dcc80987e 217 ##### Initialization and Configuration functions #####
mbed_official 610:813dcc80987e 218 ===============================================================================
mbed_official 610:813dcc80987e 219 [..]
mbed_official 610:813dcc80987e 220 This subsection provides a set of functions allowing to :
mbed_official 610:813dcc80987e 221 (+) Initialize the QuadSPI.
mbed_official 610:813dcc80987e 222 (+) De-initialize the QuadSPI.
mbed_official 610:813dcc80987e 223
mbed_official 610:813dcc80987e 224 @endverbatim
mbed_official 610:813dcc80987e 225 * @{
mbed_official 610:813dcc80987e 226 */
mbed_official 610:813dcc80987e 227
mbed_official 610:813dcc80987e 228 /**
mbed_official 610:813dcc80987e 229 * @brief Initialize the QSPI mode according to the specified parameters
mbed_official 610:813dcc80987e 230 * in the QSPI_InitTypeDef and initialize the associated handle.
mbed_official 610:813dcc80987e 231 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 232 * @retval HAL status
mbed_official 610:813dcc80987e 233 */
mbed_official 610:813dcc80987e 234 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 235 {
mbed_official 610:813dcc80987e 236 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 237
mbed_official 610:813dcc80987e 238 /* Check the QSPI handle allocation */
mbed_official 610:813dcc80987e 239 if(hqspi == NULL)
mbed_official 610:813dcc80987e 240 {
mbed_official 610:813dcc80987e 241 return HAL_ERROR;
mbed_official 610:813dcc80987e 242 }
mbed_official 610:813dcc80987e 243
mbed_official 610:813dcc80987e 244 /* Check the parameters */
mbed_official 610:813dcc80987e 245 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
mbed_official 610:813dcc80987e 246 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
mbed_official 610:813dcc80987e 247 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
mbed_official 610:813dcc80987e 248 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
mbed_official 610:813dcc80987e 249 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
mbed_official 610:813dcc80987e 250 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
mbed_official 610:813dcc80987e 251 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
mbed_official 610:813dcc80987e 252
mbed_official 610:813dcc80987e 253 /* Process locked */
mbed_official 610:813dcc80987e 254 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 255
mbed_official 610:813dcc80987e 256 if(hqspi->State == HAL_QSPI_STATE_RESET)
mbed_official 610:813dcc80987e 257 {
mbed_official 610:813dcc80987e 258 /* Allocate lock resource and initialize it */
mbed_official 610:813dcc80987e 259 hqspi->Lock = HAL_UNLOCKED;
mbed_official 610:813dcc80987e 260
mbed_official 610:813dcc80987e 261 /* Init the low level hardware : GPIO, CLOCK */
mbed_official 610:813dcc80987e 262 HAL_QSPI_MspInit(hqspi);
mbed_official 610:813dcc80987e 263
mbed_official 610:813dcc80987e 264 /* Configure the default timeout for the QSPI memory access */
mbed_official 610:813dcc80987e 265 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
mbed_official 610:813dcc80987e 266 }
mbed_official 610:813dcc80987e 267
mbed_official 610:813dcc80987e 268 /* Configure QSPI FIFO Threshold */
mbed_official 610:813dcc80987e 269 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
mbed_official 610:813dcc80987e 270 ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
mbed_official 610:813dcc80987e 271
mbed_official 610:813dcc80987e 272 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 273 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
mbed_official 610:813dcc80987e 274
mbed_official 610:813dcc80987e 275 if(status == HAL_OK)
mbed_official 610:813dcc80987e 276 {
mbed_official 610:813dcc80987e 277 /* Configure QSPI Clock Prescaler and Sample Shift */
mbed_official 610:813dcc80987e 278 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
mbed_official 610:813dcc80987e 279 ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
mbed_official 610:813dcc80987e 280 hqspi->Init.SampleShifting));
mbed_official 610:813dcc80987e 281
mbed_official 610:813dcc80987e 282 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
mbed_official 610:813dcc80987e 283 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
mbed_official 610:813dcc80987e 284 ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) |
mbed_official 610:813dcc80987e 285 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
mbed_official 610:813dcc80987e 286
mbed_official 610:813dcc80987e 287 /* Enable the QSPI peripheral */
mbed_official 610:813dcc80987e 288 __HAL_QSPI_ENABLE(hqspi);
mbed_official 610:813dcc80987e 289
mbed_official 610:813dcc80987e 290 /* Set QSPI error code to none */
mbed_official 610:813dcc80987e 291 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 292
mbed_official 610:813dcc80987e 293 /* Initialize the QSPI state */
mbed_official 610:813dcc80987e 294 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 295 }
mbed_official 610:813dcc80987e 296
mbed_official 610:813dcc80987e 297 /* Release Lock */
mbed_official 610:813dcc80987e 298 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 299
mbed_official 610:813dcc80987e 300 /* Return function status */
mbed_official 610:813dcc80987e 301 return status;
mbed_official 610:813dcc80987e 302 }
mbed_official 610:813dcc80987e 303
mbed_official 610:813dcc80987e 304 /**
mbed_official 610:813dcc80987e 305 * @brief De-Initialize the QSPI peripheral.
mbed_official 610:813dcc80987e 306 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 307 * @retval HAL status
mbed_official 610:813dcc80987e 308 */
mbed_official 610:813dcc80987e 309 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 310 {
mbed_official 610:813dcc80987e 311 /* Check the QSPI handle allocation */
mbed_official 610:813dcc80987e 312 if(hqspi == NULL)
mbed_official 610:813dcc80987e 313 {
mbed_official 610:813dcc80987e 314 return HAL_ERROR;
mbed_official 610:813dcc80987e 315 }
mbed_official 610:813dcc80987e 316
mbed_official 610:813dcc80987e 317 /* Process locked */
mbed_official 610:813dcc80987e 318 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 319
mbed_official 610:813dcc80987e 320 /* Disable the QSPI Peripheral Clock */
mbed_official 610:813dcc80987e 321 __HAL_QSPI_DISABLE(hqspi);
mbed_official 610:813dcc80987e 322
mbed_official 610:813dcc80987e 323 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 610:813dcc80987e 324 HAL_QSPI_MspDeInit(hqspi);
mbed_official 610:813dcc80987e 325
mbed_official 610:813dcc80987e 326 /* Set QSPI error code to none */
mbed_official 610:813dcc80987e 327 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 328
mbed_official 610:813dcc80987e 329 /* Initialize the QSPI state */
mbed_official 610:813dcc80987e 330 hqspi->State = HAL_QSPI_STATE_RESET;
mbed_official 610:813dcc80987e 331
mbed_official 610:813dcc80987e 332 /* Release Lock */
mbed_official 610:813dcc80987e 333 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 334
mbed_official 610:813dcc80987e 335 return HAL_OK;
mbed_official 610:813dcc80987e 336 }
mbed_official 610:813dcc80987e 337
mbed_official 610:813dcc80987e 338 /**
mbed_official 610:813dcc80987e 339 * @brief Initialize the QSPI MSP.
mbed_official 610:813dcc80987e 340 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 341 * @retval None
mbed_official 610:813dcc80987e 342 */
mbed_official 610:813dcc80987e 343 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 344 {
mbed_official 610:813dcc80987e 345 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 346 the HAL_QSPI_MspInit can be implemented in the user file
mbed_official 610:813dcc80987e 347 */
mbed_official 610:813dcc80987e 348 }
mbed_official 610:813dcc80987e 349
mbed_official 610:813dcc80987e 350 /**
mbed_official 610:813dcc80987e 351 * @brief DeInitialize the QSPI MSP.
mbed_official 610:813dcc80987e 352 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 353 * @retval None
mbed_official 610:813dcc80987e 354 */
mbed_official 610:813dcc80987e 355 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 356 {
mbed_official 610:813dcc80987e 357 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 358 the HAL_QSPI_MspDeInit can be implemented in the user file
mbed_official 610:813dcc80987e 359 */
mbed_official 610:813dcc80987e 360 }
mbed_official 610:813dcc80987e 361
mbed_official 610:813dcc80987e 362 /**
mbed_official 610:813dcc80987e 363 * @}
mbed_official 610:813dcc80987e 364 */
mbed_official 610:813dcc80987e 365
mbed_official 610:813dcc80987e 366 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
mbed_official 610:813dcc80987e 367 * @brief QSPI Transmit/Receive functions
mbed_official 610:813dcc80987e 368 *
mbed_official 610:813dcc80987e 369 @verbatim
mbed_official 610:813dcc80987e 370 ===============================================================================
mbed_official 610:813dcc80987e 371 ##### IO operation functions #####
mbed_official 610:813dcc80987e 372 ===============================================================================
mbed_official 610:813dcc80987e 373 [..]
mbed_official 610:813dcc80987e 374 This subsection provides a set of functions allowing to :
mbed_official 610:813dcc80987e 375 (+) Handle the interrupts.
mbed_official 610:813dcc80987e 376 (+) Handle the command sequence.
mbed_official 610:813dcc80987e 377 (+) Transmit data in blocking, interrupt or DMA mode.
mbed_official 610:813dcc80987e 378 (+) Receive data in blocking, interrupt or DMA mode.
mbed_official 610:813dcc80987e 379 (+) Manage the auto-polling functional mode.
mbed_official 610:813dcc80987e 380 (+) Manage the memory-mapped functional mode.
mbed_official 610:813dcc80987e 381
mbed_official 610:813dcc80987e 382 @endverbatim
mbed_official 610:813dcc80987e 383 * @{
mbed_official 610:813dcc80987e 384 */
mbed_official 610:813dcc80987e 385
mbed_official 610:813dcc80987e 386 /**
mbed_official 610:813dcc80987e 387 * @brief Handle QSPI interrupt request.
mbed_official 610:813dcc80987e 388 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 389 * @retval None
mbed_official 610:813dcc80987e 390 */
mbed_official 610:813dcc80987e 391 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 392 {
mbed_official 610:813dcc80987e 393 __IO uint32_t *data_reg;
mbed_official 610:813dcc80987e 394 uint32_t flag = 0, itsource = 0;
mbed_official 610:813dcc80987e 395
mbed_official 610:813dcc80987e 396 /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
mbed_official 610:813dcc80987e 397 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
mbed_official 610:813dcc80987e 398 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
mbed_official 610:813dcc80987e 399
mbed_official 610:813dcc80987e 400 if((flag != RESET) && (itsource != RESET))
mbed_official 610:813dcc80987e 401 {
mbed_official 610:813dcc80987e 402 data_reg = &hqspi->Instance->DR;
mbed_official 610:813dcc80987e 403
mbed_official 610:813dcc80987e 404 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
mbed_official 610:813dcc80987e 405 {
mbed_official 610:813dcc80987e 406 /* Transmission process */
mbed_official 610:813dcc80987e 407 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
mbed_official 610:813dcc80987e 408 {
mbed_official 610:813dcc80987e 409 if (hqspi->TxXferCount > 0)
mbed_official 610:813dcc80987e 410 {
mbed_official 610:813dcc80987e 411 /* Fill the FIFO until it is full */
mbed_official 610:813dcc80987e 412 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
mbed_official 610:813dcc80987e 413 hqspi->TxXferCount--;
mbed_official 610:813dcc80987e 414 }
mbed_official 610:813dcc80987e 415 else
mbed_official 610:813dcc80987e 416 {
mbed_official 610:813dcc80987e 417 /* No more data available for the transfer */
mbed_official 610:813dcc80987e 418 break;
mbed_official 610:813dcc80987e 419 }
mbed_official 610:813dcc80987e 420 }
mbed_official 610:813dcc80987e 421 }
mbed_official 610:813dcc80987e 422 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
mbed_official 610:813dcc80987e 423 {
mbed_official 610:813dcc80987e 424 /* Receiving Process */
mbed_official 610:813dcc80987e 425 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
mbed_official 610:813dcc80987e 426 {
mbed_official 610:813dcc80987e 427 if (hqspi->RxXferCount > 0)
mbed_official 610:813dcc80987e 428 {
mbed_official 610:813dcc80987e 429 /* Read the FIFO until it is empty */
mbed_official 610:813dcc80987e 430 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
mbed_official 610:813dcc80987e 431 hqspi->RxXferCount--;
mbed_official 610:813dcc80987e 432 }
mbed_official 610:813dcc80987e 433 else
mbed_official 610:813dcc80987e 434 {
mbed_official 610:813dcc80987e 435 /* All data have been received for the transfer */
mbed_official 610:813dcc80987e 436 break;
mbed_official 610:813dcc80987e 437 }
mbed_official 610:813dcc80987e 438 }
mbed_official 610:813dcc80987e 439 }
mbed_official 610:813dcc80987e 440
mbed_official 610:813dcc80987e 441 /* FIFO Threshold callback */
mbed_official 610:813dcc80987e 442 HAL_QSPI_FifoThresholdCallback(hqspi);
mbed_official 610:813dcc80987e 443 }
mbed_official 610:813dcc80987e 444
mbed_official 610:813dcc80987e 445 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
mbed_official 610:813dcc80987e 446 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 447 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
mbed_official 610:813dcc80987e 448
mbed_official 610:813dcc80987e 449 if((flag != RESET) && (itsource != RESET))
mbed_official 610:813dcc80987e 450 {
mbed_official 610:813dcc80987e 451 /* Clear interrupt */
mbed_official 610:813dcc80987e 452 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 453
mbed_official 610:813dcc80987e 454 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
mbed_official 610:813dcc80987e 455 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
mbed_official 610:813dcc80987e 456
mbed_official 610:813dcc80987e 457 /* Transfer complete callback */
mbed_official 610:813dcc80987e 458 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
mbed_official 610:813dcc80987e 459 {
mbed_official 610:813dcc80987e 460 /* Clear Busy bit */
mbed_official 610:813dcc80987e 461 HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 462
mbed_official 610:813dcc80987e 463 /* TX Complete callback */
mbed_official 610:813dcc80987e 464 HAL_QSPI_TxCpltCallback(hqspi);
mbed_official 610:813dcc80987e 465 }
mbed_official 610:813dcc80987e 466 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
mbed_official 610:813dcc80987e 467 {
mbed_official 610:813dcc80987e 468 data_reg = &hqspi->Instance->DR;
mbed_official 610:813dcc80987e 469 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
mbed_official 610:813dcc80987e 470 {
mbed_official 610:813dcc80987e 471 if (hqspi->RxXferCount > 0)
mbed_official 610:813dcc80987e 472 {
mbed_official 610:813dcc80987e 473 /* Read the last data received in the FIFO until it is empty */
mbed_official 610:813dcc80987e 474 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
mbed_official 610:813dcc80987e 475 hqspi->RxXferCount--;
mbed_official 610:813dcc80987e 476 }
mbed_official 610:813dcc80987e 477 else
mbed_official 610:813dcc80987e 478 {
mbed_official 610:813dcc80987e 479 /* All data have been received for the transfer */
mbed_official 610:813dcc80987e 480 break;
mbed_official 610:813dcc80987e 481 }
mbed_official 610:813dcc80987e 482 }
mbed_official 610:813dcc80987e 483
mbed_official 610:813dcc80987e 484 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
mbed_official 610:813dcc80987e 485 HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 486
mbed_official 610:813dcc80987e 487 /* RX Complete callback */
mbed_official 610:813dcc80987e 488 HAL_QSPI_RxCpltCallback(hqspi);
mbed_official 610:813dcc80987e 489 }
mbed_official 610:813dcc80987e 490 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
mbed_official 610:813dcc80987e 491 {
mbed_official 610:813dcc80987e 492 /* Command Complete callback */
mbed_official 610:813dcc80987e 493 HAL_QSPI_CmdCpltCallback(hqspi);
mbed_official 610:813dcc80987e 494 }
mbed_official 610:813dcc80987e 495
mbed_official 610:813dcc80987e 496 /* Change state of QSPI */
mbed_official 610:813dcc80987e 497 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 498 }
mbed_official 610:813dcc80987e 499
mbed_official 610:813dcc80987e 500 /* QSPI Status Match interrupt occurred ------------------------------------*/
mbed_official 610:813dcc80987e 501 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
mbed_official 610:813dcc80987e 502 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
mbed_official 610:813dcc80987e 503
mbed_official 610:813dcc80987e 504 if((flag != RESET) && (itsource != RESET))
mbed_official 610:813dcc80987e 505 {
mbed_official 610:813dcc80987e 506 /* Clear interrupt */
mbed_official 610:813dcc80987e 507 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
mbed_official 610:813dcc80987e 508
mbed_official 610:813dcc80987e 509 /* Check if the automatic poll mode stop is activated */
mbed_official 610:813dcc80987e 510 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
mbed_official 610:813dcc80987e 511 {
mbed_official 610:813dcc80987e 512 /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
mbed_official 610:813dcc80987e 513 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
mbed_official 610:813dcc80987e 514
mbed_official 610:813dcc80987e 515 /* Change state of QSPI */
mbed_official 610:813dcc80987e 516 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 517 }
mbed_official 610:813dcc80987e 518
mbed_official 610:813dcc80987e 519 /* Status match callback */
mbed_official 610:813dcc80987e 520 HAL_QSPI_StatusMatchCallback(hqspi);
mbed_official 610:813dcc80987e 521 }
mbed_official 610:813dcc80987e 522
mbed_official 610:813dcc80987e 523 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
mbed_official 610:813dcc80987e 524 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
mbed_official 610:813dcc80987e 525 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
mbed_official 610:813dcc80987e 526
mbed_official 610:813dcc80987e 527 if((flag != RESET) && (itsource != RESET))
mbed_official 610:813dcc80987e 528 {
mbed_official 610:813dcc80987e 529 /* Clear interrupt */
mbed_official 610:813dcc80987e 530 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
mbed_official 610:813dcc80987e 531
mbed_official 610:813dcc80987e 532 /* Disable all the QSPI Interrupts */
mbed_official 610:813dcc80987e 533 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
mbed_official 610:813dcc80987e 534
mbed_official 610:813dcc80987e 535 /* Set error code */
mbed_official 610:813dcc80987e 536 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
mbed_official 610:813dcc80987e 537
mbed_official 610:813dcc80987e 538 /* Change state of QSPI */
mbed_official 610:813dcc80987e 539 hqspi->State = HAL_QSPI_STATE_ERROR;
mbed_official 610:813dcc80987e 540
mbed_official 610:813dcc80987e 541 /* Error callback */
mbed_official 610:813dcc80987e 542 HAL_QSPI_ErrorCallback(hqspi);
mbed_official 610:813dcc80987e 543 }
mbed_official 610:813dcc80987e 544
mbed_official 610:813dcc80987e 545 /* QSPI Timeout interrupt occurred -----------------------------------------*/
mbed_official 610:813dcc80987e 546 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
mbed_official 610:813dcc80987e 547 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
mbed_official 610:813dcc80987e 548
mbed_official 610:813dcc80987e 549 if((flag != RESET) && (itsource != RESET))
mbed_official 610:813dcc80987e 550 {
mbed_official 610:813dcc80987e 551 /* Clear interrupt */
mbed_official 610:813dcc80987e 552 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
mbed_official 610:813dcc80987e 553
mbed_official 610:813dcc80987e 554 /* Timeout callback */
mbed_official 610:813dcc80987e 555 HAL_QSPI_TimeOutCallback(hqspi);
mbed_official 610:813dcc80987e 556 }
mbed_official 610:813dcc80987e 557 }
mbed_official 610:813dcc80987e 558
mbed_official 610:813dcc80987e 559 /**
mbed_official 610:813dcc80987e 560 * @brief Set the command configuration.
mbed_official 610:813dcc80987e 561 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 562 * @param cmd : structure that contains the command configuration information
mbed_official 610:813dcc80987e 563 * @param Timeout : Timeout duration
mbed_official 610:813dcc80987e 564 * @note This function is used only in Indirect Read or Write Modes
mbed_official 610:813dcc80987e 565 * @retval HAL status
mbed_official 610:813dcc80987e 566 */
mbed_official 610:813dcc80987e 567 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
mbed_official 610:813dcc80987e 568 {
mbed_official 610:813dcc80987e 569 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 570
mbed_official 610:813dcc80987e 571 /* Check the parameters */
mbed_official 610:813dcc80987e 572 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
mbed_official 610:813dcc80987e 573 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 574 {
mbed_official 610:813dcc80987e 575 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
mbed_official 610:813dcc80987e 576 }
mbed_official 610:813dcc80987e 577
mbed_official 610:813dcc80987e 578 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
mbed_official 610:813dcc80987e 579 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 580 {
mbed_official 610:813dcc80987e 581 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
mbed_official 610:813dcc80987e 582 }
mbed_official 610:813dcc80987e 583
mbed_official 610:813dcc80987e 584 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
mbed_official 610:813dcc80987e 585 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 586 {
mbed_official 610:813dcc80987e 587 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
mbed_official 610:813dcc80987e 588 }
mbed_official 610:813dcc80987e 589
mbed_official 610:813dcc80987e 590 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
mbed_official 610:813dcc80987e 591 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official 610:813dcc80987e 592
mbed_official 610:813dcc80987e 593 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
mbed_official 610:813dcc80987e 594 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
mbed_official 610:813dcc80987e 595 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official 610:813dcc80987e 596
mbed_official 610:813dcc80987e 597 /* Process locked */
mbed_official 610:813dcc80987e 598 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 599
mbed_official 610:813dcc80987e 600 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 601 {
mbed_official 610:813dcc80987e 602 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 603
mbed_official 610:813dcc80987e 604 /* Update QSPI state */
mbed_official 610:813dcc80987e 605 hqspi->State = HAL_QSPI_STATE_BUSY;
mbed_official 610:813dcc80987e 606
mbed_official 610:813dcc80987e 607 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 608 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
mbed_official 610:813dcc80987e 609
mbed_official 610:813dcc80987e 610 if (status == HAL_OK)
mbed_official 610:813dcc80987e 611 {
mbed_official 610:813dcc80987e 612 /* Call the configuration function */
mbed_official 610:813dcc80987e 613 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
mbed_official 610:813dcc80987e 614
mbed_official 610:813dcc80987e 615 if (cmd->DataMode == QSPI_DATA_NONE)
mbed_official 610:813dcc80987e 616 {
mbed_official 610:813dcc80987e 617 /* When there is no data phase, the transfer start as soon as the configuration is done
mbed_official 610:813dcc80987e 618 so wait until TC flag is set to go back in idle state */
mbed_official 610:813dcc80987e 619 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 620 {
mbed_official 610:813dcc80987e 621 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 622 }
mbed_official 610:813dcc80987e 623 else
mbed_official 610:813dcc80987e 624 {
mbed_official 610:813dcc80987e 625 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 626
mbed_official 610:813dcc80987e 627 /* Update QSPI state */
mbed_official 610:813dcc80987e 628 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 629 }
mbed_official 610:813dcc80987e 630
mbed_official 610:813dcc80987e 631 }
mbed_official 610:813dcc80987e 632 else
mbed_official 610:813dcc80987e 633 {
mbed_official 610:813dcc80987e 634 /* Update QSPI state */
mbed_official 610:813dcc80987e 635 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 636 }
mbed_official 610:813dcc80987e 637 }
mbed_official 610:813dcc80987e 638 }
mbed_official 610:813dcc80987e 639 else
mbed_official 610:813dcc80987e 640 {
mbed_official 610:813dcc80987e 641 status = HAL_BUSY;
mbed_official 610:813dcc80987e 642 }
mbed_official 610:813dcc80987e 643
mbed_official 610:813dcc80987e 644 /* Process unlocked */
mbed_official 610:813dcc80987e 645 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 646
mbed_official 610:813dcc80987e 647 /* Return function status */
mbed_official 610:813dcc80987e 648 return status;
mbed_official 610:813dcc80987e 649 }
mbed_official 610:813dcc80987e 650
mbed_official 610:813dcc80987e 651 /**
mbed_official 610:813dcc80987e 652 * @brief Set the command configuration in interrupt mode.
mbed_official 610:813dcc80987e 653 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 654 * @param cmd : structure that contains the command configuration information
mbed_official 610:813dcc80987e 655 * @note This function is used only in Indirect Read or Write Modes
mbed_official 610:813dcc80987e 656 * @retval HAL status
mbed_official 610:813dcc80987e 657 */
mbed_official 610:813dcc80987e 658 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
mbed_official 610:813dcc80987e 659 {
mbed_official 610:813dcc80987e 660 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 661
mbed_official 610:813dcc80987e 662 /* Check the parameters */
mbed_official 610:813dcc80987e 663 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
mbed_official 610:813dcc80987e 664 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 665 {
mbed_official 610:813dcc80987e 666 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
mbed_official 610:813dcc80987e 667 }
mbed_official 610:813dcc80987e 668
mbed_official 610:813dcc80987e 669 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
mbed_official 610:813dcc80987e 670 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 671 {
mbed_official 610:813dcc80987e 672 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
mbed_official 610:813dcc80987e 673 }
mbed_official 610:813dcc80987e 674
mbed_official 610:813dcc80987e 675 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
mbed_official 610:813dcc80987e 676 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 677 {
mbed_official 610:813dcc80987e 678 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
mbed_official 610:813dcc80987e 679 }
mbed_official 610:813dcc80987e 680
mbed_official 610:813dcc80987e 681 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
mbed_official 610:813dcc80987e 682 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official 610:813dcc80987e 683
mbed_official 610:813dcc80987e 684 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
mbed_official 610:813dcc80987e 685 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
mbed_official 610:813dcc80987e 686 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official 610:813dcc80987e 687
mbed_official 610:813dcc80987e 688 /* Process locked */
mbed_official 610:813dcc80987e 689 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 690
mbed_official 610:813dcc80987e 691 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 692 {
mbed_official 610:813dcc80987e 693 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 694
mbed_official 610:813dcc80987e 695 /* Update QSPI state */
mbed_official 610:813dcc80987e 696 hqspi->State = HAL_QSPI_STATE_BUSY;
mbed_official 610:813dcc80987e 697
mbed_official 610:813dcc80987e 698 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 699 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
mbed_official 610:813dcc80987e 700
mbed_official 610:813dcc80987e 701 if (status == HAL_OK)
mbed_official 610:813dcc80987e 702 {
mbed_official 610:813dcc80987e 703 if (cmd->DataMode == QSPI_DATA_NONE)
mbed_official 610:813dcc80987e 704 {
mbed_official 610:813dcc80987e 705 /* When there is no data phase, the transfer start as soon as the configuration is done
mbed_official 610:813dcc80987e 706 so activate TC and TE interrupts */
mbed_official 610:813dcc80987e 707 /* Clear interrupt */
mbed_official 610:813dcc80987e 708 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 709
mbed_official 610:813dcc80987e 710 /* Enable the QSPI Transfer Error Interrupt */
mbed_official 610:813dcc80987e 711 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
mbed_official 610:813dcc80987e 712 }
mbed_official 610:813dcc80987e 713
mbed_official 610:813dcc80987e 714 /* Call the configuration function */
mbed_official 610:813dcc80987e 715 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
mbed_official 610:813dcc80987e 716
mbed_official 610:813dcc80987e 717 if (cmd->DataMode != QSPI_DATA_NONE)
mbed_official 610:813dcc80987e 718 {
mbed_official 610:813dcc80987e 719 /* Update QSPI state */
mbed_official 610:813dcc80987e 720 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 721 }
mbed_official 610:813dcc80987e 722 }
mbed_official 610:813dcc80987e 723 }
mbed_official 610:813dcc80987e 724 else
mbed_official 610:813dcc80987e 725 {
mbed_official 610:813dcc80987e 726 status = HAL_BUSY;
mbed_official 610:813dcc80987e 727 }
mbed_official 610:813dcc80987e 728
mbed_official 610:813dcc80987e 729 /* Process unlocked */
mbed_official 610:813dcc80987e 730 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 731
mbed_official 610:813dcc80987e 732 /* Return function status */
mbed_official 610:813dcc80987e 733 return status;
mbed_official 610:813dcc80987e 734 }
mbed_official 610:813dcc80987e 735
mbed_official 610:813dcc80987e 736 /**
mbed_official 610:813dcc80987e 737 * @brief Transmit an amount of data in blocking mode.
mbed_official 610:813dcc80987e 738 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 739 * @param pData: pointer to data buffer
mbed_official 610:813dcc80987e 740 * @param Timeout : Timeout duration
mbed_official 610:813dcc80987e 741 * @note This function is used only in Indirect Write Mode
mbed_official 610:813dcc80987e 742 * @retval HAL status
mbed_official 610:813dcc80987e 743 */
mbed_official 610:813dcc80987e 744 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
mbed_official 610:813dcc80987e 745 {
mbed_official 610:813dcc80987e 746 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 747 __IO uint32_t *data_reg = &hqspi->Instance->DR;
mbed_official 610:813dcc80987e 748
mbed_official 610:813dcc80987e 749 /* Process locked */
mbed_official 610:813dcc80987e 750 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 751
mbed_official 610:813dcc80987e 752 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 753 {
mbed_official 610:813dcc80987e 754 if(pData != NULL )
mbed_official 610:813dcc80987e 755 {
mbed_official 610:813dcc80987e 756 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 757
mbed_official 610:813dcc80987e 758 /* Update state */
mbed_official 610:813dcc80987e 759 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
mbed_official 610:813dcc80987e 760
mbed_official 610:813dcc80987e 761 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 762 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 763 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 764 hqspi->pTxBuffPtr = pData;
mbed_official 610:813dcc80987e 765
mbed_official 610:813dcc80987e 766 /* Configure QSPI: CCR register with functional as indirect write */
mbed_official 610:813dcc80987e 767 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
mbed_official 610:813dcc80987e 768
mbed_official 610:813dcc80987e 769 while(hqspi->TxXferCount > 0)
mbed_official 610:813dcc80987e 770 {
mbed_official 610:813dcc80987e 771 /* Wait until FT flag is set to send data */
mbed_official 610:813dcc80987e 772 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 773 {
mbed_official 610:813dcc80987e 774 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 775 break;
mbed_official 610:813dcc80987e 776 }
mbed_official 610:813dcc80987e 777
mbed_official 610:813dcc80987e 778 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
mbed_official 610:813dcc80987e 779 hqspi->TxXferCount--;
mbed_official 610:813dcc80987e 780 }
mbed_official 610:813dcc80987e 781
mbed_official 610:813dcc80987e 782 if (status == HAL_OK)
mbed_official 610:813dcc80987e 783 {
mbed_official 610:813dcc80987e 784 /* Wait until TC flag is set to go back in idle state */
mbed_official 610:813dcc80987e 785 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 786 {
mbed_official 610:813dcc80987e 787 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 788 }
mbed_official 610:813dcc80987e 789 else
mbed_official 610:813dcc80987e 790 {
mbed_official 610:813dcc80987e 791 /* Clear Transfer Complete bit */
mbed_official 610:813dcc80987e 792 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 793
mbed_official 610:813dcc80987e 794 /* Clear Busy bit */
mbed_official 610:813dcc80987e 795 status = HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 796 }
mbed_official 610:813dcc80987e 797 }
mbed_official 610:813dcc80987e 798
mbed_official 610:813dcc80987e 799 /* Update QSPI state */
mbed_official 610:813dcc80987e 800 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 801 }
mbed_official 610:813dcc80987e 802 else
mbed_official 610:813dcc80987e 803 {
mbed_official 610:813dcc80987e 804 status = HAL_ERROR;
mbed_official 610:813dcc80987e 805 }
mbed_official 610:813dcc80987e 806 }
mbed_official 610:813dcc80987e 807 else
mbed_official 610:813dcc80987e 808 {
mbed_official 610:813dcc80987e 809 status = HAL_BUSY;
mbed_official 610:813dcc80987e 810 }
mbed_official 610:813dcc80987e 811
mbed_official 610:813dcc80987e 812 /* Process unlocked */
mbed_official 610:813dcc80987e 813 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 814
mbed_official 610:813dcc80987e 815 return status;
mbed_official 610:813dcc80987e 816 }
mbed_official 610:813dcc80987e 817
mbed_official 610:813dcc80987e 818
mbed_official 610:813dcc80987e 819 /**
mbed_official 610:813dcc80987e 820 * @brief Receive an amount of data in blocking mode.
mbed_official 610:813dcc80987e 821 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 822 * @param pData: pointer to data buffer
mbed_official 610:813dcc80987e 823 * @param Timeout : Timeout duration
mbed_official 610:813dcc80987e 824 * @note This function is used only in Indirect Read Mode
mbed_official 610:813dcc80987e 825 * @retval HAL status
mbed_official 610:813dcc80987e 826 */
mbed_official 610:813dcc80987e 827 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
mbed_official 610:813dcc80987e 828 {
mbed_official 610:813dcc80987e 829 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 830 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
mbed_official 610:813dcc80987e 831 __IO uint32_t *data_reg = &hqspi->Instance->DR;
mbed_official 610:813dcc80987e 832
mbed_official 610:813dcc80987e 833 /* Process locked */
mbed_official 610:813dcc80987e 834 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 835
mbed_official 610:813dcc80987e 836 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 837 {
mbed_official 610:813dcc80987e 838 if(pData != NULL )
mbed_official 610:813dcc80987e 839 {
mbed_official 610:813dcc80987e 840 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 841
mbed_official 610:813dcc80987e 842 /* Update state */
mbed_official 610:813dcc80987e 843 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
mbed_official 610:813dcc80987e 844
mbed_official 610:813dcc80987e 845 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 846 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 847 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 848 hqspi->pRxBuffPtr = pData;
mbed_official 610:813dcc80987e 849
mbed_official 610:813dcc80987e 850 /* Configure QSPI: CCR register with functional as indirect read */
mbed_official 610:813dcc80987e 851 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
mbed_official 610:813dcc80987e 852
mbed_official 610:813dcc80987e 853 /* Start the transfer by re-writing the address in AR register */
mbed_official 610:813dcc80987e 854 WRITE_REG(hqspi->Instance->AR, addr_reg);
mbed_official 610:813dcc80987e 855
mbed_official 610:813dcc80987e 856 while(hqspi->RxXferCount > 0)
mbed_official 610:813dcc80987e 857 {
mbed_official 610:813dcc80987e 858 /* Wait until FT or TC flag is set to read received data */
mbed_official 610:813dcc80987e 859 if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 860 {
mbed_official 610:813dcc80987e 861 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 862 break;
mbed_official 610:813dcc80987e 863 }
mbed_official 610:813dcc80987e 864
mbed_official 610:813dcc80987e 865 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
mbed_official 610:813dcc80987e 866 hqspi->RxXferCount--;
mbed_official 610:813dcc80987e 867 }
mbed_official 610:813dcc80987e 868
mbed_official 610:813dcc80987e 869 if (status == HAL_OK)
mbed_official 610:813dcc80987e 870 {
mbed_official 610:813dcc80987e 871 /* Wait until TC flag is set to go back in idle state */
mbed_official 610:813dcc80987e 872 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 873 {
mbed_official 610:813dcc80987e 874 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 875 }
mbed_official 610:813dcc80987e 876 else
mbed_official 610:813dcc80987e 877 {
mbed_official 610:813dcc80987e 878 /* Clear Transfer Complete bit */
mbed_official 610:813dcc80987e 879 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 880
mbed_official 610:813dcc80987e 881 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
mbed_official 610:813dcc80987e 882 status = HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 883 }
mbed_official 610:813dcc80987e 884 }
mbed_official 610:813dcc80987e 885
mbed_official 610:813dcc80987e 886 /* Update QSPI state */
mbed_official 610:813dcc80987e 887 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 888 }
mbed_official 610:813dcc80987e 889 else
mbed_official 610:813dcc80987e 890 {
mbed_official 610:813dcc80987e 891 status = HAL_ERROR;
mbed_official 610:813dcc80987e 892 }
mbed_official 610:813dcc80987e 893 }
mbed_official 610:813dcc80987e 894 else
mbed_official 610:813dcc80987e 895 {
mbed_official 610:813dcc80987e 896 status = HAL_BUSY;
mbed_official 610:813dcc80987e 897 }
mbed_official 610:813dcc80987e 898
mbed_official 610:813dcc80987e 899 /* Process unlocked */
mbed_official 610:813dcc80987e 900 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 901
mbed_official 610:813dcc80987e 902 return status;
mbed_official 610:813dcc80987e 903 }
mbed_official 610:813dcc80987e 904
mbed_official 610:813dcc80987e 905 /**
mbed_official 610:813dcc80987e 906 * @brief Send an amount of data in non-blocking mode with interrupt.
mbed_official 610:813dcc80987e 907 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 908 * @param pData: pointer to data buffer
mbed_official 610:813dcc80987e 909 * @note This function is used only in Indirect Write Mode
mbed_official 610:813dcc80987e 910 * @retval HAL status
mbed_official 610:813dcc80987e 911 */
mbed_official 610:813dcc80987e 912 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
mbed_official 610:813dcc80987e 913 {
mbed_official 610:813dcc80987e 914 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 915
mbed_official 610:813dcc80987e 916 /* Process locked */
mbed_official 610:813dcc80987e 917 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 918
mbed_official 610:813dcc80987e 919 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 920 {
mbed_official 610:813dcc80987e 921 if(pData != NULL )
mbed_official 610:813dcc80987e 922 {
mbed_official 610:813dcc80987e 923 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 924
mbed_official 610:813dcc80987e 925 /* Update state */
mbed_official 610:813dcc80987e 926 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
mbed_official 610:813dcc80987e 927
mbed_official 610:813dcc80987e 928 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 929 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 930 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 931 hqspi->pTxBuffPtr = pData;
mbed_official 610:813dcc80987e 932
mbed_official 610:813dcc80987e 933 /* Configure QSPI: CCR register with functional as indirect write */
mbed_official 610:813dcc80987e 934 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
mbed_official 610:813dcc80987e 935
mbed_official 610:813dcc80987e 936 /* Clear interrupt */
mbed_official 610:813dcc80987e 937 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 938
mbed_official 610:813dcc80987e 939 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
mbed_official 610:813dcc80987e 940 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
mbed_official 610:813dcc80987e 941 }
mbed_official 610:813dcc80987e 942 else
mbed_official 610:813dcc80987e 943 {
mbed_official 610:813dcc80987e 944 status = HAL_ERROR;
mbed_official 610:813dcc80987e 945 }
mbed_official 610:813dcc80987e 946 }
mbed_official 610:813dcc80987e 947 else
mbed_official 610:813dcc80987e 948 {
mbed_official 610:813dcc80987e 949 status = HAL_BUSY;
mbed_official 610:813dcc80987e 950 }
mbed_official 610:813dcc80987e 951
mbed_official 610:813dcc80987e 952 /* Process unlocked */
mbed_official 610:813dcc80987e 953 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 954
mbed_official 610:813dcc80987e 955 return status;
mbed_official 610:813dcc80987e 956 }
mbed_official 610:813dcc80987e 957
mbed_official 610:813dcc80987e 958 /**
mbed_official 610:813dcc80987e 959 * @brief Receive an amount of data in non-blocking mode with interrupt.
mbed_official 610:813dcc80987e 960 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 961 * @param pData: pointer to data buffer
mbed_official 610:813dcc80987e 962 * @note This function is used only in Indirect Read Mode
mbed_official 610:813dcc80987e 963 * @retval HAL status
mbed_official 610:813dcc80987e 964 */
mbed_official 610:813dcc80987e 965 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
mbed_official 610:813dcc80987e 966 {
mbed_official 610:813dcc80987e 967 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 968 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
mbed_official 610:813dcc80987e 969
mbed_official 610:813dcc80987e 970 /* Process locked */
mbed_official 610:813dcc80987e 971 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 972
mbed_official 610:813dcc80987e 973 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 974 {
mbed_official 610:813dcc80987e 975 if(pData != NULL )
mbed_official 610:813dcc80987e 976 {
mbed_official 610:813dcc80987e 977 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 978
mbed_official 610:813dcc80987e 979 /* Update state */
mbed_official 610:813dcc80987e 980 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
mbed_official 610:813dcc80987e 981
mbed_official 610:813dcc80987e 982 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 983 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 984 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 985 hqspi->pRxBuffPtr = pData;
mbed_official 610:813dcc80987e 986
mbed_official 610:813dcc80987e 987 /* Configure QSPI: CCR register with functional as indirect read */
mbed_official 610:813dcc80987e 988 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
mbed_official 610:813dcc80987e 989
mbed_official 610:813dcc80987e 990 /* Start the transfer by re-writing the address in AR register */
mbed_official 610:813dcc80987e 991 WRITE_REG(hqspi->Instance->AR, addr_reg);
mbed_official 610:813dcc80987e 992
mbed_official 610:813dcc80987e 993 /* Clear interrupt */
mbed_official 610:813dcc80987e 994 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 995
mbed_official 610:813dcc80987e 996 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
mbed_official 610:813dcc80987e 997 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
mbed_official 610:813dcc80987e 998 }
mbed_official 610:813dcc80987e 999 else
mbed_official 610:813dcc80987e 1000 {
mbed_official 610:813dcc80987e 1001 status = HAL_ERROR;
mbed_official 610:813dcc80987e 1002 }
mbed_official 610:813dcc80987e 1003 }
mbed_official 610:813dcc80987e 1004 else
mbed_official 610:813dcc80987e 1005 {
mbed_official 610:813dcc80987e 1006 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1007 }
mbed_official 610:813dcc80987e 1008
mbed_official 610:813dcc80987e 1009 /* Process unlocked */
mbed_official 610:813dcc80987e 1010 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1011
mbed_official 610:813dcc80987e 1012 return status;
mbed_official 610:813dcc80987e 1013 }
mbed_official 610:813dcc80987e 1014
mbed_official 610:813dcc80987e 1015 /**
mbed_official 610:813dcc80987e 1016 * @brief Send an amount of data in non-blocking mode with DMA.
mbed_official 610:813dcc80987e 1017 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1018 * @param pData: pointer to data buffer
mbed_official 610:813dcc80987e 1019 * @note This function is used only in Indirect Write Mode
mbed_official 610:813dcc80987e 1020 * @retval HAL status
mbed_official 610:813dcc80987e 1021 */
mbed_official 610:813dcc80987e 1022 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
mbed_official 610:813dcc80987e 1023 {
mbed_official 610:813dcc80987e 1024 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 1025 uint32_t *tmp;
mbed_official 610:813dcc80987e 1026
mbed_official 610:813dcc80987e 1027 /* Process locked */
mbed_official 610:813dcc80987e 1028 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 1029
mbed_official 610:813dcc80987e 1030 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 1031 {
mbed_official 610:813dcc80987e 1032 if(pData != NULL )
mbed_official 610:813dcc80987e 1033 {
mbed_official 610:813dcc80987e 1034 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 1035
mbed_official 610:813dcc80987e 1036 /* Update state */
mbed_official 610:813dcc80987e 1037 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
mbed_official 610:813dcc80987e 1038
mbed_official 610:813dcc80987e 1039 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 1040 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 1041 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 1042 hqspi->pTxBuffPtr = pData;
mbed_official 610:813dcc80987e 1043
mbed_official 610:813dcc80987e 1044 /* Configure QSPI: CCR register with functional mode as indirect write */
mbed_official 610:813dcc80987e 1045 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
mbed_official 610:813dcc80987e 1046
mbed_official 610:813dcc80987e 1047 /* Set the QSPI DMA transfer complete callback */
mbed_official 610:813dcc80987e 1048 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
mbed_official 610:813dcc80987e 1049
mbed_official 610:813dcc80987e 1050 /* Set the QSPI DMA Half transfer complete callback */
mbed_official 610:813dcc80987e 1051 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
mbed_official 610:813dcc80987e 1052
mbed_official 610:813dcc80987e 1053 /* Set the DMA error callback */
mbed_official 610:813dcc80987e 1054 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
mbed_official 610:813dcc80987e 1055
mbed_official 610:813dcc80987e 1056 /* Configure the direction of the DMA */
mbed_official 610:813dcc80987e 1057 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
mbed_official 610:813dcc80987e 1058 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
mbed_official 610:813dcc80987e 1059
mbed_official 610:813dcc80987e 1060 /* Enable the QSPI transmit DMA Channel */
mbed_official 610:813dcc80987e 1061 tmp = (uint32_t*)&pData;
mbed_official 610:813dcc80987e 1062 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
mbed_official 610:813dcc80987e 1063
mbed_official 610:813dcc80987e 1064 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
mbed_official 610:813dcc80987e 1065 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
mbed_official 610:813dcc80987e 1066 }
mbed_official 610:813dcc80987e 1067 else
mbed_official 610:813dcc80987e 1068 {
mbed_official 610:813dcc80987e 1069 status = HAL_OK;
mbed_official 610:813dcc80987e 1070 }
mbed_official 610:813dcc80987e 1071 }
mbed_official 610:813dcc80987e 1072 else
mbed_official 610:813dcc80987e 1073 {
mbed_official 610:813dcc80987e 1074 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1075 }
mbed_official 610:813dcc80987e 1076
mbed_official 610:813dcc80987e 1077 /* Process unlocked */
mbed_official 610:813dcc80987e 1078 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1079
mbed_official 610:813dcc80987e 1080 return status;
mbed_official 610:813dcc80987e 1081 }
mbed_official 610:813dcc80987e 1082
mbed_official 610:813dcc80987e 1083 /**
mbed_official 610:813dcc80987e 1084 * @brief Receive an amount of data in non-blocking mode with DMA.
mbed_official 610:813dcc80987e 1085 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1086 * @param pData: pointer to data buffer.
mbed_official 610:813dcc80987e 1087 * @note This function is used only in Indirect Read Mode
mbed_official 610:813dcc80987e 1088 * @retval HAL status
mbed_official 610:813dcc80987e 1089 */
mbed_official 610:813dcc80987e 1090 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
mbed_official 610:813dcc80987e 1091 {
mbed_official 610:813dcc80987e 1092 HAL_StatusTypeDef status = HAL_OK;
mbed_official 610:813dcc80987e 1093 uint32_t *tmp;
mbed_official 610:813dcc80987e 1094 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
mbed_official 610:813dcc80987e 1095
mbed_official 610:813dcc80987e 1096 /* Process locked */
mbed_official 610:813dcc80987e 1097 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 1098
mbed_official 610:813dcc80987e 1099 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 1100 {
mbed_official 610:813dcc80987e 1101 if(pData != NULL )
mbed_official 610:813dcc80987e 1102 {
mbed_official 610:813dcc80987e 1103 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 1104
mbed_official 610:813dcc80987e 1105 /* Update state */
mbed_official 610:813dcc80987e 1106 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
mbed_official 610:813dcc80987e 1107
mbed_official 610:813dcc80987e 1108 /* Configure counters and size of the handle */
mbed_official 610:813dcc80987e 1109 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 1110 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
mbed_official 610:813dcc80987e 1111 hqspi->pRxBuffPtr = pData;
mbed_official 610:813dcc80987e 1112
mbed_official 610:813dcc80987e 1113 /* Set the QSPI DMA transfer complete callback */
mbed_official 610:813dcc80987e 1114 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
mbed_official 610:813dcc80987e 1115
mbed_official 610:813dcc80987e 1116 /* Set the QSPI DMA Half transfer complete callback */
mbed_official 610:813dcc80987e 1117 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
mbed_official 610:813dcc80987e 1118
mbed_official 610:813dcc80987e 1119 /* Set the DMA error callback */
mbed_official 610:813dcc80987e 1120 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
mbed_official 610:813dcc80987e 1121
mbed_official 610:813dcc80987e 1122 /* Configure the direction of the DMA */
mbed_official 610:813dcc80987e 1123 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
mbed_official 610:813dcc80987e 1124 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
mbed_official 610:813dcc80987e 1125
mbed_official 610:813dcc80987e 1126 /* Enable the DMA Channel */
mbed_official 610:813dcc80987e 1127 tmp = (uint32_t*)&pData;
mbed_official 610:813dcc80987e 1128 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
mbed_official 610:813dcc80987e 1129
mbed_official 610:813dcc80987e 1130 /* Configure QSPI: CCR register with functional as indirect read */
mbed_official 610:813dcc80987e 1131 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
mbed_official 610:813dcc80987e 1132
mbed_official 610:813dcc80987e 1133 /* Start the transfer by re-writing the address in AR register */
mbed_official 610:813dcc80987e 1134 WRITE_REG(hqspi->Instance->AR, addr_reg);
mbed_official 610:813dcc80987e 1135
mbed_official 610:813dcc80987e 1136 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
mbed_official 610:813dcc80987e 1137 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
mbed_official 610:813dcc80987e 1138 }
mbed_official 610:813dcc80987e 1139 else
mbed_official 610:813dcc80987e 1140 {
mbed_official 610:813dcc80987e 1141 status = HAL_ERROR;
mbed_official 610:813dcc80987e 1142 }
mbed_official 610:813dcc80987e 1143 }
mbed_official 610:813dcc80987e 1144 else
mbed_official 610:813dcc80987e 1145 {
mbed_official 610:813dcc80987e 1146 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1147 }
mbed_official 610:813dcc80987e 1148
mbed_official 610:813dcc80987e 1149 /* Process unlocked */
mbed_official 610:813dcc80987e 1150 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1151
mbed_official 610:813dcc80987e 1152 return status;
mbed_official 610:813dcc80987e 1153 }
mbed_official 610:813dcc80987e 1154
mbed_official 610:813dcc80987e 1155 /**
mbed_official 610:813dcc80987e 1156 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
mbed_official 610:813dcc80987e 1157 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1158 * @param cmd: structure that contains the command configuration information.
mbed_official 610:813dcc80987e 1159 * @param cfg: structure that contains the polling configuration information.
mbed_official 610:813dcc80987e 1160 * @param Timeout : Timeout duration
mbed_official 610:813dcc80987e 1161 * @note This function is used only in Automatic Polling Mode
mbed_official 610:813dcc80987e 1162 * @retval HAL status
mbed_official 610:813dcc80987e 1163 */
mbed_official 610:813dcc80987e 1164 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
mbed_official 610:813dcc80987e 1165 {
mbed_official 610:813dcc80987e 1166 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 1167
mbed_official 610:813dcc80987e 1168 /* Check the parameters */
mbed_official 610:813dcc80987e 1169 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
mbed_official 610:813dcc80987e 1170 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 1171 {
mbed_official 610:813dcc80987e 1172 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
mbed_official 610:813dcc80987e 1173 }
mbed_official 610:813dcc80987e 1174
mbed_official 610:813dcc80987e 1175 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
mbed_official 610:813dcc80987e 1176 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1177 {
mbed_official 610:813dcc80987e 1178 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
mbed_official 610:813dcc80987e 1179 }
mbed_official 610:813dcc80987e 1180
mbed_official 610:813dcc80987e 1181 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
mbed_official 610:813dcc80987e 1182 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 1183 {
mbed_official 610:813dcc80987e 1184 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
mbed_official 610:813dcc80987e 1185 }
mbed_official 610:813dcc80987e 1186
mbed_official 610:813dcc80987e 1187 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
mbed_official 610:813dcc80987e 1188 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official 610:813dcc80987e 1189
mbed_official 610:813dcc80987e 1190 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
mbed_official 610:813dcc80987e 1191 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
mbed_official 610:813dcc80987e 1192 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official 610:813dcc80987e 1193
mbed_official 610:813dcc80987e 1194 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
mbed_official 610:813dcc80987e 1195 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
mbed_official 610:813dcc80987e 1196 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
mbed_official 610:813dcc80987e 1197
mbed_official 610:813dcc80987e 1198 /* Process locked */
mbed_official 610:813dcc80987e 1199 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 1200
mbed_official 610:813dcc80987e 1201 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 1202 {
mbed_official 610:813dcc80987e 1203 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 1204
mbed_official 610:813dcc80987e 1205 /* Update state */
mbed_official 610:813dcc80987e 1206 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
mbed_official 610:813dcc80987e 1207
mbed_official 610:813dcc80987e 1208 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 1209 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
mbed_official 610:813dcc80987e 1210
mbed_official 610:813dcc80987e 1211 if (status == HAL_OK)
mbed_official 610:813dcc80987e 1212 {
mbed_official 610:813dcc80987e 1213 /* Configure QSPI: PSMAR register with the status match value */
mbed_official 610:813dcc80987e 1214 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
mbed_official 610:813dcc80987e 1215
mbed_official 610:813dcc80987e 1216 /* Configure QSPI: PSMKR register with the status mask value */
mbed_official 610:813dcc80987e 1217 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
mbed_official 610:813dcc80987e 1218
mbed_official 610:813dcc80987e 1219 /* Configure QSPI: PIR register with the interval value */
mbed_official 610:813dcc80987e 1220 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
mbed_official 610:813dcc80987e 1221
mbed_official 610:813dcc80987e 1222 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
mbed_official 610:813dcc80987e 1223 (otherwise there will be an infinite loop in blocking mode) */
mbed_official 610:813dcc80987e 1224 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
mbed_official 610:813dcc80987e 1225 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
mbed_official 610:813dcc80987e 1226
mbed_official 610:813dcc80987e 1227 /* Call the configuration function */
mbed_official 610:813dcc80987e 1228 cmd->NbData = cfg->StatusBytesSize;
mbed_official 610:813dcc80987e 1229 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
mbed_official 610:813dcc80987e 1230
mbed_official 610:813dcc80987e 1231 /* Wait until SM flag is set to go back in idle state */
mbed_official 610:813dcc80987e 1232 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 1233 {
mbed_official 610:813dcc80987e 1234 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 1235 }
mbed_official 610:813dcc80987e 1236 else
mbed_official 610:813dcc80987e 1237 {
mbed_official 610:813dcc80987e 1238 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
mbed_official 610:813dcc80987e 1239
mbed_official 610:813dcc80987e 1240 /* Update state */
mbed_official 610:813dcc80987e 1241 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 1242 }
mbed_official 610:813dcc80987e 1243 }
mbed_official 610:813dcc80987e 1244 }
mbed_official 610:813dcc80987e 1245 else
mbed_official 610:813dcc80987e 1246 {
mbed_official 610:813dcc80987e 1247 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1248 }
mbed_official 610:813dcc80987e 1249
mbed_official 610:813dcc80987e 1250 /* Process unlocked */
mbed_official 610:813dcc80987e 1251 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1252
mbed_official 610:813dcc80987e 1253 /* Return function status */
mbed_official 610:813dcc80987e 1254 return status;
mbed_official 610:813dcc80987e 1255 }
mbed_official 610:813dcc80987e 1256
mbed_official 610:813dcc80987e 1257 /**
mbed_official 610:813dcc80987e 1258 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
mbed_official 610:813dcc80987e 1259 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1260 * @param cmd: structure that contains the command configuration information.
mbed_official 610:813dcc80987e 1261 * @param cfg: structure that contains the polling configuration information.
mbed_official 610:813dcc80987e 1262 * @note This function is used only in Automatic Polling Mode
mbed_official 610:813dcc80987e 1263 * @retval HAL status
mbed_official 610:813dcc80987e 1264 */
mbed_official 610:813dcc80987e 1265 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
mbed_official 610:813dcc80987e 1266 {
mbed_official 610:813dcc80987e 1267 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 1268
mbed_official 610:813dcc80987e 1269 /* Check the parameters */
mbed_official 610:813dcc80987e 1270 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
mbed_official 610:813dcc80987e 1271 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 1272 {
mbed_official 610:813dcc80987e 1273 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
mbed_official 610:813dcc80987e 1274 }
mbed_official 610:813dcc80987e 1275
mbed_official 610:813dcc80987e 1276 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
mbed_official 610:813dcc80987e 1277 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1278 {
mbed_official 610:813dcc80987e 1279 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
mbed_official 610:813dcc80987e 1280 }
mbed_official 610:813dcc80987e 1281
mbed_official 610:813dcc80987e 1282 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
mbed_official 610:813dcc80987e 1283 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 1284 {
mbed_official 610:813dcc80987e 1285 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
mbed_official 610:813dcc80987e 1286 }
mbed_official 610:813dcc80987e 1287
mbed_official 610:813dcc80987e 1288 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
mbed_official 610:813dcc80987e 1289 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official 610:813dcc80987e 1290
mbed_official 610:813dcc80987e 1291 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
mbed_official 610:813dcc80987e 1292 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
mbed_official 610:813dcc80987e 1293 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official 610:813dcc80987e 1294
mbed_official 610:813dcc80987e 1295 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
mbed_official 610:813dcc80987e 1296 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
mbed_official 610:813dcc80987e 1297 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
mbed_official 610:813dcc80987e 1298 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
mbed_official 610:813dcc80987e 1299
mbed_official 610:813dcc80987e 1300 /* Process locked */
mbed_official 610:813dcc80987e 1301 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 1302
mbed_official 610:813dcc80987e 1303 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 1304 {
mbed_official 610:813dcc80987e 1305 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 1306
mbed_official 610:813dcc80987e 1307 /* Update state */
mbed_official 610:813dcc80987e 1308 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
mbed_official 610:813dcc80987e 1309
mbed_official 610:813dcc80987e 1310 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 1311 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
mbed_official 610:813dcc80987e 1312
mbed_official 610:813dcc80987e 1313 if (status == HAL_OK)
mbed_official 610:813dcc80987e 1314 {
mbed_official 610:813dcc80987e 1315 /* Configure QSPI: PSMAR register with the status match value */
mbed_official 610:813dcc80987e 1316 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
mbed_official 610:813dcc80987e 1317
mbed_official 610:813dcc80987e 1318 /* Configure QSPI: PSMKR register with the status mask value */
mbed_official 610:813dcc80987e 1319 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
mbed_official 610:813dcc80987e 1320
mbed_official 610:813dcc80987e 1321 /* Configure QSPI: PIR register with the interval value */
mbed_official 610:813dcc80987e 1322 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
mbed_official 610:813dcc80987e 1323
mbed_official 610:813dcc80987e 1324 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
mbed_official 610:813dcc80987e 1325 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
mbed_official 610:813dcc80987e 1326 (cfg->MatchMode | cfg->AutomaticStop));
mbed_official 610:813dcc80987e 1327
mbed_official 610:813dcc80987e 1328 /* Call the configuration function */
mbed_official 610:813dcc80987e 1329 cmd->NbData = cfg->StatusBytesSize;
mbed_official 610:813dcc80987e 1330 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
mbed_official 610:813dcc80987e 1331
mbed_official 610:813dcc80987e 1332 /* Clear interrupt */
mbed_official 610:813dcc80987e 1333 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
mbed_official 610:813dcc80987e 1334
mbed_official 610:813dcc80987e 1335 /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
mbed_official 610:813dcc80987e 1336 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));
mbed_official 610:813dcc80987e 1337 }
mbed_official 610:813dcc80987e 1338 }
mbed_official 610:813dcc80987e 1339 else
mbed_official 610:813dcc80987e 1340 {
mbed_official 610:813dcc80987e 1341 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1342 }
mbed_official 610:813dcc80987e 1343
mbed_official 610:813dcc80987e 1344 /* Process unlocked */
mbed_official 610:813dcc80987e 1345 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1346
mbed_official 610:813dcc80987e 1347 /* Return function status */
mbed_official 610:813dcc80987e 1348 return status;
mbed_official 610:813dcc80987e 1349 }
mbed_official 610:813dcc80987e 1350
mbed_official 610:813dcc80987e 1351 /**
mbed_official 610:813dcc80987e 1352 * @brief Configure the Memory Mapped mode.
mbed_official 610:813dcc80987e 1353 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1354 * @param cmd: structure that contains the command configuration information.
mbed_official 610:813dcc80987e 1355 * @param cfg: structure that contains the memory mapped configuration information.
mbed_official 610:813dcc80987e 1356 * @note This function is used only in Memory mapped Mode
mbed_official 610:813dcc80987e 1357 * @retval HAL status
mbed_official 610:813dcc80987e 1358 */
mbed_official 610:813dcc80987e 1359 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
mbed_official 610:813dcc80987e 1360 {
mbed_official 610:813dcc80987e 1361 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 1362
mbed_official 610:813dcc80987e 1363 /* Check the parameters */
mbed_official 610:813dcc80987e 1364 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
mbed_official 610:813dcc80987e 1365 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 1366 {
mbed_official 610:813dcc80987e 1367 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
mbed_official 610:813dcc80987e 1368 }
mbed_official 610:813dcc80987e 1369
mbed_official 610:813dcc80987e 1370 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
mbed_official 610:813dcc80987e 1371 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1372 {
mbed_official 610:813dcc80987e 1373 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
mbed_official 610:813dcc80987e 1374 }
mbed_official 610:813dcc80987e 1375
mbed_official 610:813dcc80987e 1376 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
mbed_official 610:813dcc80987e 1377 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 1378 {
mbed_official 610:813dcc80987e 1379 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
mbed_official 610:813dcc80987e 1380 }
mbed_official 610:813dcc80987e 1381
mbed_official 610:813dcc80987e 1382 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
mbed_official 610:813dcc80987e 1383 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official 610:813dcc80987e 1384
mbed_official 610:813dcc80987e 1385 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
mbed_official 610:813dcc80987e 1386 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
mbed_official 610:813dcc80987e 1387 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official 610:813dcc80987e 1388
mbed_official 610:813dcc80987e 1389 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
mbed_official 610:813dcc80987e 1390
mbed_official 610:813dcc80987e 1391 /* Process locked */
mbed_official 610:813dcc80987e 1392 __HAL_LOCK(hqspi);
mbed_official 610:813dcc80987e 1393
mbed_official 610:813dcc80987e 1394 if(hqspi->State == HAL_QSPI_STATE_READY)
mbed_official 610:813dcc80987e 1395 {
mbed_official 610:813dcc80987e 1396 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
mbed_official 610:813dcc80987e 1397
mbed_official 610:813dcc80987e 1398 /* Update state */
mbed_official 610:813dcc80987e 1399 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
mbed_official 610:813dcc80987e 1400
mbed_official 610:813dcc80987e 1401 /* Wait till BUSY flag reset */
mbed_official 610:813dcc80987e 1402 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
mbed_official 610:813dcc80987e 1403
mbed_official 610:813dcc80987e 1404 if (status == HAL_OK)
mbed_official 610:813dcc80987e 1405 {
mbed_official 610:813dcc80987e 1406 /* Configure QSPI: CR register with timeout counter enable */
mbed_official 610:813dcc80987e 1407 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
mbed_official 610:813dcc80987e 1408
mbed_official 610:813dcc80987e 1409 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
mbed_official 610:813dcc80987e 1410 {
mbed_official 610:813dcc80987e 1411 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
mbed_official 610:813dcc80987e 1412
mbed_official 610:813dcc80987e 1413 /* Configure QSPI: LPTR register with the low-power timeout value */
mbed_official 610:813dcc80987e 1414 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
mbed_official 610:813dcc80987e 1415
mbed_official 610:813dcc80987e 1416 /* Clear interrupt */
mbed_official 610:813dcc80987e 1417 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
mbed_official 610:813dcc80987e 1418
mbed_official 610:813dcc80987e 1419 /* Enable the QSPI TimeOut Interrupt */
mbed_official 610:813dcc80987e 1420 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
mbed_official 610:813dcc80987e 1421 }
mbed_official 610:813dcc80987e 1422
mbed_official 610:813dcc80987e 1423 /* Call the configuration function */
mbed_official 610:813dcc80987e 1424 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
mbed_official 610:813dcc80987e 1425 }
mbed_official 610:813dcc80987e 1426 }
mbed_official 610:813dcc80987e 1427 else
mbed_official 610:813dcc80987e 1428 {
mbed_official 610:813dcc80987e 1429 status = HAL_BUSY;
mbed_official 610:813dcc80987e 1430 }
mbed_official 610:813dcc80987e 1431
mbed_official 610:813dcc80987e 1432 /* Process unlocked */
mbed_official 610:813dcc80987e 1433 __HAL_UNLOCK(hqspi);
mbed_official 610:813dcc80987e 1434
mbed_official 610:813dcc80987e 1435 /* Return function status */
mbed_official 610:813dcc80987e 1436 return status;
mbed_official 610:813dcc80987e 1437 }
mbed_official 610:813dcc80987e 1438
mbed_official 610:813dcc80987e 1439 /**
mbed_official 610:813dcc80987e 1440 * @brief Transfer Error callback.
mbed_official 610:813dcc80987e 1441 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1442 * @retval None
mbed_official 610:813dcc80987e 1443 */
mbed_official 610:813dcc80987e 1444 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1445 {
mbed_official 610:813dcc80987e 1446 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1447 the HAL_QSPI_ErrorCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1448 */
mbed_official 610:813dcc80987e 1449 }
mbed_official 610:813dcc80987e 1450
mbed_official 610:813dcc80987e 1451 /**
mbed_official 610:813dcc80987e 1452 * @brief Command completed callback.
mbed_official 610:813dcc80987e 1453 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1454 * @retval None
mbed_official 610:813dcc80987e 1455 */
mbed_official 610:813dcc80987e 1456 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1457 {
mbed_official 610:813dcc80987e 1458 /* NOTE: This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1459 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1460 */
mbed_official 610:813dcc80987e 1461 }
mbed_official 610:813dcc80987e 1462
mbed_official 610:813dcc80987e 1463 /**
mbed_official 610:813dcc80987e 1464 * @brief Rx Transfer completed callback.
mbed_official 610:813dcc80987e 1465 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1466 * @retval None
mbed_official 610:813dcc80987e 1467 */
mbed_official 610:813dcc80987e 1468 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1469 {
mbed_official 610:813dcc80987e 1470 /* NOTE: This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1471 the HAL_QSPI_RxCpltCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1472 */
mbed_official 610:813dcc80987e 1473 }
mbed_official 610:813dcc80987e 1474
mbed_official 610:813dcc80987e 1475 /**
mbed_official 610:813dcc80987e 1476 * @brief Tx Transfer completed callback.
mbed_official 610:813dcc80987e 1477 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1478 * @retval None
mbed_official 610:813dcc80987e 1479 */
mbed_official 610:813dcc80987e 1480 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1481 {
mbed_official 610:813dcc80987e 1482 /* NOTE: This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1483 the HAL_QSPI_TxCpltCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1484 */
mbed_official 610:813dcc80987e 1485 }
mbed_official 610:813dcc80987e 1486
mbed_official 610:813dcc80987e 1487 /**
mbed_official 610:813dcc80987e 1488 * @brief Rx Half Transfer completed callback.
mbed_official 610:813dcc80987e 1489 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1490 * @retval None
mbed_official 610:813dcc80987e 1491 */
mbed_official 610:813dcc80987e 1492 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1493 {
mbed_official 610:813dcc80987e 1494 /* NOTE: This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1495 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1496 */
mbed_official 610:813dcc80987e 1497 }
mbed_official 610:813dcc80987e 1498
mbed_official 610:813dcc80987e 1499 /**
mbed_official 610:813dcc80987e 1500 * @brief Tx Half Transfer completed callback.
mbed_official 610:813dcc80987e 1501 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1502 * @retval None
mbed_official 610:813dcc80987e 1503 */
mbed_official 610:813dcc80987e 1504 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1505 {
mbed_official 610:813dcc80987e 1506 /* NOTE: This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1507 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1508 */
mbed_official 610:813dcc80987e 1509 }
mbed_official 610:813dcc80987e 1510
mbed_official 610:813dcc80987e 1511 /**
mbed_official 610:813dcc80987e 1512 * @brief FIFO Threshold callback.
mbed_official 610:813dcc80987e 1513 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1514 * @retval None
mbed_official 610:813dcc80987e 1515 */
mbed_official 610:813dcc80987e 1516 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1517 {
mbed_official 610:813dcc80987e 1518 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1519 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1520 */
mbed_official 610:813dcc80987e 1521 }
mbed_official 610:813dcc80987e 1522
mbed_official 610:813dcc80987e 1523 /**
mbed_official 610:813dcc80987e 1524 * @brief Status Match callback.
mbed_official 610:813dcc80987e 1525 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1526 * @retval None
mbed_official 610:813dcc80987e 1527 */
mbed_official 610:813dcc80987e 1528 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1529 {
mbed_official 610:813dcc80987e 1530 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1531 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1532 */
mbed_official 610:813dcc80987e 1533 }
mbed_official 610:813dcc80987e 1534
mbed_official 610:813dcc80987e 1535 /**
mbed_official 610:813dcc80987e 1536 * @brief Timeout callback.
mbed_official 610:813dcc80987e 1537 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1538 * @retval None
mbed_official 610:813dcc80987e 1539 */
mbed_official 610:813dcc80987e 1540 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1541 {
mbed_official 610:813dcc80987e 1542 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 610:813dcc80987e 1543 the HAL_QSPI_TimeOutCallback could be implemented in the user file
mbed_official 610:813dcc80987e 1544 */
mbed_official 610:813dcc80987e 1545 }
mbed_official 610:813dcc80987e 1546
mbed_official 610:813dcc80987e 1547 /**
mbed_official 610:813dcc80987e 1548 * @}
mbed_official 610:813dcc80987e 1549 */
mbed_official 610:813dcc80987e 1550
mbed_official 610:813dcc80987e 1551 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
mbed_official 610:813dcc80987e 1552 * @brief QSPI control and State functions
mbed_official 610:813dcc80987e 1553 *
mbed_official 610:813dcc80987e 1554 @verbatim
mbed_official 610:813dcc80987e 1555 ===============================================================================
mbed_official 610:813dcc80987e 1556 ##### Peripheral Control and State functions #####
mbed_official 610:813dcc80987e 1557 ===============================================================================
mbed_official 610:813dcc80987e 1558 [..]
mbed_official 610:813dcc80987e 1559 This subsection provides a set of functions allowing to :
mbed_official 610:813dcc80987e 1560 (+) Check in run-time the state of the driver.
mbed_official 610:813dcc80987e 1561 (+) Check the error code set during last operation.
mbed_official 610:813dcc80987e 1562 (+) Abort any operation.
mbed_official 610:813dcc80987e 1563
mbed_official 610:813dcc80987e 1564
mbed_official 610:813dcc80987e 1565 @endverbatim
mbed_official 610:813dcc80987e 1566 * @{
mbed_official 610:813dcc80987e 1567 */
mbed_official 610:813dcc80987e 1568
mbed_official 610:813dcc80987e 1569 /**
mbed_official 610:813dcc80987e 1570 * @brief Return the QSPI handle state.
mbed_official 610:813dcc80987e 1571 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1572 * @retval HAL state
mbed_official 610:813dcc80987e 1573 */
mbed_official 610:813dcc80987e 1574 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1575 {
mbed_official 610:813dcc80987e 1576 /* Return QSPI handle state */
mbed_official 610:813dcc80987e 1577 return hqspi->State;
mbed_official 610:813dcc80987e 1578 }
mbed_official 610:813dcc80987e 1579
mbed_official 610:813dcc80987e 1580 /**
mbed_official 610:813dcc80987e 1581 * @brief Return the QSPI error code.
mbed_official 610:813dcc80987e 1582 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1583 * @retval QSPI Error Code
mbed_official 610:813dcc80987e 1584 */
mbed_official 610:813dcc80987e 1585 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1586 {
mbed_official 610:813dcc80987e 1587 return hqspi->ErrorCode;
mbed_official 610:813dcc80987e 1588 }
mbed_official 610:813dcc80987e 1589
mbed_official 610:813dcc80987e 1590 /**
mbed_official 610:813dcc80987e 1591 * @brief Abort the current transmission.
mbed_official 610:813dcc80987e 1592 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1593 * @retval HAL status
mbed_official 610:813dcc80987e 1594 */
mbed_official 610:813dcc80987e 1595 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
mbed_official 610:813dcc80987e 1596 {
mbed_official 610:813dcc80987e 1597 HAL_StatusTypeDef status = HAL_ERROR;
mbed_official 610:813dcc80987e 1598
mbed_official 610:813dcc80987e 1599 /* Configure QSPI: CR register with Abort request */
mbed_official 610:813dcc80987e 1600 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
mbed_official 610:813dcc80987e 1601
mbed_official 610:813dcc80987e 1602 /* Wait until TC flag is set to go back in idle state */
mbed_official 610:813dcc80987e 1603 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 1604 {
mbed_official 610:813dcc80987e 1605 status = HAL_TIMEOUT;
mbed_official 610:813dcc80987e 1606 }
mbed_official 610:813dcc80987e 1607 else
mbed_official 610:813dcc80987e 1608 {
mbed_official 610:813dcc80987e 1609 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 1610
mbed_official 610:813dcc80987e 1611 /* Wait until BUSY flag is reset */
mbed_official 610:813dcc80987e 1612 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
mbed_official 610:813dcc80987e 1613
mbed_official 610:813dcc80987e 1614 /* Update state */
mbed_official 610:813dcc80987e 1615 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 1616 }
mbed_official 610:813dcc80987e 1617
mbed_official 610:813dcc80987e 1618 return status;
mbed_official 610:813dcc80987e 1619 }
mbed_official 610:813dcc80987e 1620
mbed_official 610:813dcc80987e 1621 /** @brief Set QSPI timeout.
mbed_official 610:813dcc80987e 1622 * @param hqspi: QSPI handle.
mbed_official 610:813dcc80987e 1623 * @param Timeout: Timeout for the QSPI memory access.
mbed_official 610:813dcc80987e 1624 * @retval None
mbed_official 610:813dcc80987e 1625 */
mbed_official 610:813dcc80987e 1626 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
mbed_official 610:813dcc80987e 1627 {
mbed_official 610:813dcc80987e 1628 hqspi->Timeout = Timeout;
mbed_official 610:813dcc80987e 1629 }
mbed_official 610:813dcc80987e 1630
mbed_official 610:813dcc80987e 1631 /**
mbed_official 610:813dcc80987e 1632 * @}
mbed_official 610:813dcc80987e 1633 */
mbed_official 610:813dcc80987e 1634
mbed_official 610:813dcc80987e 1635 /**
mbed_official 610:813dcc80987e 1636 * @brief DMA QSPI receive process complete callback.
mbed_official 610:813dcc80987e 1637 * @param hdma: DMA handle
mbed_official 610:813dcc80987e 1638 * @retval None
mbed_official 610:813dcc80987e 1639 */
mbed_official 610:813dcc80987e 1640 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
mbed_official 610:813dcc80987e 1641 {
mbed_official 610:813dcc80987e 1642 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 610:813dcc80987e 1643 hqspi->RxXferCount = 0;
mbed_official 610:813dcc80987e 1644
mbed_official 610:813dcc80987e 1645 /* Wait for QSPI TC Flag */
mbed_official 610:813dcc80987e 1646 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 1647 {
mbed_official 610:813dcc80987e 1648 /* Timeout occurred */
mbed_official 610:813dcc80987e 1649 HAL_QSPI_ErrorCallback(hqspi);
mbed_official 610:813dcc80987e 1650 }
mbed_official 610:813dcc80987e 1651 else
mbed_official 610:813dcc80987e 1652 {
mbed_official 610:813dcc80987e 1653 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
mbed_official 610:813dcc80987e 1654 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
mbed_official 610:813dcc80987e 1655
mbed_official 610:813dcc80987e 1656 /* Disable the DMA channel */
mbed_official 610:813dcc80987e 1657 HAL_DMA_Abort(hdma);
mbed_official 610:813dcc80987e 1658
mbed_official 610:813dcc80987e 1659 /* Clear Transfer Complete bit */
mbed_official 610:813dcc80987e 1660 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 1661
mbed_official 610:813dcc80987e 1662 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
mbed_official 610:813dcc80987e 1663 HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 1664
mbed_official 610:813dcc80987e 1665 /* Update state */
mbed_official 610:813dcc80987e 1666 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 1667
mbed_official 610:813dcc80987e 1668 HAL_QSPI_RxCpltCallback(hqspi);
mbed_official 610:813dcc80987e 1669 }
mbed_official 610:813dcc80987e 1670 }
mbed_official 610:813dcc80987e 1671
mbed_official 610:813dcc80987e 1672 /**
mbed_official 610:813dcc80987e 1673 * @brief DMA QSPI transmit process complete callback.
mbed_official 610:813dcc80987e 1674 * @param hdma: DMA handle
mbed_official 610:813dcc80987e 1675 * @retval None
mbed_official 610:813dcc80987e 1676 */
mbed_official 610:813dcc80987e 1677 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
mbed_official 610:813dcc80987e 1678 {
mbed_official 610:813dcc80987e 1679 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 610:813dcc80987e 1680 hqspi->TxXferCount = 0;
mbed_official 610:813dcc80987e 1681
mbed_official 610:813dcc80987e 1682 /* Wait for QSPI TC Flag */
mbed_official 610:813dcc80987e 1683 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
mbed_official 610:813dcc80987e 1684 {
mbed_official 610:813dcc80987e 1685 /* Timeout occurred */
mbed_official 610:813dcc80987e 1686 HAL_QSPI_ErrorCallback(hqspi);
mbed_official 610:813dcc80987e 1687 }
mbed_official 610:813dcc80987e 1688 else
mbed_official 610:813dcc80987e 1689 {
mbed_official 610:813dcc80987e 1690 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
mbed_official 610:813dcc80987e 1691 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
mbed_official 610:813dcc80987e 1692
mbed_official 610:813dcc80987e 1693 /* Disable the DMA channel */
mbed_official 610:813dcc80987e 1694 HAL_DMA_Abort(hdma);
mbed_official 610:813dcc80987e 1695
mbed_official 610:813dcc80987e 1696 /* Clear Transfer Complete bit */
mbed_official 610:813dcc80987e 1697 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
mbed_official 610:813dcc80987e 1698
mbed_official 610:813dcc80987e 1699 /* Clear Busy bit */
mbed_official 610:813dcc80987e 1700 HAL_QSPI_Abort(hqspi);
mbed_official 610:813dcc80987e 1701
mbed_official 610:813dcc80987e 1702 /* Update state */
mbed_official 610:813dcc80987e 1703 hqspi->State = HAL_QSPI_STATE_READY;
mbed_official 610:813dcc80987e 1704
mbed_official 610:813dcc80987e 1705 HAL_QSPI_TxCpltCallback(hqspi);
mbed_official 610:813dcc80987e 1706 }
mbed_official 610:813dcc80987e 1707 }
mbed_official 610:813dcc80987e 1708
mbed_official 610:813dcc80987e 1709 /**
mbed_official 610:813dcc80987e 1710 * @brief DMA QSPI receive process half complete callback.
mbed_official 610:813dcc80987e 1711 * @param hdma : DMA handle
mbed_official 610:813dcc80987e 1712 * @retval None
mbed_official 610:813dcc80987e 1713 */
mbed_official 610:813dcc80987e 1714 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
mbed_official 610:813dcc80987e 1715 {
mbed_official 610:813dcc80987e 1716 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 610:813dcc80987e 1717
mbed_official 610:813dcc80987e 1718 HAL_QSPI_RxHalfCpltCallback(hqspi);
mbed_official 610:813dcc80987e 1719 }
mbed_official 610:813dcc80987e 1720
mbed_official 610:813dcc80987e 1721 /**
mbed_official 610:813dcc80987e 1722 * @brief DMA QSPI transmit process half complete callback.
mbed_official 610:813dcc80987e 1723 * @param hdma : DMA handle
mbed_official 610:813dcc80987e 1724 * @retval None
mbed_official 610:813dcc80987e 1725 */
mbed_official 610:813dcc80987e 1726 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
mbed_official 610:813dcc80987e 1727 {
mbed_official 610:813dcc80987e 1728 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
mbed_official 610:813dcc80987e 1729
mbed_official 610:813dcc80987e 1730 HAL_QSPI_TxHalfCpltCallback(hqspi);
mbed_official 610:813dcc80987e 1731 }
mbed_official 610:813dcc80987e 1732
mbed_official 610:813dcc80987e 1733 /**
mbed_official 610:813dcc80987e 1734 * @brief DMA QSPI communication error callback.
mbed_official 610:813dcc80987e 1735 * @param hdma: DMA handle
mbed_official 610:813dcc80987e 1736 * @retval None
mbed_official 610:813dcc80987e 1737 */
mbed_official 610:813dcc80987e 1738 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 610:813dcc80987e 1739 {
mbed_official 610:813dcc80987e 1740 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 610:813dcc80987e 1741
mbed_official 610:813dcc80987e 1742 hqspi->RxXferCount = 0;
mbed_official 610:813dcc80987e 1743 hqspi->TxXferCount = 0;
mbed_official 610:813dcc80987e 1744 hqspi->State = HAL_QSPI_STATE_ERROR;
mbed_official 610:813dcc80987e 1745 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
mbed_official 610:813dcc80987e 1746
mbed_official 610:813dcc80987e 1747 HAL_QSPI_ErrorCallback(hqspi);
mbed_official 610:813dcc80987e 1748 }
mbed_official 610:813dcc80987e 1749
mbed_official 610:813dcc80987e 1750 /**
mbed_official 610:813dcc80987e 1751 * @brief Wait for a flag state until timeout.
mbed_official 610:813dcc80987e 1752 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1753 * @param Flag: Flag checked
mbed_official 610:813dcc80987e 1754 * @param State: Value of the flag expected
mbed_official 610:813dcc80987e 1755 * @param Timeout: Duration of the timeout
mbed_official 610:813dcc80987e 1756 * @retval HAL status
mbed_official 610:813dcc80987e 1757 */
mbed_official 610:813dcc80987e 1758 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
mbed_official 610:813dcc80987e 1759 FlagStatus State, uint32_t Timeout)
mbed_official 610:813dcc80987e 1760 {
mbed_official 610:813dcc80987e 1761 uint32_t tickstart = HAL_GetTick();
mbed_official 610:813dcc80987e 1762
mbed_official 610:813dcc80987e 1763 /* Wait until flag is in expected state */
mbed_official 610:813dcc80987e 1764 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
mbed_official 610:813dcc80987e 1765 {
mbed_official 610:813dcc80987e 1766 /* Check for the Timeout */
mbed_official 610:813dcc80987e 1767 if (Timeout != HAL_MAX_DELAY)
mbed_official 610:813dcc80987e 1768 {
mbed_official 610:813dcc80987e 1769 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
mbed_official 610:813dcc80987e 1770 {
mbed_official 610:813dcc80987e 1771 hqspi->State = HAL_QSPI_STATE_ERROR;
mbed_official 610:813dcc80987e 1772 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
mbed_official 610:813dcc80987e 1773
mbed_official 610:813dcc80987e 1774 return HAL_TIMEOUT;
mbed_official 610:813dcc80987e 1775 }
mbed_official 610:813dcc80987e 1776 }
mbed_official 610:813dcc80987e 1777 }
mbed_official 610:813dcc80987e 1778 return HAL_OK;
mbed_official 610:813dcc80987e 1779 }
mbed_official 610:813dcc80987e 1780
mbed_official 610:813dcc80987e 1781 /**
mbed_official 610:813dcc80987e 1782 * @brief Configure the communication registers.
mbed_official 610:813dcc80987e 1783 * @param hqspi: QSPI handle
mbed_official 610:813dcc80987e 1784 * @param cmd: structure that contains the command configuration information
mbed_official 610:813dcc80987e 1785 * @param FunctionalMode: functional mode to configured
mbed_official 610:813dcc80987e 1786 * This parameter can be one of the following values:
mbed_official 610:813dcc80987e 1787 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
mbed_official 610:813dcc80987e 1788 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
mbed_official 610:813dcc80987e 1789 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
mbed_official 610:813dcc80987e 1790 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
mbed_official 610:813dcc80987e 1791 * @retval None
mbed_official 610:813dcc80987e 1792 */
mbed_official 610:813dcc80987e 1793 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
mbed_official 610:813dcc80987e 1794 {
mbed_official 610:813dcc80987e 1795 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
mbed_official 610:813dcc80987e 1796
mbed_official 610:813dcc80987e 1797 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
mbed_official 610:813dcc80987e 1798 {
mbed_official 610:813dcc80987e 1799 /* Configure QSPI: DLR register with the number of data to read or write */
mbed_official 610:813dcc80987e 1800 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
mbed_official 610:813dcc80987e 1801 }
mbed_official 610:813dcc80987e 1802
mbed_official 610:813dcc80987e 1803 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
mbed_official 610:813dcc80987e 1804 {
mbed_official 610:813dcc80987e 1805 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 1806 {
mbed_official 610:813dcc80987e 1807 /* Configure QSPI: ABR register with alternate bytes value */
mbed_official 610:813dcc80987e 1808 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
mbed_official 610:813dcc80987e 1809
mbed_official 610:813dcc80987e 1810 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1811 {
mbed_official 610:813dcc80987e 1812 /*---- Command with instruction, address and alternate bytes ----*/
mbed_official 610:813dcc80987e 1813 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1814 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1815 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1816 cmd->AlternateBytesSize | cmd->AlternateByteMode |
mbed_official 610:813dcc80987e 1817 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
mbed_official 610:813dcc80987e 1818 cmd->Instruction | FunctionalMode));
mbed_official 610:813dcc80987e 1819
mbed_official 610:813dcc80987e 1820 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
mbed_official 610:813dcc80987e 1821 {
mbed_official 610:813dcc80987e 1822 /* Configure QSPI: AR register with address value */
mbed_official 610:813dcc80987e 1823 WRITE_REG(hqspi->Instance->AR, cmd->Address);
mbed_official 610:813dcc80987e 1824 }
mbed_official 610:813dcc80987e 1825 }
mbed_official 610:813dcc80987e 1826 else
mbed_official 610:813dcc80987e 1827 {
mbed_official 610:813dcc80987e 1828 /*---- Command with instruction and alternate bytes ----*/
mbed_official 610:813dcc80987e 1829 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1830 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1831 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1832 cmd->AlternateBytesSize | cmd->AlternateByteMode |
mbed_official 610:813dcc80987e 1833 cmd->AddressMode | cmd->InstructionMode |
mbed_official 610:813dcc80987e 1834 cmd->Instruction | FunctionalMode));
mbed_official 610:813dcc80987e 1835 }
mbed_official 610:813dcc80987e 1836 }
mbed_official 610:813dcc80987e 1837 else
mbed_official 610:813dcc80987e 1838 {
mbed_official 610:813dcc80987e 1839 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1840 {
mbed_official 610:813dcc80987e 1841 /*---- Command with instruction and address ----*/
mbed_official 610:813dcc80987e 1842 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1843 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1844 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1845 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
mbed_official 610:813dcc80987e 1846 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
mbed_official 610:813dcc80987e 1847
mbed_official 610:813dcc80987e 1848 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
mbed_official 610:813dcc80987e 1849 {
mbed_official 610:813dcc80987e 1850 /* Configure QSPI: AR register with address value */
mbed_official 610:813dcc80987e 1851 WRITE_REG(hqspi->Instance->AR, cmd->Address);
mbed_official 610:813dcc80987e 1852 }
mbed_official 610:813dcc80987e 1853 }
mbed_official 610:813dcc80987e 1854 else
mbed_official 610:813dcc80987e 1855 {
mbed_official 610:813dcc80987e 1856 /*---- Command with only instruction ----*/
mbed_official 610:813dcc80987e 1857 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1858 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1859 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1860 cmd->AlternateByteMode | cmd->AddressMode |
mbed_official 610:813dcc80987e 1861 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
mbed_official 610:813dcc80987e 1862 }
mbed_official 610:813dcc80987e 1863 }
mbed_official 610:813dcc80987e 1864 }
mbed_official 610:813dcc80987e 1865 else
mbed_official 610:813dcc80987e 1866 {
mbed_official 610:813dcc80987e 1867 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
mbed_official 610:813dcc80987e 1868 {
mbed_official 610:813dcc80987e 1869 /* Configure QSPI: ABR register with alternate bytes value */
mbed_official 610:813dcc80987e 1870 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
mbed_official 610:813dcc80987e 1871
mbed_official 610:813dcc80987e 1872 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1873 {
mbed_official 610:813dcc80987e 1874 /*---- Command with address and alternate bytes ----*/
mbed_official 610:813dcc80987e 1875 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1876 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1877 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1878 cmd->AlternateBytesSize | cmd->AlternateByteMode |
mbed_official 610:813dcc80987e 1879 cmd->AddressSize | cmd->AddressMode |
mbed_official 610:813dcc80987e 1880 cmd->InstructionMode | FunctionalMode));
mbed_official 610:813dcc80987e 1881
mbed_official 610:813dcc80987e 1882 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
mbed_official 610:813dcc80987e 1883 {
mbed_official 610:813dcc80987e 1884 /* Configure QSPI: AR register with address value */
mbed_official 610:813dcc80987e 1885 WRITE_REG(hqspi->Instance->AR, cmd->Address);
mbed_official 610:813dcc80987e 1886 }
mbed_official 610:813dcc80987e 1887 }
mbed_official 610:813dcc80987e 1888 else
mbed_official 610:813dcc80987e 1889 {
mbed_official 610:813dcc80987e 1890 /*---- Command with only alternate bytes ----*/
mbed_official 610:813dcc80987e 1891 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1892 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1893 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1894 cmd->AlternateBytesSize | cmd->AlternateByteMode |
mbed_official 610:813dcc80987e 1895 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
mbed_official 610:813dcc80987e 1896 }
mbed_official 610:813dcc80987e 1897 }
mbed_official 610:813dcc80987e 1898 else
mbed_official 610:813dcc80987e 1899 {
mbed_official 610:813dcc80987e 1900 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
mbed_official 610:813dcc80987e 1901 {
mbed_official 610:813dcc80987e 1902 /*---- Command with only address ----*/
mbed_official 610:813dcc80987e 1903 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1904 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1905 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1906 cmd->AlternateByteMode | cmd->AddressSize |
mbed_official 610:813dcc80987e 1907 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
mbed_official 610:813dcc80987e 1908
mbed_official 610:813dcc80987e 1909 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
mbed_official 610:813dcc80987e 1910 {
mbed_official 610:813dcc80987e 1911 /* Configure QSPI: AR register with address value */
mbed_official 610:813dcc80987e 1912 WRITE_REG(hqspi->Instance->AR, cmd->Address);
mbed_official 610:813dcc80987e 1913 }
mbed_official 610:813dcc80987e 1914 }
mbed_official 610:813dcc80987e 1915 else
mbed_official 610:813dcc80987e 1916 {
mbed_official 610:813dcc80987e 1917 /*---- Command with only data phase ----*/
mbed_official 610:813dcc80987e 1918 if (cmd->DataMode != QSPI_DATA_NONE)
mbed_official 610:813dcc80987e 1919 {
mbed_official 610:813dcc80987e 1920 /* Configure QSPI: CCR register with all communications parameters */
mbed_official 610:813dcc80987e 1921 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
mbed_official 610:813dcc80987e 1922 cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
mbed_official 610:813dcc80987e 1923 cmd->AlternateByteMode | cmd->AddressMode |
mbed_official 610:813dcc80987e 1924 cmd->InstructionMode | FunctionalMode));
mbed_official 610:813dcc80987e 1925 }
mbed_official 610:813dcc80987e 1926 }
mbed_official 610:813dcc80987e 1927 }
mbed_official 610:813dcc80987e 1928 }
mbed_official 610:813dcc80987e 1929 }
mbed_official 610:813dcc80987e 1930
mbed_official 610:813dcc80987e 1931 /**
mbed_official 610:813dcc80987e 1932 * @}
mbed_official 610:813dcc80987e 1933 */
mbed_official 610:813dcc80987e 1934
mbed_official 610:813dcc80987e 1935 #endif /* HAL_QSPI_MODULE_ENABLED */
mbed_official 610:813dcc80987e 1936 /**
mbed_official 610:813dcc80987e 1937 * @}
mbed_official 610:813dcc80987e 1938 */
mbed_official 610:813dcc80987e 1939
mbed_official 610:813dcc80987e 1940 /**
mbed_official 610:813dcc80987e 1941 * @}
mbed_official 610:813dcc80987e 1942 */
mbed_official 610:813dcc80987e 1943
mbed_official 610:813dcc80987e 1944 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/