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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/system_stm32l4xx.c@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 610:813dcc80987e 1 /**
mbed_official 610:813dcc80987e 2 ******************************************************************************
mbed_official 610:813dcc80987e 3 * @file system_stm32l4xx.c
mbed_official 610:813dcc80987e 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.0
mbed_official 610:813dcc80987e 6 * @date 26-June-2015
mbed_official 610:813dcc80987e 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
mbed_official 610:813dcc80987e 8 *
mbed_official 610:813dcc80987e 9 * This file provides two functions and one global variable to be called from
mbed_official 610:813dcc80987e 10 * user application:
mbed_official 610:813dcc80987e 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 610:813dcc80987e 12 * before branch to main program. This call is made inside
mbed_official 610:813dcc80987e 13 * the "startup_stm32l4xx.s" file.
mbed_official 610:813dcc80987e 14 *
mbed_official 610:813dcc80987e 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 610:813dcc80987e 16 * by the user application to setup the SysTick
mbed_official 610:813dcc80987e 17 * timer or configure other parameters.
mbed_official 610:813dcc80987e 18 *
mbed_official 610:813dcc80987e 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 610:813dcc80987e 20 * be called whenever the core clock is changed
mbed_official 610:813dcc80987e 21 * during program execution.
mbed_official 610:813dcc80987e 22 *
mbed_official 610:813dcc80987e 23 * After each device reset the MSI (4 MHz) is used as system clock source.
mbed_official 610:813dcc80987e 24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
mbed_official 610:813dcc80987e 25 * configure the system clock before to branch to main program.
mbed_official 610:813dcc80987e 26 *
mbed_official 610:813dcc80987e 27 * This file configures the system clock as follows:
mbed_official 610:813dcc80987e 28 *=============================================================================
mbed_official 610:813dcc80987e 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 610:813dcc80987e 30 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 610:813dcc80987e 31 * | 2- PLL_HSE_XTAL | or PLL_MSI
mbed_official 610:813dcc80987e 32 * | (external 8 MHz xtal) | (internal 4 MHz)
mbed_official 610:813dcc80987e 33 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 34 * SYSCLK(MHz) | 48 | 80
mbed_official 610:813dcc80987e 35 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 36 * AHBCLK (MHz) | 48 | 80
mbed_official 610:813dcc80987e 37 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 38 * APB1CLK (MHz) | 48 | 80
mbed_official 610:813dcc80987e 39 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 40 * APB2CLK (MHz) | 48 | 80
mbed_official 610:813dcc80987e 41 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 42 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 610:813dcc80987e 43 *-----------------------------------------------------------------------------
mbed_official 610:813dcc80987e 44 *=============================================================================
mbed_official 610:813dcc80987e 45 ******************************************************************************
mbed_official 610:813dcc80987e 46 * @attention
mbed_official 610:813dcc80987e 47 *
mbed_official 610:813dcc80987e 48 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 610:813dcc80987e 49 *
mbed_official 610:813dcc80987e 50 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 610:813dcc80987e 51 * are permitted provided that the following conditions are met:
mbed_official 610:813dcc80987e 52 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 610:813dcc80987e 53 * this list of conditions and the following disclaimer.
mbed_official 610:813dcc80987e 54 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 610:813dcc80987e 55 * this list of conditions and the following disclaimer in the documentation
mbed_official 610:813dcc80987e 56 * and/or other materials provided with the distribution.
mbed_official 610:813dcc80987e 57 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 610:813dcc80987e 58 * may be used to endorse or promote products derived from this software
mbed_official 610:813dcc80987e 59 * without specific prior written permission.
mbed_official 610:813dcc80987e 60 *
mbed_official 610:813dcc80987e 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 610:813dcc80987e 62 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 610:813dcc80987e 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 610:813dcc80987e 64 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 610:813dcc80987e 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 610:813dcc80987e 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 610:813dcc80987e 67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 610:813dcc80987e 68 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 610:813dcc80987e 69 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 610:813dcc80987e 70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 610:813dcc80987e 71 *
mbed_official 610:813dcc80987e 72 ******************************************************************************
mbed_official 610:813dcc80987e 73 */
mbed_official 610:813dcc80987e 74
mbed_official 610:813dcc80987e 75 /** @addtogroup CMSIS
mbed_official 610:813dcc80987e 76 * @{
mbed_official 610:813dcc80987e 77 */
mbed_official 610:813dcc80987e 78
mbed_official 610:813dcc80987e 79 /** @addtogroup stm32l4xx_system
mbed_official 610:813dcc80987e 80 * @{
mbed_official 610:813dcc80987e 81 */
mbed_official 610:813dcc80987e 82
mbed_official 610:813dcc80987e 83 /** @addtogroup STM32L4xx_System_Private_Includes
mbed_official 610:813dcc80987e 84 * @{
mbed_official 610:813dcc80987e 85 */
mbed_official 610:813dcc80987e 86
mbed_official 610:813dcc80987e 87 #include "stm32l4xx.h"
mbed_official 610:813dcc80987e 88 #include "hal_tick.h"
mbed_official 610:813dcc80987e 89
mbed_official 610:813dcc80987e 90 #if !defined (HSE_VALUE)
mbed_official 610:813dcc80987e 91 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
mbed_official 610:813dcc80987e 92 #endif /* HSE_VALUE */
mbed_official 610:813dcc80987e 93
mbed_official 610:813dcc80987e 94 #if !defined (MSI_VALUE)
mbed_official 610:813dcc80987e 95 #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 610:813dcc80987e 96 #endif /* MSI_VALUE */
mbed_official 610:813dcc80987e 97
mbed_official 610:813dcc80987e 98 #if !defined (HSI_VALUE)
mbed_official 610:813dcc80987e 99 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 610:813dcc80987e 100 #endif /* HSI_VALUE */
mbed_official 610:813dcc80987e 101
mbed_official 610:813dcc80987e 102 /**
mbed_official 610:813dcc80987e 103 * @}
mbed_official 610:813dcc80987e 104 */
mbed_official 610:813dcc80987e 105
mbed_official 610:813dcc80987e 106 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
mbed_official 610:813dcc80987e 107 * @{
mbed_official 610:813dcc80987e 108 */
mbed_official 610:813dcc80987e 109
mbed_official 610:813dcc80987e 110 /**
mbed_official 610:813dcc80987e 111 * @}
mbed_official 610:813dcc80987e 112 */
mbed_official 610:813dcc80987e 113
mbed_official 610:813dcc80987e 114 /** @addtogroup STM32L4xx_System_Private_Defines
mbed_official 610:813dcc80987e 115 * @{
mbed_official 610:813dcc80987e 116 */
mbed_official 610:813dcc80987e 117
mbed_official 610:813dcc80987e 118 /************************* Miscellaneous Configuration ************************/
mbed_official 610:813dcc80987e 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 610:813dcc80987e 120 Internal SRAM. */
mbed_official 610:813dcc80987e 121 /* #define VECT_TAB_SRAM */
mbed_official 610:813dcc80987e 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 610:813dcc80987e 123 This value must be a multiple of 0x200. */
mbed_official 610:813dcc80987e 124 /******************************************************************************/
mbed_official 610:813dcc80987e 125 /**
mbed_official 610:813dcc80987e 126 * @}
mbed_official 610:813dcc80987e 127 */
mbed_official 610:813dcc80987e 128
mbed_official 610:813dcc80987e 129 /** @addtogroup STM32L4xx_System_Private_Macros
mbed_official 610:813dcc80987e 130 * @{
mbed_official 610:813dcc80987e 131 */
mbed_official 610:813dcc80987e 132
mbed_official 610:813dcc80987e 133 // Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
mbed_official 610:813dcc80987e 134 #define USE_PLL_HSE_EXTC (1) // Use external clock
mbed_official 610:813dcc80987e 135 #define USE_PLL_HSE_XTAL (0) // Use external xtal
mbed_official 610:813dcc80987e 136 #define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
mbed_official 610:813dcc80987e 137 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
mbed_official 610:813dcc80987e 138 /**
mbed_official 610:813dcc80987e 139 * @}
mbed_official 610:813dcc80987e 140 */
mbed_official 610:813dcc80987e 141
mbed_official 610:813dcc80987e 142 /** @addtogroup STM32L4xx_System_Private_Variables
mbed_official 610:813dcc80987e 143 * @{
mbed_official 610:813dcc80987e 144 */
mbed_official 610:813dcc80987e 145 /* This variable is updated in three ways:
mbed_official 610:813dcc80987e 146 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 610:813dcc80987e 147 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 610:813dcc80987e 148 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 610:813dcc80987e 149 Note: If you use this function to configure the system clock; then there
mbed_official 610:813dcc80987e 150 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 610:813dcc80987e 151 variable is updated automatically.
mbed_official 610:813dcc80987e 152 */
mbed_official 610:813dcc80987e 153 uint32_t SystemCoreClock = 4000000;
mbed_official 610:813dcc80987e 154
mbed_official 610:813dcc80987e 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 610:813dcc80987e 156 const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
mbed_official 610:813dcc80987e 157 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
mbed_official 610:813dcc80987e 158 /**
mbed_official 610:813dcc80987e 159 * @}
mbed_official 610:813dcc80987e 160 */
mbed_official 610:813dcc80987e 161
mbed_official 610:813dcc80987e 162 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
mbed_official 610:813dcc80987e 163 * @{
mbed_official 610:813dcc80987e 164 */
mbed_official 610:813dcc80987e 165
mbed_official 610:813dcc80987e 166 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 610:813dcc80987e 167 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 610:813dcc80987e 168 #endif
mbed_official 610:813dcc80987e 169
mbed_official 610:813dcc80987e 170 #if (USE_PLL_HSI != 0)
mbed_official 610:813dcc80987e 171 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 610:813dcc80987e 172 #endif
mbed_official 610:813dcc80987e 173
mbed_official 610:813dcc80987e 174 uint8_t SetSysClock_PLL_MSI(void);
mbed_official 610:813dcc80987e 175
mbed_official 610:813dcc80987e 176 /**
mbed_official 610:813dcc80987e 177 * @}
mbed_official 610:813dcc80987e 178 */
mbed_official 610:813dcc80987e 179
mbed_official 610:813dcc80987e 180 /** @addtogroup STM32L4xx_System_Private_Functions
mbed_official 610:813dcc80987e 181 * @{
mbed_official 610:813dcc80987e 182 */
mbed_official 610:813dcc80987e 183
mbed_official 610:813dcc80987e 184 /**
mbed_official 610:813dcc80987e 185 * @brief Setup the microcontroller system.
mbed_official 610:813dcc80987e 186 * @param None
mbed_official 610:813dcc80987e 187 * @retval None
mbed_official 610:813dcc80987e 188 */
mbed_official 610:813dcc80987e 189
mbed_official 610:813dcc80987e 190 void SystemInit(void)
mbed_official 610:813dcc80987e 191 {
mbed_official 610:813dcc80987e 192 /* FPU settings ------------------------------------------------------------*/
mbed_official 610:813dcc80987e 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 610:813dcc80987e 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 610:813dcc80987e 195 #endif
mbed_official 610:813dcc80987e 196 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 610:813dcc80987e 197 /* Set MSION bit */
mbed_official 610:813dcc80987e 198 RCC->CR |= RCC_CR_MSION;
mbed_official 610:813dcc80987e 199
mbed_official 610:813dcc80987e 200 /* Reset CFGR register */
mbed_official 610:813dcc80987e 201 RCC->CFGR = 0x00000000;
mbed_official 610:813dcc80987e 202
mbed_official 610:813dcc80987e 203 /* Reset HSEON, CSSON , HSION, and PLLON bits */
mbed_official 610:813dcc80987e 204 RCC->CR &= (uint32_t)0xEAF6FFFF;
mbed_official 610:813dcc80987e 205
mbed_official 610:813dcc80987e 206 /* Reset PLLCFGR register */
mbed_official 610:813dcc80987e 207 RCC->PLLCFGR = 0x00000800;
mbed_official 610:813dcc80987e 208
mbed_official 610:813dcc80987e 209 /* Reset HSEBYP bit */
mbed_official 610:813dcc80987e 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 610:813dcc80987e 211
mbed_official 610:813dcc80987e 212 /* Disable all interrupts */
mbed_official 610:813dcc80987e 213 RCC->CIER = 0x00000000;
mbed_official 610:813dcc80987e 214
mbed_official 610:813dcc80987e 215 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 610:813dcc80987e 216 #ifdef VECT_TAB_SRAM
mbed_official 610:813dcc80987e 217 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 610:813dcc80987e 218 #else
mbed_official 610:813dcc80987e 219 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 610:813dcc80987e 220 #endif
mbed_official 610:813dcc80987e 221
mbed_official 610:813dcc80987e 222 /* Configure the Cube driver */
mbed_official 610:813dcc80987e 223 SystemCoreClock = MSI_VALUE; // At this stage the MSI is used as system clock
mbed_official 610:813dcc80987e 224 HAL_Init();
mbed_official 610:813dcc80987e 225
mbed_official 610:813dcc80987e 226 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 610:813dcc80987e 227 AHB/APBx prescalers and Flash settings */
mbed_official 610:813dcc80987e 228 SetSysClock();
mbed_official 610:813dcc80987e 229
mbed_official 610:813dcc80987e 230 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 610:813dcc80987e 231 TIM_MST_RESET_ON;
mbed_official 610:813dcc80987e 232 TIM_MST_RESET_OFF;
mbed_official 610:813dcc80987e 233 }
mbed_official 610:813dcc80987e 234
mbed_official 610:813dcc80987e 235 /**
mbed_official 610:813dcc80987e 236 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 610:813dcc80987e 237 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 610:813dcc80987e 238 * be used by the user application to setup the SysTick timer or configure
mbed_official 610:813dcc80987e 239 * other parameters.
mbed_official 610:813dcc80987e 240 *
mbed_official 610:813dcc80987e 241 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 610:813dcc80987e 242 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 610:813dcc80987e 243 * based on this variable will be incorrect.
mbed_official 610:813dcc80987e 244 *
mbed_official 610:813dcc80987e 245 * @note - The system frequency computed by this function is not the real
mbed_official 610:813dcc80987e 246 * frequency in the chip. It is calculated based on the predefined
mbed_official 610:813dcc80987e 247 * constant and the selected clock source:
mbed_official 610:813dcc80987e 248 *
mbed_official 610:813dcc80987e 249 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
mbed_official 610:813dcc80987e 250 *
mbed_official 610:813dcc80987e 251 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
mbed_official 610:813dcc80987e 252 *
mbed_official 610:813dcc80987e 253 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
mbed_official 610:813dcc80987e 254 *
mbed_official 610:813dcc80987e 255 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
mbed_official 610:813dcc80987e 256 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 610:813dcc80987e 257 *
mbed_official 610:813dcc80987e 258 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
mbed_official 610:813dcc80987e 259 * 4 MHz) but the real value may vary depending on the variations
mbed_official 610:813dcc80987e 260 * in voltage and temperature.
mbed_official 610:813dcc80987e 261 *
mbed_official 610:813dcc80987e 262 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
mbed_official 610:813dcc80987e 263 * 16 MHz) but the real value may vary depending on the variations
mbed_official 610:813dcc80987e 264 * in voltage and temperature.
mbed_official 610:813dcc80987e 265 *
mbed_official 610:813dcc80987e 266 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
mbed_official 610:813dcc80987e 267 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 610:813dcc80987e 268 * frequency of the crystal used. Otherwise, this function may
mbed_official 610:813dcc80987e 269 * have wrong result.
mbed_official 610:813dcc80987e 270 *
mbed_official 610:813dcc80987e 271 * - The result of this function could be not correct when using fractional
mbed_official 610:813dcc80987e 272 * value for HSE crystal.
mbed_official 610:813dcc80987e 273 *
mbed_official 610:813dcc80987e 274 * @param None
mbed_official 610:813dcc80987e 275 * @retval None
mbed_official 610:813dcc80987e 276 */
mbed_official 610:813dcc80987e 277 void SystemCoreClockUpdate(void)
mbed_official 610:813dcc80987e 278 {
mbed_official 610:813dcc80987e 279 uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
mbed_official 610:813dcc80987e 280
mbed_official 610:813dcc80987e 281 /* Get MSI Range frequency--------------------------------------------------*/
mbed_official 610:813dcc80987e 282 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
mbed_official 610:813dcc80987e 283 { /* MSISRANGE from RCC_CSR applies */
mbed_official 610:813dcc80987e 284 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
mbed_official 610:813dcc80987e 285 }
mbed_official 610:813dcc80987e 286 else
mbed_official 610:813dcc80987e 287 { /* MSIRANGE from RCC_CR applies */
mbed_official 610:813dcc80987e 288 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
mbed_official 610:813dcc80987e 289 }
mbed_official 610:813dcc80987e 290 /*MSI frequency range in HZ*/
mbed_official 610:813dcc80987e 291 msirange = MSIRangeTable[msirange];
mbed_official 610:813dcc80987e 292
mbed_official 610:813dcc80987e 293 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 610:813dcc80987e 294 switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official 610:813dcc80987e 295 {
mbed_official 610:813dcc80987e 296 case 0x00: /* MSI used as system clock source */
mbed_official 610:813dcc80987e 297 SystemCoreClock = msirange;
mbed_official 610:813dcc80987e 298 break;
mbed_official 610:813dcc80987e 299
mbed_official 610:813dcc80987e 300 case 0x04: /* HSI used as system clock source */
mbed_official 610:813dcc80987e 301 SystemCoreClock = HSI_VALUE;
mbed_official 610:813dcc80987e 302 break;
mbed_official 610:813dcc80987e 303
mbed_official 610:813dcc80987e 304 case 0x08: /* HSE used as system clock source */
mbed_official 610:813dcc80987e 305 SystemCoreClock = HSE_VALUE;
mbed_official 610:813dcc80987e 306 break;
mbed_official 610:813dcc80987e 307
mbed_official 610:813dcc80987e 308 case 0x0C: /* PLL used as system clock source */
mbed_official 610:813dcc80987e 309 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
mbed_official 610:813dcc80987e 310 SYSCLK = PLL_VCO / PLLR
mbed_official 610:813dcc80987e 311 */
mbed_official 610:813dcc80987e 312 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official 610:813dcc80987e 313 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
mbed_official 610:813dcc80987e 314
mbed_official 610:813dcc80987e 315 switch (pllsource)
mbed_official 610:813dcc80987e 316 {
mbed_official 610:813dcc80987e 317 case 0x02: /* HSI used as PLL clock source */
mbed_official 610:813dcc80987e 318 pllvco = (HSI_VALUE / pllm);
mbed_official 610:813dcc80987e 319 break;
mbed_official 610:813dcc80987e 320
mbed_official 610:813dcc80987e 321 case 0x03: /* HSE used as PLL clock source */
mbed_official 610:813dcc80987e 322 pllvco = (HSE_VALUE / pllm);
mbed_official 610:813dcc80987e 323 break;
mbed_official 610:813dcc80987e 324
mbed_official 610:813dcc80987e 325 default: /* MSI used as PLL clock source */
mbed_official 610:813dcc80987e 326 pllvco = (msirange / pllm);
mbed_official 610:813dcc80987e 327 break;
mbed_official 610:813dcc80987e 328 }
mbed_official 610:813dcc80987e 329 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
mbed_official 610:813dcc80987e 330 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
mbed_official 610:813dcc80987e 331 SystemCoreClock = pllvco/pllr;
mbed_official 610:813dcc80987e 332 break;
mbed_official 610:813dcc80987e 333
mbed_official 610:813dcc80987e 334 default:
mbed_official 610:813dcc80987e 335 SystemCoreClock = msirange;
mbed_official 610:813dcc80987e 336 break;
mbed_official 610:813dcc80987e 337 }
mbed_official 610:813dcc80987e 338 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 610:813dcc80987e 339 /* Get HCLK prescaler */
mbed_official 610:813dcc80987e 340 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 610:813dcc80987e 341 /* HCLK clock frequency */
mbed_official 610:813dcc80987e 342 SystemCoreClock >>= tmp;
mbed_official 610:813dcc80987e 343 }
mbed_official 610:813dcc80987e 344
mbed_official 610:813dcc80987e 345 /**
mbed_official 610:813dcc80987e 346 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 610:813dcc80987e 347 * AHB/APBx prescalers and Flash settings
mbed_official 610:813dcc80987e 348 * @note This function should be called only once the RCC clock configuration
mbed_official 610:813dcc80987e 349 * is reset to the default reset state (done in SystemInit() function).
mbed_official 610:813dcc80987e 350 * @param None
mbed_official 610:813dcc80987e 351 * @retval None
mbed_official 610:813dcc80987e 352 */
mbed_official 610:813dcc80987e 353 void SetSysClock(void)
mbed_official 610:813dcc80987e 354 {
mbed_official 610:813dcc80987e 355 /* 1- Try to start with HSE and external clock */
mbed_official 610:813dcc80987e 356 #if USE_PLL_HSE_EXTC != 0
mbed_official 610:813dcc80987e 357 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 610:813dcc80987e 358 #endif
mbed_official 610:813dcc80987e 359 {
mbed_official 610:813dcc80987e 360 /* 2- If fail try to start with HSE and external xtal */
mbed_official 610:813dcc80987e 361 #if USE_PLL_HSE_XTAL != 0
mbed_official 610:813dcc80987e 362 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 610:813dcc80987e 363 #endif
mbed_official 610:813dcc80987e 364 {
mbed_official 610:813dcc80987e 365 /* 3- If fail start with HSI or MSI clock */
mbed_official 610:813dcc80987e 366 #if (USE_PLL_HSI != 0)
mbed_official 610:813dcc80987e 367 if (SetSysClock_PLL_HSI() == 0)
mbed_official 610:813dcc80987e 368 #else
mbed_official 610:813dcc80987e 369 if (SetSysClock_PLL_MSI() == 0)
mbed_official 610:813dcc80987e 370 #endif
mbed_official 610:813dcc80987e 371 {
mbed_official 610:813dcc80987e 372 while(1)
mbed_official 610:813dcc80987e 373 {
mbed_official 610:813dcc80987e 374 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 610:813dcc80987e 375 }
mbed_official 610:813dcc80987e 376 }
mbed_official 610:813dcc80987e 377 }
mbed_official 610:813dcc80987e 378 }
mbed_official 610:813dcc80987e 379
mbed_official 610:813dcc80987e 380 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 610:813dcc80987e 381 #if DEBUG_MCO == 1
mbed_official 610:813dcc80987e 382 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official 610:813dcc80987e 383 #endif
mbed_official 610:813dcc80987e 384 }
mbed_official 610:813dcc80987e 385
mbed_official 610:813dcc80987e 386 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 610:813dcc80987e 387 /******************************************************************************/
mbed_official 610:813dcc80987e 388 /* PLL (clocked by HSE) used as System clock source */
mbed_official 610:813dcc80987e 389 /******************************************************************************/
mbed_official 610:813dcc80987e 390 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 610:813dcc80987e 391 {
mbed_official 610:813dcc80987e 392 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
mbed_official 610:813dcc80987e 393 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
mbed_official 610:813dcc80987e 394
mbed_official 610:813dcc80987e 395 // Used to gain time after DeepSleep in case HSI is used
mbed_official 610:813dcc80987e 396 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 610:813dcc80987e 397 {
mbed_official 610:813dcc80987e 398 return 0;
mbed_official 610:813dcc80987e 399 }
mbed_official 610:813dcc80987e 400
mbed_official 610:813dcc80987e 401 // Select MSI as system clock source to allow modification of the PLL configuration
mbed_official 610:813dcc80987e 402 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
mbed_official 610:813dcc80987e 403 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
mbed_official 610:813dcc80987e 404 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
mbed_official 610:813dcc80987e 405
mbed_official 610:813dcc80987e 406 // Enable HSE oscillator and activate PLL with HSE as source
mbed_official 610:813dcc80987e 407 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
mbed_official 610:813dcc80987e 408 if (bypass == 0)
mbed_official 610:813dcc80987e 409 {
mbed_official 610:813dcc80987e 410 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 610:813dcc80987e 411 }
mbed_official 610:813dcc80987e 412 else
mbed_official 610:813dcc80987e 413 {
mbed_official 610:813dcc80987e 414 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
mbed_official 610:813dcc80987e 415 }
mbed_official 610:813dcc80987e 416 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 610:813dcc80987e 417 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
mbed_official 610:813dcc80987e 418 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 610:813dcc80987e 419
mbed_official 610:813dcc80987e 420 // Non-USB configuration : sysclock = 80MHz
mbed_official 610:813dcc80987e 421 //RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
mbed_official 610:813dcc80987e 422 //RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
mbed_official 610:813dcc80987e 423 //RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
mbed_official 610:813dcc80987e 424 //RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
mbed_official 610:813dcc80987e 425 //RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
mbed_official 610:813dcc80987e 426
mbed_official 610:813dcc80987e 427 // USB configuration : sysclock = 48 MHz
mbed_official 610:813dcc80987e 428 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
mbed_official 610:813dcc80987e 429 RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
mbed_official 610:813dcc80987e 430 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
mbed_official 610:813dcc80987e 431 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
mbed_official 610:813dcc80987e 432 RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
mbed_official 610:813dcc80987e 433
mbed_official 610:813dcc80987e 434 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 610:813dcc80987e 435 {
mbed_official 610:813dcc80987e 436 return 0; // FAIL
mbed_official 610:813dcc80987e 437 }
mbed_official 610:813dcc80987e 438
mbed_official 610:813dcc80987e 439 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 610:813dcc80987e 440 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 610:813dcc80987e 441 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
mbed_official 610:813dcc80987e 442 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
mbed_official 610:813dcc80987e 443 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
mbed_official 610:813dcc80987e 444 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
mbed_official 610:813dcc80987e 445 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
mbed_official 610:813dcc80987e 446 {
mbed_official 610:813dcc80987e 447 return 0; // FAIL
mbed_official 610:813dcc80987e 448 }
mbed_official 610:813dcc80987e 449
mbed_official 610:813dcc80987e 450 // Disable MSI Oscillator
mbed_official 610:813dcc80987e 451 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
mbed_official 610:813dcc80987e 452 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
mbed_official 610:813dcc80987e 453 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
mbed_official 610:813dcc80987e 454 HAL_RCC_OscConfig(&RCC_OscInitStruct);
mbed_official 610:813dcc80987e 455
mbed_official 610:813dcc80987e 456 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 610:813dcc80987e 457 #if DEBUG_MCO == 2
mbed_official 610:813dcc80987e 458 if (bypass == 0)
mbed_official 610:813dcc80987e 459 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 610:813dcc80987e 460 else
mbed_official 610:813dcc80987e 461 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 610:813dcc80987e 462 #endif
mbed_official 610:813dcc80987e 463
mbed_official 610:813dcc80987e 464 return 1; // OK
mbed_official 610:813dcc80987e 465 }
mbed_official 610:813dcc80987e 466 #endif
mbed_official 610:813dcc80987e 467
mbed_official 610:813dcc80987e 468 #if (USE_PLL_HSI != 0)
mbed_official 610:813dcc80987e 469 /******************************************************************************/
mbed_official 610:813dcc80987e 470 /* PLL (clocked by HSI) used as System clock source */
mbed_official 610:813dcc80987e 471 /******************************************************************************/
mbed_official 610:813dcc80987e 472 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 610:813dcc80987e 473 {
mbed_official 610:813dcc80987e 474 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
mbed_official 610:813dcc80987e 475 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
mbed_official 610:813dcc80987e 476
mbed_official 610:813dcc80987e 477 // Select MSI as system clock source to allow modification of the PLL configuration
mbed_official 610:813dcc80987e 478 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
mbed_official 610:813dcc80987e 479 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
mbed_official 610:813dcc80987e 480 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
mbed_official 610:813dcc80987e 481
mbed_official 610:813dcc80987e 482 // Enable HSI oscillator and activate PLL with HSI as source
mbed_official 610:813dcc80987e 483 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 610:813dcc80987e 484 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 610:813dcc80987e 485 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 610:813dcc80987e 486 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
mbed_official 610:813dcc80987e 487 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 610:813dcc80987e 488 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
mbed_official 610:813dcc80987e 489 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
mbed_official 610:813dcc80987e 490 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
mbed_official 610:813dcc80987e 491 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
mbed_official 610:813dcc80987e 492 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
mbed_official 610:813dcc80987e 493 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
mbed_official 610:813dcc80987e 494 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 610:813dcc80987e 495 {
mbed_official 610:813dcc80987e 496 return 0; // FAIL
mbed_official 610:813dcc80987e 497 }
mbed_official 610:813dcc80987e 498
mbed_official 610:813dcc80987e 499 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 610:813dcc80987e 500 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 610:813dcc80987e 501 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
mbed_official 610:813dcc80987e 502 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 503 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 504 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 505 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
mbed_official 610:813dcc80987e 506 {
mbed_official 610:813dcc80987e 507 return 0; // FAIL
mbed_official 610:813dcc80987e 508 }
mbed_official 610:813dcc80987e 509
mbed_official 610:813dcc80987e 510 // Disable MSI Oscillator
mbed_official 610:813dcc80987e 511 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
mbed_official 610:813dcc80987e 512 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
mbed_official 610:813dcc80987e 513 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
mbed_official 610:813dcc80987e 514 HAL_RCC_OscConfig(&RCC_OscInitStruct);
mbed_official 610:813dcc80987e 515
mbed_official 610:813dcc80987e 516 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 610:813dcc80987e 517 #if DEBUG_MCO == 3
mbed_official 610:813dcc80987e 518 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 610:813dcc80987e 519 #endif
mbed_official 610:813dcc80987e 520
mbed_official 610:813dcc80987e 521 return 1; // OK
mbed_official 610:813dcc80987e 522 }
mbed_official 610:813dcc80987e 523 #endif
mbed_official 610:813dcc80987e 524
mbed_official 610:813dcc80987e 525 /******************************************************************************/
mbed_official 610:813dcc80987e 526 /* PLL (clocked by MSI) used as System clock source */
mbed_official 610:813dcc80987e 527 /******************************************************************************/
mbed_official 610:813dcc80987e 528 uint8_t SetSysClock_PLL_MSI(void)
mbed_official 610:813dcc80987e 529 {
mbed_official 610:813dcc80987e 530 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
mbed_official 610:813dcc80987e 531 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
mbed_official 610:813dcc80987e 532
mbed_official 610:813dcc80987e 533 // Enable LSE Oscillator to automatically calibrate the MSI clock
mbed_official 610:813dcc80987e 534 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
mbed_official 610:813dcc80987e 535 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
mbed_official 610:813dcc80987e 536 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
mbed_official 610:813dcc80987e 537 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
mbed_official 610:813dcc80987e 538 RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
mbed_official 610:813dcc80987e 539 }
mbed_official 610:813dcc80987e 540
mbed_official 610:813dcc80987e 541 // Enable MSI oscillator and activate PLL with MSI as source
mbed_official 610:813dcc80987e 542 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 610:813dcc80987e 543 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
mbed_official 610:813dcc80987e 544 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 610:813dcc80987e 545 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 610:813dcc80987e 546 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
mbed_official 610:813dcc80987e 547 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
mbed_official 610:813dcc80987e 548 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 610:813dcc80987e 549 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
mbed_official 610:813dcc80987e 550 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
mbed_official 610:813dcc80987e 551 RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
mbed_official 610:813dcc80987e 552 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
mbed_official 610:813dcc80987e 553 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
mbed_official 610:813dcc80987e 554 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
mbed_official 610:813dcc80987e 555 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 610:813dcc80987e 556 {
mbed_official 610:813dcc80987e 557 return 0; // FAIL
mbed_official 610:813dcc80987e 558 }
mbed_official 610:813dcc80987e 559
mbed_official 610:813dcc80987e 560 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 610:813dcc80987e 561 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 610:813dcc80987e 562 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
mbed_official 610:813dcc80987e 563 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 564 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 565 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
mbed_official 610:813dcc80987e 566 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
mbed_official 610:813dcc80987e 567 {
mbed_official 610:813dcc80987e 568 return 0; // FAIL
mbed_official 610:813dcc80987e 569 }
mbed_official 610:813dcc80987e 570
mbed_official 610:813dcc80987e 571 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 610:813dcc80987e 572 #if DEBUG_MCO == 4
mbed_official 610:813dcc80987e 573 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
mbed_official 610:813dcc80987e 574 #endif
mbed_official 610:813dcc80987e 575
mbed_official 610:813dcc80987e 576 return 1; // OK
mbed_official 610:813dcc80987e 577 }
mbed_official 610:813dcc80987e 578
mbed_official 610:813dcc80987e 579 /**
mbed_official 610:813dcc80987e 580 * @}
mbed_official 610:813dcc80987e 581 */
mbed_official 610:813dcc80987e 582
mbed_official 610:813dcc80987e 583 /**
mbed_official 610:813dcc80987e 584 * @}
mbed_official 610:813dcc80987e 585 */
mbed_official 610:813dcc80987e 586
mbed_official 610:813dcc80987e 587 /**
mbed_official 610:813dcc80987e 588 * @}
mbed_official 610:813dcc80987e 589 */
mbed_official 610:813dcc80987e 590
mbed_official 610:813dcc80987e 591 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/