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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Parent:
573:ad23fe03a082 
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_ll_sdmmc.h
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.1
mbed_official 610:813dcc80987e 6 * @date 25-June-2015
mbed_official 573:ad23fe03a082 7 * @brief Header file of SDMMC HAL module.
mbed_official 573:ad23fe03a082 8 ******************************************************************************
mbed_official 573:ad23fe03a082 9 * @attention
mbed_official 573:ad23fe03a082 10 *
mbed_official 573:ad23fe03a082 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 12 *
mbed_official 573:ad23fe03a082 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 14 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 16 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 19 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 21 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 22 * without specific prior written permission.
mbed_official 573:ad23fe03a082 23 *
mbed_official 573:ad23fe03a082 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 34 *
mbed_official 573:ad23fe03a082 35 ******************************************************************************
mbed_official 573:ad23fe03a082 36 */
mbed_official 573:ad23fe03a082 37
mbed_official 573:ad23fe03a082 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 573:ad23fe03a082 39 #ifndef __STM32F7xx_LL_SDMMC_H
mbed_official 573:ad23fe03a082 40 #define __STM32F7xx_LL_SDMMC_H
mbed_official 573:ad23fe03a082 41
mbed_official 573:ad23fe03a082 42 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 43 extern "C" {
mbed_official 573:ad23fe03a082 44 #endif
mbed_official 573:ad23fe03a082 45
mbed_official 573:ad23fe03a082 46 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 47 #include "stm32f7xx_hal_def.h"
mbed_official 573:ad23fe03a082 48
mbed_official 573:ad23fe03a082 49 /** @addtogroup STM32F7xx_Driver
mbed_official 573:ad23fe03a082 50 * @{
mbed_official 573:ad23fe03a082 51 */
mbed_official 573:ad23fe03a082 52
mbed_official 573:ad23fe03a082 53 /** @addtogroup SDMMC_LL
mbed_official 573:ad23fe03a082 54 * @{
mbed_official 573:ad23fe03a082 55 */
mbed_official 573:ad23fe03a082 56
mbed_official 573:ad23fe03a082 57 /* Exported types ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
mbed_official 573:ad23fe03a082 59 * @{
mbed_official 573:ad23fe03a082 60 */
mbed_official 573:ad23fe03a082 61
mbed_official 573:ad23fe03a082 62 /**
mbed_official 573:ad23fe03a082 63 * @brief SDMMC Configuration Structure definition
mbed_official 573:ad23fe03a082 64 */
mbed_official 573:ad23fe03a082 65 typedef struct
mbed_official 573:ad23fe03a082 66 {
mbed_official 573:ad23fe03a082 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
mbed_official 573:ad23fe03a082 68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
mbed_official 573:ad23fe03a082 69
mbed_official 573:ad23fe03a082 70 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
mbed_official 573:ad23fe03a082 71 enabled or disabled.
mbed_official 573:ad23fe03a082 72 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
mbed_official 573:ad23fe03a082 73
mbed_official 573:ad23fe03a082 74 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
mbed_official 573:ad23fe03a082 75 disabled when the bus is idle.
mbed_official 573:ad23fe03a082 76 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
mbed_official 573:ad23fe03a082 77
mbed_official 573:ad23fe03a082 78 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
mbed_official 573:ad23fe03a082 79 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
mbed_official 573:ad23fe03a082 80
mbed_official 573:ad23fe03a082 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
mbed_official 573:ad23fe03a082 82 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
mbed_official 573:ad23fe03a082 83
mbed_official 573:ad23fe03a082 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
mbed_official 573:ad23fe03a082 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 573:ad23fe03a082 86
mbed_official 573:ad23fe03a082 87 }SDMMC_InitTypeDef;
mbed_official 573:ad23fe03a082 88
mbed_official 573:ad23fe03a082 89
mbed_official 573:ad23fe03a082 90 /**
mbed_official 573:ad23fe03a082 91 * @brief SDMMC Command Control structure
mbed_official 573:ad23fe03a082 92 */
mbed_official 573:ad23fe03a082 93 typedef struct
mbed_official 573:ad23fe03a082 94 {
mbed_official 573:ad23fe03a082 95 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
mbed_official 573:ad23fe03a082 96 to a card as part of a command message. If a command
mbed_official 573:ad23fe03a082 97 contains an argument, it must be loaded into this register
mbed_official 573:ad23fe03a082 98 before writing the command to the command register. */
mbed_official 573:ad23fe03a082 99
mbed_official 573:ad23fe03a082 100 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
mbed_official 573:ad23fe03a082 101 Max_Data = 64 */
mbed_official 573:ad23fe03a082 102
mbed_official 573:ad23fe03a082 103 uint32_t Response; /*!< Specifies the SDMMC response type.
mbed_official 573:ad23fe03a082 104 This parameter can be a value of @ref SDMMC_LL_Response_Type */
mbed_official 573:ad23fe03a082 105
mbed_official 573:ad23fe03a082 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
mbed_official 573:ad23fe03a082 107 enabled or disabled.
mbed_official 573:ad23fe03a082 108 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
mbed_official 573:ad23fe03a082 109
mbed_official 573:ad23fe03a082 110 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
mbed_official 573:ad23fe03a082 111 is enabled or disabled.
mbed_official 573:ad23fe03a082 112 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
mbed_official 573:ad23fe03a082 113 }SDMMC_CmdInitTypeDef;
mbed_official 573:ad23fe03a082 114
mbed_official 573:ad23fe03a082 115
mbed_official 573:ad23fe03a082 116 /**
mbed_official 573:ad23fe03a082 117 * @brief SDMMC Data Control structure
mbed_official 573:ad23fe03a082 118 */
mbed_official 573:ad23fe03a082 119 typedef struct
mbed_official 573:ad23fe03a082 120 {
mbed_official 573:ad23fe03a082 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
mbed_official 573:ad23fe03a082 122
mbed_official 573:ad23fe03a082 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
mbed_official 573:ad23fe03a082 124
mbed_official 573:ad23fe03a082 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
mbed_official 573:ad23fe03a082 126 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
mbed_official 573:ad23fe03a082 127
mbed_official 573:ad23fe03a082 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
mbed_official 573:ad23fe03a082 129 is a read or write.
mbed_official 573:ad23fe03a082 130 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
mbed_official 573:ad23fe03a082 131
mbed_official 573:ad23fe03a082 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
mbed_official 573:ad23fe03a082 133 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
mbed_official 573:ad23fe03a082 134
mbed_official 573:ad23fe03a082 135 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
mbed_official 573:ad23fe03a082 136 is enabled or disabled.
mbed_official 573:ad23fe03a082 137 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
mbed_official 573:ad23fe03a082 138 }SDMMC_DataInitTypeDef;
mbed_official 573:ad23fe03a082 139
mbed_official 573:ad23fe03a082 140 /**
mbed_official 573:ad23fe03a082 141 * @}
mbed_official 573:ad23fe03a082 142 */
mbed_official 573:ad23fe03a082 143
mbed_official 573:ad23fe03a082 144 /* Exported constants --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
mbed_official 573:ad23fe03a082 146 * @{
mbed_official 573:ad23fe03a082 147 */
mbed_official 573:ad23fe03a082 148
mbed_official 573:ad23fe03a082 149 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
mbed_official 573:ad23fe03a082 150 * @{
mbed_official 573:ad23fe03a082 151 */
mbed_official 573:ad23fe03a082 152 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 153 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
mbed_official 573:ad23fe03a082 154
mbed_official 573:ad23fe03a082 155 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
mbed_official 573:ad23fe03a082 156 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
mbed_official 573:ad23fe03a082 157 /**
mbed_official 573:ad23fe03a082 158 * @}
mbed_official 573:ad23fe03a082 159 */
mbed_official 573:ad23fe03a082 160
mbed_official 573:ad23fe03a082 161 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
mbed_official 573:ad23fe03a082 162 * @{
mbed_official 573:ad23fe03a082 163 */
mbed_official 573:ad23fe03a082 164 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 165 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
mbed_official 573:ad23fe03a082 166
mbed_official 573:ad23fe03a082 167 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
mbed_official 573:ad23fe03a082 168 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
mbed_official 573:ad23fe03a082 169 /**
mbed_official 573:ad23fe03a082 170 * @}
mbed_official 573:ad23fe03a082 171 */
mbed_official 573:ad23fe03a082 172
mbed_official 573:ad23fe03a082 173 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
mbed_official 573:ad23fe03a082 174 * @{
mbed_official 573:ad23fe03a082 175 */
mbed_official 573:ad23fe03a082 176 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 177 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
mbed_official 573:ad23fe03a082 178
mbed_official 573:ad23fe03a082 179 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
mbed_official 573:ad23fe03a082 180 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
mbed_official 573:ad23fe03a082 181 /**
mbed_official 573:ad23fe03a082 182 * @}
mbed_official 573:ad23fe03a082 183 */
mbed_official 573:ad23fe03a082 184
mbed_official 573:ad23fe03a082 185 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
mbed_official 573:ad23fe03a082 186 * @{
mbed_official 573:ad23fe03a082 187 */
mbed_official 573:ad23fe03a082 188 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 189 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
mbed_official 573:ad23fe03a082 190 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
mbed_official 573:ad23fe03a082 191
mbed_official 573:ad23fe03a082 192 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
mbed_official 573:ad23fe03a082 193 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
mbed_official 573:ad23fe03a082 194 ((WIDE) == SDMMC_BUS_WIDE_8B))
mbed_official 573:ad23fe03a082 195 /**
mbed_official 573:ad23fe03a082 196 * @}
mbed_official 573:ad23fe03a082 197 */
mbed_official 573:ad23fe03a082 198
mbed_official 573:ad23fe03a082 199 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
mbed_official 573:ad23fe03a082 200 * @{
mbed_official 573:ad23fe03a082 201 */
mbed_official 573:ad23fe03a082 202 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 203 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
mbed_official 573:ad23fe03a082 204
mbed_official 573:ad23fe03a082 205 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
mbed_official 573:ad23fe03a082 206 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
mbed_official 573:ad23fe03a082 207 /**
mbed_official 573:ad23fe03a082 208 * @}
mbed_official 573:ad23fe03a082 209 */
mbed_official 573:ad23fe03a082 210
mbed_official 573:ad23fe03a082 211 /** @defgroup SDMMC_LL_Clock_Division Clock Division
mbed_official 573:ad23fe03a082 212 * @{
mbed_official 573:ad23fe03a082 213 */
mbed_official 573:ad23fe03a082 214 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
mbed_official 573:ad23fe03a082 215 /**
mbed_official 573:ad23fe03a082 216 * @}
mbed_official 573:ad23fe03a082 217 */
mbed_official 573:ad23fe03a082 218
mbed_official 573:ad23fe03a082 219 /** @defgroup SDMMC_LL_Command_Index Command Index
mbed_official 573:ad23fe03a082 220 * @{
mbed_official 573:ad23fe03a082 221 */
mbed_official 573:ad23fe03a082 222 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
mbed_official 573:ad23fe03a082 223 /**
mbed_official 573:ad23fe03a082 224 * @}
mbed_official 573:ad23fe03a082 225 */
mbed_official 573:ad23fe03a082 226
mbed_official 573:ad23fe03a082 227 /** @defgroup SDMMC_LL_Response_Type Response Type
mbed_official 573:ad23fe03a082 228 * @{
mbed_official 573:ad23fe03a082 229 */
mbed_official 573:ad23fe03a082 230 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 231 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
mbed_official 573:ad23fe03a082 232 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
mbed_official 573:ad23fe03a082 233
mbed_official 573:ad23fe03a082 234 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
mbed_official 573:ad23fe03a082 235 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
mbed_official 573:ad23fe03a082 236 ((RESPONSE) == SDMMC_RESPONSE_LONG))
mbed_official 573:ad23fe03a082 237 /**
mbed_official 573:ad23fe03a082 238 * @}
mbed_official 573:ad23fe03a082 239 */
mbed_official 573:ad23fe03a082 240
mbed_official 573:ad23fe03a082 241 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
mbed_official 573:ad23fe03a082 242 * @{
mbed_official 573:ad23fe03a082 243 */
mbed_official 573:ad23fe03a082 244 #define SDMMC_WAIT_NO ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 245 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
mbed_official 573:ad23fe03a082 246 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
mbed_official 573:ad23fe03a082 247
mbed_official 573:ad23fe03a082 248 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
mbed_official 573:ad23fe03a082 249 ((WAIT) == SDMMC_WAIT_IT) || \
mbed_official 573:ad23fe03a082 250 ((WAIT) == SDMMC_WAIT_PEND))
mbed_official 573:ad23fe03a082 251 /**
mbed_official 573:ad23fe03a082 252 * @}
mbed_official 573:ad23fe03a082 253 */
mbed_official 573:ad23fe03a082 254
mbed_official 573:ad23fe03a082 255 /** @defgroup SDMMC_LL_CPSM_State CPSM State
mbed_official 573:ad23fe03a082 256 * @{
mbed_official 573:ad23fe03a082 257 */
mbed_official 573:ad23fe03a082 258 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 259 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
mbed_official 573:ad23fe03a082 260
mbed_official 573:ad23fe03a082 261 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
mbed_official 573:ad23fe03a082 262 ((CPSM) == SDMMC_CPSM_ENABLE))
mbed_official 573:ad23fe03a082 263 /**
mbed_official 573:ad23fe03a082 264 * @}
mbed_official 573:ad23fe03a082 265 */
mbed_official 573:ad23fe03a082 266
mbed_official 573:ad23fe03a082 267 /** @defgroup SDMMC_LL_Response_Registers Response Register
mbed_official 573:ad23fe03a082 268 * @{
mbed_official 573:ad23fe03a082 269 */
mbed_official 573:ad23fe03a082 270 #define SDMMC_RESP1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 271 #define SDMMC_RESP2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 272 #define SDMMC_RESP3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 273 #define SDMMC_RESP4 ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 274
mbed_official 573:ad23fe03a082 275 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
mbed_official 573:ad23fe03a082 276 ((RESP) == SDMMC_RESP2) || \
mbed_official 573:ad23fe03a082 277 ((RESP) == SDMMC_RESP3) || \
mbed_official 573:ad23fe03a082 278 ((RESP) == SDMMC_RESP4))
mbed_official 573:ad23fe03a082 279 /**
mbed_official 573:ad23fe03a082 280 * @}
mbed_official 573:ad23fe03a082 281 */
mbed_official 573:ad23fe03a082 282
mbed_official 573:ad23fe03a082 283 /** @defgroup SDMMC_LL_Data_Length Data Lenght
mbed_official 573:ad23fe03a082 284 * @{
mbed_official 573:ad23fe03a082 285 */
mbed_official 573:ad23fe03a082 286 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
mbed_official 573:ad23fe03a082 287 /**
mbed_official 573:ad23fe03a082 288 * @}
mbed_official 573:ad23fe03a082 289 */
mbed_official 573:ad23fe03a082 290
mbed_official 573:ad23fe03a082 291 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
mbed_official 573:ad23fe03a082 292 * @{
mbed_official 573:ad23fe03a082 293 */
mbed_official 573:ad23fe03a082 294 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 295 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
mbed_official 573:ad23fe03a082 296 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
mbed_official 573:ad23fe03a082 297 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
mbed_official 573:ad23fe03a082 298 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
mbed_official 573:ad23fe03a082 299 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official 573:ad23fe03a082 300 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official 573:ad23fe03a082 301 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official 573:ad23fe03a082 302 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
mbed_official 573:ad23fe03a082 303 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 304 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 305 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 306 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 307 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 308 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official 573:ad23fe03a082 309
mbed_official 573:ad23fe03a082 310 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
mbed_official 573:ad23fe03a082 311 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
mbed_official 573:ad23fe03a082 312 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
mbed_official 573:ad23fe03a082 313 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
mbed_official 573:ad23fe03a082 314 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
mbed_official 573:ad23fe03a082 315 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
mbed_official 573:ad23fe03a082 316 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
mbed_official 573:ad23fe03a082 317 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
mbed_official 573:ad23fe03a082 318 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
mbed_official 573:ad23fe03a082 319 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
mbed_official 573:ad23fe03a082 320 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
mbed_official 573:ad23fe03a082 321 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
mbed_official 573:ad23fe03a082 322 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
mbed_official 573:ad23fe03a082 323 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
mbed_official 573:ad23fe03a082 324 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
mbed_official 573:ad23fe03a082 325 /**
mbed_official 573:ad23fe03a082 326 * @}
mbed_official 573:ad23fe03a082 327 */
mbed_official 573:ad23fe03a082 328
mbed_official 573:ad23fe03a082 329 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
mbed_official 573:ad23fe03a082 330 * @{
mbed_official 573:ad23fe03a082 331 */
mbed_official 573:ad23fe03a082 332 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 333 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
mbed_official 573:ad23fe03a082 334
mbed_official 573:ad23fe03a082 335 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
mbed_official 573:ad23fe03a082 336 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
mbed_official 573:ad23fe03a082 337 /**
mbed_official 573:ad23fe03a082 338 * @}
mbed_official 573:ad23fe03a082 339 */
mbed_official 573:ad23fe03a082 340
mbed_official 573:ad23fe03a082 341 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
mbed_official 573:ad23fe03a082 342 * @{
mbed_official 573:ad23fe03a082 343 */
mbed_official 573:ad23fe03a082 344 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 345 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
mbed_official 573:ad23fe03a082 346
mbed_official 573:ad23fe03a082 347 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
mbed_official 573:ad23fe03a082 348 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
mbed_official 573:ad23fe03a082 349 /**
mbed_official 573:ad23fe03a082 350 * @}
mbed_official 573:ad23fe03a082 351 */
mbed_official 573:ad23fe03a082 352
mbed_official 573:ad23fe03a082 353 /** @defgroup SDMMC_LL_DPSM_State DPSM State
mbed_official 573:ad23fe03a082 354 * @{
mbed_official 573:ad23fe03a082 355 */
mbed_official 573:ad23fe03a082 356 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 357 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
mbed_official 573:ad23fe03a082 358
mbed_official 573:ad23fe03a082 359 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
mbed_official 573:ad23fe03a082 360 ((DPSM) == SDMMC_DPSM_ENABLE))
mbed_official 573:ad23fe03a082 361 /**
mbed_official 573:ad23fe03a082 362 * @}
mbed_official 573:ad23fe03a082 363 */
mbed_official 573:ad23fe03a082 364
mbed_official 573:ad23fe03a082 365 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
mbed_official 573:ad23fe03a082 366 * @{
mbed_official 573:ad23fe03a082 367 */
mbed_official 573:ad23fe03a082 368 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 369 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
mbed_official 573:ad23fe03a082 370
mbed_official 573:ad23fe03a082 371 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
mbed_official 573:ad23fe03a082 372 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
mbed_official 573:ad23fe03a082 373 /**
mbed_official 573:ad23fe03a082 374 * @}
mbed_official 573:ad23fe03a082 375 */
mbed_official 573:ad23fe03a082 376
mbed_official 573:ad23fe03a082 377 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
mbed_official 573:ad23fe03a082 378 * @{
mbed_official 573:ad23fe03a082 379 */
mbed_official 573:ad23fe03a082 380 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
mbed_official 573:ad23fe03a082 381 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
mbed_official 573:ad23fe03a082 382 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
mbed_official 573:ad23fe03a082 383 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
mbed_official 573:ad23fe03a082 384 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
mbed_official 573:ad23fe03a082 385 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
mbed_official 573:ad23fe03a082 386 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
mbed_official 573:ad23fe03a082 387 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
mbed_official 573:ad23fe03a082 388 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
mbed_official 573:ad23fe03a082 389 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
mbed_official 573:ad23fe03a082 390 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
mbed_official 573:ad23fe03a082 391 #define SDMMC_IT_TXACT SDMMC_STA_TXACT
mbed_official 573:ad23fe03a082 392 #define SDMMC_IT_RXACT SDMMC_STA_RXACT
mbed_official 573:ad23fe03a082 393 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
mbed_official 573:ad23fe03a082 394 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
mbed_official 573:ad23fe03a082 395 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
mbed_official 573:ad23fe03a082 396 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
mbed_official 573:ad23fe03a082 397 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
mbed_official 573:ad23fe03a082 398 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
mbed_official 573:ad23fe03a082 399 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
mbed_official 573:ad23fe03a082 400 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
mbed_official 573:ad23fe03a082 401 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
mbed_official 573:ad23fe03a082 402 /**
mbed_official 573:ad23fe03a082 403 * @}
mbed_official 573:ad23fe03a082 404 */
mbed_official 573:ad23fe03a082 405
mbed_official 573:ad23fe03a082 406 /** @defgroup SDMMC_LL_Flags Flags
mbed_official 573:ad23fe03a082 407 * @{
mbed_official 573:ad23fe03a082 408 */
mbed_official 573:ad23fe03a082 409 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
mbed_official 573:ad23fe03a082 410 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
mbed_official 573:ad23fe03a082 411 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
mbed_official 573:ad23fe03a082 412 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
mbed_official 573:ad23fe03a082 413 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
mbed_official 573:ad23fe03a082 414 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
mbed_official 573:ad23fe03a082 415 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
mbed_official 573:ad23fe03a082 416 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
mbed_official 573:ad23fe03a082 417 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
mbed_official 573:ad23fe03a082 418 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
mbed_official 573:ad23fe03a082 419 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
mbed_official 573:ad23fe03a082 420 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
mbed_official 573:ad23fe03a082 421 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
mbed_official 573:ad23fe03a082 422 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
mbed_official 573:ad23fe03a082 423 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
mbed_official 573:ad23fe03a082 424 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
mbed_official 573:ad23fe03a082 425 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
mbed_official 573:ad23fe03a082 426 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
mbed_official 573:ad23fe03a082 427 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
mbed_official 573:ad23fe03a082 428 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
mbed_official 573:ad23fe03a082 429 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
mbed_official 573:ad23fe03a082 430 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
mbed_official 573:ad23fe03a082 431 /**
mbed_official 573:ad23fe03a082 432 * @}
mbed_official 573:ad23fe03a082 433 */
mbed_official 573:ad23fe03a082 434
mbed_official 573:ad23fe03a082 435 /**
mbed_official 573:ad23fe03a082 436 * @}
mbed_official 573:ad23fe03a082 437 */
mbed_official 573:ad23fe03a082 438
mbed_official 573:ad23fe03a082 439 /* Exported macro ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 440 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
mbed_official 573:ad23fe03a082 441 * @{
mbed_official 573:ad23fe03a082 442 */
mbed_official 573:ad23fe03a082 443
mbed_official 573:ad23fe03a082 444 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
mbed_official 573:ad23fe03a082 445 * @brief SDMMC_LL registers bit address in the alias region
mbed_official 573:ad23fe03a082 446 * @{
mbed_official 573:ad23fe03a082 447 */
mbed_official 573:ad23fe03a082 448 /* ---------------------- SDMMC registers bit mask --------------------------- */
mbed_official 573:ad23fe03a082 449 /* --- CLKCR Register ---*/
mbed_official 573:ad23fe03a082 450 /* CLKCR register clear mask */
mbed_official 573:ad23fe03a082 451 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
mbed_official 573:ad23fe03a082 452 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
mbed_official 573:ad23fe03a082 453 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
mbed_official 573:ad23fe03a082 454
mbed_official 573:ad23fe03a082 455 /* --- DCTRL Register ---*/
mbed_official 573:ad23fe03a082 456 /* SDMMC DCTRL Clear Mask */
mbed_official 573:ad23fe03a082 457 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
mbed_official 573:ad23fe03a082 458 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
mbed_official 573:ad23fe03a082 459
mbed_official 573:ad23fe03a082 460 /* --- CMD Register ---*/
mbed_official 573:ad23fe03a082 461 /* CMD Register clear mask */
mbed_official 573:ad23fe03a082 462 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
mbed_official 573:ad23fe03a082 463 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
mbed_official 573:ad23fe03a082 464 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
mbed_official 573:ad23fe03a082 465
mbed_official 573:ad23fe03a082 466 /* SDMMC Initialization Frequency (400KHz max) */
mbed_official 573:ad23fe03a082 467 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
mbed_official 573:ad23fe03a082 468
mbed_official 573:ad23fe03a082 469 /* SDMMC Data Transfer Frequency (25MHz max) */
mbed_official 573:ad23fe03a082 470 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
mbed_official 573:ad23fe03a082 471
mbed_official 573:ad23fe03a082 472 /**
mbed_official 573:ad23fe03a082 473 * @}
mbed_official 573:ad23fe03a082 474 */
mbed_official 573:ad23fe03a082 475
mbed_official 573:ad23fe03a082 476 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
mbed_official 573:ad23fe03a082 477 * @brief macros to handle interrupts and specific clock configurations
mbed_official 573:ad23fe03a082 478 * @{
mbed_official 573:ad23fe03a082 479 */
mbed_official 573:ad23fe03a082 480
mbed_official 573:ad23fe03a082 481 /**
mbed_official 573:ad23fe03a082 482 * @brief Enable the SDMMC device.
mbed_official 573:ad23fe03a082 483 * @param __INSTANCE__: SDMMC Instance
mbed_official 573:ad23fe03a082 484 * @retval None
mbed_official 573:ad23fe03a082 485 */
mbed_official 573:ad23fe03a082 486 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
mbed_official 573:ad23fe03a082 487
mbed_official 573:ad23fe03a082 488 /**
mbed_official 573:ad23fe03a082 489 * @brief Disable the SDMMC device.
mbed_official 573:ad23fe03a082 490 * @param __INSTANCE__: SDMMC Instance
mbed_official 573:ad23fe03a082 491 * @retval None
mbed_official 573:ad23fe03a082 492 */
mbed_official 573:ad23fe03a082 493 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
mbed_official 573:ad23fe03a082 494
mbed_official 573:ad23fe03a082 495 /**
mbed_official 573:ad23fe03a082 496 * @brief Enable the SDMMC DMA transfer.
mbed_official 573:ad23fe03a082 497 * @param __INSTANCE__: SDMMC Instance
mbed_official 573:ad23fe03a082 498 * @retval None
mbed_official 573:ad23fe03a082 499 */
mbed_official 573:ad23fe03a082 500 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
mbed_official 573:ad23fe03a082 501 /**
mbed_official 573:ad23fe03a082 502 * @brief Disable the SDMMC DMA transfer.
mbed_official 573:ad23fe03a082 503 * @param __INSTANCE__: SDMMC Instance
mbed_official 573:ad23fe03a082 504 * @retval None
mbed_official 573:ad23fe03a082 505 */
mbed_official 573:ad23fe03a082 506 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
mbed_official 573:ad23fe03a082 507
mbed_official 573:ad23fe03a082 508 /**
mbed_official 573:ad23fe03a082 509 * @brief Enable the SDMMC device interrupt.
mbed_official 573:ad23fe03a082 510 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 511 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
mbed_official 573:ad23fe03a082 512 * This parameter can be one or a combination of the following values:
mbed_official 573:ad23fe03a082 513 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 514 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 515 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 573:ad23fe03a082 516 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official 573:ad23fe03a082 517 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 573:ad23fe03a082 518 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 573:ad23fe03a082 519 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 520 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 573:ad23fe03a082 521 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 573:ad23fe03a082 522 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 523 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official 573:ad23fe03a082 524 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official 573:ad23fe03a082 525 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official 573:ad23fe03a082 526 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 573:ad23fe03a082 527 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 573:ad23fe03a082 528 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 573:ad23fe03a082 529 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 573:ad23fe03a082 530 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 573:ad23fe03a082 531 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 573:ad23fe03a082 532 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 573:ad23fe03a082 533 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 573:ad23fe03a082 534 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 573:ad23fe03a082 535 * @retval None
mbed_official 573:ad23fe03a082 536 */
mbed_official 573:ad23fe03a082 537 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
mbed_official 573:ad23fe03a082 538
mbed_official 573:ad23fe03a082 539 /**
mbed_official 573:ad23fe03a082 540 * @brief Disable the SDMMC device interrupt.
mbed_official 573:ad23fe03a082 541 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 542 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
mbed_official 573:ad23fe03a082 543 * This parameter can be one or a combination of the following values:
mbed_official 573:ad23fe03a082 544 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 545 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 546 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 573:ad23fe03a082 547 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official 573:ad23fe03a082 548 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 573:ad23fe03a082 549 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 573:ad23fe03a082 550 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 551 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 573:ad23fe03a082 552 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 573:ad23fe03a082 553 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 554 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official 573:ad23fe03a082 555 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official 573:ad23fe03a082 556 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official 573:ad23fe03a082 557 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 573:ad23fe03a082 558 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 573:ad23fe03a082 559 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 573:ad23fe03a082 560 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 573:ad23fe03a082 561 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 573:ad23fe03a082 562 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 573:ad23fe03a082 563 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 573:ad23fe03a082 564 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 573:ad23fe03a082 565 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 573:ad23fe03a082 566 * @retval None
mbed_official 573:ad23fe03a082 567 */
mbed_official 573:ad23fe03a082 568 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
mbed_official 573:ad23fe03a082 569
mbed_official 573:ad23fe03a082 570 /**
mbed_official 573:ad23fe03a082 571 * @brief Checks whether the specified SDMMC flag is set or not.
mbed_official 573:ad23fe03a082 572 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 573 * @param __FLAG__: specifies the flag to check.
mbed_official 573:ad23fe03a082 574 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 575 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 573:ad23fe03a082 576 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 573:ad23fe03a082 577 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
mbed_official 573:ad23fe03a082 578 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
mbed_official 573:ad23fe03a082 579 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 573:ad23fe03a082 580 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 573:ad23fe03a082 581 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 573:ad23fe03a082 582 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
mbed_official 573:ad23fe03a082 583 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 573:ad23fe03a082 584 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 573:ad23fe03a082 585 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
mbed_official 573:ad23fe03a082 586 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
mbed_official 573:ad23fe03a082 587 * @arg SDMMC_FLAG_RXACT: Data receive in progress
mbed_official 573:ad23fe03a082 588 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
mbed_official 573:ad23fe03a082 589 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
mbed_official 573:ad23fe03a082 590 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
mbed_official 573:ad23fe03a082 591 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
mbed_official 573:ad23fe03a082 592 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
mbed_official 573:ad23fe03a082 593 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
mbed_official 573:ad23fe03a082 594 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
mbed_official 573:ad23fe03a082 595 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
mbed_official 573:ad23fe03a082 596 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
mbed_official 573:ad23fe03a082 597 * @retval The new state of SDMMC_FLAG (SET or RESET).
mbed_official 573:ad23fe03a082 598 */
mbed_official 573:ad23fe03a082 599 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
mbed_official 573:ad23fe03a082 600
mbed_official 573:ad23fe03a082 601
mbed_official 573:ad23fe03a082 602 /**
mbed_official 573:ad23fe03a082 603 * @brief Clears the SDMMC pending flags.
mbed_official 573:ad23fe03a082 604 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 605 * @param __FLAG__: specifies the flag to clear.
mbed_official 573:ad23fe03a082 606 * This parameter can be one or a combination of the following values:
mbed_official 573:ad23fe03a082 607 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 573:ad23fe03a082 608 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 573:ad23fe03a082 609 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
mbed_official 573:ad23fe03a082 610 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
mbed_official 573:ad23fe03a082 611 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 573:ad23fe03a082 612 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 573:ad23fe03a082 613 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 573:ad23fe03a082 614 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
mbed_official 573:ad23fe03a082 615 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 573:ad23fe03a082 616 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 573:ad23fe03a082 617 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
mbed_official 573:ad23fe03a082 618 * @retval None
mbed_official 573:ad23fe03a082 619 */
mbed_official 573:ad23fe03a082 620 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
mbed_official 573:ad23fe03a082 621
mbed_official 573:ad23fe03a082 622 /**
mbed_official 573:ad23fe03a082 623 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
mbed_official 573:ad23fe03a082 624 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 625 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
mbed_official 573:ad23fe03a082 626 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 627 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 628 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 629 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 573:ad23fe03a082 630 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official 573:ad23fe03a082 631 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 573:ad23fe03a082 632 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 573:ad23fe03a082 633 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 634 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 573:ad23fe03a082 635 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 573:ad23fe03a082 636 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 637 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official 573:ad23fe03a082 638 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official 573:ad23fe03a082 639 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official 573:ad23fe03a082 640 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 573:ad23fe03a082 641 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 573:ad23fe03a082 642 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 573:ad23fe03a082 643 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 573:ad23fe03a082 644 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 573:ad23fe03a082 645 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 573:ad23fe03a082 646 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 573:ad23fe03a082 647 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 573:ad23fe03a082 648 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 573:ad23fe03a082 649 * @retval The new state of SDMMC_IT (SET or RESET).
mbed_official 573:ad23fe03a082 650 */
mbed_official 573:ad23fe03a082 651 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
mbed_official 573:ad23fe03a082 652
mbed_official 573:ad23fe03a082 653 /**
mbed_official 573:ad23fe03a082 654 * @brief Clears the SDMMC's interrupt pending bits.
mbed_official 573:ad23fe03a082 655 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 656 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official 573:ad23fe03a082 657 * This parameter can be one or a combination of the following values:
mbed_official 573:ad23fe03a082 658 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 659 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 573:ad23fe03a082 660 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 573:ad23fe03a082 661 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official 573:ad23fe03a082 662 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 573:ad23fe03a082 663 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 573:ad23fe03a082 664 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 573:ad23fe03a082 665 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 573:ad23fe03a082 666 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
mbed_official 573:ad23fe03a082 667 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 573:ad23fe03a082 668 * @retval None
mbed_official 573:ad23fe03a082 669 */
mbed_official 573:ad23fe03a082 670 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
mbed_official 573:ad23fe03a082 671
mbed_official 573:ad23fe03a082 672 /**
mbed_official 573:ad23fe03a082 673 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 573:ad23fe03a082 674 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 675 * @retval None
mbed_official 573:ad23fe03a082 676 */
mbed_official 573:ad23fe03a082 677 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
mbed_official 573:ad23fe03a082 678
mbed_official 573:ad23fe03a082 679 /**
mbed_official 573:ad23fe03a082 680 * @brief Disable Start the SD I/O Read Wait operations.
mbed_official 573:ad23fe03a082 681 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 682 * @retval None
mbed_official 573:ad23fe03a082 683 */
mbed_official 573:ad23fe03a082 684 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
mbed_official 573:ad23fe03a082 685
mbed_official 573:ad23fe03a082 686 /**
mbed_official 573:ad23fe03a082 687 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 573:ad23fe03a082 688 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 689 * @retval None
mbed_official 573:ad23fe03a082 690 */
mbed_official 573:ad23fe03a082 691 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
mbed_official 573:ad23fe03a082 692
mbed_official 573:ad23fe03a082 693 /**
mbed_official 573:ad23fe03a082 694 * @brief Disable Stop the SD I/O Read Wait operations.
mbed_official 573:ad23fe03a082 695 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 696 * @retval None
mbed_official 573:ad23fe03a082 697 */
mbed_official 573:ad23fe03a082 698 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
mbed_official 573:ad23fe03a082 699
mbed_official 573:ad23fe03a082 700 /**
mbed_official 573:ad23fe03a082 701 * @brief Enable the SD I/O Mode Operation.
mbed_official 573:ad23fe03a082 702 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 703 * @retval None
mbed_official 573:ad23fe03a082 704 */
mbed_official 573:ad23fe03a082 705 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
mbed_official 573:ad23fe03a082 706
mbed_official 573:ad23fe03a082 707 /**
mbed_official 573:ad23fe03a082 708 * @brief Disable the SD I/O Mode Operation.
mbed_official 573:ad23fe03a082 709 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 710 * @retval None
mbed_official 573:ad23fe03a082 711 */
mbed_official 573:ad23fe03a082 712 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
mbed_official 573:ad23fe03a082 713
mbed_official 573:ad23fe03a082 714 /**
mbed_official 573:ad23fe03a082 715 * @brief Enable the SD I/O Suspend command sending.
mbed_official 573:ad23fe03a082 716 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 717 * @retval None
mbed_official 573:ad23fe03a082 718 */
mbed_official 573:ad23fe03a082 719 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
mbed_official 573:ad23fe03a082 720
mbed_official 573:ad23fe03a082 721 /**
mbed_official 573:ad23fe03a082 722 * @brief Disable the SD I/O Suspend command sending.
mbed_official 573:ad23fe03a082 723 * @param __INSTANCE__ : Pointer to SDMMC register base
mbed_official 573:ad23fe03a082 724 * @retval None
mbed_official 573:ad23fe03a082 725 */
mbed_official 573:ad23fe03a082 726 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
mbed_official 573:ad23fe03a082 727
mbed_official 573:ad23fe03a082 728 /**
mbed_official 573:ad23fe03a082 729 * @}
mbed_official 573:ad23fe03a082 730 */
mbed_official 573:ad23fe03a082 731
mbed_official 573:ad23fe03a082 732 /**
mbed_official 573:ad23fe03a082 733 * @}
mbed_official 573:ad23fe03a082 734 */
mbed_official 573:ad23fe03a082 735
mbed_official 573:ad23fe03a082 736 /* Exported functions --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 737 /** @addtogroup SDMMC_LL_Exported_Functions
mbed_official 573:ad23fe03a082 738 * @{
mbed_official 573:ad23fe03a082 739 */
mbed_official 573:ad23fe03a082 740
mbed_official 573:ad23fe03a082 741 /* Initialization/de-initialization functions **********************************/
mbed_official 573:ad23fe03a082 742 /** @addtogroup HAL_SDMMC_LL_Group1
mbed_official 573:ad23fe03a082 743 * @{
mbed_official 573:ad23fe03a082 744 */
mbed_official 573:ad23fe03a082 745 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
mbed_official 573:ad23fe03a082 746 /**
mbed_official 573:ad23fe03a082 747 * @}
mbed_official 573:ad23fe03a082 748 */
mbed_official 573:ad23fe03a082 749
mbed_official 573:ad23fe03a082 750 /* I/O operation functions *****************************************************/
mbed_official 573:ad23fe03a082 751 /** @addtogroup HAL_SDMMC_LL_Group2
mbed_official 573:ad23fe03a082 752 * @{
mbed_official 573:ad23fe03a082 753 */
mbed_official 573:ad23fe03a082 754 /* Blocking mode: Polling */
mbed_official 573:ad23fe03a082 755 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 756 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
mbed_official 573:ad23fe03a082 757 /**
mbed_official 573:ad23fe03a082 758 * @}
mbed_official 573:ad23fe03a082 759 */
mbed_official 573:ad23fe03a082 760
mbed_official 573:ad23fe03a082 761 /* Peripheral Control functions ************************************************/
mbed_official 573:ad23fe03a082 762 /** @addtogroup HAL_SDMMC_LL_Group3
mbed_official 573:ad23fe03a082 763 * @{
mbed_official 573:ad23fe03a082 764 */
mbed_official 573:ad23fe03a082 765 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 766 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 767 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 768
mbed_official 573:ad23fe03a082 769 /* Command path state machine (CPSM) management functions */
mbed_official 573:ad23fe03a082 770 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
mbed_official 573:ad23fe03a082 771 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 772 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
mbed_official 573:ad23fe03a082 773
mbed_official 573:ad23fe03a082 774 /* Data path state machine (DPSM) management functions */
mbed_official 573:ad23fe03a082 775 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
mbed_official 573:ad23fe03a082 776 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 777 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
mbed_official 573:ad23fe03a082 778
mbed_official 573:ad23fe03a082 779 /* SDMMC Cards mode management functions */
mbed_official 573:ad23fe03a082 780 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
mbed_official 573:ad23fe03a082 781
mbed_official 573:ad23fe03a082 782 /**
mbed_official 573:ad23fe03a082 783 * @}
mbed_official 573:ad23fe03a082 784 */
mbed_official 573:ad23fe03a082 785
mbed_official 573:ad23fe03a082 786 /**
mbed_official 573:ad23fe03a082 787 * @}
mbed_official 573:ad23fe03a082 788 */
mbed_official 573:ad23fe03a082 789
mbed_official 573:ad23fe03a082 790 /**
mbed_official 573:ad23fe03a082 791 * @}
mbed_official 573:ad23fe03a082 792 */
mbed_official 573:ad23fe03a082 793
mbed_official 573:ad23fe03a082 794 /**
mbed_official 573:ad23fe03a082 795 * @}
mbed_official 573:ad23fe03a082 796 */
mbed_official 573:ad23fe03a082 797
mbed_official 573:ad23fe03a082 798 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 799 }
mbed_official 573:ad23fe03a082 800 #endif
mbed_official 573:ad23fe03a082 801
mbed_official 573:ad23fe03a082 802 #endif /* __STM32F7xx_LL_SDMMC_H */
mbed_official 573:ad23fe03a082 803
mbed_official 573:ad23fe03a082 804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/