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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Parent:
573:ad23fe03a082 
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_ll_fmc.c
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.1
mbed_official 610:813dcc80987e 6 * @date 25-June-2015
mbed_official 573:ad23fe03a082 7 * @brief FMC Low Layer HAL module driver.
mbed_official 573:ad23fe03a082 8 *
mbed_official 573:ad23fe03a082 9 * This file provides firmware functions to manage the following
mbed_official 573:ad23fe03a082 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
mbed_official 573:ad23fe03a082 11 * + Initialization/de-initialization functions
mbed_official 573:ad23fe03a082 12 * + Peripheral Control functions
mbed_official 573:ad23fe03a082 13 * + Peripheral State functions
mbed_official 573:ad23fe03a082 14 *
mbed_official 573:ad23fe03a082 15 @verbatim
mbed_official 573:ad23fe03a082 16 ==============================================================================
mbed_official 573:ad23fe03a082 17 ##### FMC peripheral features #####
mbed_official 573:ad23fe03a082 18 ==============================================================================
mbed_official 573:ad23fe03a082 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
mbed_official 573:ad23fe03a082 20 (+) The NOR/PSRAM memory controller
mbed_official 573:ad23fe03a082 21 (+) The NAND memory controller
mbed_official 573:ad23fe03a082 22 (+) The Synchronous DRAM (SDRAM) controller
mbed_official 573:ad23fe03a082 23
mbed_official 573:ad23fe03a082 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
mbed_official 573:ad23fe03a082 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
mbed_official 573:ad23fe03a082 26 (+) to translate AHB transactions into the appropriate external device protocol
mbed_official 573:ad23fe03a082 27 (+) to meet the access time requirements of the external memory devices
mbed_official 573:ad23fe03a082 28
mbed_official 573:ad23fe03a082 29 [..] All external memories share the addresses, data and control signals with the controller.
mbed_official 573:ad23fe03a082 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
mbed_official 573:ad23fe03a082 31 only one access at a time to an external device.
mbed_official 573:ad23fe03a082 32 The main features of the FMC controller are the following:
mbed_official 573:ad23fe03a082 33 (+) Interface with static-memory mapped devices including:
mbed_official 573:ad23fe03a082 34 (++) Static random access memory (SRAM)
mbed_official 573:ad23fe03a082 35 (++) Read-only memory (ROM)
mbed_official 573:ad23fe03a082 36 (++) NOR Flash memory/OneNAND Flash memory
mbed_official 573:ad23fe03a082 37 (++) PSRAM (4 memory banks)
mbed_official 573:ad23fe03a082 38 (++) 16-bit PC Card compatible devices
mbed_official 573:ad23fe03a082 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
mbed_official 573:ad23fe03a082 40 data
mbed_official 573:ad23fe03a082 41 (+) Interface with synchronous DRAM (SDRAM) memories
mbed_official 573:ad23fe03a082 42 (+) Independent Chip Select control for each memory bank
mbed_official 573:ad23fe03a082 43 (+) Independent configuration for each memory bank
mbed_official 573:ad23fe03a082 44
mbed_official 573:ad23fe03a082 45 @endverbatim
mbed_official 573:ad23fe03a082 46 ******************************************************************************
mbed_official 573:ad23fe03a082 47 * @attention
mbed_official 573:ad23fe03a082 48 *
mbed_official 573:ad23fe03a082 49 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 50 *
mbed_official 573:ad23fe03a082 51 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 52 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 53 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 54 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 56 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 57 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 59 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 60 * without specific prior written permission.
mbed_official 573:ad23fe03a082 61 *
mbed_official 573:ad23fe03a082 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 72 *
mbed_official 573:ad23fe03a082 73 ******************************************************************************
mbed_official 573:ad23fe03a082 74 */
mbed_official 573:ad23fe03a082 75
mbed_official 573:ad23fe03a082 76 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 77 #include "stm32f7xx_hal.h"
mbed_official 573:ad23fe03a082 78
mbed_official 573:ad23fe03a082 79 /** @addtogroup STM32F7xx_HAL_Driver
mbed_official 573:ad23fe03a082 80 * @{
mbed_official 573:ad23fe03a082 81 */
mbed_official 573:ad23fe03a082 82
mbed_official 573:ad23fe03a082 83 /** @defgroup FMC_LL FMC Low Layer
mbed_official 573:ad23fe03a082 84 * @brief FMC driver modules
mbed_official 573:ad23fe03a082 85 * @{
mbed_official 573:ad23fe03a082 86 */
mbed_official 573:ad23fe03a082 87
mbed_official 573:ad23fe03a082 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
mbed_official 573:ad23fe03a082 89
mbed_official 573:ad23fe03a082 90 /* Private typedef -----------------------------------------------------------*/
mbed_official 573:ad23fe03a082 91 /* Private define ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 92 /* Private macro -------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 93 /* Private variables ---------------------------------------------------------*/
mbed_official 573:ad23fe03a082 94 /* Private function prototypes -----------------------------------------------*/
mbed_official 573:ad23fe03a082 95 /* Exported functions --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 96
mbed_official 573:ad23fe03a082 97 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
mbed_official 573:ad23fe03a082 98 * @{
mbed_official 573:ad23fe03a082 99 */
mbed_official 573:ad23fe03a082 100
mbed_official 573:ad23fe03a082 101 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
mbed_official 573:ad23fe03a082 102 * @brief NORSRAM Controller functions
mbed_official 573:ad23fe03a082 103 *
mbed_official 573:ad23fe03a082 104 @verbatim
mbed_official 573:ad23fe03a082 105 ==============================================================================
mbed_official 573:ad23fe03a082 106 ##### How to use NORSRAM device driver #####
mbed_official 573:ad23fe03a082 107 ==============================================================================
mbed_official 573:ad23fe03a082 108
mbed_official 573:ad23fe03a082 109 [..]
mbed_official 573:ad23fe03a082 110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
mbed_official 573:ad23fe03a082 111 to run the NORSRAM external devices.
mbed_official 573:ad23fe03a082 112
mbed_official 573:ad23fe03a082 113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
mbed_official 573:ad23fe03a082 114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
mbed_official 573:ad23fe03a082 115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
mbed_official 573:ad23fe03a082 116 (+) FMC NORSRAM bank extended timing configuration using the function
mbed_official 573:ad23fe03a082 117 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 573:ad23fe03a082 118 (+) FMC NORSRAM bank enable/disable write operation using the functions
mbed_official 573:ad23fe03a082 119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
mbed_official 573:ad23fe03a082 120
mbed_official 573:ad23fe03a082 121
mbed_official 573:ad23fe03a082 122 @endverbatim
mbed_official 573:ad23fe03a082 123 * @{
mbed_official 573:ad23fe03a082 124 */
mbed_official 573:ad23fe03a082 125
mbed_official 573:ad23fe03a082 126 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 127 * @brief Initialization and Configuration functions
mbed_official 573:ad23fe03a082 128 *
mbed_official 573:ad23fe03a082 129 @verbatim
mbed_official 573:ad23fe03a082 130 ==============================================================================
mbed_official 573:ad23fe03a082 131 ##### Initialization and de_initialization functions #####
mbed_official 573:ad23fe03a082 132 ==============================================================================
mbed_official 573:ad23fe03a082 133 [..]
mbed_official 573:ad23fe03a082 134 This section provides functions allowing to:
mbed_official 573:ad23fe03a082 135 (+) Initialize and configure the FMC NORSRAM interface
mbed_official 573:ad23fe03a082 136 (+) De-initialize the FMC NORSRAM interface
mbed_official 573:ad23fe03a082 137 (+) Configure the FMC clock and associated GPIOs
mbed_official 573:ad23fe03a082 138
mbed_official 573:ad23fe03a082 139 @endverbatim
mbed_official 573:ad23fe03a082 140 * @{
mbed_official 573:ad23fe03a082 141 */
mbed_official 573:ad23fe03a082 142
mbed_official 573:ad23fe03a082 143 /**
mbed_official 573:ad23fe03a082 144 * @brief Initialize the FMC_NORSRAM device according to the specified
mbed_official 573:ad23fe03a082 145 * control parameters in the FMC_NORSRAM_InitTypeDef
mbed_official 573:ad23fe03a082 146 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 147 * @param Init: Pointer to NORSRAM Initialization structure
mbed_official 573:ad23fe03a082 148 * @retval HAL status
mbed_official 573:ad23fe03a082 149 */
mbed_official 573:ad23fe03a082 150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
mbed_official 573:ad23fe03a082 151 {
mbed_official 573:ad23fe03a082 152 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 153
mbed_official 573:ad23fe03a082 154 /* Check the parameters */
mbed_official 573:ad23fe03a082 155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
mbed_official 573:ad23fe03a082 157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
mbed_official 573:ad23fe03a082 158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
mbed_official 573:ad23fe03a082 159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 573:ad23fe03a082 160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
mbed_official 573:ad23fe03a082 161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
mbed_official 573:ad23fe03a082 162 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
mbed_official 573:ad23fe03a082 163 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
mbed_official 573:ad23fe03a082 164 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
mbed_official 573:ad23fe03a082 165 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
mbed_official 573:ad23fe03a082 166 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
mbed_official 573:ad23fe03a082 167 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
mbed_official 573:ad23fe03a082 168 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
mbed_official 573:ad23fe03a082 169 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
mbed_official 573:ad23fe03a082 170 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
mbed_official 573:ad23fe03a082 171
mbed_official 573:ad23fe03a082 172 /* Get the BTCR register value */
mbed_official 573:ad23fe03a082 173 tmpr = Device->BTCR[Init->NSBank];
mbed_official 573:ad23fe03a082 174
mbed_official 573:ad23fe03a082 175 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
mbed_official 573:ad23fe03a082 176 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
mbed_official 573:ad23fe03a082 177 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
mbed_official 573:ad23fe03a082 178 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
mbed_official 573:ad23fe03a082 179 FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \
mbed_official 573:ad23fe03a082 180 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
mbed_official 573:ad23fe03a082 181 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
mbed_official 573:ad23fe03a082 182
mbed_official 573:ad23fe03a082 183 /* Set NORSRAM device control parameters */
mbed_official 573:ad23fe03a082 184 tmpr |= (uint32_t)(Init->DataAddressMux |\
mbed_official 573:ad23fe03a082 185 Init->MemoryType |\
mbed_official 573:ad23fe03a082 186 Init->MemoryDataWidth |\
mbed_official 573:ad23fe03a082 187 Init->BurstAccessMode |\
mbed_official 573:ad23fe03a082 188 Init->WaitSignalPolarity |\
mbed_official 573:ad23fe03a082 189 Init->WaitSignalActive |\
mbed_official 573:ad23fe03a082 190 Init->WriteOperation |\
mbed_official 573:ad23fe03a082 191 Init->WaitSignal |\
mbed_official 573:ad23fe03a082 192 Init->ExtendedMode |\
mbed_official 573:ad23fe03a082 193 Init->AsynchronousWait |\
mbed_official 573:ad23fe03a082 194 Init->WriteBurst |\
mbed_official 573:ad23fe03a082 195 Init->ContinuousClock |\
mbed_official 573:ad23fe03a082 196 Init->PageSize |\
mbed_official 573:ad23fe03a082 197 Init->WriteFifo);
mbed_official 573:ad23fe03a082 198
mbed_official 573:ad23fe03a082 199 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
mbed_official 573:ad23fe03a082 200 {
mbed_official 573:ad23fe03a082 201 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
mbed_official 573:ad23fe03a082 202 }
mbed_official 573:ad23fe03a082 203
mbed_official 573:ad23fe03a082 204 Device->BTCR[Init->NSBank] = tmpr;
mbed_official 573:ad23fe03a082 205
mbed_official 573:ad23fe03a082 206 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
mbed_official 573:ad23fe03a082 207 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
mbed_official 573:ad23fe03a082 208 {
mbed_official 573:ad23fe03a082 209 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
mbed_official 573:ad23fe03a082 210 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
mbed_official 573:ad23fe03a082 211 Init->ContinuousClock);
mbed_official 573:ad23fe03a082 212 }
mbed_official 573:ad23fe03a082 213 if(Init->NSBank != FMC_NORSRAM_BANK1)
mbed_official 573:ad23fe03a082 214 {
mbed_official 573:ad23fe03a082 215 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
mbed_official 573:ad23fe03a082 216 }
mbed_official 573:ad23fe03a082 217
mbed_official 573:ad23fe03a082 218 return HAL_OK;
mbed_official 573:ad23fe03a082 219 }
mbed_official 573:ad23fe03a082 220
mbed_official 573:ad23fe03a082 221
mbed_official 573:ad23fe03a082 222 /**
mbed_official 573:ad23fe03a082 223 * @brief DeInitialize the FMC_NORSRAM peripheral
mbed_official 573:ad23fe03a082 224 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 225 * @param ExDevice: Pointer to NORSRAM extended mode device instance
mbed_official 573:ad23fe03a082 226 * @param Bank: NORSRAM bank number
mbed_official 573:ad23fe03a082 227 * @retval HAL status
mbed_official 573:ad23fe03a082 228 */
mbed_official 573:ad23fe03a082 229 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
mbed_official 573:ad23fe03a082 230 {
mbed_official 573:ad23fe03a082 231 /* Check the parameters */
mbed_official 573:ad23fe03a082 232 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 233 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
mbed_official 573:ad23fe03a082 234 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 235
mbed_official 573:ad23fe03a082 236 /* Disable the FMC_NORSRAM device */
mbed_official 573:ad23fe03a082 237 __FMC_NORSRAM_DISABLE(Device, Bank);
mbed_official 573:ad23fe03a082 238
mbed_official 573:ad23fe03a082 239 /* De-initialize the FMC_NORSRAM device */
mbed_official 573:ad23fe03a082 240 /* FMC_NORSRAM_BANK1 */
mbed_official 573:ad23fe03a082 241 if(Bank == FMC_NORSRAM_BANK1)
mbed_official 573:ad23fe03a082 242 {
mbed_official 573:ad23fe03a082 243 Device->BTCR[Bank] = 0x000030DB;
mbed_official 573:ad23fe03a082 244 }
mbed_official 573:ad23fe03a082 245 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
mbed_official 573:ad23fe03a082 246 else
mbed_official 573:ad23fe03a082 247 {
mbed_official 573:ad23fe03a082 248 Device->BTCR[Bank] = 0x000030D2;
mbed_official 573:ad23fe03a082 249 }
mbed_official 573:ad23fe03a082 250
mbed_official 573:ad23fe03a082 251 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
mbed_official 573:ad23fe03a082 252 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 573:ad23fe03a082 253
mbed_official 573:ad23fe03a082 254 return HAL_OK;
mbed_official 573:ad23fe03a082 255 }
mbed_official 573:ad23fe03a082 256
mbed_official 573:ad23fe03a082 257
mbed_official 573:ad23fe03a082 258 /**
mbed_official 573:ad23fe03a082 259 * @brief Initialize the FMC_NORSRAM Timing according to the specified
mbed_official 573:ad23fe03a082 260 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 573:ad23fe03a082 261 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 262 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 573:ad23fe03a082 263 * @param Bank: NORSRAM bank number
mbed_official 573:ad23fe03a082 264 * @retval HAL status
mbed_official 573:ad23fe03a082 265 */
mbed_official 573:ad23fe03a082 266 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 573:ad23fe03a082 267 {
mbed_official 573:ad23fe03a082 268 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 269
mbed_official 573:ad23fe03a082 270 /* Check the parameters */
mbed_official 573:ad23fe03a082 271 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 272 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 573:ad23fe03a082 273 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 573:ad23fe03a082 274 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 573:ad23fe03a082 275 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 573:ad23fe03a082 276 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 573:ad23fe03a082 277 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 573:ad23fe03a082 278 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 573:ad23fe03a082 279 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 280
mbed_official 573:ad23fe03a082 281 /* Get the BTCR register value */
mbed_official 573:ad23fe03a082 282 tmpr = Device->BTCR[Bank + 1];
mbed_official 573:ad23fe03a082 283
mbed_official 573:ad23fe03a082 284 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
mbed_official 573:ad23fe03a082 285 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
mbed_official 573:ad23fe03a082 286 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
mbed_official 573:ad23fe03a082 287 FMC_BTR1_ACCMOD));
mbed_official 573:ad23fe03a082 288
mbed_official 573:ad23fe03a082 289 /* Set FMC_NORSRAM device timing parameters */
mbed_official 573:ad23fe03a082 290 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
mbed_official 573:ad23fe03a082 291 ((Timing->AddressHoldTime) << 4) |\
mbed_official 573:ad23fe03a082 292 ((Timing->DataSetupTime) << 8) |\
mbed_official 573:ad23fe03a082 293 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 573:ad23fe03a082 294 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 573:ad23fe03a082 295 (((Timing->DataLatency)-2) << 24) |\
mbed_official 573:ad23fe03a082 296 (Timing->AccessMode)
mbed_official 573:ad23fe03a082 297 );
mbed_official 573:ad23fe03a082 298
mbed_official 573:ad23fe03a082 299 Device->BTCR[Bank + 1] = tmpr;
mbed_official 573:ad23fe03a082 300
mbed_official 573:ad23fe03a082 301 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
mbed_official 573:ad23fe03a082 302 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
mbed_official 573:ad23fe03a082 303 {
mbed_official 573:ad23fe03a082 304 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
mbed_official 573:ad23fe03a082 305 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
mbed_official 573:ad23fe03a082 306 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
mbed_official 573:ad23fe03a082 307 }
mbed_official 573:ad23fe03a082 308
mbed_official 573:ad23fe03a082 309 return HAL_OK;
mbed_official 573:ad23fe03a082 310 }
mbed_official 573:ad23fe03a082 311
mbed_official 573:ad23fe03a082 312 /**
mbed_official 573:ad23fe03a082 313 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
mbed_official 573:ad23fe03a082 314 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 573:ad23fe03a082 315 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 316 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 573:ad23fe03a082 317 * @param Bank: NORSRAM bank number
mbed_official 573:ad23fe03a082 318 * @retval HAL status
mbed_official 573:ad23fe03a082 319 */
mbed_official 573:ad23fe03a082 320 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
mbed_official 573:ad23fe03a082 321 {
mbed_official 573:ad23fe03a082 322 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 323
mbed_official 573:ad23fe03a082 324 /* Check the parameters */
mbed_official 573:ad23fe03a082 325 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
mbed_official 573:ad23fe03a082 326
mbed_official 573:ad23fe03a082 327 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
mbed_official 573:ad23fe03a082 328 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
mbed_official 573:ad23fe03a082 329 {
mbed_official 573:ad23fe03a082 330 /* Check the parameters */
mbed_official 573:ad23fe03a082 331 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
mbed_official 573:ad23fe03a082 332 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 573:ad23fe03a082 333 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 573:ad23fe03a082 334 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 573:ad23fe03a082 335 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 573:ad23fe03a082 336 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 573:ad23fe03a082 337 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 573:ad23fe03a082 338 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 573:ad23fe03a082 339 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 340
mbed_official 573:ad23fe03a082 341 /* Get the BWTR register value */
mbed_official 573:ad23fe03a082 342 tmpr = Device->BWTR[Bank];
mbed_official 573:ad23fe03a082 343
mbed_official 573:ad23fe03a082 344 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
mbed_official 573:ad23fe03a082 345 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
mbed_official 573:ad23fe03a082 346 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
mbed_official 573:ad23fe03a082 347
mbed_official 573:ad23fe03a082 348 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
mbed_official 573:ad23fe03a082 349 ((Timing->AddressHoldTime) << 4) |\
mbed_official 573:ad23fe03a082 350 ((Timing->DataSetupTime) << 8) |\
mbed_official 573:ad23fe03a082 351 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 573:ad23fe03a082 352 (Timing->AccessMode));
mbed_official 573:ad23fe03a082 353
mbed_official 573:ad23fe03a082 354 Device->BWTR[Bank] = tmpr;
mbed_official 573:ad23fe03a082 355 }
mbed_official 573:ad23fe03a082 356 else
mbed_official 573:ad23fe03a082 357 {
mbed_official 573:ad23fe03a082 358 Device->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 573:ad23fe03a082 359 }
mbed_official 573:ad23fe03a082 360
mbed_official 573:ad23fe03a082 361 return HAL_OK;
mbed_official 573:ad23fe03a082 362 }
mbed_official 573:ad23fe03a082 363 /**
mbed_official 573:ad23fe03a082 364 * @}
mbed_official 573:ad23fe03a082 365 */
mbed_official 573:ad23fe03a082 366
mbed_official 573:ad23fe03a082 367 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
mbed_official 573:ad23fe03a082 368 * @brief management functions
mbed_official 573:ad23fe03a082 369 *
mbed_official 573:ad23fe03a082 370 @verbatim
mbed_official 573:ad23fe03a082 371 ==============================================================================
mbed_official 573:ad23fe03a082 372 ##### FMC_NORSRAM Control functions #####
mbed_official 573:ad23fe03a082 373 ==============================================================================
mbed_official 573:ad23fe03a082 374 [..]
mbed_official 573:ad23fe03a082 375 This subsection provides a set of functions allowing to control dynamically
mbed_official 573:ad23fe03a082 376 the FMC NORSRAM interface.
mbed_official 573:ad23fe03a082 377
mbed_official 573:ad23fe03a082 378 @endverbatim
mbed_official 573:ad23fe03a082 379 * @{
mbed_official 573:ad23fe03a082 380 */
mbed_official 573:ad23fe03a082 381
mbed_official 573:ad23fe03a082 382 /**
mbed_official 573:ad23fe03a082 383 * @brief Enables dynamically FMC_NORSRAM write operation.
mbed_official 573:ad23fe03a082 384 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 385 * @param Bank: NORSRAM bank number
mbed_official 573:ad23fe03a082 386 * @retval HAL status
mbed_official 573:ad23fe03a082 387 */
mbed_official 573:ad23fe03a082 388 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 389 {
mbed_official 573:ad23fe03a082 390 /* Check the parameters */
mbed_official 573:ad23fe03a082 391 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 392 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 393
mbed_official 573:ad23fe03a082 394 /* Enable write operation */
mbed_official 573:ad23fe03a082 395 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
mbed_official 573:ad23fe03a082 396
mbed_official 573:ad23fe03a082 397 return HAL_OK;
mbed_official 573:ad23fe03a082 398 }
mbed_official 573:ad23fe03a082 399
mbed_official 573:ad23fe03a082 400 /**
mbed_official 573:ad23fe03a082 401 * @brief Disables dynamically FMC_NORSRAM write operation.
mbed_official 573:ad23fe03a082 402 * @param Device: Pointer to NORSRAM device instance
mbed_official 573:ad23fe03a082 403 * @param Bank: NORSRAM bank number
mbed_official 573:ad23fe03a082 404 * @retval HAL status
mbed_official 573:ad23fe03a082 405 */
mbed_official 573:ad23fe03a082 406 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 407 {
mbed_official 573:ad23fe03a082 408 /* Check the parameters */
mbed_official 573:ad23fe03a082 409 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 410 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 411
mbed_official 573:ad23fe03a082 412 /* Disable write operation */
mbed_official 573:ad23fe03a082 413 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
mbed_official 573:ad23fe03a082 414
mbed_official 573:ad23fe03a082 415 return HAL_OK;
mbed_official 573:ad23fe03a082 416 }
mbed_official 573:ad23fe03a082 417
mbed_official 573:ad23fe03a082 418 /**
mbed_official 573:ad23fe03a082 419 * @}
mbed_official 573:ad23fe03a082 420 */
mbed_official 573:ad23fe03a082 421
mbed_official 573:ad23fe03a082 422 /**
mbed_official 573:ad23fe03a082 423 * @}
mbed_official 573:ad23fe03a082 424 */
mbed_official 573:ad23fe03a082 425
mbed_official 573:ad23fe03a082 426 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
mbed_official 573:ad23fe03a082 427 * @brief NAND Controller functions
mbed_official 573:ad23fe03a082 428 *
mbed_official 573:ad23fe03a082 429 @verbatim
mbed_official 573:ad23fe03a082 430 ==============================================================================
mbed_official 573:ad23fe03a082 431 ##### How to use NAND device driver #####
mbed_official 573:ad23fe03a082 432 ==============================================================================
mbed_official 573:ad23fe03a082 433 [..]
mbed_official 573:ad23fe03a082 434 This driver contains a set of APIs to interface with the FMC NAND banks in order
mbed_official 573:ad23fe03a082 435 to run the NAND external devices.
mbed_official 573:ad23fe03a082 436
mbed_official 573:ad23fe03a082 437 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
mbed_official 573:ad23fe03a082 438 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
mbed_official 573:ad23fe03a082 439 (+) FMC NAND bank common space timing configuration using the function
mbed_official 573:ad23fe03a082 440 FMC_NAND_CommonSpace_Timing_Init()
mbed_official 573:ad23fe03a082 441 (+) FMC NAND bank attribute space timing configuration using the function
mbed_official 573:ad23fe03a082 442 FMC_NAND_AttributeSpace_Timing_Init()
mbed_official 573:ad23fe03a082 443 (+) FMC NAND bank enable/disable ECC correction feature using the functions
mbed_official 573:ad23fe03a082 444 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
mbed_official 573:ad23fe03a082 445 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
mbed_official 573:ad23fe03a082 446
mbed_official 573:ad23fe03a082 447 @endverbatim
mbed_official 573:ad23fe03a082 448 * @{
mbed_official 573:ad23fe03a082 449 */
mbed_official 573:ad23fe03a082 450
mbed_official 573:ad23fe03a082 451 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 452 * @brief Initialization and Configuration functions
mbed_official 573:ad23fe03a082 453 *
mbed_official 573:ad23fe03a082 454 @verbatim
mbed_official 573:ad23fe03a082 455 ==============================================================================
mbed_official 573:ad23fe03a082 456 ##### Initialization and de_initialization functions #####
mbed_official 573:ad23fe03a082 457 ==============================================================================
mbed_official 573:ad23fe03a082 458 [..]
mbed_official 573:ad23fe03a082 459 This section provides functions allowing to:
mbed_official 573:ad23fe03a082 460 (+) Initialize and configure the FMC NAND interface
mbed_official 573:ad23fe03a082 461 (+) De-initialize the FMC NAND interface
mbed_official 573:ad23fe03a082 462 (+) Configure the FMC clock and associated GPIOs
mbed_official 573:ad23fe03a082 463
mbed_official 573:ad23fe03a082 464 @endverbatim
mbed_official 573:ad23fe03a082 465 * @{
mbed_official 573:ad23fe03a082 466 */
mbed_official 573:ad23fe03a082 467
mbed_official 573:ad23fe03a082 468 /**
mbed_official 573:ad23fe03a082 469 * @brief Initializes the FMC_NAND device according to the specified
mbed_official 573:ad23fe03a082 470 * control parameters in the FMC_NAND_HandleTypeDef
mbed_official 573:ad23fe03a082 471 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 472 * @param Init: Pointer to NAND Initialization structure
mbed_official 573:ad23fe03a082 473 * @retval HAL status
mbed_official 573:ad23fe03a082 474 */
mbed_official 573:ad23fe03a082 475 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
mbed_official 573:ad23fe03a082 476 {
mbed_official 573:ad23fe03a082 477 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 478
mbed_official 573:ad23fe03a082 479 /* Check the parameters */
mbed_official 573:ad23fe03a082 480 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 481 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
mbed_official 573:ad23fe03a082 482 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 573:ad23fe03a082 483 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 573:ad23fe03a082 484 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
mbed_official 573:ad23fe03a082 485 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
mbed_official 573:ad23fe03a082 486 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 573:ad23fe03a082 487 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 573:ad23fe03a082 488
mbed_official 573:ad23fe03a082 489 /* Get the NAND bank 3 register value */
mbed_official 573:ad23fe03a082 490 tmpr = Device->PCR;
mbed_official 573:ad23fe03a082 491
mbed_official 573:ad23fe03a082 492 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
mbed_official 573:ad23fe03a082 493 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
mbed_official 573:ad23fe03a082 494 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
mbed_official 573:ad23fe03a082 495 FMC_PCR_TAR | FMC_PCR_ECCPS));
mbed_official 573:ad23fe03a082 496 /* Set NAND device control parameters */
mbed_official 573:ad23fe03a082 497 tmpr |= (uint32_t)(Init->Waitfeature |\
mbed_official 573:ad23fe03a082 498 FMC_PCR_MEMORY_TYPE_NAND |\
mbed_official 573:ad23fe03a082 499 Init->MemoryDataWidth |\
mbed_official 573:ad23fe03a082 500 Init->EccComputation |\
mbed_official 573:ad23fe03a082 501 Init->ECCPageSize |\
mbed_official 573:ad23fe03a082 502 ((Init->TCLRSetupTime) << 9) |\
mbed_official 573:ad23fe03a082 503 ((Init->TARSetupTime) << 13));
mbed_official 573:ad23fe03a082 504
mbed_official 573:ad23fe03a082 505 /* NAND bank 3 registers configuration */
mbed_official 573:ad23fe03a082 506 Device->PCR = tmpr;
mbed_official 573:ad23fe03a082 507
mbed_official 573:ad23fe03a082 508 return HAL_OK;
mbed_official 573:ad23fe03a082 509
mbed_official 573:ad23fe03a082 510 }
mbed_official 573:ad23fe03a082 511
mbed_official 573:ad23fe03a082 512 /**
mbed_official 573:ad23fe03a082 513 * @brief Initializes the FMC_NAND Common space Timing according to the specified
mbed_official 573:ad23fe03a082 514 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 573:ad23fe03a082 515 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 516 * @param Timing: Pointer to NAND timing structure
mbed_official 573:ad23fe03a082 517 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 518 * @retval HAL status
mbed_official 573:ad23fe03a082 519 */
mbed_official 573:ad23fe03a082 520 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 573:ad23fe03a082 521 {
mbed_official 573:ad23fe03a082 522 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 523
mbed_official 573:ad23fe03a082 524 /* Check the parameters */
mbed_official 573:ad23fe03a082 525 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 526 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 573:ad23fe03a082 527 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 573:ad23fe03a082 528 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 573:ad23fe03a082 529 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 573:ad23fe03a082 530 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 531
mbed_official 573:ad23fe03a082 532 /* Get the NAND bank 3 register value */
mbed_official 573:ad23fe03a082 533 tmpr = Device->PMEM;
mbed_official 573:ad23fe03a082 534
mbed_official 573:ad23fe03a082 535 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
mbed_official 573:ad23fe03a082 536 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
mbed_official 573:ad23fe03a082 537 FMC_PMEM_MEMHIZ3));
mbed_official 573:ad23fe03a082 538 /* Set FMC_NAND device timing parameters */
mbed_official 573:ad23fe03a082 539 tmpr |= (uint32_t)(Timing->SetupTime |\
mbed_official 573:ad23fe03a082 540 ((Timing->WaitSetupTime) << 8) |\
mbed_official 573:ad23fe03a082 541 ((Timing->HoldSetupTime) << 16) |\
mbed_official 573:ad23fe03a082 542 ((Timing->HiZSetupTime) << 24)
mbed_official 573:ad23fe03a082 543 );
mbed_official 573:ad23fe03a082 544
mbed_official 573:ad23fe03a082 545 /* NAND bank 3 registers configuration */
mbed_official 573:ad23fe03a082 546 Device->PMEM = tmpr;
mbed_official 573:ad23fe03a082 547
mbed_official 573:ad23fe03a082 548 return HAL_OK;
mbed_official 573:ad23fe03a082 549 }
mbed_official 573:ad23fe03a082 550
mbed_official 573:ad23fe03a082 551 /**
mbed_official 573:ad23fe03a082 552 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
mbed_official 573:ad23fe03a082 553 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 573:ad23fe03a082 554 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 555 * @param Timing: Pointer to NAND timing structure
mbed_official 573:ad23fe03a082 556 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 557 * @retval HAL status
mbed_official 573:ad23fe03a082 558 */
mbed_official 573:ad23fe03a082 559 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 573:ad23fe03a082 560 {
mbed_official 573:ad23fe03a082 561 uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 562
mbed_official 573:ad23fe03a082 563 /* Check the parameters */
mbed_official 573:ad23fe03a082 564 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 565 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 573:ad23fe03a082 566 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 573:ad23fe03a082 567 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 573:ad23fe03a082 568 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 573:ad23fe03a082 569 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 570
mbed_official 573:ad23fe03a082 571 /* Get the NAND bank 3 register value */
mbed_official 573:ad23fe03a082 572 tmpr = Device->PATT;
mbed_official 573:ad23fe03a082 573
mbed_official 573:ad23fe03a082 574 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
mbed_official 573:ad23fe03a082 575 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
mbed_official 573:ad23fe03a082 576 FMC_PATT_ATTHIZ3));
mbed_official 573:ad23fe03a082 577 /* Set FMC_NAND device timing parameters */
mbed_official 573:ad23fe03a082 578 tmpr |= (uint32_t)(Timing->SetupTime |\
mbed_official 573:ad23fe03a082 579 ((Timing->WaitSetupTime) << 8) |\
mbed_official 573:ad23fe03a082 580 ((Timing->HoldSetupTime) << 16) |\
mbed_official 573:ad23fe03a082 581 ((Timing->HiZSetupTime) << 24));
mbed_official 573:ad23fe03a082 582
mbed_official 573:ad23fe03a082 583 /* NAND bank 3 registers configuration */
mbed_official 573:ad23fe03a082 584 Device->PATT = tmpr;
mbed_official 573:ad23fe03a082 585
mbed_official 573:ad23fe03a082 586 return HAL_OK;
mbed_official 573:ad23fe03a082 587 }
mbed_official 573:ad23fe03a082 588
mbed_official 573:ad23fe03a082 589 /**
mbed_official 573:ad23fe03a082 590 * @brief DeInitializes the FMC_NAND device
mbed_official 573:ad23fe03a082 591 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 592 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 593 * @retval HAL status
mbed_official 573:ad23fe03a082 594 */
mbed_official 573:ad23fe03a082 595 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 596 {
mbed_official 573:ad23fe03a082 597 /* Check the parameters */
mbed_official 573:ad23fe03a082 598 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 599 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 600
mbed_official 573:ad23fe03a082 601 /* Disable the NAND Bank */
mbed_official 573:ad23fe03a082 602 __FMC_NAND_DISABLE(Device);
mbed_official 573:ad23fe03a082 603
mbed_official 573:ad23fe03a082 604 /* Set the FMC_NAND_BANK3 registers to their reset values */
mbed_official 573:ad23fe03a082 605 Device->PCR = 0x00000018;
mbed_official 573:ad23fe03a082 606 Device->SR = 0x00000040;
mbed_official 573:ad23fe03a082 607 Device->PMEM = 0xFCFCFCFC;
mbed_official 573:ad23fe03a082 608 Device->PATT = 0xFCFCFCFC;
mbed_official 573:ad23fe03a082 609
mbed_official 573:ad23fe03a082 610 return HAL_OK;
mbed_official 573:ad23fe03a082 611 }
mbed_official 573:ad23fe03a082 612
mbed_official 573:ad23fe03a082 613 /**
mbed_official 573:ad23fe03a082 614 * @}
mbed_official 573:ad23fe03a082 615 */
mbed_official 573:ad23fe03a082 616
mbed_official 573:ad23fe03a082 617 /** @defgroup HAL_FMC_NAND_Group3 Control functions
mbed_official 573:ad23fe03a082 618 * @brief management functions
mbed_official 573:ad23fe03a082 619 *
mbed_official 573:ad23fe03a082 620 @verbatim
mbed_official 573:ad23fe03a082 621 ==============================================================================
mbed_official 573:ad23fe03a082 622 ##### FMC_NAND Control functions #####
mbed_official 573:ad23fe03a082 623 ==============================================================================
mbed_official 573:ad23fe03a082 624 [..]
mbed_official 573:ad23fe03a082 625 This subsection provides a set of functions allowing to control dynamically
mbed_official 573:ad23fe03a082 626 the FMC NAND interface.
mbed_official 573:ad23fe03a082 627
mbed_official 573:ad23fe03a082 628 @endverbatim
mbed_official 573:ad23fe03a082 629 * @{
mbed_official 573:ad23fe03a082 630 */
mbed_official 573:ad23fe03a082 631
mbed_official 573:ad23fe03a082 632
mbed_official 573:ad23fe03a082 633 /**
mbed_official 573:ad23fe03a082 634 * @brief Enables dynamically FMC_NAND ECC feature.
mbed_official 573:ad23fe03a082 635 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 636 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 637 * @retval HAL status
mbed_official 573:ad23fe03a082 638 */
mbed_official 573:ad23fe03a082 639 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 640 {
mbed_official 573:ad23fe03a082 641 /* Check the parameters */
mbed_official 573:ad23fe03a082 642 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 643 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 644
mbed_official 573:ad23fe03a082 645 /* Enable ECC feature */
mbed_official 573:ad23fe03a082 646 Device->PCR |= FMC_PCR_ECCEN;
mbed_official 573:ad23fe03a082 647
mbed_official 573:ad23fe03a082 648 return HAL_OK;
mbed_official 573:ad23fe03a082 649 }
mbed_official 573:ad23fe03a082 650
mbed_official 573:ad23fe03a082 651
mbed_official 573:ad23fe03a082 652 /**
mbed_official 573:ad23fe03a082 653 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 573:ad23fe03a082 654 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 655 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 656 * @retval HAL status
mbed_official 573:ad23fe03a082 657 */
mbed_official 573:ad23fe03a082 658 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 659 {
mbed_official 573:ad23fe03a082 660 /* Check the parameters */
mbed_official 573:ad23fe03a082 661 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 662 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 663
mbed_official 573:ad23fe03a082 664 /* Disable ECC feature */
mbed_official 573:ad23fe03a082 665 Device->PCR &= ~FMC_PCR_ECCEN;
mbed_official 573:ad23fe03a082 666
mbed_official 573:ad23fe03a082 667 return HAL_OK;
mbed_official 573:ad23fe03a082 668 }
mbed_official 573:ad23fe03a082 669
mbed_official 573:ad23fe03a082 670 /**
mbed_official 573:ad23fe03a082 671 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 573:ad23fe03a082 672 * @param Device: Pointer to NAND device instance
mbed_official 573:ad23fe03a082 673 * @param ECCval: Pointer to ECC value
mbed_official 573:ad23fe03a082 674 * @param Bank: NAND bank number
mbed_official 573:ad23fe03a082 675 * @param Timeout: Timeout wait value
mbed_official 573:ad23fe03a082 676 * @retval HAL status
mbed_official 573:ad23fe03a082 677 */
mbed_official 573:ad23fe03a082 678 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
mbed_official 573:ad23fe03a082 679 {
mbed_official 573:ad23fe03a082 680 uint32_t tickstart = 0;
mbed_official 573:ad23fe03a082 681
mbed_official 573:ad23fe03a082 682 /* Check the parameters */
mbed_official 573:ad23fe03a082 683 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 573:ad23fe03a082 684 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 573:ad23fe03a082 685
mbed_official 573:ad23fe03a082 686 /* Get tick */
mbed_official 573:ad23fe03a082 687 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 688
mbed_official 573:ad23fe03a082 689 /* Wait until FIFO is empty */
mbed_official 573:ad23fe03a082 690 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
mbed_official 573:ad23fe03a082 691 {
mbed_official 573:ad23fe03a082 692 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 693 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 694 {
mbed_official 573:ad23fe03a082 695 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 573:ad23fe03a082 696 {
mbed_official 573:ad23fe03a082 697 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 698 }
mbed_official 573:ad23fe03a082 699 }
mbed_official 573:ad23fe03a082 700 }
mbed_official 573:ad23fe03a082 701
mbed_official 573:ad23fe03a082 702 /* Get the ECCR register value */
mbed_official 573:ad23fe03a082 703 *ECCval = (uint32_t)Device->ECCR;
mbed_official 573:ad23fe03a082 704
mbed_official 573:ad23fe03a082 705 return HAL_OK;
mbed_official 573:ad23fe03a082 706 }
mbed_official 573:ad23fe03a082 707
mbed_official 573:ad23fe03a082 708 /**
mbed_official 573:ad23fe03a082 709 * @}
mbed_official 573:ad23fe03a082 710 */
mbed_official 573:ad23fe03a082 711
mbed_official 573:ad23fe03a082 712 /**
mbed_official 573:ad23fe03a082 713 * @}
mbed_official 573:ad23fe03a082 714 */
mbed_official 573:ad23fe03a082 715
mbed_official 573:ad23fe03a082 716 /** @defgroup FMC_LL_SDRAM
mbed_official 573:ad23fe03a082 717 * @brief SDRAM Controller functions
mbed_official 573:ad23fe03a082 718 *
mbed_official 573:ad23fe03a082 719 @verbatim
mbed_official 573:ad23fe03a082 720 ==============================================================================
mbed_official 573:ad23fe03a082 721 ##### How to use SDRAM device driver #####
mbed_official 573:ad23fe03a082 722 ==============================================================================
mbed_official 573:ad23fe03a082 723 [..]
mbed_official 573:ad23fe03a082 724 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
mbed_official 573:ad23fe03a082 725 to run the SDRAM external devices.
mbed_official 573:ad23fe03a082 726
mbed_official 573:ad23fe03a082 727 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
mbed_official 573:ad23fe03a082 728 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
mbed_official 573:ad23fe03a082 729 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
mbed_official 573:ad23fe03a082 730 (+) FMC SDRAM bank enable/disable write operation using the functions
mbed_official 573:ad23fe03a082 731 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
mbed_official 573:ad23fe03a082 732 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
mbed_official 573:ad23fe03a082 733
mbed_official 573:ad23fe03a082 734 @endverbatim
mbed_official 573:ad23fe03a082 735 * @{
mbed_official 573:ad23fe03a082 736 */
mbed_official 573:ad23fe03a082 737
mbed_official 573:ad23fe03a082 738 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
mbed_official 573:ad23fe03a082 739 * @brief Initialization and Configuration functions
mbed_official 573:ad23fe03a082 740 *
mbed_official 573:ad23fe03a082 741 @verbatim
mbed_official 573:ad23fe03a082 742 ==============================================================================
mbed_official 573:ad23fe03a082 743 ##### Initialization and de_initialization functions #####
mbed_official 573:ad23fe03a082 744 ==============================================================================
mbed_official 573:ad23fe03a082 745 [..]
mbed_official 573:ad23fe03a082 746 This section provides functions allowing to:
mbed_official 573:ad23fe03a082 747 (+) Initialize and configure the FMC SDRAM interface
mbed_official 573:ad23fe03a082 748 (+) De-initialize the FMC SDRAM interface
mbed_official 573:ad23fe03a082 749 (+) Configure the FMC clock and associated GPIOs
mbed_official 573:ad23fe03a082 750
mbed_official 573:ad23fe03a082 751 @endverbatim
mbed_official 573:ad23fe03a082 752 * @{
mbed_official 573:ad23fe03a082 753 */
mbed_official 573:ad23fe03a082 754
mbed_official 573:ad23fe03a082 755 /**
mbed_official 573:ad23fe03a082 756 * @brief Initializes the FMC_SDRAM device according to the specified
mbed_official 573:ad23fe03a082 757 * control parameters in the FMC_SDRAM_InitTypeDef
mbed_official 573:ad23fe03a082 758 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 759 * @param Init: Pointer to SDRAM Initialization structure
mbed_official 573:ad23fe03a082 760 * @retval HAL status
mbed_official 573:ad23fe03a082 761 */
mbed_official 573:ad23fe03a082 762 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
mbed_official 573:ad23fe03a082 763 {
mbed_official 573:ad23fe03a082 764 uint32_t tmpr1 = 0;
mbed_official 573:ad23fe03a082 765 uint32_t tmpr2 = 0;
mbed_official 573:ad23fe03a082 766
mbed_official 573:ad23fe03a082 767 /* Check the parameters */
mbed_official 573:ad23fe03a082 768 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 769 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
mbed_official 573:ad23fe03a082 770 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
mbed_official 573:ad23fe03a082 771 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
mbed_official 573:ad23fe03a082 772 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 573:ad23fe03a082 773 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
mbed_official 573:ad23fe03a082 774 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
mbed_official 573:ad23fe03a082 775 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
mbed_official 573:ad23fe03a082 776 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
mbed_official 573:ad23fe03a082 777 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
mbed_official 573:ad23fe03a082 778 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
mbed_official 573:ad23fe03a082 779
mbed_official 573:ad23fe03a082 780 /* Set SDRAM bank configuration parameters */
mbed_official 573:ad23fe03a082 781 if (Init->SDBank != FMC_SDRAM_BANK2)
mbed_official 573:ad23fe03a082 782 {
mbed_official 573:ad23fe03a082 783 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
mbed_official 573:ad23fe03a082 784
mbed_official 573:ad23fe03a082 785 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
mbed_official 573:ad23fe03a082 786 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
mbed_official 573:ad23fe03a082 787 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
mbed_official 573:ad23fe03a082 788 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
mbed_official 573:ad23fe03a082 789
mbed_official 573:ad23fe03a082 790 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 573:ad23fe03a082 791 Init->RowBitsNumber |\
mbed_official 573:ad23fe03a082 792 Init->MemoryDataWidth |\
mbed_official 573:ad23fe03a082 793 Init->InternalBankNumber |\
mbed_official 573:ad23fe03a082 794 Init->CASLatency |\
mbed_official 573:ad23fe03a082 795 Init->WriteProtection |\
mbed_official 573:ad23fe03a082 796 Init->SDClockPeriod |\
mbed_official 573:ad23fe03a082 797 Init->ReadBurst |\
mbed_official 573:ad23fe03a082 798 Init->ReadPipeDelay
mbed_official 573:ad23fe03a082 799 );
mbed_official 573:ad23fe03a082 800 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 573:ad23fe03a082 801 }
mbed_official 573:ad23fe03a082 802 else /* FMC_Bank2_SDRAM */
mbed_official 573:ad23fe03a082 803 {
mbed_official 573:ad23fe03a082 804 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
mbed_official 573:ad23fe03a082 805
mbed_official 573:ad23fe03a082 806 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
mbed_official 573:ad23fe03a082 807 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
mbed_official 573:ad23fe03a082 808 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
mbed_official 573:ad23fe03a082 809 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
mbed_official 573:ad23fe03a082 810
mbed_official 573:ad23fe03a082 811 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
mbed_official 573:ad23fe03a082 812 Init->ReadBurst |\
mbed_official 573:ad23fe03a082 813 Init->ReadPipeDelay);
mbed_official 573:ad23fe03a082 814
mbed_official 573:ad23fe03a082 815 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
mbed_official 573:ad23fe03a082 816
mbed_official 573:ad23fe03a082 817 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
mbed_official 573:ad23fe03a082 818 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
mbed_official 573:ad23fe03a082 819 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
mbed_official 573:ad23fe03a082 820 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
mbed_official 573:ad23fe03a082 821
mbed_official 573:ad23fe03a082 822 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 573:ad23fe03a082 823 Init->RowBitsNumber |\
mbed_official 573:ad23fe03a082 824 Init->MemoryDataWidth |\
mbed_official 573:ad23fe03a082 825 Init->InternalBankNumber |\
mbed_official 573:ad23fe03a082 826 Init->CASLatency |\
mbed_official 573:ad23fe03a082 827 Init->WriteProtection);
mbed_official 573:ad23fe03a082 828
mbed_official 573:ad23fe03a082 829 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 573:ad23fe03a082 830 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
mbed_official 573:ad23fe03a082 831 }
mbed_official 573:ad23fe03a082 832
mbed_official 573:ad23fe03a082 833 return HAL_OK;
mbed_official 573:ad23fe03a082 834 }
mbed_official 573:ad23fe03a082 835
mbed_official 573:ad23fe03a082 836 /**
mbed_official 573:ad23fe03a082 837 * @brief Initializes the FMC_SDRAM device timing according to the specified
mbed_official 573:ad23fe03a082 838 * parameters in the FMC_SDRAM_TimingTypeDef
mbed_official 573:ad23fe03a082 839 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 840 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 573:ad23fe03a082 841 * @param Bank: SDRAM bank number
mbed_official 573:ad23fe03a082 842 * @retval HAL status
mbed_official 573:ad23fe03a082 843 */
mbed_official 573:ad23fe03a082 844 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 573:ad23fe03a082 845 {
mbed_official 573:ad23fe03a082 846 uint32_t tmpr1 = 0;
mbed_official 573:ad23fe03a082 847 uint32_t tmpr2 = 0;
mbed_official 573:ad23fe03a082 848
mbed_official 573:ad23fe03a082 849 /* Check the parameters */
mbed_official 573:ad23fe03a082 850 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 851 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
mbed_official 573:ad23fe03a082 852 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
mbed_official 573:ad23fe03a082 853 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
mbed_official 573:ad23fe03a082 854 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
mbed_official 573:ad23fe03a082 855 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
mbed_official 573:ad23fe03a082 856 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
mbed_official 573:ad23fe03a082 857 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
mbed_official 573:ad23fe03a082 858 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 859
mbed_official 573:ad23fe03a082 860 /* Set SDRAM device timing parameters */
mbed_official 573:ad23fe03a082 861 if (Bank != FMC_SDRAM_BANK2)
mbed_official 573:ad23fe03a082 862 {
mbed_official 573:ad23fe03a082 863 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
mbed_official 573:ad23fe03a082 864
mbed_official 573:ad23fe03a082 865 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
mbed_official 573:ad23fe03a082 866 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
mbed_official 573:ad23fe03a082 867 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
mbed_official 573:ad23fe03a082 868 FMC_SDTR1_TRCD));
mbed_official 573:ad23fe03a082 869
mbed_official 573:ad23fe03a082 870 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 573:ad23fe03a082 871 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 573:ad23fe03a082 872 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 573:ad23fe03a082 873 (((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 573:ad23fe03a082 874 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 573:ad23fe03a082 875 (((Timing->RPDelay)-1) << 20) |\
mbed_official 573:ad23fe03a082 876 (((Timing->RCDDelay)-1) << 24));
mbed_official 573:ad23fe03a082 877 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 573:ad23fe03a082 878 }
mbed_official 573:ad23fe03a082 879 else /* FMC_Bank2_SDRAM */
mbed_official 573:ad23fe03a082 880 {
mbed_official 573:ad23fe03a082 881 tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
mbed_official 573:ad23fe03a082 882
mbed_official 573:ad23fe03a082 883 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
mbed_official 573:ad23fe03a082 884 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
mbed_official 573:ad23fe03a082 885 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
mbed_official 573:ad23fe03a082 886 FMC_SDTR1_TRCD));
mbed_official 573:ad23fe03a082 887
mbed_official 573:ad23fe03a082 888 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 573:ad23fe03a082 889 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 573:ad23fe03a082 890 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 573:ad23fe03a082 891 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 573:ad23fe03a082 892 (((Timing->RCDDelay)-1) << 24));
mbed_official 573:ad23fe03a082 893
mbed_official 573:ad23fe03a082 894 tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
mbed_official 573:ad23fe03a082 895
mbed_official 573:ad23fe03a082 896 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
mbed_official 573:ad23fe03a082 897 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
mbed_official 573:ad23fe03a082 898 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
mbed_official 573:ad23fe03a082 899 FMC_SDTR1_TRCD));
mbed_official 573:ad23fe03a082 900 tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 573:ad23fe03a082 901 (((Timing->RPDelay)-1) << 20));
mbed_official 573:ad23fe03a082 902
mbed_official 573:ad23fe03a082 903 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
mbed_official 573:ad23fe03a082 904 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
mbed_official 573:ad23fe03a082 905 }
mbed_official 573:ad23fe03a082 906
mbed_official 573:ad23fe03a082 907 return HAL_OK;
mbed_official 573:ad23fe03a082 908 }
mbed_official 573:ad23fe03a082 909
mbed_official 573:ad23fe03a082 910 /**
mbed_official 573:ad23fe03a082 911 * @brief DeInitializes the FMC_SDRAM peripheral
mbed_official 573:ad23fe03a082 912 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 913 * @retval HAL status
mbed_official 573:ad23fe03a082 914 */
mbed_official 573:ad23fe03a082 915 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 916 {
mbed_official 573:ad23fe03a082 917 /* Check the parameters */
mbed_official 573:ad23fe03a082 918 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 919 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 920
mbed_official 573:ad23fe03a082 921 /* De-initialize the SDRAM device */
mbed_official 573:ad23fe03a082 922 Device->SDCR[Bank] = 0x000002D0;
mbed_official 573:ad23fe03a082 923 Device->SDTR[Bank] = 0x0FFFFFFF;
mbed_official 573:ad23fe03a082 924 Device->SDCMR = 0x00000000;
mbed_official 573:ad23fe03a082 925 Device->SDRTR = 0x00000000;
mbed_official 573:ad23fe03a082 926 Device->SDSR = 0x00000000;
mbed_official 573:ad23fe03a082 927
mbed_official 573:ad23fe03a082 928 return HAL_OK;
mbed_official 573:ad23fe03a082 929 }
mbed_official 573:ad23fe03a082 930
mbed_official 573:ad23fe03a082 931 /**
mbed_official 573:ad23fe03a082 932 * @}
mbed_official 573:ad23fe03a082 933 */
mbed_official 573:ad23fe03a082 934
mbed_official 573:ad23fe03a082 935 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
mbed_official 573:ad23fe03a082 936 * @brief management functions
mbed_official 573:ad23fe03a082 937 *
mbed_official 573:ad23fe03a082 938 @verbatim
mbed_official 573:ad23fe03a082 939 ==============================================================================
mbed_official 573:ad23fe03a082 940 ##### FMC_SDRAM Control functions #####
mbed_official 573:ad23fe03a082 941 ==============================================================================
mbed_official 573:ad23fe03a082 942 [..]
mbed_official 573:ad23fe03a082 943 This subsection provides a set of functions allowing to control dynamically
mbed_official 573:ad23fe03a082 944 the FMC SDRAM interface.
mbed_official 573:ad23fe03a082 945
mbed_official 573:ad23fe03a082 946 @endverbatim
mbed_official 573:ad23fe03a082 947 * @{
mbed_official 573:ad23fe03a082 948 */
mbed_official 573:ad23fe03a082 949
mbed_official 573:ad23fe03a082 950 /**
mbed_official 573:ad23fe03a082 951 * @brief Enables dynamically FMC_SDRAM write protection.
mbed_official 573:ad23fe03a082 952 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 953 * @param Bank: SDRAM bank number
mbed_official 573:ad23fe03a082 954 * @retval HAL status
mbed_official 573:ad23fe03a082 955 */
mbed_official 573:ad23fe03a082 956 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 957 {
mbed_official 573:ad23fe03a082 958 /* Check the parameters */
mbed_official 573:ad23fe03a082 959 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 960 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 961
mbed_official 573:ad23fe03a082 962 /* Enable write protection */
mbed_official 573:ad23fe03a082 963 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 573:ad23fe03a082 964
mbed_official 573:ad23fe03a082 965 return HAL_OK;
mbed_official 573:ad23fe03a082 966 }
mbed_official 573:ad23fe03a082 967
mbed_official 573:ad23fe03a082 968 /**
mbed_official 573:ad23fe03a082 969 * @brief Disables dynamically FMC_SDRAM write protection.
mbed_official 573:ad23fe03a082 970 * @param hsdram: FMC_SDRAM handle
mbed_official 573:ad23fe03a082 971 * @retval HAL status
mbed_official 573:ad23fe03a082 972 */
mbed_official 573:ad23fe03a082 973 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 974 {
mbed_official 573:ad23fe03a082 975 /* Check the parameters */
mbed_official 573:ad23fe03a082 976 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 977 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 978
mbed_official 573:ad23fe03a082 979 /* Disable write protection */
mbed_official 573:ad23fe03a082 980 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 573:ad23fe03a082 981
mbed_official 573:ad23fe03a082 982 return HAL_OK;
mbed_official 573:ad23fe03a082 983 }
mbed_official 573:ad23fe03a082 984
mbed_official 573:ad23fe03a082 985 /**
mbed_official 573:ad23fe03a082 986 * @brief Send Command to the FMC SDRAM bank
mbed_official 573:ad23fe03a082 987 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 988 * @param Command: Pointer to SDRAM command structure
mbed_official 573:ad23fe03a082 989 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 573:ad23fe03a082 990 * @param Timeout: Timeout wait value
mbed_official 573:ad23fe03a082 991 * @retval HAL state
mbed_official 573:ad23fe03a082 992 */
mbed_official 573:ad23fe03a082 993 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 573:ad23fe03a082 994 {
mbed_official 573:ad23fe03a082 995 __IO uint32_t tmpr = 0;
mbed_official 573:ad23fe03a082 996 uint32_t tickstart = 0;
mbed_official 573:ad23fe03a082 997
mbed_official 573:ad23fe03a082 998 /* Check the parameters */
mbed_official 573:ad23fe03a082 999 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 1000 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
mbed_official 573:ad23fe03a082 1001 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
mbed_official 573:ad23fe03a082 1002 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
mbed_official 573:ad23fe03a082 1003 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
mbed_official 573:ad23fe03a082 1004
mbed_official 573:ad23fe03a082 1005 /* Set command register */
mbed_official 573:ad23fe03a082 1006 tmpr = (uint32_t)((Command->CommandMode) |\
mbed_official 573:ad23fe03a082 1007 (Command->CommandTarget) |\
mbed_official 573:ad23fe03a082 1008 (((Command->AutoRefreshNumber)-1) << 5) |\
mbed_official 573:ad23fe03a082 1009 ((Command->ModeRegisterDefinition) << 9)
mbed_official 573:ad23fe03a082 1010 );
mbed_official 573:ad23fe03a082 1011
mbed_official 573:ad23fe03a082 1012 Device->SDCMR = tmpr;
mbed_official 573:ad23fe03a082 1013
mbed_official 573:ad23fe03a082 1014 /* Get tick */
mbed_official 573:ad23fe03a082 1015 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 1016
mbed_official 573:ad23fe03a082 1017 /* wait until command is send */
mbed_official 573:ad23fe03a082 1018 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
mbed_official 573:ad23fe03a082 1019 {
mbed_official 573:ad23fe03a082 1020 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 1021 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 1022 {
mbed_official 573:ad23fe03a082 1023 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 573:ad23fe03a082 1024 {
mbed_official 573:ad23fe03a082 1025 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 1026 }
mbed_official 573:ad23fe03a082 1027 }
mbed_official 573:ad23fe03a082 1028
mbed_official 573:ad23fe03a082 1029 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1030 }
mbed_official 573:ad23fe03a082 1031
mbed_official 573:ad23fe03a082 1032 return HAL_OK;
mbed_official 573:ad23fe03a082 1033 }
mbed_official 573:ad23fe03a082 1034
mbed_official 573:ad23fe03a082 1035 /**
mbed_official 573:ad23fe03a082 1036 * @brief Program the SDRAM Memory Refresh rate.
mbed_official 573:ad23fe03a082 1037 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 1038 * @param RefreshRate: The SDRAM refresh rate value.
mbed_official 573:ad23fe03a082 1039 * @retval HAL state
mbed_official 573:ad23fe03a082 1040 */
mbed_official 573:ad23fe03a082 1041 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
mbed_official 573:ad23fe03a082 1042 {
mbed_official 573:ad23fe03a082 1043 /* Check the parameters */
mbed_official 573:ad23fe03a082 1044 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 1045 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
mbed_official 573:ad23fe03a082 1046
mbed_official 573:ad23fe03a082 1047 /* Set the refresh rate in command register */
mbed_official 573:ad23fe03a082 1048 Device->SDRTR |= (RefreshRate<<1);
mbed_official 573:ad23fe03a082 1049
mbed_official 573:ad23fe03a082 1050 return HAL_OK;
mbed_official 573:ad23fe03a082 1051 }
mbed_official 573:ad23fe03a082 1052
mbed_official 573:ad23fe03a082 1053 /**
mbed_official 573:ad23fe03a082 1054 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 573:ad23fe03a082 1055 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 1056 * @param AutoRefreshNumber: Specifies the auto Refresh number.
mbed_official 573:ad23fe03a082 1057 * @retval None
mbed_official 573:ad23fe03a082 1058 */
mbed_official 573:ad23fe03a082 1059 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
mbed_official 573:ad23fe03a082 1060 {
mbed_official 573:ad23fe03a082 1061 /* Check the parameters */
mbed_official 573:ad23fe03a082 1062 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 1063 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
mbed_official 573:ad23fe03a082 1064
mbed_official 573:ad23fe03a082 1065 /* Set the Auto-refresh number in command register */
mbed_official 573:ad23fe03a082 1066 Device->SDCMR |= (AutoRefreshNumber << 5);
mbed_official 573:ad23fe03a082 1067
mbed_official 573:ad23fe03a082 1068 return HAL_OK;
mbed_official 573:ad23fe03a082 1069 }
mbed_official 573:ad23fe03a082 1070
mbed_official 573:ad23fe03a082 1071 /**
mbed_official 573:ad23fe03a082 1072 * @brief Returns the indicated FMC SDRAM bank mode status.
mbed_official 573:ad23fe03a082 1073 * @param Device: Pointer to SDRAM device instance
mbed_official 573:ad23fe03a082 1074 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
mbed_official 573:ad23fe03a082 1075 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
mbed_official 573:ad23fe03a082 1076 * @retval The FMC SDRAM bank mode status, could be on of the following values:
mbed_official 573:ad23fe03a082 1077 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
mbed_official 573:ad23fe03a082 1078 * FMC_SDRAM_POWER_DOWN_MODE.
mbed_official 573:ad23fe03a082 1079 */
mbed_official 573:ad23fe03a082 1080 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 573:ad23fe03a082 1081 {
mbed_official 573:ad23fe03a082 1082 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1083
mbed_official 573:ad23fe03a082 1084 /* Check the parameters */
mbed_official 573:ad23fe03a082 1085 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 573:ad23fe03a082 1086 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 573:ad23fe03a082 1087
mbed_official 573:ad23fe03a082 1088 /* Get the corresponding bank mode */
mbed_official 573:ad23fe03a082 1089 if(Bank == FMC_SDRAM_BANK1)
mbed_official 573:ad23fe03a082 1090 {
mbed_official 573:ad23fe03a082 1091 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
mbed_official 573:ad23fe03a082 1092 }
mbed_official 573:ad23fe03a082 1093 else
mbed_official 573:ad23fe03a082 1094 {
mbed_official 573:ad23fe03a082 1095 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
mbed_official 573:ad23fe03a082 1096 }
mbed_official 573:ad23fe03a082 1097
mbed_official 573:ad23fe03a082 1098 /* Return the mode status */
mbed_official 573:ad23fe03a082 1099 return tmpreg;
mbed_official 573:ad23fe03a082 1100 }
mbed_official 573:ad23fe03a082 1101
mbed_official 573:ad23fe03a082 1102 /**
mbed_official 573:ad23fe03a082 1103 * @}
mbed_official 573:ad23fe03a082 1104 */
mbed_official 573:ad23fe03a082 1105
mbed_official 573:ad23fe03a082 1106 /**
mbed_official 573:ad23fe03a082 1107 * @}
mbed_official 573:ad23fe03a082 1108 */
mbed_official 573:ad23fe03a082 1109
mbed_official 573:ad23fe03a082 1110 /**
mbed_official 573:ad23fe03a082 1111 * @}
mbed_official 573:ad23fe03a082 1112 */
mbed_official 573:ad23fe03a082 1113 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
mbed_official 573:ad23fe03a082 1114
mbed_official 573:ad23fe03a082 1115 /**
mbed_official 573:ad23fe03a082 1116 * @}
mbed_official 573:ad23fe03a082 1117 */
mbed_official 573:ad23fe03a082 1118
mbed_official 573:ad23fe03a082 1119 /**
mbed_official 573:ad23fe03a082 1120 * @}
mbed_official 573:ad23fe03a082 1121 */
mbed_official 573:ad23fe03a082 1122
mbed_official 573:ad23fe03a082 1123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/