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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Parent:
573:ad23fe03a082 
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_hal_rcc_ex.h
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.1
mbed_official 610:813dcc80987e 6 * @date 25-June-2015
mbed_official 573:ad23fe03a082 7 * @brief Header file of RCC HAL Extension module.
mbed_official 573:ad23fe03a082 8 ******************************************************************************
mbed_official 573:ad23fe03a082 9 * @attention
mbed_official 573:ad23fe03a082 10 *
mbed_official 573:ad23fe03a082 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 12 *
mbed_official 573:ad23fe03a082 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 14 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 16 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 19 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 21 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 22 * without specific prior written permission.
mbed_official 573:ad23fe03a082 23 *
mbed_official 573:ad23fe03a082 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 34 *
mbed_official 573:ad23fe03a082 35 ******************************************************************************
mbed_official 573:ad23fe03a082 36 */
mbed_official 573:ad23fe03a082 37
mbed_official 573:ad23fe03a082 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 573:ad23fe03a082 39 #ifndef __STM32F7xx_HAL_RCC_EX_H
mbed_official 573:ad23fe03a082 40 #define __STM32F7xx_HAL_RCC_EX_H
mbed_official 573:ad23fe03a082 41
mbed_official 573:ad23fe03a082 42 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 43 extern "C" {
mbed_official 573:ad23fe03a082 44 #endif
mbed_official 573:ad23fe03a082 45
mbed_official 573:ad23fe03a082 46 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 47 #include "stm32f7xx_hal_def.h"
mbed_official 573:ad23fe03a082 48
mbed_official 573:ad23fe03a082 49 /** @addtogroup STM32F7xx_HAL_Driver
mbed_official 573:ad23fe03a082 50 * @{
mbed_official 573:ad23fe03a082 51 */
mbed_official 573:ad23fe03a082 52
mbed_official 573:ad23fe03a082 53 /** @addtogroup RCCEx
mbed_official 573:ad23fe03a082 54 * @{
mbed_official 573:ad23fe03a082 55 */
mbed_official 573:ad23fe03a082 56
mbed_official 573:ad23fe03a082 57 /* Exported types ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official 573:ad23fe03a082 59 * @{
mbed_official 573:ad23fe03a082 60 */
mbed_official 573:ad23fe03a082 61
mbed_official 573:ad23fe03a082 62 /**
mbed_official 573:ad23fe03a082 63 * @brief PLLI2S Clock structure definition
mbed_official 573:ad23fe03a082 64 */
mbed_official 573:ad23fe03a082 65 typedef struct
mbed_official 573:ad23fe03a082 66 {
mbed_official 573:ad23fe03a082 67 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 573:ad23fe03a082 68 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
mbed_official 573:ad23fe03a082 69 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 573:ad23fe03a082 70
mbed_official 573:ad23fe03a082 71 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official 573:ad23fe03a082 72 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 573:ad23fe03a082 73 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 573:ad23fe03a082 74
mbed_official 573:ad23fe03a082 75 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 573:ad23fe03a082 76 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 573:ad23fe03a082 77 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 573:ad23fe03a082 78
mbed_official 573:ad23fe03a082 79 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
mbed_official 573:ad23fe03a082 80 This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8.
mbed_official 573:ad23fe03a082 81 This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */
mbed_official 573:ad23fe03a082 82 }RCC_PLLI2SInitTypeDef;
mbed_official 573:ad23fe03a082 83
mbed_official 573:ad23fe03a082 84 /**
mbed_official 573:ad23fe03a082 85 * @brief PLLSAI Clock structure definition
mbed_official 573:ad23fe03a082 86 */
mbed_official 573:ad23fe03a082 87 typedef struct
mbed_official 573:ad23fe03a082 88 {
mbed_official 573:ad23fe03a082 89 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 573:ad23fe03a082 90 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
mbed_official 573:ad23fe03a082 91 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 573:ad23fe03a082 92
mbed_official 573:ad23fe03a082 93 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 573:ad23fe03a082 94 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 573:ad23fe03a082 95 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 573:ad23fe03a082 96
mbed_official 573:ad23fe03a082 97 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
mbed_official 573:ad23fe03a082 98 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 573:ad23fe03a082 99 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
mbed_official 573:ad23fe03a082 100
mbed_official 573:ad23fe03a082 101 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
mbed_official 573:ad23fe03a082 102 This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider
mbed_official 573:ad23fe03a082 103 This parameter will be used only when PLLSAI is disabled */
mbed_official 573:ad23fe03a082 104 }RCC_PLLSAIInitTypeDef;
mbed_official 573:ad23fe03a082 105
mbed_official 573:ad23fe03a082 106 /**
mbed_official 573:ad23fe03a082 107 * @brief RCC extended clocks structure definition
mbed_official 573:ad23fe03a082 108 */
mbed_official 573:ad23fe03a082 109 typedef struct
mbed_official 573:ad23fe03a082 110 {
mbed_official 573:ad23fe03a082 111 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official 573:ad23fe03a082 112 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official 573:ad23fe03a082 113
mbed_official 573:ad23fe03a082 114 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official 573:ad23fe03a082 115 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 573:ad23fe03a082 116
mbed_official 573:ad23fe03a082 117 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official 573:ad23fe03a082 118 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official 573:ad23fe03a082 119
mbed_official 573:ad23fe03a082 120 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 573:ad23fe03a082 121 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 573:ad23fe03a082 122 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 573:ad23fe03a082 123
mbed_official 573:ad23fe03a082 124 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 573:ad23fe03a082 125 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 573:ad23fe03a082 126 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official 573:ad23fe03a082 127
mbed_official 573:ad23fe03a082 128 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
mbed_official 573:ad23fe03a082 129 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
mbed_official 573:ad23fe03a082 130
mbed_official 573:ad23fe03a082 131 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
mbed_official 573:ad23fe03a082 132 This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official 573:ad23fe03a082 133
mbed_official 573:ad23fe03a082 134 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
mbed_official 573:ad23fe03a082 135 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official 573:ad23fe03a082 136
mbed_official 573:ad23fe03a082 137 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
mbed_official 573:ad23fe03a082 138 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
mbed_official 573:ad23fe03a082 139
mbed_official 573:ad23fe03a082 140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
mbed_official 573:ad23fe03a082 141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
mbed_official 573:ad23fe03a082 142
mbed_official 573:ad23fe03a082 143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
mbed_official 573:ad23fe03a082 144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
mbed_official 573:ad23fe03a082 145
mbed_official 573:ad23fe03a082 146 uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official 573:ad23fe03a082 147 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official 573:ad23fe03a082 148
mbed_official 573:ad23fe03a082 149 uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official 573:ad23fe03a082 150 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official 573:ad23fe03a082 151
mbed_official 573:ad23fe03a082 152 uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official 573:ad23fe03a082 153 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
mbed_official 573:ad23fe03a082 154
mbed_official 573:ad23fe03a082 155 uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official 573:ad23fe03a082 156 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official 573:ad23fe03a082 157
mbed_official 573:ad23fe03a082 158 uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official 573:ad23fe03a082 159 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official 573:ad23fe03a082 160
mbed_official 573:ad23fe03a082 161 uint32_t Usart6ClockSelection; /*!< USART6 clock source
mbed_official 573:ad23fe03a082 162 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
mbed_official 573:ad23fe03a082 163
mbed_official 573:ad23fe03a082 164 uint32_t Uart7ClockSelection; /*!< UART7 clock source
mbed_official 573:ad23fe03a082 165 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
mbed_official 573:ad23fe03a082 166
mbed_official 573:ad23fe03a082 167 uint32_t Uart8ClockSelection; /*!< UART8 clock source
mbed_official 573:ad23fe03a082 168 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
mbed_official 573:ad23fe03a082 169
mbed_official 573:ad23fe03a082 170 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official 573:ad23fe03a082 171 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
mbed_official 573:ad23fe03a082 172
mbed_official 573:ad23fe03a082 173 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official 573:ad23fe03a082 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official 573:ad23fe03a082 175
mbed_official 573:ad23fe03a082 176 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official 573:ad23fe03a082 177 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official 573:ad23fe03a082 178
mbed_official 573:ad23fe03a082 179 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
mbed_official 573:ad23fe03a082 180 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
mbed_official 573:ad23fe03a082 181
mbed_official 573:ad23fe03a082 182 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
mbed_official 573:ad23fe03a082 183 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
mbed_official 573:ad23fe03a082 184
mbed_official 573:ad23fe03a082 185 uint32_t CecClockSelection; /*!< CEC clock source
mbed_official 573:ad23fe03a082 186 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official 573:ad23fe03a082 187
mbed_official 573:ad23fe03a082 188 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
mbed_official 573:ad23fe03a082 189 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
mbed_official 573:ad23fe03a082 190
mbed_official 573:ad23fe03a082 191 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
mbed_official 573:ad23fe03a082 192 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
mbed_official 573:ad23fe03a082 193
mbed_official 573:ad23fe03a082 194 }RCC_PeriphCLKInitTypeDef;
mbed_official 573:ad23fe03a082 195 /**
mbed_official 573:ad23fe03a082 196 * @}
mbed_official 573:ad23fe03a082 197 */
mbed_official 573:ad23fe03a082 198
mbed_official 573:ad23fe03a082 199 /* Exported constants --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 200 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official 573:ad23fe03a082 201 * @{
mbed_official 573:ad23fe03a082 202 */
mbed_official 573:ad23fe03a082 203
mbed_official 573:ad23fe03a082 204 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
mbed_official 573:ad23fe03a082 205 * @{
mbed_official 573:ad23fe03a082 206 */
mbed_official 573:ad23fe03a082 207 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 208 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 209 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 210 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 211 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 212 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 213 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 214 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 215 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 216 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 217 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 218 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 219 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 220 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 221 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 222 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 223 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 224 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 225 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 226 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 227 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 228 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 229 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 230 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 231 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 232 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 233
mbed_official 573:ad23fe03a082 234
mbed_official 573:ad23fe03a082 235 /**
mbed_official 573:ad23fe03a082 236 * @}
mbed_official 573:ad23fe03a082 237 */
mbed_official 573:ad23fe03a082 238
mbed_official 573:ad23fe03a082 239 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
mbed_official 573:ad23fe03a082 240 * @{
mbed_official 573:ad23fe03a082 241 */
mbed_official 573:ad23fe03a082 242 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 243 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 244 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 245 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 246 /**
mbed_official 573:ad23fe03a082 247 * @}
mbed_official 573:ad23fe03a082 248 */
mbed_official 573:ad23fe03a082 249
mbed_official 573:ad23fe03a082 250 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
mbed_official 573:ad23fe03a082 251 * @{
mbed_official 573:ad23fe03a082 252 */
mbed_official 573:ad23fe03a082 253 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 254 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
mbed_official 573:ad23fe03a082 255 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
mbed_official 573:ad23fe03a082 256 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
mbed_official 573:ad23fe03a082 257 /**
mbed_official 573:ad23fe03a082 258 * @}
mbed_official 573:ad23fe03a082 259 */
mbed_official 573:ad23fe03a082 260
mbed_official 573:ad23fe03a082 261 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
mbed_official 573:ad23fe03a082 262 * @{
mbed_official 573:ad23fe03a082 263 */
mbed_official 573:ad23fe03a082 264 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 265 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
mbed_official 573:ad23fe03a082 266
mbed_official 573:ad23fe03a082 267 /**
mbed_official 573:ad23fe03a082 268 * @}
mbed_official 573:ad23fe03a082 269 */
mbed_official 573:ad23fe03a082 270
mbed_official 573:ad23fe03a082 271
mbed_official 573:ad23fe03a082 272 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
mbed_official 573:ad23fe03a082 273 * @{
mbed_official 573:ad23fe03a082 274 */
mbed_official 573:ad23fe03a082 275 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 276 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
mbed_official 573:ad23fe03a082 277 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
mbed_official 573:ad23fe03a082 278
mbed_official 573:ad23fe03a082 279 /**
mbed_official 573:ad23fe03a082 280 * @}
mbed_official 573:ad23fe03a082 281 */
mbed_official 573:ad23fe03a082 282
mbed_official 573:ad23fe03a082 283 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
mbed_official 573:ad23fe03a082 284 * @{
mbed_official 573:ad23fe03a082 285 */
mbed_official 573:ad23fe03a082 286 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 287 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
mbed_official 573:ad23fe03a082 288 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
mbed_official 573:ad23fe03a082 289 /**
mbed_official 573:ad23fe03a082 290 * @}
mbed_official 573:ad23fe03a082 291 */
mbed_official 573:ad23fe03a082 292
mbed_official 573:ad23fe03a082 293 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
mbed_official 573:ad23fe03a082 294 * @{
mbed_official 573:ad23fe03a082 295 */
mbed_official 573:ad23fe03a082 296 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 297 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
mbed_official 573:ad23fe03a082 298 /**
mbed_official 573:ad23fe03a082 299 * @}
mbed_official 573:ad23fe03a082 300 */
mbed_official 573:ad23fe03a082 301
mbed_official 573:ad23fe03a082 302 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
mbed_official 573:ad23fe03a082 303 * @{
mbed_official 573:ad23fe03a082 304 */
mbed_official 573:ad23fe03a082 305 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 306 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
mbed_official 573:ad23fe03a082 307 /**
mbed_official 573:ad23fe03a082 308 * @}
mbed_official 573:ad23fe03a082 309 */
mbed_official 573:ad23fe03a082 310
mbed_official 573:ad23fe03a082 311 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
mbed_official 573:ad23fe03a082 312 * @{
mbed_official 573:ad23fe03a082 313 */
mbed_official 573:ad23fe03a082 314 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 315 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
mbed_official 573:ad23fe03a082 316 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
mbed_official 573:ad23fe03a082 317 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
mbed_official 573:ad23fe03a082 318 /**
mbed_official 573:ad23fe03a082 319 * @}
mbed_official 573:ad23fe03a082 320 */
mbed_official 573:ad23fe03a082 321
mbed_official 573:ad23fe03a082 322 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
mbed_official 573:ad23fe03a082 323 * @{
mbed_official 573:ad23fe03a082 324 */
mbed_official 573:ad23fe03a082 325 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 326 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
mbed_official 573:ad23fe03a082 327 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
mbed_official 573:ad23fe03a082 328 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
mbed_official 573:ad23fe03a082 329 /**
mbed_official 573:ad23fe03a082 330 * @}
mbed_official 573:ad23fe03a082 331 */
mbed_official 573:ad23fe03a082 332
mbed_official 573:ad23fe03a082 333 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
mbed_official 573:ad23fe03a082 334 * @{
mbed_official 573:ad23fe03a082 335 */
mbed_official 573:ad23fe03a082 336 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 337 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
mbed_official 573:ad23fe03a082 338 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
mbed_official 573:ad23fe03a082 339 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
mbed_official 573:ad23fe03a082 340 /**
mbed_official 573:ad23fe03a082 341 * @}
mbed_official 573:ad23fe03a082 342 */
mbed_official 573:ad23fe03a082 343
mbed_official 573:ad23fe03a082 344 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
mbed_official 573:ad23fe03a082 345 * @{
mbed_official 573:ad23fe03a082 346 */
mbed_official 573:ad23fe03a082 347 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 348 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
mbed_official 573:ad23fe03a082 349 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
mbed_official 573:ad23fe03a082 350 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
mbed_official 573:ad23fe03a082 351 /**
mbed_official 573:ad23fe03a082 352 * @}
mbed_official 573:ad23fe03a082 353 */
mbed_official 573:ad23fe03a082 354
mbed_official 573:ad23fe03a082 355 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
mbed_official 573:ad23fe03a082 356 * @{
mbed_official 573:ad23fe03a082 357 */
mbed_official 573:ad23fe03a082 358 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 359 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
mbed_official 573:ad23fe03a082 360 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
mbed_official 573:ad23fe03a082 361 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
mbed_official 573:ad23fe03a082 362 /**
mbed_official 573:ad23fe03a082 363 * @}
mbed_official 573:ad23fe03a082 364 */
mbed_official 573:ad23fe03a082 365
mbed_official 573:ad23fe03a082 366 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
mbed_official 573:ad23fe03a082 367 * @{
mbed_official 573:ad23fe03a082 368 */
mbed_official 573:ad23fe03a082 369 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 370 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
mbed_official 573:ad23fe03a082 371 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
mbed_official 573:ad23fe03a082 372 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
mbed_official 573:ad23fe03a082 373 /**
mbed_official 573:ad23fe03a082 374 * @}
mbed_official 573:ad23fe03a082 375 */
mbed_official 573:ad23fe03a082 376
mbed_official 573:ad23fe03a082 377 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
mbed_official 573:ad23fe03a082 378 * @{
mbed_official 573:ad23fe03a082 379 */
mbed_official 573:ad23fe03a082 380 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 381 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
mbed_official 573:ad23fe03a082 382 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
mbed_official 573:ad23fe03a082 383 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
mbed_official 573:ad23fe03a082 384 /**
mbed_official 573:ad23fe03a082 385 * @}
mbed_official 573:ad23fe03a082 386 */
mbed_official 573:ad23fe03a082 387
mbed_official 573:ad23fe03a082 388 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
mbed_official 573:ad23fe03a082 389 * @{
mbed_official 573:ad23fe03a082 390 */
mbed_official 573:ad23fe03a082 391 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 392 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
mbed_official 573:ad23fe03a082 393 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
mbed_official 573:ad23fe03a082 394 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
mbed_official 573:ad23fe03a082 395 /**
mbed_official 573:ad23fe03a082 396 * @}
mbed_official 573:ad23fe03a082 397 */
mbed_official 573:ad23fe03a082 398
mbed_official 573:ad23fe03a082 399 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
mbed_official 573:ad23fe03a082 400 * @{
mbed_official 573:ad23fe03a082 401 */
mbed_official 573:ad23fe03a082 402 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 403 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
mbed_official 573:ad23fe03a082 404 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
mbed_official 573:ad23fe03a082 405 /**
mbed_official 573:ad23fe03a082 406 * @}
mbed_official 573:ad23fe03a082 407 */
mbed_official 573:ad23fe03a082 408
mbed_official 573:ad23fe03a082 409 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
mbed_official 573:ad23fe03a082 410 * @{
mbed_official 573:ad23fe03a082 411 */
mbed_official 573:ad23fe03a082 412 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 413 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
mbed_official 573:ad23fe03a082 414 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
mbed_official 573:ad23fe03a082 415
mbed_official 573:ad23fe03a082 416 /**
mbed_official 573:ad23fe03a082 417 * @}
mbed_official 573:ad23fe03a082 418 */
mbed_official 573:ad23fe03a082 419
mbed_official 573:ad23fe03a082 420 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
mbed_official 573:ad23fe03a082 421 * @{
mbed_official 573:ad23fe03a082 422 */
mbed_official 573:ad23fe03a082 423 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 424 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
mbed_official 573:ad23fe03a082 425 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
mbed_official 573:ad23fe03a082 426 /**
mbed_official 573:ad23fe03a082 427 * @}
mbed_official 573:ad23fe03a082 428 */
mbed_official 573:ad23fe03a082 429
mbed_official 573:ad23fe03a082 430 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
mbed_official 573:ad23fe03a082 431 * @{
mbed_official 573:ad23fe03a082 432 */
mbed_official 573:ad23fe03a082 433 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 434 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
mbed_official 573:ad23fe03a082 435 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
mbed_official 573:ad23fe03a082 436 /**
mbed_official 573:ad23fe03a082 437 * @}
mbed_official 573:ad23fe03a082 438 */
mbed_official 573:ad23fe03a082 439
mbed_official 573:ad23fe03a082 440
mbed_official 573:ad23fe03a082 441 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
mbed_official 573:ad23fe03a082 442 * @{
mbed_official 573:ad23fe03a082 443 */
mbed_official 573:ad23fe03a082 444 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 445 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
mbed_official 573:ad23fe03a082 446 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
mbed_official 573:ad23fe03a082 447 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
mbed_official 573:ad23fe03a082 448
mbed_official 573:ad23fe03a082 449 /**
mbed_official 573:ad23fe03a082 450 * @}
mbed_official 573:ad23fe03a082 451 */
mbed_official 573:ad23fe03a082 452
mbed_official 573:ad23fe03a082 453 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
mbed_official 573:ad23fe03a082 454 * @{
mbed_official 573:ad23fe03a082 455 */
mbed_official 573:ad23fe03a082 456 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 457 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
mbed_official 573:ad23fe03a082 458 /**
mbed_official 573:ad23fe03a082 459 * @}
mbed_official 573:ad23fe03a082 460 */
mbed_official 573:ad23fe03a082 461
mbed_official 573:ad23fe03a082 462 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
mbed_official 573:ad23fe03a082 463 * @{
mbed_official 573:ad23fe03a082 464 */
mbed_official 573:ad23fe03a082 465 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 466 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
mbed_official 573:ad23fe03a082 467
mbed_official 573:ad23fe03a082 468
mbed_official 573:ad23fe03a082 469 /**
mbed_official 573:ad23fe03a082 470 * @}
mbed_official 573:ad23fe03a082 471 */
mbed_official 573:ad23fe03a082 472
mbed_official 573:ad23fe03a082 473 /**
mbed_official 573:ad23fe03a082 474 * @}
mbed_official 573:ad23fe03a082 475 */
mbed_official 573:ad23fe03a082 476
mbed_official 573:ad23fe03a082 477 /* Exported macro ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 478 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official 573:ad23fe03a082 479 * @{
mbed_official 573:ad23fe03a082 480 */
mbed_official 573:ad23fe03a082 481 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
mbed_official 573:ad23fe03a082 482 * @brief Enables or disables the AHB/APB peripheral clock.
mbed_official 573:ad23fe03a082 483 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 484 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 485 * using it.
mbed_official 573:ad23fe03a082 486 * @{
mbed_official 573:ad23fe03a082 487 */
mbed_official 573:ad23fe03a082 488
mbed_official 573:ad23fe03a082 489 /** @brief Enables or disables the AHB1 peripheral clock.
mbed_official 573:ad23fe03a082 490 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 491 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 492 * using it.
mbed_official 573:ad23fe03a082 493 */
mbed_official 573:ad23fe03a082 494 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 495 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 496 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
mbed_official 573:ad23fe03a082 497 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 498 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
mbed_official 573:ad23fe03a082 499 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 500 } while(0)
mbed_official 573:ad23fe03a082 501
mbed_official 573:ad23fe03a082 502 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 503 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 504 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
mbed_official 573:ad23fe03a082 505 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 506 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
mbed_official 573:ad23fe03a082 507 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 508 } while(0)
mbed_official 573:ad23fe03a082 509
mbed_official 573:ad23fe03a082 510 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 511 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 512 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
mbed_official 573:ad23fe03a082 513 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 514 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
mbed_official 573:ad23fe03a082 515 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 516 } while(0)
mbed_official 573:ad23fe03a082 517
mbed_official 573:ad23fe03a082 518 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 519 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 520 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
mbed_official 573:ad23fe03a082 521 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 522 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
mbed_official 573:ad23fe03a082 523 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 524 } while(0)
mbed_official 573:ad23fe03a082 525
mbed_official 573:ad23fe03a082 526 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 527 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 528 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official 573:ad23fe03a082 529 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 530 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
mbed_official 573:ad23fe03a082 531 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 532 } while(0)
mbed_official 573:ad23fe03a082 533
mbed_official 573:ad23fe03a082 534 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 535 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 536 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official 573:ad23fe03a082 537 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 538 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
mbed_official 573:ad23fe03a082 539 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 540 } while(0)
mbed_official 573:ad23fe03a082 541
mbed_official 573:ad23fe03a082 542 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 543 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 544 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
mbed_official 573:ad23fe03a082 545 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 546 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
mbed_official 573:ad23fe03a082 547 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 548 } while(0)
mbed_official 573:ad23fe03a082 549
mbed_official 573:ad23fe03a082 550 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 551 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 552 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
mbed_official 573:ad23fe03a082 553 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 554 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
mbed_official 573:ad23fe03a082 555 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 556 } while(0)
mbed_official 573:ad23fe03a082 557
mbed_official 573:ad23fe03a082 558 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 559 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 560 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
mbed_official 573:ad23fe03a082 561 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 562 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
mbed_official 573:ad23fe03a082 563 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 564 } while(0)
mbed_official 573:ad23fe03a082 565
mbed_official 573:ad23fe03a082 566 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 567 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 568 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
mbed_official 573:ad23fe03a082 569 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 570 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
mbed_official 573:ad23fe03a082 571 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 572 } while(0)
mbed_official 573:ad23fe03a082 573
mbed_official 573:ad23fe03a082 574 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 575 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 576 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
mbed_official 573:ad23fe03a082 577 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 578 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
mbed_official 573:ad23fe03a082 579 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 580 } while(0)
mbed_official 573:ad23fe03a082 581
mbed_official 573:ad23fe03a082 582 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 583 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 584 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official 573:ad23fe03a082 585 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 586 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
mbed_official 573:ad23fe03a082 587 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 588 } while(0)
mbed_official 573:ad23fe03a082 589
mbed_official 573:ad23fe03a082 590 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 591 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 592 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official 573:ad23fe03a082 593 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 594 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
mbed_official 573:ad23fe03a082 595 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 596 } while(0)
mbed_official 573:ad23fe03a082 597
mbed_official 573:ad23fe03a082 598 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 599 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 600 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
mbed_official 573:ad23fe03a082 601 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 602 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
mbed_official 573:ad23fe03a082 603 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 604 } while(0)
mbed_official 573:ad23fe03a082 605
mbed_official 573:ad23fe03a082 606 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 607 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 608 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official 573:ad23fe03a082 609 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 610 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
mbed_official 573:ad23fe03a082 611 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 612 } while(0)
mbed_official 573:ad23fe03a082 613
mbed_official 573:ad23fe03a082 614 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 615 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 616 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
mbed_official 573:ad23fe03a082 617 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 618 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
mbed_official 573:ad23fe03a082 619 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 620 } while(0)
mbed_official 573:ad23fe03a082 621
mbed_official 573:ad23fe03a082 622 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 623 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 624 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
mbed_official 573:ad23fe03a082 625 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 626 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
mbed_official 573:ad23fe03a082 627 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 628 } while(0)
mbed_official 573:ad23fe03a082 629
mbed_official 573:ad23fe03a082 630 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
mbed_official 573:ad23fe03a082 631 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
mbed_official 573:ad23fe03a082 632 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
mbed_official 573:ad23fe03a082 633 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
mbed_official 573:ad23fe03a082 634 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official 573:ad23fe03a082 635 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 573:ad23fe03a082 636 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
mbed_official 573:ad23fe03a082 637 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
mbed_official 573:ad23fe03a082 638 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
mbed_official 573:ad23fe03a082 639 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
mbed_official 573:ad23fe03a082 640 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
mbed_official 573:ad23fe03a082 641 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official 573:ad23fe03a082 642 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official 573:ad23fe03a082 643 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
mbed_official 573:ad23fe03a082 644 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official 573:ad23fe03a082 645 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
mbed_official 573:ad23fe03a082 646 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
mbed_official 573:ad23fe03a082 647 /**
mbed_official 573:ad23fe03a082 648 * @brief Enable ETHERNET clock.
mbed_official 573:ad23fe03a082 649 */
mbed_official 573:ad23fe03a082 650 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 651 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 652 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official 573:ad23fe03a082 653 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 654 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
mbed_official 573:ad23fe03a082 655 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 656 } while(0)
mbed_official 573:ad23fe03a082 657
mbed_official 573:ad23fe03a082 658 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 659 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 660 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official 573:ad23fe03a082 661 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 662 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
mbed_official 573:ad23fe03a082 663 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 664 } while(0)
mbed_official 573:ad23fe03a082 665
mbed_official 573:ad23fe03a082 666 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 667 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 668 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official 573:ad23fe03a082 669 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 670 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
mbed_official 573:ad23fe03a082 671 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 672 } while(0)
mbed_official 573:ad23fe03a082 673
mbed_official 573:ad23fe03a082 674 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 675 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official 573:ad23fe03a082 677 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 678 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
mbed_official 573:ad23fe03a082 679 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 680 } while(0)
mbed_official 573:ad23fe03a082 681
mbed_official 573:ad23fe03a082 682 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 683 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
mbed_official 573:ad23fe03a082 684 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
mbed_official 573:ad23fe03a082 685 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
mbed_official 573:ad23fe03a082 686 } while(0)
mbed_official 573:ad23fe03a082 687 /**
mbed_official 573:ad23fe03a082 688 * @brief Disable ETHERNET clock.
mbed_official 573:ad23fe03a082 689 */
mbed_official 573:ad23fe03a082 690 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official 573:ad23fe03a082 691 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official 573:ad23fe03a082 692 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official 573:ad23fe03a082 693 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 573:ad23fe03a082 694 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
mbed_official 573:ad23fe03a082 695 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
mbed_official 573:ad23fe03a082 696 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
mbed_official 573:ad23fe03a082 697 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
mbed_official 573:ad23fe03a082 698 } while(0)
mbed_official 573:ad23fe03a082 699
mbed_official 573:ad23fe03a082 700 /** @brief Enable or disable the AHB2 peripheral clock.
mbed_official 573:ad23fe03a082 701 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 702 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 703 * using it.
mbed_official 573:ad23fe03a082 704 */
mbed_official 573:ad23fe03a082 705 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 706 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 707 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official 573:ad23fe03a082 708 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 709 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
mbed_official 573:ad23fe03a082 710 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 711 } while(0)
mbed_official 573:ad23fe03a082 712
mbed_official 573:ad23fe03a082 713 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 714 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 715 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
mbed_official 573:ad23fe03a082 716 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 717 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
mbed_official 573:ad23fe03a082 718 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 719 } while(0)
mbed_official 573:ad23fe03a082 720
mbed_official 573:ad23fe03a082 721 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 722 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
mbed_official 573:ad23fe03a082 724 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
mbed_official 573:ad23fe03a082 726 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 727 __HAL_RCC_SYSCFG_CLK_ENABLE();\
mbed_official 573:ad23fe03a082 728 } while(0)
mbed_official 573:ad23fe03a082 729
mbed_official 573:ad23fe03a082 730 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official 573:ad23fe03a082 731 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
mbed_official 573:ad23fe03a082 732
mbed_official 573:ad23fe03a082 733 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
mbed_official 573:ad23fe03a082 734 __HAL_RCC_SYSCFG_CLK_DISABLE();\
mbed_official 573:ad23fe03a082 735 }while(0)
mbed_official 573:ad23fe03a082 736 #if defined(STM32F756xx)
mbed_official 573:ad23fe03a082 737 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 738 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 739 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official 573:ad23fe03a082 740 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 741 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
mbed_official 573:ad23fe03a082 742 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 743 } while(0)
mbed_official 573:ad23fe03a082 744
mbed_official 573:ad23fe03a082 745 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 746 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 747 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official 573:ad23fe03a082 748 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 749 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
mbed_official 573:ad23fe03a082 750 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 751 } while(0)
mbed_official 573:ad23fe03a082 752
mbed_official 573:ad23fe03a082 753 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official 573:ad23fe03a082 754 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official 573:ad23fe03a082 755 #endif /* STM32F756x */
mbed_official 573:ad23fe03a082 756 /** @brief Enables or disables the AHB3 peripheral clock.
mbed_official 573:ad23fe03a082 757 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 758 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 759 * using it.
mbed_official 573:ad23fe03a082 760 */
mbed_official 573:ad23fe03a082 761 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 762 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 763 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official 573:ad23fe03a082 764 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 765 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
mbed_official 573:ad23fe03a082 766 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 767 } while(0)
mbed_official 573:ad23fe03a082 768
mbed_official 573:ad23fe03a082 769 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 770 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 771 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
mbed_official 573:ad23fe03a082 772 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 773 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
mbed_official 573:ad23fe03a082 774 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 775 } while(0)
mbed_official 573:ad23fe03a082 776
mbed_official 573:ad23fe03a082 777 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official 573:ad23fe03a082 778 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
mbed_official 573:ad23fe03a082 779
mbed_official 573:ad23fe03a082 780 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official 573:ad23fe03a082 781 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 782 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 783 * using it.
mbed_official 573:ad23fe03a082 784 */
mbed_official 573:ad23fe03a082 785 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 786 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 787 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official 573:ad23fe03a082 788 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 789 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official 573:ad23fe03a082 790 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 791 } while(0)
mbed_official 573:ad23fe03a082 792
mbed_official 573:ad23fe03a082 793 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 794 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official 573:ad23fe03a082 796 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official 573:ad23fe03a082 798 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 799 } while(0)
mbed_official 573:ad23fe03a082 800
mbed_official 573:ad23fe03a082 801 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 802 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 803 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official 573:ad23fe03a082 804 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 805 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official 573:ad23fe03a082 806 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 807 } while(0)
mbed_official 573:ad23fe03a082 808
mbed_official 573:ad23fe03a082 809 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 810 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 811 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official 573:ad23fe03a082 812 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 813 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official 573:ad23fe03a082 814 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 815 } while(0)
mbed_official 573:ad23fe03a082 816
mbed_official 573:ad23fe03a082 817 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 818 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 819 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official 573:ad23fe03a082 820 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 821 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official 573:ad23fe03a082 822 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 823 } while(0)
mbed_official 573:ad23fe03a082 824
mbed_official 573:ad23fe03a082 825 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 826 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 827 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official 573:ad23fe03a082 828 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 829 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official 573:ad23fe03a082 830 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 831 } while(0)
mbed_official 573:ad23fe03a082 832
mbed_official 573:ad23fe03a082 833 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 834 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 835 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official 573:ad23fe03a082 836 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 837 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official 573:ad23fe03a082 838 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 839 } while(0)
mbed_official 573:ad23fe03a082 840
mbed_official 573:ad23fe03a082 841 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 842 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 843 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official 573:ad23fe03a082 844 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 845 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official 573:ad23fe03a082 846 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 847 } while(0)
mbed_official 573:ad23fe03a082 848
mbed_official 573:ad23fe03a082 849 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 850 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 851 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official 573:ad23fe03a082 852 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 853 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official 573:ad23fe03a082 854 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 855 } while(0)
mbed_official 573:ad23fe03a082 856
mbed_official 573:ad23fe03a082 857 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 858 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 859 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
mbed_official 573:ad23fe03a082 860 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 861 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
mbed_official 573:ad23fe03a082 862 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 863 } while(0)
mbed_official 573:ad23fe03a082 864
mbed_official 573:ad23fe03a082 865 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 866 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 867 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official 573:ad23fe03a082 868 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 869 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official 573:ad23fe03a082 870 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 871 } while(0)
mbed_official 573:ad23fe03a082 872
mbed_official 573:ad23fe03a082 873 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 874 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 875 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official 573:ad23fe03a082 876 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 877 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official 573:ad23fe03a082 878 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 879 } while(0)
mbed_official 573:ad23fe03a082 880
mbed_official 573:ad23fe03a082 881 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 882 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 883 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
mbed_official 573:ad23fe03a082 884 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 885 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
mbed_official 573:ad23fe03a082 886 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 887 } while(0)
mbed_official 573:ad23fe03a082 888
mbed_official 573:ad23fe03a082 889 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 890 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 891 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official 573:ad23fe03a082 892 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 893 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official 573:ad23fe03a082 894 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 895 } while(0)
mbed_official 573:ad23fe03a082 896
mbed_official 573:ad23fe03a082 897 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 898 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 899 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official 573:ad23fe03a082 900 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 901 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official 573:ad23fe03a082 902 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 903 } while(0)
mbed_official 573:ad23fe03a082 904
mbed_official 573:ad23fe03a082 905 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 906 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 907 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official 573:ad23fe03a082 908 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 909 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official 573:ad23fe03a082 910 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 911 } while(0)
mbed_official 573:ad23fe03a082 912
mbed_official 573:ad23fe03a082 913 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 914 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 915 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official 573:ad23fe03a082 916 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 917 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official 573:ad23fe03a082 918 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 919 } while(0)
mbed_official 573:ad23fe03a082 920
mbed_official 573:ad23fe03a082 921 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 922 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official 573:ad23fe03a082 924 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official 573:ad23fe03a082 926 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 927 } while(0)
mbed_official 573:ad23fe03a082 928
mbed_official 573:ad23fe03a082 929 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 930 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 931 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official 573:ad23fe03a082 932 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 933 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official 573:ad23fe03a082 934 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 935 } while(0)
mbed_official 573:ad23fe03a082 936
mbed_official 573:ad23fe03a082 937 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 938 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 939 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
mbed_official 573:ad23fe03a082 940 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 941 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
mbed_official 573:ad23fe03a082 942 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 943 } while(0)
mbed_official 573:ad23fe03a082 944
mbed_official 573:ad23fe03a082 945 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 946 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 947 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
mbed_official 573:ad23fe03a082 948 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 949 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
mbed_official 573:ad23fe03a082 950 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 951 } while(0)
mbed_official 573:ad23fe03a082 952
mbed_official 573:ad23fe03a082 953 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 954 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 955 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official 573:ad23fe03a082 956 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 957 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official 573:ad23fe03a082 958 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 959 } while(0)
mbed_official 573:ad23fe03a082 960
mbed_official 573:ad23fe03a082 961 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 962 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 963 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official 573:ad23fe03a082 964 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 965 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official 573:ad23fe03a082 966 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 967 } while(0)
mbed_official 573:ad23fe03a082 968
mbed_official 573:ad23fe03a082 969 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 970 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 971 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official 573:ad23fe03a082 972 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 973 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official 573:ad23fe03a082 974 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 975 } while(0)
mbed_official 573:ad23fe03a082 976
mbed_official 573:ad23fe03a082 977 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 978 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 979 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official 573:ad23fe03a082 980 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 981 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official 573:ad23fe03a082 982 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 983 } while(0)
mbed_official 573:ad23fe03a082 984
mbed_official 573:ad23fe03a082 985 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 986 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 987 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
mbed_official 573:ad23fe03a082 988 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 989 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
mbed_official 573:ad23fe03a082 990 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 991 } while(0)
mbed_official 573:ad23fe03a082 992
mbed_official 573:ad23fe03a082 993 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 994 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
mbed_official 573:ad23fe03a082 996 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
mbed_official 573:ad23fe03a082 998 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 999 } while(0)
mbed_official 573:ad23fe03a082 1000
mbed_official 573:ad23fe03a082 1001 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official 573:ad23fe03a082 1002 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official 573:ad23fe03a082 1003 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official 573:ad23fe03a082 1004 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official 573:ad23fe03a082 1005 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official 573:ad23fe03a082 1006 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official 573:ad23fe03a082 1007 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official 573:ad23fe03a082 1008 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official 573:ad23fe03a082 1009 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official 573:ad23fe03a082 1010 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
mbed_official 573:ad23fe03a082 1011 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official 573:ad23fe03a082 1012 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official 573:ad23fe03a082 1013 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
mbed_official 573:ad23fe03a082 1014 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official 573:ad23fe03a082 1015 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official 573:ad23fe03a082 1016 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official 573:ad23fe03a082 1017 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official 573:ad23fe03a082 1018 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official 573:ad23fe03a082 1019 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official 573:ad23fe03a082 1020 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official 573:ad23fe03a082 1021 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
mbed_official 573:ad23fe03a082 1022 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official 573:ad23fe03a082 1023 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official 573:ad23fe03a082 1024 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official 573:ad23fe03a082 1025 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official 573:ad23fe03a082 1026 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
mbed_official 573:ad23fe03a082 1027 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
mbed_official 573:ad23fe03a082 1028
mbed_official 573:ad23fe03a082 1029 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 573:ad23fe03a082 1030 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1031 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1032 * using it.
mbed_official 573:ad23fe03a082 1033 */
mbed_official 573:ad23fe03a082 1034 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1035 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1036 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official 573:ad23fe03a082 1037 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1038 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official 573:ad23fe03a082 1039 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1040 } while(0)
mbed_official 573:ad23fe03a082 1041
mbed_official 573:ad23fe03a082 1042 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1043 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1044 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official 573:ad23fe03a082 1045 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1046 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official 573:ad23fe03a082 1047 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1048 } while(0)
mbed_official 573:ad23fe03a082 1049
mbed_official 573:ad23fe03a082 1050 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1051 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1052 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official 573:ad23fe03a082 1053 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1054 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official 573:ad23fe03a082 1055 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1056 } while(0)
mbed_official 573:ad23fe03a082 1057
mbed_official 573:ad23fe03a082 1058 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1059 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1060 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official 573:ad23fe03a082 1061 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1062 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official 573:ad23fe03a082 1063 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1064 } while(0)
mbed_official 573:ad23fe03a082 1065
mbed_official 573:ad23fe03a082 1066 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1067 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1068 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official 573:ad23fe03a082 1069 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1070 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official 573:ad23fe03a082 1071 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1072 } while(0)
mbed_official 573:ad23fe03a082 1073
mbed_official 573:ad23fe03a082 1074 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1075 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1076 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official 573:ad23fe03a082 1077 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1078 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official 573:ad23fe03a082 1079 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1080 } while(0)
mbed_official 573:ad23fe03a082 1081
mbed_official 573:ad23fe03a082 1082 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1083 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1084 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official 573:ad23fe03a082 1085 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1086 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official 573:ad23fe03a082 1087 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1088 } while(0)
mbed_official 573:ad23fe03a082 1089
mbed_official 573:ad23fe03a082 1090 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1091 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1092 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
mbed_official 573:ad23fe03a082 1093 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1094 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
mbed_official 573:ad23fe03a082 1095 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1096 } while(0)
mbed_official 573:ad23fe03a082 1097
mbed_official 573:ad23fe03a082 1098 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1099 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1100 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official 573:ad23fe03a082 1101 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1102 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official 573:ad23fe03a082 1103 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1104 } while(0)
mbed_official 573:ad23fe03a082 1105
mbed_official 573:ad23fe03a082 1106 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1107 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1108 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
mbed_official 573:ad23fe03a082 1109 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1110 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
mbed_official 573:ad23fe03a082 1111 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1112 } while(0)
mbed_official 573:ad23fe03a082 1113
mbed_official 573:ad23fe03a082 1114 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1115 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1116 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official 573:ad23fe03a082 1117 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1118 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official 573:ad23fe03a082 1119 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1120 } while(0)
mbed_official 573:ad23fe03a082 1121
mbed_official 573:ad23fe03a082 1122 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1123 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1124 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official 573:ad23fe03a082 1125 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1126 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official 573:ad23fe03a082 1127 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1128 } while(0)
mbed_official 573:ad23fe03a082 1129
mbed_official 573:ad23fe03a082 1130 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1131 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1132 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official 573:ad23fe03a082 1133 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1134 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official 573:ad23fe03a082 1135 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1136 } while(0)
mbed_official 573:ad23fe03a082 1137
mbed_official 573:ad23fe03a082 1138 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1139 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1140 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official 573:ad23fe03a082 1141 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1142 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
mbed_official 573:ad23fe03a082 1143 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1144 } while(0)
mbed_official 573:ad23fe03a082 1145
mbed_official 573:ad23fe03a082 1146 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1147 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1148 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
mbed_official 573:ad23fe03a082 1149 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1150 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
mbed_official 573:ad23fe03a082 1151 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1152 } while(0)
mbed_official 573:ad23fe03a082 1153
mbed_official 573:ad23fe03a082 1154 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1155 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1156 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official 573:ad23fe03a082 1157 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1158 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
mbed_official 573:ad23fe03a082 1159 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1160 } while(0)
mbed_official 573:ad23fe03a082 1161
mbed_official 573:ad23fe03a082 1162 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1163 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1164 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
mbed_official 573:ad23fe03a082 1165 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1166 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
mbed_official 573:ad23fe03a082 1167 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1168 } while(0)
mbed_official 573:ad23fe03a082 1169
mbed_official 573:ad23fe03a082 1170 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1171 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
mbed_official 573:ad23fe03a082 1172 __IO uint32_t tmpreg; \
mbed_official 573:ad23fe03a082 1173 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
mbed_official 573:ad23fe03a082 1174 /* Delay after an RCC peripheral clock enabling */ \
mbed_official 573:ad23fe03a082 1175 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
mbed_official 573:ad23fe03a082 1176 UNUSED(tmpreg); \
mbed_official 573:ad23fe03a082 1177 } while(0)
mbed_official 573:ad23fe03a082 1178 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1179
mbed_official 573:ad23fe03a082 1180 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official 573:ad23fe03a082 1181 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official 573:ad23fe03a082 1182 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official 573:ad23fe03a082 1183 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official 573:ad23fe03a082 1184 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official 573:ad23fe03a082 1185 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official 573:ad23fe03a082 1186 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official 573:ad23fe03a082 1187 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
mbed_official 573:ad23fe03a082 1188 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official 573:ad23fe03a082 1189 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official 573:ad23fe03a082 1190 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official 573:ad23fe03a082 1191 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official 573:ad23fe03a082 1192 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official 573:ad23fe03a082 1193 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official 573:ad23fe03a082 1194 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
mbed_official 573:ad23fe03a082 1195 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official 573:ad23fe03a082 1196 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
mbed_official 573:ad23fe03a082 1197 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1198 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official 573:ad23fe03a082 1199 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1200 /**
mbed_official 573:ad23fe03a082 1201 * @}
mbed_official 573:ad23fe03a082 1202 */
mbed_official 573:ad23fe03a082 1203
mbed_official 573:ad23fe03a082 1204
mbed_official 573:ad23fe03a082 1205 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
mbed_official 573:ad23fe03a082 1206 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
mbed_official 573:ad23fe03a082 1207 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1208 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1209 * using it.
mbed_official 573:ad23fe03a082 1210 * @{
mbed_official 573:ad23fe03a082 1211 */
mbed_official 573:ad23fe03a082 1212
mbed_official 573:ad23fe03a082 1213 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
mbed_official 573:ad23fe03a082 1214 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1215 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1216 * using it.
mbed_official 573:ad23fe03a082 1217 */
mbed_official 573:ad23fe03a082 1218 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
mbed_official 573:ad23fe03a082 1219 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
mbed_official 573:ad23fe03a082 1220 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
mbed_official 573:ad23fe03a082 1221 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
mbed_official 573:ad23fe03a082 1222 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
mbed_official 573:ad23fe03a082 1223 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
mbed_official 573:ad23fe03a082 1224 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
mbed_official 573:ad23fe03a082 1225 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
mbed_official 573:ad23fe03a082 1226 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
mbed_official 573:ad23fe03a082 1227 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
mbed_official 573:ad23fe03a082 1228 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
mbed_official 573:ad23fe03a082 1229 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
mbed_official 573:ad23fe03a082 1230 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
mbed_official 573:ad23fe03a082 1231 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
mbed_official 573:ad23fe03a082 1232 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
mbed_official 573:ad23fe03a082 1233 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
mbed_official 573:ad23fe03a082 1234 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
mbed_official 573:ad23fe03a082 1235
mbed_official 573:ad23fe03a082 1236 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
mbed_official 573:ad23fe03a082 1237 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
mbed_official 573:ad23fe03a082 1238 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
mbed_official 573:ad23fe03a082 1239 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
mbed_official 573:ad23fe03a082 1240 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
mbed_official 573:ad23fe03a082 1241 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
mbed_official 573:ad23fe03a082 1242 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
mbed_official 573:ad23fe03a082 1243 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
mbed_official 573:ad23fe03a082 1244 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
mbed_official 573:ad23fe03a082 1245 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
mbed_official 573:ad23fe03a082 1246 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
mbed_official 573:ad23fe03a082 1247 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
mbed_official 573:ad23fe03a082 1248 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
mbed_official 573:ad23fe03a082 1249 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
mbed_official 573:ad23fe03a082 1250 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
mbed_official 573:ad23fe03a082 1251 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
mbed_official 573:ad23fe03a082 1252 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
mbed_official 573:ad23fe03a082 1253 /**
mbed_official 573:ad23fe03a082 1254 * @brief Enable ETHERNET clock.
mbed_official 573:ad23fe03a082 1255 */
mbed_official 573:ad23fe03a082 1256 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
mbed_official 573:ad23fe03a082 1257 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
mbed_official 573:ad23fe03a082 1258 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
mbed_official 573:ad23fe03a082 1259 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
mbed_official 573:ad23fe03a082 1260 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
mbed_official 573:ad23fe03a082 1261 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
mbed_official 573:ad23fe03a082 1262 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
mbed_official 573:ad23fe03a082 1263
mbed_official 573:ad23fe03a082 1264 /**
mbed_official 573:ad23fe03a082 1265 * @brief Disable ETHERNET clock.
mbed_official 573:ad23fe03a082 1266 */
mbed_official 573:ad23fe03a082 1267 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
mbed_official 573:ad23fe03a082 1268 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
mbed_official 573:ad23fe03a082 1269 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
mbed_official 573:ad23fe03a082 1270 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
mbed_official 573:ad23fe03a082 1271 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
mbed_official 573:ad23fe03a082 1272 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
mbed_official 573:ad23fe03a082 1273 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
mbed_official 573:ad23fe03a082 1274
mbed_official 573:ad23fe03a082 1275 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
mbed_official 573:ad23fe03a082 1276 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1277 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1278 * using it.
mbed_official 573:ad23fe03a082 1279 */
mbed_official 573:ad23fe03a082 1280 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
mbed_official 573:ad23fe03a082 1281 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
mbed_official 573:ad23fe03a082 1282 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
mbed_official 573:ad23fe03a082 1283
mbed_official 573:ad23fe03a082 1284
mbed_official 573:ad23fe03a082 1285 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
mbed_official 573:ad23fe03a082 1286 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
mbed_official 573:ad23fe03a082 1287 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
mbed_official 573:ad23fe03a082 1288
mbed_official 573:ad23fe03a082 1289 #if defined(STM32F756xx)
mbed_official 573:ad23fe03a082 1290 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
mbed_official 573:ad23fe03a082 1291 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
mbed_official 573:ad23fe03a082 1292 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
mbed_official 573:ad23fe03a082 1293 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
mbed_official 573:ad23fe03a082 1294 #endif /* STM32F756x */
mbed_official 573:ad23fe03a082 1295
mbed_official 573:ad23fe03a082 1296 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
mbed_official 573:ad23fe03a082 1297 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1298 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1299 * using it.
mbed_official 573:ad23fe03a082 1300 */
mbed_official 573:ad23fe03a082 1301 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
mbed_official 573:ad23fe03a082 1302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
mbed_official 573:ad23fe03a082 1303
mbed_official 573:ad23fe03a082 1304 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
mbed_official 573:ad23fe03a082 1305 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
mbed_official 573:ad23fe03a082 1306
mbed_official 573:ad23fe03a082 1307 /** @brief Get the enable or disable status of the APB1 peripheral clock.
mbed_official 573:ad23fe03a082 1308 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1309 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1310 * using it.
mbed_official 573:ad23fe03a082 1311 */
mbed_official 573:ad23fe03a082 1312 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
mbed_official 573:ad23fe03a082 1313 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
mbed_official 573:ad23fe03a082 1314 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
mbed_official 573:ad23fe03a082 1315 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
mbed_official 573:ad23fe03a082 1316 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
mbed_official 573:ad23fe03a082 1317 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
mbed_official 573:ad23fe03a082 1318 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
mbed_official 573:ad23fe03a082 1319 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
mbed_official 573:ad23fe03a082 1320 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
mbed_official 573:ad23fe03a082 1321 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
mbed_official 573:ad23fe03a082 1322 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
mbed_official 573:ad23fe03a082 1323 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
mbed_official 573:ad23fe03a082 1324 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
mbed_official 573:ad23fe03a082 1325 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
mbed_official 573:ad23fe03a082 1326 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
mbed_official 573:ad23fe03a082 1327 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
mbed_official 573:ad23fe03a082 1328 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
mbed_official 573:ad23fe03a082 1329 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
mbed_official 573:ad23fe03a082 1330 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
mbed_official 573:ad23fe03a082 1331 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
mbed_official 573:ad23fe03a082 1332 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
mbed_official 573:ad23fe03a082 1333 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
mbed_official 573:ad23fe03a082 1334 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
mbed_official 573:ad23fe03a082 1335 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
mbed_official 573:ad23fe03a082 1336 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
mbed_official 573:ad23fe03a082 1337 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
mbed_official 573:ad23fe03a082 1338 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
mbed_official 573:ad23fe03a082 1339
mbed_official 573:ad23fe03a082 1340 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
mbed_official 573:ad23fe03a082 1341 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
mbed_official 573:ad23fe03a082 1342 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
mbed_official 573:ad23fe03a082 1343 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
mbed_official 573:ad23fe03a082 1344 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
mbed_official 573:ad23fe03a082 1345 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
mbed_official 573:ad23fe03a082 1346 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
mbed_official 573:ad23fe03a082 1347 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
mbed_official 573:ad23fe03a082 1348 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
mbed_official 573:ad23fe03a082 1349 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
mbed_official 573:ad23fe03a082 1350 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
mbed_official 573:ad23fe03a082 1351 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
mbed_official 573:ad23fe03a082 1352 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
mbed_official 573:ad23fe03a082 1353 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
mbed_official 573:ad23fe03a082 1354 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
mbed_official 573:ad23fe03a082 1355 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
mbed_official 573:ad23fe03a082 1356 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
mbed_official 573:ad23fe03a082 1357 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
mbed_official 573:ad23fe03a082 1358 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
mbed_official 573:ad23fe03a082 1359 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
mbed_official 573:ad23fe03a082 1360 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
mbed_official 573:ad23fe03a082 1361 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
mbed_official 573:ad23fe03a082 1362 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
mbed_official 573:ad23fe03a082 1363 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
mbed_official 573:ad23fe03a082 1364 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
mbed_official 573:ad23fe03a082 1365 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
mbed_official 573:ad23fe03a082 1366 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
mbed_official 573:ad23fe03a082 1367
mbed_official 573:ad23fe03a082 1368 /** @brief Get the enable or disable status of the APB2 peripheral clock.
mbed_official 573:ad23fe03a082 1369 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 573:ad23fe03a082 1370 * is disabled and the application software has to enable this clock before
mbed_official 573:ad23fe03a082 1371 * using it.
mbed_official 573:ad23fe03a082 1372 */
mbed_official 573:ad23fe03a082 1373 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
mbed_official 573:ad23fe03a082 1374 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
mbed_official 573:ad23fe03a082 1375 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
mbed_official 573:ad23fe03a082 1376 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
mbed_official 573:ad23fe03a082 1377 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
mbed_official 573:ad23fe03a082 1378 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
mbed_official 573:ad23fe03a082 1379 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
mbed_official 573:ad23fe03a082 1380 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
mbed_official 573:ad23fe03a082 1381 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
mbed_official 573:ad23fe03a082 1382 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
mbed_official 573:ad23fe03a082 1383 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
mbed_official 573:ad23fe03a082 1384 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
mbed_official 573:ad23fe03a082 1385 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
mbed_official 573:ad23fe03a082 1386 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
mbed_official 573:ad23fe03a082 1387 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
mbed_official 573:ad23fe03a082 1388 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
mbed_official 573:ad23fe03a082 1389 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
mbed_official 573:ad23fe03a082 1390 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1391 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
mbed_official 573:ad23fe03a082 1392 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1393 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
mbed_official 573:ad23fe03a082 1394 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
mbed_official 573:ad23fe03a082 1395 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
mbed_official 573:ad23fe03a082 1396 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
mbed_official 573:ad23fe03a082 1397 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
mbed_official 573:ad23fe03a082 1398 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
mbed_official 573:ad23fe03a082 1399 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
mbed_official 573:ad23fe03a082 1400 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
mbed_official 573:ad23fe03a082 1401 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
mbed_official 573:ad23fe03a082 1402 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
mbed_official 573:ad23fe03a082 1403 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
mbed_official 573:ad23fe03a082 1404 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
mbed_official 573:ad23fe03a082 1405 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
mbed_official 573:ad23fe03a082 1406 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
mbed_official 573:ad23fe03a082 1407 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
mbed_official 573:ad23fe03a082 1408 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
mbed_official 573:ad23fe03a082 1409 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
mbed_official 573:ad23fe03a082 1410 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1411 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
mbed_official 573:ad23fe03a082 1412 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1413 /**
mbed_official 573:ad23fe03a082 1414 * @}
mbed_official 573:ad23fe03a082 1415 */
mbed_official 573:ad23fe03a082 1416
mbed_official 573:ad23fe03a082 1417 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
mbed_official 573:ad23fe03a082 1418 * @brief Forces or releases AHB/APB peripheral reset.
mbed_official 573:ad23fe03a082 1419 * @{
mbed_official 573:ad23fe03a082 1420 */
mbed_official 573:ad23fe03a082 1421
mbed_official 573:ad23fe03a082 1422 /** @brief Force or release AHB1 peripheral reset.
mbed_official 573:ad23fe03a082 1423 */
mbed_official 573:ad23fe03a082 1424 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
mbed_official 573:ad23fe03a082 1425 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
mbed_official 573:ad23fe03a082 1426 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
mbed_official 573:ad23fe03a082 1427 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
mbed_official 573:ad23fe03a082 1428 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
mbed_official 573:ad23fe03a082 1429 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
mbed_official 573:ad23fe03a082 1430 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
mbed_official 573:ad23fe03a082 1431 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
mbed_official 573:ad23fe03a082 1432 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
mbed_official 573:ad23fe03a082 1433 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
mbed_official 573:ad23fe03a082 1434 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
mbed_official 573:ad23fe03a082 1435 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
mbed_official 573:ad23fe03a082 1436 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
mbed_official 573:ad23fe03a082 1437 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
mbed_official 573:ad23fe03a082 1438 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
mbed_official 573:ad23fe03a082 1439
mbed_official 573:ad23fe03a082 1440 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
mbed_official 573:ad23fe03a082 1441 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
mbed_official 573:ad23fe03a082 1442 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official 573:ad23fe03a082 1443 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official 573:ad23fe03a082 1444 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
mbed_official 573:ad23fe03a082 1445 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
mbed_official 573:ad23fe03a082 1446 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
mbed_official 573:ad23fe03a082 1447 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
mbed_official 573:ad23fe03a082 1448 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
mbed_official 573:ad23fe03a082 1449 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official 573:ad23fe03a082 1450 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official 573:ad23fe03a082 1451 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
mbed_official 573:ad23fe03a082 1452 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official 573:ad23fe03a082 1453 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
mbed_official 573:ad23fe03a082 1454 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
mbed_official 573:ad23fe03a082 1455
mbed_official 573:ad23fe03a082 1456 /** @brief Force or release AHB2 peripheral reset.
mbed_official 573:ad23fe03a082 1457 */
mbed_official 573:ad23fe03a082 1458 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
mbed_official 573:ad23fe03a082 1459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
mbed_official 573:ad23fe03a082 1460
mbed_official 573:ad23fe03a082 1461 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
mbed_official 573:ad23fe03a082 1462 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
mbed_official 573:ad23fe03a082 1463
mbed_official 573:ad23fe03a082 1464 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
mbed_official 573:ad23fe03a082 1465 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official 573:ad23fe03a082 1466 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
mbed_official 573:ad23fe03a082 1467 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
mbed_official 573:ad23fe03a082 1468
mbed_official 573:ad23fe03a082 1469 #if defined(STM32F756xx)
mbed_official 573:ad23fe03a082 1470 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
mbed_official 573:ad23fe03a082 1471 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
mbed_official 573:ad23fe03a082 1472 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official 573:ad23fe03a082 1473 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official 573:ad23fe03a082 1474 #endif /* STM32F756xx */
mbed_official 573:ad23fe03a082 1475
mbed_official 573:ad23fe03a082 1476 /** @brief Force or release AHB3 peripheral reset
mbed_official 573:ad23fe03a082 1477 */
mbed_official 573:ad23fe03a082 1478 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
mbed_official 573:ad23fe03a082 1479 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
mbed_official 573:ad23fe03a082 1480 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
mbed_official 573:ad23fe03a082 1481
mbed_official 573:ad23fe03a082 1482 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
mbed_official 573:ad23fe03a082 1483 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official 573:ad23fe03a082 1484 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
mbed_official 573:ad23fe03a082 1485
mbed_official 573:ad23fe03a082 1486 /** @brief Force or release APB1 peripheral reset.
mbed_official 573:ad23fe03a082 1487 */
mbed_official 573:ad23fe03a082 1488 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
mbed_official 573:ad23fe03a082 1489 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
mbed_official 573:ad23fe03a082 1490 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
mbed_official 573:ad23fe03a082 1491 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
mbed_official 573:ad23fe03a082 1492 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
mbed_official 573:ad23fe03a082 1493 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
mbed_official 573:ad23fe03a082 1494 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
mbed_official 573:ad23fe03a082 1495 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
mbed_official 573:ad23fe03a082 1496 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
mbed_official 573:ad23fe03a082 1497 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
mbed_official 573:ad23fe03a082 1498 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
mbed_official 573:ad23fe03a082 1499 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
mbed_official 573:ad23fe03a082 1500 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
mbed_official 573:ad23fe03a082 1501 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
mbed_official 573:ad23fe03a082 1502 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
mbed_official 573:ad23fe03a082 1503 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
mbed_official 573:ad23fe03a082 1504 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
mbed_official 573:ad23fe03a082 1505 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
mbed_official 573:ad23fe03a082 1506 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
mbed_official 573:ad23fe03a082 1507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
mbed_official 573:ad23fe03a082 1508 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
mbed_official 573:ad23fe03a082 1509 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
mbed_official 573:ad23fe03a082 1510 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
mbed_official 573:ad23fe03a082 1511 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
mbed_official 573:ad23fe03a082 1512 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
mbed_official 573:ad23fe03a082 1513 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
mbed_official 573:ad23fe03a082 1514 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
mbed_official 573:ad23fe03a082 1515
mbed_official 573:ad23fe03a082 1516 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official 573:ad23fe03a082 1517 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official 573:ad23fe03a082 1518 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official 573:ad23fe03a082 1519 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official 573:ad23fe03a082 1520 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official 573:ad23fe03a082 1521 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official 573:ad23fe03a082 1522 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official 573:ad23fe03a082 1523 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official 573:ad23fe03a082 1524 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official 573:ad23fe03a082 1525 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
mbed_official 573:ad23fe03a082 1526 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official 573:ad23fe03a082 1527 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official 573:ad23fe03a082 1528 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
mbed_official 573:ad23fe03a082 1529 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official 573:ad23fe03a082 1530 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official 573:ad23fe03a082 1531 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official 573:ad23fe03a082 1532 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official 573:ad23fe03a082 1533 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official 573:ad23fe03a082 1534 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official 573:ad23fe03a082 1535 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official 573:ad23fe03a082 1536 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
mbed_official 573:ad23fe03a082 1537 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official 573:ad23fe03a082 1538 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official 573:ad23fe03a082 1539 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official 573:ad23fe03a082 1540 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official 573:ad23fe03a082 1541 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
mbed_official 573:ad23fe03a082 1542 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
mbed_official 573:ad23fe03a082 1543
mbed_official 573:ad23fe03a082 1544 /** @brief Force or release APB2 peripheral reset.
mbed_official 573:ad23fe03a082 1545 */
mbed_official 573:ad23fe03a082 1546 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
mbed_official 573:ad23fe03a082 1547 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
mbed_official 573:ad23fe03a082 1548 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
mbed_official 573:ad23fe03a082 1549 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
mbed_official 573:ad23fe03a082 1550 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
mbed_official 573:ad23fe03a082 1551 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
mbed_official 573:ad23fe03a082 1552 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
mbed_official 573:ad23fe03a082 1553 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
mbed_official 573:ad23fe03a082 1554 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
mbed_official 573:ad23fe03a082 1555 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
mbed_official 573:ad23fe03a082 1556 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
mbed_official 573:ad23fe03a082 1557 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
mbed_official 573:ad23fe03a082 1558 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
mbed_official 573:ad23fe03a082 1559 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
mbed_official 573:ad23fe03a082 1560 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
mbed_official 573:ad23fe03a082 1561 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1562 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
mbed_official 573:ad23fe03a082 1563 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1564
mbed_official 573:ad23fe03a082 1565 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official 573:ad23fe03a082 1566 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official 573:ad23fe03a082 1567 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official 573:ad23fe03a082 1568 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official 573:ad23fe03a082 1569 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
mbed_official 573:ad23fe03a082 1570 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
mbed_official 573:ad23fe03a082 1571 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official 573:ad23fe03a082 1572 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official 573:ad23fe03a082 1573 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official 573:ad23fe03a082 1574 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official 573:ad23fe03a082 1575 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official 573:ad23fe03a082 1576 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official 573:ad23fe03a082 1577 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
mbed_official 573:ad23fe03a082 1578 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official 573:ad23fe03a082 1579 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
mbed_official 573:ad23fe03a082 1580 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1581 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official 573:ad23fe03a082 1582 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1583 /**
mbed_official 573:ad23fe03a082 1584 * @}
mbed_official 573:ad23fe03a082 1585 */
mbed_official 573:ad23fe03a082 1586
mbed_official 573:ad23fe03a082 1587 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
mbed_official 573:ad23fe03a082 1588 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1589 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1590 * power consumption.
mbed_official 573:ad23fe03a082 1591 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1592 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1593 * @{
mbed_official 573:ad23fe03a082 1594 */
mbed_official 573:ad23fe03a082 1595
mbed_official 573:ad23fe03a082 1596 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1597 */
mbed_official 573:ad23fe03a082 1598 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
mbed_official 573:ad23fe03a082 1599 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
mbed_official 573:ad23fe03a082 1600 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
mbed_official 573:ad23fe03a082 1601 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 573:ad23fe03a082 1602 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official 573:ad23fe03a082 1603 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
mbed_official 573:ad23fe03a082 1604 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
mbed_official 573:ad23fe03a082 1605 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 573:ad23fe03a082 1606 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 573:ad23fe03a082 1607 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 573:ad23fe03a082 1608 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 573:ad23fe03a082 1609 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 573:ad23fe03a082 1610 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 573:ad23fe03a082 1611 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 573:ad23fe03a082 1612 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
mbed_official 573:ad23fe03a082 1613 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
mbed_official 573:ad23fe03a082 1614 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
mbed_official 573:ad23fe03a082 1615 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
mbed_official 573:ad23fe03a082 1616 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
mbed_official 573:ad23fe03a082 1617 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 573:ad23fe03a082 1618 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 573:ad23fe03a082 1619 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
mbed_official 573:ad23fe03a082 1620 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official 573:ad23fe03a082 1621 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 573:ad23fe03a082 1622 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 573:ad23fe03a082 1623
mbed_official 573:ad23fe03a082 1624 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
mbed_official 573:ad23fe03a082 1625 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
mbed_official 573:ad23fe03a082 1626 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
mbed_official 573:ad23fe03a082 1627 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 573:ad23fe03a082 1628 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official 573:ad23fe03a082 1629 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
mbed_official 573:ad23fe03a082 1630 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
mbed_official 573:ad23fe03a082 1631 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 573:ad23fe03a082 1632 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 573:ad23fe03a082 1633 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 573:ad23fe03a082 1634 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 573:ad23fe03a082 1635 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 573:ad23fe03a082 1636 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 573:ad23fe03a082 1637 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 573:ad23fe03a082 1638 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
mbed_official 573:ad23fe03a082 1639 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
mbed_official 573:ad23fe03a082 1640 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
mbed_official 573:ad23fe03a082 1641 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
mbed_official 573:ad23fe03a082 1642 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
mbed_official 573:ad23fe03a082 1643 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 573:ad23fe03a082 1644 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 573:ad23fe03a082 1645 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
mbed_official 573:ad23fe03a082 1646 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official 573:ad23fe03a082 1647 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 573:ad23fe03a082 1648 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 573:ad23fe03a082 1649
mbed_official 573:ad23fe03a082 1650 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1651 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1652 * power consumption.
mbed_official 573:ad23fe03a082 1653 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1654 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1655 */
mbed_official 573:ad23fe03a082 1656 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
mbed_official 573:ad23fe03a082 1657 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official 573:ad23fe03a082 1658
mbed_official 573:ad23fe03a082 1659 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
mbed_official 573:ad23fe03a082 1660 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
mbed_official 573:ad23fe03a082 1661
mbed_official 573:ad23fe03a082 1662 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
mbed_official 573:ad23fe03a082 1663 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
mbed_official 573:ad23fe03a082 1664
mbed_official 573:ad23fe03a082 1665 #if defined(STM32F756xx)
mbed_official 573:ad23fe03a082 1666 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official 573:ad23fe03a082 1667 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
mbed_official 573:ad23fe03a082 1668
mbed_official 573:ad23fe03a082 1669 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official 573:ad23fe03a082 1670 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official 573:ad23fe03a082 1671 #endif /* STM32F756xx */
mbed_official 573:ad23fe03a082 1672
mbed_official 573:ad23fe03a082 1673 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1675 * power consumption.
mbed_official 573:ad23fe03a082 1676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1677 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1678 */
mbed_official 573:ad23fe03a082 1679 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
mbed_official 573:ad23fe03a082 1680 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official 573:ad23fe03a082 1681
mbed_official 573:ad23fe03a082 1682 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
mbed_official 573:ad23fe03a082 1683 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
mbed_official 573:ad23fe03a082 1684
mbed_official 573:ad23fe03a082 1685 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1686 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1687 * power consumption.
mbed_official 573:ad23fe03a082 1688 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1689 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1690 */
mbed_official 573:ad23fe03a082 1691 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
mbed_official 573:ad23fe03a082 1692 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
mbed_official 573:ad23fe03a082 1693 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
mbed_official 573:ad23fe03a082 1694 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
mbed_official 573:ad23fe03a082 1695 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
mbed_official 573:ad23fe03a082 1696 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
mbed_official 573:ad23fe03a082 1697 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
mbed_official 573:ad23fe03a082 1698 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
mbed_official 573:ad23fe03a082 1699 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
mbed_official 573:ad23fe03a082 1700 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
mbed_official 573:ad23fe03a082 1701 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
mbed_official 573:ad23fe03a082 1702 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
mbed_official 573:ad23fe03a082 1703 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
mbed_official 573:ad23fe03a082 1704 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
mbed_official 573:ad23fe03a082 1705 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
mbed_official 573:ad23fe03a082 1706 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
mbed_official 573:ad23fe03a082 1707 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
mbed_official 573:ad23fe03a082 1708 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
mbed_official 573:ad23fe03a082 1709 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
mbed_official 573:ad23fe03a082 1710 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
mbed_official 573:ad23fe03a082 1711 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
mbed_official 573:ad23fe03a082 1712 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
mbed_official 573:ad23fe03a082 1713 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
mbed_official 573:ad23fe03a082 1714 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
mbed_official 573:ad23fe03a082 1715 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
mbed_official 573:ad23fe03a082 1716 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
mbed_official 573:ad23fe03a082 1717 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
mbed_official 573:ad23fe03a082 1718
mbed_official 573:ad23fe03a082 1719 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official 573:ad23fe03a082 1720 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official 573:ad23fe03a082 1721 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official 573:ad23fe03a082 1722 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
mbed_official 573:ad23fe03a082 1723 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official 573:ad23fe03a082 1724 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official 573:ad23fe03a082 1725 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official 573:ad23fe03a082 1726 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official 573:ad23fe03a082 1727 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official 573:ad23fe03a082 1728 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
mbed_official 573:ad23fe03a082 1729 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official 573:ad23fe03a082 1730 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
mbed_official 573:ad23fe03a082 1731 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
mbed_official 573:ad23fe03a082 1732 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official 573:ad23fe03a082 1733 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official 573:ad23fe03a082 1734 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official 573:ad23fe03a082 1735 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official 573:ad23fe03a082 1736 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official 573:ad23fe03a082 1737 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official 573:ad23fe03a082 1738 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
mbed_official 573:ad23fe03a082 1739 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
mbed_official 573:ad23fe03a082 1740 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official 573:ad23fe03a082 1741 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official 573:ad23fe03a082 1742 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
mbed_official 573:ad23fe03a082 1743 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official 573:ad23fe03a082 1744 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official 573:ad23fe03a082 1745 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
mbed_official 573:ad23fe03a082 1746
mbed_official 573:ad23fe03a082 1747 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1748 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1749 * power consumption.
mbed_official 573:ad23fe03a082 1750 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1751 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1752 */
mbed_official 573:ad23fe03a082 1753 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
mbed_official 573:ad23fe03a082 1754 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
mbed_official 573:ad23fe03a082 1755 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
mbed_official 573:ad23fe03a082 1756 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
mbed_official 573:ad23fe03a082 1757 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
mbed_official 573:ad23fe03a082 1758 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
mbed_official 573:ad23fe03a082 1759 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
mbed_official 573:ad23fe03a082 1760 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
mbed_official 573:ad23fe03a082 1761 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
mbed_official 573:ad23fe03a082 1762 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
mbed_official 573:ad23fe03a082 1763 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
mbed_official 573:ad23fe03a082 1764 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
mbed_official 573:ad23fe03a082 1765 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
mbed_official 573:ad23fe03a082 1766 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
mbed_official 573:ad23fe03a082 1767 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
mbed_official 573:ad23fe03a082 1768 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
mbed_official 573:ad23fe03a082 1769 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
mbed_official 573:ad23fe03a082 1770 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1771 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
mbed_official 573:ad23fe03a082 1772 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1773
mbed_official 573:ad23fe03a082 1774 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
mbed_official 573:ad23fe03a082 1775 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official 573:ad23fe03a082 1776 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official 573:ad23fe03a082 1777 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
mbed_official 573:ad23fe03a082 1778 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official 573:ad23fe03a082 1779 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official 573:ad23fe03a082 1780 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official 573:ad23fe03a082 1781 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
mbed_official 573:ad23fe03a082 1782 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official 573:ad23fe03a082 1783 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
mbed_official 573:ad23fe03a082 1784 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official 573:ad23fe03a082 1785 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official 573:ad23fe03a082 1786 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official 573:ad23fe03a082 1787 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official 573:ad23fe03a082 1788 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
mbed_official 573:ad23fe03a082 1789 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official 573:ad23fe03a082 1790 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
mbed_official 573:ad23fe03a082 1791 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1792 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official 573:ad23fe03a082 1793 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1794 /**
mbed_official 573:ad23fe03a082 1795 * @}
mbed_official 573:ad23fe03a082 1796 */
mbed_official 573:ad23fe03a082 1797
mbed_official 573:ad23fe03a082 1798 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
mbed_official 573:ad23fe03a082 1799 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1800 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1801 * power consumption.
mbed_official 573:ad23fe03a082 1802 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1803 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1804 * @{
mbed_official 573:ad23fe03a082 1805 */
mbed_official 573:ad23fe03a082 1806
mbed_official 573:ad23fe03a082 1807 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1808 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1809 * power consumption.
mbed_official 573:ad23fe03a082 1810 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1811 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1812 */
mbed_official 573:ad23fe03a082 1813 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1814 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
mbed_official 573:ad23fe03a082 1815 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1816 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1817 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1818 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1819 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1820 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1821 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1822 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1823 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1824 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1825 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1826 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
mbed_official 573:ad23fe03a082 1827 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
mbed_official 573:ad23fe03a082 1828 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1829 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1830 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1831 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
mbed_official 573:ad23fe03a082 1832 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1833 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1834 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1835 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
mbed_official 573:ad23fe03a082 1836 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1837 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1838
mbed_official 573:ad23fe03a082 1839 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1840 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
mbed_official 573:ad23fe03a082 1841 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1842 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1843 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1844 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1845 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1846 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1847 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1848 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1849 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1850 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1851 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1852 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
mbed_official 573:ad23fe03a082 1853 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
mbed_official 573:ad23fe03a082 1854 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1855 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1856 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1857 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
mbed_official 573:ad23fe03a082 1858 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1859 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1860 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1861 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
mbed_official 573:ad23fe03a082 1862 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1863 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1864
mbed_official 573:ad23fe03a082 1865 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1866 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1867 * power consumption.
mbed_official 573:ad23fe03a082 1868 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1869 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1870 */
mbed_official 573:ad23fe03a082 1871 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
mbed_official 573:ad23fe03a082 1872 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
mbed_official 573:ad23fe03a082 1873
mbed_official 573:ad23fe03a082 1874 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1875 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1876
mbed_official 573:ad23fe03a082 1877 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1878 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1879
mbed_official 573:ad23fe03a082 1880 #if defined(STM32F756xx)
mbed_official 573:ad23fe03a082 1881 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1882 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1883
mbed_official 573:ad23fe03a082 1884 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1885 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1886 #endif /* STM32F756xx */
mbed_official 573:ad23fe03a082 1887
mbed_official 573:ad23fe03a082 1888 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1889 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1890 * power consumption.
mbed_official 573:ad23fe03a082 1891 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1892 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1893 */
mbed_official 573:ad23fe03a082 1894 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1895 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1896
mbed_official 573:ad23fe03a082 1897 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
mbed_official 573:ad23fe03a082 1898 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
mbed_official 573:ad23fe03a082 1899
mbed_official 573:ad23fe03a082 1900 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1901 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1902 * power consumption.
mbed_official 573:ad23fe03a082 1903 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1904 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1905 */
mbed_official 573:ad23fe03a082 1906 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1907 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1908 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1909 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1910 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1911 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1912 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1913 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1914 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1915 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1916 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1917 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1918 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1919 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1920 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1921 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1922 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1923 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1924 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1925 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1926 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1927 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1928 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1929 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1930 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1931 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1932 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1933
mbed_official 573:ad23fe03a082 1934 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1935 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1936 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1937 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1938 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1939 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1940 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1941 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1942 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1943 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1944 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1945 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1946 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1947 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1948 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1949 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1950 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1951 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1952 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1953 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1954 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1955 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1956 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1957 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1958 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
mbed_official 573:ad23fe03a082 1959 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1960 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1961
mbed_official 573:ad23fe03a082 1962 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 573:ad23fe03a082 1963 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 573:ad23fe03a082 1964 * power consumption.
mbed_official 573:ad23fe03a082 1965 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 573:ad23fe03a082 1966 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 573:ad23fe03a082 1967 */
mbed_official 573:ad23fe03a082 1968 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1969 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1970 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1971 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1972 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1973 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1974 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1975 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1976 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1977 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1978 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1979 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1980 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1981 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1982 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1983 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1984 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
mbed_official 573:ad23fe03a082 1985 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 1986 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
mbed_official 573:ad23fe03a082 1987 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 1988
mbed_official 573:ad23fe03a082 1989 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1990 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1991 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1992 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1993 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1994 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1995 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1996 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1997 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1998 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
mbed_official 573:ad23fe03a082 1999 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2000 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2001 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2002 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2003 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2004 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2005 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
mbed_official 573:ad23fe03a082 2006 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 2007 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
mbed_official 573:ad23fe03a082 2008 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 2009 /**
mbed_official 573:ad23fe03a082 2010 * @}
mbed_official 573:ad23fe03a082 2011 */
mbed_official 573:ad23fe03a082 2012
mbed_official 573:ad23fe03a082 2013 /*---------------------------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 2014
mbed_official 573:ad23fe03a082 2015 /** @brief Macro to configure the Timers clocks prescalers
mbed_official 573:ad23fe03a082 2016 * @param __PRESC__ : specifies the Timers clocks prescalers selection
mbed_official 573:ad23fe03a082 2017 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2018 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
mbed_official 573:ad23fe03a082 2019 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
mbed_official 573:ad23fe03a082 2020 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
mbed_official 573:ad23fe03a082 2021 * division by 4 or more.
mbed_official 573:ad23fe03a082 2022 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
mbed_official 573:ad23fe03a082 2023 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
mbed_official 573:ad23fe03a082 2024 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
mbed_official 573:ad23fe03a082 2025 * to division by 8 or more.
mbed_official 573:ad23fe03a082 2026 */
mbed_official 573:ad23fe03a082 2027 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
mbed_official 573:ad23fe03a082 2028 RCC->DCKCFGR1 |= (__PRESC__);\
mbed_official 573:ad23fe03a082 2029 }while(0)
mbed_official 573:ad23fe03a082 2030
mbed_official 573:ad23fe03a082 2031 /** @brief Macros to Enable or Disable the PLLISAI.
mbed_official 573:ad23fe03a082 2032 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 573:ad23fe03a082 2033 */
mbed_official 573:ad23fe03a082 2034 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
mbed_official 573:ad23fe03a082 2035 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
mbed_official 573:ad23fe03a082 2036
mbed_official 573:ad23fe03a082 2037 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official 573:ad23fe03a082 2038 * @note This function must be used only when the PLLSAI is disabled.
mbed_official 573:ad23fe03a082 2039 * @note PLLSAI clock source is common with the main PLL (configured in
mbed_official 573:ad23fe03a082 2040 * RCC_PLLConfig function )
mbed_official 573:ad23fe03a082 2041 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official 573:ad23fe03a082 2042 * This parameter must be a number between Min_Data = 49 and Max_Data = 432.
mbed_official 573:ad23fe03a082 2043 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official 573:ad23fe03a082 2044 * output frequency is between Min_Data = 49 and Max_Data = 432 MHz.
mbed_official 573:ad23fe03a082 2045 * @param __PLLSAIQ__: specifies the division factor for SAI clock
mbed_official 573:ad23fe03a082 2046 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 573:ad23fe03a082 2047 * @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official 573:ad23fe03a082 2048 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 573:ad23fe03a082 2049 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
mbed_official 573:ad23fe03a082 2050 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider .
mbed_official 573:ad23fe03a082 2051 */
mbed_official 573:ad23fe03a082 2052 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
mbed_official 573:ad23fe03a082 2053
mbed_official 573:ad23fe03a082 2054 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
mbed_official 573:ad23fe03a082 2055 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 573:ad23fe03a082 2056 * @note PLLI2S clock source is common with the main PLL (configured in
mbed_official 573:ad23fe03a082 2057 * HAL_RCC_ClockConfig() API)
mbed_official 573:ad23fe03a082 2058 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 573:ad23fe03a082 2059 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 573:ad23fe03a082 2060 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official 573:ad23fe03a082 2061 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 573:ad23fe03a082 2062 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
mbed_official 573:ad23fe03a082 2063 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 573:ad23fe03a082 2064 * @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official 573:ad23fe03a082 2065 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 573:ad23fe03a082 2066 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official 573:ad23fe03a082 2067 * on the I2S clock frequency.
mbed_official 573:ad23fe03a082 2068 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
mbed_official 573:ad23fe03a082 2069 * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8
mbed_official 573:ad23fe03a082 2070 */
mbed_official 573:ad23fe03a082 2071 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
mbed_official 573:ad23fe03a082 2072
mbed_official 573:ad23fe03a082 2073 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
mbed_official 573:ad23fe03a082 2074 * @note This function must be called before enabling the PLLI2S.
mbed_official 573:ad23fe03a082 2075 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
mbed_official 573:ad23fe03a082 2076 * This parameter must be a number between 1 and 32.
mbed_official 573:ad23fe03a082 2077 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
mbed_official 573:ad23fe03a082 2078 */
mbed_official 573:ad23fe03a082 2079 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
mbed_official 573:ad23fe03a082 2080
mbed_official 573:ad23fe03a082 2081 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
mbed_official 573:ad23fe03a082 2082 * @note This function must be called before enabling the PLLSAI.
mbed_official 573:ad23fe03a082 2083 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
mbed_official 573:ad23fe03a082 2084 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
mbed_official 573:ad23fe03a082 2085 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
mbed_official 573:ad23fe03a082 2086 */
mbed_official 573:ad23fe03a082 2087 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
mbed_official 573:ad23fe03a082 2088
mbed_official 573:ad23fe03a082 2089 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
mbed_official 573:ad23fe03a082 2090 *
mbed_official 573:ad23fe03a082 2091 * @note This function must be called before enabling the PLLSAI.
mbed_official 573:ad23fe03a082 2092 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official 573:ad23fe03a082 2093 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
mbed_official 573:ad23fe03a082 2094 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
mbed_official 573:ad23fe03a082 2095 */
mbed_official 573:ad23fe03a082 2096 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
mbed_official 573:ad23fe03a082 2097 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
mbed_official 573:ad23fe03a082 2098
mbed_official 573:ad23fe03a082 2099 /** @brief Macro to configure SAI1 clock source selection.
mbed_official 573:ad23fe03a082 2100 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 573:ad23fe03a082 2101 * the SAI clock.
mbed_official 573:ad23fe03a082 2102 * @param __SOURCE__: specifies the SAI1 clock source.
mbed_official 573:ad23fe03a082 2103 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2104 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 573:ad23fe03a082 2105 * as SAI1 clock.
mbed_official 573:ad23fe03a082 2106 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 573:ad23fe03a082 2107 * as SAI1 clock.
mbed_official 573:ad23fe03a082 2108 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
mbed_official 573:ad23fe03a082 2109 * used as SAI1 clock.
mbed_official 573:ad23fe03a082 2110 */
mbed_official 573:ad23fe03a082 2111 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
mbed_official 573:ad23fe03a082 2112 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
mbed_official 573:ad23fe03a082 2113
mbed_official 573:ad23fe03a082 2114 /** @brief Macro to get the SAI1 clock source.
mbed_official 573:ad23fe03a082 2115 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2116 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 573:ad23fe03a082 2117 * as SAI1 clock.
mbed_official 573:ad23fe03a082 2118 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 573:ad23fe03a082 2119 * as SAI1 clock.
mbed_official 573:ad23fe03a082 2120 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
mbed_official 573:ad23fe03a082 2121 * used as SAI1 clock.
mbed_official 573:ad23fe03a082 2122 */
mbed_official 573:ad23fe03a082 2123 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
mbed_official 573:ad23fe03a082 2124
mbed_official 573:ad23fe03a082 2125
mbed_official 573:ad23fe03a082 2126 /** @brief Macro to configure SAI2 clock source selection.
mbed_official 573:ad23fe03a082 2127 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 573:ad23fe03a082 2128 * the SAI clock.
mbed_official 573:ad23fe03a082 2129 * @param __SOURCE__: specifies the SAI2 clock source.
mbed_official 573:ad23fe03a082 2130 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2131 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 573:ad23fe03a082 2132 * as SAI2 clock.
mbed_official 573:ad23fe03a082 2133 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 573:ad23fe03a082 2134 * as SAI2 clock.
mbed_official 573:ad23fe03a082 2135 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
mbed_official 573:ad23fe03a082 2136 * used as SAI2 clock.
mbed_official 573:ad23fe03a082 2137 */
mbed_official 573:ad23fe03a082 2138 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
mbed_official 573:ad23fe03a082 2139 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
mbed_official 573:ad23fe03a082 2140
mbed_official 573:ad23fe03a082 2141
mbed_official 573:ad23fe03a082 2142 /** @brief Macro to get the SAI2 clock source.
mbed_official 573:ad23fe03a082 2143 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2144 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 573:ad23fe03a082 2145 * as SAI2 clock.
mbed_official 573:ad23fe03a082 2146 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 573:ad23fe03a082 2147 * as SAI2 clock.
mbed_official 573:ad23fe03a082 2148 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
mbed_official 573:ad23fe03a082 2149 * used as SAI2 clock.
mbed_official 573:ad23fe03a082 2150 */
mbed_official 573:ad23fe03a082 2151 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
mbed_official 573:ad23fe03a082 2152
mbed_official 573:ad23fe03a082 2153
mbed_official 573:ad23fe03a082 2154 /** @brief Enable PLLSAI_RDY interrupt.
mbed_official 573:ad23fe03a082 2155 */
mbed_official 573:ad23fe03a082 2156 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
mbed_official 573:ad23fe03a082 2157
mbed_official 573:ad23fe03a082 2158 /** @brief Disable PLLSAI_RDY interrupt.
mbed_official 573:ad23fe03a082 2159 */
mbed_official 573:ad23fe03a082 2160 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
mbed_official 573:ad23fe03a082 2161
mbed_official 573:ad23fe03a082 2162 /** @brief Clear the PLLSAI RDY interrupt pending bits.
mbed_official 573:ad23fe03a082 2163 */
mbed_official 573:ad23fe03a082 2164 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
mbed_official 573:ad23fe03a082 2165
mbed_official 573:ad23fe03a082 2166 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
mbed_official 573:ad23fe03a082 2167 * @retval The new state (TRUE or FALSE).
mbed_official 573:ad23fe03a082 2168 */
mbed_official 573:ad23fe03a082 2169 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
mbed_official 573:ad23fe03a082 2170
mbed_official 573:ad23fe03a082 2171 /** @brief Check PLLSAI RDY flag is set or not.
mbed_official 573:ad23fe03a082 2172 * @retval The new state (TRUE or FALSE).
mbed_official 573:ad23fe03a082 2173 */
mbed_official 573:ad23fe03a082 2174 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
mbed_official 573:ad23fe03a082 2175
mbed_official 573:ad23fe03a082 2176 /** @brief Macro to Get I2S clock source selection.
mbed_official 573:ad23fe03a082 2177 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2178 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
mbed_official 573:ad23fe03a082 2179 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
mbed_official 573:ad23fe03a082 2180 */
mbed_official 573:ad23fe03a082 2181 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
mbed_official 573:ad23fe03a082 2182
mbed_official 573:ad23fe03a082 2183 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
mbed_official 573:ad23fe03a082 2184 *
mbed_official 573:ad23fe03a082 2185 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
mbed_official 573:ad23fe03a082 2186 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2187 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
mbed_official 573:ad23fe03a082 2188 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official 573:ad23fe03a082 2189 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official 573:ad23fe03a082 2190 */
mbed_official 573:ad23fe03a082 2191 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2192 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2193
mbed_official 573:ad23fe03a082 2194 /** @brief Macro to get the I2C1 clock source.
mbed_official 573:ad23fe03a082 2195 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2196 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
mbed_official 573:ad23fe03a082 2197 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official 573:ad23fe03a082 2198 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official 573:ad23fe03a082 2199 */
mbed_official 573:ad23fe03a082 2200 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
mbed_official 573:ad23fe03a082 2201
mbed_official 573:ad23fe03a082 2202 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official 573:ad23fe03a082 2203 *
mbed_official 573:ad23fe03a082 2204 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
mbed_official 573:ad23fe03a082 2205 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2206 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
mbed_official 573:ad23fe03a082 2207 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official 573:ad23fe03a082 2208 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official 573:ad23fe03a082 2209 */
mbed_official 573:ad23fe03a082 2210 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2211 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2212
mbed_official 573:ad23fe03a082 2213 /** @brief Macro to get the I2C2 clock source.
mbed_official 573:ad23fe03a082 2214 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2215 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
mbed_official 573:ad23fe03a082 2216 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official 573:ad23fe03a082 2217 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official 573:ad23fe03a082 2218 */
mbed_official 573:ad23fe03a082 2219 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
mbed_official 573:ad23fe03a082 2220
mbed_official 573:ad23fe03a082 2221 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
mbed_official 573:ad23fe03a082 2222 *
mbed_official 573:ad23fe03a082 2223 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
mbed_official 573:ad23fe03a082 2224 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2225 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
mbed_official 573:ad23fe03a082 2226 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official 573:ad23fe03a082 2227 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official 573:ad23fe03a082 2228 */
mbed_official 573:ad23fe03a082 2229 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2230 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2231
mbed_official 573:ad23fe03a082 2232 /** @brief macro to get the I2C3 clock source.
mbed_official 573:ad23fe03a082 2233 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2234 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
mbed_official 573:ad23fe03a082 2235 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official 573:ad23fe03a082 2236 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official 573:ad23fe03a082 2237 */
mbed_official 573:ad23fe03a082 2238 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
mbed_official 573:ad23fe03a082 2239
mbed_official 573:ad23fe03a082 2240 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
mbed_official 573:ad23fe03a082 2241 *
mbed_official 573:ad23fe03a082 2242 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
mbed_official 573:ad23fe03a082 2243 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2244 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
mbed_official 573:ad23fe03a082 2245 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
mbed_official 573:ad23fe03a082 2246 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
mbed_official 573:ad23fe03a082 2247 */
mbed_official 573:ad23fe03a082 2248 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2249 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2250
mbed_official 573:ad23fe03a082 2251 /** @brief macro to get the I2C4 clock source.
mbed_official 573:ad23fe03a082 2252 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2253 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
mbed_official 573:ad23fe03a082 2254 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
mbed_official 573:ad23fe03a082 2255 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
mbed_official 573:ad23fe03a082 2256 */
mbed_official 573:ad23fe03a082 2257 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
mbed_official 573:ad23fe03a082 2258
mbed_official 573:ad23fe03a082 2259 /** @brief Macro to configure the USART1 clock (USART1CLK).
mbed_official 573:ad23fe03a082 2260 *
mbed_official 573:ad23fe03a082 2261 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
mbed_official 573:ad23fe03a082 2262 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2263 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
mbed_official 573:ad23fe03a082 2264 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official 573:ad23fe03a082 2265 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official 573:ad23fe03a082 2266 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official 573:ad23fe03a082 2267 */
mbed_official 573:ad23fe03a082 2268 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2269 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2270
mbed_official 573:ad23fe03a082 2271 /** @brief macro to get the USART1 clock source.
mbed_official 573:ad23fe03a082 2272 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2273 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
mbed_official 573:ad23fe03a082 2274 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official 573:ad23fe03a082 2275 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official 573:ad23fe03a082 2276 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official 573:ad23fe03a082 2277 */
mbed_official 573:ad23fe03a082 2278 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
mbed_official 573:ad23fe03a082 2279
mbed_official 573:ad23fe03a082 2280 /** @brief Macro to configure the USART2 clock (USART2CLK).
mbed_official 573:ad23fe03a082 2281 *
mbed_official 573:ad23fe03a082 2282 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
mbed_official 573:ad23fe03a082 2283 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2284 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official 573:ad23fe03a082 2285 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official 573:ad23fe03a082 2286 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official 573:ad23fe03a082 2287 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official 573:ad23fe03a082 2288 */
mbed_official 573:ad23fe03a082 2289 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2290 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2291
mbed_official 573:ad23fe03a082 2292 /** @brief macro to get the USART2 clock source.
mbed_official 573:ad23fe03a082 2293 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2294 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official 573:ad23fe03a082 2295 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official 573:ad23fe03a082 2296 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official 573:ad23fe03a082 2297 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official 573:ad23fe03a082 2298 */
mbed_official 573:ad23fe03a082 2299 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
mbed_official 573:ad23fe03a082 2300
mbed_official 573:ad23fe03a082 2301 /** @brief Macro to configure the USART3 clock (USART3CLK).
mbed_official 573:ad23fe03a082 2302 *
mbed_official 573:ad23fe03a082 2303 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
mbed_official 573:ad23fe03a082 2304 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2305 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official 573:ad23fe03a082 2306 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official 573:ad23fe03a082 2307 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official 573:ad23fe03a082 2308 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official 573:ad23fe03a082 2309 */
mbed_official 573:ad23fe03a082 2310 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2311 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2312
mbed_official 573:ad23fe03a082 2313 /** @brief macro to get the USART3 clock source.
mbed_official 573:ad23fe03a082 2314 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2315 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official 573:ad23fe03a082 2316 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official 573:ad23fe03a082 2317 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official 573:ad23fe03a082 2318 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official 573:ad23fe03a082 2319 */
mbed_official 573:ad23fe03a082 2320 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
mbed_official 573:ad23fe03a082 2321
mbed_official 573:ad23fe03a082 2322 /** @brief Macro to configure the UART4 clock (UART4CLK).
mbed_official 573:ad23fe03a082 2323 *
mbed_official 573:ad23fe03a082 2324 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
mbed_official 573:ad23fe03a082 2325 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2326 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official 573:ad23fe03a082 2327 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official 573:ad23fe03a082 2328 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official 573:ad23fe03a082 2329 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official 573:ad23fe03a082 2330 */
mbed_official 573:ad23fe03a082 2331 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2332 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2333
mbed_official 573:ad23fe03a082 2334 /** @brief macro to get the UART4 clock source.
mbed_official 573:ad23fe03a082 2335 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2336 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official 573:ad23fe03a082 2337 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official 573:ad23fe03a082 2338 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official 573:ad23fe03a082 2339 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official 573:ad23fe03a082 2340 */
mbed_official 573:ad23fe03a082 2341 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
mbed_official 573:ad23fe03a082 2342
mbed_official 573:ad23fe03a082 2343 /** @brief Macro to configure the UART5 clock (UART5CLK).
mbed_official 573:ad23fe03a082 2344 *
mbed_official 573:ad23fe03a082 2345 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
mbed_official 573:ad23fe03a082 2346 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2347 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official 573:ad23fe03a082 2348 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official 573:ad23fe03a082 2349 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official 573:ad23fe03a082 2350 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official 573:ad23fe03a082 2351 */
mbed_official 573:ad23fe03a082 2352 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2353 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2354
mbed_official 573:ad23fe03a082 2355 /** @brief macro to get the UART5 clock source.
mbed_official 573:ad23fe03a082 2356 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2357 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official 573:ad23fe03a082 2358 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official 573:ad23fe03a082 2359 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official 573:ad23fe03a082 2360 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official 573:ad23fe03a082 2361 */
mbed_official 573:ad23fe03a082 2362 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
mbed_official 573:ad23fe03a082 2363
mbed_official 573:ad23fe03a082 2364 /** @brief Macro to configure the USART6 clock (USART6CLK).
mbed_official 573:ad23fe03a082 2365 *
mbed_official 573:ad23fe03a082 2366 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
mbed_official 573:ad23fe03a082 2367 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2368 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
mbed_official 573:ad23fe03a082 2369 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
mbed_official 573:ad23fe03a082 2370 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
mbed_official 573:ad23fe03a082 2371 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
mbed_official 573:ad23fe03a082 2372 */
mbed_official 573:ad23fe03a082 2373 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2374 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2375
mbed_official 573:ad23fe03a082 2376 /** @brief macro to get the USART6 clock source.
mbed_official 573:ad23fe03a082 2377 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2378 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
mbed_official 573:ad23fe03a082 2379 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
mbed_official 573:ad23fe03a082 2380 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
mbed_official 573:ad23fe03a082 2381 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
mbed_official 573:ad23fe03a082 2382 */
mbed_official 573:ad23fe03a082 2383 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
mbed_official 573:ad23fe03a082 2384
mbed_official 573:ad23fe03a082 2385 /** @brief Macro to configure the UART7 clock (UART7CLK).
mbed_official 573:ad23fe03a082 2386 *
mbed_official 573:ad23fe03a082 2387 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
mbed_official 573:ad23fe03a082 2388 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2389 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
mbed_official 573:ad23fe03a082 2390 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
mbed_official 573:ad23fe03a082 2391 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
mbed_official 573:ad23fe03a082 2392 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
mbed_official 573:ad23fe03a082 2393 */
mbed_official 573:ad23fe03a082 2394 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2395 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2396
mbed_official 573:ad23fe03a082 2397 /** @brief macro to get the UART7 clock source.
mbed_official 573:ad23fe03a082 2398 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2399 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
mbed_official 573:ad23fe03a082 2400 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
mbed_official 573:ad23fe03a082 2401 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
mbed_official 573:ad23fe03a082 2402 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
mbed_official 573:ad23fe03a082 2403 */
mbed_official 573:ad23fe03a082 2404 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
mbed_official 573:ad23fe03a082 2405
mbed_official 573:ad23fe03a082 2406 /** @brief Macro to configure the UART8 clock (UART8CLK).
mbed_official 573:ad23fe03a082 2407 *
mbed_official 573:ad23fe03a082 2408 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
mbed_official 573:ad23fe03a082 2409 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2410 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
mbed_official 573:ad23fe03a082 2411 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
mbed_official 573:ad23fe03a082 2412 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
mbed_official 573:ad23fe03a082 2413 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
mbed_official 573:ad23fe03a082 2414 */
mbed_official 573:ad23fe03a082 2415 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2416 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2417
mbed_official 573:ad23fe03a082 2418 /** @brief macro to get the UART8 clock source.
mbed_official 573:ad23fe03a082 2419 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2420 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
mbed_official 573:ad23fe03a082 2421 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
mbed_official 573:ad23fe03a082 2422 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
mbed_official 573:ad23fe03a082 2423 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
mbed_official 573:ad23fe03a082 2424 */
mbed_official 573:ad23fe03a082 2425 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
mbed_official 573:ad23fe03a082 2426
mbed_official 573:ad23fe03a082 2427 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
mbed_official 573:ad23fe03a082 2428 *
mbed_official 573:ad23fe03a082 2429 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
mbed_official 573:ad23fe03a082 2430 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2431 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2432 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2433 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2434 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2435 */
mbed_official 573:ad23fe03a082 2436 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2437 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2438
mbed_official 573:ad23fe03a082 2439 /** @brief macro to get the LPTIM1 clock source.
mbed_official 573:ad23fe03a082 2440 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2441 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2442 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2443 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2444 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
mbed_official 573:ad23fe03a082 2445 */
mbed_official 573:ad23fe03a082 2446 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
mbed_official 573:ad23fe03a082 2447
mbed_official 573:ad23fe03a082 2448 /** @brief Macro to configure the CEC clock (CECCLK).
mbed_official 573:ad23fe03a082 2449 *
mbed_official 573:ad23fe03a082 2450 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
mbed_official 573:ad23fe03a082 2451 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2452 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official 573:ad23fe03a082 2453 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official 573:ad23fe03a082 2454 */
mbed_official 573:ad23fe03a082 2455 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2456 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2457
mbed_official 573:ad23fe03a082 2458 /** @brief macro to get the CEC clock source.
mbed_official 573:ad23fe03a082 2459 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2460 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official 573:ad23fe03a082 2461 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official 573:ad23fe03a082 2462 */
mbed_official 573:ad23fe03a082 2463 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
mbed_official 573:ad23fe03a082 2464
mbed_official 573:ad23fe03a082 2465 /** @brief Macro to configure the CLK48 source (CLK48CLK).
mbed_official 573:ad23fe03a082 2466 *
mbed_official 573:ad23fe03a082 2467 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
mbed_official 573:ad23fe03a082 2468 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2469 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
mbed_official 573:ad23fe03a082 2470 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source
mbed_official 573:ad23fe03a082 2471 */
mbed_official 573:ad23fe03a082 2472 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
mbed_official 573:ad23fe03a082 2473 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
mbed_official 573:ad23fe03a082 2474
mbed_official 573:ad23fe03a082 2475 /** @brief macro to get the CLK48 source.
mbed_official 573:ad23fe03a082 2476 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2477 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
mbed_official 573:ad23fe03a082 2478 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source
mbed_official 573:ad23fe03a082 2479 */
mbed_official 573:ad23fe03a082 2480 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
mbed_official 573:ad23fe03a082 2481
mbed_official 573:ad23fe03a082 2482 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
mbed_official 573:ad23fe03a082 2483 *
mbed_official 573:ad23fe03a082 2484 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
mbed_official 573:ad23fe03a082 2485 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2486 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
mbed_official 573:ad23fe03a082 2487 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
mbed_official 573:ad23fe03a082 2488 */
mbed_official 573:ad23fe03a082 2489 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
mbed_official 573:ad23fe03a082 2490 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
mbed_official 573:ad23fe03a082 2491
mbed_official 573:ad23fe03a082 2492 /** @brief macro to get the SDMMC1 clock source.
mbed_official 573:ad23fe03a082 2493 * @retval The clock source can be one of the following values:
mbed_official 573:ad23fe03a082 2494 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
mbed_official 573:ad23fe03a082 2495 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
mbed_official 573:ad23fe03a082 2496 */
mbed_official 573:ad23fe03a082 2497 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
mbed_official 573:ad23fe03a082 2498
mbed_official 573:ad23fe03a082 2499 /**
mbed_official 573:ad23fe03a082 2500 * @}
mbed_official 573:ad23fe03a082 2501 */
mbed_official 573:ad23fe03a082 2502
mbed_official 573:ad23fe03a082 2503 /* Exported functions --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 2504 /** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official 573:ad23fe03a082 2505 * @{
mbed_official 573:ad23fe03a082 2506 */
mbed_official 573:ad23fe03a082 2507 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 573:ad23fe03a082 2508 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 573:ad23fe03a082 2509 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
mbed_official 573:ad23fe03a082 2510
mbed_official 573:ad23fe03a082 2511 /**
mbed_official 573:ad23fe03a082 2512 * @}
mbed_official 573:ad23fe03a082 2513 */
mbed_official 573:ad23fe03a082 2514 /* Private macros ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 2515 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
mbed_official 573:ad23fe03a082 2516 * @{
mbed_official 573:ad23fe03a082 2517 */
mbed_official 573:ad23fe03a082 2518 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
mbed_official 573:ad23fe03a082 2519 * @{
mbed_official 573:ad23fe03a082 2520 */
mbed_official 573:ad23fe03a082 2521 #if defined(STM32F756xx) || defined(STM32F746xx)
mbed_official 573:ad23fe03a082 2522 #define IS_RCC_PERIPHCLOCK(SELECTION) \
mbed_official 573:ad23fe03a082 2523 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
mbed_official 573:ad23fe03a082 2524 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
mbed_official 573:ad23fe03a082 2525 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
mbed_official 573:ad23fe03a082 2526 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
mbed_official 573:ad23fe03a082 2527 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
mbed_official 573:ad23fe03a082 2528 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
mbed_official 573:ad23fe03a082 2529 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
mbed_official 573:ad23fe03a082 2530 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
mbed_official 573:ad23fe03a082 2531 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
mbed_official 573:ad23fe03a082 2532 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
mbed_official 573:ad23fe03a082 2533 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
mbed_official 573:ad23fe03a082 2534 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
mbed_official 573:ad23fe03a082 2535 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
mbed_official 573:ad23fe03a082 2536 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
mbed_official 573:ad23fe03a082 2537 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
mbed_official 573:ad23fe03a082 2538 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
mbed_official 573:ad23fe03a082 2539 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
mbed_official 573:ad23fe03a082 2540 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
mbed_official 573:ad23fe03a082 2541 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
mbed_official 573:ad23fe03a082 2542 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
mbed_official 573:ad23fe03a082 2543 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
mbed_official 573:ad23fe03a082 2544 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
mbed_official 573:ad23fe03a082 2545 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
mbed_official 573:ad23fe03a082 2546 #elif defined(STM32F745xx)
mbed_official 573:ad23fe03a082 2547 #define IS_RCC_PERIPHCLOCK(SELECTION) \
mbed_official 573:ad23fe03a082 2548 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
mbed_official 573:ad23fe03a082 2549 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
mbed_official 573:ad23fe03a082 2550 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
mbed_official 573:ad23fe03a082 2551 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
mbed_official 573:ad23fe03a082 2552 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
mbed_official 573:ad23fe03a082 2553 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
mbed_official 573:ad23fe03a082 2554 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
mbed_official 573:ad23fe03a082 2555 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
mbed_official 573:ad23fe03a082 2556 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
mbed_official 573:ad23fe03a082 2557 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
mbed_official 573:ad23fe03a082 2558 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
mbed_official 573:ad23fe03a082 2559 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
mbed_official 573:ad23fe03a082 2560 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
mbed_official 573:ad23fe03a082 2561 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
mbed_official 573:ad23fe03a082 2562 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
mbed_official 573:ad23fe03a082 2563 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
mbed_official 573:ad23fe03a082 2564 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
mbed_official 573:ad23fe03a082 2565 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
mbed_official 573:ad23fe03a082 2566 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
mbed_official 573:ad23fe03a082 2567 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
mbed_official 573:ad23fe03a082 2568 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
mbed_official 573:ad23fe03a082 2569 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
mbed_official 573:ad23fe03a082 2570 #endif /* STM32F756xx || STM32F746xx */
mbed_official 573:ad23fe03a082 2571 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 573:ad23fe03a082 2572 #define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
mbed_official 573:ad23fe03a082 2573 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 573:ad23fe03a082 2574 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official 573:ad23fe03a082 2575
mbed_official 573:ad23fe03a082 2576 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 573:ad23fe03a082 2577 #define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
mbed_official 573:ad23fe03a082 2578 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 573:ad23fe03a082 2579 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official 573:ad23fe03a082 2580
mbed_official 573:ad23fe03a082 2581 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 573:ad23fe03a082 2582
mbed_official 573:ad23fe03a082 2583 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 573:ad23fe03a082 2584
mbed_official 573:ad23fe03a082 2585 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
mbed_official 573:ad23fe03a082 2586 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
mbed_official 573:ad23fe03a082 2587 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
mbed_official 573:ad23fe03a082 2588 ((VALUE) == RCC_PLLSAIDIVR_16))
mbed_official 573:ad23fe03a082 2589 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
mbed_official 573:ad23fe03a082 2590 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official 573:ad23fe03a082 2591 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
mbed_official 573:ad23fe03a082 2592 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
mbed_official 573:ad23fe03a082 2593 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
mbed_official 573:ad23fe03a082 2594 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
mbed_official 573:ad23fe03a082 2595 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
mbed_official 573:ad23fe03a082 2596 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
mbed_official 573:ad23fe03a082 2597
mbed_official 573:ad23fe03a082 2598 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2599 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
mbed_official 573:ad23fe03a082 2600
mbed_official 573:ad23fe03a082 2601 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
mbed_official 573:ad23fe03a082 2602 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official 573:ad23fe03a082 2603 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2604 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
mbed_official 573:ad23fe03a082 2605 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2606 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2607 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2608
mbed_official 573:ad23fe03a082 2609 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2610 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2611 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2612 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2613 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2614 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2615 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2616 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2617 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2618 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2619
mbed_official 573:ad23fe03a082 2620 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2621 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2622 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2623 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2624 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2625
mbed_official 573:ad23fe03a082 2626 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2627 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2628 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2629 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2630 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2631
mbed_official 573:ad23fe03a082 2632 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2633 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
mbed_official 573:ad23fe03a082 2634 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2635 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2636 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2637
mbed_official 573:ad23fe03a082 2638 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2639 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2640 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2641 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2642 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2643
mbed_official 573:ad23fe03a082 2644 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2645 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2646 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
mbed_official 573:ad23fe03a082 2647 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
mbed_official 573:ad23fe03a082 2648 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2649 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2650 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2651 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
mbed_official 573:ad23fe03a082 2652 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2653 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2654 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2655 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
mbed_official 573:ad23fe03a082 2656 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2657
mbed_official 573:ad23fe03a082 2658 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2659 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2660 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
mbed_official 573:ad23fe03a082 2661 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2662 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2663 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
mbed_official 573:ad23fe03a082 2664 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
mbed_official 573:ad23fe03a082 2665 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
mbed_official 573:ad23fe03a082 2666 #define IS_RCC_LPTIM1CLK(SOURCE) \
mbed_official 573:ad23fe03a082 2667 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
mbed_official 573:ad23fe03a082 2668 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
mbed_official 573:ad23fe03a082 2669 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
mbed_official 573:ad23fe03a082 2670 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
mbed_official 573:ad23fe03a082 2671 #define IS_RCC_CLK48SOURCE(SOURCE) \
mbed_official 573:ad23fe03a082 2672 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
mbed_official 573:ad23fe03a082 2673 ((SOURCE) == RCC_CLK48SOURCE_PLL))
mbed_official 573:ad23fe03a082 2674 #define IS_RCC_TIMPRES(VALUE) \
mbed_official 573:ad23fe03a082 2675 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
mbed_official 573:ad23fe03a082 2676 ((VALUE) == RCC_TIMPRES_ACTIVATED))
mbed_official 573:ad23fe03a082 2677 /**
mbed_official 573:ad23fe03a082 2678 * @}
mbed_official 573:ad23fe03a082 2679 */
mbed_official 573:ad23fe03a082 2680
mbed_official 573:ad23fe03a082 2681 /**
mbed_official 573:ad23fe03a082 2682 * @}
mbed_official 573:ad23fe03a082 2683 */
mbed_official 573:ad23fe03a082 2684
mbed_official 573:ad23fe03a082 2685 /**
mbed_official 573:ad23fe03a082 2686 * @}
mbed_official 573:ad23fe03a082 2687 */
mbed_official 573:ad23fe03a082 2688
mbed_official 573:ad23fe03a082 2689 /**
mbed_official 573:ad23fe03a082 2690 * @}
mbed_official 573:ad23fe03a082 2691 */
mbed_official 573:ad23fe03a082 2692 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 2693 }
mbed_official 573:ad23fe03a082 2694 #endif
mbed_official 573:ad23fe03a082 2695
mbed_official 573:ad23fe03a082 2696 #endif /* __STM32F7xx_HAL_RCC_EX_H */
mbed_official 573:ad23fe03a082 2697
mbed_official 573:ad23fe03a082 2698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/