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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h@610:813dcc80987e, 2015-08-14 (annotated)

Committer:
mbed_official
Date:
Fri Aug 14 13:15:17 2015 +0100
Revision:
610:813dcc80987e
Parent:
573:ad23fe03a082 
Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599



Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/



DISCO_F746NG - Improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f746xx.h
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 610:813dcc80987e 5 * @version V1.0.1
mbed_official 610:813dcc80987e 6 * @date 25-June-2015
mbed_official 573:ad23fe03a082 7 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
mbed_official 573:ad23fe03a082 8 *
mbed_official 573:ad23fe03a082 9 * This file contains:
mbed_official 573:ad23fe03a082 10 * - Data structures and the address mapping for all peripherals
mbed_official 573:ad23fe03a082 11 * - Peripheral's registers declarations and bits definition
mbed_official 573:ad23fe03a082 12 * - Macros to access peripheral’s registers hardware
mbed_official 573:ad23fe03a082 13 *
mbed_official 573:ad23fe03a082 14 ******************************************************************************
mbed_official 573:ad23fe03a082 15 * @attention
mbed_official 573:ad23fe03a082 16 *
mbed_official 573:ad23fe03a082 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 18 *
mbed_official 573:ad23fe03a082 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 20 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 22 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 25 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 27 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 28 * without specific prior written permission.
mbed_official 573:ad23fe03a082 29 *
mbed_official 573:ad23fe03a082 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 40 *
mbed_official 573:ad23fe03a082 41 ******************************************************************************
mbed_official 573:ad23fe03a082 42 */
mbed_official 573:ad23fe03a082 43
mbed_official 573:ad23fe03a082 44 /** @addtogroup CMSIS_Device
mbed_official 573:ad23fe03a082 45 * @{
mbed_official 573:ad23fe03a082 46 */
mbed_official 573:ad23fe03a082 47
mbed_official 573:ad23fe03a082 48 /** @addtogroup stm32f746xx
mbed_official 573:ad23fe03a082 49 * @{
mbed_official 573:ad23fe03a082 50 */
mbed_official 573:ad23fe03a082 51
mbed_official 573:ad23fe03a082 52 #ifndef __STM32F746xx_H
mbed_official 573:ad23fe03a082 53 #define __STM32F746xx_H
mbed_official 573:ad23fe03a082 54
mbed_official 573:ad23fe03a082 55 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 56 extern "C" {
mbed_official 573:ad23fe03a082 57 #endif /* __cplusplus */
mbed_official 573:ad23fe03a082 58
mbed_official 573:ad23fe03a082 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 573:ad23fe03a082 60 * @{
mbed_official 573:ad23fe03a082 61 */
mbed_official 573:ad23fe03a082 62
mbed_official 573:ad23fe03a082 63 /**
mbed_official 573:ad23fe03a082 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
mbed_official 573:ad23fe03a082 65 * in @ref Library_configuration_section
mbed_official 573:ad23fe03a082 66 */
mbed_official 573:ad23fe03a082 67 typedef enum IRQn
mbed_official 573:ad23fe03a082 68 {
mbed_official 573:ad23fe03a082 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
mbed_official 573:ad23fe03a082 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 573:ad23fe03a082 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
mbed_official 573:ad23fe03a082 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
mbed_official 573:ad23fe03a082 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
mbed_official 573:ad23fe03a082 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
mbed_official 573:ad23fe03a082 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
mbed_official 573:ad23fe03a082 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
mbed_official 573:ad23fe03a082 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
mbed_official 573:ad23fe03a082 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 573:ad23fe03a082 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 573:ad23fe03a082 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 573:ad23fe03a082 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 573:ad23fe03a082 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 573:ad23fe03a082 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 573:ad23fe03a082 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 573:ad23fe03a082 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 573:ad23fe03a082 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 573:ad23fe03a082 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 573:ad23fe03a082 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 573:ad23fe03a082 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 573:ad23fe03a082 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 573:ad23fe03a082 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 573:ad23fe03a082 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 573:ad23fe03a082 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 573:ad23fe03a082 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 573:ad23fe03a082 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 573:ad23fe03a082 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 573:ad23fe03a082 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 573:ad23fe03a082 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 573:ad23fe03a082 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 573:ad23fe03a082 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 573:ad23fe03a082 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 573:ad23fe03a082 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 573:ad23fe03a082 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 573:ad23fe03a082 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 573:ad23fe03a082 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 573:ad23fe03a082 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 573:ad23fe03a082 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 573:ad23fe03a082 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 573:ad23fe03a082 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 573:ad23fe03a082 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 573:ad23fe03a082 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 573:ad23fe03a082 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 573:ad23fe03a082 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 573:ad23fe03a082 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 573:ad23fe03a082 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 573:ad23fe03a082 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 573:ad23fe03a082 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 573:ad23fe03a082 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 573:ad23fe03a082 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 573:ad23fe03a082 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 573:ad23fe03a082 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 573:ad23fe03a082 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 573:ad23fe03a082 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 573:ad23fe03a082 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 573:ad23fe03a082 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 573:ad23fe03a082 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 573:ad23fe03a082 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
mbed_official 573:ad23fe03a082 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
mbed_official 573:ad23fe03a082 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 573:ad23fe03a082 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 573:ad23fe03a082 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 573:ad23fe03a082 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 573:ad23fe03a082 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 573:ad23fe03a082 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 573:ad23fe03a082 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 573:ad23fe03a082 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 573:ad23fe03a082 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 573:ad23fe03a082 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 573:ad23fe03a082 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 573:ad23fe03a082 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
mbed_official 573:ad23fe03a082 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
mbed_official 573:ad23fe03a082 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 573:ad23fe03a082 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 573:ad23fe03a082 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 573:ad23fe03a082 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 573:ad23fe03a082 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 573:ad23fe03a082 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 573:ad23fe03a082 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 573:ad23fe03a082 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 573:ad23fe03a082 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 573:ad23fe03a082 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 573:ad23fe03a082 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 573:ad23fe03a082 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 573:ad23fe03a082 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 573:ad23fe03a082 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 573:ad23fe03a082 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 573:ad23fe03a082 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
mbed_official 573:ad23fe03a082 158 RNG_IRQn = 80, /*!< RNG global interrupt */
mbed_official 573:ad23fe03a082 159 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 573:ad23fe03a082 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
mbed_official 573:ad23fe03a082 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
mbed_official 573:ad23fe03a082 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 573:ad23fe03a082 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
mbed_official 573:ad23fe03a082 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
mbed_official 573:ad23fe03a082 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
mbed_official 573:ad23fe03a082 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
mbed_official 573:ad23fe03a082 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
mbed_official 573:ad23fe03a082 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
mbed_official 573:ad23fe03a082 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
mbed_official 573:ad23fe03a082 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
mbed_official 573:ad23fe03a082 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
mbed_official 573:ad23fe03a082 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
mbed_official 573:ad23fe03a082 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
mbed_official 573:ad23fe03a082 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
mbed_official 573:ad23fe03a082 175 SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */
mbed_official 573:ad23fe03a082 176 } IRQn_Type;
mbed_official 573:ad23fe03a082 177
mbed_official 573:ad23fe03a082 178 /**
mbed_official 573:ad23fe03a082 179 * @}
mbed_official 573:ad23fe03a082 180 */
mbed_official 573:ad23fe03a082 181
mbed_official 573:ad23fe03a082 182 /**
mbed_official 573:ad23fe03a082 183 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
mbed_official 573:ad23fe03a082 184 */
mbed_official 573:ad23fe03a082 185 #define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
mbed_official 573:ad23fe03a082 186 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
mbed_official 573:ad23fe03a082 187 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
mbed_official 573:ad23fe03a082 188 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 573:ad23fe03a082 189 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 573:ad23fe03a082 190 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
mbed_official 573:ad23fe03a082 191 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
mbed_official 573:ad23fe03a082 192 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
mbed_official 573:ad23fe03a082 193
mbed_official 573:ad23fe03a082 194
mbed_official 573:ad23fe03a082 195 #include "system_stm32f7xx.h"
mbed_official 573:ad23fe03a082 196 #include <stdint.h>
mbed_official 573:ad23fe03a082 197
mbed_official 573:ad23fe03a082 198 /** @addtogroup Peripheral_registers_structures
mbed_official 573:ad23fe03a082 199 * @{
mbed_official 573:ad23fe03a082 200 */
mbed_official 573:ad23fe03a082 201
mbed_official 573:ad23fe03a082 202 /**
mbed_official 573:ad23fe03a082 203 * @brief Analog to Digital Converter
mbed_official 573:ad23fe03a082 204 */
mbed_official 573:ad23fe03a082 205
mbed_official 573:ad23fe03a082 206 typedef struct
mbed_official 573:ad23fe03a082 207 {
mbed_official 573:ad23fe03a082 208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 573:ad23fe03a082 223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 573:ad23fe03a082 228 } ADC_TypeDef;
mbed_official 573:ad23fe03a082 229
mbed_official 573:ad23fe03a082 230 typedef struct
mbed_official 573:ad23fe03a082 231 {
mbed_official 573:ad23fe03a082 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 573:ad23fe03a082 233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 573:ad23fe03a082 234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 573:ad23fe03a082 235 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 573:ad23fe03a082 236 } ADC_Common_TypeDef;
mbed_official 573:ad23fe03a082 237
mbed_official 573:ad23fe03a082 238
mbed_official 573:ad23fe03a082 239 /**
mbed_official 573:ad23fe03a082 240 * @brief Controller Area Network TxMailBox
mbed_official 573:ad23fe03a082 241 */
mbed_official 573:ad23fe03a082 242
mbed_official 573:ad23fe03a082 243 typedef struct
mbed_official 573:ad23fe03a082 244 {
mbed_official 573:ad23fe03a082 245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 573:ad23fe03a082 246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 573:ad23fe03a082 247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 573:ad23fe03a082 248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 573:ad23fe03a082 249 } CAN_TxMailBox_TypeDef;
mbed_official 573:ad23fe03a082 250
mbed_official 573:ad23fe03a082 251 /**
mbed_official 573:ad23fe03a082 252 * @brief Controller Area Network FIFOMailBox
mbed_official 573:ad23fe03a082 253 */
mbed_official 573:ad23fe03a082 254
mbed_official 573:ad23fe03a082 255 typedef struct
mbed_official 573:ad23fe03a082 256 {
mbed_official 573:ad23fe03a082 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 573:ad23fe03a082 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 573:ad23fe03a082 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 573:ad23fe03a082 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 573:ad23fe03a082 261 } CAN_FIFOMailBox_TypeDef;
mbed_official 573:ad23fe03a082 262
mbed_official 573:ad23fe03a082 263 /**
mbed_official 573:ad23fe03a082 264 * @brief Controller Area Network FilterRegister
mbed_official 573:ad23fe03a082 265 */
mbed_official 573:ad23fe03a082 266
mbed_official 573:ad23fe03a082 267 typedef struct
mbed_official 573:ad23fe03a082 268 {
mbed_official 573:ad23fe03a082 269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 573:ad23fe03a082 270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 573:ad23fe03a082 271 } CAN_FilterRegister_TypeDef;
mbed_official 573:ad23fe03a082 272
mbed_official 573:ad23fe03a082 273 /**
mbed_official 573:ad23fe03a082 274 * @brief Controller Area Network
mbed_official 573:ad23fe03a082 275 */
mbed_official 573:ad23fe03a082 276
mbed_official 573:ad23fe03a082 277 typedef struct
mbed_official 573:ad23fe03a082 278 {
mbed_official 573:ad23fe03a082 279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 573:ad23fe03a082 288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 573:ad23fe03a082 289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 573:ad23fe03a082 290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 573:ad23fe03a082 291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 573:ad23fe03a082 292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 573:ad23fe03a082 293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 573:ad23fe03a082 294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 573:ad23fe03a082 295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 573:ad23fe03a082 296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 573:ad23fe03a082 297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 573:ad23fe03a082 298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 573:ad23fe03a082 299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 573:ad23fe03a082 300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 573:ad23fe03a082 301 } CAN_TypeDef;
mbed_official 573:ad23fe03a082 302
mbed_official 573:ad23fe03a082 303 /**
mbed_official 573:ad23fe03a082 304 * @brief HDMI-CEC
mbed_official 573:ad23fe03a082 305 */
mbed_official 573:ad23fe03a082 306
mbed_official 573:ad23fe03a082 307 typedef struct
mbed_official 573:ad23fe03a082 308 {
mbed_official 573:ad23fe03a082 309 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 573:ad23fe03a082 310 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 573:ad23fe03a082 311 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 573:ad23fe03a082 312 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 573:ad23fe03a082 313 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 573:ad23fe03a082 314 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 573:ad23fe03a082 315 }CEC_TypeDef;
mbed_official 573:ad23fe03a082 316
mbed_official 573:ad23fe03a082 317
mbed_official 573:ad23fe03a082 318 /**
mbed_official 573:ad23fe03a082 319 * @brief CRC calculation unit
mbed_official 573:ad23fe03a082 320 */
mbed_official 573:ad23fe03a082 321
mbed_official 573:ad23fe03a082 322 typedef struct
mbed_official 573:ad23fe03a082 323 {
mbed_official 573:ad23fe03a082 324 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 610:813dcc80987e 325 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 610:813dcc80987e 326 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 610:813dcc80987e 327 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 573:ad23fe03a082 328 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 610:813dcc80987e 329 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 573:ad23fe03a082 330 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 331 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 332 } CRC_TypeDef;
mbed_official 573:ad23fe03a082 333
mbed_official 573:ad23fe03a082 334 /**
mbed_official 573:ad23fe03a082 335 * @brief Digital to Analog Converter
mbed_official 573:ad23fe03a082 336 */
mbed_official 573:ad23fe03a082 337
mbed_official 573:ad23fe03a082 338 typedef struct
mbed_official 573:ad23fe03a082 339 {
mbed_official 573:ad23fe03a082 340 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 341 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 342 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 343 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 344 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 345 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 346 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 347 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 348 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 349 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 350 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 351 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 352 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 353 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 354 } DAC_TypeDef;
mbed_official 573:ad23fe03a082 355
mbed_official 573:ad23fe03a082 356 /**
mbed_official 573:ad23fe03a082 357 * @brief Debug MCU
mbed_official 573:ad23fe03a082 358 */
mbed_official 573:ad23fe03a082 359
mbed_official 573:ad23fe03a082 360 typedef struct
mbed_official 573:ad23fe03a082 361 {
mbed_official 573:ad23fe03a082 362 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 363 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 364 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 365 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 366 }DBGMCU_TypeDef;
mbed_official 573:ad23fe03a082 367
mbed_official 573:ad23fe03a082 368 /**
mbed_official 573:ad23fe03a082 369 * @brief DCMI
mbed_official 573:ad23fe03a082 370 */
mbed_official 573:ad23fe03a082 371
mbed_official 573:ad23fe03a082 372 typedef struct
mbed_official 573:ad23fe03a082 373 {
mbed_official 573:ad23fe03a082 374 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 375 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 376 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 377 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 378 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 379 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 380 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 381 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 382 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 383 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 384 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 385 } DCMI_TypeDef;
mbed_official 573:ad23fe03a082 386
mbed_official 573:ad23fe03a082 387 /**
mbed_official 573:ad23fe03a082 388 * @brief DMA Controller
mbed_official 573:ad23fe03a082 389 */
mbed_official 573:ad23fe03a082 390
mbed_official 573:ad23fe03a082 391 typedef struct
mbed_official 573:ad23fe03a082 392 {
mbed_official 573:ad23fe03a082 393 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 573:ad23fe03a082 394 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 573:ad23fe03a082 395 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 573:ad23fe03a082 396 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 573:ad23fe03a082 397 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 573:ad23fe03a082 398 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 573:ad23fe03a082 399 } DMA_Stream_TypeDef;
mbed_official 573:ad23fe03a082 400
mbed_official 573:ad23fe03a082 401 typedef struct
mbed_official 573:ad23fe03a082 402 {
mbed_official 573:ad23fe03a082 403 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 404 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 405 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 406 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 407 } DMA_TypeDef;
mbed_official 573:ad23fe03a082 408
mbed_official 573:ad23fe03a082 409
mbed_official 573:ad23fe03a082 410 /**
mbed_official 573:ad23fe03a082 411 * @brief DMA2D Controller
mbed_official 573:ad23fe03a082 412 */
mbed_official 573:ad23fe03a082 413
mbed_official 573:ad23fe03a082 414 typedef struct
mbed_official 573:ad23fe03a082 415 {
mbed_official 573:ad23fe03a082 416 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 417 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 418 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 419 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 420 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 421 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 422 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 423 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 424 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 425 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 426 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 427 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 428 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 429 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 430 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 431 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 432 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 433 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 434 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 435 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
mbed_official 573:ad23fe03a082 436 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
mbed_official 573:ad23fe03a082 437 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
mbed_official 573:ad23fe03a082 438 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
mbed_official 573:ad23fe03a082 439 } DMA2D_TypeDef;
mbed_official 573:ad23fe03a082 440
mbed_official 573:ad23fe03a082 441
mbed_official 573:ad23fe03a082 442 /**
mbed_official 573:ad23fe03a082 443 * @brief Ethernet MAC
mbed_official 573:ad23fe03a082 444 */
mbed_official 573:ad23fe03a082 445
mbed_official 573:ad23fe03a082 446 typedef struct
mbed_official 573:ad23fe03a082 447 {
mbed_official 573:ad23fe03a082 448 __IO uint32_t MACCR;
mbed_official 573:ad23fe03a082 449 __IO uint32_t MACFFR;
mbed_official 573:ad23fe03a082 450 __IO uint32_t MACHTHR;
mbed_official 573:ad23fe03a082 451 __IO uint32_t MACHTLR;
mbed_official 573:ad23fe03a082 452 __IO uint32_t MACMIIAR;
mbed_official 573:ad23fe03a082 453 __IO uint32_t MACMIIDR;
mbed_official 573:ad23fe03a082 454 __IO uint32_t MACFCR;
mbed_official 573:ad23fe03a082 455 __IO uint32_t MACVLANTR; /* 8 */
mbed_official 573:ad23fe03a082 456 uint32_t RESERVED0[2];
mbed_official 573:ad23fe03a082 457 __IO uint32_t MACRWUFFR; /* 11 */
mbed_official 573:ad23fe03a082 458 __IO uint32_t MACPMTCSR;
mbed_official 573:ad23fe03a082 459 uint32_t RESERVED1[2];
mbed_official 573:ad23fe03a082 460 __IO uint32_t MACSR; /* 15 */
mbed_official 573:ad23fe03a082 461 __IO uint32_t MACIMR;
mbed_official 573:ad23fe03a082 462 __IO uint32_t MACA0HR;
mbed_official 573:ad23fe03a082 463 __IO uint32_t MACA0LR;
mbed_official 573:ad23fe03a082 464 __IO uint32_t MACA1HR;
mbed_official 573:ad23fe03a082 465 __IO uint32_t MACA1LR;
mbed_official 573:ad23fe03a082 466 __IO uint32_t MACA2HR;
mbed_official 573:ad23fe03a082 467 __IO uint32_t MACA2LR;
mbed_official 573:ad23fe03a082 468 __IO uint32_t MACA3HR;
mbed_official 573:ad23fe03a082 469 __IO uint32_t MACA3LR; /* 24 */
mbed_official 573:ad23fe03a082 470 uint32_t RESERVED2[40];
mbed_official 573:ad23fe03a082 471 __IO uint32_t MMCCR; /* 65 */
mbed_official 573:ad23fe03a082 472 __IO uint32_t MMCRIR;
mbed_official 573:ad23fe03a082 473 __IO uint32_t MMCTIR;
mbed_official 573:ad23fe03a082 474 __IO uint32_t MMCRIMR;
mbed_official 573:ad23fe03a082 475 __IO uint32_t MMCTIMR; /* 69 */
mbed_official 573:ad23fe03a082 476 uint32_t RESERVED3[14];
mbed_official 573:ad23fe03a082 477 __IO uint32_t MMCTGFSCCR; /* 84 */
mbed_official 573:ad23fe03a082 478 __IO uint32_t MMCTGFMSCCR;
mbed_official 573:ad23fe03a082 479 uint32_t RESERVED4[5];
mbed_official 573:ad23fe03a082 480 __IO uint32_t MMCTGFCR;
mbed_official 573:ad23fe03a082 481 uint32_t RESERVED5[10];
mbed_official 573:ad23fe03a082 482 __IO uint32_t MMCRFCECR;
mbed_official 573:ad23fe03a082 483 __IO uint32_t MMCRFAECR;
mbed_official 573:ad23fe03a082 484 uint32_t RESERVED6[10];
mbed_official 573:ad23fe03a082 485 __IO uint32_t MMCRGUFCR;
mbed_official 573:ad23fe03a082 486 uint32_t RESERVED7[334];
mbed_official 573:ad23fe03a082 487 __IO uint32_t PTPTSCR;
mbed_official 573:ad23fe03a082 488 __IO uint32_t PTPSSIR;
mbed_official 573:ad23fe03a082 489 __IO uint32_t PTPTSHR;
mbed_official 573:ad23fe03a082 490 __IO uint32_t PTPTSLR;
mbed_official 573:ad23fe03a082 491 __IO uint32_t PTPTSHUR;
mbed_official 573:ad23fe03a082 492 __IO uint32_t PTPTSLUR;
mbed_official 573:ad23fe03a082 493 __IO uint32_t PTPTSAR;
mbed_official 573:ad23fe03a082 494 __IO uint32_t PTPTTHR;
mbed_official 573:ad23fe03a082 495 __IO uint32_t PTPTTLR;
mbed_official 573:ad23fe03a082 496 __IO uint32_t RESERVED8;
mbed_official 573:ad23fe03a082 497 __IO uint32_t PTPTSSR;
mbed_official 573:ad23fe03a082 498 uint32_t RESERVED9[565];
mbed_official 573:ad23fe03a082 499 __IO uint32_t DMABMR;
mbed_official 573:ad23fe03a082 500 __IO uint32_t DMATPDR;
mbed_official 573:ad23fe03a082 501 __IO uint32_t DMARPDR;
mbed_official 573:ad23fe03a082 502 __IO uint32_t DMARDLAR;
mbed_official 573:ad23fe03a082 503 __IO uint32_t DMATDLAR;
mbed_official 573:ad23fe03a082 504 __IO uint32_t DMASR;
mbed_official 573:ad23fe03a082 505 __IO uint32_t DMAOMR;
mbed_official 573:ad23fe03a082 506 __IO uint32_t DMAIER;
mbed_official 573:ad23fe03a082 507 __IO uint32_t DMAMFBOCR;
mbed_official 573:ad23fe03a082 508 __IO uint32_t DMARSWTR;
mbed_official 573:ad23fe03a082 509 uint32_t RESERVED10[8];
mbed_official 573:ad23fe03a082 510 __IO uint32_t DMACHTDR;
mbed_official 573:ad23fe03a082 511 __IO uint32_t DMACHRDR;
mbed_official 573:ad23fe03a082 512 __IO uint32_t DMACHTBAR;
mbed_official 573:ad23fe03a082 513 __IO uint32_t DMACHRBAR;
mbed_official 573:ad23fe03a082 514 } ETH_TypeDef;
mbed_official 573:ad23fe03a082 515
mbed_official 573:ad23fe03a082 516 /**
mbed_official 573:ad23fe03a082 517 * @brief External Interrupt/Event Controller
mbed_official 573:ad23fe03a082 518 */
mbed_official 573:ad23fe03a082 519
mbed_official 573:ad23fe03a082 520 typedef struct
mbed_official 573:ad23fe03a082 521 {
mbed_official 573:ad23fe03a082 522 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 523 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 524 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 525 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 526 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 527 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 528 } EXTI_TypeDef;
mbed_official 573:ad23fe03a082 529
mbed_official 573:ad23fe03a082 530 /**
mbed_official 573:ad23fe03a082 531 * @brief FLASH Registers
mbed_official 573:ad23fe03a082 532 */
mbed_official 573:ad23fe03a082 533
mbed_official 573:ad23fe03a082 534 typedef struct
mbed_official 573:ad23fe03a082 535 {
mbed_official 573:ad23fe03a082 536 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 537 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 538 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 539 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 540 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 541 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 573:ad23fe03a082 542 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
mbed_official 573:ad23fe03a082 543 } FLASH_TypeDef;
mbed_official 573:ad23fe03a082 544
mbed_official 573:ad23fe03a082 545
mbed_official 573:ad23fe03a082 546
mbed_official 573:ad23fe03a082 547 /**
mbed_official 573:ad23fe03a082 548 * @brief Flexible Memory Controller
mbed_official 573:ad23fe03a082 549 */
mbed_official 573:ad23fe03a082 550
mbed_official 573:ad23fe03a082 551 typedef struct
mbed_official 573:ad23fe03a082 552 {
mbed_official 573:ad23fe03a082 553 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 573:ad23fe03a082 554 } FMC_Bank1_TypeDef;
mbed_official 573:ad23fe03a082 555
mbed_official 573:ad23fe03a082 556 /**
mbed_official 573:ad23fe03a082 557 * @brief Flexible Memory Controller Bank1E
mbed_official 573:ad23fe03a082 558 */
mbed_official 573:ad23fe03a082 559
mbed_official 573:ad23fe03a082 560 typedef struct
mbed_official 573:ad23fe03a082 561 {
mbed_official 573:ad23fe03a082 562 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 573:ad23fe03a082 563 } FMC_Bank1E_TypeDef;
mbed_official 573:ad23fe03a082 564
mbed_official 573:ad23fe03a082 565 /**
mbed_official 573:ad23fe03a082 566 * @brief Flexible Memory Controller Bank3
mbed_official 573:ad23fe03a082 567 */
mbed_official 573:ad23fe03a082 568
mbed_official 573:ad23fe03a082 569 typedef struct
mbed_official 573:ad23fe03a082 570 {
mbed_official 573:ad23fe03a082 571 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
mbed_official 573:ad23fe03a082 572 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
mbed_official 573:ad23fe03a082 573 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
mbed_official 573:ad23fe03a082 574 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
mbed_official 573:ad23fe03a082 575 uint32_t RESERVED0; /*!< Reserved, 0x90 */
mbed_official 573:ad23fe03a082 576 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
mbed_official 573:ad23fe03a082 577 } FMC_Bank3_TypeDef;
mbed_official 573:ad23fe03a082 578
mbed_official 573:ad23fe03a082 579 /**
mbed_official 573:ad23fe03a082 580 * @brief Flexible Memory Controller Bank5_6
mbed_official 573:ad23fe03a082 581 */
mbed_official 573:ad23fe03a082 582
mbed_official 573:ad23fe03a082 583 typedef struct
mbed_official 573:ad23fe03a082 584 {
mbed_official 573:ad23fe03a082 585 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
mbed_official 573:ad23fe03a082 586 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
mbed_official 573:ad23fe03a082 587 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
mbed_official 573:ad23fe03a082 588 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
mbed_official 573:ad23fe03a082 589 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
mbed_official 573:ad23fe03a082 590 } FMC_Bank5_6_TypeDef;
mbed_official 573:ad23fe03a082 591
mbed_official 573:ad23fe03a082 592
mbed_official 573:ad23fe03a082 593 /**
mbed_official 573:ad23fe03a082 594 * @brief General Purpose I/O
mbed_official 573:ad23fe03a082 595 */
mbed_official 573:ad23fe03a082 596
mbed_official 573:ad23fe03a082 597 typedef struct
mbed_official 573:ad23fe03a082 598 {
mbed_official 573:ad23fe03a082 599 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 600 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 601 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 602 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 603 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 604 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 605 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 606 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 607 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 573:ad23fe03a082 608 } GPIO_TypeDef;
mbed_official 573:ad23fe03a082 609
mbed_official 573:ad23fe03a082 610 /**
mbed_official 573:ad23fe03a082 611 * @brief System configuration controller
mbed_official 573:ad23fe03a082 612 */
mbed_official 573:ad23fe03a082 613
mbed_official 573:ad23fe03a082 614 typedef struct
mbed_official 573:ad23fe03a082 615 {
mbed_official 573:ad23fe03a082 616 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 617 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 618 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 573:ad23fe03a082 619 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 573:ad23fe03a082 620 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 621 } SYSCFG_TypeDef;
mbed_official 573:ad23fe03a082 622
mbed_official 573:ad23fe03a082 623 /**
mbed_official 573:ad23fe03a082 624 * @brief Inter-integrated Circuit Interface
mbed_official 573:ad23fe03a082 625 */
mbed_official 573:ad23fe03a082 626
mbed_official 573:ad23fe03a082 627 typedef struct
mbed_official 573:ad23fe03a082 628 {
mbed_official 573:ad23fe03a082 629 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 630 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 631 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 632 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 633 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 634 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 635 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 636 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 637 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 638 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 639 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 640 } I2C_TypeDef;
mbed_official 573:ad23fe03a082 641
mbed_official 573:ad23fe03a082 642 /**
mbed_official 573:ad23fe03a082 643 * @brief Independent WATCHDOG
mbed_official 573:ad23fe03a082 644 */
mbed_official 573:ad23fe03a082 645
mbed_official 573:ad23fe03a082 646 typedef struct
mbed_official 573:ad23fe03a082 647 {
mbed_official 573:ad23fe03a082 648 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 649 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 650 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 651 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 652 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 653 } IWDG_TypeDef;
mbed_official 573:ad23fe03a082 654
mbed_official 573:ad23fe03a082 655
mbed_official 573:ad23fe03a082 656 /**
mbed_official 573:ad23fe03a082 657 * @brief LCD-TFT Display Controller
mbed_official 573:ad23fe03a082 658 */
mbed_official 573:ad23fe03a082 659
mbed_official 573:ad23fe03a082 660 typedef struct
mbed_official 573:ad23fe03a082 661 {
mbed_official 573:ad23fe03a082 662 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
mbed_official 573:ad23fe03a082 663 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 664 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 665 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 666 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 667 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 668 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
mbed_official 573:ad23fe03a082 669 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 670 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
mbed_official 573:ad23fe03a082 671 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 672 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
mbed_official 573:ad23fe03a082 673 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 674 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 675 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 676 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 677 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 678 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 679 } LTDC_TypeDef;
mbed_official 573:ad23fe03a082 680
mbed_official 573:ad23fe03a082 681 /**
mbed_official 573:ad23fe03a082 682 * @brief LCD-TFT Display layer x Controller
mbed_official 573:ad23fe03a082 683 */
mbed_official 573:ad23fe03a082 684
mbed_official 573:ad23fe03a082 685 typedef struct
mbed_official 573:ad23fe03a082 686 {
mbed_official 573:ad23fe03a082 687 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
mbed_official 573:ad23fe03a082 688 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
mbed_official 573:ad23fe03a082 689 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
mbed_official 573:ad23fe03a082 690 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
mbed_official 573:ad23fe03a082 691 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
mbed_official 573:ad23fe03a082 692 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
mbed_official 573:ad23fe03a082 693 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
mbed_official 573:ad23fe03a082 694 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
mbed_official 573:ad23fe03a082 695 uint32_t RESERVED0[2]; /*!< Reserved */
mbed_official 573:ad23fe03a082 696 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
mbed_official 573:ad23fe03a082 697 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
mbed_official 573:ad23fe03a082 698 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
mbed_official 573:ad23fe03a082 699 uint32_t RESERVED1[3]; /*!< Reserved */
mbed_official 573:ad23fe03a082 700 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
mbed_official 573:ad23fe03a082 701
mbed_official 573:ad23fe03a082 702 } LTDC_Layer_TypeDef;
mbed_official 573:ad23fe03a082 703
mbed_official 573:ad23fe03a082 704
mbed_official 573:ad23fe03a082 705 /**
mbed_official 573:ad23fe03a082 706 * @brief Power Control
mbed_official 573:ad23fe03a082 707 */
mbed_official 573:ad23fe03a082 708
mbed_official 573:ad23fe03a082 709 typedef struct
mbed_official 573:ad23fe03a082 710 {
mbed_official 573:ad23fe03a082 711 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 712 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 713 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 714 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 715 } PWR_TypeDef;
mbed_official 573:ad23fe03a082 716
mbed_official 573:ad23fe03a082 717
mbed_official 573:ad23fe03a082 718 /**
mbed_official 573:ad23fe03a082 719 * @brief Reset and Clock Control
mbed_official 573:ad23fe03a082 720 */
mbed_official 573:ad23fe03a082 721
mbed_official 573:ad23fe03a082 722 typedef struct
mbed_official 573:ad23fe03a082 723 {
mbed_official 573:ad23fe03a082 724 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 725 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 726 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 727 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 728 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 729 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 730 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 731 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 573:ad23fe03a082 732 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 733 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 734 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 573:ad23fe03a082 735 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 736 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 737 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 738 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 573:ad23fe03a082 739 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 740 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 741 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 573:ad23fe03a082 742 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 573:ad23fe03a082 743 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 573:ad23fe03a082 744 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 573:ad23fe03a082 745 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 573:ad23fe03a082 746 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 573:ad23fe03a082 747 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 573:ad23fe03a082 748 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 573:ad23fe03a082 749 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 573:ad23fe03a082 750 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 573:ad23fe03a082 751 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 573:ad23fe03a082 752 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 573:ad23fe03a082 753 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 573:ad23fe03a082 754 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
mbed_official 573:ad23fe03a082 755 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
mbed_official 573:ad23fe03a082 756 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
mbed_official 573:ad23fe03a082 757
mbed_official 573:ad23fe03a082 758 } RCC_TypeDef;
mbed_official 573:ad23fe03a082 759
mbed_official 573:ad23fe03a082 760 /**
mbed_official 573:ad23fe03a082 761 * @brief Real-Time Clock
mbed_official 573:ad23fe03a082 762 */
mbed_official 573:ad23fe03a082 763
mbed_official 573:ad23fe03a082 764 typedef struct
mbed_official 573:ad23fe03a082 765 {
mbed_official 573:ad23fe03a082 766 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 767 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 768 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 769 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 770 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 771 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 772 uint32_t reserved; /*!< Reserved */
mbed_official 573:ad23fe03a082 773 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 774 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 775 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 776 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 777 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 778 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 779 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 780 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 781 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 782 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 783 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 784 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 785 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
mbed_official 573:ad23fe03a082 786 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 573:ad23fe03a082 787 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 573:ad23fe03a082 788 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 573:ad23fe03a082 789 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 573:ad23fe03a082 790 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 573:ad23fe03a082 791 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 573:ad23fe03a082 792 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 573:ad23fe03a082 793 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 573:ad23fe03a082 794 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 573:ad23fe03a082 795 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 573:ad23fe03a082 796 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 573:ad23fe03a082 797 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 573:ad23fe03a082 798 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 573:ad23fe03a082 799 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 573:ad23fe03a082 800 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 573:ad23fe03a082 801 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 573:ad23fe03a082 802 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 573:ad23fe03a082 803 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 573:ad23fe03a082 804 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 573:ad23fe03a082 805 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 573:ad23fe03a082 806 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
mbed_official 573:ad23fe03a082 807 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
mbed_official 573:ad23fe03a082 808 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
mbed_official 573:ad23fe03a082 809 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
mbed_official 573:ad23fe03a082 810 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
mbed_official 573:ad23fe03a082 811 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
mbed_official 573:ad23fe03a082 812 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
mbed_official 573:ad23fe03a082 813 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
mbed_official 573:ad23fe03a082 814 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
mbed_official 573:ad23fe03a082 815 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
mbed_official 573:ad23fe03a082 816 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
mbed_official 573:ad23fe03a082 817 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
mbed_official 573:ad23fe03a082 818 } RTC_TypeDef;
mbed_official 573:ad23fe03a082 819
mbed_official 573:ad23fe03a082 820
mbed_official 573:ad23fe03a082 821 /**
mbed_official 573:ad23fe03a082 822 * @brief Serial Audio Interface
mbed_official 573:ad23fe03a082 823 */
mbed_official 573:ad23fe03a082 824
mbed_official 573:ad23fe03a082 825 typedef struct
mbed_official 573:ad23fe03a082 826 {
mbed_official 573:ad23fe03a082 827 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 828 } SAI_TypeDef;
mbed_official 573:ad23fe03a082 829
mbed_official 573:ad23fe03a082 830 typedef struct
mbed_official 573:ad23fe03a082 831 {
mbed_official 573:ad23fe03a082 832 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 833 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 834 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 835 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 836 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 837 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 838 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 839 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 840 } SAI_Block_TypeDef;
mbed_official 573:ad23fe03a082 841
mbed_official 573:ad23fe03a082 842 /**
mbed_official 573:ad23fe03a082 843 * @brief SPDIF-RX Interface
mbed_official 573:ad23fe03a082 844 */
mbed_official 573:ad23fe03a082 845
mbed_official 573:ad23fe03a082 846 typedef struct
mbed_official 573:ad23fe03a082 847 {
mbed_official 573:ad23fe03a082 848 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 849 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 850 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 851 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 852 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 853 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 854 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 855 } SPDIFRX_TypeDef;
mbed_official 573:ad23fe03a082 856
mbed_official 573:ad23fe03a082 857
mbed_official 573:ad23fe03a082 858 /**
mbed_official 573:ad23fe03a082 859 * @brief SD host Interface
mbed_official 573:ad23fe03a082 860 */
mbed_official 573:ad23fe03a082 861
mbed_official 573:ad23fe03a082 862 typedef struct
mbed_official 573:ad23fe03a082 863 {
mbed_official 573:ad23fe03a082 864 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 865 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 866 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 867 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 868 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 869 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 870 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 871 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 872 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 873 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 874 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 875 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 876 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 877 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 878 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 879 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 880 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 573:ad23fe03a082 881 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 882 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 573:ad23fe03a082 883 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
mbed_official 573:ad23fe03a082 884 } SDMMC_TypeDef;
mbed_official 573:ad23fe03a082 885
mbed_official 573:ad23fe03a082 886 /**
mbed_official 573:ad23fe03a082 887 * @brief Serial Peripheral Interface
mbed_official 573:ad23fe03a082 888 */
mbed_official 573:ad23fe03a082 889
mbed_official 573:ad23fe03a082 890 typedef struct
mbed_official 573:ad23fe03a082 891 {
mbed_official 573:ad23fe03a082 892 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 573:ad23fe03a082 893 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 894 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 895 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 896 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 573:ad23fe03a082 897 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 573:ad23fe03a082 898 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 573:ad23fe03a082 899 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 900 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 901 } SPI_TypeDef;
mbed_official 573:ad23fe03a082 902
mbed_official 573:ad23fe03a082 903 /**
mbed_official 573:ad23fe03a082 904 * @brief QUAD Serial Peripheral Interface
mbed_official 573:ad23fe03a082 905 */
mbed_official 573:ad23fe03a082 906
mbed_official 573:ad23fe03a082 907 typedef struct
mbed_official 573:ad23fe03a082 908 {
mbed_official 573:ad23fe03a082 909 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 910 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 911 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 912 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 913 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 914 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 915 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 916 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 917 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 918 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 919 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 920 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 921 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 922 } QUADSPI_TypeDef;
mbed_official 573:ad23fe03a082 923
mbed_official 573:ad23fe03a082 924 /**
mbed_official 573:ad23fe03a082 925 * @brief TIM
mbed_official 573:ad23fe03a082 926 */
mbed_official 573:ad23fe03a082 927
mbed_official 573:ad23fe03a082 928 typedef struct
mbed_official 573:ad23fe03a082 929 {
mbed_official 573:ad23fe03a082 930 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 931 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 932 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 933 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 934 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 935 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 936 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 937 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 938 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 939 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 940 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 941 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 573:ad23fe03a082 942 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 573:ad23fe03a082 943 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 573:ad23fe03a082 944 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 573:ad23fe03a082 945 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 573:ad23fe03a082 946 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 573:ad23fe03a082 947 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 573:ad23fe03a082 948 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 573:ad23fe03a082 949 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 573:ad23fe03a082 950 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 573:ad23fe03a082 951 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 573:ad23fe03a082 952 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
mbed_official 573:ad23fe03a082 953 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
mbed_official 573:ad23fe03a082 954
mbed_official 573:ad23fe03a082 955 } TIM_TypeDef;
mbed_official 573:ad23fe03a082 956
mbed_official 573:ad23fe03a082 957 /**
mbed_official 573:ad23fe03a082 958 * @brief LPTIMIMER
mbed_official 573:ad23fe03a082 959 */
mbed_official 573:ad23fe03a082 960 typedef struct
mbed_official 573:ad23fe03a082 961 {
mbed_official 573:ad23fe03a082 962 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 963 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 964 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 965 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 966 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 967 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 968 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 969 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 970 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 971 } LPTIM_TypeDef;
mbed_official 573:ad23fe03a082 972
mbed_official 573:ad23fe03a082 973
mbed_official 573:ad23fe03a082 974 /**
mbed_official 573:ad23fe03a082 975 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 573:ad23fe03a082 976 */
mbed_official 573:ad23fe03a082 977
mbed_official 573:ad23fe03a082 978 typedef struct
mbed_official 573:ad23fe03a082 979 {
mbed_official 573:ad23fe03a082 980 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 981 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 982 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 983 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 573:ad23fe03a082 984 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 573:ad23fe03a082 985 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 573:ad23fe03a082 986 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 573:ad23fe03a082 987 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 573:ad23fe03a082 988 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 573:ad23fe03a082 989 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 573:ad23fe03a082 990 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 573:ad23fe03a082 991 } USART_TypeDef;
mbed_official 573:ad23fe03a082 992
mbed_official 573:ad23fe03a082 993
mbed_official 573:ad23fe03a082 994 /**
mbed_official 573:ad23fe03a082 995 * @brief Window WATCHDOG
mbed_official 573:ad23fe03a082 996 */
mbed_official 573:ad23fe03a082 997
mbed_official 573:ad23fe03a082 998 typedef struct
mbed_official 573:ad23fe03a082 999 {
mbed_official 573:ad23fe03a082 1000 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 1001 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 1002 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 1003 } WWDG_TypeDef;
mbed_official 573:ad23fe03a082 1004
mbed_official 573:ad23fe03a082 1005 /**
mbed_official 573:ad23fe03a082 1006 * @brief RNG
mbed_official 573:ad23fe03a082 1007 */
mbed_official 573:ad23fe03a082 1008
mbed_official 573:ad23fe03a082 1009 typedef struct
mbed_official 573:ad23fe03a082 1010 {
mbed_official 573:ad23fe03a082 1011 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 573:ad23fe03a082 1012 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 573:ad23fe03a082 1013 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 573:ad23fe03a082 1014 } RNG_TypeDef;
mbed_official 573:ad23fe03a082 1015
mbed_official 573:ad23fe03a082 1016 /**
mbed_official 573:ad23fe03a082 1017 * @}
mbed_official 573:ad23fe03a082 1018 */
mbed_official 573:ad23fe03a082 1019
mbed_official 573:ad23fe03a082 1020 /**
mbed_official 573:ad23fe03a082 1021 * @brief USB_OTG_Core_Registers
mbed_official 573:ad23fe03a082 1022 */
mbed_official 573:ad23fe03a082 1023 typedef struct
mbed_official 573:ad23fe03a082 1024 {
mbed_official 573:ad23fe03a082 1025 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
mbed_official 573:ad23fe03a082 1026 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
mbed_official 573:ad23fe03a082 1027 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
mbed_official 573:ad23fe03a082 1028 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
mbed_official 573:ad23fe03a082 1029 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
mbed_official 573:ad23fe03a082 1030 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
mbed_official 573:ad23fe03a082 1031 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
mbed_official 573:ad23fe03a082 1032 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
mbed_official 573:ad23fe03a082 1033 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
mbed_official 573:ad23fe03a082 1034 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
mbed_official 573:ad23fe03a082 1035 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
mbed_official 573:ad23fe03a082 1036 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
mbed_official 573:ad23fe03a082 1037 uint32_t Reserved30[2]; /*!< Reserved 030h */
mbed_official 573:ad23fe03a082 1038 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
mbed_official 573:ad23fe03a082 1039 __IO uint32_t CID; /*!< User ID Register 03Ch */
mbed_official 573:ad23fe03a082 1040 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
mbed_official 573:ad23fe03a082 1041 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
mbed_official 573:ad23fe03a082 1042 uint32_t Reserved6; /*!< Reserved 050h */
mbed_official 573:ad23fe03a082 1043 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
mbed_official 573:ad23fe03a082 1044 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
mbed_official 573:ad23fe03a082 1045 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
mbed_official 573:ad23fe03a082 1046 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
mbed_official 573:ad23fe03a082 1047 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
mbed_official 573:ad23fe03a082 1048 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
mbed_official 573:ad23fe03a082 1049 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
mbed_official 573:ad23fe03a082 1050 } USB_OTG_GlobalTypeDef;
mbed_official 573:ad23fe03a082 1051
mbed_official 573:ad23fe03a082 1052
mbed_official 573:ad23fe03a082 1053 /**
mbed_official 573:ad23fe03a082 1054 * @brief USB_OTG_device_Registers
mbed_official 573:ad23fe03a082 1055 */
mbed_official 573:ad23fe03a082 1056 typedef struct
mbed_official 573:ad23fe03a082 1057 {
mbed_official 573:ad23fe03a082 1058 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
mbed_official 573:ad23fe03a082 1059 __IO uint32_t DCTL; /*!< dev Control Register 804h */
mbed_official 573:ad23fe03a082 1060 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
mbed_official 573:ad23fe03a082 1061 uint32_t Reserved0C; /*!< Reserved 80Ch */
mbed_official 573:ad23fe03a082 1062 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
mbed_official 573:ad23fe03a082 1063 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
mbed_official 573:ad23fe03a082 1064 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
mbed_official 573:ad23fe03a082 1065 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
mbed_official 573:ad23fe03a082 1066 uint32_t Reserved20; /*!< Reserved 820h */
mbed_official 573:ad23fe03a082 1067 uint32_t Reserved9; /*!< Reserved 824h */
mbed_official 573:ad23fe03a082 1068 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
mbed_official 573:ad23fe03a082 1069 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
mbed_official 573:ad23fe03a082 1070 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
mbed_official 573:ad23fe03a082 1071 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
mbed_official 573:ad23fe03a082 1072 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
mbed_official 573:ad23fe03a082 1073 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
mbed_official 573:ad23fe03a082 1074 uint32_t Reserved40; /*!< dedicated EP mask 840h */
mbed_official 573:ad23fe03a082 1075 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
mbed_official 573:ad23fe03a082 1076 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
mbed_official 573:ad23fe03a082 1077 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
mbed_official 573:ad23fe03a082 1078 } USB_OTG_DeviceTypeDef;
mbed_official 573:ad23fe03a082 1079
mbed_official 573:ad23fe03a082 1080
mbed_official 573:ad23fe03a082 1081 /**
mbed_official 573:ad23fe03a082 1082 * @brief USB_OTG_IN_Endpoint-Specific_Register
mbed_official 573:ad23fe03a082 1083 */
mbed_official 573:ad23fe03a082 1084 typedef struct
mbed_official 573:ad23fe03a082 1085 {
mbed_official 573:ad23fe03a082 1086 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
mbed_official 573:ad23fe03a082 1087 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
mbed_official 573:ad23fe03a082 1088 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
mbed_official 573:ad23fe03a082 1089 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
mbed_official 573:ad23fe03a082 1090 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
mbed_official 573:ad23fe03a082 1091 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
mbed_official 573:ad23fe03a082 1092 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
mbed_official 573:ad23fe03a082 1093 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
mbed_official 573:ad23fe03a082 1094 } USB_OTG_INEndpointTypeDef;
mbed_official 573:ad23fe03a082 1095
mbed_official 573:ad23fe03a082 1096
mbed_official 573:ad23fe03a082 1097 /**
mbed_official 573:ad23fe03a082 1098 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
mbed_official 573:ad23fe03a082 1099 */
mbed_official 573:ad23fe03a082 1100 typedef struct
mbed_official 573:ad23fe03a082 1101 {
mbed_official 573:ad23fe03a082 1102 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
mbed_official 573:ad23fe03a082 1103 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
mbed_official 573:ad23fe03a082 1104 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
mbed_official 573:ad23fe03a082 1105 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
mbed_official 573:ad23fe03a082 1106 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
mbed_official 573:ad23fe03a082 1107 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
mbed_official 573:ad23fe03a082 1108 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
mbed_official 573:ad23fe03a082 1109 } USB_OTG_OUTEndpointTypeDef;
mbed_official 573:ad23fe03a082 1110
mbed_official 573:ad23fe03a082 1111
mbed_official 573:ad23fe03a082 1112 /**
mbed_official 573:ad23fe03a082 1113 * @brief USB_OTG_Host_Mode_Register_Structures
mbed_official 573:ad23fe03a082 1114 */
mbed_official 573:ad23fe03a082 1115 typedef struct
mbed_official 573:ad23fe03a082 1116 {
mbed_official 573:ad23fe03a082 1117 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
mbed_official 573:ad23fe03a082 1118 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
mbed_official 573:ad23fe03a082 1119 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
mbed_official 573:ad23fe03a082 1120 uint32_t Reserved40C; /*!< Reserved 40Ch */
mbed_official 573:ad23fe03a082 1121 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
mbed_official 573:ad23fe03a082 1122 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
mbed_official 573:ad23fe03a082 1123 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
mbed_official 573:ad23fe03a082 1124 } USB_OTG_HostTypeDef;
mbed_official 573:ad23fe03a082 1125
mbed_official 573:ad23fe03a082 1126 /**
mbed_official 573:ad23fe03a082 1127 * @brief USB_OTG_Host_Channel_Specific_Registers
mbed_official 573:ad23fe03a082 1128 */
mbed_official 573:ad23fe03a082 1129 typedef struct
mbed_official 573:ad23fe03a082 1130 {
mbed_official 573:ad23fe03a082 1131 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
mbed_official 573:ad23fe03a082 1132 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
mbed_official 573:ad23fe03a082 1133 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
mbed_official 573:ad23fe03a082 1134 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
mbed_official 573:ad23fe03a082 1135 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
mbed_official 573:ad23fe03a082 1136 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
mbed_official 573:ad23fe03a082 1137 uint32_t Reserved[2]; /*!< Reserved */
mbed_official 573:ad23fe03a082 1138 } USB_OTG_HostChannelTypeDef;
mbed_official 573:ad23fe03a082 1139 /**
mbed_official 573:ad23fe03a082 1140 * @}
mbed_official 573:ad23fe03a082 1141 */
mbed_official 573:ad23fe03a082 1142
mbed_official 573:ad23fe03a082 1143
mbed_official 573:ad23fe03a082 1144 /** @addtogroup Peripheral_memory_map
mbed_official 573:ad23fe03a082 1145 * @{
mbed_official 573:ad23fe03a082 1146 */
mbed_official 573:ad23fe03a082 1147 #define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */
mbed_official 573:ad23fe03a082 1148 #define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
mbed_official 573:ad23fe03a082 1149 #define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
mbed_official 573:ad23fe03a082 1150 #define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
mbed_official 573:ad23fe03a082 1151 #define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
mbed_official 573:ad23fe03a082 1152 #define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
mbed_official 573:ad23fe03a082 1153 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
mbed_official 573:ad23fe03a082 1154 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
mbed_official 573:ad23fe03a082 1155 #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
mbed_official 573:ad23fe03a082 1156 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
mbed_official 573:ad23fe03a082 1157 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
mbed_official 573:ad23fe03a082 1158 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
mbed_official 573:ad23fe03a082 1159
mbed_official 573:ad23fe03a082 1160 /* Legacy define */
mbed_official 573:ad23fe03a082 1161 #define FLASH_BASE FLASHAXI_BASE
mbed_official 573:ad23fe03a082 1162
mbed_official 573:ad23fe03a082 1163 /*!< Peripheral memory map */
mbed_official 573:ad23fe03a082 1164 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 573:ad23fe03a082 1165 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 573:ad23fe03a082 1166 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 573:ad23fe03a082 1167 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 573:ad23fe03a082 1168
mbed_official 573:ad23fe03a082 1169 /*!< APB1 peripherals */
mbed_official 573:ad23fe03a082 1170 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 573:ad23fe03a082 1171 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 573:ad23fe03a082 1172 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 573:ad23fe03a082 1173 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 573:ad23fe03a082 1174 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 573:ad23fe03a082 1175 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 573:ad23fe03a082 1176 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
mbed_official 573:ad23fe03a082 1177 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
mbed_official 573:ad23fe03a082 1178 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
mbed_official 573:ad23fe03a082 1179 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
mbed_official 573:ad23fe03a082 1180 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 573:ad23fe03a082 1181 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 573:ad23fe03a082 1182 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 573:ad23fe03a082 1183 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 573:ad23fe03a082 1184 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 573:ad23fe03a082 1185 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 573:ad23fe03a082 1186 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 573:ad23fe03a082 1187 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 573:ad23fe03a082 1188 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official 573:ad23fe03a082 1189 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official 573:ad23fe03a082 1190 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 573:ad23fe03a082 1191 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 573:ad23fe03a082 1192 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 573:ad23fe03a082 1193 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
mbed_official 573:ad23fe03a082 1194 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
mbed_official 573:ad23fe03a082 1195 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
mbed_official 573:ad23fe03a082 1196 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
mbed_official 573:ad23fe03a082 1197 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 573:ad23fe03a082 1198 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 573:ad23fe03a082 1199 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
mbed_official 573:ad23fe03a082 1200 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
mbed_official 573:ad23fe03a082 1201
mbed_official 573:ad23fe03a082 1202 /*!< APB2 peripherals */
mbed_official 573:ad23fe03a082 1203 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 573:ad23fe03a082 1204 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 573:ad23fe03a082 1205 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 573:ad23fe03a082 1206 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 573:ad23fe03a082 1207 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 573:ad23fe03a082 1208 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
mbed_official 573:ad23fe03a082 1209 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
mbed_official 573:ad23fe03a082 1210 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 573:ad23fe03a082 1211 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 573:ad23fe03a082 1212 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 573:ad23fe03a082 1213 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
mbed_official 573:ad23fe03a082 1214 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 573:ad23fe03a082 1215 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 573:ad23fe03a082 1216 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 573:ad23fe03a082 1217 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 573:ad23fe03a082 1218 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 573:ad23fe03a082 1219 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
mbed_official 573:ad23fe03a082 1220 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
mbed_official 573:ad23fe03a082 1221 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
mbed_official 573:ad23fe03a082 1222 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
mbed_official 573:ad23fe03a082 1223 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
mbed_official 573:ad23fe03a082 1224 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
mbed_official 573:ad23fe03a082 1225 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
mbed_official 573:ad23fe03a082 1226 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
mbed_official 573:ad23fe03a082 1227 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
mbed_official 573:ad23fe03a082 1228 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
mbed_official 573:ad23fe03a082 1229 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
mbed_official 573:ad23fe03a082 1230 /*!< AHB1 peripherals */
mbed_official 573:ad23fe03a082 1231 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 573:ad23fe03a082 1232 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 573:ad23fe03a082 1233 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 573:ad23fe03a082 1234 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 573:ad23fe03a082 1235 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 573:ad23fe03a082 1236 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
mbed_official 573:ad23fe03a082 1237 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
mbed_official 573:ad23fe03a082 1238 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 573:ad23fe03a082 1239 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
mbed_official 573:ad23fe03a082 1240 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
mbed_official 573:ad23fe03a082 1241 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
mbed_official 573:ad23fe03a082 1242 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 573:ad23fe03a082 1243 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 573:ad23fe03a082 1244 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 573:ad23fe03a082 1245 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 573:ad23fe03a082 1246 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 573:ad23fe03a082 1247 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 573:ad23fe03a082 1248 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 573:ad23fe03a082 1249 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 573:ad23fe03a082 1250 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 573:ad23fe03a082 1251 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 573:ad23fe03a082 1252 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 573:ad23fe03a082 1253 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 573:ad23fe03a082 1254 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 573:ad23fe03a082 1255 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 573:ad23fe03a082 1256 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 573:ad23fe03a082 1257 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 573:ad23fe03a082 1258 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 573:ad23fe03a082 1259 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 573:ad23fe03a082 1260 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 573:ad23fe03a082 1261 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 573:ad23fe03a082 1262 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 573:ad23fe03a082 1263 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
mbed_official 573:ad23fe03a082 1264 #define ETH_MAC_BASE (ETH_BASE)
mbed_official 573:ad23fe03a082 1265 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
mbed_official 573:ad23fe03a082 1266 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
mbed_official 573:ad23fe03a082 1267 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
mbed_official 573:ad23fe03a082 1268 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
mbed_official 573:ad23fe03a082 1269 /*!< AHB2 peripherals */
mbed_official 573:ad23fe03a082 1270 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
mbed_official 573:ad23fe03a082 1271 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
mbed_official 573:ad23fe03a082 1272 /*!< FMC Bankx registers base address */
mbed_official 573:ad23fe03a082 1273 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
mbed_official 573:ad23fe03a082 1274 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
mbed_official 573:ad23fe03a082 1275 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
mbed_official 573:ad23fe03a082 1276 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
mbed_official 573:ad23fe03a082 1277
mbed_official 573:ad23fe03a082 1278 /* Debug MCU registers base address */
mbed_official 573:ad23fe03a082 1279 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 573:ad23fe03a082 1280
mbed_official 573:ad23fe03a082 1281 /*!< USB registers base address */
mbed_official 573:ad23fe03a082 1282 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
mbed_official 573:ad23fe03a082 1283 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 573:ad23fe03a082 1284
mbed_official 573:ad23fe03a082 1285 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 573:ad23fe03a082 1286 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 573:ad23fe03a082 1287 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 573:ad23fe03a082 1288 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 573:ad23fe03a082 1289 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 573:ad23fe03a082 1290 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 573:ad23fe03a082 1291 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 573:ad23fe03a082 1292 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 573:ad23fe03a082 1293 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 573:ad23fe03a082 1294 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 573:ad23fe03a082 1295 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 573:ad23fe03a082 1296 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 573:ad23fe03a082 1297
mbed_official 573:ad23fe03a082 1298 /**
mbed_official 573:ad23fe03a082 1299 * @}
mbed_official 573:ad23fe03a082 1300 */
mbed_official 573:ad23fe03a082 1301
mbed_official 573:ad23fe03a082 1302 /** @addtogroup Peripheral_declaration
mbed_official 573:ad23fe03a082 1303 * @{
mbed_official 573:ad23fe03a082 1304 */
mbed_official 573:ad23fe03a082 1305 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 573:ad23fe03a082 1306 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 573:ad23fe03a082 1307 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 573:ad23fe03a082 1308 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 573:ad23fe03a082 1309 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 573:ad23fe03a082 1310 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 573:ad23fe03a082 1311 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 573:ad23fe03a082 1312 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 573:ad23fe03a082 1313 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 573:ad23fe03a082 1314 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official 573:ad23fe03a082 1315 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 573:ad23fe03a082 1316 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 573:ad23fe03a082 1317 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 573:ad23fe03a082 1318 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 573:ad23fe03a082 1319 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 573:ad23fe03a082 1320 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
mbed_official 573:ad23fe03a082 1321 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 573:ad23fe03a082 1322 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 573:ad23fe03a082 1323 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 573:ad23fe03a082 1324 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 573:ad23fe03a082 1325 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 573:ad23fe03a082 1326 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 573:ad23fe03a082 1327 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 573:ad23fe03a082 1328 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
mbed_official 573:ad23fe03a082 1329 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 573:ad23fe03a082 1330 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 573:ad23fe03a082 1331 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 573:ad23fe03a082 1332 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 573:ad23fe03a082 1333 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 573:ad23fe03a082 1334 #define UART7 ((USART_TypeDef *) UART7_BASE)
mbed_official 573:ad23fe03a082 1335 #define UART8 ((USART_TypeDef *) UART8_BASE)
mbed_official 573:ad23fe03a082 1336 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 573:ad23fe03a082 1337 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 573:ad23fe03a082 1338 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 573:ad23fe03a082 1339 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 573:ad23fe03a082 1340 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 573:ad23fe03a082 1341 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 573:ad23fe03a082 1342 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 573:ad23fe03a082 1343 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 573:ad23fe03a082 1344 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
mbed_official 573:ad23fe03a082 1345 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 573:ad23fe03a082 1346 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 573:ad23fe03a082 1347 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 573:ad23fe03a082 1348 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 573:ad23fe03a082 1349 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 573:ad23fe03a082 1350 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 573:ad23fe03a082 1351 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 573:ad23fe03a082 1352 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 573:ad23fe03a082 1353 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
mbed_official 573:ad23fe03a082 1354 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
mbed_official 573:ad23fe03a082 1355 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
mbed_official 573:ad23fe03a082 1356 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
mbed_official 573:ad23fe03a082 1357 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
mbed_official 573:ad23fe03a082 1358 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
mbed_official 573:ad23fe03a082 1359 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
mbed_official 573:ad23fe03a082 1360 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
mbed_official 573:ad23fe03a082 1361 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
mbed_official 573:ad23fe03a082 1362 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
mbed_official 573:ad23fe03a082 1363 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 573:ad23fe03a082 1364 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 573:ad23fe03a082 1365 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 573:ad23fe03a082 1366 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 573:ad23fe03a082 1367 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 573:ad23fe03a082 1368 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 573:ad23fe03a082 1369 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 573:ad23fe03a082 1370 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 573:ad23fe03a082 1371 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
mbed_official 573:ad23fe03a082 1372 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
mbed_official 573:ad23fe03a082 1373 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
mbed_official 573:ad23fe03a082 1374 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 573:ad23fe03a082 1375 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 573:ad23fe03a082 1376 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 573:ad23fe03a082 1377 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 573:ad23fe03a082 1378 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 573:ad23fe03a082 1379 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 573:ad23fe03a082 1380 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 573:ad23fe03a082 1381 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 573:ad23fe03a082 1382 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 573:ad23fe03a082 1383 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 573:ad23fe03a082 1384 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 573:ad23fe03a082 1385 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 573:ad23fe03a082 1386 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 573:ad23fe03a082 1387 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 573:ad23fe03a082 1388 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 573:ad23fe03a082 1389 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 573:ad23fe03a082 1390 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 573:ad23fe03a082 1391 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 573:ad23fe03a082 1392 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 573:ad23fe03a082 1393 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 573:ad23fe03a082 1394 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 573:ad23fe03a082 1395 #define ETH ((ETH_TypeDef *) ETH_BASE)
mbed_official 573:ad23fe03a082 1396 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
mbed_official 573:ad23fe03a082 1397 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
mbed_official 573:ad23fe03a082 1398 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 573:ad23fe03a082 1399 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
mbed_official 573:ad23fe03a082 1400 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
mbed_official 573:ad23fe03a082 1401 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
mbed_official 573:ad23fe03a082 1402 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
mbed_official 573:ad23fe03a082 1403 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
mbed_official 573:ad23fe03a082 1404 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 573:ad23fe03a082 1405 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 573:ad23fe03a082 1406 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 573:ad23fe03a082 1407
mbed_official 573:ad23fe03a082 1408 /**
mbed_official 573:ad23fe03a082 1409 * @}
mbed_official 573:ad23fe03a082 1410 */
mbed_official 573:ad23fe03a082 1411
mbed_official 573:ad23fe03a082 1412 /** @addtogroup Exported_constants
mbed_official 573:ad23fe03a082 1413 * @{
mbed_official 573:ad23fe03a082 1414 */
mbed_official 573:ad23fe03a082 1415
mbed_official 573:ad23fe03a082 1416 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 573:ad23fe03a082 1417 * @{
mbed_official 573:ad23fe03a082 1418 */
mbed_official 573:ad23fe03a082 1419
mbed_official 573:ad23fe03a082 1420 /******************************************************************************/
mbed_official 573:ad23fe03a082 1421 /* Peripheral Registers_Bits_Definition */
mbed_official 573:ad23fe03a082 1422 /******************************************************************************/
mbed_official 573:ad23fe03a082 1423
mbed_official 573:ad23fe03a082 1424 /******************************************************************************/
mbed_official 573:ad23fe03a082 1425 /* */
mbed_official 573:ad23fe03a082 1426 /* Analog to Digital Converter */
mbed_official 573:ad23fe03a082 1427 /* */
mbed_official 573:ad23fe03a082 1428 /******************************************************************************/
mbed_official 573:ad23fe03a082 1429 /******************** Bit definition for ADC_SR register ********************/
mbed_official 573:ad23fe03a082 1430 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 573:ad23fe03a082 1431 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 573:ad23fe03a082 1432 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 573:ad23fe03a082 1433 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 573:ad23fe03a082 1434 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 573:ad23fe03a082 1435 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 573:ad23fe03a082 1436
mbed_official 573:ad23fe03a082 1437 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 573:ad23fe03a082 1438 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 573:ad23fe03a082 1439 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1440 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1441 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1442 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1443 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1444 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 573:ad23fe03a082 1445 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 573:ad23fe03a082 1446 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 573:ad23fe03a082 1447 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 573:ad23fe03a082 1448 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 573:ad23fe03a082 1449 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 573:ad23fe03a082 1450 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 573:ad23fe03a082 1451 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 573:ad23fe03a082 1452 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 573:ad23fe03a082 1453 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1454 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1455 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1456 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 573:ad23fe03a082 1457 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 573:ad23fe03a082 1458 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 573:ad23fe03a082 1459 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1460 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1461 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 573:ad23fe03a082 1462
mbed_official 573:ad23fe03a082 1463 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 573:ad23fe03a082 1464 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 573:ad23fe03a082 1465 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 573:ad23fe03a082 1466 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 573:ad23fe03a082 1467 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 573:ad23fe03a082 1468 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 573:ad23fe03a082 1469 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 573:ad23fe03a082 1470 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 573:ad23fe03a082 1471 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1472 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1473 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1474 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1475 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 573:ad23fe03a082 1476 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1477 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1478 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 573:ad23fe03a082 1479 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 573:ad23fe03a082 1480 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1481 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1482 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1483 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1484 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 573:ad23fe03a082 1485 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1486 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1487 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 573:ad23fe03a082 1488
mbed_official 573:ad23fe03a082 1489 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 573:ad23fe03a082 1490 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 573:ad23fe03a082 1491 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1492 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1493 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1494 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 573:ad23fe03a082 1495 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1496 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1497 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1498 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 573:ad23fe03a082 1499 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1500 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1501 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1502 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 573:ad23fe03a082 1503 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1504 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1505 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1506 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 573:ad23fe03a082 1507 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1508 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1509 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1510 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 573:ad23fe03a082 1511 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1512 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1513 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1514 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 573:ad23fe03a082 1515 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1516 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1517 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1518 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 573:ad23fe03a082 1519 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1520 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1521 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1522 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 573:ad23fe03a082 1523 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1524 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1525 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1526
mbed_official 573:ad23fe03a082 1527 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 573:ad23fe03a082 1528 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 573:ad23fe03a082 1529 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1530 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1531 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1532 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 573:ad23fe03a082 1533 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1534 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1535 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1536 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 573:ad23fe03a082 1537 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1538 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1539 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1540 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 573:ad23fe03a082 1541 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1542 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1543 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1544 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 573:ad23fe03a082 1545 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1546 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1547 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1548 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 573:ad23fe03a082 1549 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1550 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1551 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1552 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 573:ad23fe03a082 1553 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1554 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1555 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1556 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 573:ad23fe03a082 1557 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1558 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1559 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1560 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 573:ad23fe03a082 1561 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1562 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1563 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1564 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 573:ad23fe03a082 1565 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1566 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1567 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1568
mbed_official 573:ad23fe03a082 1569 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 573:ad23fe03a082 1570 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 573:ad23fe03a082 1571
mbed_official 573:ad23fe03a082 1572 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 573:ad23fe03a082 1573 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 573:ad23fe03a082 1574
mbed_official 573:ad23fe03a082 1575 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 573:ad23fe03a082 1576 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 573:ad23fe03a082 1577
mbed_official 573:ad23fe03a082 1578 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 573:ad23fe03a082 1579 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 573:ad23fe03a082 1580
mbed_official 573:ad23fe03a082 1581 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 573:ad23fe03a082 1582 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 573:ad23fe03a082 1583
mbed_official 573:ad23fe03a082 1584 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 573:ad23fe03a082 1585 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 573:ad23fe03a082 1586
mbed_official 573:ad23fe03a082 1587 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 573:ad23fe03a082 1588 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1589 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1590 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1591 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1592 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1593 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1594 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1595 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1596 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1597 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1598 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1599 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1600 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1601 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1602 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1603 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1604 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1605 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1606 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1607 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1608 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1609 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1610 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1611 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1612 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 573:ad23fe03a082 1613 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1614 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1615 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1616 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1617
mbed_official 573:ad23fe03a082 1618 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 573:ad23fe03a082 1619 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1620 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1621 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1622 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1623 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1624 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1625 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1626 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1627 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1628 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1629 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1630 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1631 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1632 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1633 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1634 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1635 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1636 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1637 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1638 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1639 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1640 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1641 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1642 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1643 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1644 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1645 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1646 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1647 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1648 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1649 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1650 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1651 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1652 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1653 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1654 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1655
mbed_official 573:ad23fe03a082 1656 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 573:ad23fe03a082 1657 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1658 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1659 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1660 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1661 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1662 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1663 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1664 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1665 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1666 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1667 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1668 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1669 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1670 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1671 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1672 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1673 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1674 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1675 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1676 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1677 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1678 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1679 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1680 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1681 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1682 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1683 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1684 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1685 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1686 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1687 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 573:ad23fe03a082 1688 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1689 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1690 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1691 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1692 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1693
mbed_official 573:ad23fe03a082 1694 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 573:ad23fe03a082 1695 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 573:ad23fe03a082 1696 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1697 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1698 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1699 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1700 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1701 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 573:ad23fe03a082 1702 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1703 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1704 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1705 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1706 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1707 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 573:ad23fe03a082 1708 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1709 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1710 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1711 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1712 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1713 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 573:ad23fe03a082 1714 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1715 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1716 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1717 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1718 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1719 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 573:ad23fe03a082 1720 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1721 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1722
mbed_official 573:ad23fe03a082 1723 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 573:ad23fe03a082 1724 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
mbed_official 573:ad23fe03a082 1725
mbed_official 573:ad23fe03a082 1726 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 573:ad23fe03a082 1727 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
mbed_official 573:ad23fe03a082 1728
mbed_official 573:ad23fe03a082 1729 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 573:ad23fe03a082 1730 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
mbed_official 573:ad23fe03a082 1731
mbed_official 573:ad23fe03a082 1732 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 573:ad23fe03a082 1733 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
mbed_official 573:ad23fe03a082 1734
mbed_official 573:ad23fe03a082 1735 /******************** Bit definition for ADC_DR register ********************/
mbed_official 573:ad23fe03a082 1736 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 573:ad23fe03a082 1737 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 573:ad23fe03a082 1738
mbed_official 573:ad23fe03a082 1739 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 573:ad23fe03a082 1740 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 573:ad23fe03a082 1741 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 573:ad23fe03a082 1742 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 573:ad23fe03a082 1743 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 573:ad23fe03a082 1744 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 573:ad23fe03a082 1745 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 573:ad23fe03a082 1746 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 573:ad23fe03a082 1747 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 573:ad23fe03a082 1748 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 573:ad23fe03a082 1749 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 573:ad23fe03a082 1750 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 573:ad23fe03a082 1751 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 573:ad23fe03a082 1752 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 573:ad23fe03a082 1753 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 573:ad23fe03a082 1754 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 573:ad23fe03a082 1755 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 573:ad23fe03a082 1756 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 573:ad23fe03a082 1757 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 573:ad23fe03a082 1758
mbed_official 573:ad23fe03a082 1759 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 573:ad23fe03a082 1760 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 573:ad23fe03a082 1761 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1762 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1763 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1764 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1765 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 1766 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 573:ad23fe03a082 1767 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1768 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1769 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1770 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1771 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 573:ad23fe03a082 1772 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 573:ad23fe03a082 1773 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1774 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1775 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 573:ad23fe03a082 1776 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1777 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1778 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 573:ad23fe03a082 1779 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 573:ad23fe03a082 1780
mbed_official 573:ad23fe03a082 1781 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 573:ad23fe03a082 1782 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 573:ad23fe03a082 1783 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 573:ad23fe03a082 1784
mbed_official 573:ad23fe03a082 1785 /******************************************************************************/
mbed_official 573:ad23fe03a082 1786 /* */
mbed_official 573:ad23fe03a082 1787 /* Controller Area Network */
mbed_official 573:ad23fe03a082 1788 /* */
mbed_official 573:ad23fe03a082 1789 /******************************************************************************/
mbed_official 573:ad23fe03a082 1790 /*!<CAN control and status registers */
mbed_official 573:ad23fe03a082 1791 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 573:ad23fe03a082 1792 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 573:ad23fe03a082 1793 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 573:ad23fe03a082 1794 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 573:ad23fe03a082 1795 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 573:ad23fe03a082 1796 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 573:ad23fe03a082 1797 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 573:ad23fe03a082 1798 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 573:ad23fe03a082 1799 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 573:ad23fe03a082 1800 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 573:ad23fe03a082 1801
mbed_official 573:ad23fe03a082 1802 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 573:ad23fe03a082 1803 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 573:ad23fe03a082 1804 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 573:ad23fe03a082 1805 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 573:ad23fe03a082 1806 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 573:ad23fe03a082 1807 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 573:ad23fe03a082 1808 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 573:ad23fe03a082 1809 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 573:ad23fe03a082 1810 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 573:ad23fe03a082 1811 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 573:ad23fe03a082 1812
mbed_official 573:ad23fe03a082 1813 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 573:ad23fe03a082 1814 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 573:ad23fe03a082 1815 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 573:ad23fe03a082 1816 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 573:ad23fe03a082 1817 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 573:ad23fe03a082 1818 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 573:ad23fe03a082 1819 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 573:ad23fe03a082 1820 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 573:ad23fe03a082 1821 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 573:ad23fe03a082 1822 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 573:ad23fe03a082 1823 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 573:ad23fe03a082 1824 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 573:ad23fe03a082 1825 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 573:ad23fe03a082 1826 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 573:ad23fe03a082 1827 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 573:ad23fe03a082 1828 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 573:ad23fe03a082 1829 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 573:ad23fe03a082 1830
mbed_official 573:ad23fe03a082 1831 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 573:ad23fe03a082 1832 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 573:ad23fe03a082 1833 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 573:ad23fe03a082 1834 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 573:ad23fe03a082 1835
mbed_official 573:ad23fe03a082 1836 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 573:ad23fe03a082 1837 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 573:ad23fe03a082 1838 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 573:ad23fe03a082 1839 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 573:ad23fe03a082 1840
mbed_official 573:ad23fe03a082 1841 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 573:ad23fe03a082 1842 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 573:ad23fe03a082 1843 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 573:ad23fe03a082 1844 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 573:ad23fe03a082 1845 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 573:ad23fe03a082 1846
mbed_official 573:ad23fe03a082 1847 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 573:ad23fe03a082 1848 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 573:ad23fe03a082 1849 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 573:ad23fe03a082 1850 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 573:ad23fe03a082 1851 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 573:ad23fe03a082 1852
mbed_official 573:ad23fe03a082 1853 /******************** Bit definition for CAN_IER register *******************/
mbed_official 573:ad23fe03a082 1854 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 573:ad23fe03a082 1855 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 573:ad23fe03a082 1856 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 573:ad23fe03a082 1857 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 573:ad23fe03a082 1858 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 573:ad23fe03a082 1859 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 573:ad23fe03a082 1860 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 573:ad23fe03a082 1861 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 573:ad23fe03a082 1862 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 573:ad23fe03a082 1863 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 573:ad23fe03a082 1864 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 573:ad23fe03a082 1865 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 573:ad23fe03a082 1866 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 573:ad23fe03a082 1867 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 573:ad23fe03a082 1868
mbed_official 573:ad23fe03a082 1869 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 573:ad23fe03a082 1870 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 573:ad23fe03a082 1871 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 573:ad23fe03a082 1872 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 573:ad23fe03a082 1873
mbed_official 573:ad23fe03a082 1874 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 573:ad23fe03a082 1875 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1876 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1877 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1878
mbed_official 573:ad23fe03a082 1879 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 573:ad23fe03a082 1880 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 573:ad23fe03a082 1881
mbed_official 573:ad23fe03a082 1882 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 573:ad23fe03a082 1883 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 573:ad23fe03a082 1884 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 573:ad23fe03a082 1885 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1886 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1887 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1888 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 1889 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 573:ad23fe03a082 1890 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1891 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1892 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 1893 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 573:ad23fe03a082 1894 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 1895 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 1896 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 573:ad23fe03a082 1897 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 573:ad23fe03a082 1898
mbed_official 573:ad23fe03a082 1899 /*!<Mailbox registers */
mbed_official 573:ad23fe03a082 1900 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 573:ad23fe03a082 1901 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 573:ad23fe03a082 1902 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 573:ad23fe03a082 1903 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 573:ad23fe03a082 1904 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 573:ad23fe03a082 1905 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 573:ad23fe03a082 1906
mbed_official 573:ad23fe03a082 1907 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 573:ad23fe03a082 1908 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 573:ad23fe03a082 1909 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 573:ad23fe03a082 1910 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 573:ad23fe03a082 1911
mbed_official 573:ad23fe03a082 1912 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 573:ad23fe03a082 1913 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 573:ad23fe03a082 1914 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 573:ad23fe03a082 1915 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 573:ad23fe03a082 1916 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 573:ad23fe03a082 1917
mbed_official 573:ad23fe03a082 1918 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 573:ad23fe03a082 1919 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 573:ad23fe03a082 1920 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 573:ad23fe03a082 1921 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 573:ad23fe03a082 1922 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 573:ad23fe03a082 1923
mbed_official 573:ad23fe03a082 1924 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 573:ad23fe03a082 1925 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 573:ad23fe03a082 1926 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 573:ad23fe03a082 1927 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 573:ad23fe03a082 1928 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 573:ad23fe03a082 1929 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 573:ad23fe03a082 1930
mbed_official 573:ad23fe03a082 1931 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 573:ad23fe03a082 1932 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 573:ad23fe03a082 1933 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 573:ad23fe03a082 1934 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 573:ad23fe03a082 1935
mbed_official 573:ad23fe03a082 1936 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 573:ad23fe03a082 1937 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 573:ad23fe03a082 1938 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 573:ad23fe03a082 1939 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 573:ad23fe03a082 1940 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 573:ad23fe03a082 1941
mbed_official 573:ad23fe03a082 1942 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 573:ad23fe03a082 1943 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 573:ad23fe03a082 1944 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 573:ad23fe03a082 1945 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 573:ad23fe03a082 1946 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 573:ad23fe03a082 1947
mbed_official 573:ad23fe03a082 1948 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 573:ad23fe03a082 1949 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 573:ad23fe03a082 1950 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 573:ad23fe03a082 1951 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 573:ad23fe03a082 1952 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 573:ad23fe03a082 1953 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 573:ad23fe03a082 1954
mbed_official 573:ad23fe03a082 1955 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 573:ad23fe03a082 1956 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 573:ad23fe03a082 1957 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 573:ad23fe03a082 1958 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 573:ad23fe03a082 1959
mbed_official 573:ad23fe03a082 1960 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 573:ad23fe03a082 1961 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 573:ad23fe03a082 1962 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 573:ad23fe03a082 1963 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 573:ad23fe03a082 1964 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 573:ad23fe03a082 1965
mbed_official 573:ad23fe03a082 1966 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 573:ad23fe03a082 1967 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 573:ad23fe03a082 1968 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 573:ad23fe03a082 1969 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 573:ad23fe03a082 1970 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 573:ad23fe03a082 1971
mbed_official 573:ad23fe03a082 1972 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 573:ad23fe03a082 1973 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 573:ad23fe03a082 1974 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 573:ad23fe03a082 1975 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 573:ad23fe03a082 1976 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 573:ad23fe03a082 1977
mbed_official 573:ad23fe03a082 1978 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 573:ad23fe03a082 1979 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 573:ad23fe03a082 1980 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 573:ad23fe03a082 1981 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 573:ad23fe03a082 1982
mbed_official 573:ad23fe03a082 1983 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 573:ad23fe03a082 1984 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 573:ad23fe03a082 1985 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 573:ad23fe03a082 1986 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 573:ad23fe03a082 1987 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 573:ad23fe03a082 1988
mbed_official 573:ad23fe03a082 1989 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 573:ad23fe03a082 1990 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 573:ad23fe03a082 1991 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 573:ad23fe03a082 1992 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 573:ad23fe03a082 1993 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 573:ad23fe03a082 1994
mbed_official 573:ad23fe03a082 1995 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 573:ad23fe03a082 1996 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 573:ad23fe03a082 1997 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 573:ad23fe03a082 1998 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 573:ad23fe03a082 1999 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 573:ad23fe03a082 2000
mbed_official 573:ad23fe03a082 2001 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 573:ad23fe03a082 2002 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 573:ad23fe03a082 2003 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 573:ad23fe03a082 2004 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 573:ad23fe03a082 2005
mbed_official 573:ad23fe03a082 2006 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 573:ad23fe03a082 2007 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 573:ad23fe03a082 2008 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 573:ad23fe03a082 2009 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 573:ad23fe03a082 2010 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 573:ad23fe03a082 2011
mbed_official 573:ad23fe03a082 2012 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 573:ad23fe03a082 2013 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 573:ad23fe03a082 2014 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 573:ad23fe03a082 2015 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 573:ad23fe03a082 2016 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 573:ad23fe03a082 2017
mbed_official 573:ad23fe03a082 2018 /*!<CAN filter registers */
mbed_official 573:ad23fe03a082 2019 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 573:ad23fe03a082 2020 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
mbed_official 573:ad23fe03a082 2021 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 573:ad23fe03a082 2022
mbed_official 573:ad23fe03a082 2023 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 573:ad23fe03a082 2024 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
mbed_official 573:ad23fe03a082 2025 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
mbed_official 573:ad23fe03a082 2026 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
mbed_official 573:ad23fe03a082 2027 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
mbed_official 573:ad23fe03a082 2028 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
mbed_official 573:ad23fe03a082 2029 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
mbed_official 573:ad23fe03a082 2030 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
mbed_official 573:ad23fe03a082 2031 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
mbed_official 573:ad23fe03a082 2032 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
mbed_official 573:ad23fe03a082 2033 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
mbed_official 573:ad23fe03a082 2034 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
mbed_official 573:ad23fe03a082 2035 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
mbed_official 573:ad23fe03a082 2036 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
mbed_official 573:ad23fe03a082 2037 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
mbed_official 573:ad23fe03a082 2038 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
mbed_official 573:ad23fe03a082 2039
mbed_official 573:ad23fe03a082 2040 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 573:ad23fe03a082 2041 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
mbed_official 573:ad23fe03a082 2042 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 573:ad23fe03a082 2043 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 573:ad23fe03a082 2044 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 573:ad23fe03a082 2045 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 573:ad23fe03a082 2046 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 573:ad23fe03a082 2047 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 573:ad23fe03a082 2048 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 573:ad23fe03a082 2049 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 573:ad23fe03a082 2050 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 573:ad23fe03a082 2051 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 573:ad23fe03a082 2052 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 573:ad23fe03a082 2053 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 573:ad23fe03a082 2054 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 573:ad23fe03a082 2055 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 573:ad23fe03a082 2056
mbed_official 573:ad23fe03a082 2057 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 573:ad23fe03a082 2058 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
mbed_official 573:ad23fe03a082 2059 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 573:ad23fe03a082 2060 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 573:ad23fe03a082 2061 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 573:ad23fe03a082 2062 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 573:ad23fe03a082 2063 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 573:ad23fe03a082 2064 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 573:ad23fe03a082 2065 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 573:ad23fe03a082 2066 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 573:ad23fe03a082 2067 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 573:ad23fe03a082 2068 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 573:ad23fe03a082 2069 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 573:ad23fe03a082 2070 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 573:ad23fe03a082 2071 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 573:ad23fe03a082 2072 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 573:ad23fe03a082 2073
mbed_official 573:ad23fe03a082 2074 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 573:ad23fe03a082 2075 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
mbed_official 573:ad23fe03a082 2076 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
mbed_official 573:ad23fe03a082 2077 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
mbed_official 573:ad23fe03a082 2078 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
mbed_official 573:ad23fe03a082 2079 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
mbed_official 573:ad23fe03a082 2080 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
mbed_official 573:ad23fe03a082 2081 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
mbed_official 573:ad23fe03a082 2082 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
mbed_official 573:ad23fe03a082 2083 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
mbed_official 573:ad23fe03a082 2084 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
mbed_official 573:ad23fe03a082 2085 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
mbed_official 573:ad23fe03a082 2086 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
mbed_official 573:ad23fe03a082 2087 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
mbed_official 573:ad23fe03a082 2088 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
mbed_official 573:ad23fe03a082 2089 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
mbed_official 573:ad23fe03a082 2090
mbed_official 573:ad23fe03a082 2091 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 573:ad23fe03a082 2092 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2093 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2094 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2095 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2096 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2097 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2098 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2099 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2100 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2101 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2102 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2103 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2104 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2105 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2106 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2107 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2108 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2109 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2110 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2111 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2112 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2113 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2114 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2115 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2116 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2117 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2118 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2119 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2120 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2121 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2122 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2123 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2124
mbed_official 573:ad23fe03a082 2125 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 573:ad23fe03a082 2126 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2127 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2128 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2129 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2130 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2131 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2132 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2133 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2134 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2135 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2136 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2137 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2138 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2139 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2140 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2141 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2142 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2143 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2144 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2145 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2146 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2147 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2148 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2149 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2150 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2151 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2152 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2153 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2154 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2155 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2156 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2157 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2158
mbed_official 573:ad23fe03a082 2159 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 573:ad23fe03a082 2160 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2161 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2162 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2163 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2164 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2165 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2166 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2167 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2168 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2169 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2170 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2171 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2172 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2173 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2174 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2175 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2176 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2177 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2178 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2179 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2180 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2181 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2182 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2183 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2184 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2185 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2186 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2187 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2188 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2189 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2190 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2191 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2192
mbed_official 573:ad23fe03a082 2193 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 573:ad23fe03a082 2194 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2195 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2196 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2197 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2198 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2199 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2200 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2201 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2202 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2203 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2204 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2205 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2206 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2207 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2208 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2209 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2210 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2211 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2212 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2213 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2214 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2215 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2216 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2217 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2218 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2219 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2220 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2221 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2222 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2223 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2224 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2225 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2226
mbed_official 573:ad23fe03a082 2227 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 573:ad23fe03a082 2228 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2229 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2230 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2231 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2232 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2233 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2234 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2235 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2236 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2237 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2238 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2239 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2240 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2241 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2242 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2243 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2244 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2245 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2246 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2247 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2248 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2249 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2250 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2251 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2252 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2253 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2254 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2255 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2256 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2257 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2258 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2259 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2260
mbed_official 573:ad23fe03a082 2261 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 573:ad23fe03a082 2262 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2263 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2264 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2265 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2266 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2267 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2268 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2269 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2270 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2271 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2272 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2273 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2274 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2275 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2276 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2277 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2278 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2279 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2280 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2281 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2282 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2283 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2284 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2285 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2286 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2287 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2288 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2289 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2290 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2291 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2292 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2293 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2294
mbed_official 573:ad23fe03a082 2295 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 573:ad23fe03a082 2296 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2297 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2298 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2299 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2300 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2301 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2302 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2303 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2304 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2305 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2306 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2307 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2308 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2309 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2310 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2311 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2312 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2313 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2314 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2315 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2316 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2317 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2318 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2319 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2320 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2321 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2322 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2323 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2324 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2325 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2326 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2327 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2328
mbed_official 573:ad23fe03a082 2329 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 573:ad23fe03a082 2330 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2331 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2332 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2333 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2334 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2335 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2336 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2337 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2338 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2339 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2340 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2341 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2342 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2343 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2344 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2345 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2346 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2347 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2348 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2349 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2350 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2351 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2352 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2353 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2354 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2355 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2356 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2357 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2358 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2359 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2360 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2361 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2362
mbed_official 573:ad23fe03a082 2363 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 573:ad23fe03a082 2364 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2365 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2366 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2367 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2368 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2369 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2370 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2371 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2372 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2373 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2374 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2375 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2376 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2377 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2378 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2379 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2380 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2381 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2382 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2383 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2384 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2385 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2386 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2387 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2388 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2389 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2390 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2391 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2392 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2393 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2394 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2395 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2396
mbed_official 573:ad23fe03a082 2397 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 573:ad23fe03a082 2398 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2399 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2400 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2401 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2402 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2403 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2404 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2405 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2406 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2407 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2408 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2409 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2410 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2411 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2412 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2413 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2414 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2415 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2416 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2417 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2418 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2419 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2420 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2421 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2422 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2423 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2424 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2425 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2426 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2427 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2428 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2429 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2430
mbed_official 573:ad23fe03a082 2431 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 573:ad23fe03a082 2432 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2433 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2434 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2435 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2436 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2437 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2438 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2439 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2440 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2441 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2442 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2443 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2444 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2445 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2446 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2447 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2448 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2449 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2450 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2451 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2452 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2453 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2454 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2455 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2456 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2457 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2458 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2459 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2460 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2461 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2462 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2463 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2464
mbed_official 573:ad23fe03a082 2465 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 573:ad23fe03a082 2466 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2467 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2468 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2469 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2470 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2471 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2472 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2473 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2474 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2475 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2476 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2477 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2478 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2479 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2480 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2481 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2482 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2483 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2484 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2485 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2486 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2487 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2488 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2489 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2490 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2491 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2492 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2493 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2494 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2495 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2496 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2497 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2498
mbed_official 573:ad23fe03a082 2499 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 573:ad23fe03a082 2500 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2501 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2502 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2503 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2504 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2505 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2506 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2507 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2508 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2509 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2510 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2511 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2512 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2513 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2514 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2515 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2516 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2517 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2518 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2519 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2520 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2521 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2522 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2523 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2524 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2525 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2526 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2527 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2528 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2529 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2530 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2531 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2532
mbed_official 573:ad23fe03a082 2533 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 573:ad23fe03a082 2534 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2535 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2536 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2537 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2538 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2539 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2540 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2541 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2542 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2543 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2544 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2545 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2546 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2547 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2548 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2549 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2550 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2551 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2552 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2553 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2554 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2555 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2556 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2557 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2558 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2559 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2560 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2561 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2562 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2563 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2564 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2565 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2566
mbed_official 573:ad23fe03a082 2567 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 573:ad23fe03a082 2568 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2569 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2570 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2571 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2572 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2573 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2574 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2575 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2576 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2577 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2578 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2579 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2580 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2581 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2582 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2583 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2584 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2585 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2586 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2587 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2588 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2589 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2590 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2591 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2592 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2593 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2594 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2595 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2596 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2597 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2598 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2599 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2600
mbed_official 573:ad23fe03a082 2601 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 573:ad23fe03a082 2602 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2603 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2604 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2605 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2606 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2607 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2608 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2609 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2610 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2611 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2612 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2613 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2614 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2615 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2616 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2617 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2618 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2619 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2620 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2621 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2622 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2623 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2624 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2625 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2626 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2627 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2628 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2629 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2630 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2631 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2632 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2633 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2634
mbed_official 573:ad23fe03a082 2635 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 573:ad23fe03a082 2636 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2637 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2638 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2639 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2640 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2641 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2642 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2643 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2644 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2645 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2646 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2647 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2648 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2649 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2650 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2651 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2652 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2653 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2654 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2655 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2656 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2657 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2658 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2659 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2660 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2661 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2662 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2663 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2664 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2665 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2666 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2667 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2668
mbed_official 573:ad23fe03a082 2669 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 573:ad23fe03a082 2670 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2671 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2672 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2673 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2674 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2675 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2676 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2677 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2678 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2679 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2680 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2681 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2682 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2683 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2684 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2685 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2686 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2687 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2688 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2689 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2690 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2691 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2692 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2693 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2694 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2695 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2696 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2697 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2698 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2699 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2700 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2701 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2702
mbed_official 573:ad23fe03a082 2703 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 573:ad23fe03a082 2704 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2705 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2706 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2707 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2708 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2709 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2710 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2711 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2712 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2713 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2714 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2715 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2716 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2717 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2718 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2719 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2720 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2721 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2722 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2723 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2724 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2725 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2726 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2727 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2728 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2729 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2730 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2731 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2732 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2733 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2734 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2735 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2736
mbed_official 573:ad23fe03a082 2737 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 573:ad23fe03a082 2738 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2739 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2740 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2741 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2742 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2743 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2744 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2745 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2746 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2747 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2748 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2749 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2750 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2751 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2752 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2753 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2754 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2755 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2756 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2757 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2758 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2759 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2760 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2761 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2762 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2763 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2764 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2765 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2766 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2767 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2768 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2769 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2770
mbed_official 573:ad23fe03a082 2771 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 573:ad23fe03a082 2772 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2773 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2774 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2775 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2776 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2777 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2778 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2779 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2780 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2781 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2782 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2783 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2784 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2785 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2786 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2787 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2788 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2789 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2790 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2791 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2792 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2793 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2794 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2795 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2796 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2797 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2798 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2799 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2800 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2801 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2802 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2803 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2804
mbed_official 573:ad23fe03a082 2805 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 573:ad23fe03a082 2806 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2807 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2808 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2809 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2810 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2811 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2812 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2813 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2814 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2815 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2816 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2817 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2818 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2819 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2820 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2821 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2822 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2823 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2824 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2825 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2826 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2827 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2828 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2829 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2830 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2831 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2832 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2833 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2834 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2835 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2836 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2837 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2838
mbed_official 573:ad23fe03a082 2839 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 573:ad23fe03a082 2840 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2841 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2842 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2843 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2844 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2845 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2846 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2847 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2848 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2849 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2850 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2851 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2852 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2853 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2854 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2855 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2856 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2857 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2858 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2859 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2860 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2861 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2862 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2863 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2864 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2865 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2866 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2867 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2868 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2869 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2870 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2871 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2872
mbed_official 573:ad23fe03a082 2873 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 573:ad23fe03a082 2874 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2875 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2876 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2877 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2878 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2879 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2880 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2881 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2882 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2883 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2884 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2885 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2886 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2887 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2888 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2889 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2890 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2891 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2892 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2893 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2894 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2895 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2896 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2897 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2898 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2899 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2900 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2901 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2902 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2903 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2904 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2905 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2906
mbed_official 573:ad23fe03a082 2907 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 573:ad23fe03a082 2908 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2909 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2910 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2911 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2912 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2913 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2914 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2915 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2916 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2917 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2918 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2919 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2920 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2921 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2922 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2923 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2924 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2925 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2926 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2927 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2928 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2929 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2930 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2931 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2932 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2933 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2934 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2935 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2936 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2937 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2938 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2939 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2940
mbed_official 573:ad23fe03a082 2941 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 573:ad23fe03a082 2942 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2943 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2944 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2945 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2946 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2947 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2948 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2949 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2950 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2951 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2952 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2953 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2954 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2955 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2956 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2957 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2958 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2959 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2960 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2961 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2962 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2963 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2964 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2965 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 2966 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 2967 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 2968 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 2969 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 2970 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 2971 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 2972 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 2973 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 2974
mbed_official 573:ad23fe03a082 2975 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 573:ad23fe03a082 2976 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 2977 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 2978 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 2979 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 2980 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 2981 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 2982 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 2983 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 2984 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 2985 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 2986 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 2987 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 2988 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 2989 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 2990 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 2991 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 2992 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 2993 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 2994 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 2995 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 2996 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 2997 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 2998 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 2999 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 3000 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 3001 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 3002 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 3003 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 3004 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 3005 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 3006 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 3007 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 3008
mbed_official 573:ad23fe03a082 3009 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 573:ad23fe03a082 3010 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 573:ad23fe03a082 3011 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 573:ad23fe03a082 3012 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 573:ad23fe03a082 3013 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 573:ad23fe03a082 3014 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 573:ad23fe03a082 3015 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 573:ad23fe03a082 3016 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 573:ad23fe03a082 3017 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 573:ad23fe03a082 3018 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 573:ad23fe03a082 3019 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 573:ad23fe03a082 3020 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 573:ad23fe03a082 3021 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 573:ad23fe03a082 3022 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 573:ad23fe03a082 3023 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 573:ad23fe03a082 3024 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 573:ad23fe03a082 3025 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 573:ad23fe03a082 3026 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 573:ad23fe03a082 3027 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 573:ad23fe03a082 3028 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 573:ad23fe03a082 3029 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 573:ad23fe03a082 3030 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 573:ad23fe03a082 3031 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 573:ad23fe03a082 3032 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 573:ad23fe03a082 3033 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 573:ad23fe03a082 3034 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 573:ad23fe03a082 3035 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 573:ad23fe03a082 3036 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 573:ad23fe03a082 3037 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 573:ad23fe03a082 3038 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 573:ad23fe03a082 3039 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 573:ad23fe03a082 3040 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 573:ad23fe03a082 3041 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 573:ad23fe03a082 3042
mbed_official 573:ad23fe03a082 3043 /******************************************************************************/
mbed_official 573:ad23fe03a082 3044 /* */
mbed_official 573:ad23fe03a082 3045 /* HDMI-CEC (CEC) */
mbed_official 573:ad23fe03a082 3046 /* */
mbed_official 573:ad23fe03a082 3047 /******************************************************************************/
mbed_official 573:ad23fe03a082 3048
mbed_official 573:ad23fe03a082 3049 /******************* Bit definition for CEC_CR register *********************/
mbed_official 573:ad23fe03a082 3050 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 573:ad23fe03a082 3051 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 573:ad23fe03a082 3052 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 573:ad23fe03a082 3053
mbed_official 573:ad23fe03a082 3054 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 573:ad23fe03a082 3055 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 573:ad23fe03a082 3056 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 573:ad23fe03a082 3057 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 573:ad23fe03a082 3058 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 573:ad23fe03a082 3059 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
mbed_official 573:ad23fe03a082 3060 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
mbed_official 573:ad23fe03a082 3061 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 573:ad23fe03a082 3062 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 573:ad23fe03a082 3063 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 573:ad23fe03a082 3064
mbed_official 573:ad23fe03a082 3065 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 573:ad23fe03a082 3066 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 573:ad23fe03a082 3067
mbed_official 573:ad23fe03a082 3068 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 573:ad23fe03a082 3069 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 573:ad23fe03a082 3070
mbed_official 573:ad23fe03a082 3071 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 573:ad23fe03a082 3072 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 573:ad23fe03a082 3073 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 573:ad23fe03a082 3074 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 573:ad23fe03a082 3075 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 573:ad23fe03a082 3076 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 573:ad23fe03a082 3077 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 573:ad23fe03a082 3078 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 573:ad23fe03a082 3079 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 573:ad23fe03a082 3080 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 573:ad23fe03a082 3081 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 573:ad23fe03a082 3082 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 573:ad23fe03a082 3083 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 573:ad23fe03a082 3084 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 573:ad23fe03a082 3085
mbed_official 573:ad23fe03a082 3086 /******************* Bit definition for CEC_IER register ********************/
mbed_official 573:ad23fe03a082 3087 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 573:ad23fe03a082 3088 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 573:ad23fe03a082 3089 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 573:ad23fe03a082 3090 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 573:ad23fe03a082 3091 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
mbed_official 573:ad23fe03a082 3092 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 573:ad23fe03a082 3093 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 573:ad23fe03a082 3094 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 573:ad23fe03a082 3095 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 573:ad23fe03a082 3096 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 573:ad23fe03a082 3097 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 573:ad23fe03a082 3098 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 573:ad23fe03a082 3099 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 573:ad23fe03a082 3100
mbed_official 573:ad23fe03a082 3101 /******************************************************************************/
mbed_official 573:ad23fe03a082 3102 /* */
mbed_official 573:ad23fe03a082 3103 /* CRC calculation unit */
mbed_official 573:ad23fe03a082 3104 /* */
mbed_official 573:ad23fe03a082 3105 /******************************************************************************/
mbed_official 573:ad23fe03a082 3106 /******************* Bit definition for CRC_DR register *********************/
mbed_official 573:ad23fe03a082 3107 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 573:ad23fe03a082 3108
mbed_official 573:ad23fe03a082 3109 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 573:ad23fe03a082 3110 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
mbed_official 573:ad23fe03a082 3111
mbed_official 573:ad23fe03a082 3112 /******************** Bit definition for CRC_CR register ********************/
mbed_official 573:ad23fe03a082 3113 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 573:ad23fe03a082 3114 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 573:ad23fe03a082 3115 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 573:ad23fe03a082 3116 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 573:ad23fe03a082 3117 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 573:ad23fe03a082 3118 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 3119 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 3120 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 573:ad23fe03a082 3121
mbed_official 573:ad23fe03a082 3122 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 573:ad23fe03a082 3123 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 573:ad23fe03a082 3124
mbed_official 573:ad23fe03a082 3125 /******************* Bit definition for CRC_POL register ********************/
mbed_official 573:ad23fe03a082 3126 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 573:ad23fe03a082 3127
mbed_official 573:ad23fe03a082 3128 /******************************************************************************/
mbed_official 573:ad23fe03a082 3129 /* */
mbed_official 573:ad23fe03a082 3130 /* Digital to Analog Converter */
mbed_official 573:ad23fe03a082 3131 /* */
mbed_official 573:ad23fe03a082 3132 /******************************************************************************/
mbed_official 573:ad23fe03a082 3133 /******************** Bit definition for DAC_CR register ********************/
mbed_official 573:ad23fe03a082 3134 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 573:ad23fe03a082 3135 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 573:ad23fe03a082 3136 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 573:ad23fe03a082 3137
mbed_official 573:ad23fe03a082 3138 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 573:ad23fe03a082 3139 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3140 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3141 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3142
mbed_official 573:ad23fe03a082 3143 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 573:ad23fe03a082 3144 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3145 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3146
mbed_official 573:ad23fe03a082 3147 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 573:ad23fe03a082 3148 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3149 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3150 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3151 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3152
mbed_official 573:ad23fe03a082 3153 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 573:ad23fe03a082 3154 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 573:ad23fe03a082 3155 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 573:ad23fe03a082 3156 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 573:ad23fe03a082 3157
mbed_official 573:ad23fe03a082 3158 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 573:ad23fe03a082 3159 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3160 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3161 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3162
mbed_official 573:ad23fe03a082 3163 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 573:ad23fe03a082 3164 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3165 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3166
mbed_official 573:ad23fe03a082 3167 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 573:ad23fe03a082 3168 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3169 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3170 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3171 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3172
mbed_official 573:ad23fe03a082 3173 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 573:ad23fe03a082 3174
mbed_official 573:ad23fe03a082 3175 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 573:ad23fe03a082 3176 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 573:ad23fe03a082 3177 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 573:ad23fe03a082 3178
mbed_official 573:ad23fe03a082 3179 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 573:ad23fe03a082 3180 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 573:ad23fe03a082 3181
mbed_official 573:ad23fe03a082 3182 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 573:ad23fe03a082 3183 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 573:ad23fe03a082 3184
mbed_official 573:ad23fe03a082 3185 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 573:ad23fe03a082 3186 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 573:ad23fe03a082 3187
mbed_official 573:ad23fe03a082 3188 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 573:ad23fe03a082 3189 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 573:ad23fe03a082 3190
mbed_official 573:ad23fe03a082 3191 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 573:ad23fe03a082 3192 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 573:ad23fe03a082 3193
mbed_official 573:ad23fe03a082 3194 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 573:ad23fe03a082 3195 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 573:ad23fe03a082 3196
mbed_official 573:ad23fe03a082 3197 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 573:ad23fe03a082 3198 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 573:ad23fe03a082 3199 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 573:ad23fe03a082 3200
mbed_official 573:ad23fe03a082 3201 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 573:ad23fe03a082 3202 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 573:ad23fe03a082 3203 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 573:ad23fe03a082 3204
mbed_official 573:ad23fe03a082 3205 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 573:ad23fe03a082 3206 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 573:ad23fe03a082 3207 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 573:ad23fe03a082 3208
mbed_official 573:ad23fe03a082 3209 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 573:ad23fe03a082 3210 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 573:ad23fe03a082 3211
mbed_official 573:ad23fe03a082 3212 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 573:ad23fe03a082 3213 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 573:ad23fe03a082 3214
mbed_official 573:ad23fe03a082 3215 /******************** Bit definition for DAC_SR register ********************/
mbed_official 573:ad23fe03a082 3216 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 573:ad23fe03a082 3217 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 573:ad23fe03a082 3218
mbed_official 573:ad23fe03a082 3219 /******************************************************************************/
mbed_official 573:ad23fe03a082 3220 /* */
mbed_official 573:ad23fe03a082 3221 /* Debug MCU */
mbed_official 573:ad23fe03a082 3222 /* */
mbed_official 573:ad23fe03a082 3223 /******************************************************************************/
mbed_official 573:ad23fe03a082 3224
mbed_official 573:ad23fe03a082 3225 /******************************************************************************/
mbed_official 573:ad23fe03a082 3226 /* */
mbed_official 573:ad23fe03a082 3227 /* DCMI */
mbed_official 573:ad23fe03a082 3228 /* */
mbed_official 573:ad23fe03a082 3229 /******************************************************************************/
mbed_official 573:ad23fe03a082 3230 /******************** Bits definition for DCMI_CR register ******************/
mbed_official 573:ad23fe03a082 3231 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3232 #define DCMI_CR_CM ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3233 #define DCMI_CR_CROP ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3234 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3235 #define DCMI_CR_ESS ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3236 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3237 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3238 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3239 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3240 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3241 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3242 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3243 #define DCMI_CR_CRE ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 3244 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 3245 #define DCMI_CR_BSM ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 3246 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3247 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 3248 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3249 #define DCMI_CR_LSM ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3250 #define DCMI_CR_OELS ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3251
mbed_official 573:ad23fe03a082 3252 /******************** Bits definition for DCMI_SR register ******************/
mbed_official 573:ad23fe03a082 3253 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3254 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3255 #define DCMI_SR_FNE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3256
mbed_official 573:ad23fe03a082 3257 /******************** Bits definition for DCMI_RISR register ****************/
mbed_official 573:ad23fe03a082 3258 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3259 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3260 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3261 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3262 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3263
mbed_official 573:ad23fe03a082 3264 /******************** Bits definition for DCMI_IER register *****************/
mbed_official 573:ad23fe03a082 3265 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3266 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3267 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3268 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3269 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3270
mbed_official 573:ad23fe03a082 3271 /******************** Bits definition for DCMI_MISR register ****************/
mbed_official 573:ad23fe03a082 3272 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3273 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3274 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3275 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3276 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3277
mbed_official 573:ad23fe03a082 3278 /******************** Bits definition for DCMI_ICR register *****************/
mbed_official 573:ad23fe03a082 3279 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3280 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3281 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3282 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3283 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3284
mbed_official 573:ad23fe03a082 3285 /******************************************************************************/
mbed_official 573:ad23fe03a082 3286 /* */
mbed_official 573:ad23fe03a082 3287 /* DMA Controller */
mbed_official 573:ad23fe03a082 3288 /* */
mbed_official 573:ad23fe03a082 3289 /******************************************************************************/
mbed_official 573:ad23fe03a082 3290 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 573:ad23fe03a082 3291 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 573:ad23fe03a082 3292 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3293 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 3294 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 3295 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 573:ad23fe03a082 3296 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 3297 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3298 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 573:ad23fe03a082 3299 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3300 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3301 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3302 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3303 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3304 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 3305 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3306 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 3307 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 3308 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 573:ad23fe03a082 3309 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 3310 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 3311 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 573:ad23fe03a082 3312 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3313 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 3314 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3315 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3316 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3317 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 3318 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3319 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3320 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3321 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3322 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3323 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3324 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3325 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3326
mbed_official 573:ad23fe03a082 3327 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 573:ad23fe03a082 3328 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 573:ad23fe03a082 3329 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3330 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3331 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3332 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3333 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3334 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3335 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3336 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3337 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3338 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3339 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3340 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3341 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 3342 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 3343 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 3344 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 3345
mbed_official 573:ad23fe03a082 3346 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 573:ad23fe03a082 3347 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3348 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 573:ad23fe03a082 3349 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3350 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3351 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3352 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3353 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 3354 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3355 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3356
mbed_official 573:ad23fe03a082 3357 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 573:ad23fe03a082 3358 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 3359 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 3360 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3361 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3362 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3363 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3364 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3365 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3366 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3367 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3368 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3369 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3370 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3371 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3372 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3373 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3374 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3375 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3376 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3377 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3378
mbed_official 573:ad23fe03a082 3379 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 573:ad23fe03a082 3380 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 3381 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 3382 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3383 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3384 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3385 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3386 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3387 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3388 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3389 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3390 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3391 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3392 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3393 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3394 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3395 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3396 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3397 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3398 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3399 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3400
mbed_official 573:ad23fe03a082 3401 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 573:ad23fe03a082 3402 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 3403 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 3404 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3405 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3406 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3407 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3408 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3409 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3410 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3411 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3412 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3413 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3414 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3415 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3416 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3417 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3418 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3419 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3420 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3421 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3422
mbed_official 573:ad23fe03a082 3423 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 573:ad23fe03a082 3424 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 3425 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 3426 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3427 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3428 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3429 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3430 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3431 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3432 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3433 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3434 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3435 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3436 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3437 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3438 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3439 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3440 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3441 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3442 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3443 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3444
mbed_official 573:ad23fe03a082 3445 /******************************************************************************/
mbed_official 573:ad23fe03a082 3446 /* */
mbed_official 573:ad23fe03a082 3447 /* AHB Master DMA2D Controller (DMA2D) */
mbed_official 573:ad23fe03a082 3448 /* */
mbed_official 573:ad23fe03a082 3449 /******************************************************************************/
mbed_official 573:ad23fe03a082 3450
mbed_official 573:ad23fe03a082 3451 /******************** Bit definition for DMA2D_CR register ******************/
mbed_official 573:ad23fe03a082 3452
mbed_official 573:ad23fe03a082 3453 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
mbed_official 573:ad23fe03a082 3454 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
mbed_official 573:ad23fe03a082 3455 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
mbed_official 573:ad23fe03a082 3456 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
mbed_official 573:ad23fe03a082 3457 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
mbed_official 573:ad23fe03a082 3458 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
mbed_official 573:ad23fe03a082 3459 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
mbed_official 573:ad23fe03a082 3460 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
mbed_official 573:ad23fe03a082 3461 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
mbed_official 573:ad23fe03a082 3462 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
mbed_official 573:ad23fe03a082 3463
mbed_official 573:ad23fe03a082 3464 /******************** Bit definition for DMA2D_ISR register *****************/
mbed_official 573:ad23fe03a082 3465
mbed_official 573:ad23fe03a082 3466 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3467 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
mbed_official 573:ad23fe03a082 3468 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
mbed_official 573:ad23fe03a082 3469 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3470 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
mbed_official 573:ad23fe03a082 3471 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3472
mbed_official 573:ad23fe03a082 3473 /******************** Bit definition for DMA2D_IFSR register ****************/
mbed_official 573:ad23fe03a082 3474
mbed_official 573:ad23fe03a082 3475 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3476 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
mbed_official 573:ad23fe03a082 3477 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
mbed_official 573:ad23fe03a082 3478 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3479 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
mbed_official 573:ad23fe03a082 3480 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
mbed_official 573:ad23fe03a082 3481
mbed_official 573:ad23fe03a082 3482 /******************** Bit definition for DMA2D_FGMAR register ***************/
mbed_official 573:ad23fe03a082 3483
mbed_official 573:ad23fe03a082 3484 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 573:ad23fe03a082 3485
mbed_official 573:ad23fe03a082 3486 /******************** Bit definition for DMA2D_FGOR register ****************/
mbed_official 573:ad23fe03a082 3487
mbed_official 573:ad23fe03a082 3488 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 573:ad23fe03a082 3489
mbed_official 573:ad23fe03a082 3490 /******************** Bit definition for DMA2D_BGMAR register ***************/
mbed_official 573:ad23fe03a082 3491
mbed_official 573:ad23fe03a082 3492 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 573:ad23fe03a082 3493
mbed_official 573:ad23fe03a082 3494 /******************** Bit definition for DMA2D_BGOR register ****************/
mbed_official 573:ad23fe03a082 3495
mbed_official 573:ad23fe03a082 3496 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 573:ad23fe03a082 3497
mbed_official 573:ad23fe03a082 3498 /******************** Bit definition for DMA2D_FGPFCCR register *************/
mbed_official 573:ad23fe03a082 3499
mbed_official 573:ad23fe03a082 3500 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
mbed_official 573:ad23fe03a082 3501 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
mbed_official 573:ad23fe03a082 3502 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
mbed_official 573:ad23fe03a082 3503 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
mbed_official 573:ad23fe03a082 3504 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
mbed_official 573:ad23fe03a082 3505 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
mbed_official 573:ad23fe03a082 3506
mbed_official 573:ad23fe03a082 3507 /******************** Bit definition for DMA2D_FGCOLR register **************/
mbed_official 573:ad23fe03a082 3508
mbed_official 573:ad23fe03a082 3509 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
mbed_official 573:ad23fe03a082 3510 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
mbed_official 573:ad23fe03a082 3511 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 573:ad23fe03a082 3512
mbed_official 573:ad23fe03a082 3513 /******************** Bit definition for DMA2D_BGPFCCR register *************/
mbed_official 573:ad23fe03a082 3514
mbed_official 573:ad23fe03a082 3515 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
mbed_official 573:ad23fe03a082 3516 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
mbed_official 573:ad23fe03a082 3517 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
mbed_official 573:ad23fe03a082 3518 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
mbed_official 573:ad23fe03a082 3519 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
mbed_official 573:ad23fe03a082 3520 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
mbed_official 573:ad23fe03a082 3521
mbed_official 573:ad23fe03a082 3522 /******************** Bit definition for DMA2D_BGCOLR register **************/
mbed_official 573:ad23fe03a082 3523
mbed_official 573:ad23fe03a082 3524 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
mbed_official 573:ad23fe03a082 3525 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
mbed_official 573:ad23fe03a082 3526 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 573:ad23fe03a082 3527
mbed_official 573:ad23fe03a082 3528 /******************** Bit definition for DMA2D_FGCMAR register **************/
mbed_official 573:ad23fe03a082 3529
mbed_official 573:ad23fe03a082 3530 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 573:ad23fe03a082 3531
mbed_official 573:ad23fe03a082 3532 /******************** Bit definition for DMA2D_BGCMAR register **************/
mbed_official 573:ad23fe03a082 3533
mbed_official 573:ad23fe03a082 3534 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 573:ad23fe03a082 3535
mbed_official 573:ad23fe03a082 3536 /******************** Bit definition for DMA2D_OPFCCR register **************/
mbed_official 573:ad23fe03a082 3537
mbed_official 573:ad23fe03a082 3538 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
mbed_official 573:ad23fe03a082 3539
mbed_official 573:ad23fe03a082 3540 /******************** Bit definition for DMA2D_OCOLR register ***************/
mbed_official 573:ad23fe03a082 3541
mbed_official 573:ad23fe03a082 3542 /*!<Mode_ARGB8888/RGB888 */
mbed_official 573:ad23fe03a082 3543
mbed_official 573:ad23fe03a082 3544 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
mbed_official 573:ad23fe03a082 3545 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
mbed_official 573:ad23fe03a082 3546 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 573:ad23fe03a082 3547 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
mbed_official 573:ad23fe03a082 3548
mbed_official 573:ad23fe03a082 3549 /*!<Mode_RGB565 */
mbed_official 573:ad23fe03a082 3550 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
mbed_official 573:ad23fe03a082 3551 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
mbed_official 573:ad23fe03a082 3552 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
mbed_official 573:ad23fe03a082 3553
mbed_official 573:ad23fe03a082 3554 /*!<Mode_ARGB1555 */
mbed_official 573:ad23fe03a082 3555 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
mbed_official 573:ad23fe03a082 3556 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
mbed_official 573:ad23fe03a082 3557 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
mbed_official 573:ad23fe03a082 3558 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
mbed_official 573:ad23fe03a082 3559
mbed_official 573:ad23fe03a082 3560 /*!<Mode_ARGB4444 */
mbed_official 573:ad23fe03a082 3561 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
mbed_official 573:ad23fe03a082 3562 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
mbed_official 573:ad23fe03a082 3563 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
mbed_official 573:ad23fe03a082 3564 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
mbed_official 573:ad23fe03a082 3565
mbed_official 573:ad23fe03a082 3566 /******************** Bit definition for DMA2D_OMAR register ****************/
mbed_official 573:ad23fe03a082 3567
mbed_official 573:ad23fe03a082 3568 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 573:ad23fe03a082 3569
mbed_official 573:ad23fe03a082 3570 /******************** Bit definition for DMA2D_OOR register *****************/
mbed_official 573:ad23fe03a082 3571
mbed_official 573:ad23fe03a082 3572 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 573:ad23fe03a082 3573
mbed_official 573:ad23fe03a082 3574 /******************** Bit definition for DMA2D_NLR register *****************/
mbed_official 573:ad23fe03a082 3575
mbed_official 573:ad23fe03a082 3576 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
mbed_official 573:ad23fe03a082 3577 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
mbed_official 573:ad23fe03a082 3578
mbed_official 573:ad23fe03a082 3579 /******************** Bit definition for DMA2D_LWR register *****************/
mbed_official 573:ad23fe03a082 3580
mbed_official 573:ad23fe03a082 3581 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
mbed_official 573:ad23fe03a082 3582
mbed_official 573:ad23fe03a082 3583 /******************** Bit definition for DMA2D_AMTCR register ***************/
mbed_official 573:ad23fe03a082 3584
mbed_official 573:ad23fe03a082 3585 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
mbed_official 573:ad23fe03a082 3586 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
mbed_official 573:ad23fe03a082 3587
mbed_official 573:ad23fe03a082 3588
mbed_official 573:ad23fe03a082 3589
mbed_official 573:ad23fe03a082 3590 /******************** Bit definition for DMA2D_FGCLUT register **************/
mbed_official 573:ad23fe03a082 3591
mbed_official 573:ad23fe03a082 3592 /******************** Bit definition for DMA2D_BGCLUT register **************/
mbed_official 573:ad23fe03a082 3593
mbed_official 573:ad23fe03a082 3594
mbed_official 573:ad23fe03a082 3595 /******************************************************************************/
mbed_official 573:ad23fe03a082 3596 /* */
mbed_official 573:ad23fe03a082 3597 /* External Interrupt/Event Controller */
mbed_official 573:ad23fe03a082 3598 /* */
mbed_official 573:ad23fe03a082 3599 /******************************************************************************/
mbed_official 573:ad23fe03a082 3600 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 573:ad23fe03a082 3601 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 573:ad23fe03a082 3602 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 573:ad23fe03a082 3603 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 573:ad23fe03a082 3604 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 573:ad23fe03a082 3605 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 573:ad23fe03a082 3606 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 573:ad23fe03a082 3607 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 573:ad23fe03a082 3608 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 573:ad23fe03a082 3609 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 573:ad23fe03a082 3610 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 573:ad23fe03a082 3611 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 573:ad23fe03a082 3612 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 573:ad23fe03a082 3613 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 573:ad23fe03a082 3614 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 573:ad23fe03a082 3615 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 573:ad23fe03a082 3616 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 573:ad23fe03a082 3617 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 573:ad23fe03a082 3618 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 573:ad23fe03a082 3619 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 573:ad23fe03a082 3620 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 573:ad23fe03a082 3621 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 573:ad23fe03a082 3622 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 573:ad23fe03a082 3623 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 573:ad23fe03a082 3624 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 573:ad23fe03a082 3625
mbed_official 573:ad23fe03a082 3626 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 573:ad23fe03a082 3627 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 573:ad23fe03a082 3628 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 573:ad23fe03a082 3629 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 573:ad23fe03a082 3630 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 573:ad23fe03a082 3631 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 573:ad23fe03a082 3632 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 573:ad23fe03a082 3633 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 573:ad23fe03a082 3634 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 573:ad23fe03a082 3635 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 573:ad23fe03a082 3636 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 573:ad23fe03a082 3637 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 573:ad23fe03a082 3638 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 573:ad23fe03a082 3639 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 573:ad23fe03a082 3640 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 573:ad23fe03a082 3641 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 573:ad23fe03a082 3642 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 573:ad23fe03a082 3643 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 573:ad23fe03a082 3644 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 573:ad23fe03a082 3645 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 573:ad23fe03a082 3646 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 573:ad23fe03a082 3647 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 573:ad23fe03a082 3648 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 573:ad23fe03a082 3649 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 573:ad23fe03a082 3650 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 573:ad23fe03a082 3651
mbed_official 573:ad23fe03a082 3652 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 573:ad23fe03a082 3653 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 573:ad23fe03a082 3654 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 573:ad23fe03a082 3655 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 573:ad23fe03a082 3656 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 573:ad23fe03a082 3657 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 573:ad23fe03a082 3658 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 573:ad23fe03a082 3659 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 573:ad23fe03a082 3660 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 573:ad23fe03a082 3661 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 573:ad23fe03a082 3662 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 573:ad23fe03a082 3663 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 573:ad23fe03a082 3664 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 573:ad23fe03a082 3665 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 573:ad23fe03a082 3666 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 573:ad23fe03a082 3667 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 573:ad23fe03a082 3668 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 573:ad23fe03a082 3669 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 573:ad23fe03a082 3670 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 573:ad23fe03a082 3671 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 573:ad23fe03a082 3672 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 573:ad23fe03a082 3673 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 573:ad23fe03a082 3674 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 573:ad23fe03a082 3675 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 573:ad23fe03a082 3676 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 573:ad23fe03a082 3677
mbed_official 573:ad23fe03a082 3678 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 573:ad23fe03a082 3679 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 573:ad23fe03a082 3680 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 573:ad23fe03a082 3681 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 573:ad23fe03a082 3682 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 573:ad23fe03a082 3683 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 573:ad23fe03a082 3684 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 573:ad23fe03a082 3685 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 573:ad23fe03a082 3686 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 573:ad23fe03a082 3687 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 573:ad23fe03a082 3688 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 573:ad23fe03a082 3689 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 573:ad23fe03a082 3690 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 573:ad23fe03a082 3691 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 573:ad23fe03a082 3692 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 573:ad23fe03a082 3693 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 573:ad23fe03a082 3694 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 573:ad23fe03a082 3695 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 573:ad23fe03a082 3696 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 573:ad23fe03a082 3697 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 573:ad23fe03a082 3698 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 573:ad23fe03a082 3699 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 573:ad23fe03a082 3700 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 573:ad23fe03a082 3701 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 573:ad23fe03a082 3702 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 573:ad23fe03a082 3703
mbed_official 573:ad23fe03a082 3704 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 573:ad23fe03a082 3705 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 573:ad23fe03a082 3706 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 573:ad23fe03a082 3707 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 573:ad23fe03a082 3708 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 573:ad23fe03a082 3709 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 573:ad23fe03a082 3710 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 573:ad23fe03a082 3711 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 573:ad23fe03a082 3712 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 573:ad23fe03a082 3713 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 573:ad23fe03a082 3714 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 573:ad23fe03a082 3715 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 573:ad23fe03a082 3716 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 573:ad23fe03a082 3717 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 573:ad23fe03a082 3718 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 573:ad23fe03a082 3719 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 573:ad23fe03a082 3720 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 573:ad23fe03a082 3721 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 573:ad23fe03a082 3722 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 573:ad23fe03a082 3723 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 573:ad23fe03a082 3724 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 573:ad23fe03a082 3725 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 573:ad23fe03a082 3726 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 573:ad23fe03a082 3727 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 573:ad23fe03a082 3728 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 573:ad23fe03a082 3729
mbed_official 573:ad23fe03a082 3730 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 573:ad23fe03a082 3731 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 573:ad23fe03a082 3732 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 573:ad23fe03a082 3733 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 573:ad23fe03a082 3734 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 573:ad23fe03a082 3735 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 573:ad23fe03a082 3736 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 573:ad23fe03a082 3737 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 573:ad23fe03a082 3738 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 573:ad23fe03a082 3739 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 573:ad23fe03a082 3740 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 573:ad23fe03a082 3741 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 573:ad23fe03a082 3742 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 573:ad23fe03a082 3743 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 573:ad23fe03a082 3744 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 573:ad23fe03a082 3745 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 573:ad23fe03a082 3746 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 573:ad23fe03a082 3747 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 573:ad23fe03a082 3748 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 573:ad23fe03a082 3749 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 573:ad23fe03a082 3750 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 573:ad23fe03a082 3751 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 573:ad23fe03a082 3752 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 573:ad23fe03a082 3753 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 573:ad23fe03a082 3754 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 573:ad23fe03a082 3755
mbed_official 573:ad23fe03a082 3756 /******************************************************************************/
mbed_official 573:ad23fe03a082 3757 /* */
mbed_official 573:ad23fe03a082 3758 /* FLASH */
mbed_official 573:ad23fe03a082 3759 /* */
mbed_official 573:ad23fe03a082 3760 /******************************************************************************/
mbed_official 573:ad23fe03a082 3761 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 573:ad23fe03a082 3762 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 3763 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 3764 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3765 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3766 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 3767 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3768 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 573:ad23fe03a082 3769 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 573:ad23fe03a082 3770 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 573:ad23fe03a082 3771 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3772 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
mbed_official 573:ad23fe03a082 3773 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
mbed_official 573:ad23fe03a082 3774 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
mbed_official 573:ad23fe03a082 3775 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 3776 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
mbed_official 573:ad23fe03a082 3777 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
mbed_official 573:ad23fe03a082 3778 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 3779 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3780 #define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3781 #define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3782
mbed_official 573:ad23fe03a082 3783 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 573:ad23fe03a082 3784 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3785 #define FLASH_SR_OPERR ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3786 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3787 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3788 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3789 #define FLASH_SR_ERSERR ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3790 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3791
mbed_official 573:ad23fe03a082 3792 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 573:ad23fe03a082 3793 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3794 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3795 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3796 #define FLASH_CR_SNB ((uint32_t)0x00000078)
mbed_official 573:ad23fe03a082 3797 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3798 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3799 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3800 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3801 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 3802 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3803 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3804 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3805 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 3806 #define FLASH_CR_ERRIE ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 3807 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 3808
mbed_official 573:ad23fe03a082 3809 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 573:ad23fe03a082 3810 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 3811 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 3812 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 3813 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 3814 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 3815 #define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 3816 #define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 3817 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 3818 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 3819 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 573:ad23fe03a082 3820 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 3821 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 3822 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 3823 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 3824 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 3825 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 3826 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 3827 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 3828 #define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
mbed_official 573:ad23fe03a082 3829 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 3830 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 3831 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 3832 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 3833 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 3834 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 3835 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 3836 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 3837 #define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 3838 #define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 3839
mbed_official 573:ad23fe03a082 3840 /******************* Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 573:ad23fe03a082 3841 #define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
mbed_official 573:ad23fe03a082 3842 #define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
mbed_official 573:ad23fe03a082 3843
mbed_official 573:ad23fe03a082 3844
mbed_official 573:ad23fe03a082 3845
mbed_official 573:ad23fe03a082 3846 /******************************************************************************/
mbed_official 573:ad23fe03a082 3847 /* */
mbed_official 573:ad23fe03a082 3848 /* Flexible Memory Controller */
mbed_official 573:ad23fe03a082 3849 /* */
mbed_official 573:ad23fe03a082 3850 /******************************************************************************/
mbed_official 573:ad23fe03a082 3851 /****************** Bit definition for FMC_BCR1 register *******************/
mbed_official 573:ad23fe03a082 3852 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 573:ad23fe03a082 3853 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 573:ad23fe03a082 3854
mbed_official 573:ad23fe03a082 3855 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 573:ad23fe03a082 3856 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3857 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3858
mbed_official 573:ad23fe03a082 3859 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 573:ad23fe03a082 3860 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3861 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3862
mbed_official 573:ad23fe03a082 3863 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 573:ad23fe03a082 3864 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 573:ad23fe03a082 3865 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 573:ad23fe03a082 3866 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 573:ad23fe03a082 3867 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 573:ad23fe03a082 3868 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 573:ad23fe03a082 3869 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 573:ad23fe03a082 3870 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 573:ad23fe03a082 3871 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 573:ad23fe03a082 3872 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
mbed_official 573:ad23fe03a082 3873 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3874 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3875 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3876 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 573:ad23fe03a082 3877 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
mbed_official 573:ad23fe03a082 3878 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
mbed_official 573:ad23fe03a082 3879
mbed_official 573:ad23fe03a082 3880 /****************** Bit definition for FMC_BCR2 register *******************/
mbed_official 573:ad23fe03a082 3881 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 573:ad23fe03a082 3882 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 573:ad23fe03a082 3883
mbed_official 573:ad23fe03a082 3884 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 573:ad23fe03a082 3885 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3886 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3887
mbed_official 573:ad23fe03a082 3888 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 573:ad23fe03a082 3889 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3890 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3891
mbed_official 573:ad23fe03a082 3892 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 573:ad23fe03a082 3893 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 573:ad23fe03a082 3894 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 573:ad23fe03a082 3895 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 573:ad23fe03a082 3896 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 573:ad23fe03a082 3897 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 573:ad23fe03a082 3898 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 573:ad23fe03a082 3899 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 573:ad23fe03a082 3900 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 573:ad23fe03a082 3901 #define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
mbed_official 573:ad23fe03a082 3902 #define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3903 #define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3904 #define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3905 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 573:ad23fe03a082 3906
mbed_official 573:ad23fe03a082 3907 /****************** Bit definition for FMC_BCR3 register *******************/
mbed_official 573:ad23fe03a082 3908 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 573:ad23fe03a082 3909 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 573:ad23fe03a082 3910
mbed_official 573:ad23fe03a082 3911 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 573:ad23fe03a082 3912 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3913 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3914
mbed_official 573:ad23fe03a082 3915 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 573:ad23fe03a082 3916 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3917 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3918
mbed_official 573:ad23fe03a082 3919 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 573:ad23fe03a082 3920 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 573:ad23fe03a082 3921 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 573:ad23fe03a082 3922 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 573:ad23fe03a082 3923 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 573:ad23fe03a082 3924 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 573:ad23fe03a082 3925 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 573:ad23fe03a082 3926 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 573:ad23fe03a082 3927 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 573:ad23fe03a082 3928 #define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
mbed_official 573:ad23fe03a082 3929 #define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3930 #define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3931 #define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3932 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 573:ad23fe03a082 3933
mbed_official 573:ad23fe03a082 3934 /****************** Bit definition for FMC_BCR4 register *******************/
mbed_official 573:ad23fe03a082 3935 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 573:ad23fe03a082 3936 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 573:ad23fe03a082 3937
mbed_official 573:ad23fe03a082 3938 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 573:ad23fe03a082 3939 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3940 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3941
mbed_official 573:ad23fe03a082 3942 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 573:ad23fe03a082 3943 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3944 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3945
mbed_official 573:ad23fe03a082 3946 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 573:ad23fe03a082 3947 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 573:ad23fe03a082 3948 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 573:ad23fe03a082 3949 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 573:ad23fe03a082 3950 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 573:ad23fe03a082 3951 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 573:ad23fe03a082 3952 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 573:ad23fe03a082 3953 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 573:ad23fe03a082 3954 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 573:ad23fe03a082 3955 #define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
mbed_official 573:ad23fe03a082 3956 #define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3957 #define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3958 #define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3959 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 573:ad23fe03a082 3960
mbed_official 573:ad23fe03a082 3961 /****************** Bit definition for FMC_BTR1 register ******************/
mbed_official 573:ad23fe03a082 3962 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 3963 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3964 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3965 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3966 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3967
mbed_official 573:ad23fe03a082 3968 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 3969 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3970 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3971 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3972 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3973
mbed_official 573:ad23fe03a082 3974 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 3975 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3976 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3977 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3978 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3979 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 3980 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 3981 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 3982 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 3983
mbed_official 573:ad23fe03a082 3984 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 3985 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3986 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3987 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3988 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3989
mbed_official 573:ad23fe03a082 3990 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 573:ad23fe03a082 3991 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3992 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3993 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 3994 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 3995
mbed_official 573:ad23fe03a082 3996 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 573:ad23fe03a082 3997 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 3998 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 3999 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4000 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4001
mbed_official 573:ad23fe03a082 4002 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4003 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4004 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4005
mbed_official 573:ad23fe03a082 4006 /****************** Bit definition for FMC_BTR2 register *******************/
mbed_official 573:ad23fe03a082 4007 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4008 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4009 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4010 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4011 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4012
mbed_official 573:ad23fe03a082 4013 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4014 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4015 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4016 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4017 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4018
mbed_official 573:ad23fe03a082 4019 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4020 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4021 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4022 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4023 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4024 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4025 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4026 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4027 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4028
mbed_official 573:ad23fe03a082 4029 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4030 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4031 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4032 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4033 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4034
mbed_official 573:ad23fe03a082 4035 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 573:ad23fe03a082 4036 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4037 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4038 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4039 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4040
mbed_official 573:ad23fe03a082 4041 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 573:ad23fe03a082 4042 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4043 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4044 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4045 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4046
mbed_official 573:ad23fe03a082 4047 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4048 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4049 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4050
mbed_official 573:ad23fe03a082 4051 /******************* Bit definition for FMC_BTR3 register *******************/
mbed_official 573:ad23fe03a082 4052 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4053 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4054 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4055 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4056 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4057
mbed_official 573:ad23fe03a082 4058 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4059 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4060 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4061 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4062 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4063
mbed_official 573:ad23fe03a082 4064 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4065 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4066 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4067 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4068 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4069 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4070 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4071 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4072 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4073
mbed_official 573:ad23fe03a082 4074 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4075 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4076 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4077 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4078 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4079
mbed_official 573:ad23fe03a082 4080 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 573:ad23fe03a082 4081 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4082 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4083 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4084 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4085
mbed_official 573:ad23fe03a082 4086 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 573:ad23fe03a082 4087 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4088 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4089 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4090 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4091
mbed_official 573:ad23fe03a082 4092 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4093 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4094 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4095
mbed_official 573:ad23fe03a082 4096 /****************** Bit definition for FMC_BTR4 register *******************/
mbed_official 573:ad23fe03a082 4097 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4098 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4099 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4100 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4101 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4102
mbed_official 573:ad23fe03a082 4103 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4104 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4105 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4106 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4107 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4108
mbed_official 573:ad23fe03a082 4109 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4110 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4111 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4112 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4113 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4114 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4115 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4116 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4117 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4118
mbed_official 573:ad23fe03a082 4119 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4120 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4121 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4122 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4123 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4124
mbed_official 573:ad23fe03a082 4125 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 573:ad23fe03a082 4126 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4127 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4128 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4129 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4130
mbed_official 573:ad23fe03a082 4131 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 573:ad23fe03a082 4132 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4133 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4134 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4135 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4136
mbed_official 573:ad23fe03a082 4137 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4138 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4139 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4140
mbed_official 573:ad23fe03a082 4141 /****************** Bit definition for FMC_BWTR1 register ******************/
mbed_official 573:ad23fe03a082 4142 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4143 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4144 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4145 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4146 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4147
mbed_official 573:ad23fe03a082 4148 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4149 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4150 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4151 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4152 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4153
mbed_official 573:ad23fe03a082 4154 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4155 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4156 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4157 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4158 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4159 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4160 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4161 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4162 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4163
mbed_official 573:ad23fe03a082 4164 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4165 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4166 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4167 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4168 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4169
mbed_official 573:ad23fe03a082 4170 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4171 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4172 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4173
mbed_official 573:ad23fe03a082 4174 /****************** Bit definition for FMC_BWTR2 register ******************/
mbed_official 573:ad23fe03a082 4175 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4176 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4177 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4178 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4179 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4180
mbed_official 573:ad23fe03a082 4181 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4182 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4183 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4184 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4185 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4186
mbed_official 573:ad23fe03a082 4187 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4188 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4189 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4190 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4191 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4192 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4193 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4194 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4195 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4196
mbed_official 573:ad23fe03a082 4197 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4198 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4199 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4200 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4201 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4202
mbed_official 573:ad23fe03a082 4203 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4204 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4205 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4206
mbed_official 573:ad23fe03a082 4207 /****************** Bit definition for FMC_BWTR3 register ******************/
mbed_official 573:ad23fe03a082 4208 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4209 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4210 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4211 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4212 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4213
mbed_official 573:ad23fe03a082 4214 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4215 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4216 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4217 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4218 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4219
mbed_official 573:ad23fe03a082 4220 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4221 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4222 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4223 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4224 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4225 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4226 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4227 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4228 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4229
mbed_official 573:ad23fe03a082 4230 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4231 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4232 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4233 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4234 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4235
mbed_official 573:ad23fe03a082 4236 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4237 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4238 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4239
mbed_official 573:ad23fe03a082 4240 /****************** Bit definition for FMC_BWTR4 register ******************/
mbed_official 573:ad23fe03a082 4241 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 573:ad23fe03a082 4242 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4243 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4244 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4245 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4246
mbed_official 573:ad23fe03a082 4247 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 573:ad23fe03a082 4248 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4249 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4250 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4251 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4252
mbed_official 573:ad23fe03a082 4253 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 573:ad23fe03a082 4254 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4255 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4256 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4257 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4258 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4259 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4260 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4261 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4262
mbed_official 573:ad23fe03a082 4263 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 573:ad23fe03a082 4264 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4265 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4266 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4267 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4268
mbed_official 573:ad23fe03a082 4269 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 573:ad23fe03a082 4270 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4271 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4272
mbed_official 573:ad23fe03a082 4273 /****************** Bit definition for FMC_PCR register *******************/
mbed_official 573:ad23fe03a082 4274 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 573:ad23fe03a082 4275 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 573:ad23fe03a082 4276 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 573:ad23fe03a082 4277
mbed_official 573:ad23fe03a082 4278 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 573:ad23fe03a082 4279 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4280 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4281
mbed_official 573:ad23fe03a082 4282 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 573:ad23fe03a082 4283
mbed_official 573:ad23fe03a082 4284 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 573:ad23fe03a082 4285 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4286 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4287 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4288 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4289
mbed_official 573:ad23fe03a082 4290 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 573:ad23fe03a082 4291 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4292 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4293 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4294 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4295
mbed_official 573:ad23fe03a082 4296 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 573:ad23fe03a082 4297 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4298 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4299 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4300
mbed_official 573:ad23fe03a082 4301 /******************* Bit definition for FMC_SR register *******************/
mbed_official 573:ad23fe03a082 4302 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 573:ad23fe03a082 4303 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 573:ad23fe03a082 4304 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 573:ad23fe03a082 4305 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 573:ad23fe03a082 4306 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 573:ad23fe03a082 4307 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 573:ad23fe03a082 4308 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 573:ad23fe03a082 4309
mbed_official 573:ad23fe03a082 4310 /****************** Bit definition for FMC_PMEM register ******************/
mbed_official 573:ad23fe03a082 4311 #define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
mbed_official 573:ad23fe03a082 4312 #define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4313 #define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4314 #define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4315 #define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4316 #define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4317 #define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4318 #define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4319 #define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4320
mbed_official 573:ad23fe03a082 4321 #define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
mbed_official 573:ad23fe03a082 4322 #define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4323 #define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4324 #define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4325 #define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4326 #define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4327 #define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4328 #define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4329 #define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4330
mbed_official 573:ad23fe03a082 4331 #define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
mbed_official 573:ad23fe03a082 4332 #define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4333 #define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4334 #define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4335 #define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4336 #define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4337 #define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4338 #define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4339 #define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4340
mbed_official 573:ad23fe03a082 4341 #define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
mbed_official 573:ad23fe03a082 4342 #define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4343 #define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4344 #define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4345 #define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4346 #define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4347 #define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4348 #define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4349 #define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4350
mbed_official 573:ad23fe03a082 4351 /****************** Bit definition for FMC_PATT register ******************/
mbed_official 573:ad23fe03a082 4352 #define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
mbed_official 573:ad23fe03a082 4353 #define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4354 #define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4355 #define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4356 #define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4357 #define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4358 #define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4359 #define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4360 #define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4361
mbed_official 573:ad23fe03a082 4362 #define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
mbed_official 573:ad23fe03a082 4363 #define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4364 #define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4365 #define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4366 #define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4367 #define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4368 #define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4369 #define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4370 #define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4371
mbed_official 573:ad23fe03a082 4372 #define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
mbed_official 573:ad23fe03a082 4373 #define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4374 #define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4375 #define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4376 #define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4377 #define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4378 #define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4379 #define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4380 #define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4381
mbed_official 573:ad23fe03a082 4382 #define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
mbed_official 573:ad23fe03a082 4383 #define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4384 #define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4385 #define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4386 #define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4387 #define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 4388 #define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 4389 #define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 4390 #define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 4391
mbed_official 573:ad23fe03a082 4392 /****************** Bit definition for FMC_ECCR register ******************/
mbed_official 573:ad23fe03a082 4393 #define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 573:ad23fe03a082 4394
mbed_official 573:ad23fe03a082 4395 /****************** Bit definition for FMC_SDCR1 register ******************/
mbed_official 573:ad23fe03a082 4396 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 573:ad23fe03a082 4397 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4398 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4399
mbed_official 573:ad23fe03a082 4400 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 573:ad23fe03a082 4401 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4402 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4403
mbed_official 573:ad23fe03a082 4404 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 573:ad23fe03a082 4405 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4406 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4407
mbed_official 573:ad23fe03a082 4408 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 573:ad23fe03a082 4409
mbed_official 573:ad23fe03a082 4410 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 573:ad23fe03a082 4411 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4412 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4413
mbed_official 573:ad23fe03a082 4414 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 573:ad23fe03a082 4415
mbed_official 573:ad23fe03a082 4416 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
mbed_official 573:ad23fe03a082 4417 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4418 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4419
mbed_official 573:ad23fe03a082 4420 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 573:ad23fe03a082 4421
mbed_official 573:ad23fe03a082 4422 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
mbed_official 573:ad23fe03a082 4423 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4424 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4425
mbed_official 573:ad23fe03a082 4426 /****************** Bit definition for FMC_SDCR2 register ******************/
mbed_official 573:ad23fe03a082 4427 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 573:ad23fe03a082 4428 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4429 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4430
mbed_official 573:ad23fe03a082 4431 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 573:ad23fe03a082 4432 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4433 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4434
mbed_official 573:ad23fe03a082 4435 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 573:ad23fe03a082 4436 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4437 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4438
mbed_official 573:ad23fe03a082 4439 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 573:ad23fe03a082 4440
mbed_official 573:ad23fe03a082 4441 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 573:ad23fe03a082 4442 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4443 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4444
mbed_official 573:ad23fe03a082 4445 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 573:ad23fe03a082 4446
mbed_official 573:ad23fe03a082 4447 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
mbed_official 573:ad23fe03a082 4448 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4449 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4450
mbed_official 573:ad23fe03a082 4451 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 573:ad23fe03a082 4452
mbed_official 573:ad23fe03a082 4453 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
mbed_official 573:ad23fe03a082 4454 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4455 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4456
mbed_official 573:ad23fe03a082 4457 /****************** Bit definition for FMC_SDTR1 register ******************/
mbed_official 573:ad23fe03a082 4458 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 573:ad23fe03a082 4459 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4460 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4461 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4462 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4463
mbed_official 573:ad23fe03a082 4464 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 573:ad23fe03a082 4465 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4466 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4467 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4468 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4469
mbed_official 573:ad23fe03a082 4470 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 573:ad23fe03a082 4471 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4472 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4473 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4474 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4475
mbed_official 573:ad23fe03a082 4476 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 573:ad23fe03a082 4477 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4478 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4479 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4480
mbed_official 573:ad23fe03a082 4481 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 573:ad23fe03a082 4482 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4483 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4484 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4485
mbed_official 573:ad23fe03a082 4486 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 573:ad23fe03a082 4487 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4488 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4489 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4490
mbed_official 573:ad23fe03a082 4491 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 573:ad23fe03a082 4492 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4493 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4494 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4495
mbed_official 573:ad23fe03a082 4496 /****************** Bit definition for FMC_SDTR2 register ******************/
mbed_official 573:ad23fe03a082 4497 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 573:ad23fe03a082 4498 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4499 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4500 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4501 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4502
mbed_official 573:ad23fe03a082 4503 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 573:ad23fe03a082 4504 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4505 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4506 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4507 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4508
mbed_official 573:ad23fe03a082 4509 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 573:ad23fe03a082 4510 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4511 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4512 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4513 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4514
mbed_official 573:ad23fe03a082 4515 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 573:ad23fe03a082 4516 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4517 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4518 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4519
mbed_official 573:ad23fe03a082 4520 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 573:ad23fe03a082 4521 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4522 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4523 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4524
mbed_official 573:ad23fe03a082 4525 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 573:ad23fe03a082 4526 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4527 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4528 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4529
mbed_official 573:ad23fe03a082 4530 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 573:ad23fe03a082 4531 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4532 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4533 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4534
mbed_official 573:ad23fe03a082 4535 /****************** Bit definition for FMC_SDCMR register ******************/
mbed_official 573:ad23fe03a082 4536 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
mbed_official 573:ad23fe03a082 4537 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4538 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4539 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4540
mbed_official 573:ad23fe03a082 4541 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
mbed_official 573:ad23fe03a082 4542
mbed_official 573:ad23fe03a082 4543 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
mbed_official 573:ad23fe03a082 4544
mbed_official 573:ad23fe03a082 4545 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
mbed_official 573:ad23fe03a082 4546 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4547 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4548 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 4549 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 4550
mbed_official 573:ad23fe03a082 4551 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
mbed_official 573:ad23fe03a082 4552
mbed_official 573:ad23fe03a082 4553 /****************** Bit definition for FMC_SDRTR register ******************/
mbed_official 573:ad23fe03a082 4554 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
mbed_official 573:ad23fe03a082 4555
mbed_official 573:ad23fe03a082 4556 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
mbed_official 573:ad23fe03a082 4557
mbed_official 573:ad23fe03a082 4558 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
mbed_official 573:ad23fe03a082 4559
mbed_official 573:ad23fe03a082 4560 /****************** Bit definition for FMC_SDSR register ******************/
mbed_official 573:ad23fe03a082 4561 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
mbed_official 573:ad23fe03a082 4562
mbed_official 573:ad23fe03a082 4563 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
mbed_official 573:ad23fe03a082 4564 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4565 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4566
mbed_official 573:ad23fe03a082 4567 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
mbed_official 573:ad23fe03a082 4568 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 4569 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 4570
mbed_official 573:ad23fe03a082 4571 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
mbed_official 573:ad23fe03a082 4572
mbed_official 573:ad23fe03a082 4573 /******************************************************************************/
mbed_official 573:ad23fe03a082 4574 /* */
mbed_official 573:ad23fe03a082 4575 /* General Purpose I/O */
mbed_official 573:ad23fe03a082 4576 /* */
mbed_official 573:ad23fe03a082 4577 /******************************************************************************/
mbed_official 573:ad23fe03a082 4578 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 573:ad23fe03a082 4579 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 4580 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4581 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4582
mbed_official 573:ad23fe03a082 4583 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 4584 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4585 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4586
mbed_official 573:ad23fe03a082 4587 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 4588 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4589 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4590
mbed_official 573:ad23fe03a082 4591 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 4592 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4593 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4594
mbed_official 573:ad23fe03a082 4595 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 4596 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4597 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4598
mbed_official 573:ad23fe03a082 4599 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 573:ad23fe03a082 4600 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4601 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4602
mbed_official 573:ad23fe03a082 4603 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 573:ad23fe03a082 4604 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4605 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4606
mbed_official 573:ad23fe03a082 4607 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 573:ad23fe03a082 4608 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4609 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4610
mbed_official 573:ad23fe03a082 4611 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 4612 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 4613 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 4614
mbed_official 573:ad23fe03a082 4615 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 573:ad23fe03a082 4616 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 4617 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 4618
mbed_official 573:ad23fe03a082 4619 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 4620 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 4621 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 4622
mbed_official 573:ad23fe03a082 4623 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 573:ad23fe03a082 4624 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 4625 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 4626
mbed_official 573:ad23fe03a082 4627 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 573:ad23fe03a082 4628 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 4629 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 4630
mbed_official 573:ad23fe03a082 4631 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 573:ad23fe03a082 4632 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 4633 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 4634
mbed_official 573:ad23fe03a082 4635 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 573:ad23fe03a082 4636 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 4637 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 4638
mbed_official 573:ad23fe03a082 4639 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 573:ad23fe03a082 4640 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 4641 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 4642
mbed_official 573:ad23fe03a082 4643 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 573:ad23fe03a082 4644 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4645 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4646 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4647 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4648 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4649 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4650 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4651 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4652 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4653 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4654 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4655 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4656 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4657 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4658 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4659 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4660
mbed_official 573:ad23fe03a082 4661 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 573:ad23fe03a082 4662 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 4663 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4664 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4665
mbed_official 573:ad23fe03a082 4666 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 4667 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4668 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4669
mbed_official 573:ad23fe03a082 4670 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 4671 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4672 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4673
mbed_official 573:ad23fe03a082 4674 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 4675 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4676 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4677
mbed_official 573:ad23fe03a082 4678 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 4679 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4680 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4681
mbed_official 573:ad23fe03a082 4682 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 573:ad23fe03a082 4683 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4684 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4685
mbed_official 573:ad23fe03a082 4686 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 573:ad23fe03a082 4687 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4688 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4689
mbed_official 573:ad23fe03a082 4690 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 573:ad23fe03a082 4691 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4692 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4693
mbed_official 573:ad23fe03a082 4694 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 4695 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 4696 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 4697
mbed_official 573:ad23fe03a082 4698 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 573:ad23fe03a082 4699 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 4700 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 4701
mbed_official 573:ad23fe03a082 4702 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 4703 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 4704 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 4705
mbed_official 573:ad23fe03a082 4706 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 573:ad23fe03a082 4707 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 4708 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 4709
mbed_official 573:ad23fe03a082 4710 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 573:ad23fe03a082 4711 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 4712 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 4713
mbed_official 573:ad23fe03a082 4714 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 573:ad23fe03a082 4715 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 4716 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 4717
mbed_official 573:ad23fe03a082 4718 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 573:ad23fe03a082 4719 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 4720 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 4721
mbed_official 573:ad23fe03a082 4722 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 573:ad23fe03a082 4723 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 4724 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 4725
mbed_official 573:ad23fe03a082 4726 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 573:ad23fe03a082 4727 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 4728 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4729 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4730
mbed_official 573:ad23fe03a082 4731 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 4732 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4733 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4734
mbed_official 573:ad23fe03a082 4735 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 4736 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4737 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4738
mbed_official 573:ad23fe03a082 4739 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 4740 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4741 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4742
mbed_official 573:ad23fe03a082 4743 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 4744 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4745 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4746
mbed_official 573:ad23fe03a082 4747 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 573:ad23fe03a082 4748 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4749 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4750
mbed_official 573:ad23fe03a082 4751 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 573:ad23fe03a082 4752 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4753 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4754
mbed_official 573:ad23fe03a082 4755 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 573:ad23fe03a082 4756 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4757 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4758
mbed_official 573:ad23fe03a082 4759 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 4760 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 4761 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 4762
mbed_official 573:ad23fe03a082 4763 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 573:ad23fe03a082 4764 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 4765 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 4766
mbed_official 573:ad23fe03a082 4767 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 4768 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 4769 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 4770
mbed_official 573:ad23fe03a082 4771 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 573:ad23fe03a082 4772 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 4773 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 4774
mbed_official 573:ad23fe03a082 4775 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 573:ad23fe03a082 4776 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 4777 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 4778
mbed_official 573:ad23fe03a082 4779 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 573:ad23fe03a082 4780 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 4781 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 4782
mbed_official 573:ad23fe03a082 4783 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 573:ad23fe03a082 4784 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 4785 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 4786
mbed_official 573:ad23fe03a082 4787 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 573:ad23fe03a082 4788 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 4789 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 4790
mbed_official 573:ad23fe03a082 4791 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 573:ad23fe03a082 4792 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4793 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4794 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4795 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4796 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4797 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4798 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4799 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4800 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4801 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4802 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4803 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4804 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4805 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4806 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4807 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4808
mbed_official 573:ad23fe03a082 4809 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 573:ad23fe03a082 4810 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4811 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4812 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4813 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4814 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4815 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4816 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4817 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4818 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4819 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4820 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4821 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4822 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4823 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4824 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4825 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4826
mbed_official 573:ad23fe03a082 4827 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 573:ad23fe03a082 4828 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4829 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4830 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4831 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4832 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4833 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4834 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4835 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4836 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4837 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4838 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4839 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4840 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4841 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4842 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4843 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4844 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 4845 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 4846 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 4847 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 4848 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 4849 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 4850 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 4851 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 4852 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 4853 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 4854 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 4855 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 4856 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 4857 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 4858 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 4859 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 4860
mbed_official 573:ad23fe03a082 4861 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 573:ad23fe03a082 4862 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 4863 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 4864 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 4865 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 4866 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 4867 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 4868 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 4869 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 4870 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 4871 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 4872 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 4873 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 4874 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 4875 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 4876 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 4877 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 4878 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 4879
mbed_official 573:ad23fe03a082 4880 /******************************************************************************/
mbed_official 573:ad23fe03a082 4881 /* */
mbed_official 573:ad23fe03a082 4882 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 573:ad23fe03a082 4883 /* */
mbed_official 573:ad23fe03a082 4884 /******************************************************************************/
mbed_official 573:ad23fe03a082 4885 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 573:ad23fe03a082 4886 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 573:ad23fe03a082 4887 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 573:ad23fe03a082 4888 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 573:ad23fe03a082 4889 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 573:ad23fe03a082 4890 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 573:ad23fe03a082 4891 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 573:ad23fe03a082 4892 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 573:ad23fe03a082 4893 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 573:ad23fe03a082 4894 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 573:ad23fe03a082 4895 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 573:ad23fe03a082 4896 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 573:ad23fe03a082 4897 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 573:ad23fe03a082 4898 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 573:ad23fe03a082 4899 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 573:ad23fe03a082 4900 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 573:ad23fe03a082 4901 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 573:ad23fe03a082 4902 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 573:ad23fe03a082 4903 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 573:ad23fe03a082 4904 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 573:ad23fe03a082 4905 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 573:ad23fe03a082 4906 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 573:ad23fe03a082 4907
mbed_official 573:ad23fe03a082 4908 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 573:ad23fe03a082 4909 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 573:ad23fe03a082 4910 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 573:ad23fe03a082 4911 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 573:ad23fe03a082 4912 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 573:ad23fe03a082 4913 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 573:ad23fe03a082 4914 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 573:ad23fe03a082 4915 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 573:ad23fe03a082 4916 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 573:ad23fe03a082 4917 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 573:ad23fe03a082 4918 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 573:ad23fe03a082 4919 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 573:ad23fe03a082 4920
mbed_official 573:ad23fe03a082 4921 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 573:ad23fe03a082 4922 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 573:ad23fe03a082 4923 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 573:ad23fe03a082 4924 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 573:ad23fe03a082 4925
mbed_official 573:ad23fe03a082 4926 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 573:ad23fe03a082 4927 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 573:ad23fe03a082 4928 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 610:813dcc80987e 4929 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
mbed_official 610:813dcc80987e 4930 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
mbed_official 610:813dcc80987e 4931 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
mbed_official 610:813dcc80987e 4932 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
mbed_official 610:813dcc80987e 4933 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
mbed_official 610:813dcc80987e 4934 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
mbed_official 610:813dcc80987e 4935 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
mbed_official 610:813dcc80987e 4936 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
mbed_official 573:ad23fe03a082 4937 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 573:ad23fe03a082 4938
mbed_official 573:ad23fe03a082 4939 /******************* Bit definition for I2C_TIMINGR register *******************/
mbed_official 573:ad23fe03a082 4940 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 573:ad23fe03a082 4941 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 573:ad23fe03a082 4942 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 573:ad23fe03a082 4943 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 573:ad23fe03a082 4944 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 573:ad23fe03a082 4945
mbed_official 573:ad23fe03a082 4946 /******************* Bit definition for I2C_TIMEOUTR register *******************/
mbed_official 573:ad23fe03a082 4947 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 573:ad23fe03a082 4948 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 573:ad23fe03a082 4949 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 573:ad23fe03a082 4950 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
mbed_official 573:ad23fe03a082 4951 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 573:ad23fe03a082 4952
mbed_official 573:ad23fe03a082 4953 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 573:ad23fe03a082 4954 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 573:ad23fe03a082 4955 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 573:ad23fe03a082 4956 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 573:ad23fe03a082 4957 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
mbed_official 573:ad23fe03a082 4958 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 573:ad23fe03a082 4959 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 573:ad23fe03a082 4960 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 573:ad23fe03a082 4961 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 573:ad23fe03a082 4962 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 573:ad23fe03a082 4963 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 573:ad23fe03a082 4964 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 573:ad23fe03a082 4965 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 573:ad23fe03a082 4966 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 573:ad23fe03a082 4967 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 573:ad23fe03a082 4968 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 573:ad23fe03a082 4969 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 573:ad23fe03a082 4970 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 573:ad23fe03a082 4971
mbed_official 573:ad23fe03a082 4972 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 573:ad23fe03a082 4973 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 573:ad23fe03a082 4974 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 573:ad23fe03a082 4975 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 573:ad23fe03a082 4976 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 573:ad23fe03a082 4977 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 573:ad23fe03a082 4978 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 573:ad23fe03a082 4979 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 573:ad23fe03a082 4980 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 573:ad23fe03a082 4981 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 573:ad23fe03a082 4982
mbed_official 573:ad23fe03a082 4983 /****************** Bit definition for I2C_PECR register *********************/
mbed_official 573:ad23fe03a082 4984 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 573:ad23fe03a082 4985
mbed_official 573:ad23fe03a082 4986 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 573:ad23fe03a082 4987 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 573:ad23fe03a082 4988
mbed_official 573:ad23fe03a082 4989 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 573:ad23fe03a082 4990 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 573:ad23fe03a082 4991
mbed_official 573:ad23fe03a082 4992
mbed_official 573:ad23fe03a082 4993 /******************************************************************************/
mbed_official 573:ad23fe03a082 4994 /* */
mbed_official 573:ad23fe03a082 4995 /* Independent WATCHDOG */
mbed_official 573:ad23fe03a082 4996 /* */
mbed_official 573:ad23fe03a082 4997 /******************************************************************************/
mbed_official 573:ad23fe03a082 4998 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 573:ad23fe03a082 4999 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 573:ad23fe03a082 5000
mbed_official 573:ad23fe03a082 5001 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 573:ad23fe03a082 5002 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 573:ad23fe03a082 5003 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 5004 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 5005 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 5006
mbed_official 573:ad23fe03a082 5007 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 573:ad23fe03a082 5008 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 573:ad23fe03a082 5009
mbed_official 573:ad23fe03a082 5010 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 573:ad23fe03a082 5011 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 573:ad23fe03a082 5012 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 573:ad23fe03a082 5013 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
mbed_official 573:ad23fe03a082 5014
mbed_official 573:ad23fe03a082 5015 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 573:ad23fe03a082 5016 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 573:ad23fe03a082 5017
mbed_official 573:ad23fe03a082 5018 /******************************************************************************/
mbed_official 573:ad23fe03a082 5019 /* */
mbed_official 573:ad23fe03a082 5020 /* LCD-TFT Display Controller (LTDC) */
mbed_official 573:ad23fe03a082 5021 /* */
mbed_official 573:ad23fe03a082 5022 /******************************************************************************/
mbed_official 573:ad23fe03a082 5023
mbed_official 573:ad23fe03a082 5024 /******************** Bit definition for LTDC_SSCR register *****************/
mbed_official 573:ad23fe03a082 5025
mbed_official 573:ad23fe03a082 5026 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
mbed_official 573:ad23fe03a082 5027 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
mbed_official 573:ad23fe03a082 5028
mbed_official 573:ad23fe03a082 5029 /******************** Bit definition for LTDC_BPCR register *****************/
mbed_official 573:ad23fe03a082 5030
mbed_official 573:ad23fe03a082 5031 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
mbed_official 573:ad23fe03a082 5032 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
mbed_official 573:ad23fe03a082 5033
mbed_official 573:ad23fe03a082 5034 /******************** Bit definition for LTDC_AWCR register *****************/
mbed_official 573:ad23fe03a082 5035
mbed_official 573:ad23fe03a082 5036 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
mbed_official 573:ad23fe03a082 5037 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
mbed_official 573:ad23fe03a082 5038
mbed_official 573:ad23fe03a082 5039 /******************** Bit definition for LTDC_TWCR register *****************/
mbed_official 573:ad23fe03a082 5040
mbed_official 573:ad23fe03a082 5041 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
mbed_official 573:ad23fe03a082 5042 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
mbed_official 573:ad23fe03a082 5043
mbed_official 573:ad23fe03a082 5044 /******************** Bit definition for LTDC_GCR register ******************/
mbed_official 573:ad23fe03a082 5045
mbed_official 573:ad23fe03a082 5046 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
mbed_official 573:ad23fe03a082 5047 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
mbed_official 573:ad23fe03a082 5048 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
mbed_official 573:ad23fe03a082 5049 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
mbed_official 573:ad23fe03a082 5050 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
mbed_official 573:ad23fe03a082 5051 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
mbed_official 573:ad23fe03a082 5052 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
mbed_official 573:ad23fe03a082 5053 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
mbed_official 573:ad23fe03a082 5054 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
mbed_official 573:ad23fe03a082 5055
mbed_official 573:ad23fe03a082 5056 /******************** Bit definition for LTDC_SRCR register *****************/
mbed_official 573:ad23fe03a082 5057
mbed_official 573:ad23fe03a082 5058 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
mbed_official 573:ad23fe03a082 5059 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
mbed_official 573:ad23fe03a082 5060
mbed_official 573:ad23fe03a082 5061 /******************** Bit definition for LTDC_BCCR register *****************/
mbed_official 573:ad23fe03a082 5062
mbed_official 573:ad23fe03a082 5063 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
mbed_official 573:ad23fe03a082 5064 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
mbed_official 573:ad23fe03a082 5065 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
mbed_official 573:ad23fe03a082 5066
mbed_official 573:ad23fe03a082 5067 /******************** Bit definition for LTDC_IER register ******************/
mbed_official 573:ad23fe03a082 5068
mbed_official 573:ad23fe03a082 5069 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
mbed_official 573:ad23fe03a082 5070 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
mbed_official 573:ad23fe03a082 5071 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
mbed_official 573:ad23fe03a082 5072 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
mbed_official 573:ad23fe03a082 5073
mbed_official 573:ad23fe03a082 5074 /******************** Bit definition for LTDC_ISR register ******************/
mbed_official 573:ad23fe03a082 5075
mbed_official 573:ad23fe03a082 5076 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
mbed_official 573:ad23fe03a082 5077 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
mbed_official 573:ad23fe03a082 5078 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
mbed_official 573:ad23fe03a082 5079 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
mbed_official 573:ad23fe03a082 5080
mbed_official 573:ad23fe03a082 5081 /******************** Bit definition for LTDC_ICR register ******************/
mbed_official 573:ad23fe03a082 5082
mbed_official 573:ad23fe03a082 5083 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
mbed_official 573:ad23fe03a082 5084 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
mbed_official 573:ad23fe03a082 5085 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
mbed_official 573:ad23fe03a082 5086 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
mbed_official 573:ad23fe03a082 5087
mbed_official 573:ad23fe03a082 5088 /******************** Bit definition for LTDC_LIPCR register ****************/
mbed_official 573:ad23fe03a082 5089
mbed_official 573:ad23fe03a082 5090 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
mbed_official 573:ad23fe03a082 5091
mbed_official 573:ad23fe03a082 5092 /******************** Bit definition for LTDC_CPSR register *****************/
mbed_official 573:ad23fe03a082 5093
mbed_official 573:ad23fe03a082 5094 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
mbed_official 573:ad23fe03a082 5095 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
mbed_official 573:ad23fe03a082 5096
mbed_official 573:ad23fe03a082 5097 /******************** Bit definition for LTDC_CDSR register *****************/
mbed_official 573:ad23fe03a082 5098
mbed_official 573:ad23fe03a082 5099 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
mbed_official 573:ad23fe03a082 5100 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
mbed_official 573:ad23fe03a082 5101 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
mbed_official 573:ad23fe03a082 5102 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
mbed_official 573:ad23fe03a082 5103
mbed_official 573:ad23fe03a082 5104 /******************** Bit definition for LTDC_LxCR register *****************/
mbed_official 573:ad23fe03a082 5105
mbed_official 573:ad23fe03a082 5106 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
mbed_official 573:ad23fe03a082 5107 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
mbed_official 573:ad23fe03a082 5108 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
mbed_official 573:ad23fe03a082 5109
mbed_official 573:ad23fe03a082 5110 /******************** Bit definition for LTDC_LxWHPCR register **************/
mbed_official 573:ad23fe03a082 5111
mbed_official 573:ad23fe03a082 5112 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
mbed_official 573:ad23fe03a082 5113 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
mbed_official 573:ad23fe03a082 5114
mbed_official 573:ad23fe03a082 5115 /******************** Bit definition for LTDC_LxWVPCR register **************/
mbed_official 573:ad23fe03a082 5116
mbed_official 573:ad23fe03a082 5117 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
mbed_official 573:ad23fe03a082 5118 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
mbed_official 573:ad23fe03a082 5119
mbed_official 573:ad23fe03a082 5120 /******************** Bit definition for LTDC_LxCKCR register ***************/
mbed_official 573:ad23fe03a082 5121
mbed_official 573:ad23fe03a082 5122 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
mbed_official 573:ad23fe03a082 5123 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
mbed_official 573:ad23fe03a082 5124 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
mbed_official 573:ad23fe03a082 5125
mbed_official 573:ad23fe03a082 5126 /******************** Bit definition for LTDC_LxPFCR register ***************/
mbed_official 573:ad23fe03a082 5127
mbed_official 573:ad23fe03a082 5128 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
mbed_official 573:ad23fe03a082 5129
mbed_official 573:ad23fe03a082 5130 /******************** Bit definition for LTDC_LxCACR register ***************/
mbed_official 573:ad23fe03a082 5131
mbed_official 573:ad23fe03a082 5132 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
mbed_official 573:ad23fe03a082 5133
mbed_official 573:ad23fe03a082 5134 /******************** Bit definition for LTDC_LxDCCR register ***************/
mbed_official 573:ad23fe03a082 5135
mbed_official 573:ad23fe03a082 5136 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
mbed_official 573:ad23fe03a082 5137 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
mbed_official 573:ad23fe03a082 5138 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
mbed_official 573:ad23fe03a082 5139 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
mbed_official 573:ad23fe03a082 5140
mbed_official 573:ad23fe03a082 5141 /******************** Bit definition for LTDC_LxBFCR register ***************/
mbed_official 573:ad23fe03a082 5142
mbed_official 573:ad23fe03a082 5143 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
mbed_official 573:ad23fe03a082 5144 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
mbed_official 573:ad23fe03a082 5145
mbed_official 573:ad23fe03a082 5146 /******************** Bit definition for LTDC_LxCFBAR register **************/
mbed_official 573:ad23fe03a082 5147
mbed_official 573:ad23fe03a082 5148 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
mbed_official 573:ad23fe03a082 5149
mbed_official 573:ad23fe03a082 5150 /******************** Bit definition for LTDC_LxCFBLR register **************/
mbed_official 573:ad23fe03a082 5151
mbed_official 573:ad23fe03a082 5152 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
mbed_official 573:ad23fe03a082 5153 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
mbed_official 573:ad23fe03a082 5154
mbed_official 573:ad23fe03a082 5155 /******************** Bit definition for LTDC_LxCFBLNR register *************/
mbed_official 573:ad23fe03a082 5156
mbed_official 573:ad23fe03a082 5157 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
mbed_official 573:ad23fe03a082 5158
mbed_official 573:ad23fe03a082 5159 /******************** Bit definition for LTDC_LxCLUTWR register *************/
mbed_official 573:ad23fe03a082 5160
mbed_official 573:ad23fe03a082 5161 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
mbed_official 573:ad23fe03a082 5162 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
mbed_official 573:ad23fe03a082 5163 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
mbed_official 573:ad23fe03a082 5164 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
mbed_official 573:ad23fe03a082 5165
mbed_official 573:ad23fe03a082 5166
mbed_official 573:ad23fe03a082 5167 /******************************************************************************/
mbed_official 573:ad23fe03a082 5168 /* */
mbed_official 573:ad23fe03a082 5169 /* Power Control */
mbed_official 573:ad23fe03a082 5170 /* */
mbed_official 573:ad23fe03a082 5171 /******************************************************************************/
mbed_official 573:ad23fe03a082 5172 /******************** Bit definition for PWR_CR1 register ********************/
mbed_official 573:ad23fe03a082 5173 #define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 573:ad23fe03a082 5174 #define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 573:ad23fe03a082 5175 #define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 573:ad23fe03a082 5176 #define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 573:ad23fe03a082 5177
mbed_official 573:ad23fe03a082 5178 #define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 573:ad23fe03a082 5179 #define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5180 #define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5181 #define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5182
mbed_official 573:ad23fe03a082 5183 /*!< PVD level configuration */
mbed_official 573:ad23fe03a082 5184 #define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 573:ad23fe03a082 5185 #define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 573:ad23fe03a082 5186 #define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 573:ad23fe03a082 5187 #define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 573:ad23fe03a082 5188 #define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 573:ad23fe03a082 5189 #define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 573:ad23fe03a082 5190 #define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 573:ad23fe03a082 5191 #define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 573:ad23fe03a082 5192
mbed_official 573:ad23fe03a082 5193 #define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 573:ad23fe03a082 5194 #define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 573:ad23fe03a082 5195
mbed_official 573:ad23fe03a082 5196 #define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */
mbed_official 573:ad23fe03a082 5197 #define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */
mbed_official 573:ad23fe03a082 5198
mbed_official 573:ad23fe03a082 5199 #define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 573:ad23fe03a082 5200
mbed_official 573:ad23fe03a082 5201 #define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
mbed_official 573:ad23fe03a082 5202 #define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5203 #define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5204
mbed_official 573:ad23fe03a082 5205 #define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
mbed_official 573:ad23fe03a082 5206 #define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
mbed_official 573:ad23fe03a082 5207 #define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
mbed_official 573:ad23fe03a082 5208 #define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5209 #define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5210
mbed_official 573:ad23fe03a082 5211 /******************* Bit definition for PWR_CSR1 register ********************/
mbed_official 573:ad23fe03a082 5212 #define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */
mbed_official 573:ad23fe03a082 5213 #define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 573:ad23fe03a082 5214 #define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 573:ad23fe03a082 5215 #define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 573:ad23fe03a082 5216 #define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 573:ad23fe03a082 5217 #define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 573:ad23fe03a082 5218
mbed_official 573:ad23fe03a082 5219 #define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
mbed_official 573:ad23fe03a082 5220 #define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
mbed_official 573:ad23fe03a082 5221 #define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
mbed_official 573:ad23fe03a082 5222
mbed_official 573:ad23fe03a082 5223 /******************** Bit definition for PWR_CR2 register ********************/
mbed_official 573:ad23fe03a082 5224 #define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */
mbed_official 573:ad23fe03a082 5225 #define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */
mbed_official 573:ad23fe03a082 5226 #define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */
mbed_official 573:ad23fe03a082 5227 #define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */
mbed_official 573:ad23fe03a082 5228 #define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */
mbed_official 573:ad23fe03a082 5229 #define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */
mbed_official 573:ad23fe03a082 5230
mbed_official 573:ad23fe03a082 5231 #define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */
mbed_official 573:ad23fe03a082 5232 #define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */
mbed_official 573:ad23fe03a082 5233 #define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */
mbed_official 573:ad23fe03a082 5234 #define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */
mbed_official 573:ad23fe03a082 5235 #define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */
mbed_official 573:ad23fe03a082 5236 #define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */
mbed_official 573:ad23fe03a082 5237
mbed_official 573:ad23fe03a082 5238 /******************* Bit definition for PWR_CSR2 register ********************/
mbed_official 573:ad23fe03a082 5239 #define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */
mbed_official 573:ad23fe03a082 5240 #define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */
mbed_official 573:ad23fe03a082 5241 #define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */
mbed_official 573:ad23fe03a082 5242 #define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */
mbed_official 573:ad23fe03a082 5243 #define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */
mbed_official 573:ad23fe03a082 5244 #define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */
mbed_official 573:ad23fe03a082 5245
mbed_official 573:ad23fe03a082 5246 #define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */
mbed_official 573:ad23fe03a082 5247 #define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */
mbed_official 573:ad23fe03a082 5248 #define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */
mbed_official 573:ad23fe03a082 5249 #define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */
mbed_official 573:ad23fe03a082 5250 #define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */
mbed_official 573:ad23fe03a082 5251 #define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */
mbed_official 573:ad23fe03a082 5252
mbed_official 573:ad23fe03a082 5253 /******************************************************************************/
mbed_official 573:ad23fe03a082 5254 /* */
mbed_official 573:ad23fe03a082 5255 /* QUADSPI */
mbed_official 573:ad23fe03a082 5256 /* */
mbed_official 573:ad23fe03a082 5257 /******************************************************************************/
mbed_official 573:ad23fe03a082 5258 /***************** Bit definition for QUADSPI_CR register *******************/
mbed_official 573:ad23fe03a082 5259 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
mbed_official 573:ad23fe03a082 5260 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
mbed_official 573:ad23fe03a082 5261 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
mbed_official 573:ad23fe03a082 5262 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
mbed_official 573:ad23fe03a082 5263 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */
mbed_official 573:ad23fe03a082 5264 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
mbed_official 573:ad23fe03a082 5265 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
mbed_official 573:ad23fe03a082 5266 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
mbed_official 573:ad23fe03a082 5267 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5268 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5269 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5270 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5271 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
mbed_official 573:ad23fe03a082 5272 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
mbed_official 573:ad23fe03a082 5273 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
mbed_official 573:ad23fe03a082 5274 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
mbed_official 573:ad23fe03a082 5275 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
mbed_official 573:ad23fe03a082 5276 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5277 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
mbed_official 573:ad23fe03a082 5278 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
mbed_official 573:ad23fe03a082 5279 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5280 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5281 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5282 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5283 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 5284 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
mbed_official 573:ad23fe03a082 5285 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
mbed_official 573:ad23fe03a082 5286 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
mbed_official 573:ad23fe03a082 5287
mbed_official 573:ad23fe03a082 5288 /***************** Bit definition for QUADSPI_DCR register ******************/
mbed_official 573:ad23fe03a082 5289 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
mbed_official 573:ad23fe03a082 5290 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
mbed_official 573:ad23fe03a082 5291 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5292 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5293 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5294 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
mbed_official 573:ad23fe03a082 5295 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5296 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5297 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5298 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5299 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 5300
mbed_official 573:ad23fe03a082 5301 /****************** Bit definition for QUADSPI_SR register *******************/
mbed_official 573:ad23fe03a082 5302 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
mbed_official 573:ad23fe03a082 5303 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
mbed_official 573:ad23fe03a082 5304 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
mbed_official 573:ad23fe03a082 5305 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
mbed_official 573:ad23fe03a082 5306 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
mbed_official 573:ad23fe03a082 5307 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
mbed_official 573:ad23fe03a082 5308 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */
mbed_official 573:ad23fe03a082 5309 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5310 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5311 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5312 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5313 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 5314
mbed_official 573:ad23fe03a082 5315 /****************** Bit definition for QUADSPI_FCR register ******************/
mbed_official 573:ad23fe03a082 5316 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
mbed_official 573:ad23fe03a082 5317 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
mbed_official 573:ad23fe03a082 5318 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
mbed_official 573:ad23fe03a082 5319 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
mbed_official 573:ad23fe03a082 5320
mbed_official 573:ad23fe03a082 5321 /****************** Bit definition for QUADSPI_DLR register ******************/
mbed_official 573:ad23fe03a082 5322 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
mbed_official 573:ad23fe03a082 5323
mbed_official 573:ad23fe03a082 5324 /****************** Bit definition for QUADSPI_CCR register ******************/
mbed_official 573:ad23fe03a082 5325 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
mbed_official 573:ad23fe03a082 5326 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5327 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5328 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5329 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5330 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 5331 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 573:ad23fe03a082 5332 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 573:ad23fe03a082 5333 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 573:ad23fe03a082 5334 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
mbed_official 573:ad23fe03a082 5335 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5336 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5337 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
mbed_official 573:ad23fe03a082 5338 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5339 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5340 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
mbed_official 573:ad23fe03a082 5341 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5342 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5343 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
mbed_official 573:ad23fe03a082 5344 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5345 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5346 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
mbed_official 573:ad23fe03a082 5347 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5348 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5349 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
mbed_official 573:ad23fe03a082 5350 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5351 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5352 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5353 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5354 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 5355 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
mbed_official 573:ad23fe03a082 5356 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5357 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5358 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
mbed_official 573:ad23fe03a082 5359 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5360 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5361 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
mbed_official 573:ad23fe03a082 5362 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
mbed_official 573:ad23fe03a082 5363 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
mbed_official 573:ad23fe03a082 5364 /****************** Bit definition for QUADSPI_AR register *******************/
mbed_official 573:ad23fe03a082 5365 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
mbed_official 573:ad23fe03a082 5366
mbed_official 573:ad23fe03a082 5367 /****************** Bit definition for QUADSPI_ABR register ******************/
mbed_official 573:ad23fe03a082 5368 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
mbed_official 573:ad23fe03a082 5369
mbed_official 573:ad23fe03a082 5370 /****************** Bit definition for QUADSPI_DR register *******************/
mbed_official 573:ad23fe03a082 5371 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
mbed_official 573:ad23fe03a082 5372
mbed_official 573:ad23fe03a082 5373 /****************** Bit definition for QUADSPI_PSMKR register ****************/
mbed_official 573:ad23fe03a082 5374 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
mbed_official 573:ad23fe03a082 5375
mbed_official 573:ad23fe03a082 5376 /****************** Bit definition for QUADSPI_PSMAR register ****************/
mbed_official 573:ad23fe03a082 5377 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
mbed_official 573:ad23fe03a082 5378
mbed_official 573:ad23fe03a082 5379 /****************** Bit definition for QUADSPI_PIR register *****************/
mbed_official 573:ad23fe03a082 5380 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
mbed_official 573:ad23fe03a082 5381
mbed_official 573:ad23fe03a082 5382 /****************** Bit definition for QUADSPI_LPTR register *****************/
mbed_official 573:ad23fe03a082 5383 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
mbed_official 573:ad23fe03a082 5384
mbed_official 573:ad23fe03a082 5385 /******************************************************************************/
mbed_official 573:ad23fe03a082 5386 /* */
mbed_official 573:ad23fe03a082 5387 /* Reset and Clock Control */
mbed_official 573:ad23fe03a082 5388 /* */
mbed_official 573:ad23fe03a082 5389 /******************************************************************************/
mbed_official 573:ad23fe03a082 5390 /******************** Bit definition for RCC_CR register ********************/
mbed_official 573:ad23fe03a082 5391 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5392 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5393
mbed_official 573:ad23fe03a082 5394 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 573:ad23fe03a082 5395 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 5396 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 5397 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 5398 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 5399 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 5400
mbed_official 573:ad23fe03a082 5401 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 573:ad23fe03a082 5402 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 5403 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 5404 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 5405 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 5406 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 5407 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 5408 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 5409 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 5410
mbed_official 573:ad23fe03a082 5411 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5412 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5413 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5414 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5415 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5416 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5417 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5418 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5419 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5420 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5421
mbed_official 573:ad23fe03a082 5422 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 573:ad23fe03a082 5423 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 573:ad23fe03a082 5424 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5425 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5426 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5427 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5428 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5429 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5430
mbed_official 573:ad23fe03a082 5431 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 573:ad23fe03a082 5432 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5433 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5434 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5435 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5436 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5437 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5438 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5439 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5440 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5441
mbed_official 573:ad23fe03a082 5442 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 5443 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5444 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5445
mbed_official 573:ad23fe03a082 5446 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5447 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5448 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 5449
mbed_official 573:ad23fe03a082 5450 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 5451 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5452 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5453 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5454 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5455
mbed_official 573:ad23fe03a082 5456 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 573:ad23fe03a082 5457 /*!< SW configuration */
mbed_official 573:ad23fe03a082 5458 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 573:ad23fe03a082 5459 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5460 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5461
mbed_official 573:ad23fe03a082 5462 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 573:ad23fe03a082 5463 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 573:ad23fe03a082 5464 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 573:ad23fe03a082 5465
mbed_official 573:ad23fe03a082 5466 /*!< SWS configuration */
mbed_official 573:ad23fe03a082 5467 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 573:ad23fe03a082 5468 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5469 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5470
mbed_official 573:ad23fe03a082 5471 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 573:ad23fe03a082 5472 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 573:ad23fe03a082 5473 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 573:ad23fe03a082 5474
mbed_official 573:ad23fe03a082 5475 /*!< HPRE configuration */
mbed_official 573:ad23fe03a082 5476 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 573:ad23fe03a082 5477 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5478 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5479 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5480 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 5481
mbed_official 573:ad23fe03a082 5482 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 573:ad23fe03a082 5483 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 573:ad23fe03a082 5484 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 573:ad23fe03a082 5485 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 573:ad23fe03a082 5486 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 573:ad23fe03a082 5487 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 573:ad23fe03a082 5488 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 573:ad23fe03a082 5489 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 573:ad23fe03a082 5490 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 573:ad23fe03a082 5491
mbed_official 573:ad23fe03a082 5492 /*!< PPRE1 configuration */
mbed_official 573:ad23fe03a082 5493 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 573:ad23fe03a082 5494 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5495 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5496 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5497
mbed_official 573:ad23fe03a082 5498 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 573:ad23fe03a082 5499 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 573:ad23fe03a082 5500 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 573:ad23fe03a082 5501 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 573:ad23fe03a082 5502 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 573:ad23fe03a082 5503
mbed_official 573:ad23fe03a082 5504 /*!< PPRE2 configuration */
mbed_official 573:ad23fe03a082 5505 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 573:ad23fe03a082 5506 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 5507 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 5508 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 5509
mbed_official 573:ad23fe03a082 5510 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 573:ad23fe03a082 5511 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 573:ad23fe03a082 5512 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 573:ad23fe03a082 5513 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 573:ad23fe03a082 5514 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 573:ad23fe03a082 5515
mbed_official 573:ad23fe03a082 5516 /*!< RTCPRE configuration */
mbed_official 573:ad23fe03a082 5517 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 573:ad23fe03a082 5518 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5519 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5520 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5521 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5522 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5523
mbed_official 573:ad23fe03a082 5524 /*!< MCO1 configuration */
mbed_official 573:ad23fe03a082 5525 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 573:ad23fe03a082 5526 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5527 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5528
mbed_official 573:ad23fe03a082 5529 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5530
mbed_official 573:ad23fe03a082 5531 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 573:ad23fe03a082 5532 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5533 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5534 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5535
mbed_official 573:ad23fe03a082 5536 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 573:ad23fe03a082 5537 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5538 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5539 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5540
mbed_official 573:ad23fe03a082 5541 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 573:ad23fe03a082 5542 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5543 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5544
mbed_official 573:ad23fe03a082 5545 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 573:ad23fe03a082 5546 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5547 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5548 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5549 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5550 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5551 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5552 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5553 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5554 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5555 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5556 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5557 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5558 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5559 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5560 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5561 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5562 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5563 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5564 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5565 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5566 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5567 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5568 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5569
mbed_official 573:ad23fe03a082 5570 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 573:ad23fe03a082 5571 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5572 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5573 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5574 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5575 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5576 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5577 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5578 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5579 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5580 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5581 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5582 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5583 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5584 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5585 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5586 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5587 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5588
mbed_official 573:ad23fe03a082 5589 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 573:ad23fe03a082 5590 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5591 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5592 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5593
mbed_official 573:ad23fe03a082 5594 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 573:ad23fe03a082 5595
mbed_official 573:ad23fe03a082 5596 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5597 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5598
mbed_official 573:ad23fe03a082 5599 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 573:ad23fe03a082 5600 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5601 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5602 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5603 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5604 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5605 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5606 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5607 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5608 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5609 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5610 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5611 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5612 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5613 #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5614 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5615 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5616 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5617 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5618 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5619 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5620 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5621 #define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5622 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5623 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5624 #define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5625 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5626 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5627 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5628 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5629
mbed_official 573:ad23fe03a082 5630 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 573:ad23fe03a082 5631 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5632 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5633 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5634 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5635 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5636 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5637 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5638 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5639 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5640 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5641 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5642 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5643 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5644 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5645 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5646 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5647 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5648
mbed_official 573:ad23fe03a082 5649 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 573:ad23fe03a082 5650 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5651 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5652 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5653 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5654 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5655 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5656 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5657 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5658 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5659 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5660 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5661 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5662 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5663 #define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5664 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5665 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5666 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5667 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5668 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5669 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5670 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5671 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5672 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5673
mbed_official 573:ad23fe03a082 5674 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 573:ad23fe03a082 5675 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5676 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5677 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5678
mbed_official 573:ad23fe03a082 5679 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 573:ad23fe03a082 5680
mbed_official 573:ad23fe03a082 5681 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5682 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5683
mbed_official 573:ad23fe03a082 5684 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 573:ad23fe03a082 5685 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5686 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5687 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5688 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5689 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5690 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5691 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5692 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5693 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5694 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5695 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5696 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5697 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5698 #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5699 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5700 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5701 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5702 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5703 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5704 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5705 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5706 #define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5707 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5708 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5709 #define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5710 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5711 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5712 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5713 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5714
mbed_official 573:ad23fe03a082 5715 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 573:ad23fe03a082 5716 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5717 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5718 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5719 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5720 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5721 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5722 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5723 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5724 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5725 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5726 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5727 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5728 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5729 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5730 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5731 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5732 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5733 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5734 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5735
mbed_official 573:ad23fe03a082 5736 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 573:ad23fe03a082 5737 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5738 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5739 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5740 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5741 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5742 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5743 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5744 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5745 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5746 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5747 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5748
mbed_official 573:ad23fe03a082 5749 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5750 #define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5751 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5752 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5753 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5754 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5755 #define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5756 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5757 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5758 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5759 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5760 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5761 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5762 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5763 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5764 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5765
mbed_official 573:ad23fe03a082 5766 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 573:ad23fe03a082 5767 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5768 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5769 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5770
mbed_official 573:ad23fe03a082 5771 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 573:ad23fe03a082 5772 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5773 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5774 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 573:ad23fe03a082 5775 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5776 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5777 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5778 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5779 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5780 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5781 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5782 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5783 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5784 #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5785 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5786 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5787 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5788 #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5789 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5790 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5791 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5792 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5793 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5794 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5795 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5796 #define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5797 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5798 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5799 #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5800 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5801 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5802 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5803 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5804
mbed_official 573:ad23fe03a082 5805 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 573:ad23fe03a082 5806 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5807 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5808 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5809 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5810 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5811 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5812 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5813 #define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5814 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5815 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5816 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5817 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5818 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5819 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5820 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5821 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5822 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5823 #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5824 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5825
mbed_official 573:ad23fe03a082 5826 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 573:ad23fe03a082 5827 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5828 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5829 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5830 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
mbed_official 573:ad23fe03a082 5831 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5832 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5833 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 5834 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5835 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5836 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5837 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5838
mbed_official 573:ad23fe03a082 5839 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 573:ad23fe03a082 5840 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5841 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5842 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5843 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5844 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5845 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5846 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5847 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5848 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5849 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5850
mbed_official 573:ad23fe03a082 5851 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 573:ad23fe03a082 5852 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 573:ad23fe03a082 5853 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 573:ad23fe03a082 5854 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5855 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 5856
mbed_official 573:ad23fe03a082 5857 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 573:ad23fe03a082 5858 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 573:ad23fe03a082 5859 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5860 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5861 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5862 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5863 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5864 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5865 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5866 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5867 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5868
mbed_official 573:ad23fe03a082 5869 #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 5870 #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5871 #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5872
mbed_official 573:ad23fe03a082 5873 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 5874 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5875 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5876 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5877 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5878
mbed_official 573:ad23fe03a082 5879 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 573:ad23fe03a082 5880 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5881 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5882 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5883
mbed_official 573:ad23fe03a082 5884 /******************** Bit definition for RCC_PLLSAICFGR register ************/
mbed_official 573:ad23fe03a082 5885 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
mbed_official 573:ad23fe03a082 5886 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5887 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5888 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5889 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5890 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5891 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5892 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5893 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5894 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5895
mbed_official 573:ad23fe03a082 5896 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 5897 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5898 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5899
mbed_official 573:ad23fe03a082 5900 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 5901 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5902 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5903 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5904 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5905
mbed_official 573:ad23fe03a082 5906 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
mbed_official 573:ad23fe03a082 5907 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5908 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 5909 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 5910
mbed_official 573:ad23fe03a082 5911 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
mbed_official 573:ad23fe03a082 5912 #define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
mbed_official 573:ad23fe03a082 5913 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5914 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5915 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5916 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5917 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5918
mbed_official 573:ad23fe03a082 5919 #define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
mbed_official 573:ad23fe03a082 5920 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5921 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5922 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5923 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5924 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5925
mbed_official 573:ad23fe03a082 5926 #define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 5927 #define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5928 #define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5929
mbed_official 573:ad23fe03a082 5930 #define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 5931 #define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5932 #define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5933
mbed_official 573:ad23fe03a082 5934 #define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
mbed_official 573:ad23fe03a082 5935 #define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5936 #define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5937
mbed_official 573:ad23fe03a082 5938 #define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5939
mbed_official 573:ad23fe03a082 5940 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
mbed_official 573:ad23fe03a082 5941 #define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
mbed_official 573:ad23fe03a082 5942 #define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5943 #define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5944 #define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
mbed_official 573:ad23fe03a082 5945 #define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5946 #define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5947 #define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 5948 #define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 5949 #define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5950 #define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 5951 #define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5952 #define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 5953 #define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 5954 #define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 5955 #define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 5956 #define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
mbed_official 573:ad23fe03a082 5957 #define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 5958 #define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 5959 #define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
mbed_official 573:ad23fe03a082 5960 #define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 5961 #define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 5962 #define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
mbed_official 573:ad23fe03a082 5963 #define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 5964 #define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 5965 #define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
mbed_official 573:ad23fe03a082 5966 #define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 5967 #define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 5968 #define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
mbed_official 573:ad23fe03a082 5969 #define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 5970 #define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 5971 #define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 5972 #define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 5973 #define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 5974 #define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
mbed_official 573:ad23fe03a082 5975 #define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 5976 #define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 5977 #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
mbed_official 573:ad23fe03a082 5978 #define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 5979 #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 5980 #define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 5981 #define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 5982 #define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 5983
mbed_official 573:ad23fe03a082 5984 /******************************************************************************/
mbed_official 573:ad23fe03a082 5985 /* */
mbed_official 573:ad23fe03a082 5986 /* RNG */
mbed_official 573:ad23fe03a082 5987 /* */
mbed_official 573:ad23fe03a082 5988 /******************************************************************************/
mbed_official 573:ad23fe03a082 5989 /******************** Bits definition for RNG_CR register *******************/
mbed_official 573:ad23fe03a082 5990 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5991 #define RNG_CR_IE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 5992
mbed_official 573:ad23fe03a082 5993 /******************** Bits definition for RNG_SR register *******************/
mbed_official 573:ad23fe03a082 5994 #define RNG_SR_DRDY ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 5995 #define RNG_SR_CECS ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 5996 #define RNG_SR_SECS ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 5997 #define RNG_SR_CEIS ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 5998 #define RNG_SR_SEIS ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 5999
mbed_official 573:ad23fe03a082 6000 /******************************************************************************/
mbed_official 573:ad23fe03a082 6001 /* */
mbed_official 573:ad23fe03a082 6002 /* Real-Time Clock (RTC) */
mbed_official 573:ad23fe03a082 6003 /* */
mbed_official 573:ad23fe03a082 6004 /******************************************************************************/
mbed_official 573:ad23fe03a082 6005 /******************** Bits definition for RTC_TR register *******************/
mbed_official 573:ad23fe03a082 6006 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6007 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 6008 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6009 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6010 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 573:ad23fe03a082 6011 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6012 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6013 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6014 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6015 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 573:ad23fe03a082 6016 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6017 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6018 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6019 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6020 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6021 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6022 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6023 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6024 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 573:ad23fe03a082 6025 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6026 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6027 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6028 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6029 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6030 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6031 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6032 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6033
mbed_official 573:ad23fe03a082 6034 /******************** Bits definition for RTC_DR register *******************/
mbed_official 573:ad23fe03a082 6035 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 573:ad23fe03a082 6036 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6037 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6038 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6039 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 6040 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 573:ad23fe03a082 6041 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6042 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6043 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6044 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6045 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 573:ad23fe03a082 6046 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6047 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6048 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6049 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6050 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6051 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6052 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6053 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6054 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6055 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 6056 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6057 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6058 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6059 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6060 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6061 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6062 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6063
mbed_official 573:ad23fe03a082 6064 /******************** Bits definition for RTC_CR register *******************/
mbed_official 573:ad23fe03a082 6065 #define RTC_CR_ITSE ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6066 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 6067 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 573:ad23fe03a082 6068 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6069 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6070 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6071 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6072 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6073 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6074 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6075 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6076 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6077 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6078 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6079 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6080 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6081 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6082 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6083 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6084 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6085 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6086 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6087 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 573:ad23fe03a082 6088 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6089 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6090 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6091
mbed_official 573:ad23fe03a082 6092 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 573:ad23fe03a082 6093 #define RTC_ISR_ITSF ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6094 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6095 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6096 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6097 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6098 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6099 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6100 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6101 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6102 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6103 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 6104 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6105 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6106 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6107 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6108 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6109 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6110 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6111
mbed_official 573:ad23fe03a082 6112 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 573:ad23fe03a082 6113 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 573:ad23fe03a082 6114 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 573:ad23fe03a082 6115
mbed_official 573:ad23fe03a082 6116 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 573:ad23fe03a082 6117 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 573:ad23fe03a082 6118
mbed_official 573:ad23fe03a082 6119 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 573:ad23fe03a082 6120 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 6121 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 6122 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 573:ad23fe03a082 6123 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 6124 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 6125 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 6126 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6127 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 6128 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 6129 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 6130 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 6131 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6132 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 6133 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6134 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6135 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 573:ad23fe03a082 6136 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6137 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6138 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6139 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6140 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6141 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 573:ad23fe03a082 6142 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6143 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6144 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6145 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6146 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6147 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6148 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6149 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6150 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 6151 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 573:ad23fe03a082 6152 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6153 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6154 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6155 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6156 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6157 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6158 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6159 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6160
mbed_official 573:ad23fe03a082 6161 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 573:ad23fe03a082 6162 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 6163 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 573:ad23fe03a082 6164 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 573:ad23fe03a082 6165 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 573:ad23fe03a082 6166 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 573:ad23fe03a082 6167 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 6168 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6169 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 6170 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 6171 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 6172 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 6173 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6174 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 6175 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6176 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6177 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 573:ad23fe03a082 6178 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6179 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6180 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6181 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6182 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6183 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 573:ad23fe03a082 6184 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6185 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6186 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6187 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6188 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6189 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6190 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6191 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6192 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 6193 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 573:ad23fe03a082 6194 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6195 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6196 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6197 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6198 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6199 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6200 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6201 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6202
mbed_official 573:ad23fe03a082 6203 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 573:ad23fe03a082 6204 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 573:ad23fe03a082 6205
mbed_official 573:ad23fe03a082 6206 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 573:ad23fe03a082 6207 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 573:ad23fe03a082 6208
mbed_official 573:ad23fe03a082 6209 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 573:ad23fe03a082 6210 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 573:ad23fe03a082 6211 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 6212
mbed_official 573:ad23fe03a082 6213 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 573:ad23fe03a082 6214 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6215 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 573:ad23fe03a082 6216 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6217 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6218 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 573:ad23fe03a082 6219 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6220 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6221 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6222 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6223 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 573:ad23fe03a082 6224 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6225 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6226 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6227 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6228 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6229 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6230 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6231 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6232 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 573:ad23fe03a082 6233 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6234 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6235 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6236 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6237 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6238 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6239 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6240 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6241
mbed_official 573:ad23fe03a082 6242 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 573:ad23fe03a082 6243 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 573:ad23fe03a082 6244 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6245 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6246 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6247 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6248 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 573:ad23fe03a082 6249 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6250 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6251 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6252 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6253 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 573:ad23fe03a082 6254 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6255 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6256 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 573:ad23fe03a082 6257 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6258 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6259 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6260 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6261
mbed_official 573:ad23fe03a082 6262 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 573:ad23fe03a082 6263 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 573:ad23fe03a082 6264
mbed_official 573:ad23fe03a082 6265 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 573:ad23fe03a082 6266 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6267 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6268 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6269 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 573:ad23fe03a082 6270 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6271 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6272 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6273 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6274 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6275 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6276 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6277 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 6278 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6279
mbed_official 573:ad23fe03a082 6280 /******************** Bits definition for RTC_TAMPCR register ****************/
mbed_official 573:ad23fe03a082 6281 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6282 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 6283 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 6284 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 6285 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
mbed_official 573:ad23fe03a082 6286 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
mbed_official 573:ad23fe03a082 6287 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 6288 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 6289 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 6290 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 6291 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 573:ad23fe03a082 6292 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 6293 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 6294 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 573:ad23fe03a082 6295 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6296 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 6297 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 573:ad23fe03a082 6298 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 6299 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 6300 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6301 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 6302 #define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 6303 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6304 #define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 6305 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6306 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6307 #define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6308 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 6309
mbed_official 573:ad23fe03a082 6310 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 573:ad23fe03a082 6311 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 6312 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6313 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 6314 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 6315 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 6316 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 573:ad23fe03a082 6317
mbed_official 573:ad23fe03a082 6318 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 573:ad23fe03a082 6319 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 573:ad23fe03a082 6320 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 6321 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 6322 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 6323 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 573:ad23fe03a082 6324 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 573:ad23fe03a082 6325
mbed_official 573:ad23fe03a082 6326 /******************** Bits definition for RTC_OR register ****************/
mbed_official 573:ad23fe03a082 6327 #define RTC_OR_TSINSEL ((uint32_t)0x00000006)
mbed_official 573:ad23fe03a082 6328 #define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 6329 #define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 6330 #define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 6331
mbed_official 573:ad23fe03a082 6332
mbed_official 573:ad23fe03a082 6333 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 573:ad23fe03a082 6334 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6335
mbed_official 573:ad23fe03a082 6336 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 573:ad23fe03a082 6337 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6338
mbed_official 573:ad23fe03a082 6339 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 573:ad23fe03a082 6340 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6341
mbed_official 573:ad23fe03a082 6342 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 573:ad23fe03a082 6343 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6344
mbed_official 573:ad23fe03a082 6345 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 573:ad23fe03a082 6346 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6347
mbed_official 573:ad23fe03a082 6348 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 573:ad23fe03a082 6349 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6350
mbed_official 573:ad23fe03a082 6351 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 573:ad23fe03a082 6352 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6353
mbed_official 573:ad23fe03a082 6354 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 573:ad23fe03a082 6355 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6356
mbed_official 573:ad23fe03a082 6357 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 573:ad23fe03a082 6358 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6359
mbed_official 573:ad23fe03a082 6360 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 573:ad23fe03a082 6361 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6362
mbed_official 573:ad23fe03a082 6363 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 573:ad23fe03a082 6364 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6365
mbed_official 573:ad23fe03a082 6366 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 573:ad23fe03a082 6367 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6368
mbed_official 573:ad23fe03a082 6369 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 573:ad23fe03a082 6370 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6371
mbed_official 573:ad23fe03a082 6372 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 573:ad23fe03a082 6373 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6374
mbed_official 573:ad23fe03a082 6375 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 573:ad23fe03a082 6376 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6377
mbed_official 573:ad23fe03a082 6378 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 573:ad23fe03a082 6379 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6380
mbed_official 573:ad23fe03a082 6381 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 573:ad23fe03a082 6382 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6383
mbed_official 573:ad23fe03a082 6384 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 573:ad23fe03a082 6385 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6386
mbed_official 573:ad23fe03a082 6387 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 573:ad23fe03a082 6388 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6389
mbed_official 573:ad23fe03a082 6390 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 573:ad23fe03a082 6391 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6392
mbed_official 573:ad23fe03a082 6393 /******************** Bits definition for RTC_BKP20R register ***************/
mbed_official 573:ad23fe03a082 6394 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6395
mbed_official 573:ad23fe03a082 6396 /******************** Bits definition for RTC_BKP21R register ***************/
mbed_official 573:ad23fe03a082 6397 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6398
mbed_official 573:ad23fe03a082 6399 /******************** Bits definition for RTC_BKP22R register ***************/
mbed_official 573:ad23fe03a082 6400 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6401
mbed_official 573:ad23fe03a082 6402 /******************** Bits definition for RTC_BKP23R register ***************/
mbed_official 573:ad23fe03a082 6403 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6404
mbed_official 573:ad23fe03a082 6405 /******************** Bits definition for RTC_BKP24R register ***************/
mbed_official 573:ad23fe03a082 6406 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6407
mbed_official 573:ad23fe03a082 6408 /******************** Bits definition for RTC_BKP25R register ***************/
mbed_official 573:ad23fe03a082 6409 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6410
mbed_official 573:ad23fe03a082 6411 /******************** Bits definition for RTC_BKP26R register ***************/
mbed_official 573:ad23fe03a082 6412 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6413
mbed_official 573:ad23fe03a082 6414 /******************** Bits definition for RTC_BKP27R register ***************/
mbed_official 573:ad23fe03a082 6415 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6416
mbed_official 573:ad23fe03a082 6417 /******************** Bits definition for RTC_BKP28R register ***************/
mbed_official 573:ad23fe03a082 6418 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6419
mbed_official 573:ad23fe03a082 6420 /******************** Bits definition for RTC_BKP29R register ***************/
mbed_official 573:ad23fe03a082 6421 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6422
mbed_official 573:ad23fe03a082 6423 /******************** Bits definition for RTC_BKP30R register ***************/
mbed_official 573:ad23fe03a082 6424 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6425
mbed_official 573:ad23fe03a082 6426 /******************** Bits definition for RTC_BKP31R register ***************/
mbed_official 573:ad23fe03a082 6427 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6428
mbed_official 573:ad23fe03a082 6429 /******************** Number of backup registers ******************************/
mbed_official 573:ad23fe03a082 6430 #define RTC_BKP_NUMBER ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 6431
mbed_official 573:ad23fe03a082 6432
mbed_official 573:ad23fe03a082 6433 /******************************************************************************/
mbed_official 573:ad23fe03a082 6434 /* */
mbed_official 573:ad23fe03a082 6435 /* Serial Audio Interface */
mbed_official 573:ad23fe03a082 6436 /* */
mbed_official 573:ad23fe03a082 6437 /******************************************************************************/
mbed_official 573:ad23fe03a082 6438 /******************** Bit definition for SAI_GCR register *******************/
mbed_official 573:ad23fe03a082 6439 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
mbed_official 573:ad23fe03a082 6440 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6441 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6442
mbed_official 573:ad23fe03a082 6443 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
mbed_official 573:ad23fe03a082 6444 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6445 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6446
mbed_official 573:ad23fe03a082 6447 /******************* Bit definition for SAI_xCR1 register *******************/
mbed_official 573:ad23fe03a082 6448 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
mbed_official 573:ad23fe03a082 6449 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6450 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6451
mbed_official 573:ad23fe03a082 6452 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
mbed_official 573:ad23fe03a082 6453 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6454 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6455
mbed_official 573:ad23fe03a082 6456 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
mbed_official 573:ad23fe03a082 6457 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6458 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6459 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6460
mbed_official 573:ad23fe03a082 6461 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
mbed_official 573:ad23fe03a082 6462 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
mbed_official 573:ad23fe03a082 6463
mbed_official 573:ad23fe03a082 6464 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
mbed_official 573:ad23fe03a082 6465 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6466 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6467
mbed_official 573:ad23fe03a082 6468 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
mbed_official 573:ad23fe03a082 6469 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
mbed_official 573:ad23fe03a082 6470 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
mbed_official 573:ad23fe03a082 6471 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
mbed_official 573:ad23fe03a082 6472 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
mbed_official 573:ad23fe03a082 6473
mbed_official 573:ad23fe03a082 6474 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
mbed_official 573:ad23fe03a082 6475 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6476 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6477 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6478 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6479
mbed_official 573:ad23fe03a082 6480 /******************* Bit definition for SAI_xCR2 register *******************/
mbed_official 573:ad23fe03a082 6481 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
mbed_official 573:ad23fe03a082 6482 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6483 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6484 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6485
mbed_official 573:ad23fe03a082 6486 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
mbed_official 573:ad23fe03a082 6487 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
mbed_official 573:ad23fe03a082 6488 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
mbed_official 573:ad23fe03a082 6489 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
mbed_official 573:ad23fe03a082 6490
mbed_official 573:ad23fe03a082 6491 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
mbed_official 573:ad23fe03a082 6492 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6493 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6494 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6495 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6496 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 6497 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 6498
mbed_official 573:ad23fe03a082 6499 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
mbed_official 573:ad23fe03a082 6500
mbed_official 573:ad23fe03a082 6501 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
mbed_official 573:ad23fe03a082 6502 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6503 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6504
mbed_official 573:ad23fe03a082 6505 /****************** Bit definition for SAI_xFRCR register *******************/
mbed_official 573:ad23fe03a082 6506 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
mbed_official 573:ad23fe03a082 6507 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6508 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6509 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6510 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6511 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 6512 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 6513 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 6514 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 6515
mbed_official 573:ad23fe03a082 6516 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
mbed_official 573:ad23fe03a082 6517 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6518 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6519 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6520 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6521 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 6522 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 6523 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 6524
mbed_official 573:ad23fe03a082 6525 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
mbed_official 573:ad23fe03a082 6526 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
mbed_official 573:ad23fe03a082 6527 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
mbed_official 573:ad23fe03a082 6528
mbed_official 573:ad23fe03a082 6529 /****************** Bit definition for SAI_xSLOTR register *******************/
mbed_official 573:ad23fe03a082 6530 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
mbed_official 573:ad23fe03a082 6531 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6532 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6533 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6534 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6535 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 6536
mbed_official 573:ad23fe03a082 6537 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
mbed_official 573:ad23fe03a082 6538 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6539 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6540
mbed_official 573:ad23fe03a082 6541 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
mbed_official 573:ad23fe03a082 6542 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6543 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6544 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6545 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6546
mbed_official 573:ad23fe03a082 6547 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
mbed_official 573:ad23fe03a082 6548
mbed_official 573:ad23fe03a082 6549 /******************* Bit definition for SAI_xIMR register *******************/
mbed_official 573:ad23fe03a082 6550 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
mbed_official 573:ad23fe03a082 6551 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
mbed_official 573:ad23fe03a082 6552 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
mbed_official 573:ad23fe03a082 6553 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
mbed_official 573:ad23fe03a082 6554 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
mbed_official 573:ad23fe03a082 6555 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
mbed_official 573:ad23fe03a082 6556 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
mbed_official 573:ad23fe03a082 6557
mbed_official 573:ad23fe03a082 6558 /******************** Bit definition for SAI_xSR register *******************/
mbed_official 573:ad23fe03a082 6559 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
mbed_official 573:ad23fe03a082 6560 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
mbed_official 573:ad23fe03a082 6561 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
mbed_official 573:ad23fe03a082 6562 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
mbed_official 573:ad23fe03a082 6563 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
mbed_official 573:ad23fe03a082 6564 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
mbed_official 573:ad23fe03a082 6565 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
mbed_official 573:ad23fe03a082 6566
mbed_official 573:ad23fe03a082 6567 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
mbed_official 573:ad23fe03a082 6568 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6569 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 610:813dcc80987e 6570 #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6571
mbed_official 573:ad23fe03a082 6572 /****************** Bit definition for SAI_xCLRFR register ******************/
mbed_official 573:ad23fe03a082 6573 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
mbed_official 573:ad23fe03a082 6574 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
mbed_official 573:ad23fe03a082 6575 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
mbed_official 573:ad23fe03a082 6576 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
mbed_official 573:ad23fe03a082 6577 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
mbed_official 573:ad23fe03a082 6578 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
mbed_official 573:ad23fe03a082 6579 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
mbed_official 573:ad23fe03a082 6580
mbed_official 573:ad23fe03a082 6581 /****************** Bit definition for SAI_xDR register *********************/
mbed_official 573:ad23fe03a082 6582 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
mbed_official 573:ad23fe03a082 6583
mbed_official 573:ad23fe03a082 6584 /******************************************************************************/
mbed_official 573:ad23fe03a082 6585 /* */
mbed_official 573:ad23fe03a082 6586 /* SPDIF-RX Interface */
mbed_official 573:ad23fe03a082 6587 /* */
mbed_official 573:ad23fe03a082 6588 /******************************************************************************/
mbed_official 573:ad23fe03a082 6589 /******************** Bit definition for SPDIF_CR register *******************/
mbed_official 573:ad23fe03a082 6590 #define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
mbed_official 573:ad23fe03a082 6591 #define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
mbed_official 573:ad23fe03a082 6592 #define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
mbed_official 573:ad23fe03a082 6593 #define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
mbed_official 573:ad23fe03a082 6594 #define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
mbed_official 573:ad23fe03a082 6595 #define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
mbed_official 573:ad23fe03a082 6596 #define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
mbed_official 573:ad23fe03a082 6597 #define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
mbed_official 573:ad23fe03a082 6598 #define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
mbed_official 573:ad23fe03a082 6599 #define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
mbed_official 573:ad23fe03a082 6600 #define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
mbed_official 573:ad23fe03a082 6601 #define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
mbed_official 573:ad23fe03a082 6602 #define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */
mbed_official 573:ad23fe03a082 6603
mbed_official 573:ad23fe03a082 6604 /******************* Bit definition for SPDIFRX_IMR register *******************/
mbed_official 573:ad23fe03a082 6605 #define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
mbed_official 573:ad23fe03a082 6606 #define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
mbed_official 573:ad23fe03a082 6607 #define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
mbed_official 573:ad23fe03a082 6608 #define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
mbed_official 573:ad23fe03a082 6609 #define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
mbed_official 573:ad23fe03a082 6610 #define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
mbed_official 573:ad23fe03a082 6611 #define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
mbed_official 573:ad23fe03a082 6612
mbed_official 573:ad23fe03a082 6613 /******************* Bit definition for SPDIFRX_SR register *******************/
mbed_official 573:ad23fe03a082 6614 #define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
mbed_official 573:ad23fe03a082 6615 #define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
mbed_official 573:ad23fe03a082 6616 #define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
mbed_official 573:ad23fe03a082 6617 #define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
mbed_official 573:ad23fe03a082 6618 #define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
mbed_official 573:ad23fe03a082 6619 #define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
mbed_official 573:ad23fe03a082 6620 #define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
mbed_official 573:ad23fe03a082 6621 #define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
mbed_official 573:ad23fe03a082 6622 #define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
mbed_official 573:ad23fe03a082 6623 #define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */
mbed_official 573:ad23fe03a082 6624
mbed_official 573:ad23fe03a082 6625 /******************* Bit definition for SPDIFRX_IFCR register *******************/
mbed_official 573:ad23fe03a082 6626 #define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
mbed_official 573:ad23fe03a082 6627 #define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
mbed_official 573:ad23fe03a082 6628 #define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
mbed_official 573:ad23fe03a082 6629 #define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
mbed_official 573:ad23fe03a082 6630
mbed_official 573:ad23fe03a082 6631 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
mbed_official 573:ad23fe03a082 6632 #define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
mbed_official 573:ad23fe03a082 6633 #define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
mbed_official 573:ad23fe03a082 6634 #define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
mbed_official 573:ad23fe03a082 6635 #define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
mbed_official 573:ad23fe03a082 6636 #define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
mbed_official 573:ad23fe03a082 6637 #define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
mbed_official 573:ad23fe03a082 6638
mbed_official 573:ad23fe03a082 6639 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
mbed_official 573:ad23fe03a082 6640 #define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
mbed_official 573:ad23fe03a082 6641 #define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
mbed_official 573:ad23fe03a082 6642 #define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
mbed_official 573:ad23fe03a082 6643 #define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
mbed_official 573:ad23fe03a082 6644 #define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
mbed_official 573:ad23fe03a082 6645 #define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
mbed_official 573:ad23fe03a082 6646
mbed_official 573:ad23fe03a082 6647 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
mbed_official 573:ad23fe03a082 6648 #define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
mbed_official 573:ad23fe03a082 6649 #define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
mbed_official 573:ad23fe03a082 6650
mbed_official 573:ad23fe03a082 6651 /******************* Bit definition for SPDIFRX_CSR register *******************/
mbed_official 573:ad23fe03a082 6652 #define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
mbed_official 573:ad23fe03a082 6653 #define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
mbed_official 573:ad23fe03a082 6654 #define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
mbed_official 573:ad23fe03a082 6655
mbed_official 573:ad23fe03a082 6656 /******************* Bit definition for SPDIFRX_DIR register *******************/
mbed_official 573:ad23fe03a082 6657 #define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
mbed_official 573:ad23fe03a082 6658 #define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
mbed_official 573:ad23fe03a082 6659
mbed_official 573:ad23fe03a082 6660
mbed_official 573:ad23fe03a082 6661 /******************************************************************************/
mbed_official 573:ad23fe03a082 6662 /* */
mbed_official 573:ad23fe03a082 6663 /* SD host Interface */
mbed_official 573:ad23fe03a082 6664 /* */
mbed_official 573:ad23fe03a082 6665 /******************************************************************************/
mbed_official 573:ad23fe03a082 6666 /****************** Bit definition for SDMMC_POWER register ******************/
mbed_official 573:ad23fe03a082 6667 #define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 573:ad23fe03a082 6668 #define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6669 #define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6670
mbed_official 573:ad23fe03a082 6671 /****************** Bit definition for SDMMC_CLKCR register ******************/
mbed_official 573:ad23fe03a082 6672 #define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 573:ad23fe03a082 6673 #define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 573:ad23fe03a082 6674 #define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 573:ad23fe03a082 6675 #define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 573:ad23fe03a082 6676
mbed_official 573:ad23fe03a082 6677 #define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 573:ad23fe03a082 6678 #define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6679 #define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6680
mbed_official 573:ad23fe03a082 6681 #define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */
mbed_official 573:ad23fe03a082 6682 #define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 573:ad23fe03a082 6683
mbed_official 573:ad23fe03a082 6684 /******************* Bit definition for SDMMC_ARG register *******************/
mbed_official 573:ad23fe03a082 6685 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 573:ad23fe03a082 6686
mbed_official 573:ad23fe03a082 6687 /******************* Bit definition for SDMMC_CMD register *******************/
mbed_official 573:ad23fe03a082 6688 #define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 573:ad23fe03a082 6689
mbed_official 573:ad23fe03a082 6690 #define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 573:ad23fe03a082 6691 #define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 6692 #define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 6693
mbed_official 573:ad23fe03a082 6694 #define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 573:ad23fe03a082 6695 #define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 573:ad23fe03a082 6696 #define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 573:ad23fe03a082 6697 #define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 573:ad23fe03a082 6698
mbed_official 573:ad23fe03a082 6699 /***************** Bit definition for SDMMC_RESPCMD register *****************/
mbed_official 573:ad23fe03a082 6700 #define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 573:ad23fe03a082 6701
mbed_official 573:ad23fe03a082 6702 /****************** Bit definition for SDMMC_RESP0 register ******************/
mbed_official 573:ad23fe03a082 6703 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 573:ad23fe03a082 6704
mbed_official 573:ad23fe03a082 6705 /****************** Bit definition for SDMMC_RESP1 register ******************/
mbed_official 573:ad23fe03a082 6706 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 573:ad23fe03a082 6707
mbed_official 573:ad23fe03a082 6708 /****************** Bit definition for SDMMC_RESP2 register ******************/
mbed_official 573:ad23fe03a082 6709 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 573:ad23fe03a082 6710
mbed_official 573:ad23fe03a082 6711 /****************** Bit definition for SDMMC_RESP3 register ******************/
mbed_official 573:ad23fe03a082 6712 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 573:ad23fe03a082 6713
mbed_official 573:ad23fe03a082 6714 /****************** Bit definition for SDMMC_RESP4 register ******************/
mbed_official 573:ad23fe03a082 6715 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 573:ad23fe03a082 6716
mbed_official 573:ad23fe03a082 6717 /****************** Bit definition for SDMMC_DTIMER register *****************/
mbed_official 573:ad23fe03a082 6718 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 573:ad23fe03a082 6719
mbed_official 573:ad23fe03a082 6720 /****************** Bit definition for SDMMC_DLEN register *******************/
mbed_official 573:ad23fe03a082 6721 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 573:ad23fe03a082 6722
mbed_official 573:ad23fe03a082 6723 /****************** Bit definition for SDMMC_DCTRL register ******************/
mbed_official 573:ad23fe03a082 6724 #define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 573:ad23fe03a082 6725 #define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 573:ad23fe03a082 6726 #define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 573:ad23fe03a082 6727 #define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 573:ad23fe03a082 6728
mbed_official 573:ad23fe03a082 6729 #define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 573:ad23fe03a082 6730 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6731 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6732 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 6733 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 6734
mbed_official 573:ad23fe03a082 6735 #define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 573:ad23fe03a082 6736 #define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 573:ad23fe03a082 6737 #define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 573:ad23fe03a082 6738 #define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 573:ad23fe03a082 6739
mbed_official 573:ad23fe03a082 6740 /****************** Bit definition for SDMMC_DCOUNT register *****************/
mbed_official 573:ad23fe03a082 6741 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 573:ad23fe03a082 6742
mbed_official 573:ad23fe03a082 6743 /****************** Bit definition for SDMMC_STA register ********************/
mbed_official 573:ad23fe03a082 6744 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 573:ad23fe03a082 6745 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 573:ad23fe03a082 6746 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 573:ad23fe03a082 6747 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 573:ad23fe03a082 6748 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 573:ad23fe03a082 6749 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 573:ad23fe03a082 6750 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 573:ad23fe03a082 6751 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 573:ad23fe03a082 6752 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 573:ad23fe03a082 6753 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 573:ad23fe03a082 6754 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 573:ad23fe03a082 6755 #define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 573:ad23fe03a082 6756 #define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 573:ad23fe03a082 6757 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 573:ad23fe03a082 6758 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 573:ad23fe03a082 6759 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 573:ad23fe03a082 6760 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 573:ad23fe03a082 6761 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 573:ad23fe03a082 6762 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 573:ad23fe03a082 6763 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 573:ad23fe03a082 6764 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 573:ad23fe03a082 6765 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */
mbed_official 573:ad23fe03a082 6766
mbed_official 573:ad23fe03a082 6767 /******************* Bit definition for SDMMC_ICR register *******************/
mbed_official 573:ad23fe03a082 6768 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 573:ad23fe03a082 6769 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 573:ad23fe03a082 6770 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 573:ad23fe03a082 6771 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 573:ad23fe03a082 6772 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 573:ad23fe03a082 6773 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 573:ad23fe03a082 6774 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 573:ad23fe03a082 6775 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 573:ad23fe03a082 6776 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 573:ad23fe03a082 6777 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 573:ad23fe03a082 6778 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */
mbed_official 573:ad23fe03a082 6779
mbed_official 573:ad23fe03a082 6780 /****************** Bit definition for SDMMC_MASK register *******************/
mbed_official 573:ad23fe03a082 6781 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 573:ad23fe03a082 6782 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 573:ad23fe03a082 6783 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 573:ad23fe03a082 6784 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 573:ad23fe03a082 6785 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 573:ad23fe03a082 6786 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 573:ad23fe03a082 6787 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 573:ad23fe03a082 6788 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 573:ad23fe03a082 6789 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 573:ad23fe03a082 6790 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 573:ad23fe03a082 6791 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 573:ad23fe03a082 6792 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 573:ad23fe03a082 6793 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 573:ad23fe03a082 6794 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 573:ad23fe03a082 6795 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 573:ad23fe03a082 6796 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 573:ad23fe03a082 6797 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 573:ad23fe03a082 6798 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 573:ad23fe03a082 6799 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 573:ad23fe03a082 6800 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 573:ad23fe03a082 6801 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 573:ad23fe03a082 6802 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
mbed_official 573:ad23fe03a082 6803
mbed_official 573:ad23fe03a082 6804 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
mbed_official 573:ad23fe03a082 6805 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 573:ad23fe03a082 6806
mbed_official 573:ad23fe03a082 6807 /****************** Bit definition for SDMMC_FIFO register *******************/
mbed_official 573:ad23fe03a082 6808 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 573:ad23fe03a082 6809
mbed_official 573:ad23fe03a082 6810 /******************************************************************************/
mbed_official 573:ad23fe03a082 6811 /* */
mbed_official 573:ad23fe03a082 6812 /* Serial Peripheral Interface (SPI) */
mbed_official 573:ad23fe03a082 6813 /* */
mbed_official 573:ad23fe03a082 6814 /******************************************************************************/
mbed_official 573:ad23fe03a082 6815 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 573:ad23fe03a082 6816 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 573:ad23fe03a082 6817 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 573:ad23fe03a082 6818 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 573:ad23fe03a082 6819 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 573:ad23fe03a082 6820 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 6821 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 6822 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 6823 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 573:ad23fe03a082 6824 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 573:ad23fe03a082 6825 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 573:ad23fe03a082 6826 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 573:ad23fe03a082 6827 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 573:ad23fe03a082 6828 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 573:ad23fe03a082 6829 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 573:ad23fe03a082 6830 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 573:ad23fe03a082 6831 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 573:ad23fe03a082 6832 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 573:ad23fe03a082 6833
mbed_official 573:ad23fe03a082 6834 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 573:ad23fe03a082 6835 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 573:ad23fe03a082 6836 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 573:ad23fe03a082 6837 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 573:ad23fe03a082 6838 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 573:ad23fe03a082 6839 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 573:ad23fe03a082 6840 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 573:ad23fe03a082 6841 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 573:ad23fe03a082 6842 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 573:ad23fe03a082 6843 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 573:ad23fe03a082 6844 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 6845 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 6846 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 6847 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 6848 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 573:ad23fe03a082 6849 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 573:ad23fe03a082 6850 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 573:ad23fe03a082 6851
mbed_official 573:ad23fe03a082 6852 /******************** Bit definition for SPI_SR register ********************/
mbed_official 573:ad23fe03a082 6853 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 573:ad23fe03a082 6854 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 573:ad23fe03a082 6855 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 573:ad23fe03a082 6856 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 573:ad23fe03a082 6857 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 573:ad23fe03a082 6858 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 573:ad23fe03a082 6859 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 573:ad23fe03a082 6860 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 573:ad23fe03a082 6861 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 573:ad23fe03a082 6862 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 573:ad23fe03a082 6863 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 6864 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 6865 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 573:ad23fe03a082 6866 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 6867 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 6868
mbed_official 573:ad23fe03a082 6869 /******************** Bit definition for SPI_DR register ********************/
mbed_official 573:ad23fe03a082 6870 #define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */
mbed_official 573:ad23fe03a082 6871
mbed_official 573:ad23fe03a082 6872 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 573:ad23fe03a082 6873 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */
mbed_official 573:ad23fe03a082 6874
mbed_official 573:ad23fe03a082 6875 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 573:ad23fe03a082 6876 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */
mbed_official 573:ad23fe03a082 6877
mbed_official 573:ad23fe03a082 6878 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 573:ad23fe03a082 6879 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */
mbed_official 573:ad23fe03a082 6880
mbed_official 573:ad23fe03a082 6881 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 573:ad23fe03a082 6882 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 573:ad23fe03a082 6883 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 573:ad23fe03a082 6884 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6885 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6886 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 573:ad23fe03a082 6887 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 573:ad23fe03a082 6888 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6889 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6890 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 573:ad23fe03a082 6891 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 573:ad23fe03a082 6892 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 6893 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 6894 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 573:ad23fe03a082 6895 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 573:ad23fe03a082 6896 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
mbed_official 573:ad23fe03a082 6897
mbed_official 573:ad23fe03a082 6898 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 573:ad23fe03a082 6899 #define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */
mbed_official 573:ad23fe03a082 6900 #define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */
mbed_official 573:ad23fe03a082 6901 #define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */
mbed_official 573:ad23fe03a082 6902
mbed_official 573:ad23fe03a082 6903
mbed_official 573:ad23fe03a082 6904 /******************************************************************************/
mbed_official 573:ad23fe03a082 6905 /* */
mbed_official 573:ad23fe03a082 6906 /* SYSCFG */
mbed_official 573:ad23fe03a082 6907 /* */
mbed_official 573:ad23fe03a082 6908 /******************************************************************************/
mbed_official 573:ad23fe03a082 6909 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 573:ad23fe03a082 6910 #define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
mbed_official 573:ad23fe03a082 6911
mbed_official 573:ad23fe03a082 6912 #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
mbed_official 573:ad23fe03a082 6913 #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 6914 #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 6915
mbed_official 573:ad23fe03a082 6916 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 573:ad23fe03a082 6917 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 573:ad23fe03a082 6918 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 573:ad23fe03a082 6919 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 573:ad23fe03a082 6920 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 573:ad23fe03a082 6921
mbed_official 573:ad23fe03a082 6922 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
mbed_official 573:ad23fe03a082 6923
mbed_official 573:ad23fe03a082 6924 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 573:ad23fe03a082 6925 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 573:ad23fe03a082 6926 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 573:ad23fe03a082 6927 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 573:ad23fe03a082 6928 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 573:ad23fe03a082 6929 /**
mbed_official 573:ad23fe03a082 6930 * @brief EXTI0 configuration
mbed_official 573:ad23fe03a082 6931 */
mbed_official 573:ad23fe03a082 6932 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 573:ad23fe03a082 6933 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 573:ad23fe03a082 6934 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 573:ad23fe03a082 6935 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 573:ad23fe03a082 6936 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 573:ad23fe03a082 6937 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
mbed_official 573:ad23fe03a082 6938 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
mbed_official 573:ad23fe03a082 6939 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 573:ad23fe03a082 6940 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
mbed_official 573:ad23fe03a082 6941 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
mbed_official 573:ad23fe03a082 6942 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
mbed_official 573:ad23fe03a082 6943
mbed_official 573:ad23fe03a082 6944 /**
mbed_official 573:ad23fe03a082 6945 * @brief EXTI1 configuration
mbed_official 573:ad23fe03a082 6946 */
mbed_official 573:ad23fe03a082 6947 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 573:ad23fe03a082 6948 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 573:ad23fe03a082 6949 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 573:ad23fe03a082 6950 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 573:ad23fe03a082 6951 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 573:ad23fe03a082 6952 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
mbed_official 573:ad23fe03a082 6953 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
mbed_official 573:ad23fe03a082 6954 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 573:ad23fe03a082 6955 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
mbed_official 573:ad23fe03a082 6956 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
mbed_official 573:ad23fe03a082 6957 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
mbed_official 573:ad23fe03a082 6958
mbed_official 573:ad23fe03a082 6959 /**
mbed_official 573:ad23fe03a082 6960 * @brief EXTI2 configuration
mbed_official 573:ad23fe03a082 6961 */
mbed_official 573:ad23fe03a082 6962 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 573:ad23fe03a082 6963 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 573:ad23fe03a082 6964 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 573:ad23fe03a082 6965 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 573:ad23fe03a082 6966 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 573:ad23fe03a082 6967 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
mbed_official 573:ad23fe03a082 6968 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
mbed_official 573:ad23fe03a082 6969 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 573:ad23fe03a082 6970 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
mbed_official 573:ad23fe03a082 6971 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
mbed_official 573:ad23fe03a082 6972 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
mbed_official 573:ad23fe03a082 6973
mbed_official 573:ad23fe03a082 6974 /**
mbed_official 573:ad23fe03a082 6975 * @brief EXTI3 configuration
mbed_official 573:ad23fe03a082 6976 */
mbed_official 573:ad23fe03a082 6977 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 573:ad23fe03a082 6978 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 573:ad23fe03a082 6979 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 573:ad23fe03a082 6980 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 573:ad23fe03a082 6981 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 573:ad23fe03a082 6982 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
mbed_official 573:ad23fe03a082 6983 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
mbed_official 573:ad23fe03a082 6984 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 573:ad23fe03a082 6985 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
mbed_official 573:ad23fe03a082 6986 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
mbed_official 573:ad23fe03a082 6987 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
mbed_official 573:ad23fe03a082 6988
mbed_official 573:ad23fe03a082 6989 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 573:ad23fe03a082 6990 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 573:ad23fe03a082 6991 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 573:ad23fe03a082 6992 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 573:ad23fe03a082 6993 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 573:ad23fe03a082 6994 /**
mbed_official 573:ad23fe03a082 6995 * @brief EXTI4 configuration
mbed_official 573:ad23fe03a082 6996 */
mbed_official 573:ad23fe03a082 6997 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 573:ad23fe03a082 6998 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 573:ad23fe03a082 6999 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 573:ad23fe03a082 7000 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 573:ad23fe03a082 7001 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 573:ad23fe03a082 7002 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
mbed_official 573:ad23fe03a082 7003 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
mbed_official 573:ad23fe03a082 7004 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 573:ad23fe03a082 7005 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
mbed_official 573:ad23fe03a082 7006 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
mbed_official 573:ad23fe03a082 7007 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
mbed_official 573:ad23fe03a082 7008
mbed_official 573:ad23fe03a082 7009 /**
mbed_official 573:ad23fe03a082 7010 * @brief EXTI5 configuration
mbed_official 573:ad23fe03a082 7011 */
mbed_official 573:ad23fe03a082 7012 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 573:ad23fe03a082 7013 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 573:ad23fe03a082 7014 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 573:ad23fe03a082 7015 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 573:ad23fe03a082 7016 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 573:ad23fe03a082 7017 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
mbed_official 573:ad23fe03a082 7018 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
mbed_official 573:ad23fe03a082 7019 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 573:ad23fe03a082 7020 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
mbed_official 573:ad23fe03a082 7021 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
mbed_official 573:ad23fe03a082 7022 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
mbed_official 573:ad23fe03a082 7023
mbed_official 573:ad23fe03a082 7024 /**
mbed_official 573:ad23fe03a082 7025 * @brief EXTI6 configuration
mbed_official 573:ad23fe03a082 7026 */
mbed_official 573:ad23fe03a082 7027 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 573:ad23fe03a082 7028 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 573:ad23fe03a082 7029 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 573:ad23fe03a082 7030 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 573:ad23fe03a082 7031 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 573:ad23fe03a082 7032 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
mbed_official 573:ad23fe03a082 7033 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
mbed_official 573:ad23fe03a082 7034 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 573:ad23fe03a082 7035 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
mbed_official 573:ad23fe03a082 7036 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
mbed_official 573:ad23fe03a082 7037 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
mbed_official 573:ad23fe03a082 7038
mbed_official 573:ad23fe03a082 7039 /**
mbed_official 573:ad23fe03a082 7040 * @brief EXTI7 configuration
mbed_official 573:ad23fe03a082 7041 */
mbed_official 573:ad23fe03a082 7042 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 573:ad23fe03a082 7043 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 573:ad23fe03a082 7044 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 573:ad23fe03a082 7045 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 573:ad23fe03a082 7046 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 573:ad23fe03a082 7047 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
mbed_official 573:ad23fe03a082 7048 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
mbed_official 573:ad23fe03a082 7049 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 573:ad23fe03a082 7050 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
mbed_official 573:ad23fe03a082 7051 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
mbed_official 573:ad23fe03a082 7052 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
mbed_official 573:ad23fe03a082 7053
mbed_official 573:ad23fe03a082 7054 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 573:ad23fe03a082 7055 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 573:ad23fe03a082 7056 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 573:ad23fe03a082 7057 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 573:ad23fe03a082 7058 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 573:ad23fe03a082 7059
mbed_official 573:ad23fe03a082 7060 /**
mbed_official 573:ad23fe03a082 7061 * @brief EXTI8 configuration
mbed_official 573:ad23fe03a082 7062 */
mbed_official 573:ad23fe03a082 7063 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 573:ad23fe03a082 7064 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 573:ad23fe03a082 7065 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 573:ad23fe03a082 7066 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 573:ad23fe03a082 7067 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 573:ad23fe03a082 7068 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
mbed_official 573:ad23fe03a082 7069 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
mbed_official 573:ad23fe03a082 7070 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 573:ad23fe03a082 7071 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
mbed_official 573:ad23fe03a082 7072 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
mbed_official 573:ad23fe03a082 7073
mbed_official 573:ad23fe03a082 7074 /**
mbed_official 573:ad23fe03a082 7075 * @brief EXTI9 configuration
mbed_official 573:ad23fe03a082 7076 */
mbed_official 573:ad23fe03a082 7077 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 573:ad23fe03a082 7078 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 573:ad23fe03a082 7079 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 573:ad23fe03a082 7080 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 573:ad23fe03a082 7081 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 573:ad23fe03a082 7082 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
mbed_official 573:ad23fe03a082 7083 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
mbed_official 573:ad23fe03a082 7084 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 573:ad23fe03a082 7085 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
mbed_official 573:ad23fe03a082 7086 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
mbed_official 573:ad23fe03a082 7087
mbed_official 573:ad23fe03a082 7088 /**
mbed_official 573:ad23fe03a082 7089 * @brief EXTI10 configuration
mbed_official 573:ad23fe03a082 7090 */
mbed_official 573:ad23fe03a082 7091 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 573:ad23fe03a082 7092 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 573:ad23fe03a082 7093 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 573:ad23fe03a082 7094 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 573:ad23fe03a082 7095 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 573:ad23fe03a082 7096 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
mbed_official 573:ad23fe03a082 7097 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
mbed_official 573:ad23fe03a082 7098 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 573:ad23fe03a082 7099 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
mbed_official 573:ad23fe03a082 7100 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
mbed_official 573:ad23fe03a082 7101
mbed_official 573:ad23fe03a082 7102 /**
mbed_official 573:ad23fe03a082 7103 * @brief EXTI11 configuration
mbed_official 573:ad23fe03a082 7104 */
mbed_official 573:ad23fe03a082 7105 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 573:ad23fe03a082 7106 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 573:ad23fe03a082 7107 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 573:ad23fe03a082 7108 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 573:ad23fe03a082 7109 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 573:ad23fe03a082 7110 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
mbed_official 573:ad23fe03a082 7111 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
mbed_official 573:ad23fe03a082 7112 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 573:ad23fe03a082 7113 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
mbed_official 573:ad23fe03a082 7114 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
mbed_official 573:ad23fe03a082 7115
mbed_official 573:ad23fe03a082 7116
mbed_official 573:ad23fe03a082 7117 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 573:ad23fe03a082 7118 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 573:ad23fe03a082 7119 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 573:ad23fe03a082 7120 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 573:ad23fe03a082 7121 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 573:ad23fe03a082 7122 /**
mbed_official 573:ad23fe03a082 7123 * @brief EXTI12 configuration
mbed_official 573:ad23fe03a082 7124 */
mbed_official 573:ad23fe03a082 7125 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 573:ad23fe03a082 7126 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 573:ad23fe03a082 7127 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 573:ad23fe03a082 7128 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 573:ad23fe03a082 7129 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 573:ad23fe03a082 7130 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
mbed_official 573:ad23fe03a082 7131 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
mbed_official 573:ad23fe03a082 7132 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 573:ad23fe03a082 7133 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
mbed_official 573:ad23fe03a082 7134 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
mbed_official 573:ad23fe03a082 7135
mbed_official 573:ad23fe03a082 7136 /**
mbed_official 573:ad23fe03a082 7137 * @brief EXTI13 configuration
mbed_official 573:ad23fe03a082 7138 */
mbed_official 573:ad23fe03a082 7139 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 573:ad23fe03a082 7140 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 573:ad23fe03a082 7141 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 573:ad23fe03a082 7142 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 573:ad23fe03a082 7143 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 573:ad23fe03a082 7144 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
mbed_official 573:ad23fe03a082 7145 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
mbed_official 573:ad23fe03a082 7146 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 573:ad23fe03a082 7147 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
mbed_official 573:ad23fe03a082 7148 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
mbed_official 573:ad23fe03a082 7149
mbed_official 573:ad23fe03a082 7150 /**
mbed_official 573:ad23fe03a082 7151 * @brief EXTI14 configuration
mbed_official 573:ad23fe03a082 7152 */
mbed_official 573:ad23fe03a082 7153 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 573:ad23fe03a082 7154 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 573:ad23fe03a082 7155 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 573:ad23fe03a082 7156 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 573:ad23fe03a082 7157 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 573:ad23fe03a082 7158 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
mbed_official 573:ad23fe03a082 7159 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
mbed_official 573:ad23fe03a082 7160 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 573:ad23fe03a082 7161 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
mbed_official 573:ad23fe03a082 7162 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
mbed_official 573:ad23fe03a082 7163
mbed_official 573:ad23fe03a082 7164 /**
mbed_official 573:ad23fe03a082 7165 * @brief EXTI15 configuration
mbed_official 573:ad23fe03a082 7166 */
mbed_official 573:ad23fe03a082 7167 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 573:ad23fe03a082 7168 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 573:ad23fe03a082 7169 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 573:ad23fe03a082 7170 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 573:ad23fe03a082 7171 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 573:ad23fe03a082 7172 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
mbed_official 573:ad23fe03a082 7173 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
mbed_official 573:ad23fe03a082 7174 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 573:ad23fe03a082 7175 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
mbed_official 573:ad23fe03a082 7176 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
mbed_official 573:ad23fe03a082 7177
mbed_official 573:ad23fe03a082 7178 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 573:ad23fe03a082 7179 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */
mbed_official 573:ad23fe03a082 7180 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
mbed_official 573:ad23fe03a082 7181
mbed_official 573:ad23fe03a082 7182 /******************************************************************************/
mbed_official 573:ad23fe03a082 7183 /* */
mbed_official 573:ad23fe03a082 7184 /* TIM */
mbed_official 573:ad23fe03a082 7185 /* */
mbed_official 573:ad23fe03a082 7186 /******************************************************************************/
mbed_official 573:ad23fe03a082 7187 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 573:ad23fe03a082 7188 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 573:ad23fe03a082 7189 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 573:ad23fe03a082 7190 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 573:ad23fe03a082 7191 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 573:ad23fe03a082 7192 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 573:ad23fe03a082 7193
mbed_official 573:ad23fe03a082 7194 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 573:ad23fe03a082 7195 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7196 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7197
mbed_official 573:ad23fe03a082 7198 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 573:ad23fe03a082 7199
mbed_official 573:ad23fe03a082 7200 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 573:ad23fe03a082 7201 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7202 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7203 #define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */
mbed_official 573:ad23fe03a082 7204
mbed_official 573:ad23fe03a082 7205 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 573:ad23fe03a082 7206 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 573:ad23fe03a082 7207 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 573:ad23fe03a082 7208 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 573:ad23fe03a082 7209
mbed_official 573:ad23fe03a082 7210 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 573:ad23fe03a082 7211 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 573:ad23fe03a082 7212
mbed_official 573:ad23fe03a082 7213 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 573:ad23fe03a082 7214 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7215 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7216 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7217
mbed_official 573:ad23fe03a082 7218 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 573:ad23fe03a082 7219 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7220 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7221 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7222 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7223
mbed_official 573:ad23fe03a082 7224 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 573:ad23fe03a082 7225 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 573:ad23fe03a082 7226 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 573:ad23fe03a082 7227 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 573:ad23fe03a082 7228 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 573:ad23fe03a082 7229 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 573:ad23fe03a082 7230 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 573:ad23fe03a082 7231 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 573:ad23fe03a082 7232
mbed_official 573:ad23fe03a082 7233 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 573:ad23fe03a082 7234 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 573:ad23fe03a082 7235 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7236 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7237 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7238 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7239 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 573:ad23fe03a082 7240
mbed_official 573:ad23fe03a082 7241 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 573:ad23fe03a082 7242 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7243 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7244 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7245
mbed_official 573:ad23fe03a082 7246 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 573:ad23fe03a082 7247
mbed_official 573:ad23fe03a082 7248 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 573:ad23fe03a082 7249 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7250 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7251 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7252 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7253
mbed_official 573:ad23fe03a082 7254 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 573:ad23fe03a082 7255 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7256 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7257
mbed_official 573:ad23fe03a082 7258
mbed_official 573:ad23fe03a082 7259 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 573:ad23fe03a082 7260 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 573:ad23fe03a082 7261
mbed_official 573:ad23fe03a082 7262 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 573:ad23fe03a082 7263 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 573:ad23fe03a082 7264 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 573:ad23fe03a082 7265 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 573:ad23fe03a082 7266 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 573:ad23fe03a082 7267 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 573:ad23fe03a082 7268 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 573:ad23fe03a082 7269 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 573:ad23fe03a082 7270 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 573:ad23fe03a082 7271 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 573:ad23fe03a082 7272 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 573:ad23fe03a082 7273 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 573:ad23fe03a082 7274 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 573:ad23fe03a082 7275 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 573:ad23fe03a082 7276 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 573:ad23fe03a082 7277 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 573:ad23fe03a082 7278
mbed_official 573:ad23fe03a082 7279 /******************** Bit definition for TIM_SR register ********************/
mbed_official 573:ad23fe03a082 7280 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 573:ad23fe03a082 7281 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 573:ad23fe03a082 7282 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 573:ad23fe03a082 7283 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 573:ad23fe03a082 7284 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 573:ad23fe03a082 7285 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 573:ad23fe03a082 7286 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 573:ad23fe03a082 7287 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 573:ad23fe03a082 7288 #define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */
mbed_official 573:ad23fe03a082 7289 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 573:ad23fe03a082 7290 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 573:ad23fe03a082 7291 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 573:ad23fe03a082 7292 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 573:ad23fe03a082 7293
mbed_official 573:ad23fe03a082 7294 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 573:ad23fe03a082 7295 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 573:ad23fe03a082 7296 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 573:ad23fe03a082 7297 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 573:ad23fe03a082 7298 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 573:ad23fe03a082 7299 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 573:ad23fe03a082 7300 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 573:ad23fe03a082 7301 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 573:ad23fe03a082 7302 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 573:ad23fe03a082 7303 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */
mbed_official 573:ad23fe03a082 7304
mbed_official 573:ad23fe03a082 7305 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 573:ad23fe03a082 7306 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 573:ad23fe03a082 7307 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7308 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7309
mbed_official 573:ad23fe03a082 7310 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 573:ad23fe03a082 7311 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 573:ad23fe03a082 7312
mbed_official 573:ad23fe03a082 7313 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 573:ad23fe03a082 7314 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7315 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7316 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7317 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7318
mbed_official 573:ad23fe03a082 7319 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 573:ad23fe03a082 7320
mbed_official 573:ad23fe03a082 7321 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 573:ad23fe03a082 7322 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7323 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7324
mbed_official 573:ad23fe03a082 7325 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 573:ad23fe03a082 7326 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 573:ad23fe03a082 7327
mbed_official 573:ad23fe03a082 7328 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 573:ad23fe03a082 7329 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7330 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7331 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7332 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7333
mbed_official 573:ad23fe03a082 7334 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 573:ad23fe03a082 7335
mbed_official 573:ad23fe03a082 7336 /*----------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 7337
mbed_official 573:ad23fe03a082 7338 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 573:ad23fe03a082 7339 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7340 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7341
mbed_official 573:ad23fe03a082 7342 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 573:ad23fe03a082 7343 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7344 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7345 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7346 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7347
mbed_official 573:ad23fe03a082 7348 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 573:ad23fe03a082 7349 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7350 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7351
mbed_official 573:ad23fe03a082 7352 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 573:ad23fe03a082 7353 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7354 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7355 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7356 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7357
mbed_official 573:ad23fe03a082 7358 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 573:ad23fe03a082 7359 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 573:ad23fe03a082 7360 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7361 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7362
mbed_official 573:ad23fe03a082 7363 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 573:ad23fe03a082 7364 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 573:ad23fe03a082 7365
mbed_official 573:ad23fe03a082 7366 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 573:ad23fe03a082 7367 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7368 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7369 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7370 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7371
mbed_official 573:ad23fe03a082 7372
mbed_official 573:ad23fe03a082 7373
mbed_official 573:ad23fe03a082 7374 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 573:ad23fe03a082 7375
mbed_official 573:ad23fe03a082 7376 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 573:ad23fe03a082 7377 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7378 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7379
mbed_official 573:ad23fe03a082 7380 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 573:ad23fe03a082 7381 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 573:ad23fe03a082 7382
mbed_official 573:ad23fe03a082 7383 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 573:ad23fe03a082 7384 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7385 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7386 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7387 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7388
mbed_official 573:ad23fe03a082 7389 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 573:ad23fe03a082 7390
mbed_official 573:ad23fe03a082 7391 /*----------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 7392
mbed_official 573:ad23fe03a082 7393 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 573:ad23fe03a082 7394 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7395 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7396
mbed_official 573:ad23fe03a082 7397 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 573:ad23fe03a082 7398 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7399 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7400 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7401 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7402
mbed_official 573:ad23fe03a082 7403 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 573:ad23fe03a082 7404 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7405 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7406
mbed_official 573:ad23fe03a082 7407 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 573:ad23fe03a082 7408 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7409 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7410 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7411 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7412
mbed_official 573:ad23fe03a082 7413 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 573:ad23fe03a082 7414 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 573:ad23fe03a082 7415 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 573:ad23fe03a082 7416 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 573:ad23fe03a082 7417 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 573:ad23fe03a082 7418 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 573:ad23fe03a082 7419 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 573:ad23fe03a082 7420 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 573:ad23fe03a082 7421 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 573:ad23fe03a082 7422 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 573:ad23fe03a082 7423 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 573:ad23fe03a082 7424 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 573:ad23fe03a082 7425 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 573:ad23fe03a082 7426 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 573:ad23fe03a082 7427 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 573:ad23fe03a082 7428 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 573:ad23fe03a082 7429 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
mbed_official 573:ad23fe03a082 7430 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
mbed_official 573:ad23fe03a082 7431 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
mbed_official 573:ad23fe03a082 7432 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
mbed_official 573:ad23fe03a082 7433
mbed_official 573:ad23fe03a082 7434
mbed_official 573:ad23fe03a082 7435 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 573:ad23fe03a082 7436 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 573:ad23fe03a082 7437
mbed_official 573:ad23fe03a082 7438 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 573:ad23fe03a082 7439 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 573:ad23fe03a082 7440
mbed_official 573:ad23fe03a082 7441 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 573:ad23fe03a082 7442 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 573:ad23fe03a082 7443
mbed_official 573:ad23fe03a082 7444 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 573:ad23fe03a082 7445 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
mbed_official 573:ad23fe03a082 7446
mbed_official 573:ad23fe03a082 7447 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 573:ad23fe03a082 7448 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 573:ad23fe03a082 7449
mbed_official 573:ad23fe03a082 7450 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 573:ad23fe03a082 7451 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 573:ad23fe03a082 7452
mbed_official 573:ad23fe03a082 7453 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 573:ad23fe03a082 7454 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 573:ad23fe03a082 7455
mbed_official 573:ad23fe03a082 7456 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 573:ad23fe03a082 7457 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 573:ad23fe03a082 7458
mbed_official 573:ad23fe03a082 7459 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 573:ad23fe03a082 7460 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 573:ad23fe03a082 7461 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7462 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7463 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7464 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7465 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 7466 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 7467 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 7468 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 7469
mbed_official 573:ad23fe03a082 7470 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 573:ad23fe03a082 7471 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7472 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7473
mbed_official 573:ad23fe03a082 7474 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 573:ad23fe03a082 7475 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 573:ad23fe03a082 7476 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
mbed_official 573:ad23fe03a082 7477 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
mbed_official 573:ad23fe03a082 7478 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 573:ad23fe03a082 7479 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 573:ad23fe03a082 7480 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
mbed_official 573:ad23fe03a082 7481 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
mbed_official 573:ad23fe03a082 7482 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
mbed_official 573:ad23fe03a082 7483 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
mbed_official 573:ad23fe03a082 7484
mbed_official 573:ad23fe03a082 7485 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 573:ad23fe03a082 7486 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 573:ad23fe03a082 7487 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7488 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7489 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7490 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7491 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 7492
mbed_official 573:ad23fe03a082 7493 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 573:ad23fe03a082 7494 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7495 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7496 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7497 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7498 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 7499
mbed_official 573:ad23fe03a082 7500 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 573:ad23fe03a082 7501 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 573:ad23fe03a082 7502
mbed_official 573:ad23fe03a082 7503 /******************* Bit definition for TIM_OR register *********************/
mbed_official 573:ad23fe03a082 7504 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 573:ad23fe03a082 7505 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7506 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7507 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 573:ad23fe03a082 7508 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7509 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7510
mbed_official 573:ad23fe03a082 7511 /****************** Bit definition for TIM_CCMR3 register *******************/
mbed_official 573:ad23fe03a082 7512 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
mbed_official 573:ad23fe03a082 7513 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
mbed_official 573:ad23fe03a082 7514
mbed_official 573:ad23fe03a082 7515 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
mbed_official 573:ad23fe03a082 7516 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7517 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7518 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7519 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7520
mbed_official 573:ad23fe03a082 7521 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
mbed_official 573:ad23fe03a082 7522
mbed_official 573:ad23fe03a082 7523 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 573:ad23fe03a082 7524 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 573:ad23fe03a082 7525
mbed_official 573:ad23fe03a082 7526 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 573:ad23fe03a082 7527 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7528 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7529 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7530 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7531
mbed_official 573:ad23fe03a082 7532 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 573:ad23fe03a082 7533
mbed_official 573:ad23fe03a082 7534 /******************* Bit definition for TIM_CCR5 register *******************/
mbed_official 573:ad23fe03a082 7535 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
mbed_official 573:ad23fe03a082 7536 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
mbed_official 573:ad23fe03a082 7537 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
mbed_official 573:ad23fe03a082 7538 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
mbed_official 573:ad23fe03a082 7539
mbed_official 573:ad23fe03a082 7540 /******************* Bit definition for TIM_CCR6 register *******************/
mbed_official 573:ad23fe03a082 7541 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
mbed_official 573:ad23fe03a082 7542
mbed_official 573:ad23fe03a082 7543 /******************************************************************************/
mbed_official 573:ad23fe03a082 7544 /* */
mbed_official 573:ad23fe03a082 7545 /* Low Power Timer (LPTIM) */
mbed_official 573:ad23fe03a082 7546 /* */
mbed_official 573:ad23fe03a082 7547 /******************************************************************************/
mbed_official 573:ad23fe03a082 7548 /****************** Bit definition for LPTIM_ISR register *******************/
mbed_official 573:ad23fe03a082 7549 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
mbed_official 573:ad23fe03a082 7550 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
mbed_official 573:ad23fe03a082 7551 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
mbed_official 573:ad23fe03a082 7552 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
mbed_official 573:ad23fe03a082 7553 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
mbed_official 573:ad23fe03a082 7554 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
mbed_official 573:ad23fe03a082 7555 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
mbed_official 573:ad23fe03a082 7556
mbed_official 573:ad23fe03a082 7557 /****************** Bit definition for LPTIM_ICR register *******************/
mbed_official 573:ad23fe03a082 7558 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
mbed_official 573:ad23fe03a082 7559 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
mbed_official 573:ad23fe03a082 7560 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
mbed_official 573:ad23fe03a082 7561 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
mbed_official 573:ad23fe03a082 7562 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
mbed_official 573:ad23fe03a082 7563 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
mbed_official 573:ad23fe03a082 7564 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
mbed_official 573:ad23fe03a082 7565
mbed_official 573:ad23fe03a082 7566 /****************** Bit definition for LPTIM_IER register ********************/
mbed_official 573:ad23fe03a082 7567 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
mbed_official 573:ad23fe03a082 7568 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
mbed_official 573:ad23fe03a082 7569 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
mbed_official 573:ad23fe03a082 7570 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
mbed_official 573:ad23fe03a082 7571 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
mbed_official 573:ad23fe03a082 7572 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
mbed_official 573:ad23fe03a082 7573 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
mbed_official 573:ad23fe03a082 7574
mbed_official 573:ad23fe03a082 7575 /****************** Bit definition for LPTIM_CFGR register *******************/
mbed_official 573:ad23fe03a082 7576 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
mbed_official 573:ad23fe03a082 7577
mbed_official 573:ad23fe03a082 7578 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
mbed_official 573:ad23fe03a082 7579 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7580 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7581
mbed_official 573:ad23fe03a082 7582 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
mbed_official 573:ad23fe03a082 7583 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7584 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7585
mbed_official 573:ad23fe03a082 7586 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
mbed_official 573:ad23fe03a082 7587 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7588 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7589
mbed_official 573:ad23fe03a082 7590 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
mbed_official 573:ad23fe03a082 7591 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7592 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7593 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 7594
mbed_official 573:ad23fe03a082 7595 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
mbed_official 573:ad23fe03a082 7596 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7597 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7598 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 7599
mbed_official 573:ad23fe03a082 7600 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
mbed_official 573:ad23fe03a082 7601 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7602 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7603
mbed_official 573:ad23fe03a082 7604 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
mbed_official 573:ad23fe03a082 7605 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
mbed_official 573:ad23fe03a082 7606 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
mbed_official 573:ad23fe03a082 7607 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
mbed_official 573:ad23fe03a082 7608 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
mbed_official 573:ad23fe03a082 7609 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
mbed_official 573:ad23fe03a082 7610
mbed_official 573:ad23fe03a082 7611 /****************** Bit definition for LPTIM_CR register ********************/
mbed_official 573:ad23fe03a082 7612 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
mbed_official 573:ad23fe03a082 7613 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
mbed_official 573:ad23fe03a082 7614 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
mbed_official 573:ad23fe03a082 7615
mbed_official 573:ad23fe03a082 7616 /****************** Bit definition for LPTIM_CMP register *******************/
mbed_official 573:ad23fe03a082 7617 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
mbed_official 573:ad23fe03a082 7618
mbed_official 573:ad23fe03a082 7619 /****************** Bit definition for LPTIM_ARR register *******************/
mbed_official 573:ad23fe03a082 7620 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
mbed_official 573:ad23fe03a082 7621
mbed_official 573:ad23fe03a082 7622 /****************** Bit definition for LPTIM_CNT register *******************/
mbed_official 573:ad23fe03a082 7623 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
mbed_official 573:ad23fe03a082 7624 /******************************************************************************/
mbed_official 573:ad23fe03a082 7625 /* */
mbed_official 573:ad23fe03a082 7626 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 573:ad23fe03a082 7627 /* */
mbed_official 573:ad23fe03a082 7628 /******************************************************************************/
mbed_official 573:ad23fe03a082 7629 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 573:ad23fe03a082 7630 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 573:ad23fe03a082 7631 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 573:ad23fe03a082 7632 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 573:ad23fe03a082 7633 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 573:ad23fe03a082 7634 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 573:ad23fe03a082 7635 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 573:ad23fe03a082 7636 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 573:ad23fe03a082 7637 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 573:ad23fe03a082 7638 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 573:ad23fe03a082 7639 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 573:ad23fe03a082 7640 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 573:ad23fe03a082 7641 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
mbed_official 573:ad23fe03a082 7642 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
mbed_official 573:ad23fe03a082 7643 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 573:ad23fe03a082 7644 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 573:ad23fe03a082 7645 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 573:ad23fe03a082 7646 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 573:ad23fe03a082 7647 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7648 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7649 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 7650 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 7651 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 7652 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 573:ad23fe03a082 7653 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7654 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7655 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 7656 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 573:ad23fe03a082 7657 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 573:ad23fe03a082 7658 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 573:ad23fe03a082 7659 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 573:ad23fe03a082 7660 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
mbed_official 573:ad23fe03a082 7661
mbed_official 573:ad23fe03a082 7662 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 573:ad23fe03a082 7663 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 573:ad23fe03a082 7664 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 573:ad23fe03a082 7665 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 573:ad23fe03a082 7666 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 573:ad23fe03a082 7667 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 573:ad23fe03a082 7668 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 573:ad23fe03a082 7669 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 573:ad23fe03a082 7670 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 573:ad23fe03a082 7671 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7672 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7673 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 573:ad23fe03a082 7674 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 573:ad23fe03a082 7675 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 573:ad23fe03a082 7676 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 573:ad23fe03a082 7677 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 573:ad23fe03a082 7678 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 573:ad23fe03a082 7679 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */
mbed_official 573:ad23fe03a082 7680 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 573:ad23fe03a082 7681 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7682 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7683 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 573:ad23fe03a082 7684 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 573:ad23fe03a082 7685
mbed_official 573:ad23fe03a082 7686 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 573:ad23fe03a082 7687 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 573:ad23fe03a082 7688 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 573:ad23fe03a082 7689 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 573:ad23fe03a082 7690 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 573:ad23fe03a082 7691 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 573:ad23fe03a082 7692 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 573:ad23fe03a082 7693 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 573:ad23fe03a082 7694 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 573:ad23fe03a082 7695 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 573:ad23fe03a082 7696 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 573:ad23fe03a082 7697 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 573:ad23fe03a082 7698 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 573:ad23fe03a082 7699 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 573:ad23fe03a082 7700 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 573:ad23fe03a082 7701 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 573:ad23fe03a082 7702 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 573:ad23fe03a082 7703 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 573:ad23fe03a082 7704 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 573:ad23fe03a082 7705 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 573:ad23fe03a082 7706 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 573:ad23fe03a082 7707
mbed_official 573:ad23fe03a082 7708 /****************** Bit definition for USART_BRR register *******************/
mbed_official 573:ad23fe03a082 7709 #define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
mbed_official 573:ad23fe03a082 7710 #define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
mbed_official 573:ad23fe03a082 7711
mbed_official 573:ad23fe03a082 7712 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 573:ad23fe03a082 7713 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 573:ad23fe03a082 7714 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 573:ad23fe03a082 7715
mbed_official 573:ad23fe03a082 7716
mbed_official 573:ad23fe03a082 7717 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 573:ad23fe03a082 7718 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 573:ad23fe03a082 7719 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 573:ad23fe03a082 7720
mbed_official 573:ad23fe03a082 7721 /******************* Bit definition for USART_RQR register ******************/
mbed_official 573:ad23fe03a082 7722 #define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */
mbed_official 573:ad23fe03a082 7723 #define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */
mbed_official 573:ad23fe03a082 7724 #define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */
mbed_official 573:ad23fe03a082 7725 #define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */
mbed_official 573:ad23fe03a082 7726 #define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */
mbed_official 573:ad23fe03a082 7727
mbed_official 573:ad23fe03a082 7728 /******************* Bit definition for USART_ISR register ******************/
mbed_official 573:ad23fe03a082 7729 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 573:ad23fe03a082 7730 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 573:ad23fe03a082 7731 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 573:ad23fe03a082 7732 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 573:ad23fe03a082 7733 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 573:ad23fe03a082 7734 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 573:ad23fe03a082 7735 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 573:ad23fe03a082 7736 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 573:ad23fe03a082 7737 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 573:ad23fe03a082 7738 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 573:ad23fe03a082 7739 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 573:ad23fe03a082 7740 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 573:ad23fe03a082 7741 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 573:ad23fe03a082 7742 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 573:ad23fe03a082 7743 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 573:ad23fe03a082 7744 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 573:ad23fe03a082 7745 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 573:ad23fe03a082 7746 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 573:ad23fe03a082 7747 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 573:ad23fe03a082 7748 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 573:ad23fe03a082 7749 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 573:ad23fe03a082 7750 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 573:ad23fe03a082 7751
mbed_official 573:ad23fe03a082 7752 /******************* Bit definition for USART_ICR register ******************/
mbed_official 573:ad23fe03a082 7753 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 573:ad23fe03a082 7754 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 573:ad23fe03a082 7755 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 573:ad23fe03a082 7756 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 573:ad23fe03a082 7757 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 573:ad23fe03a082 7758 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 573:ad23fe03a082 7759 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 573:ad23fe03a082 7760 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 573:ad23fe03a082 7761 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 573:ad23fe03a082 7762 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 573:ad23fe03a082 7763 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 573:ad23fe03a082 7764 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 573:ad23fe03a082 7765
mbed_official 573:ad23fe03a082 7766 /******************* Bit definition for USART_RDR register ******************/
mbed_official 573:ad23fe03a082 7767 #define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 573:ad23fe03a082 7768
mbed_official 573:ad23fe03a082 7769 /******************* Bit definition for USART_TDR register ******************/
mbed_official 573:ad23fe03a082 7770 #define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 573:ad23fe03a082 7771
mbed_official 573:ad23fe03a082 7772 /******************************************************************************/
mbed_official 573:ad23fe03a082 7773 /* */
mbed_official 573:ad23fe03a082 7774 /* Window WATCHDOG */
mbed_official 573:ad23fe03a082 7775 /* */
mbed_official 573:ad23fe03a082 7776 /******************************************************************************/
mbed_official 573:ad23fe03a082 7777 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 573:ad23fe03a082 7778 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 573:ad23fe03a082 7779 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7780 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7781 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7782 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7783 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 7784 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 7785 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 7786
mbed_official 573:ad23fe03a082 7787 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 573:ad23fe03a082 7788
mbed_official 573:ad23fe03a082 7789 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 573:ad23fe03a082 7790 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 573:ad23fe03a082 7791 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7792 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7793 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 7794 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 7795 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 7796 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 7797 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 7798
mbed_official 573:ad23fe03a082 7799 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 573:ad23fe03a082 7800 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7801 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7802
mbed_official 573:ad23fe03a082 7803 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 573:ad23fe03a082 7804
mbed_official 573:ad23fe03a082 7805 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 573:ad23fe03a082 7806 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 573:ad23fe03a082 7807
mbed_official 573:ad23fe03a082 7808 /******************************************************************************/
mbed_official 573:ad23fe03a082 7809 /* */
mbed_official 573:ad23fe03a082 7810 /* DBG */
mbed_official 573:ad23fe03a082 7811 /* */
mbed_official 573:ad23fe03a082 7812 /******************************************************************************/
mbed_official 573:ad23fe03a082 7813 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 573:ad23fe03a082 7814 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 573:ad23fe03a082 7815 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 573:ad23fe03a082 7816
mbed_official 573:ad23fe03a082 7817 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 573:ad23fe03a082 7818 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 7819 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 7820 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 7821 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 7822
mbed_official 573:ad23fe03a082 7823 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 573:ad23fe03a082 7824 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 7825 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 7826
mbed_official 573:ad23fe03a082 7827 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 573:ad23fe03a082 7828 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 7829 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 7830 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 7831 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 7832 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 7833 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 7834 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 7835 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 7836 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 573:ad23fe03a082 7837 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 7838 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 7839 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 7840 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 7841 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 7842 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 7843 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 7844 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 7845
mbed_official 573:ad23fe03a082 7846 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 573:ad23fe03a082 7847 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 7848 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 7849 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 7850 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 573:ad23fe03a082 7851 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 573:ad23fe03a082 7852
mbed_official 573:ad23fe03a082 7853 /******************************************************************************/
mbed_official 573:ad23fe03a082 7854 /* */
mbed_official 573:ad23fe03a082 7855 /* Ethernet MAC Registers bits definitions */
mbed_official 573:ad23fe03a082 7856 /* */
mbed_official 573:ad23fe03a082 7857 /******************************************************************************/
mbed_official 573:ad23fe03a082 7858 /* Bit definition for Ethernet MAC Control Register register */
mbed_official 573:ad23fe03a082 7859 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
mbed_official 573:ad23fe03a082 7860 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
mbed_official 573:ad23fe03a082 7861 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
mbed_official 573:ad23fe03a082 7862 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
mbed_official 573:ad23fe03a082 7863 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
mbed_official 573:ad23fe03a082 7864 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
mbed_official 573:ad23fe03a082 7865 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
mbed_official 573:ad23fe03a082 7866 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
mbed_official 573:ad23fe03a082 7867 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
mbed_official 573:ad23fe03a082 7868 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
mbed_official 573:ad23fe03a082 7869 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
mbed_official 573:ad23fe03a082 7870 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
mbed_official 573:ad23fe03a082 7871 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
mbed_official 573:ad23fe03a082 7872 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
mbed_official 573:ad23fe03a082 7873 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
mbed_official 573:ad23fe03a082 7874 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
mbed_official 573:ad23fe03a082 7875 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
mbed_official 573:ad23fe03a082 7876 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
mbed_official 573:ad23fe03a082 7877 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
mbed_official 573:ad23fe03a082 7878 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
mbed_official 573:ad23fe03a082 7879 a transmission attempt during retries after a collision: 0 =< r <2^k */
mbed_official 573:ad23fe03a082 7880 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
mbed_official 573:ad23fe03a082 7881 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
mbed_official 573:ad23fe03a082 7882 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
mbed_official 573:ad23fe03a082 7883 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
mbed_official 573:ad23fe03a082 7884 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
mbed_official 573:ad23fe03a082 7885 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
mbed_official 573:ad23fe03a082 7886 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
mbed_official 573:ad23fe03a082 7887
mbed_official 573:ad23fe03a082 7888 /* Bit definition for Ethernet MAC Frame Filter Register */
mbed_official 573:ad23fe03a082 7889 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
mbed_official 573:ad23fe03a082 7890 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
mbed_official 573:ad23fe03a082 7891 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
mbed_official 573:ad23fe03a082 7892 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
mbed_official 573:ad23fe03a082 7893 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
mbed_official 573:ad23fe03a082 7894 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
mbed_official 573:ad23fe03a082 7895 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 573:ad23fe03a082 7896 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
mbed_official 573:ad23fe03a082 7897 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
mbed_official 573:ad23fe03a082 7898 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
mbed_official 573:ad23fe03a082 7899 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
mbed_official 573:ad23fe03a082 7900 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
mbed_official 573:ad23fe03a082 7901 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
mbed_official 573:ad23fe03a082 7902 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
mbed_official 573:ad23fe03a082 7903
mbed_official 573:ad23fe03a082 7904 /* Bit definition for Ethernet MAC Hash Table High Register */
mbed_official 573:ad23fe03a082 7905 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
mbed_official 573:ad23fe03a082 7906
mbed_official 573:ad23fe03a082 7907 /* Bit definition for Ethernet MAC Hash Table Low Register */
mbed_official 573:ad23fe03a082 7908 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
mbed_official 573:ad23fe03a082 7909
mbed_official 573:ad23fe03a082 7910 /* Bit definition for Ethernet MAC MII Address Register */
mbed_official 573:ad23fe03a082 7911 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
mbed_official 573:ad23fe03a082 7912 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
mbed_official 573:ad23fe03a082 7913 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
mbed_official 573:ad23fe03a082 7914 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
mbed_official 573:ad23fe03a082 7915 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
mbed_official 573:ad23fe03a082 7916 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
mbed_official 573:ad23fe03a082 7917 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
mbed_official 573:ad23fe03a082 7918 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
mbed_official 573:ad23fe03a082 7919 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
mbed_official 573:ad23fe03a082 7920 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
mbed_official 573:ad23fe03a082 7921
mbed_official 573:ad23fe03a082 7922 /* Bit definition for Ethernet MAC MII Data Register */
mbed_official 573:ad23fe03a082 7923 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
mbed_official 573:ad23fe03a082 7924
mbed_official 573:ad23fe03a082 7925 /* Bit definition for Ethernet MAC Flow Control Register */
mbed_official 573:ad23fe03a082 7926 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
mbed_official 573:ad23fe03a082 7927 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
mbed_official 573:ad23fe03a082 7928 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
mbed_official 573:ad23fe03a082 7929 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
mbed_official 573:ad23fe03a082 7930 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
mbed_official 573:ad23fe03a082 7931 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
mbed_official 573:ad23fe03a082 7932 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
mbed_official 573:ad23fe03a082 7933 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
mbed_official 573:ad23fe03a082 7934 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
mbed_official 573:ad23fe03a082 7935 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
mbed_official 573:ad23fe03a082 7936 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
mbed_official 573:ad23fe03a082 7937
mbed_official 573:ad23fe03a082 7938 /* Bit definition for Ethernet MAC VLAN Tag Register */
mbed_official 573:ad23fe03a082 7939 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
mbed_official 573:ad23fe03a082 7940 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
mbed_official 573:ad23fe03a082 7941
mbed_official 573:ad23fe03a082 7942 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
mbed_official 573:ad23fe03a082 7943 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
mbed_official 573:ad23fe03a082 7944 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
mbed_official 573:ad23fe03a082 7945 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
mbed_official 573:ad23fe03a082 7946 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
mbed_official 573:ad23fe03a082 7947 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
mbed_official 573:ad23fe03a082 7948 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
mbed_official 573:ad23fe03a082 7949 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
mbed_official 573:ad23fe03a082 7950 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
mbed_official 573:ad23fe03a082 7951 RSVD - Filter1 Command - RSVD - Filter0 Command
mbed_official 573:ad23fe03a082 7952 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
mbed_official 573:ad23fe03a082 7953 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
mbed_official 573:ad23fe03a082 7954 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
mbed_official 573:ad23fe03a082 7955
mbed_official 573:ad23fe03a082 7956 /* Bit definition for Ethernet MAC PMT Control and Status Register */
mbed_official 573:ad23fe03a082 7957 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
mbed_official 573:ad23fe03a082 7958 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
mbed_official 573:ad23fe03a082 7959 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
mbed_official 573:ad23fe03a082 7960 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
mbed_official 573:ad23fe03a082 7961 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
mbed_official 573:ad23fe03a082 7962 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
mbed_official 573:ad23fe03a082 7963 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
mbed_official 573:ad23fe03a082 7964
mbed_official 573:ad23fe03a082 7965 /* Bit definition for Ethernet MAC Status Register */
mbed_official 573:ad23fe03a082 7966 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
mbed_official 573:ad23fe03a082 7967 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
mbed_official 573:ad23fe03a082 7968 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
mbed_official 573:ad23fe03a082 7969 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
mbed_official 573:ad23fe03a082 7970 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
mbed_official 573:ad23fe03a082 7971
mbed_official 573:ad23fe03a082 7972 /* Bit definition for Ethernet MAC Interrupt Mask Register */
mbed_official 573:ad23fe03a082 7973 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
mbed_official 573:ad23fe03a082 7974 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
mbed_official 573:ad23fe03a082 7975
mbed_official 573:ad23fe03a082 7976 /* Bit definition for Ethernet MAC Address0 High Register */
mbed_official 573:ad23fe03a082 7977 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
mbed_official 573:ad23fe03a082 7978
mbed_official 573:ad23fe03a082 7979 /* Bit definition for Ethernet MAC Address0 Low Register */
mbed_official 573:ad23fe03a082 7980 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
mbed_official 573:ad23fe03a082 7981
mbed_official 573:ad23fe03a082 7982 /* Bit definition for Ethernet MAC Address1 High Register */
mbed_official 573:ad23fe03a082 7983 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 573:ad23fe03a082 7984 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 573:ad23fe03a082 7985 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
mbed_official 573:ad23fe03a082 7986 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 573:ad23fe03a082 7987 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 573:ad23fe03a082 7988 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 573:ad23fe03a082 7989 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 573:ad23fe03a082 7990 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 573:ad23fe03a082 7991 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
mbed_official 573:ad23fe03a082 7992 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 573:ad23fe03a082 7993
mbed_official 573:ad23fe03a082 7994 /* Bit definition for Ethernet MAC Address1 Low Register */
mbed_official 573:ad23fe03a082 7995 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
mbed_official 573:ad23fe03a082 7996
mbed_official 573:ad23fe03a082 7997 /* Bit definition for Ethernet MAC Address2 High Register */
mbed_official 573:ad23fe03a082 7998 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 573:ad23fe03a082 7999 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 573:ad23fe03a082 8000 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 573:ad23fe03a082 8001 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 573:ad23fe03a082 8002 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 573:ad23fe03a082 8003 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 573:ad23fe03a082 8004 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 573:ad23fe03a082 8005 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 573:ad23fe03a082 8006 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 573:ad23fe03a082 8007 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 573:ad23fe03a082 8008
mbed_official 573:ad23fe03a082 8009 /* Bit definition for Ethernet MAC Address2 Low Register */
mbed_official 573:ad23fe03a082 8010 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
mbed_official 573:ad23fe03a082 8011
mbed_official 573:ad23fe03a082 8012 /* Bit definition for Ethernet MAC Address3 High Register */
mbed_official 573:ad23fe03a082 8013 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 573:ad23fe03a082 8014 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 573:ad23fe03a082 8015 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 573:ad23fe03a082 8016 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 573:ad23fe03a082 8017 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 573:ad23fe03a082 8018 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 573:ad23fe03a082 8019 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 573:ad23fe03a082 8020 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 573:ad23fe03a082 8021 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 573:ad23fe03a082 8022 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
mbed_official 573:ad23fe03a082 8023
mbed_official 573:ad23fe03a082 8024 /* Bit definition for Ethernet MAC Address3 Low Register */
mbed_official 573:ad23fe03a082 8025 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
mbed_official 573:ad23fe03a082 8026
mbed_official 573:ad23fe03a082 8027 /******************************************************************************/
mbed_official 573:ad23fe03a082 8028 /* Ethernet MMC Registers bits definition */
mbed_official 573:ad23fe03a082 8029 /******************************************************************************/
mbed_official 573:ad23fe03a082 8030
mbed_official 573:ad23fe03a082 8031 /* Bit definition for Ethernet MMC Contol Register */
mbed_official 573:ad23fe03a082 8032 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
mbed_official 573:ad23fe03a082 8033 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
mbed_official 573:ad23fe03a082 8034 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
mbed_official 573:ad23fe03a082 8035 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
mbed_official 573:ad23fe03a082 8036 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
mbed_official 573:ad23fe03a082 8037 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
mbed_official 573:ad23fe03a082 8038
mbed_official 573:ad23fe03a082 8039 /* Bit definition for Ethernet MMC Receive Interrupt Register */
mbed_official 573:ad23fe03a082 8040 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8041 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8042 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8043
mbed_official 573:ad23fe03a082 8044 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
mbed_official 573:ad23fe03a082 8045 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8046 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8047 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8048
mbed_official 573:ad23fe03a082 8049 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
mbed_official 573:ad23fe03a082 8050 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8051 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8052 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8053
mbed_official 573:ad23fe03a082 8054 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
mbed_official 573:ad23fe03a082 8055 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8056 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8057 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 8058
mbed_official 573:ad23fe03a082 8059 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
mbed_official 573:ad23fe03a082 8060 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
mbed_official 573:ad23fe03a082 8061
mbed_official 573:ad23fe03a082 8062 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
mbed_official 573:ad23fe03a082 8063 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
mbed_official 573:ad23fe03a082 8064
mbed_official 573:ad23fe03a082 8065 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
mbed_official 573:ad23fe03a082 8066 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
mbed_official 573:ad23fe03a082 8067
mbed_official 573:ad23fe03a082 8068 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
mbed_official 573:ad23fe03a082 8069 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
mbed_official 573:ad23fe03a082 8070
mbed_official 573:ad23fe03a082 8071 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
mbed_official 573:ad23fe03a082 8072 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
mbed_official 573:ad23fe03a082 8073
mbed_official 573:ad23fe03a082 8074 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
mbed_official 573:ad23fe03a082 8075 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
mbed_official 573:ad23fe03a082 8076
mbed_official 573:ad23fe03a082 8077 /******************************************************************************/
mbed_official 573:ad23fe03a082 8078 /* Ethernet PTP Registers bits definition */
mbed_official 573:ad23fe03a082 8079 /******************************************************************************/
mbed_official 573:ad23fe03a082 8080
mbed_official 573:ad23fe03a082 8081 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
mbed_official 573:ad23fe03a082 8082 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
mbed_official 573:ad23fe03a082 8083 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
mbed_official 573:ad23fe03a082 8084 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
mbed_official 573:ad23fe03a082 8085 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
mbed_official 573:ad23fe03a082 8086 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
mbed_official 573:ad23fe03a082 8087 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
mbed_official 573:ad23fe03a082 8088 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
mbed_official 573:ad23fe03a082 8089 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
mbed_official 573:ad23fe03a082 8090 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
mbed_official 573:ad23fe03a082 8091
mbed_official 573:ad23fe03a082 8092 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
mbed_official 573:ad23fe03a082 8093 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
mbed_official 573:ad23fe03a082 8094 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
mbed_official 573:ad23fe03a082 8095 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
mbed_official 573:ad23fe03a082 8096 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
mbed_official 573:ad23fe03a082 8097 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
mbed_official 573:ad23fe03a082 8098
mbed_official 573:ad23fe03a082 8099 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
mbed_official 573:ad23fe03a082 8100 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
mbed_official 573:ad23fe03a082 8101
mbed_official 573:ad23fe03a082 8102 /* Bit definition for Ethernet PTP Time Stamp High Register */
mbed_official 573:ad23fe03a082 8103 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
mbed_official 573:ad23fe03a082 8104
mbed_official 573:ad23fe03a082 8105 /* Bit definition for Ethernet PTP Time Stamp Low Register */
mbed_official 573:ad23fe03a082 8106 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
mbed_official 573:ad23fe03a082 8107 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
mbed_official 573:ad23fe03a082 8108
mbed_official 573:ad23fe03a082 8109 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
mbed_official 573:ad23fe03a082 8110 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
mbed_official 573:ad23fe03a082 8111
mbed_official 573:ad23fe03a082 8112 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
mbed_official 573:ad23fe03a082 8113 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
mbed_official 573:ad23fe03a082 8114 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
mbed_official 573:ad23fe03a082 8115
mbed_official 573:ad23fe03a082 8116 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
mbed_official 573:ad23fe03a082 8117 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
mbed_official 573:ad23fe03a082 8118
mbed_official 573:ad23fe03a082 8119 /* Bit definition for Ethernet PTP Target Time High Register */
mbed_official 573:ad23fe03a082 8120 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
mbed_official 573:ad23fe03a082 8121
mbed_official 573:ad23fe03a082 8122 /* Bit definition for Ethernet PTP Target Time Low Register */
mbed_official 573:ad23fe03a082 8123 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
mbed_official 573:ad23fe03a082 8124
mbed_official 573:ad23fe03a082 8125 /* Bit definition for Ethernet PTP Time Stamp Status Register */
mbed_official 573:ad23fe03a082 8126 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
mbed_official 573:ad23fe03a082 8127 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
mbed_official 573:ad23fe03a082 8128
mbed_official 573:ad23fe03a082 8129 /******************************************************************************/
mbed_official 573:ad23fe03a082 8130 /* Ethernet DMA Registers bits definition */
mbed_official 573:ad23fe03a082 8131 /******************************************************************************/
mbed_official 573:ad23fe03a082 8132
mbed_official 573:ad23fe03a082 8133 /* Bit definition for Ethernet DMA Bus Mode Register */
mbed_official 573:ad23fe03a082 8134 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
mbed_official 573:ad23fe03a082 8135 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
mbed_official 573:ad23fe03a082 8136 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
mbed_official 573:ad23fe03a082 8137 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
mbed_official 573:ad23fe03a082 8138 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 573:ad23fe03a082 8139 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 573:ad23fe03a082 8140 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 573:ad23fe03a082 8141 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 573:ad23fe03a082 8142 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 573:ad23fe03a082 8143 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 573:ad23fe03a082 8144 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 573:ad23fe03a082 8145 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 573:ad23fe03a082 8146 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 573:ad23fe03a082 8147 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 573:ad23fe03a082 8148 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 573:ad23fe03a082 8149 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 573:ad23fe03a082 8150 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
mbed_official 573:ad23fe03a082 8151 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 573:ad23fe03a082 8152 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
mbed_official 573:ad23fe03a082 8153 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
mbed_official 573:ad23fe03a082 8154 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
mbed_official 573:ad23fe03a082 8155 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 573:ad23fe03a082 8156 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
mbed_official 573:ad23fe03a082 8157 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 573:ad23fe03a082 8158 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 573:ad23fe03a082 8159 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 573:ad23fe03a082 8160 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 573:ad23fe03a082 8161 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 573:ad23fe03a082 8162 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 573:ad23fe03a082 8163 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 573:ad23fe03a082 8164 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 573:ad23fe03a082 8165 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 573:ad23fe03a082 8166 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 573:ad23fe03a082 8167 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 573:ad23fe03a082 8168 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 573:ad23fe03a082 8169 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
mbed_official 573:ad23fe03a082 8170 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
mbed_official 573:ad23fe03a082 8171 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
mbed_official 573:ad23fe03a082 8172 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
mbed_official 573:ad23fe03a082 8173
mbed_official 573:ad23fe03a082 8174 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
mbed_official 573:ad23fe03a082 8175 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
mbed_official 573:ad23fe03a082 8176
mbed_official 573:ad23fe03a082 8177 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
mbed_official 573:ad23fe03a082 8178 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
mbed_official 573:ad23fe03a082 8179
mbed_official 573:ad23fe03a082 8180 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
mbed_official 573:ad23fe03a082 8181 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
mbed_official 573:ad23fe03a082 8182
mbed_official 573:ad23fe03a082 8183 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
mbed_official 573:ad23fe03a082 8184 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
mbed_official 573:ad23fe03a082 8185
mbed_official 573:ad23fe03a082 8186 /* Bit definition for Ethernet DMA Status Register */
mbed_official 573:ad23fe03a082 8187 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
mbed_official 573:ad23fe03a082 8188 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
mbed_official 573:ad23fe03a082 8189 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
mbed_official 573:ad23fe03a082 8190 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
mbed_official 573:ad23fe03a082 8191 /* combination with EBS[2:0] for GetFlagStatus function */
mbed_official 573:ad23fe03a082 8192 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
mbed_official 573:ad23fe03a082 8193 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
mbed_official 573:ad23fe03a082 8194 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 573:ad23fe03a082 8195 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
mbed_official 573:ad23fe03a082 8196 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
mbed_official 573:ad23fe03a082 8197 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
mbed_official 573:ad23fe03a082 8198 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
mbed_official 573:ad23fe03a082 8199 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
mbed_official 573:ad23fe03a082 8200 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
mbed_official 573:ad23fe03a082 8201 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
mbed_official 573:ad23fe03a082 8202 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
mbed_official 573:ad23fe03a082 8203 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
mbed_official 573:ad23fe03a082 8204 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
mbed_official 573:ad23fe03a082 8205 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
mbed_official 573:ad23fe03a082 8206 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
mbed_official 573:ad23fe03a082 8207 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
mbed_official 573:ad23fe03a082 8208 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
mbed_official 573:ad23fe03a082 8209 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
mbed_official 573:ad23fe03a082 8210 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
mbed_official 573:ad23fe03a082 8211 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
mbed_official 573:ad23fe03a082 8212 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
mbed_official 573:ad23fe03a082 8213 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
mbed_official 573:ad23fe03a082 8214 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
mbed_official 573:ad23fe03a082 8215 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
mbed_official 573:ad23fe03a082 8216 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
mbed_official 573:ad23fe03a082 8217 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
mbed_official 573:ad23fe03a082 8218 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
mbed_official 573:ad23fe03a082 8219 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
mbed_official 573:ad23fe03a082 8220 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
mbed_official 573:ad23fe03a082 8221 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
mbed_official 573:ad23fe03a082 8222 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
mbed_official 573:ad23fe03a082 8223 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
mbed_official 573:ad23fe03a082 8224
mbed_official 573:ad23fe03a082 8225 /* Bit definition for Ethernet DMA Operation Mode Register */
mbed_official 573:ad23fe03a082 8226 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
mbed_official 573:ad23fe03a082 8227 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
mbed_official 573:ad23fe03a082 8228 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
mbed_official 573:ad23fe03a082 8229 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
mbed_official 573:ad23fe03a082 8230 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
mbed_official 573:ad23fe03a082 8231 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
mbed_official 573:ad23fe03a082 8232 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 573:ad23fe03a082 8233 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 573:ad23fe03a082 8234 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 573:ad23fe03a082 8235 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 573:ad23fe03a082 8236 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 573:ad23fe03a082 8237 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 573:ad23fe03a082 8238 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 573:ad23fe03a082 8239 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 573:ad23fe03a082 8240 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
mbed_official 573:ad23fe03a082 8241 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
mbed_official 573:ad23fe03a082 8242 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
mbed_official 573:ad23fe03a082 8243 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
mbed_official 573:ad23fe03a082 8244 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 573:ad23fe03a082 8245 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 573:ad23fe03a082 8246 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 573:ad23fe03a082 8247 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 573:ad23fe03a082 8248 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
mbed_official 573:ad23fe03a082 8249 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
mbed_official 573:ad23fe03a082 8250
mbed_official 573:ad23fe03a082 8251 /* Bit definition for Ethernet DMA Interrupt Enable Register */
mbed_official 573:ad23fe03a082 8252 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
mbed_official 573:ad23fe03a082 8253 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
mbed_official 573:ad23fe03a082 8254 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
mbed_official 573:ad23fe03a082 8255 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
mbed_official 573:ad23fe03a082 8256 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
mbed_official 573:ad23fe03a082 8257 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
mbed_official 573:ad23fe03a082 8258 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
mbed_official 573:ad23fe03a082 8259 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
mbed_official 573:ad23fe03a082 8260 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
mbed_official 573:ad23fe03a082 8261 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
mbed_official 573:ad23fe03a082 8262 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
mbed_official 573:ad23fe03a082 8263 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
mbed_official 573:ad23fe03a082 8264 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
mbed_official 573:ad23fe03a082 8265 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
mbed_official 573:ad23fe03a082 8266 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
mbed_official 573:ad23fe03a082 8267
mbed_official 573:ad23fe03a082 8268 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
mbed_official 573:ad23fe03a082 8269 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
mbed_official 573:ad23fe03a082 8270 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
mbed_official 573:ad23fe03a082 8271 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
mbed_official 573:ad23fe03a082 8272 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
mbed_official 573:ad23fe03a082 8273
mbed_official 573:ad23fe03a082 8274 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
mbed_official 573:ad23fe03a082 8275 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
mbed_official 573:ad23fe03a082 8276
mbed_official 573:ad23fe03a082 8277 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
mbed_official 573:ad23fe03a082 8278 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
mbed_official 573:ad23fe03a082 8279
mbed_official 573:ad23fe03a082 8280 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
mbed_official 573:ad23fe03a082 8281 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
mbed_official 573:ad23fe03a082 8282
mbed_official 573:ad23fe03a082 8283 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
mbed_official 573:ad23fe03a082 8284 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
mbed_official 573:ad23fe03a082 8285
mbed_official 573:ad23fe03a082 8286 /******************************************************************************/
mbed_official 573:ad23fe03a082 8287 /* */
mbed_official 573:ad23fe03a082 8288 /* USB_OTG */
mbed_official 573:ad23fe03a082 8289 /* */
mbed_official 573:ad23fe03a082 8290 /******************************************************************************/
mbed_official 573:ad23fe03a082 8291 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
mbed_official 573:ad23fe03a082 8292 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 573:ad23fe03a082 8293 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 573:ad23fe03a082 8294 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
mbed_official 573:ad23fe03a082 8295 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
mbed_official 573:ad23fe03a082 8296 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
mbed_official 573:ad23fe03a082 8297 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
mbed_official 573:ad23fe03a082 8298 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
mbed_official 573:ad23fe03a082 8299 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
mbed_official 573:ad23fe03a082 8300 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
mbed_official 573:ad23fe03a082 8301 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 573:ad23fe03a082 8302 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 573:ad23fe03a082 8303 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 573:ad23fe03a082 8304 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
mbed_official 573:ad23fe03a082 8305 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 573:ad23fe03a082 8306 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 573:ad23fe03a082 8307 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 573:ad23fe03a082 8308 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 573:ad23fe03a082 8309 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
mbed_official 573:ad23fe03a082 8310
mbed_official 573:ad23fe03a082 8311 /******************** Bit definition for USB_OTG_HCFG register ********************/
mbed_official 573:ad23fe03a082 8312 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 573:ad23fe03a082 8313 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8314 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8315 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 573:ad23fe03a082 8316
mbed_official 573:ad23fe03a082 8317 /******************** Bit definition for USB_OTG_DCFG register ********************/
mbed_official 573:ad23fe03a082 8318 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 573:ad23fe03a082 8319 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8320 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8321 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 573:ad23fe03a082 8322
mbed_official 573:ad23fe03a082 8323 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 573:ad23fe03a082 8324 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8325 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8326 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8327 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8328 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8329 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8330 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8331
mbed_official 573:ad23fe03a082 8332 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 573:ad23fe03a082 8333 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8334 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8335
mbed_official 573:ad23fe03a082 8336 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 573:ad23fe03a082 8337 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8338 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8339
mbed_official 573:ad23fe03a082 8340 /******************** Bit definition for USB_OTG_PCGCR register ********************/
mbed_official 573:ad23fe03a082 8341 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 573:ad23fe03a082 8342 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 573:ad23fe03a082 8343 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 573:ad23fe03a082 8344
mbed_official 573:ad23fe03a082 8345 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
mbed_official 573:ad23fe03a082 8346 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 573:ad23fe03a082 8347 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 573:ad23fe03a082 8348 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 573:ad23fe03a082 8349 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 573:ad23fe03a082 8350 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 573:ad23fe03a082 8351 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 573:ad23fe03a082 8352 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
mbed_official 573:ad23fe03a082 8353
mbed_official 573:ad23fe03a082 8354 /******************** Bit definition for USB_OTG_DCTL register ********************/
mbed_official 573:ad23fe03a082 8355 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 573:ad23fe03a082 8356 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 573:ad23fe03a082 8357 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 573:ad23fe03a082 8358 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 573:ad23fe03a082 8359
mbed_official 573:ad23fe03a082 8360 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 573:ad23fe03a082 8361 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8362 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8363 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8364 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 573:ad23fe03a082 8365 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 573:ad23fe03a082 8366 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 573:ad23fe03a082 8367 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 573:ad23fe03a082 8368 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 573:ad23fe03a082 8369
mbed_official 573:ad23fe03a082 8370 /******************** Bit definition for USB_OTG_HFIR register ********************/
mbed_official 573:ad23fe03a082 8371 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 573:ad23fe03a082 8372
mbed_official 573:ad23fe03a082 8373 /******************** Bit definition for USB_OTG_HFNUM register ********************/
mbed_official 573:ad23fe03a082 8374 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 573:ad23fe03a082 8375 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 573:ad23fe03a082 8376
mbed_official 573:ad23fe03a082 8377 /******************** Bit definition for USB_OTG_DSTS register ********************/
mbed_official 573:ad23fe03a082 8378 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 573:ad23fe03a082 8379
mbed_official 573:ad23fe03a082 8380 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 573:ad23fe03a082 8381 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8382 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8383 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 573:ad23fe03a082 8384 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 573:ad23fe03a082 8385
mbed_official 573:ad23fe03a082 8386 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
mbed_official 573:ad23fe03a082 8387 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 573:ad23fe03a082 8388 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 573:ad23fe03a082 8389 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8390 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8391 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8392 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8393 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 573:ad23fe03a082 8394 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 573:ad23fe03a082 8395 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 573:ad23fe03a082 8396
mbed_official 573:ad23fe03a082 8397 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
mbed_official 573:ad23fe03a082 8398 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 573:ad23fe03a082 8399 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8400 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8401 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8402 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 573:ad23fe03a082 8403 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 573:ad23fe03a082 8404 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 573:ad23fe03a082 8405 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 573:ad23fe03a082 8406 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8407 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8408 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8409 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8410 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 573:ad23fe03a082 8411 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 573:ad23fe03a082 8412 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 573:ad23fe03a082 8413 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 573:ad23fe03a082 8414 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 573:ad23fe03a082 8415 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 573:ad23fe03a082 8416 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 573:ad23fe03a082 8417 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 573:ad23fe03a082 8418 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 573:ad23fe03a082 8419 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 573:ad23fe03a082 8420 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 573:ad23fe03a082 8421 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 573:ad23fe03a082 8422 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 573:ad23fe03a082 8423
mbed_official 573:ad23fe03a082 8424 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
mbed_official 573:ad23fe03a082 8425 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 573:ad23fe03a082 8426 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 573:ad23fe03a082 8427 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 573:ad23fe03a082 8428 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 573:ad23fe03a082 8429 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 573:ad23fe03a082 8430 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 573:ad23fe03a082 8431 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8432 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8433 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8434 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8435 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8436 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 573:ad23fe03a082 8437 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 573:ad23fe03a082 8438
mbed_official 573:ad23fe03a082 8439 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
mbed_official 573:ad23fe03a082 8440 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 573:ad23fe03a082 8441 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 573:ad23fe03a082 8442 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 573:ad23fe03a082 8443 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 573:ad23fe03a082 8444 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 573:ad23fe03a082 8445 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 573:ad23fe03a082 8446 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 573:ad23fe03a082 8447 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 573:ad23fe03a082 8448
mbed_official 573:ad23fe03a082 8449 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
mbed_official 573:ad23fe03a082 8450 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 573:ad23fe03a082 8451 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 573:ad23fe03a082 8452 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8453 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8454 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8455 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8456 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8457 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8458 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8459 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 8460
mbed_official 573:ad23fe03a082 8461 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 573:ad23fe03a082 8462 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8463 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8464 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8465 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8466 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8467 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8468 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8469 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 8470
mbed_official 573:ad23fe03a082 8471 /******************** Bit definition for USB_OTG_HAINT register ********************/
mbed_official 573:ad23fe03a082 8472 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 573:ad23fe03a082 8473
mbed_official 573:ad23fe03a082 8474 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
mbed_official 573:ad23fe03a082 8475 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 573:ad23fe03a082 8476 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 573:ad23fe03a082 8477 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 573:ad23fe03a082 8478 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 573:ad23fe03a082 8479 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 573:ad23fe03a082 8480 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 573:ad23fe03a082 8481 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 573:ad23fe03a082 8482
mbed_official 573:ad23fe03a082 8483 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
mbed_official 573:ad23fe03a082 8484 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 573:ad23fe03a082 8485 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 573:ad23fe03a082 8486 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 573:ad23fe03a082 8487 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 573:ad23fe03a082 8488 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 573:ad23fe03a082 8489 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 573:ad23fe03a082 8490 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 573:ad23fe03a082 8491 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 573:ad23fe03a082 8492 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 573:ad23fe03a082 8493 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 573:ad23fe03a082 8494 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 573:ad23fe03a082 8495 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 573:ad23fe03a082 8496 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 573:ad23fe03a082 8497 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 573:ad23fe03a082 8498 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 573:ad23fe03a082 8499 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 573:ad23fe03a082 8500 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 573:ad23fe03a082 8501 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 573:ad23fe03a082 8502 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 573:ad23fe03a082 8503 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
mbed_official 573:ad23fe03a082 8504 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 573:ad23fe03a082 8505 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 573:ad23fe03a082 8506 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 573:ad23fe03a082 8507 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
mbed_official 573:ad23fe03a082 8508 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 573:ad23fe03a082 8509 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 573:ad23fe03a082 8510 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 573:ad23fe03a082 8511 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 573:ad23fe03a082 8512
mbed_official 573:ad23fe03a082 8513 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
mbed_official 573:ad23fe03a082 8514 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 573:ad23fe03a082 8515 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 573:ad23fe03a082 8516 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 573:ad23fe03a082 8517 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 573:ad23fe03a082 8518 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 573:ad23fe03a082 8519 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 573:ad23fe03a082 8520 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 573:ad23fe03a082 8521 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 573:ad23fe03a082 8522 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 573:ad23fe03a082 8523 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 573:ad23fe03a082 8524 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 573:ad23fe03a082 8525 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 573:ad23fe03a082 8526 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 573:ad23fe03a082 8527 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 573:ad23fe03a082 8528 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 573:ad23fe03a082 8529 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 573:ad23fe03a082 8530 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 573:ad23fe03a082 8531 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 573:ad23fe03a082 8532 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 573:ad23fe03a082 8533 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
mbed_official 573:ad23fe03a082 8534 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 573:ad23fe03a082 8535 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 573:ad23fe03a082 8536 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 573:ad23fe03a082 8537 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
mbed_official 573:ad23fe03a082 8538 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 573:ad23fe03a082 8539 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 573:ad23fe03a082 8540 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 573:ad23fe03a082 8541 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 573:ad23fe03a082 8542
mbed_official 573:ad23fe03a082 8543 /******************** Bit definition for USB_OTG_DAINT register ********************/
mbed_official 573:ad23fe03a082 8544 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 573:ad23fe03a082 8545 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 573:ad23fe03a082 8546
mbed_official 573:ad23fe03a082 8547 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
mbed_official 573:ad23fe03a082 8548 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 573:ad23fe03a082 8549
mbed_official 573:ad23fe03a082 8550 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 573:ad23fe03a082 8551 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8552 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8553 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8554 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8555
mbed_official 573:ad23fe03a082 8556 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
mbed_official 573:ad23fe03a082 8557 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8558 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 573:ad23fe03a082 8559
mbed_official 573:ad23fe03a082 8560 /******************** Bit definition for OTG register ********************/
mbed_official 573:ad23fe03a082 8561
mbed_official 573:ad23fe03a082 8562 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 573:ad23fe03a082 8563 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8564 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8565 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8566 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8567 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 573:ad23fe03a082 8568
mbed_official 573:ad23fe03a082 8569 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 573:ad23fe03a082 8570 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8571 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8572
mbed_official 573:ad23fe03a082 8573 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 573:ad23fe03a082 8574 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8575 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8576 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8577 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8578
mbed_official 573:ad23fe03a082 8579 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 573:ad23fe03a082 8580 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8581 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8582 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8583 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8584
mbed_official 573:ad23fe03a082 8585 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 573:ad23fe03a082 8586 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8587 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8588 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8589 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8590
mbed_official 573:ad23fe03a082 8591 /******************** Bit definition for OTG register ********************/
mbed_official 573:ad23fe03a082 8592
mbed_official 573:ad23fe03a082 8593 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 573:ad23fe03a082 8594 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8595 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8596 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8597 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8598 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 573:ad23fe03a082 8599
mbed_official 573:ad23fe03a082 8600 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 573:ad23fe03a082 8601 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8602 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8603
mbed_official 573:ad23fe03a082 8604 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 573:ad23fe03a082 8605 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8606 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8607 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8608 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8609
mbed_official 573:ad23fe03a082 8610 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 573:ad23fe03a082 8611 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8612 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8613 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8614 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8615
mbed_official 573:ad23fe03a082 8616 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 573:ad23fe03a082 8617 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8618 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8619 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8620 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8621
mbed_official 573:ad23fe03a082 8622 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
mbed_official 573:ad23fe03a082 8623 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 573:ad23fe03a082 8624
mbed_official 573:ad23fe03a082 8625 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
mbed_official 573:ad23fe03a082 8626 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 573:ad23fe03a082 8627
mbed_official 573:ad23fe03a082 8628 /******************** Bit definition for OTG register ********************/
mbed_official 573:ad23fe03a082 8629 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 573:ad23fe03a082 8630 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 573:ad23fe03a082 8631 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 573:ad23fe03a082 8632 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 573:ad23fe03a082 8633
mbed_official 573:ad23fe03a082 8634 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
mbed_official 573:ad23fe03a082 8635 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 573:ad23fe03a082 8636
mbed_official 573:ad23fe03a082 8637 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
mbed_official 573:ad23fe03a082 8638 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 573:ad23fe03a082 8639
mbed_official 573:ad23fe03a082 8640 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 573:ad23fe03a082 8641 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8642 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8643 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8644 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8645 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8646 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8647 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8648 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 8649
mbed_official 573:ad23fe03a082 8650 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 573:ad23fe03a082 8651 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8652 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8653 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8654 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8655 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8656 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8657 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8658
mbed_official 573:ad23fe03a082 8659 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
mbed_official 573:ad23fe03a082 8660 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 573:ad23fe03a082 8661 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 573:ad23fe03a082 8662
mbed_official 573:ad23fe03a082 8663 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 573:ad23fe03a082 8664 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8665 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8666 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8667 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8668 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8669 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8670 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8671 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 8672 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 573:ad23fe03a082 8673 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 573:ad23fe03a082 8674
mbed_official 573:ad23fe03a082 8675 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 573:ad23fe03a082 8676 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8677 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8678 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8679 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8680 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8681 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8682 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8683 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 573:ad23fe03a082 8684 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 573:ad23fe03a082 8685 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 573:ad23fe03a082 8686
mbed_official 573:ad23fe03a082 8687 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
mbed_official 573:ad23fe03a082 8688 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 573:ad23fe03a082 8689
mbed_official 573:ad23fe03a082 8690 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
mbed_official 573:ad23fe03a082 8691 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 573:ad23fe03a082 8692 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 573:ad23fe03a082 8693
mbed_official 573:ad23fe03a082 8694 /******************** Bit definition for USB_OTG_GCCFG register ********************/
mbed_official 573:ad23fe03a082 8695 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 573:ad23fe03a082 8696 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
mbed_official 573:ad23fe03a082 8697
mbed_official 573:ad23fe03a082 8698 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
mbed_official 573:ad23fe03a082 8699 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
mbed_official 573:ad23fe03a082 8700 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
mbed_official 573:ad23fe03a082 8701
mbed_official 573:ad23fe03a082 8702 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
mbed_official 573:ad23fe03a082 8703 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 573:ad23fe03a082 8704 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 573:ad23fe03a082 8705
mbed_official 573:ad23fe03a082 8706 /******************** Bit definition for USB_OTG_CID register ********************/
mbed_official 573:ad23fe03a082 8707 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 573:ad23fe03a082 8708
mbed_official 573:ad23fe03a082 8709 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
mbed_official 573:ad23fe03a082 8710 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
mbed_official 573:ad23fe03a082 8711 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
mbed_official 573:ad23fe03a082 8712 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
mbed_official 573:ad23fe03a082 8713 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 573:ad23fe03a082 8714 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
mbed_official 573:ad23fe03a082 8715 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
mbed_official 573:ad23fe03a082 8716 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
mbed_official 573:ad23fe03a082 8717 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
mbed_official 573:ad23fe03a082 8718 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
mbed_official 573:ad23fe03a082 8719 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
mbed_official 573:ad23fe03a082 8720 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
mbed_official 573:ad23fe03a082 8721 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
mbed_official 573:ad23fe03a082 8722 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
mbed_official 573:ad23fe03a082 8723 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
mbed_official 573:ad23fe03a082 8724 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
mbed_official 573:ad23fe03a082 8725
mbed_official 573:ad23fe03a082 8726 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 573:ad23fe03a082 8727 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 573:ad23fe03a082 8728 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 573:ad23fe03a082 8729 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 573:ad23fe03a082 8730 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 573:ad23fe03a082 8731 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 573:ad23fe03a082 8732 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 573:ad23fe03a082 8733 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 573:ad23fe03a082 8734 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 573:ad23fe03a082 8735 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 573:ad23fe03a082 8736
mbed_official 573:ad23fe03a082 8737 /******************** Bit definition for USB_OTG_HPRT register ********************/
mbed_official 573:ad23fe03a082 8738 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 573:ad23fe03a082 8739 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 573:ad23fe03a082 8740 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 573:ad23fe03a082 8741 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 573:ad23fe03a082 8742 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 573:ad23fe03a082 8743 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 573:ad23fe03a082 8744 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 573:ad23fe03a082 8745 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 573:ad23fe03a082 8746 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 573:ad23fe03a082 8747
mbed_official 573:ad23fe03a082 8748 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 573:ad23fe03a082 8749 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8750 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8751 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 573:ad23fe03a082 8752
mbed_official 573:ad23fe03a082 8753 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 573:ad23fe03a082 8754 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8755 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8756 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8757 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8758
mbed_official 573:ad23fe03a082 8759 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 573:ad23fe03a082 8760 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8761 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8762
mbed_official 573:ad23fe03a082 8763 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 573:ad23fe03a082 8764 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 573:ad23fe03a082 8765 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 573:ad23fe03a082 8766 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 573:ad23fe03a082 8767 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 573:ad23fe03a082 8768 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 573:ad23fe03a082 8769 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 573:ad23fe03a082 8770 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 573:ad23fe03a082 8771 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 573:ad23fe03a082 8772 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 573:ad23fe03a082 8773 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 573:ad23fe03a082 8774 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 573:ad23fe03a082 8775
mbed_official 573:ad23fe03a082 8776 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
mbed_official 573:ad23fe03a082 8777 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 573:ad23fe03a082 8778 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 573:ad23fe03a082 8779
mbed_official 573:ad23fe03a082 8780 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
mbed_official 573:ad23fe03a082 8781 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 573:ad23fe03a082 8782 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 573:ad23fe03a082 8783 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 573:ad23fe03a082 8784 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 573:ad23fe03a082 8785
mbed_official 573:ad23fe03a082 8786 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 573:ad23fe03a082 8787 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8788 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8789 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 573:ad23fe03a082 8790
mbed_official 573:ad23fe03a082 8791 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 573:ad23fe03a082 8792 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8793 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8794 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8795 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8796 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 573:ad23fe03a082 8797 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 573:ad23fe03a082 8798 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 573:ad23fe03a082 8799 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 573:ad23fe03a082 8800 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 573:ad23fe03a082 8801 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 573:ad23fe03a082 8802
mbed_official 573:ad23fe03a082 8803 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
mbed_official 573:ad23fe03a082 8804 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 573:ad23fe03a082 8805
mbed_official 573:ad23fe03a082 8806 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 573:ad23fe03a082 8807 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8808 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8809 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8810 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8811 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 573:ad23fe03a082 8812 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 573:ad23fe03a082 8813
mbed_official 573:ad23fe03a082 8814 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 573:ad23fe03a082 8815 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8816 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8817
mbed_official 573:ad23fe03a082 8818 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 573:ad23fe03a082 8819 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8820 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8821
mbed_official 573:ad23fe03a082 8822 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 573:ad23fe03a082 8823 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8824 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8825 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8826 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8827 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8828 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8829 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8830 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 573:ad23fe03a082 8831 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 573:ad23fe03a082 8832 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 573:ad23fe03a082 8833
mbed_official 573:ad23fe03a082 8834 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
mbed_official 573:ad23fe03a082 8835
mbed_official 573:ad23fe03a082 8836 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 573:ad23fe03a082 8837 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8838 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8839 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8840 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8841 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8842 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8843 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8844
mbed_official 573:ad23fe03a082 8845 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 573:ad23fe03a082 8846 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8847 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8848 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 573:ad23fe03a082 8849 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 573:ad23fe03a082 8850 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 573:ad23fe03a082 8851 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 573:ad23fe03a082 8852 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 573:ad23fe03a082 8853
mbed_official 573:ad23fe03a082 8854 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 573:ad23fe03a082 8855 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8856 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8857 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 573:ad23fe03a082 8858 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 573:ad23fe03a082 8859
mbed_official 573:ad23fe03a082 8860 /******************** Bit definition for USB_OTG_HCINT register ********************/
mbed_official 573:ad23fe03a082 8861 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 573:ad23fe03a082 8862 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 573:ad23fe03a082 8863 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 573:ad23fe03a082 8864 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 573:ad23fe03a082 8865 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 573:ad23fe03a082 8866 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 573:ad23fe03a082 8867 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 573:ad23fe03a082 8868 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 573:ad23fe03a082 8869 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 573:ad23fe03a082 8870 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 573:ad23fe03a082 8871 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 573:ad23fe03a082 8872
mbed_official 573:ad23fe03a082 8873 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
mbed_official 573:ad23fe03a082 8874 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 573:ad23fe03a082 8875 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 573:ad23fe03a082 8876 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 573:ad23fe03a082 8877 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 573:ad23fe03a082 8878 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 573:ad23fe03a082 8879 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 573:ad23fe03a082 8880 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 573:ad23fe03a082 8881 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 573:ad23fe03a082 8882 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 573:ad23fe03a082 8883 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 573:ad23fe03a082 8884 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 573:ad23fe03a082 8885
mbed_official 573:ad23fe03a082 8886 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
mbed_official 573:ad23fe03a082 8887 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 573:ad23fe03a082 8888 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 573:ad23fe03a082 8889 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 573:ad23fe03a082 8890 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 573:ad23fe03a082 8891 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 573:ad23fe03a082 8892 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 573:ad23fe03a082 8893 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 573:ad23fe03a082 8894 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 573:ad23fe03a082 8895 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 573:ad23fe03a082 8896 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 573:ad23fe03a082 8897 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 573:ad23fe03a082 8898
mbed_official 573:ad23fe03a082 8899 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 573:ad23fe03a082 8900
mbed_official 573:ad23fe03a082 8901 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 573:ad23fe03a082 8902 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 573:ad23fe03a082 8903 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 573:ad23fe03a082 8904 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
mbed_official 573:ad23fe03a082 8905 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 573:ad23fe03a082 8906 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 573:ad23fe03a082 8907 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 573:ad23fe03a082 8908 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 573:ad23fe03a082 8909 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8910 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8911
mbed_official 573:ad23fe03a082 8912 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
mbed_official 573:ad23fe03a082 8913 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 573:ad23fe03a082 8914
mbed_official 573:ad23fe03a082 8915 /******************** Bit definition for USB_OTG_HCDMA register ********************/
mbed_official 573:ad23fe03a082 8916 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 573:ad23fe03a082 8917
mbed_official 573:ad23fe03a082 8918 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
mbed_official 573:ad23fe03a082 8919 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
mbed_official 573:ad23fe03a082 8920
mbed_official 573:ad23fe03a082 8921 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
mbed_official 573:ad23fe03a082 8922 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 573:ad23fe03a082 8923 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 573:ad23fe03a082 8924
mbed_official 573:ad23fe03a082 8925 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
mbed_official 573:ad23fe03a082 8926 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8927 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 573:ad23fe03a082 8928 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 573:ad23fe03a082 8929 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 573:ad23fe03a082 8930 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 573:ad23fe03a082 8931 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 573:ad23fe03a082 8932 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8933 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8934 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 573:ad23fe03a082 8935 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 573:ad23fe03a082 8936 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 573:ad23fe03a082 8937 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 573:ad23fe03a082 8938 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 573:ad23fe03a082 8939 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 573:ad23fe03a082 8940
mbed_official 573:ad23fe03a082 8941 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
mbed_official 573:ad23fe03a082 8942 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 573:ad23fe03a082 8943 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 573:ad23fe03a082 8944 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 573:ad23fe03a082 8945 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 573:ad23fe03a082 8946 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 573:ad23fe03a082 8947 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 573:ad23fe03a082 8948
mbed_official 573:ad23fe03a082 8949 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
mbed_official 573:ad23fe03a082 8950 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 573:ad23fe03a082 8951 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 573:ad23fe03a082 8952
mbed_official 573:ad23fe03a082 8953 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 573:ad23fe03a082 8954 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8955 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8956
mbed_official 573:ad23fe03a082 8957 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 573:ad23fe03a082 8958 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 573:ad23fe03a082 8959 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 573:ad23fe03a082 8960 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 573:ad23fe03a082 8961
mbed_official 573:ad23fe03a082 8962 /**
mbed_official 573:ad23fe03a082 8963 * @}
mbed_official 573:ad23fe03a082 8964 */
mbed_official 573:ad23fe03a082 8965
mbed_official 573:ad23fe03a082 8966 /**
mbed_official 573:ad23fe03a082 8967 * @}
mbed_official 573:ad23fe03a082 8968 */
mbed_official 573:ad23fe03a082 8969
mbed_official 573:ad23fe03a082 8970 /** @addtogroup Exported_macros
mbed_official 573:ad23fe03a082 8971 * @{
mbed_official 573:ad23fe03a082 8972 */
mbed_official 573:ad23fe03a082 8973
mbed_official 573:ad23fe03a082 8974 /******************************* ADC Instances ********************************/
mbed_official 573:ad23fe03a082 8975 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
mbed_official 573:ad23fe03a082 8976 ((__INSTANCE__) == ADC2) || \
mbed_official 573:ad23fe03a082 8977 ((__INSTANCE__) == ADC3))
mbed_official 573:ad23fe03a082 8978
mbed_official 573:ad23fe03a082 8979 /******************************* CAN Instances ********************************/
mbed_official 573:ad23fe03a082 8980 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
mbed_official 573:ad23fe03a082 8981 ((__INSTANCE__) == CAN2))
mbed_official 573:ad23fe03a082 8982
mbed_official 573:ad23fe03a082 8983 /******************************* CRC Instances ********************************/
mbed_official 573:ad23fe03a082 8984 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
mbed_official 573:ad23fe03a082 8985
mbed_official 573:ad23fe03a082 8986 /******************************* DAC Instances ********************************/
mbed_official 573:ad23fe03a082 8987 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
mbed_official 573:ad23fe03a082 8988
mbed_official 573:ad23fe03a082 8989 /******************************* DCMI Instances *******************************/
mbed_official 573:ad23fe03a082 8990 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
mbed_official 573:ad23fe03a082 8991
mbed_official 573:ad23fe03a082 8992 /******************************* DMA2D Instances *******************************/
mbed_official 573:ad23fe03a082 8993 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
mbed_official 573:ad23fe03a082 8994
mbed_official 573:ad23fe03a082 8995 /******************************** DMA Instances *******************************/
mbed_official 573:ad23fe03a082 8996 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
mbed_official 573:ad23fe03a082 8997 ((__INSTANCE__) == DMA1_Stream1) || \
mbed_official 573:ad23fe03a082 8998 ((__INSTANCE__) == DMA1_Stream2) || \
mbed_official 573:ad23fe03a082 8999 ((__INSTANCE__) == DMA1_Stream3) || \
mbed_official 573:ad23fe03a082 9000 ((__INSTANCE__) == DMA1_Stream4) || \
mbed_official 573:ad23fe03a082 9001 ((__INSTANCE__) == DMA1_Stream5) || \
mbed_official 573:ad23fe03a082 9002 ((__INSTANCE__) == DMA1_Stream6) || \
mbed_official 573:ad23fe03a082 9003 ((__INSTANCE__) == DMA1_Stream7) || \
mbed_official 573:ad23fe03a082 9004 ((__INSTANCE__) == DMA2_Stream0) || \
mbed_official 573:ad23fe03a082 9005 ((__INSTANCE__) == DMA2_Stream1) || \
mbed_official 573:ad23fe03a082 9006 ((__INSTANCE__) == DMA2_Stream2) || \
mbed_official 573:ad23fe03a082 9007 ((__INSTANCE__) == DMA2_Stream3) || \
mbed_official 573:ad23fe03a082 9008 ((__INSTANCE__) == DMA2_Stream4) || \
mbed_official 573:ad23fe03a082 9009 ((__INSTANCE__) == DMA2_Stream5) || \
mbed_official 573:ad23fe03a082 9010 ((__INSTANCE__) == DMA2_Stream6) || \
mbed_official 573:ad23fe03a082 9011 ((__INSTANCE__) == DMA2_Stream7))
mbed_official 573:ad23fe03a082 9012
mbed_official 573:ad23fe03a082 9013 /******************************* GPIO Instances *******************************/
mbed_official 573:ad23fe03a082 9014 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
mbed_official 573:ad23fe03a082 9015 ((__INSTANCE__) == GPIOB) || \
mbed_official 573:ad23fe03a082 9016 ((__INSTANCE__) == GPIOC) || \
mbed_official 573:ad23fe03a082 9017 ((__INSTANCE__) == GPIOD) || \
mbed_official 573:ad23fe03a082 9018 ((__INSTANCE__) == GPIOE) || \
mbed_official 573:ad23fe03a082 9019 ((__INSTANCE__) == GPIOF) || \
mbed_official 573:ad23fe03a082 9020 ((__INSTANCE__) == GPIOG) || \
mbed_official 573:ad23fe03a082 9021 ((__INSTANCE__) == GPIOH) || \
mbed_official 573:ad23fe03a082 9022 ((__INSTANCE__) == GPIOI) || \
mbed_official 573:ad23fe03a082 9023 ((__INSTANCE__) == GPIOJ) || \
mbed_official 573:ad23fe03a082 9024 ((__INSTANCE__) == GPIOK))
mbed_official 573:ad23fe03a082 9025
mbed_official 573:ad23fe03a082 9026 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
mbed_official 573:ad23fe03a082 9027 ((__INSTANCE__) == GPIOB) || \
mbed_official 573:ad23fe03a082 9028 ((__INSTANCE__) == GPIOC) || \
mbed_official 573:ad23fe03a082 9029 ((__INSTANCE__) == GPIOD) || \
mbed_official 573:ad23fe03a082 9030 ((__INSTANCE__) == GPIOE) || \
mbed_official 573:ad23fe03a082 9031 ((__INSTANCE__) == GPIOF) || \
mbed_official 573:ad23fe03a082 9032 ((__INSTANCE__) == GPIOG) || \
mbed_official 573:ad23fe03a082 9033 ((__INSTANCE__) == GPIOH) || \
mbed_official 573:ad23fe03a082 9034 ((__INSTANCE__) == GPIOI) || \
mbed_official 573:ad23fe03a082 9035 ((__INSTANCE__) == GPIOJ) || \
mbed_official 573:ad23fe03a082 9036 ((__INSTANCE__) == GPIOK))
mbed_official 573:ad23fe03a082 9037
mbed_official 573:ad23fe03a082 9038 /****************************** CEC Instances *********************************/
mbed_official 573:ad23fe03a082 9039 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
mbed_official 573:ad23fe03a082 9040
mbed_official 573:ad23fe03a082 9041 /****************************** QSPI Instances *********************************/
mbed_official 573:ad23fe03a082 9042 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
mbed_official 573:ad23fe03a082 9043
mbed_official 573:ad23fe03a082 9044
mbed_official 573:ad23fe03a082 9045 /******************************** I2C Instances *******************************/
mbed_official 573:ad23fe03a082 9046 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
mbed_official 573:ad23fe03a082 9047 ((__INSTANCE__) == I2C2) || \
mbed_official 573:ad23fe03a082 9048 ((__INSTANCE__) == I2C3) || \
mbed_official 573:ad23fe03a082 9049 ((__INSTANCE__) == I2C4))
mbed_official 573:ad23fe03a082 9050
mbed_official 573:ad23fe03a082 9051 /******************************** I2S Instances *******************************/
mbed_official 573:ad23fe03a082 9052 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
mbed_official 573:ad23fe03a082 9053 ((__INSTANCE__) == SPI2) || \
mbed_official 573:ad23fe03a082 9054 ((__INSTANCE__) == SPI3))
mbed_official 573:ad23fe03a082 9055
mbed_official 573:ad23fe03a082 9056 /******************************* LPTIM Instances ********************************/
mbed_official 573:ad23fe03a082 9057 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
mbed_official 573:ad23fe03a082 9058
mbed_official 573:ad23fe03a082 9059 /****************************** LTDC Instances ********************************/
mbed_official 573:ad23fe03a082 9060 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
mbed_official 573:ad23fe03a082 9061
mbed_official 573:ad23fe03a082 9062 /******************************* RNG Instances ********************************/
mbed_official 573:ad23fe03a082 9063 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
mbed_official 573:ad23fe03a082 9064
mbed_official 573:ad23fe03a082 9065 /****************************** RTC Instances *********************************/
mbed_official 573:ad23fe03a082 9066 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
mbed_official 573:ad23fe03a082 9067
mbed_official 573:ad23fe03a082 9068 /******************************* SAI Instances ********************************/
mbed_official 573:ad23fe03a082 9069 #define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
mbed_official 573:ad23fe03a082 9070 ((__PERIPH__) == SAI1_Block_B) || \
mbed_official 573:ad23fe03a082 9071 ((__PERIPH__) == SAI2_Block_A) || \
mbed_official 573:ad23fe03a082 9072 ((__PERIPH__) == SAI2_Block_B))
mbed_official 573:ad23fe03a082 9073
mbed_official 573:ad23fe03a082 9074
mbed_official 573:ad23fe03a082 9075 /******************************** SDMMC Instances *******************************/
mbed_official 573:ad23fe03a082 9076 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
mbed_official 573:ad23fe03a082 9077
mbed_official 573:ad23fe03a082 9078
mbed_official 573:ad23fe03a082 9079 /****************************** SPDIFRX Instances *********************************/
mbed_official 573:ad23fe03a082 9080 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
mbed_official 573:ad23fe03a082 9081
mbed_official 573:ad23fe03a082 9082 /******************************** SPI Instances *******************************/
mbed_official 573:ad23fe03a082 9083 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
mbed_official 573:ad23fe03a082 9084 ((__INSTANCE__) == SPI2) || \
mbed_official 573:ad23fe03a082 9085 ((__INSTANCE__) == SPI3) || \
mbed_official 573:ad23fe03a082 9086 ((__INSTANCE__) == SPI4) || \
mbed_official 573:ad23fe03a082 9087 ((__INSTANCE__) == SPI5) || \
mbed_official 573:ad23fe03a082 9088 ((__INSTANCE__) == SPI6))
mbed_official 573:ad23fe03a082 9089
mbed_official 573:ad23fe03a082 9090 /****************** TIM Instances : All supported instances *******************/
mbed_official 573:ad23fe03a082 9091 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9092 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9093 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9094 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9095 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9096 ((__INSTANCE__) == TIM6) || \
mbed_official 573:ad23fe03a082 9097 ((__INSTANCE__) == TIM7) || \
mbed_official 573:ad23fe03a082 9098 ((__INSTANCE__) == TIM8) || \
mbed_official 573:ad23fe03a082 9099 ((__INSTANCE__) == TIM9) || \
mbed_official 573:ad23fe03a082 9100 ((__INSTANCE__) == TIM10) || \
mbed_official 573:ad23fe03a082 9101 ((__INSTANCE__) == TIM11) || \
mbed_official 573:ad23fe03a082 9102 ((__INSTANCE__) == TIM12) || \
mbed_official 573:ad23fe03a082 9103 ((__INSTANCE__) == TIM13) || \
mbed_official 573:ad23fe03a082 9104 ((__INSTANCE__) == TIM14))
mbed_official 573:ad23fe03a082 9105
mbed_official 573:ad23fe03a082 9106 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 573:ad23fe03a082 9107 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9108 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9109 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9110 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9111 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9112 ((__INSTANCE__) == TIM8) || \
mbed_official 573:ad23fe03a082 9113 ((__INSTANCE__) == TIM9) || \
mbed_official 573:ad23fe03a082 9114 ((__INSTANCE__) == TIM10) || \
mbed_official 573:ad23fe03a082 9115 ((__INSTANCE__) == TIM11) || \
mbed_official 573:ad23fe03a082 9116 ((__INSTANCE__) == TIM12) || \
mbed_official 573:ad23fe03a082 9117 ((__INSTANCE__) == TIM13) || \
mbed_official 573:ad23fe03a082 9118 ((__INSTANCE__) == TIM14))
mbed_official 573:ad23fe03a082 9119
mbed_official 573:ad23fe03a082 9120 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 573:ad23fe03a082 9121 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9122 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9123 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9124 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9125 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9126 ((__INSTANCE__) == TIM8) || \
mbed_official 573:ad23fe03a082 9127 ((__INSTANCE__) == TIM9) || \
mbed_official 573:ad23fe03a082 9128 ((__INSTANCE__) == TIM12))
mbed_official 573:ad23fe03a082 9129
mbed_official 573:ad23fe03a082 9130 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 573:ad23fe03a082 9131 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9132 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9133 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9134 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9135 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9136 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9137
mbed_official 573:ad23fe03a082 9138 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 573:ad23fe03a082 9139 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9140 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9141 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9142 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9143 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9144 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9145
mbed_official 573:ad23fe03a082 9146 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
mbed_official 573:ad23fe03a082 9147 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
mbed_official 573:ad23fe03a082 9148 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9149 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9150
mbed_official 573:ad23fe03a082 9151 /****************** TIM Instances : supporting OCxREF clear *******************/
mbed_official 573:ad23fe03a082 9152 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9153 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9154 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9155 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9156 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9157 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9158
mbed_official 573:ad23fe03a082 9159 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 573:ad23fe03a082 9160 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9161 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9162 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9163 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9164 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9165 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9166 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9167
mbed_official 573:ad23fe03a082 9168 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 573:ad23fe03a082 9169 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9170 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9171 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9172 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9173 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9174 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9175 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9176 /****************** TIM Instances : at least 5 capture/compare channels *******/
mbed_official 573:ad23fe03a082 9177 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9178 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9179 ((__INSTANCE__) == TIM8) )
mbed_official 573:ad23fe03a082 9180
mbed_official 573:ad23fe03a082 9181 /****************** TIM Instances : at least 6 capture/compare channels *******/
mbed_official 573:ad23fe03a082 9182 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9183 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9184 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9185
mbed_official 573:ad23fe03a082 9186
mbed_official 573:ad23fe03a082 9187 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 573:ad23fe03a082 9188 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9189 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9190
mbed_official 573:ad23fe03a082 9191 /****************** TIM Instances : supporting 2 break inputs *****************/
mbed_official 573:ad23fe03a082 9192 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9193 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9194 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9195
mbed_official 573:ad23fe03a082 9196 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 573:ad23fe03a082 9197 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9198 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9199 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9200 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9201 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9202 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9203
mbed_official 573:ad23fe03a082 9204 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 573:ad23fe03a082 9205 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9206 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9207 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9208 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9209 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9210 ((__INSTANCE__) == TIM6) || \
mbed_official 573:ad23fe03a082 9211 ((__INSTANCE__) == TIM7) || \
mbed_official 573:ad23fe03a082 9212 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9213
mbed_official 573:ad23fe03a082 9214 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 573:ad23fe03a082 9215 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9216 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9217 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9218 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9219 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9220 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9221
mbed_official 573:ad23fe03a082 9222 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 573:ad23fe03a082 9223 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9224 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9225 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9226 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9227 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9228 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9229
mbed_official 573:ad23fe03a082 9230 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 573:ad23fe03a082 9231 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9232 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9233 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9234 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9235 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9236 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9237
mbed_official 573:ad23fe03a082 9238 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 573:ad23fe03a082 9239 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9240 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9241 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9242 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9243 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9244 ((__INSTANCE__) == TIM6) || \
mbed_official 573:ad23fe03a082 9245 ((__INSTANCE__) == TIM7) || \
mbed_official 573:ad23fe03a082 9246 ((__INSTANCE__) == TIM8) || \
mbed_official 573:ad23fe03a082 9247 ((__INSTANCE__) == TIM13) || \
mbed_official 573:ad23fe03a082 9248 ((__INSTANCE__) == TIM14))
mbed_official 573:ad23fe03a082 9249
mbed_official 573:ad23fe03a082 9250 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 573:ad23fe03a082 9251 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9252 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9253 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9254 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9255 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9256 ((__INSTANCE__) == TIM8) || \
mbed_official 573:ad23fe03a082 9257 ((__INSTANCE__) == TIM9) || \
mbed_official 573:ad23fe03a082 9258 ((__INSTANCE__) == TIM12))
mbed_official 573:ad23fe03a082 9259
mbed_official 573:ad23fe03a082 9260 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 573:ad23fe03a082 9261 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9262 ((__INSTANCE__) == TIM5))
mbed_official 573:ad23fe03a082 9263
mbed_official 573:ad23fe03a082 9264 /***************** TIM Instances : external trigger input available ************/
mbed_official 573:ad23fe03a082 9265 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9266 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9267 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9268 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9269 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9270 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9271
mbed_official 573:ad23fe03a082 9272 /****************** TIM Instances : remapping capability **********************/
mbed_official 573:ad23fe03a082 9273 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9274 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9275 ((__INSTANCE__) == TIM11))
mbed_official 573:ad23fe03a082 9276
mbed_official 573:ad23fe03a082 9277 /******************* TIM Instances : output(s) available **********************/
mbed_official 573:ad23fe03a082 9278 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
mbed_official 573:ad23fe03a082 9279 ((((__INSTANCE__) == TIM1) && \
mbed_official 573:ad23fe03a082 9280 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9281 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9282 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9283 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9284 || \
mbed_official 573:ad23fe03a082 9285 (((__INSTANCE__) == TIM2) && \
mbed_official 573:ad23fe03a082 9286 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9287 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9288 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9289 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9290 || \
mbed_official 573:ad23fe03a082 9291 (((__INSTANCE__) == TIM3) && \
mbed_official 573:ad23fe03a082 9292 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9293 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9294 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9295 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9296 || \
mbed_official 573:ad23fe03a082 9297 (((__INSTANCE__) == TIM4) && \
mbed_official 573:ad23fe03a082 9298 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9299 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9300 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9301 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9302 || \
mbed_official 573:ad23fe03a082 9303 (((__INSTANCE__) == TIM5) && \
mbed_official 573:ad23fe03a082 9304 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9305 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9306 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9307 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9308 || \
mbed_official 573:ad23fe03a082 9309 (((__INSTANCE__) == TIM8) && \
mbed_official 573:ad23fe03a082 9310 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9311 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9312 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 573:ad23fe03a082 9313 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 573:ad23fe03a082 9314 || \
mbed_official 573:ad23fe03a082 9315 (((__INSTANCE__) == TIM9) && \
mbed_official 573:ad23fe03a082 9316 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9317 ((__CHANNEL__) == TIM_CHANNEL_2))) \
mbed_official 573:ad23fe03a082 9318 || \
mbed_official 573:ad23fe03a082 9319 (((__INSTANCE__) == TIM10) && \
mbed_official 573:ad23fe03a082 9320 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 573:ad23fe03a082 9321 || \
mbed_official 573:ad23fe03a082 9322 (((__INSTANCE__) == TIM11) && \
mbed_official 573:ad23fe03a082 9323 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 573:ad23fe03a082 9324 || \
mbed_official 573:ad23fe03a082 9325 (((__INSTANCE__) == TIM12) && \
mbed_official 573:ad23fe03a082 9326 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9327 ((__CHANNEL__) == TIM_CHANNEL_2))) \
mbed_official 573:ad23fe03a082 9328 || \
mbed_official 573:ad23fe03a082 9329 (((__INSTANCE__) == TIM13) && \
mbed_official 573:ad23fe03a082 9330 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 573:ad23fe03a082 9331 || \
mbed_official 573:ad23fe03a082 9332 (((__INSTANCE__) == TIM14) && \
mbed_official 573:ad23fe03a082 9333 (((__CHANNEL__) == TIM_CHANNEL_1))))
mbed_official 573:ad23fe03a082 9334
mbed_official 573:ad23fe03a082 9335 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 573:ad23fe03a082 9336 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
mbed_official 573:ad23fe03a082 9337 ((((__INSTANCE__) == TIM1) && \
mbed_official 573:ad23fe03a082 9338 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9339 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9340 ((__CHANNEL__) == TIM_CHANNEL_3))) \
mbed_official 573:ad23fe03a082 9341 || \
mbed_official 573:ad23fe03a082 9342 (((__INSTANCE__) == TIM8) && \
mbed_official 573:ad23fe03a082 9343 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 573:ad23fe03a082 9344 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 573:ad23fe03a082 9345 ((__CHANNEL__) == TIM_CHANNEL_3))))
mbed_official 573:ad23fe03a082 9346
mbed_official 573:ad23fe03a082 9347 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
mbed_official 573:ad23fe03a082 9348 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9349 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9350 ((__INSTANCE__) == TIM8) )
mbed_official 573:ad23fe03a082 9351
mbed_official 573:ad23fe03a082 9352 /****************** TIM Instances : supporting synchronization ****************/
mbed_official 573:ad23fe03a082 9353 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
mbed_official 573:ad23fe03a082 9354 (((__INSTANCE__) == TIM1) || \
mbed_official 573:ad23fe03a082 9355 ((__INSTANCE__) == TIM2) || \
mbed_official 573:ad23fe03a082 9356 ((__INSTANCE__) == TIM3) || \
mbed_official 573:ad23fe03a082 9357 ((__INSTANCE__) == TIM4) || \
mbed_official 573:ad23fe03a082 9358 ((__INSTANCE__) == TIM5) || \
mbed_official 573:ad23fe03a082 9359 ((__INSTANCE__) == TIM6) || \
mbed_official 573:ad23fe03a082 9360 ((__INSTANCE__) == TIM7) || \
mbed_official 573:ad23fe03a082 9361 ((__INSTANCE__) == TIM8))
mbed_official 573:ad23fe03a082 9362
mbed_official 573:ad23fe03a082 9363 /******************** USART Instances : Synchronous mode **********************/
mbed_official 573:ad23fe03a082 9364 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 573:ad23fe03a082 9365 ((__INSTANCE__) == USART2) || \
mbed_official 573:ad23fe03a082 9366 ((__INSTANCE__) == USART3) || \
mbed_official 573:ad23fe03a082 9367 ((__INSTANCE__) == USART6))
mbed_official 573:ad23fe03a082 9368
mbed_official 573:ad23fe03a082 9369 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 573:ad23fe03a082 9370 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 573:ad23fe03a082 9371 ((__INSTANCE__) == USART2) || \
mbed_official 573:ad23fe03a082 9372 ((__INSTANCE__) == USART3) || \
mbed_official 573:ad23fe03a082 9373 ((__INSTANCE__) == UART4) || \
mbed_official 573:ad23fe03a082 9374 ((__INSTANCE__) == UART5) || \
mbed_official 573:ad23fe03a082 9375 ((__INSTANCE__) == USART6) || \
mbed_official 573:ad23fe03a082 9376 ((__INSTANCE__) == UART7) || \
mbed_official 573:ad23fe03a082 9377 ((__INSTANCE__) == UART8))
mbed_official 573:ad23fe03a082 9378
mbed_official 573:ad23fe03a082 9379 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 573:ad23fe03a082 9380 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 573:ad23fe03a082 9381 ((__INSTANCE__) == USART2) || \
mbed_official 573:ad23fe03a082 9382 ((__INSTANCE__) == USART3) || \
mbed_official 573:ad23fe03a082 9383 ((__INSTANCE__) == UART4) || \
mbed_official 573:ad23fe03a082 9384 ((__INSTANCE__) == UART5) || \
mbed_official 573:ad23fe03a082 9385 ((__INSTANCE__) == USART6) || \
mbed_official 573:ad23fe03a082 9386 ((__INSTANCE__) == UART7) || \
mbed_official 573:ad23fe03a082 9387 ((__INSTANCE__) == UART8))
mbed_official 573:ad23fe03a082 9388
mbed_official 573:ad23fe03a082 9389 /********************* UART Instances : Smart card mode ***********************/
mbed_official 573:ad23fe03a082 9390 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 573:ad23fe03a082 9391 ((__INSTANCE__) == USART2) || \
mbed_official 573:ad23fe03a082 9392 ((__INSTANCE__) == USART3) || \
mbed_official 573:ad23fe03a082 9393 ((__INSTANCE__) == USART6))
mbed_official 573:ad23fe03a082 9394
mbed_official 573:ad23fe03a082 9395 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 573:ad23fe03a082 9396 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 573:ad23fe03a082 9397 ((__INSTANCE__) == USART2) || \
mbed_official 573:ad23fe03a082 9398 ((__INSTANCE__) == USART3) || \
mbed_official 573:ad23fe03a082 9399 ((__INSTANCE__) == UART4) || \
mbed_official 573:ad23fe03a082 9400 ((__INSTANCE__) == UART5) || \
mbed_official 573:ad23fe03a082 9401 ((__INSTANCE__) == USART6) || \
mbed_official 573:ad23fe03a082 9402 ((__INSTANCE__) == UART7) || \
mbed_official 573:ad23fe03a082 9403 ((__INSTANCE__) == UART8))
mbed_official 573:ad23fe03a082 9404
mbed_official 573:ad23fe03a082 9405 /****************************** IWDG Instances ********************************/
mbed_official 573:ad23fe03a082 9406 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
mbed_official 573:ad23fe03a082 9407
mbed_official 573:ad23fe03a082 9408 /****************************** WWDG Instances ********************************/
mbed_official 573:ad23fe03a082 9409 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
mbed_official 573:ad23fe03a082 9410
mbed_official 573:ad23fe03a082 9411
mbed_official 573:ad23fe03a082 9412 /******************************************************************************/
mbed_official 573:ad23fe03a082 9413 /* For a painless codes migration between the STM32F7xx device product */
mbed_official 573:ad23fe03a082 9414 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 573:ad23fe03a082 9415 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 573:ad23fe03a082 9416 /* No need to update developed interrupt code when moving across */
mbed_official 573:ad23fe03a082 9417 /* product lines within the same STM32F7 Family */
mbed_official 573:ad23fe03a082 9418 /******************************************************************************/
mbed_official 573:ad23fe03a082 9419
mbed_official 573:ad23fe03a082 9420 /* Aliases for __IRQn */
mbed_official 573:ad23fe03a082 9421 #define HASH_RNG_IRQn RNG_IRQn
mbed_official 573:ad23fe03a082 9422
mbed_official 573:ad23fe03a082 9423 /* Aliases for __IRQHandler */
mbed_official 573:ad23fe03a082 9424 #define HASH_RNG_IRQHandler RNG_IRQHandler
mbed_official 573:ad23fe03a082 9425
mbed_official 573:ad23fe03a082 9426 /**
mbed_official 573:ad23fe03a082 9427 * @}
mbed_official 573:ad23fe03a082 9428 */
mbed_official 573:ad23fe03a082 9429
mbed_official 573:ad23fe03a082 9430 /**
mbed_official 573:ad23fe03a082 9431 * @}
mbed_official 573:ad23fe03a082 9432 */
mbed_official 573:ad23fe03a082 9433
mbed_official 573:ad23fe03a082 9434 /**
mbed_official 573:ad23fe03a082 9435 * @}
mbed_official 573:ad23fe03a082 9436 */
mbed_official 573:ad23fe03a082 9437
mbed_official 573:ad23fe03a082 9438 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 9439 }
mbed_official 573:ad23fe03a082 9440 #endif /* __cplusplus */
mbed_official 573:ad23fe03a082 9441
mbed_official 573:ad23fe03a082 9442 #endif /* __STM32F746xx_H */
mbed_official 573:ad23fe03a082 9443
mbed_official 573:ad23fe03a082 9444
mbed_official 573:ad23fe03a082 9445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/