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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.h@632:7687fb9c4f91, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 14:00:11 2015 +0100
Revision:: 632:7687fb9c4f91
Parent:: 385:be64abf45658
Child:: 634:ac7d6880524d

Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0

Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/

NUCLEO_F303K8 - add support of the STM32F303K8

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	375:3d36234a1087	1	/**
mbed_official	375:3d36234a1087	2	******************************************************************************
mbed_official	375:3d36234a1087	3	* @file stm32f3xx_ll_fmc.h
mbed_official	375:3d36234a1087	4	* @author MCD Application Team
mbed_official	632:7687fb9c4f91	5	* @version V1.1.1
mbed_official	632:7687fb9c4f91	6	* @date 19-June-2015
mbed_official	375:3d36234a1087	7	* @brief Header file of FMC HAL module.
mbed_official	375:3d36234a1087	8	******************************************************************************
mbed_official	375:3d36234a1087	9	* @attention
mbed_official	375:3d36234a1087	10	*
mbed_official	632:7687fb9c4f91	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	375:3d36234a1087	12	*
mbed_official	375:3d36234a1087	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	375:3d36234a1087	14	* are permitted provided that the following conditions are met:
mbed_official	375:3d36234a1087	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	375:3d36234a1087	16	* this list of conditions and the following disclaimer.
mbed_official	375:3d36234a1087	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	375:3d36234a1087	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	375:3d36234a1087	19	* and/or other materials provided with the distribution.
mbed_official	375:3d36234a1087	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	375:3d36234a1087	21	* may be used to endorse or promote products derived from this software
mbed_official	375:3d36234a1087	22	* without specific prior written permission.
mbed_official	375:3d36234a1087	23	*
mbed_official	375:3d36234a1087	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	375:3d36234a1087	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	375:3d36234a1087	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	375:3d36234a1087	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	375:3d36234a1087	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	375:3d36234a1087	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	375:3d36234a1087	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	375:3d36234a1087	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	375:3d36234a1087	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	375:3d36234a1087	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	375:3d36234a1087	34	*
mbed_official	375:3d36234a1087	35	******************************************************************************
mbed_official	375:3d36234a1087	36	*/
mbed_official	375:3d36234a1087	37
mbed_official	375:3d36234a1087	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	375:3d36234a1087	39	#ifndef __STM32F3xx_LL_FMC_H
mbed_official	375:3d36234a1087	40	#define __STM32F3xx_LL_FMC_H
mbed_official	375:3d36234a1087	41
mbed_official	375:3d36234a1087	42	#ifdef __cplusplus
mbed_official	375:3d36234a1087	43	extern "C" {
mbed_official	375:3d36234a1087	44	#endif
mbed_official	375:3d36234a1087	45
mbed_official	375:3d36234a1087	46	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	375:3d36234a1087	47
mbed_official	375:3d36234a1087	48	/* Includes ------------------------------------------------------------------*/
mbed_official	375:3d36234a1087	49	#include "stm32f3xx_hal_def.h"
mbed_official	375:3d36234a1087	50
mbed_official	375:3d36234a1087	51	/** @addtogroup STM32F3xx_HAL_Driver
mbed_official	375:3d36234a1087	52	* @{
mbed_official	375:3d36234a1087	53	*/
mbed_official	375:3d36234a1087	54
mbed_official	375:3d36234a1087	55	/** @addtogroup FMC
mbed_official	375:3d36234a1087	56	* @{
mbed_official	375:3d36234a1087	57	*/
mbed_official	375:3d36234a1087	58
mbed_official	375:3d36234a1087	59	/* Exported typedef ----------------------------------------------------------*/
mbed_official	375:3d36234a1087	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	375:3d36234a1087	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	375:3d36234a1087	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official	375:3d36234a1087	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	375:3d36234a1087	64
mbed_official	375:3d36234a1087	65	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	375:3d36234a1087	66	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	375:3d36234a1087	67	#define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official	375:3d36234a1087	68	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	375:3d36234a1087	69
mbed_official	375:3d36234a1087	70	/**
mbed_official	375:3d36234a1087	71	* @brief FMC_NORSRAM Configuration Structure definition
mbed_official	375:3d36234a1087	72	*/
mbed_official	375:3d36234a1087	73	typedef struct
mbed_official	375:3d36234a1087	74	{
mbed_official	375:3d36234a1087	75	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	375:3d36234a1087	76	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	375:3d36234a1087	77
mbed_official	375:3d36234a1087	78	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	375:3d36234a1087	79	multiplexed on the data bus or not.
mbed_official	375:3d36234a1087	80	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	375:3d36234a1087	81
mbed_official	375:3d36234a1087	82	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	375:3d36234a1087	83	the corresponding memory device.
mbed_official	375:3d36234a1087	84	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	375:3d36234a1087	85
mbed_official	375:3d36234a1087	86	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	375:3d36234a1087	87	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	375:3d36234a1087	88
mbed_official	375:3d36234a1087	89	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	375:3d36234a1087	90	valid only with synchronous burst Flash memories.
mbed_official	375:3d36234a1087	91	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	375:3d36234a1087	92
mbed_official	375:3d36234a1087	93	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	375:3d36234a1087	94	the Flash memory in burst mode.
mbed_official	375:3d36234a1087	95	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	375:3d36234a1087	96
mbed_official	375:3d36234a1087	97	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	375:3d36234a1087	98	memory, valid only when accessing Flash memories in burst mode.
mbed_official	375:3d36234a1087	99	This parameter can be a value of @ref FMC_Wrap_Mode */
mbed_official	375:3d36234a1087	100
mbed_official	375:3d36234a1087	101	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	375:3d36234a1087	102	clock cycle before the wait state or during the wait state,
mbed_official	375:3d36234a1087	103	valid only when accessing memories in burst mode.
mbed_official	375:3d36234a1087	104	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	375:3d36234a1087	105
mbed_official	375:3d36234a1087	106	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	375:3d36234a1087	107	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	375:3d36234a1087	108
mbed_official	375:3d36234a1087	109	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	375:3d36234a1087	110	signal, valid for Flash memory access in burst mode.
mbed_official	375:3d36234a1087	111	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	375:3d36234a1087	112
mbed_official	375:3d36234a1087	113	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	375:3d36234a1087	114	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	375:3d36234a1087	115
mbed_official	375:3d36234a1087	116	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	375:3d36234a1087	117	valid only with asynchronous Flash memories.
mbed_official	375:3d36234a1087	118	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	375:3d36234a1087	119
mbed_official	375:3d36234a1087	120	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	375:3d36234a1087	121	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	375:3d36234a1087	122
mbed_official	375:3d36234a1087	123	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	375:3d36234a1087	124	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	375:3d36234a1087	125	through FMC_BCR2..4 registers.
mbed_official	375:3d36234a1087	126	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	375:3d36234a1087	127
mbed_official	375:3d36234a1087	128	}FMC_NORSRAM_InitTypeDef;
mbed_official	375:3d36234a1087	129
mbed_official	375:3d36234a1087	130	/**
mbed_official	375:3d36234a1087	131	* @brief FMC_NORSRAM Timing parameters structure definition
mbed_official	375:3d36234a1087	132	*/
mbed_official	375:3d36234a1087	133	typedef struct
mbed_official	375:3d36234a1087	134	{
mbed_official	375:3d36234a1087	135	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	375:3d36234a1087	136	the duration of the address setup time.
mbed_official	375:3d36234a1087	137	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	375:3d36234a1087	138	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	375:3d36234a1087	139
mbed_official	375:3d36234a1087	140	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	375:3d36234a1087	141	the duration of the address hold time.
mbed_official	375:3d36234a1087	142	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	375:3d36234a1087	143	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	375:3d36234a1087	144
mbed_official	375:3d36234a1087	145	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	375:3d36234a1087	146	the duration of the data setup time.
mbed_official	375:3d36234a1087	147	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	375:3d36234a1087	148	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	375:3d36234a1087	149	NOR Flash memories. */
mbed_official	375:3d36234a1087	150
mbed_official	375:3d36234a1087	151	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	375:3d36234a1087	152	the duration of the bus turnaround.
mbed_official	375:3d36234a1087	153	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	375:3d36234a1087	154	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	375:3d36234a1087	155
mbed_official	375:3d36234a1087	156	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	375:3d36234a1087	157	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	375:3d36234a1087	158	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	375:3d36234a1087	159	accesses. */
mbed_official	375:3d36234a1087	160
mbed_official	375:3d36234a1087	161	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	375:3d36234a1087	162	to the memory before getting the first data.
mbed_official	375:3d36234a1087	163	The parameter value depends on the memory type as shown below:
mbed_official	375:3d36234a1087	164	- It must be set to 0 in case of a CRAM
mbed_official	375:3d36234a1087	165	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	375:3d36234a1087	166	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	375:3d36234a1087	167	with synchronous burst mode enable */
mbed_official	375:3d36234a1087	168
mbed_official	375:3d36234a1087	169	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	375:3d36234a1087	170	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	375:3d36234a1087	171
mbed_official	375:3d36234a1087	172	}FMC_NORSRAM_TimingTypeDef;
mbed_official	375:3d36234a1087	173
mbed_official	375:3d36234a1087	174	/**
mbed_official	375:3d36234a1087	175	* @brief FMC_NAND Configuration Structure definition
mbed_official	375:3d36234a1087	176	*/
mbed_official	375:3d36234a1087	177	typedef struct
mbed_official	375:3d36234a1087	178	{
mbed_official	375:3d36234a1087	179	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	375:3d36234a1087	180	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	375:3d36234a1087	181
mbed_official	375:3d36234a1087	182	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	375:3d36234a1087	183	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	375:3d36234a1087	184
mbed_official	375:3d36234a1087	185	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	375:3d36234a1087	186	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	375:3d36234a1087	187
mbed_official	375:3d36234a1087	188	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	375:3d36234a1087	189	This parameter can be any value of @ref FMC_ECC */
mbed_official	375:3d36234a1087	190
mbed_official	375:3d36234a1087	191	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	375:3d36234a1087	192	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	375:3d36234a1087	193
mbed_official	375:3d36234a1087	194	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	375:3d36234a1087	195	delay between CLE low and RE low.
mbed_official	375:3d36234a1087	196	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	197
mbed_official	375:3d36234a1087	198	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	375:3d36234a1087	199	delay between ALE low and RE low.
mbed_official	375:3d36234a1087	200	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	201
mbed_official	375:3d36234a1087	202	}FMC_NAND_InitTypeDef;
mbed_official	375:3d36234a1087	203
mbed_official	375:3d36234a1087	204	/**
mbed_official	375:3d36234a1087	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
mbed_official	375:3d36234a1087	206	*/
mbed_official	375:3d36234a1087	207	typedef struct
mbed_official	375:3d36234a1087	208	{
mbed_official	375:3d36234a1087	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	375:3d36234a1087	210	the command assertion for NAND-Flash read or write access
mbed_official	375:3d36234a1087	211	to common/Attribute or I/O memory space (depending on
mbed_official	375:3d36234a1087	212	the memory space timing to be configured).
mbed_official	375:3d36234a1087	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	214
mbed_official	375:3d36234a1087	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	375:3d36234a1087	216	command for NAND-Flash read or write access to
mbed_official	375:3d36234a1087	217	common/Attribute or I/O memory space (depending on the
mbed_official	375:3d36234a1087	218	memory space timing to be configured).
mbed_official	375:3d36234a1087	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	220
mbed_official	375:3d36234a1087	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	375:3d36234a1087	222	(and data for write access) after the command de-assertion
mbed_official	375:3d36234a1087	223	for NAND-Flash read or write access to common/Attribute
mbed_official	375:3d36234a1087	224	or I/O memory space (depending on the memory space timing
mbed_official	375:3d36234a1087	225	to be configured).
mbed_official	375:3d36234a1087	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	227
mbed_official	375:3d36234a1087	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	375:3d36234a1087	229	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	375:3d36234a1087	230	write access to common/Attribute or I/O memory space (depending
mbed_official	375:3d36234a1087	231	on the memory space timing to be configured).
mbed_official	375:3d36234a1087	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	233
mbed_official	375:3d36234a1087	234	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	375:3d36234a1087	235
mbed_official	375:3d36234a1087	236	/**
mbed_official	375:3d36234a1087	237	* @brief FMC_NAND Configuration Structure definition
mbed_official	375:3d36234a1087	238	*/
mbed_official	375:3d36234a1087	239	typedef struct
mbed_official	375:3d36234a1087	240	{
mbed_official	375:3d36234a1087	241	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	375:3d36234a1087	242	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	375:3d36234a1087	243
mbed_official	375:3d36234a1087	244	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	375:3d36234a1087	245	delay between CLE low and RE low.
mbed_official	375:3d36234a1087	246	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	247
mbed_official	375:3d36234a1087	248	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	375:3d36234a1087	249	delay between ALE low and RE low.
mbed_official	375:3d36234a1087	250	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	375:3d36234a1087	251
mbed_official	375:3d36234a1087	252	}FMC_PCCARD_InitTypeDef;
mbed_official	375:3d36234a1087	253
mbed_official	375:3d36234a1087	254	/* Exported constants --------------------------------------------------------*/
mbed_official	375:3d36234a1087	255
mbed_official	375:3d36234a1087	256	/** @defgroup FMC_NOR_SRAM_Controller
mbed_official	375:3d36234a1087	257	* @{
mbed_official	375:3d36234a1087	258	*/
mbed_official	375:3d36234a1087	259
mbed_official	375:3d36234a1087	260	/** @defgroup FMC_NORSRAM_Bank
mbed_official	375:3d36234a1087	261	* @{
mbed_official	375:3d36234a1087	262	*/
mbed_official	375:3d36234a1087	263	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	264	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	375:3d36234a1087	265	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	375:3d36234a1087	266	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	375:3d36234a1087	267
mbed_official	375:3d36234a1087	268	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	375:3d36234a1087	269	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	375:3d36234a1087	270	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	375:3d36234a1087	271	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	375:3d36234a1087	272	/**
mbed_official	375:3d36234a1087	273	* @}
mbed_official	375:3d36234a1087	274	*/
mbed_official	375:3d36234a1087	275
mbed_official	375:3d36234a1087	276	/** @defgroup FMC_Data_Address_Bus_Multiplexing
mbed_official	375:3d36234a1087	277	* @{
mbed_official	375:3d36234a1087	278	*/
mbed_official	375:3d36234a1087	279	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	280	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	375:3d36234a1087	281
mbed_official	375:3d36234a1087	282	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	375:3d36234a1087	283	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	375:3d36234a1087	284	/**
mbed_official	375:3d36234a1087	285	* @}
mbed_official	375:3d36234a1087	286	*/
mbed_official	375:3d36234a1087	287
mbed_official	375:3d36234a1087	288	/** @defgroup FMC_Memory_Type
mbed_official	375:3d36234a1087	289	* @{
mbed_official	375:3d36234a1087	290	*/
mbed_official	375:3d36234a1087	291	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	292	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	375:3d36234a1087	293	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	375:3d36234a1087	294
mbed_official	375:3d36234a1087	295	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	375:3d36234a1087	296	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	375:3d36234a1087	297	((MEMORY) == FMC_MEMORY_TYPE_NOR))
mbed_official	375:3d36234a1087	298	/**
mbed_official	375:3d36234a1087	299	* @}
mbed_official	375:3d36234a1087	300	*/
mbed_official	375:3d36234a1087	301
mbed_official	375:3d36234a1087	302	/** @defgroup FMC_NORSRAM_Data_Width
mbed_official	375:3d36234a1087	303	* @{
mbed_official	375:3d36234a1087	304	*/
mbed_official	375:3d36234a1087	305	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	306	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	375:3d36234a1087	307	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	375:3d36234a1087	308
mbed_official	375:3d36234a1087	309	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	375:3d36234a1087	310	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	375:3d36234a1087	311	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	375:3d36234a1087	312	/**
mbed_official	375:3d36234a1087	313	* @}
mbed_official	375:3d36234a1087	314	*/
mbed_official	375:3d36234a1087	315
mbed_official	375:3d36234a1087	316	/** @defgroup FMC_NORSRAM_Flash_Access
mbed_official	375:3d36234a1087	317	* @{
mbed_official	375:3d36234a1087	318	*/
mbed_official	375:3d36234a1087	319	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	375:3d36234a1087	320	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	321	/**
mbed_official	375:3d36234a1087	322	* @}
mbed_official	375:3d36234a1087	323	*/
mbed_official	375:3d36234a1087	324
mbed_official	375:3d36234a1087	325	/** @defgroup FMC_Burst_Access_Mode
mbed_official	375:3d36234a1087	326	* @{
mbed_official	375:3d36234a1087	327	*/
mbed_official	375:3d36234a1087	328	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	329	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	375:3d36234a1087	330
mbed_official	375:3d36234a1087	331	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	375:3d36234a1087	332	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	375:3d36234a1087	333	/**
mbed_official	375:3d36234a1087	334	* @}
mbed_official	375:3d36234a1087	335	*/
mbed_official	375:3d36234a1087	336
mbed_official	375:3d36234a1087	337
mbed_official	375:3d36234a1087	338	/** @defgroup FMC_Wait_Signal_Polarity
mbed_official	375:3d36234a1087	339	* @{
mbed_official	375:3d36234a1087	340	*/
mbed_official	375:3d36234a1087	341	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	342	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	375:3d36234a1087	343
mbed_official	375:3d36234a1087	344	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	375:3d36234a1087	345	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	375:3d36234a1087	346	/**
mbed_official	375:3d36234a1087	347	* @}
mbed_official	375:3d36234a1087	348	*/
mbed_official	375:3d36234a1087	349
mbed_official	375:3d36234a1087	350	/** @defgroup FMC_Wrap_Mode
mbed_official	375:3d36234a1087	351	* @{
mbed_official	375:3d36234a1087	352	*/
mbed_official	375:3d36234a1087	353	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	354	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	375:3d36234a1087	355
mbed_official	375:3d36234a1087	356	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	375:3d36234a1087	357	((MODE) == FMC_WRAP_MODE_ENABLE))
mbed_official	375:3d36234a1087	358	/**
mbed_official	375:3d36234a1087	359	* @}
mbed_official	375:3d36234a1087	360	*/
mbed_official	375:3d36234a1087	361
mbed_official	375:3d36234a1087	362	/** @defgroup FMC_Wait_Timing
mbed_official	375:3d36234a1087	363	* @{
mbed_official	375:3d36234a1087	364	*/
mbed_official	375:3d36234a1087	365	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	366	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	375:3d36234a1087	367
mbed_official	375:3d36234a1087	368	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	375:3d36234a1087	369	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	375:3d36234a1087	370	/**
mbed_official	375:3d36234a1087	371	* @}
mbed_official	375:3d36234a1087	372	*/
mbed_official	375:3d36234a1087	373
mbed_official	375:3d36234a1087	374	/** @defgroup FMC_Write_Operation
mbed_official	375:3d36234a1087	375	* @{
mbed_official	375:3d36234a1087	376	*/
mbed_official	375:3d36234a1087	377	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	378	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	375:3d36234a1087	379
mbed_official	375:3d36234a1087	380	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	375:3d36234a1087	381	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	375:3d36234a1087	382	/**
mbed_official	375:3d36234a1087	383	* @}
mbed_official	375:3d36234a1087	384	*/
mbed_official	375:3d36234a1087	385
mbed_official	375:3d36234a1087	386	/** @defgroup FMC_Wait_Signal
mbed_official	375:3d36234a1087	387	* @{
mbed_official	375:3d36234a1087	388	*/
mbed_official	375:3d36234a1087	389	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	390	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	375:3d36234a1087	391
mbed_official	375:3d36234a1087	392	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	375:3d36234a1087	393	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	375:3d36234a1087	394	/**
mbed_official	375:3d36234a1087	395	* @}
mbed_official	375:3d36234a1087	396	*/
mbed_official	375:3d36234a1087	397
mbed_official	375:3d36234a1087	398	/** @defgroup FMC_Extended_Mode
mbed_official	375:3d36234a1087	399	* @{
mbed_official	375:3d36234a1087	400	*/
mbed_official	375:3d36234a1087	401	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	402	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	375:3d36234a1087	403
mbed_official	375:3d36234a1087	404	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	375:3d36234a1087	405	((MODE) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	375:3d36234a1087	406	/**
mbed_official	375:3d36234a1087	407	* @}
mbed_official	375:3d36234a1087	408	*/
mbed_official	375:3d36234a1087	409
mbed_official	375:3d36234a1087	410	/** @defgroup FMC_AsynchronousWait
mbed_official	375:3d36234a1087	411	* @{
mbed_official	375:3d36234a1087	412	*/
mbed_official	375:3d36234a1087	413	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	414	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	375:3d36234a1087	415
mbed_official	375:3d36234a1087	416	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	375:3d36234a1087	417	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	375:3d36234a1087	418	/**
mbed_official	375:3d36234a1087	419	* @}
mbed_official	375:3d36234a1087	420	*/
mbed_official	375:3d36234a1087	421
mbed_official	375:3d36234a1087	422	/** @defgroup FMC_Write_Burst
mbed_official	375:3d36234a1087	423	* @{
mbed_official	375:3d36234a1087	424	*/
mbed_official	375:3d36234a1087	425	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	426	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	375:3d36234a1087	427
mbed_official	375:3d36234a1087	428	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	375:3d36234a1087	429	((BURST) == FMC_WRITE_BURST_ENABLE))
mbed_official	375:3d36234a1087	430	/**
mbed_official	375:3d36234a1087	431	* @}
mbed_official	375:3d36234a1087	432	*/
mbed_official	375:3d36234a1087	433
mbed_official	375:3d36234a1087	434	/** @defgroup FMC_Continous_Clock
mbed_official	375:3d36234a1087	435	* @{
mbed_official	375:3d36234a1087	436	*/
mbed_official	375:3d36234a1087	437	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	438	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	375:3d36234a1087	439
mbed_official	375:3d36234a1087	440	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	375:3d36234a1087	441	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	375:3d36234a1087	442	/**
mbed_official	375:3d36234a1087	443	* @}
mbed_official	375:3d36234a1087	444	*/
mbed_official	375:3d36234a1087	445
mbed_official	375:3d36234a1087	446	/** @defgroup FMC_Address_Setup_Time
mbed_official	375:3d36234a1087	447	* @{
mbed_official	375:3d36234a1087	448	*/
mbed_official	375:3d36234a1087	449	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official	375:3d36234a1087	450	/**
mbed_official	375:3d36234a1087	451	* @}
mbed_official	375:3d36234a1087	452	*/
mbed_official	375:3d36234a1087	453
mbed_official	375:3d36234a1087	454	/** @defgroup FMC_Address_Hold_Time
mbed_official	375:3d36234a1087	455	* @{
mbed_official	375:3d36234a1087	456	*/
mbed_official	375:3d36234a1087	457	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official	375:3d36234a1087	458	/**
mbed_official	375:3d36234a1087	459	* @}
mbed_official	375:3d36234a1087	460	*/
mbed_official	375:3d36234a1087	461
mbed_official	375:3d36234a1087	462	/** @defgroup FMC_Data_Setup_Time
mbed_official	375:3d36234a1087	463	* @{
mbed_official	375:3d36234a1087	464	*/
mbed_official	375:3d36234a1087	465	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official	375:3d36234a1087	466	/**
mbed_official	375:3d36234a1087	467	* @}
mbed_official	375:3d36234a1087	468	*/
mbed_official	375:3d36234a1087	469
mbed_official	375:3d36234a1087	470	/** @defgroup FMC_Bus_Turn_around_Duration
mbed_official	375:3d36234a1087	471	* @{
mbed_official	375:3d36234a1087	472	*/
mbed_official	375:3d36234a1087	473	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official	375:3d36234a1087	474	/**
mbed_official	375:3d36234a1087	475	* @}
mbed_official	375:3d36234a1087	476	*/
mbed_official	375:3d36234a1087	477
mbed_official	375:3d36234a1087	478	/** @defgroup FMC_CLK_Division
mbed_official	375:3d36234a1087	479	* @{
mbed_official	375:3d36234a1087	480	*/
mbed_official	375:3d36234a1087	481	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	375:3d36234a1087	482	/**
mbed_official	375:3d36234a1087	483	* @}
mbed_official	375:3d36234a1087	484	*/
mbed_official	375:3d36234a1087	485
mbed_official	375:3d36234a1087	486	/** @defgroup FMC_Data_Latency
mbed_official	375:3d36234a1087	487	* @{
mbed_official	375:3d36234a1087	488	*/
mbed_official	375:3d36234a1087	489	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official	375:3d36234a1087	490	/**
mbed_official	375:3d36234a1087	491	* @}
mbed_official	375:3d36234a1087	492	*/
mbed_official	375:3d36234a1087	493
mbed_official	375:3d36234a1087	494	/** @defgroup FMC_Access_Mode
mbed_official	375:3d36234a1087	495	* @{
mbed_official	375:3d36234a1087	496	*/
mbed_official	375:3d36234a1087	497	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	498	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	375:3d36234a1087	499	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	375:3d36234a1087	500	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	375:3d36234a1087	501
mbed_official	375:3d36234a1087	502	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	375:3d36234a1087	503	((MODE) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	375:3d36234a1087	504	((MODE) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	375:3d36234a1087	505	((MODE) == FMC_ACCESS_MODE_D))
mbed_official	375:3d36234a1087	506	/**
mbed_official	375:3d36234a1087	507	* @}
mbed_official	375:3d36234a1087	508	*/
mbed_official	375:3d36234a1087	509
mbed_official	375:3d36234a1087	510	/**
mbed_official	375:3d36234a1087	511	* @}
mbed_official	375:3d36234a1087	512	*/
mbed_official	375:3d36234a1087	513
mbed_official	375:3d36234a1087	514	/** @defgroup FMC_NAND_Controller
mbed_official	375:3d36234a1087	515	* @{
mbed_official	375:3d36234a1087	516	*/
mbed_official	375:3d36234a1087	517
mbed_official	375:3d36234a1087	518	/** @defgroup FMC_NAND_Bank
mbed_official	375:3d36234a1087	519	* @{
mbed_official	375:3d36234a1087	520	*/
mbed_official	375:3d36234a1087	521	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	375:3d36234a1087	522	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	375:3d36234a1087	523
mbed_official	375:3d36234a1087	524	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
mbed_official	375:3d36234a1087	525	((BANK) == FMC_NAND_BANK3))
mbed_official	375:3d36234a1087	526	/**
mbed_official	375:3d36234a1087	527	* @}
mbed_official	375:3d36234a1087	528	*/
mbed_official	375:3d36234a1087	529
mbed_official	375:3d36234a1087	530	/** @defgroup FMC_Wait_feature
mbed_official	375:3d36234a1087	531	* @{
mbed_official	375:3d36234a1087	532	*/
mbed_official	375:3d36234a1087	533	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	534	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	375:3d36234a1087	535
mbed_official	375:3d36234a1087	536	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	375:3d36234a1087	537	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	375:3d36234a1087	538	/**
mbed_official	375:3d36234a1087	539	* @}
mbed_official	375:3d36234a1087	540	*/
mbed_official	375:3d36234a1087	541
mbed_official	375:3d36234a1087	542	/** @defgroup FMC_PCR_Memory_Type
mbed_official	375:3d36234a1087	543	* @{
mbed_official	375:3d36234a1087	544	*/
mbed_official	375:3d36234a1087	545	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	546	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	375:3d36234a1087	547	/**
mbed_official	375:3d36234a1087	548	* @}
mbed_official	375:3d36234a1087	549	*/
mbed_official	375:3d36234a1087	550
mbed_official	375:3d36234a1087	551	/** @defgroup FMC_NAND_Data_Width
mbed_official	375:3d36234a1087	552	* @{
mbed_official	375:3d36234a1087	553	*/
mbed_official	375:3d36234a1087	554	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	555	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	375:3d36234a1087	556
mbed_official	375:3d36234a1087	557	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	375:3d36234a1087	558	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	375:3d36234a1087	559	/**
mbed_official	375:3d36234a1087	560	* @}
mbed_official	375:3d36234a1087	561	*/
mbed_official	375:3d36234a1087	562
mbed_official	375:3d36234a1087	563	/** @defgroup FMC_ECC
mbed_official	375:3d36234a1087	564	* @{
mbed_official	375:3d36234a1087	565	*/
mbed_official	375:3d36234a1087	566	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	567	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	375:3d36234a1087	568
mbed_official	375:3d36234a1087	569	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	375:3d36234a1087	570	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	375:3d36234a1087	571	/**
mbed_official	375:3d36234a1087	572	* @}
mbed_official	375:3d36234a1087	573	*/
mbed_official	375:3d36234a1087	574
mbed_official	375:3d36234a1087	575	/** @defgroup FMC_ECC_Page_Size
mbed_official	375:3d36234a1087	576	* @{
mbed_official	375:3d36234a1087	577	*/
mbed_official	375:3d36234a1087	578	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	375:3d36234a1087	579	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	375:3d36234a1087	580	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	375:3d36234a1087	581	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	375:3d36234a1087	582	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	375:3d36234a1087	583	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	375:3d36234a1087	584
mbed_official	375:3d36234a1087	585	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	375:3d36234a1087	586	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	375:3d36234a1087	587	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	375:3d36234a1087	588	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	375:3d36234a1087	589	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	375:3d36234a1087	590	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	375:3d36234a1087	591	/**
mbed_official	375:3d36234a1087	592	* @}
mbed_official	375:3d36234a1087	593	*/
mbed_official	375:3d36234a1087	594
mbed_official	375:3d36234a1087	595	/** @defgroup FMC_TCLR_Setup_Time
mbed_official	375:3d36234a1087	596	* @{
mbed_official	375:3d36234a1087	597	*/
mbed_official	375:3d36234a1087	598	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	599	/**
mbed_official	375:3d36234a1087	600	* @}
mbed_official	375:3d36234a1087	601	*/
mbed_official	375:3d36234a1087	602
mbed_official	375:3d36234a1087	603	/** @defgroup FMC_TAR_Setup_Time
mbed_official	375:3d36234a1087	604	* @{
mbed_official	375:3d36234a1087	605	*/
mbed_official	375:3d36234a1087	606	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	607	/**
mbed_official	375:3d36234a1087	608	* @}
mbed_official	375:3d36234a1087	609	*/
mbed_official	375:3d36234a1087	610
mbed_official	375:3d36234a1087	611	/** @defgroup FMC_Setup_Time
mbed_official	375:3d36234a1087	612	* @{
mbed_official	375:3d36234a1087	613	*/
mbed_official	375:3d36234a1087	614	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	615	/**
mbed_official	375:3d36234a1087	616	* @}
mbed_official	375:3d36234a1087	617	*/
mbed_official	375:3d36234a1087	618
mbed_official	375:3d36234a1087	619	/** @defgroup FMC_Wait_Setup_Time
mbed_official	375:3d36234a1087	620	* @{
mbed_official	375:3d36234a1087	621	*/
mbed_official	375:3d36234a1087	622	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	623	/**
mbed_official	375:3d36234a1087	624	* @}
mbed_official	375:3d36234a1087	625	*/
mbed_official	375:3d36234a1087	626
mbed_official	375:3d36234a1087	627	/** @defgroup FMC_Hold_Setup_Time
mbed_official	375:3d36234a1087	628	* @{
mbed_official	375:3d36234a1087	629	*/
mbed_official	375:3d36234a1087	630	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	631	/**
mbed_official	375:3d36234a1087	632	* @}
mbed_official	375:3d36234a1087	633	*/
mbed_official	375:3d36234a1087	634
mbed_official	375:3d36234a1087	635	/** @defgroup FMC_HiZ_Setup_Time
mbed_official	375:3d36234a1087	636	* @{
mbed_official	375:3d36234a1087	637	*/
mbed_official	375:3d36234a1087	638	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	375:3d36234a1087	639	/**
mbed_official	375:3d36234a1087	640	* @}
mbed_official	375:3d36234a1087	641	*/
mbed_official	375:3d36234a1087	642
mbed_official	375:3d36234a1087	643	/**
mbed_official	375:3d36234a1087	644	* @}
mbed_official	375:3d36234a1087	645	*/
mbed_official	375:3d36234a1087	646
mbed_official	375:3d36234a1087	647	/** @defgroup FMC_NORSRAM_Device_Instance
mbed_official	375:3d36234a1087	648	* @{
mbed_official	375:3d36234a1087	649	*/
mbed_official	375:3d36234a1087	650	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
mbed_official	375:3d36234a1087	651	/**
mbed_official	375:3d36234a1087	652	* @}
mbed_official	375:3d36234a1087	653	*/
mbed_official	375:3d36234a1087	654
mbed_official	375:3d36234a1087	655	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
mbed_official	375:3d36234a1087	656	* @{
mbed_official	375:3d36234a1087	657	*/
mbed_official	375:3d36234a1087	658	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	375:3d36234a1087	659	/**
mbed_official	375:3d36234a1087	660	* @}
mbed_official	375:3d36234a1087	661	*/
mbed_official	375:3d36234a1087	662
mbed_official	375:3d36234a1087	663	/** @defgroup FMC_NAND_Device_Instance
mbed_official	375:3d36234a1087	664	* @{
mbed_official	375:3d36234a1087	665	*/
mbed_official	375:3d36234a1087	666	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
mbed_official	375:3d36234a1087	667	/**
mbed_official	375:3d36234a1087	668	* @}
mbed_official	375:3d36234a1087	669	*/
mbed_official	375:3d36234a1087	670
mbed_official	375:3d36234a1087	671	/** @defgroup FMC_PCCARD_Device_Instance
mbed_official	375:3d36234a1087	672	* @{
mbed_official	375:3d36234a1087	673	*/
mbed_official	375:3d36234a1087	674	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
mbed_official	375:3d36234a1087	675
mbed_official	375:3d36234a1087	676	/**
mbed_official	375:3d36234a1087	677	* @}
mbed_official	375:3d36234a1087	678	*/
mbed_official	375:3d36234a1087	679
mbed_official	375:3d36234a1087	680	/** @defgroup FMC_Interrupt_definition
mbed_official	375:3d36234a1087	681	* @brief FMC Interrupt definition
mbed_official	375:3d36234a1087	682	* @{
mbed_official	375:3d36234a1087	683	*/
mbed_official	375:3d36234a1087	684	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	375:3d36234a1087	685	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	375:3d36234a1087	686	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	375:3d36234a1087	687	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	375:3d36234a1087	688
mbed_official	375:3d36234a1087	689	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	375:3d36234a1087	690
mbed_official	375:3d36234a1087	691	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
mbed_official	375:3d36234a1087	692	((IT) == FMC_IT_LEVEL) \|\| \
mbed_official	375:3d36234a1087	693	((IT) == FMC_IT_FALLING_EDGE) \|\| \
mbed_official	375:3d36234a1087	694	((IT) == FMC_IT_REFRESH_ERROR))
mbed_official	375:3d36234a1087	695	/**
mbed_official	375:3d36234a1087	696	* @}
mbed_official	375:3d36234a1087	697	*/
mbed_official	375:3d36234a1087	698
mbed_official	375:3d36234a1087	699	/** @defgroup FMC_Flag_definition
mbed_official	375:3d36234a1087	700	* @brief FMC Flag definition
mbed_official	375:3d36234a1087	701	* @{
mbed_official	375:3d36234a1087	702	*/
mbed_official	375:3d36234a1087	703	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	375:3d36234a1087	704	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	375:3d36234a1087	705	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	375:3d36234a1087	706	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	375:3d36234a1087	707
mbed_official	375:3d36234a1087	708	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
mbed_official	375:3d36234a1087	709	((FLAG) == FMC_FLAG_LEVEL) \|\| \
mbed_official	375:3d36234a1087	710	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
mbed_official	375:3d36234a1087	711	((FLAG) == FMC_FLAG_FEMPT))
mbed_official	375:3d36234a1087	712
mbed_official	375:3d36234a1087	713	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	375:3d36234a1087	714	/**
mbed_official	375:3d36234a1087	715	* @}
mbed_official	375:3d36234a1087	716	*/
mbed_official	375:3d36234a1087	717
mbed_official	375:3d36234a1087	718	/* Exported macro ------------------------------------------------------------*/
mbed_official	375:3d36234a1087	719
mbed_official	375:3d36234a1087	720	/** @defgroup FMC_NOR_Macros
mbed_official	375:3d36234a1087	721	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	375:3d36234a1087	722	* @{
mbed_official	375:3d36234a1087	723	*/
mbed_official	375:3d36234a1087	724
mbed_official	375:3d36234a1087	725	/**
mbed_official	375:3d36234a1087	726	* @brief Enable the NORSRAM device access.
mbed_official	375:3d36234a1087	727	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	375:3d36234a1087	728	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	375:3d36234a1087	729	* @retval None
mbed_official	375:3d36234a1087	730	*/
mbed_official	375:3d36234a1087	731	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	375:3d36234a1087	732
mbed_official	375:3d36234a1087	733	/**
mbed_official	375:3d36234a1087	734	* @brief Disable the NORSRAM device access.
mbed_official	375:3d36234a1087	735	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	375:3d36234a1087	736	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	375:3d36234a1087	737	* @retval None
mbed_official	375:3d36234a1087	738	*/
mbed_official	375:3d36234a1087	739	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	375:3d36234a1087	740
mbed_official	375:3d36234a1087	741	/**
mbed_official	375:3d36234a1087	742	* @}
mbed_official	375:3d36234a1087	743	*/
mbed_official	375:3d36234a1087	744
mbed_official	375:3d36234a1087	745	/** @defgroup FMC_NAND_Macros
mbed_official	375:3d36234a1087	746	* @brief macros to handle NAND device enable/disable
mbed_official	375:3d36234a1087	747	* @{
mbed_official	375:3d36234a1087	748	*/
mbed_official	375:3d36234a1087	749
mbed_official	375:3d36234a1087	750	/**
mbed_official	375:3d36234a1087	751	* @brief Enable the NAND device access.
mbed_official	375:3d36234a1087	752	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	753	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	754	* @retval None
mbed_official	375:3d36234a1087	755	*/
mbed_official	375:3d36234a1087	756	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
mbed_official	375:3d36234a1087	757	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
mbed_official	375:3d36234a1087	758
mbed_official	375:3d36234a1087	759	/**
mbed_official	375:3d36234a1087	760	* @brief Disable the NAND device access.
mbed_official	375:3d36234a1087	761	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	762	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	763	* @retval None
mbed_official	375:3d36234a1087	764	*/
mbed_official	375:3d36234a1087	765	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official	375:3d36234a1087	766	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official	375:3d36234a1087	767	/**
mbed_official	375:3d36234a1087	768	* @}
mbed_official	375:3d36234a1087	769	*/
mbed_official	375:3d36234a1087	770
mbed_official	375:3d36234a1087	771	/** @defgroup FMC_PCCARD_Macros
mbed_official	375:3d36234a1087	772	* @brief macros to handle SRAM read/write operations
mbed_official	375:3d36234a1087	773	* @{
mbed_official	375:3d36234a1087	774	*/
mbed_official	375:3d36234a1087	775
mbed_official	375:3d36234a1087	776	/**
mbed_official	375:3d36234a1087	777	* @brief Enable the PCCARD device access.
mbed_official	375:3d36234a1087	778	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	779	* @retval None
mbed_official	375:3d36234a1087	780	*/
mbed_official	375:3d36234a1087	781	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
mbed_official	375:3d36234a1087	782
mbed_official	375:3d36234a1087	783	/**
mbed_official	375:3d36234a1087	784	* @brief Disable the PCCARD device access.
mbed_official	375:3d36234a1087	785	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	786	* @retval None
mbed_official	375:3d36234a1087	787	*/
mbed_official	375:3d36234a1087	788	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official	375:3d36234a1087	789	/**
mbed_official	375:3d36234a1087	790	* @}
mbed_official	375:3d36234a1087	791	*/
mbed_official	375:3d36234a1087	792
mbed_official	375:3d36234a1087	793	/** @defgroup FMC_Interrupt
mbed_official	375:3d36234a1087	794	* @brief macros to handle FMC interrupts
mbed_official	375:3d36234a1087	795	* @{
mbed_official	375:3d36234a1087	796	*/
mbed_official	375:3d36234a1087	797
mbed_official	375:3d36234a1087	798	/**
mbed_official	375:3d36234a1087	799	* @brief Enable the NAND device interrupt.
mbed_official	375:3d36234a1087	800	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	801	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	802	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	375:3d36234a1087	803	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	804	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	375:3d36234a1087	805	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	375:3d36234a1087	806	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	375:3d36234a1087	807	* @retval None
mbed_official	375:3d36234a1087	808	*/
mbed_official	375:3d36234a1087	809	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	375:3d36234a1087	810	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	375:3d36234a1087	811
mbed_official	375:3d36234a1087	812	/**
mbed_official	375:3d36234a1087	813	* @brief Disable the NAND device interrupt.
mbed_official	375:3d36234a1087	814	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	815	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	816	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	375:3d36234a1087	817	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	818	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	375:3d36234a1087	819	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	375:3d36234a1087	820	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	375:3d36234a1087	821	* @retval None
mbed_official	375:3d36234a1087	822	*/
mbed_official	375:3d36234a1087	823	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	375:3d36234a1087	824	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	375:3d36234a1087	825
mbed_official	375:3d36234a1087	826	/**
mbed_official	375:3d36234a1087	827	* @brief Get flag status of the NAND device.
mbed_official	375:3d36234a1087	828	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	829	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	830	* @param __FLAG__: FMC_NAND flag
mbed_official	375:3d36234a1087	831	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	832	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	375:3d36234a1087	833	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	375:3d36234a1087	834	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	375:3d36234a1087	835	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	375:3d36234a1087	836	* @retval The state of FLAG (SET or RESET).
mbed_official	375:3d36234a1087	837	*/
mbed_official	375:3d36234a1087	838	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	375:3d36234a1087	839	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	375:3d36234a1087	840	/**
mbed_official	375:3d36234a1087	841	* @brief Clear flag status of the NAND device.
mbed_official	375:3d36234a1087	842	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	375:3d36234a1087	843	* @param __BANK__: FMC_NAND Bank
mbed_official	375:3d36234a1087	844	* @param __FLAG__: FMC_NAND flag
mbed_official	375:3d36234a1087	845	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	846	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	375:3d36234a1087	847	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	375:3d36234a1087	848	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	375:3d36234a1087	849	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	375:3d36234a1087	850	* @retval None
mbed_official	375:3d36234a1087	851	*/
mbed_official	375:3d36234a1087	852	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	375:3d36234a1087	853	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	375:3d36234a1087	854	/**
mbed_official	375:3d36234a1087	855	* @brief Enable the PCCARD device interrupt.
mbed_official	375:3d36234a1087	856	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	857	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	375:3d36234a1087	858	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	859	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	375:3d36234a1087	860	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	375:3d36234a1087	861	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	375:3d36234a1087	862	* @retval None
mbed_official	375:3d36234a1087	863	*/
mbed_official	375:3d36234a1087	864	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	375:3d36234a1087	865
mbed_official	375:3d36234a1087	866	/**
mbed_official	375:3d36234a1087	867	* @brief Disable the PCCARD device interrupt.
mbed_official	375:3d36234a1087	868	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	869	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	375:3d36234a1087	870	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	871	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	375:3d36234a1087	872	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	375:3d36234a1087	873	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	375:3d36234a1087	874	* @retval None
mbed_official	375:3d36234a1087	875	*/
mbed_official	375:3d36234a1087	876	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	375:3d36234a1087	877
mbed_official	375:3d36234a1087	878	/**
mbed_official	375:3d36234a1087	879	* @brief Get flag status of the PCCARD device.
mbed_official	375:3d36234a1087	880	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	881	* @param __FLAG__: FMC_PCCARD flag
mbed_official	375:3d36234a1087	882	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	883	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	375:3d36234a1087	884	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	375:3d36234a1087	885	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	375:3d36234a1087	886	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	375:3d36234a1087	887	* @retval The state of FLAG (SET or RESET).
mbed_official	375:3d36234a1087	888	*/
mbed_official	375:3d36234a1087	889	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	375:3d36234a1087	890
mbed_official	375:3d36234a1087	891	/**
mbed_official	375:3d36234a1087	892	* @brief Clear flag status of the PCCARD device.
mbed_official	375:3d36234a1087	893	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	375:3d36234a1087	894	* @param __FLAG__: FMC_PCCARD flag
mbed_official	375:3d36234a1087	895	* This parameter can be any combination of the following values:
mbed_official	375:3d36234a1087	896	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	375:3d36234a1087	897	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	375:3d36234a1087	898	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	375:3d36234a1087	899	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	375:3d36234a1087	900	* @retval None
mbed_official	375:3d36234a1087	901	*/
mbed_official	375:3d36234a1087	902	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	375:3d36234a1087	903
mbed_official	375:3d36234a1087	904	/**
mbed_official	375:3d36234a1087	905	* @}
mbed_official	375:3d36234a1087	906	*/
mbed_official	375:3d36234a1087	907
mbed_official	375:3d36234a1087	908	/* Exported functions --------------------------------------------------------*/
mbed_official	375:3d36234a1087	909
mbed_official	375:3d36234a1087	910	/* FMC_NORSRAM Controller functions *******************************************/
mbed_official	375:3d36234a1087	911	/* Initialization/de-initialization functions */
mbed_official	375:3d36234a1087	912	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	375:3d36234a1087	913	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	375:3d36234a1087	914	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	375:3d36234a1087	915	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	375:3d36234a1087	916
mbed_official	375:3d36234a1087	917	/* FMC_NORSRAM Control functions */
mbed_official	375:3d36234a1087	918	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	375:3d36234a1087	919	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	375:3d36234a1087	920
mbed_official	375:3d36234a1087	921	/* FMC_NAND Controller functions **********************************************/
mbed_official	375:3d36234a1087	922	/* Initialization/de-initialization functions */
mbed_official	375:3d36234a1087	923	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	375:3d36234a1087	924	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	375:3d36234a1087	925	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	375:3d36234a1087	926	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	375:3d36234a1087	927
mbed_official	375:3d36234a1087	928	/* FMC_NAND Control functions */
mbed_official	375:3d36234a1087	929	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	375:3d36234a1087	930	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	375:3d36234a1087	931	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	375:3d36234a1087	932
mbed_official	375:3d36234a1087	933	/* FMC_PCCARD Controller functions ********************************************/
mbed_official	375:3d36234a1087	934	/* Initialization/de-initialization functions */
mbed_official	375:3d36234a1087	935	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
mbed_official	375:3d36234a1087	936	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	375:3d36234a1087	937	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	375:3d36234a1087	938	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	375:3d36234a1087	939	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official	375:3d36234a1087	940
mbed_official	375:3d36234a1087	941	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	375:3d36234a1087	942	/**
mbed_official	375:3d36234a1087	943	* @}
mbed_official	375:3d36234a1087	944	*/
mbed_official	375:3d36234a1087	945
mbed_official	375:3d36234a1087	946	/**
mbed_official	375:3d36234a1087	947	* @}
mbed_official	375:3d36234a1087	948	*/
mbed_official	375:3d36234a1087	949
mbed_official	375:3d36234a1087	950	#ifdef __cplusplus
mbed_official	375:3d36234a1087	951	}
mbed_official	375:3d36234a1087	952	#endif
mbed_official	375:3d36234a1087	953
mbed_official	375:3d36234a1087	954	#endif /* __STM32F3xx_LL_FMC_H */
mbed_official	375:3d36234a1087	955
mbed_official	375:3d36234a1087	956	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/