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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c@632:7687fb9c4f91, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 14:00:11 2015 +0100
- Revision:
- 632:7687fb9c4f91
- Parent:
- 385:be64abf45658
- Child:
- 634:ac7d6880524d
Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0
Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/
NUCLEO_F303K8 - add support of the STM32F303K8
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 237:f3da66175598 | 1 | /** |
| mbed_official | 237:f3da66175598 | 2 | ****************************************************************************** |
| mbed_official | 237:f3da66175598 | 3 | * @file stm32f3xx_hal_tim_ex.c |
| mbed_official | 237:f3da66175598 | 4 | * @author MCD Application Team |
| mbed_official | 632:7687fb9c4f91 | 5 | * @version V1.1.1 |
| mbed_official | 632:7687fb9c4f91 | 6 | * @date 19-June-2015 |
| mbed_official | 237:f3da66175598 | 7 | * @brief TIM HAL module driver. |
| mbed_official | 237:f3da66175598 | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 375:3d36234a1087 | 9 | * functionalities of the Timer Extended peripheral: |
| mbed_official | 237:f3da66175598 | 10 | * + Time Hall Sensor Interface Initialization |
| mbed_official | 237:f3da66175598 | 11 | * + Time Hall Sensor Interface Start |
| mbed_official | 237:f3da66175598 | 12 | * + Time Complementary signal bread and dead time configuration |
| mbed_official | 237:f3da66175598 | 13 | * + Time Master and Slave synchronization configuration |
| mbed_official | 237:f3da66175598 | 14 | * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) |
| mbed_official | 237:f3da66175598 | 15 | * + Time OCRef clear configuration |
| mbed_official | 237:f3da66175598 | 16 | * + Timer remapping capabilities configuration |
| mbed_official | 237:f3da66175598 | 17 | @verbatim |
| mbed_official | 237:f3da66175598 | 18 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 19 | ##### TIMER Extended features ##### |
| mbed_official | 237:f3da66175598 | 20 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 21 | [..] |
| mbed_official | 375:3d36234a1087 | 22 | The Timer Extended features include: |
| mbed_official | 237:f3da66175598 | 23 | (#) Complementary outputs with programmable dead-time for : |
| mbed_official | 237:f3da66175598 | 24 | (++) Output Compare |
| mbed_official | 237:f3da66175598 | 25 | (++) PWM generation (Edge and Center-aligned Mode) |
| mbed_official | 237:f3da66175598 | 26 | (++) One-pulse mode output |
| mbed_official | 237:f3da66175598 | 27 | (#) Synchronization circuit to control the timer with external signals and to |
| mbed_official | 237:f3da66175598 | 28 | interconnect several timers together. |
| mbed_official | 237:f3da66175598 | 29 | (#) Break input to put the timer output signals in reset state or in a known state. |
| mbed_official | 237:f3da66175598 | 30 | (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for |
| mbed_official | 237:f3da66175598 | 31 | positioning purposes |
| mbed_official | 237:f3da66175598 | 32 | |
| mbed_official | 237:f3da66175598 | 33 | ##### How to use this driver ##### |
| mbed_official | 237:f3da66175598 | 34 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 35 | [..] |
| mbed_official | 237:f3da66175598 | 36 | (#) Initialize the TIM low level resources by implementing the following functions |
| mbed_official | 237:f3da66175598 | 37 | depending from feature used : |
| mbed_official | 237:f3da66175598 | 38 | (++) Complementary Output Compare : HAL_TIM_OC_MspInit() |
| mbed_official | 237:f3da66175598 | 39 | (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() |
| mbed_official | 237:f3da66175598 | 40 | (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() |
| mbed_official | 237:f3da66175598 | 41 | (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() |
| mbed_official | 237:f3da66175598 | 42 | |
| mbed_official | 237:f3da66175598 | 43 | (#) Initialize the TIM low level resources : |
| mbed_official | 237:f3da66175598 | 44 | (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); |
| mbed_official | 237:f3da66175598 | 45 | (##) TIM pins configuration |
| mbed_official | 237:f3da66175598 | 46 | (+++) Enable the clock for the TIM GPIOs using the following function: |
| mbed_official | 237:f3da66175598 | 47 | __GPIOx_CLK_ENABLE(); |
| mbed_official | 237:f3da66175598 | 48 | (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); |
| mbed_official | 237:f3da66175598 | 49 | |
| mbed_official | 237:f3da66175598 | 50 | (#) The external Clock can be configured, if needed (the default clock is the |
| mbed_official | 237:f3da66175598 | 51 | internal clock from the APBx), using the following function: |
| mbed_official | 237:f3da66175598 | 52 | HAL_TIM_ConfigClockSource, the clock configuration should be done before |
| mbed_official | 237:f3da66175598 | 53 | any start function. |
| mbed_official | 237:f3da66175598 | 54 | |
| mbed_official | 237:f3da66175598 | 55 | (#) Configure the TIM in the desired functioning mode using one of the |
| mbed_official | 237:f3da66175598 | 56 | initialization function of this driver: |
| mbed_official | 237:f3da66175598 | 57 | (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the |
| mbed_official | 237:f3da66175598 | 58 | Timer Hall Sensor Interface and the commutation event with the corresponding |
| mbed_official | 237:f3da66175598 | 59 | Interrupt and DMA request if needed (Note that One Timer is used to interface |
| mbed_official | 237:f3da66175598 | 60 | with the Hall sensor Interface and another Timer should be used to use |
| mbed_official | 237:f3da66175598 | 61 | the commutation event). |
| mbed_official | 237:f3da66175598 | 62 | |
| mbed_official | 237:f3da66175598 | 63 | (#) Activate the TIM peripheral using one of the start functions: |
| mbed_official | 375:3d36234a1087 | 64 | (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() |
| mbed_official | 237:f3da66175598 | 65 | (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() |
| mbed_official | 237:f3da66175598 | 66 | (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() |
| mbed_official | 237:f3da66175598 | 67 | (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). |
| mbed_official | 237:f3da66175598 | 68 | |
| mbed_official | 237:f3da66175598 | 69 | |
| mbed_official | 237:f3da66175598 | 70 | @endverbatim |
| mbed_official | 237:f3da66175598 | 71 | ****************************************************************************** |
| mbed_official | 237:f3da66175598 | 72 | * @attention |
| mbed_official | 237:f3da66175598 | 73 | * |
| mbed_official | 632:7687fb9c4f91 | 74 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 237:f3da66175598 | 75 | * |
| mbed_official | 237:f3da66175598 | 76 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 237:f3da66175598 | 77 | * are permitted provided that the following conditions are met: |
| mbed_official | 237:f3da66175598 | 78 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 237:f3da66175598 | 79 | * this list of conditions and the following disclaimer. |
| mbed_official | 237:f3da66175598 | 80 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 237:f3da66175598 | 81 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 237:f3da66175598 | 82 | * and/or other materials provided with the distribution. |
| mbed_official | 237:f3da66175598 | 83 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 237:f3da66175598 | 84 | * may be used to endorse or promote products derived from this software |
| mbed_official | 237:f3da66175598 | 85 | * without specific prior written permission. |
| mbed_official | 237:f3da66175598 | 86 | * |
| mbed_official | 237:f3da66175598 | 87 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 237:f3da66175598 | 88 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 237:f3da66175598 | 89 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 237:f3da66175598 | 90 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 237:f3da66175598 | 91 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 237:f3da66175598 | 92 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 237:f3da66175598 | 93 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 237:f3da66175598 | 94 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 237:f3da66175598 | 95 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 237:f3da66175598 | 96 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 237:f3da66175598 | 97 | * |
| mbed_official | 237:f3da66175598 | 98 | ****************************************************************************** |
| mbed_official | 237:f3da66175598 | 99 | */ |
| mbed_official | 237:f3da66175598 | 100 | |
| mbed_official | 237:f3da66175598 | 101 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 237:f3da66175598 | 102 | #include "stm32f3xx_hal.h" |
| mbed_official | 237:f3da66175598 | 103 | |
| mbed_official | 237:f3da66175598 | 104 | /** @addtogroup STM32F3xx_HAL_Driver |
| mbed_official | 237:f3da66175598 | 105 | * @{ |
| mbed_official | 237:f3da66175598 | 106 | */ |
| mbed_official | 237:f3da66175598 | 107 | |
| mbed_official | 375:3d36234a1087 | 108 | /** @defgroup TIMEx TIM Extended HAL module driver |
| mbed_official | 237:f3da66175598 | 109 | * @brief TIM Extended HAL module driver |
| mbed_official | 237:f3da66175598 | 110 | * @{ |
| mbed_official | 237:f3da66175598 | 111 | */ |
| mbed_official | 237:f3da66175598 | 112 | |
| mbed_official | 237:f3da66175598 | 113 | #ifdef HAL_TIM_MODULE_ENABLED |
| mbed_official | 237:f3da66175598 | 114 | |
| mbed_official | 237:f3da66175598 | 115 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 237:f3da66175598 | 116 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 375:3d36234a1087 | 117 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 118 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 119 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 120 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 375:3d36234a1087 | 121 | |
| mbed_official | 237:f3da66175598 | 122 | #define BDTR_BKF_SHIFT (16) |
| mbed_official | 237:f3da66175598 | 123 | #define BDTR_BK2F_SHIFT (20) |
| mbed_official | 375:3d36234a1087 | 124 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 125 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 126 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 127 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 375:3d36234a1087 | 128 | |
| mbed_official | 237:f3da66175598 | 129 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 237:f3da66175598 | 130 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 237:f3da66175598 | 131 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 375:3d36234a1087 | 132 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 133 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 134 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 135 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 237:f3da66175598 | 136 | static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, |
| mbed_official | 237:f3da66175598 | 137 | TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 237:f3da66175598 | 138 | |
| mbed_official | 237:f3da66175598 | 139 | static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, |
| mbed_official | 237:f3da66175598 | 140 | TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 375:3d36234a1087 | 141 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 142 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 143 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 144 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 237:f3da66175598 | 145 | |
| mbed_official | 237:f3da66175598 | 146 | static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); |
| mbed_official | 237:f3da66175598 | 147 | |
| mbed_official | 237:f3da66175598 | 148 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 375:3d36234a1087 | 149 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 150 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 151 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 152 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 237:f3da66175598 | 153 | /** |
| mbed_official | 237:f3da66175598 | 154 | * @brief Timer Ouput Compare 5 configuration |
| mbed_official | 237:f3da66175598 | 155 | * @param TIMx to select the TIM peripheral |
| mbed_official | 237:f3da66175598 | 156 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 237:f3da66175598 | 157 | * @retval None |
| mbed_official | 237:f3da66175598 | 158 | */ |
| mbed_official | 237:f3da66175598 | 159 | static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, |
| mbed_official | 237:f3da66175598 | 160 | TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 237:f3da66175598 | 161 | { |
| mbed_official | 237:f3da66175598 | 162 | uint32_t tmpccmrx = 0; |
| mbed_official | 237:f3da66175598 | 163 | uint32_t tmpccer = 0; |
| mbed_official | 237:f3da66175598 | 164 | uint32_t tmpcr2 = 0; |
| mbed_official | 237:f3da66175598 | 165 | |
| mbed_official | 237:f3da66175598 | 166 | /* Disable the output: Reset the CCxE Bit */ |
| mbed_official | 237:f3da66175598 | 167 | TIMx->CCER &= ~TIM_CCER_CC5E; |
| mbed_official | 237:f3da66175598 | 168 | |
| mbed_official | 237:f3da66175598 | 169 | /* Get the TIMx CCER register value */ |
| mbed_official | 237:f3da66175598 | 170 | tmpccer = TIMx->CCER; |
| mbed_official | 237:f3da66175598 | 171 | /* Get the TIMx CR2 register value */ |
| mbed_official | 237:f3da66175598 | 172 | tmpcr2 = TIMx->CR2; |
| mbed_official | 237:f3da66175598 | 173 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 237:f3da66175598 | 174 | tmpccmrx = TIMx->CCMR3; |
| mbed_official | 237:f3da66175598 | 175 | |
| mbed_official | 237:f3da66175598 | 176 | /* Reset the Output Compare Mode Bits */ |
| mbed_official | 237:f3da66175598 | 177 | tmpccmrx &= ~(TIM_CCMR3_OC5M); |
| mbed_official | 237:f3da66175598 | 178 | /* Select the Output Compare Mode */ |
| mbed_official | 237:f3da66175598 | 179 | tmpccmrx |= OC_Config->OCMode; |
| mbed_official | 237:f3da66175598 | 180 | |
| mbed_official | 237:f3da66175598 | 181 | /* Reset the Output Polarity level */ |
| mbed_official | 237:f3da66175598 | 182 | tmpccer &= ~TIM_CCER_CC5P; |
| mbed_official | 237:f3da66175598 | 183 | /* Set the Output Compare Polarity */ |
| mbed_official | 237:f3da66175598 | 184 | tmpccer |= (OC_Config->OCPolarity << 16); |
| mbed_official | 237:f3da66175598 | 185 | |
| mbed_official | 237:f3da66175598 | 186 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| mbed_official | 237:f3da66175598 | 187 | { |
| mbed_official | 237:f3da66175598 | 188 | /* Reset the Output Compare IDLE State */ |
| mbed_official | 237:f3da66175598 | 189 | tmpcr2 &= ~TIM_CR2_OIS5; |
| mbed_official | 237:f3da66175598 | 190 | /* Set the Output Idle state */ |
| mbed_official | 237:f3da66175598 | 191 | tmpcr2 |= (OC_Config->OCIdleState << 8); |
| mbed_official | 237:f3da66175598 | 192 | } |
| mbed_official | 237:f3da66175598 | 193 | /* Write to TIMx CR2 */ |
| mbed_official | 237:f3da66175598 | 194 | TIMx->CR2 = tmpcr2; |
| mbed_official | 237:f3da66175598 | 195 | |
| mbed_official | 237:f3da66175598 | 196 | /* Write to TIMx CCMR3 */ |
| mbed_official | 237:f3da66175598 | 197 | TIMx->CCMR3 = tmpccmrx; |
| mbed_official | 237:f3da66175598 | 198 | |
| mbed_official | 237:f3da66175598 | 199 | /* Set the Capture Compare Register value */ |
| mbed_official | 237:f3da66175598 | 200 | TIMx->CCR5 = OC_Config->Pulse; |
| mbed_official | 237:f3da66175598 | 201 | |
| mbed_official | 237:f3da66175598 | 202 | /* Write to TIMx CCER */ |
| mbed_official | 237:f3da66175598 | 203 | TIMx->CCER = tmpccer; |
| mbed_official | 237:f3da66175598 | 204 | } |
| mbed_official | 237:f3da66175598 | 205 | |
| mbed_official | 237:f3da66175598 | 206 | /** |
| mbed_official | 237:f3da66175598 | 207 | * @brief Timer Ouput Compare 6 configuration |
| mbed_official | 237:f3da66175598 | 208 | * @param TIMx to select the TIM peripheral |
| mbed_official | 237:f3da66175598 | 209 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 237:f3da66175598 | 210 | * @retval None |
| mbed_official | 237:f3da66175598 | 211 | */ |
| mbed_official | 237:f3da66175598 | 212 | static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, |
| mbed_official | 237:f3da66175598 | 213 | TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 237:f3da66175598 | 214 | { |
| mbed_official | 237:f3da66175598 | 215 | uint32_t tmpccmrx = 0; |
| mbed_official | 237:f3da66175598 | 216 | uint32_t tmpccer = 0; |
| mbed_official | 237:f3da66175598 | 217 | uint32_t tmpcr2 = 0; |
| mbed_official | 237:f3da66175598 | 218 | |
| mbed_official | 237:f3da66175598 | 219 | /* Disable the output: Reset the CCxE Bit */ |
| mbed_official | 237:f3da66175598 | 220 | TIMx->CCER &= ~TIM_CCER_CC6E; |
| mbed_official | 237:f3da66175598 | 221 | |
| mbed_official | 237:f3da66175598 | 222 | /* Get the TIMx CCER register value */ |
| mbed_official | 237:f3da66175598 | 223 | tmpccer = TIMx->CCER; |
| mbed_official | 237:f3da66175598 | 224 | /* Get the TIMx CR2 register value */ |
| mbed_official | 237:f3da66175598 | 225 | tmpcr2 = TIMx->CR2; |
| mbed_official | 237:f3da66175598 | 226 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 237:f3da66175598 | 227 | tmpccmrx = TIMx->CCMR3; |
| mbed_official | 237:f3da66175598 | 228 | |
| mbed_official | 237:f3da66175598 | 229 | /* Reset the Output Compare Mode Bits */ |
| mbed_official | 237:f3da66175598 | 230 | tmpccmrx &= ~(TIM_CCMR3_OC6M); |
| mbed_official | 237:f3da66175598 | 231 | /* Select the Output Compare Mode */ |
| mbed_official | 237:f3da66175598 | 232 | tmpccmrx |= (OC_Config->OCMode << 8); |
| mbed_official | 237:f3da66175598 | 233 | |
| mbed_official | 237:f3da66175598 | 234 | /* Reset the Output Polarity level */ |
| mbed_official | 237:f3da66175598 | 235 | tmpccer &= (uint32_t)~TIM_CCER_CC6P; |
| mbed_official | 237:f3da66175598 | 236 | /* Set the Output Compare Polarity */ |
| mbed_official | 237:f3da66175598 | 237 | tmpccer |= (OC_Config->OCPolarity << 20); |
| mbed_official | 237:f3da66175598 | 238 | |
| mbed_official | 237:f3da66175598 | 239 | if(IS_TIM_BREAK_INSTANCE(TIMx)) |
| mbed_official | 237:f3da66175598 | 240 | { |
| mbed_official | 237:f3da66175598 | 241 | /* Reset the Output Compare IDLE State */ |
| mbed_official | 237:f3da66175598 | 242 | tmpcr2 &= ~TIM_CR2_OIS6; |
| mbed_official | 237:f3da66175598 | 243 | /* Set the Output Idle state */ |
| mbed_official | 237:f3da66175598 | 244 | tmpcr2 |= (OC_Config->OCIdleState << 10); |
| mbed_official | 237:f3da66175598 | 245 | } |
| mbed_official | 237:f3da66175598 | 246 | |
| mbed_official | 237:f3da66175598 | 247 | /* Write to TIMx CR2 */ |
| mbed_official | 237:f3da66175598 | 248 | TIMx->CR2 = tmpcr2; |
| mbed_official | 237:f3da66175598 | 249 | |
| mbed_official | 237:f3da66175598 | 250 | /* Write to TIMx CCMR3 */ |
| mbed_official | 237:f3da66175598 | 251 | TIMx->CCMR3 = tmpccmrx; |
| mbed_official | 237:f3da66175598 | 252 | |
| mbed_official | 237:f3da66175598 | 253 | /* Set the Capture Compare Register value */ |
| mbed_official | 237:f3da66175598 | 254 | TIMx->CCR6 = OC_Config->Pulse; |
| mbed_official | 237:f3da66175598 | 255 | |
| mbed_official | 237:f3da66175598 | 256 | /* Write to TIMx CCER */ |
| mbed_official | 237:f3da66175598 | 257 | TIMx->CCER = tmpccer; |
| mbed_official | 237:f3da66175598 | 258 | } |
| mbed_official | 375:3d36234a1087 | 259 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 260 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 261 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 262 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 237:f3da66175598 | 263 | |
| mbed_official | 375:3d36234a1087 | 264 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
| mbed_official | 237:f3da66175598 | 265 | * @{ |
| mbed_official | 237:f3da66175598 | 266 | */ |
| mbed_official | 237:f3da66175598 | 267 | |
| mbed_official | 375:3d36234a1087 | 268 | /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions |
| mbed_official | 237:f3da66175598 | 269 | * @brief Timer Hall Sensor functions |
| mbed_official | 237:f3da66175598 | 270 | * |
| mbed_official | 237:f3da66175598 | 271 | @verbatim |
| mbed_official | 237:f3da66175598 | 272 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 273 | ##### Timer Hall Sensor functions ##### |
| mbed_official | 237:f3da66175598 | 274 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 275 | [..] |
| mbed_official | 237:f3da66175598 | 276 | This section provides functions allowing to: |
| mbed_official | 237:f3da66175598 | 277 | (+) Initialize and configure TIM HAL Sensor. |
| mbed_official | 237:f3da66175598 | 278 | (+) De-initialize TIM HAL Sensor. |
| mbed_official | 237:f3da66175598 | 279 | (+) Start the Hall Sensor Interface. |
| mbed_official | 237:f3da66175598 | 280 | (+) Stop the Hall Sensor Interface. |
| mbed_official | 237:f3da66175598 | 281 | (+) Start the Hall Sensor Interface and enable interrupts. |
| mbed_official | 237:f3da66175598 | 282 | (+) Stop the Hall Sensor Interface and disable interrupts. |
| mbed_official | 237:f3da66175598 | 283 | (+) Start the Hall Sensor Interface and enable DMA transfers. |
| mbed_official | 237:f3da66175598 | 284 | (+) Stop the Hall Sensor Interface and disable DMA transfers. |
| mbed_official | 237:f3da66175598 | 285 | |
| mbed_official | 237:f3da66175598 | 286 | @endverbatim |
| mbed_official | 237:f3da66175598 | 287 | * @{ |
| mbed_official | 237:f3da66175598 | 288 | */ |
| mbed_official | 237:f3da66175598 | 289 | /** |
| mbed_official | 237:f3da66175598 | 290 | * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. |
| mbed_official | 237:f3da66175598 | 291 | * @param htim: TIM Encoder Interface handle |
| mbed_official | 237:f3da66175598 | 292 | * @param sConfig: TIM Hall Sensor configuration structure |
| mbed_official | 237:f3da66175598 | 293 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 294 | */ |
| mbed_official | 237:f3da66175598 | 295 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) |
| mbed_official | 237:f3da66175598 | 296 | { |
| mbed_official | 237:f3da66175598 | 297 | TIM_OC_InitTypeDef OC_Config; |
| mbed_official | 237:f3da66175598 | 298 | |
| mbed_official | 237:f3da66175598 | 299 | /* Check the TIM handle allocation */ |
| mbed_official | 632:7687fb9c4f91 | 300 | if(htim == NULL) |
| mbed_official | 237:f3da66175598 | 301 | { |
| mbed_official | 237:f3da66175598 | 302 | return HAL_ERROR; |
| mbed_official | 237:f3da66175598 | 303 | } |
| mbed_official | 237:f3da66175598 | 304 | |
| mbed_official | 237:f3da66175598 | 305 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 306 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 237:f3da66175598 | 307 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 237:f3da66175598 | 308 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); |
| mbed_official | 237:f3da66175598 | 309 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
| mbed_official | 237:f3da66175598 | 310 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
| mbed_official | 237:f3da66175598 | 311 | |
| mbed_official | 237:f3da66175598 | 312 | /* Set the TIM state */ |
| mbed_official | 237:f3da66175598 | 313 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 314 | |
| mbed_official | 237:f3da66175598 | 315 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 237:f3da66175598 | 316 | HAL_TIMEx_HallSensor_MspInit(htim); |
| mbed_official | 237:f3da66175598 | 317 | |
| mbed_official | 237:f3da66175598 | 318 | /* Configure the Time base in the Encoder Mode */ |
| mbed_official | 237:f3da66175598 | 319 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 237:f3da66175598 | 320 | |
| mbed_official | 237:f3da66175598 | 321 | /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ |
| mbed_official | 237:f3da66175598 | 322 | TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); |
| mbed_official | 237:f3da66175598 | 323 | |
| mbed_official | 237:f3da66175598 | 324 | /* Reset the IC1PSC Bits */ |
| mbed_official | 237:f3da66175598 | 325 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; |
| mbed_official | 237:f3da66175598 | 326 | /* Set the IC1PSC value */ |
| mbed_official | 237:f3da66175598 | 327 | htim->Instance->CCMR1 |= sConfig->IC1Prescaler; |
| mbed_official | 237:f3da66175598 | 328 | |
| mbed_official | 237:f3da66175598 | 329 | /* Enable the Hall sensor interface (XOR function of the three inputs) */ |
| mbed_official | 237:f3da66175598 | 330 | htim->Instance->CR2 |= TIM_CR2_TI1S; |
| mbed_official | 237:f3da66175598 | 331 | |
| mbed_official | 237:f3da66175598 | 332 | /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ |
| mbed_official | 237:f3da66175598 | 333 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 237:f3da66175598 | 334 | htim->Instance->SMCR |= TIM_TS_TI1F_ED; |
| mbed_official | 237:f3da66175598 | 335 | |
| mbed_official | 237:f3da66175598 | 336 | /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ |
| mbed_official | 237:f3da66175598 | 337 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 237:f3da66175598 | 338 | htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; |
| mbed_official | 237:f3da66175598 | 339 | |
| mbed_official | 237:f3da66175598 | 340 | /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ |
| mbed_official | 237:f3da66175598 | 341 | OC_Config.OCFastMode = TIM_OCFAST_DISABLE; |
| mbed_official | 237:f3da66175598 | 342 | OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; |
| mbed_official | 237:f3da66175598 | 343 | OC_Config.OCMode = TIM_OCMODE_PWM2; |
| mbed_official | 237:f3da66175598 | 344 | OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; |
| mbed_official | 237:f3da66175598 | 345 | OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; |
| mbed_official | 237:f3da66175598 | 346 | OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; |
| mbed_official | 237:f3da66175598 | 347 | OC_Config.Pulse = sConfig->Commutation_Delay; |
| mbed_official | 237:f3da66175598 | 348 | |
| mbed_official | 237:f3da66175598 | 349 | TIM_OC2_SetConfig(htim->Instance, &OC_Config); |
| mbed_official | 237:f3da66175598 | 350 | |
| mbed_official | 237:f3da66175598 | 351 | /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 |
| mbed_official | 237:f3da66175598 | 352 | register to 101 */ |
| mbed_official | 237:f3da66175598 | 353 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
| mbed_official | 237:f3da66175598 | 354 | htim->Instance->CR2 |= TIM_TRGO_OC2REF; |
| mbed_official | 237:f3da66175598 | 355 | |
| mbed_official | 237:f3da66175598 | 356 | /* Initialize the TIM state*/ |
| mbed_official | 237:f3da66175598 | 357 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 358 | |
| mbed_official | 237:f3da66175598 | 359 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 360 | } |
| mbed_official | 237:f3da66175598 | 361 | |
| mbed_official | 237:f3da66175598 | 362 | /** |
| mbed_official | 237:f3da66175598 | 363 | * @brief DeInitializes the TIM Hall Sensor interface |
| mbed_official | 237:f3da66175598 | 364 | * @param htim: TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 365 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 366 | */ |
| mbed_official | 237:f3da66175598 | 367 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 368 | { |
| mbed_official | 237:f3da66175598 | 369 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 370 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 371 | |
| mbed_official | 237:f3da66175598 | 372 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 373 | |
| mbed_official | 237:f3da66175598 | 374 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 237:f3da66175598 | 375 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 376 | |
| mbed_official | 237:f3da66175598 | 377 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 237:f3da66175598 | 378 | HAL_TIMEx_HallSensor_MspDeInit(htim); |
| mbed_official | 237:f3da66175598 | 379 | |
| mbed_official | 237:f3da66175598 | 380 | /* Change TIM state */ |
| mbed_official | 237:f3da66175598 | 381 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 237:f3da66175598 | 382 | |
| mbed_official | 237:f3da66175598 | 383 | /* Release Lock */ |
| mbed_official | 237:f3da66175598 | 384 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 385 | |
| mbed_official | 237:f3da66175598 | 386 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 387 | } |
| mbed_official | 237:f3da66175598 | 388 | |
| mbed_official | 237:f3da66175598 | 389 | /** |
| mbed_official | 237:f3da66175598 | 390 | * @brief Initializes the TIM Hall Sensor MSP. |
| mbed_official | 237:f3da66175598 | 391 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 392 | * @retval None |
| mbed_official | 237:f3da66175598 | 393 | */ |
| mbed_official | 237:f3da66175598 | 394 | __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 395 | { |
| mbed_official | 237:f3da66175598 | 396 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 237:f3da66175598 | 397 | the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file |
| mbed_official | 237:f3da66175598 | 398 | */ |
| mbed_official | 237:f3da66175598 | 399 | } |
| mbed_official | 237:f3da66175598 | 400 | |
| mbed_official | 237:f3da66175598 | 401 | /** |
| mbed_official | 237:f3da66175598 | 402 | * @brief DeInitializes TIM Hall Sensor MSP. |
| mbed_official | 237:f3da66175598 | 403 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 404 | * @retval None |
| mbed_official | 237:f3da66175598 | 405 | */ |
| mbed_official | 237:f3da66175598 | 406 | __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 407 | { |
| mbed_official | 237:f3da66175598 | 408 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 237:f3da66175598 | 409 | the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file |
| mbed_official | 237:f3da66175598 | 410 | */ |
| mbed_official | 237:f3da66175598 | 411 | } |
| mbed_official | 237:f3da66175598 | 412 | |
| mbed_official | 237:f3da66175598 | 413 | /** |
| mbed_official | 237:f3da66175598 | 414 | * @brief Starts the TIM Hall Sensor Interface. |
| mbed_official | 237:f3da66175598 | 415 | * @param htim : TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 416 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 417 | */ |
| mbed_official | 237:f3da66175598 | 418 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 419 | { |
| mbed_official | 237:f3da66175598 | 420 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 421 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 422 | |
| mbed_official | 237:f3da66175598 | 423 | /* Enable the Input Capture channels 1 |
| mbed_official | 237:f3da66175598 | 424 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 425 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 237:f3da66175598 | 426 | |
| mbed_official | 237:f3da66175598 | 427 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 428 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 429 | |
| mbed_official | 237:f3da66175598 | 430 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 431 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 432 | } |
| mbed_official | 237:f3da66175598 | 433 | |
| mbed_official | 237:f3da66175598 | 434 | /** |
| mbed_official | 237:f3da66175598 | 435 | * @brief Stops the TIM Hall sensor Interface. |
| mbed_official | 237:f3da66175598 | 436 | * @param htim : TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 437 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 438 | */ |
| mbed_official | 237:f3da66175598 | 439 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 440 | { |
| mbed_official | 237:f3da66175598 | 441 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 442 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 443 | |
| mbed_official | 237:f3da66175598 | 444 | /* Disable the Input Capture channels 1, 2 and 3 |
| mbed_official | 237:f3da66175598 | 445 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 446 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 237:f3da66175598 | 447 | |
| mbed_official | 237:f3da66175598 | 448 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 449 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 450 | |
| mbed_official | 237:f3da66175598 | 451 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 452 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 453 | } |
| mbed_official | 237:f3da66175598 | 454 | |
| mbed_official | 237:f3da66175598 | 455 | /** |
| mbed_official | 237:f3da66175598 | 456 | * @brief Starts the TIM Hall Sensor Interface in interrupt mode. |
| mbed_official | 237:f3da66175598 | 457 | * @param htim : TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 458 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 459 | */ |
| mbed_official | 237:f3da66175598 | 460 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 461 | { |
| mbed_official | 237:f3da66175598 | 462 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 463 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 464 | |
| mbed_official | 237:f3da66175598 | 465 | /* Enable the capture compare Interrupts 1 event */ |
| mbed_official | 237:f3da66175598 | 466 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 467 | |
| mbed_official | 237:f3da66175598 | 468 | /* Enable the Input Capture channels 1 |
| mbed_official | 237:f3da66175598 | 469 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 470 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 237:f3da66175598 | 471 | |
| mbed_official | 237:f3da66175598 | 472 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 473 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 474 | |
| mbed_official | 237:f3da66175598 | 475 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 476 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 477 | } |
| mbed_official | 237:f3da66175598 | 478 | |
| mbed_official | 237:f3da66175598 | 479 | /** |
| mbed_official | 237:f3da66175598 | 480 | * @brief Stops the TIM Hall Sensor Interface in interrupt mode. |
| mbed_official | 237:f3da66175598 | 481 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 482 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 483 | */ |
| mbed_official | 237:f3da66175598 | 484 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 485 | { |
| mbed_official | 237:f3da66175598 | 486 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 487 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 488 | |
| mbed_official | 237:f3da66175598 | 489 | /* Disable the Input Capture channels 1 |
| mbed_official | 237:f3da66175598 | 490 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 491 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 237:f3da66175598 | 492 | |
| mbed_official | 237:f3da66175598 | 493 | /* Disable the capture compare Interrupts event */ |
| mbed_official | 237:f3da66175598 | 494 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 495 | |
| mbed_official | 237:f3da66175598 | 496 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 497 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 498 | |
| mbed_official | 237:f3da66175598 | 499 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 500 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 501 | } |
| mbed_official | 237:f3da66175598 | 502 | |
| mbed_official | 237:f3da66175598 | 503 | /** |
| mbed_official | 237:f3da66175598 | 504 | * @brief Starts the TIM Hall Sensor Interface in DMA mode. |
| mbed_official | 237:f3da66175598 | 505 | * @param htim : TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 506 | * @param pData: The destination Buffer address. |
| mbed_official | 237:f3da66175598 | 507 | * @param Length: The length of data to be transferred from TIM peripheral to memory. |
| mbed_official | 237:f3da66175598 | 508 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 509 | */ |
| mbed_official | 237:f3da66175598 | 510 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
| mbed_official | 237:f3da66175598 | 511 | { |
| mbed_official | 237:f3da66175598 | 512 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 513 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 514 | |
| mbed_official | 237:f3da66175598 | 515 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 237:f3da66175598 | 516 | { |
| mbed_official | 237:f3da66175598 | 517 | return HAL_BUSY; |
| mbed_official | 237:f3da66175598 | 518 | } |
| mbed_official | 237:f3da66175598 | 519 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 237:f3da66175598 | 520 | { |
| mbed_official | 237:f3da66175598 | 521 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 237:f3da66175598 | 522 | { |
| mbed_official | 237:f3da66175598 | 523 | return HAL_ERROR; |
| mbed_official | 237:f3da66175598 | 524 | } |
| mbed_official | 237:f3da66175598 | 525 | else |
| mbed_official | 237:f3da66175598 | 526 | { |
| mbed_official | 237:f3da66175598 | 527 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 528 | } |
| mbed_official | 237:f3da66175598 | 529 | } |
| mbed_official | 237:f3da66175598 | 530 | /* Enable the Input Capture channels 1 |
| mbed_official | 237:f3da66175598 | 531 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 532 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 237:f3da66175598 | 533 | |
| mbed_official | 237:f3da66175598 | 534 | /* Set the DMA Input Capture 1 Callback */ |
| mbed_official | 237:f3da66175598 | 535 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; |
| mbed_official | 237:f3da66175598 | 536 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 537 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 538 | |
| mbed_official | 237:f3da66175598 | 539 | /* Enable the DMA channel for Capture 1*/ |
| mbed_official | 237:f3da66175598 | 540 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); |
| mbed_official | 237:f3da66175598 | 541 | |
| mbed_official | 237:f3da66175598 | 542 | /* Enable the capture compare 1 Interrupt */ |
| mbed_official | 237:f3da66175598 | 543 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 544 | |
| mbed_official | 237:f3da66175598 | 545 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 546 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 547 | |
| mbed_official | 237:f3da66175598 | 548 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 549 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 550 | } |
| mbed_official | 237:f3da66175598 | 551 | |
| mbed_official | 237:f3da66175598 | 552 | /** |
| mbed_official | 237:f3da66175598 | 553 | * @brief Stops the TIM Hall Sensor Interface in DMA mode. |
| mbed_official | 237:f3da66175598 | 554 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 555 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 556 | */ |
| mbed_official | 237:f3da66175598 | 557 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 558 | { |
| mbed_official | 237:f3da66175598 | 559 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 560 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 561 | |
| mbed_official | 237:f3da66175598 | 562 | /* Disable the Input Capture channels 1 |
| mbed_official | 237:f3da66175598 | 563 | (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
| mbed_official | 237:f3da66175598 | 564 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 237:f3da66175598 | 565 | |
| mbed_official | 237:f3da66175598 | 566 | |
| mbed_official | 237:f3da66175598 | 567 | /* Disable the capture compare Interrupts 1 event */ |
| mbed_official | 237:f3da66175598 | 568 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 569 | |
| mbed_official | 237:f3da66175598 | 570 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 571 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 572 | |
| mbed_official | 237:f3da66175598 | 573 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 574 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 575 | } |
| mbed_official | 237:f3da66175598 | 576 | |
| mbed_official | 237:f3da66175598 | 577 | /** |
| mbed_official | 237:f3da66175598 | 578 | * @} |
| mbed_official | 237:f3da66175598 | 579 | */ |
| mbed_official | 237:f3da66175598 | 580 | |
| mbed_official | 375:3d36234a1087 | 581 | /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions |
| mbed_official | 237:f3da66175598 | 582 | * @brief Timer Complementary Output Compare functions |
| mbed_official | 237:f3da66175598 | 583 | * |
| mbed_official | 237:f3da66175598 | 584 | @verbatim |
| mbed_official | 237:f3da66175598 | 585 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 586 | ##### Timer Complementary Output Compare functions ##### |
| mbed_official | 237:f3da66175598 | 587 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 588 | [..] |
| mbed_official | 237:f3da66175598 | 589 | This section provides functions allowing to: |
| mbed_official | 237:f3da66175598 | 590 | (+) Start the Complementary Output Compare/PWM. |
| mbed_official | 237:f3da66175598 | 591 | (+) Stop the Complementary Output Compare/PWM. |
| mbed_official | 237:f3da66175598 | 592 | (+) Start the Complementary Output Compare/PWM and enable interrupts. |
| mbed_official | 237:f3da66175598 | 593 | (+) Stop the Complementary Output Compare/PWM and disable interrupts. |
| mbed_official | 237:f3da66175598 | 594 | (+) Start the Complementary Output Compare/PWM and enable DMA transfers. |
| mbed_official | 237:f3da66175598 | 595 | (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. |
| mbed_official | 237:f3da66175598 | 596 | |
| mbed_official | 237:f3da66175598 | 597 | @endverbatim |
| mbed_official | 237:f3da66175598 | 598 | * @{ |
| mbed_official | 237:f3da66175598 | 599 | */ |
| mbed_official | 237:f3da66175598 | 600 | |
| mbed_official | 237:f3da66175598 | 601 | /** |
| mbed_official | 237:f3da66175598 | 602 | * @brief Starts the TIM Output Compare signal generation on the complementary |
| mbed_official | 237:f3da66175598 | 603 | * output. |
| mbed_official | 237:f3da66175598 | 604 | * @param htim : TIM Output Compare handle |
| mbed_official | 237:f3da66175598 | 605 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 606 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 607 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 608 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 609 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 610 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 611 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 612 | */ |
| mbed_official | 237:f3da66175598 | 613 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 614 | { |
| mbed_official | 237:f3da66175598 | 615 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 616 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 617 | |
| mbed_official | 237:f3da66175598 | 618 | /* Enable the Capture compare channel N */ |
| mbed_official | 237:f3da66175598 | 619 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 620 | |
| mbed_official | 237:f3da66175598 | 621 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 622 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 623 | |
| mbed_official | 237:f3da66175598 | 624 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 625 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 626 | |
| mbed_official | 237:f3da66175598 | 627 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 628 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 629 | } |
| mbed_official | 237:f3da66175598 | 630 | |
| mbed_official | 237:f3da66175598 | 631 | /** |
| mbed_official | 237:f3da66175598 | 632 | * @brief Stops the TIM Output Compare signal generation on the complementary |
| mbed_official | 237:f3da66175598 | 633 | * output. |
| mbed_official | 237:f3da66175598 | 634 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 635 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 636 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 637 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 638 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 639 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 640 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 641 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 642 | */ |
| mbed_official | 237:f3da66175598 | 643 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 644 | { |
| mbed_official | 237:f3da66175598 | 645 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 646 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 647 | |
| mbed_official | 237:f3da66175598 | 648 | /* Disable the Capture compare channel N */ |
| mbed_official | 237:f3da66175598 | 649 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 650 | |
| mbed_official | 237:f3da66175598 | 651 | /* Disable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 652 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 653 | |
| mbed_official | 237:f3da66175598 | 654 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 655 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 656 | |
| mbed_official | 237:f3da66175598 | 657 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 658 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 659 | } |
| mbed_official | 237:f3da66175598 | 660 | |
| mbed_official | 237:f3da66175598 | 661 | /** |
| mbed_official | 237:f3da66175598 | 662 | * @brief Starts the TIM Output Compare signal generation in interrupt mode |
| mbed_official | 237:f3da66175598 | 663 | * on the complementary output. |
| mbed_official | 237:f3da66175598 | 664 | * @param htim : TIM OC handle |
| mbed_official | 237:f3da66175598 | 665 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 666 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 667 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 668 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 669 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 670 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 671 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 672 | */ |
| mbed_official | 237:f3da66175598 | 673 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 674 | { |
| mbed_official | 237:f3da66175598 | 675 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 676 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 677 | |
| mbed_official | 237:f3da66175598 | 678 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 679 | { |
| mbed_official | 237:f3da66175598 | 680 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 681 | { |
| mbed_official | 237:f3da66175598 | 682 | /* Enable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 683 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 684 | } |
| mbed_official | 237:f3da66175598 | 685 | break; |
| mbed_official | 237:f3da66175598 | 686 | |
| mbed_official | 237:f3da66175598 | 687 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 688 | { |
| mbed_official | 237:f3da66175598 | 689 | /* Enable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 690 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 691 | } |
| mbed_official | 237:f3da66175598 | 692 | break; |
| mbed_official | 237:f3da66175598 | 693 | |
| mbed_official | 237:f3da66175598 | 694 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 695 | { |
| mbed_official | 237:f3da66175598 | 696 | /* Enable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 697 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 237:f3da66175598 | 698 | } |
| mbed_official | 237:f3da66175598 | 699 | break; |
| mbed_official | 237:f3da66175598 | 700 | |
| mbed_official | 237:f3da66175598 | 701 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 702 | { |
| mbed_official | 237:f3da66175598 | 703 | /* Enable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 704 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 237:f3da66175598 | 705 | } |
| mbed_official | 237:f3da66175598 | 706 | break; |
| mbed_official | 237:f3da66175598 | 707 | |
| mbed_official | 237:f3da66175598 | 708 | default: |
| mbed_official | 237:f3da66175598 | 709 | break; |
| mbed_official | 237:f3da66175598 | 710 | } |
| mbed_official | 237:f3da66175598 | 711 | |
| mbed_official | 375:3d36234a1087 | 712 | /* Enable the TIM Break interrupt */ |
| mbed_official | 375:3d36234a1087 | 713 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
| mbed_official | 375:3d36234a1087 | 714 | |
| mbed_official | 375:3d36234a1087 | 715 | /* Enable the Capture compare channel N */ |
| mbed_official | 375:3d36234a1087 | 716 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 375:3d36234a1087 | 717 | |
| mbed_official | 237:f3da66175598 | 718 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 719 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 720 | |
| mbed_official | 237:f3da66175598 | 721 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 722 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 723 | |
| mbed_official | 237:f3da66175598 | 724 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 725 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 726 | } |
| mbed_official | 237:f3da66175598 | 727 | |
| mbed_official | 237:f3da66175598 | 728 | /** |
| mbed_official | 237:f3da66175598 | 729 | * @brief Stops the TIM Output Compare signal generation in interrupt mode |
| mbed_official | 237:f3da66175598 | 730 | * on the complementary output. |
| mbed_official | 237:f3da66175598 | 731 | * @param htim : TIM Output Compare handle |
| mbed_official | 237:f3da66175598 | 732 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 733 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 734 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 735 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 736 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 737 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 738 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 739 | */ |
| mbed_official | 237:f3da66175598 | 740 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 741 | { |
| mbed_official | 375:3d36234a1087 | 742 | uint32_t tmpccer = 0; |
| mbed_official | 375:3d36234a1087 | 743 | |
| mbed_official | 237:f3da66175598 | 744 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 745 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 746 | |
| mbed_official | 237:f3da66175598 | 747 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 748 | { |
| mbed_official | 237:f3da66175598 | 749 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 750 | { |
| mbed_official | 237:f3da66175598 | 751 | /* Disable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 752 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 753 | } |
| mbed_official | 237:f3da66175598 | 754 | break; |
| mbed_official | 237:f3da66175598 | 755 | |
| mbed_official | 237:f3da66175598 | 756 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 757 | { |
| mbed_official | 237:f3da66175598 | 758 | /* Disable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 759 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 760 | } |
| mbed_official | 237:f3da66175598 | 761 | break; |
| mbed_official | 237:f3da66175598 | 762 | |
| mbed_official | 237:f3da66175598 | 763 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 764 | { |
| mbed_official | 237:f3da66175598 | 765 | /* Disable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 766 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 237:f3da66175598 | 767 | } |
| mbed_official | 237:f3da66175598 | 768 | break; |
| mbed_official | 237:f3da66175598 | 769 | |
| mbed_official | 237:f3da66175598 | 770 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 771 | { |
| mbed_official | 237:f3da66175598 | 772 | /* Disable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 773 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 237:f3da66175598 | 774 | } |
| mbed_official | 237:f3da66175598 | 775 | break; |
| mbed_official | 237:f3da66175598 | 776 | |
| mbed_official | 237:f3da66175598 | 777 | default: |
| mbed_official | 237:f3da66175598 | 778 | break; |
| mbed_official | 237:f3da66175598 | 779 | } |
| mbed_official | 237:f3da66175598 | 780 | |
| mbed_official | 375:3d36234a1087 | 781 | /* Disable the Capture compare channel N */ |
| mbed_official | 375:3d36234a1087 | 782 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 783 | |
| mbed_official | 375:3d36234a1087 | 784 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
| mbed_official | 375:3d36234a1087 | 785 | tmpccer = htim->Instance->CCER; |
| mbed_official | 375:3d36234a1087 | 786 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) |
| mbed_official | 375:3d36234a1087 | 787 | { |
| mbed_official | 375:3d36234a1087 | 788 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
| mbed_official | 375:3d36234a1087 | 789 | } |
| mbed_official | 375:3d36234a1087 | 790 | |
| mbed_official | 237:f3da66175598 | 791 | /* Disable the Main Ouput */ |
| mbed_official | 375:3d36234a1087 | 792 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 793 | |
| mbed_official | 237:f3da66175598 | 794 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 795 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 796 | |
| mbed_official | 237:f3da66175598 | 797 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 798 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 799 | } |
| mbed_official | 237:f3da66175598 | 800 | |
| mbed_official | 237:f3da66175598 | 801 | /** |
| mbed_official | 237:f3da66175598 | 802 | * @brief Starts the TIM Output Compare signal generation in DMA mode |
| mbed_official | 237:f3da66175598 | 803 | * on the complementary output. |
| mbed_official | 237:f3da66175598 | 804 | * @param htim : TIM Output Compare handle |
| mbed_official | 237:f3da66175598 | 805 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 806 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 807 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 808 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 809 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 810 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 811 | * @param pData: The source Buffer address. |
| mbed_official | 237:f3da66175598 | 812 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 237:f3da66175598 | 813 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 814 | */ |
| mbed_official | 237:f3da66175598 | 815 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 237:f3da66175598 | 816 | { |
| mbed_official | 237:f3da66175598 | 817 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 818 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 819 | |
| mbed_official | 237:f3da66175598 | 820 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 237:f3da66175598 | 821 | { |
| mbed_official | 237:f3da66175598 | 822 | return HAL_BUSY; |
| mbed_official | 237:f3da66175598 | 823 | } |
| mbed_official | 237:f3da66175598 | 824 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 237:f3da66175598 | 825 | { |
| mbed_official | 237:f3da66175598 | 826 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 237:f3da66175598 | 827 | { |
| mbed_official | 237:f3da66175598 | 828 | return HAL_ERROR; |
| mbed_official | 237:f3da66175598 | 829 | } |
| mbed_official | 237:f3da66175598 | 830 | else |
| mbed_official | 237:f3da66175598 | 831 | { |
| mbed_official | 237:f3da66175598 | 832 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 833 | } |
| mbed_official | 237:f3da66175598 | 834 | } |
| mbed_official | 237:f3da66175598 | 835 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 836 | { |
| mbed_official | 237:f3da66175598 | 837 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 838 | { |
| mbed_official | 237:f3da66175598 | 839 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 840 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 841 | |
| mbed_official | 237:f3da66175598 | 842 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 843 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 844 | |
| mbed_official | 237:f3da66175598 | 845 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 846 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 237:f3da66175598 | 847 | |
| mbed_official | 237:f3da66175598 | 848 | /* Enable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 849 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 850 | } |
| mbed_official | 237:f3da66175598 | 851 | break; |
| mbed_official | 237:f3da66175598 | 852 | |
| mbed_official | 237:f3da66175598 | 853 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 854 | { |
| mbed_official | 237:f3da66175598 | 855 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 856 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 857 | |
| mbed_official | 237:f3da66175598 | 858 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 859 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 860 | |
| mbed_official | 237:f3da66175598 | 861 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 862 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 237:f3da66175598 | 863 | |
| mbed_official | 237:f3da66175598 | 864 | /* Enable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 865 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 237:f3da66175598 | 866 | } |
| mbed_official | 237:f3da66175598 | 867 | break; |
| mbed_official | 237:f3da66175598 | 868 | |
| mbed_official | 237:f3da66175598 | 869 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 870 | { |
| mbed_official | 237:f3da66175598 | 871 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 872 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 873 | |
| mbed_official | 237:f3da66175598 | 874 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 875 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 876 | |
| mbed_official | 237:f3da66175598 | 877 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 878 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 237:f3da66175598 | 879 | |
| mbed_official | 237:f3da66175598 | 880 | /* Enable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 881 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 237:f3da66175598 | 882 | } |
| mbed_official | 237:f3da66175598 | 883 | break; |
| mbed_official | 237:f3da66175598 | 884 | |
| mbed_official | 237:f3da66175598 | 885 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 886 | { |
| mbed_official | 237:f3da66175598 | 887 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 888 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 889 | |
| mbed_official | 237:f3da66175598 | 890 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 891 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 892 | |
| mbed_official | 237:f3da66175598 | 893 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 894 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 237:f3da66175598 | 895 | |
| mbed_official | 237:f3da66175598 | 896 | /* Enable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 897 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 237:f3da66175598 | 898 | } |
| mbed_official | 237:f3da66175598 | 899 | break; |
| mbed_official | 237:f3da66175598 | 900 | |
| mbed_official | 237:f3da66175598 | 901 | default: |
| mbed_official | 237:f3da66175598 | 902 | break; |
| mbed_official | 237:f3da66175598 | 903 | } |
| mbed_official | 237:f3da66175598 | 904 | |
| mbed_official | 237:f3da66175598 | 905 | /* Enable the Capture compare channel N */ |
| mbed_official | 237:f3da66175598 | 906 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 907 | |
| mbed_official | 237:f3da66175598 | 908 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 909 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 910 | |
| mbed_official | 237:f3da66175598 | 911 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 912 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 913 | |
| mbed_official | 237:f3da66175598 | 914 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 915 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 916 | } |
| mbed_official | 237:f3da66175598 | 917 | |
| mbed_official | 237:f3da66175598 | 918 | /** |
| mbed_official | 237:f3da66175598 | 919 | * @brief Stops the TIM Output Compare signal generation in DMA mode |
| mbed_official | 237:f3da66175598 | 920 | * on the complementary output. |
| mbed_official | 237:f3da66175598 | 921 | * @param htim : TIM Output Compare handle |
| mbed_official | 237:f3da66175598 | 922 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 923 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 924 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 925 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 926 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 927 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 928 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 929 | */ |
| mbed_official | 237:f3da66175598 | 930 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 931 | { |
| mbed_official | 237:f3da66175598 | 932 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 933 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 934 | |
| mbed_official | 237:f3da66175598 | 935 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 936 | { |
| mbed_official | 237:f3da66175598 | 937 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 938 | { |
| mbed_official | 237:f3da66175598 | 939 | /* Disable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 940 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 941 | } |
| mbed_official | 237:f3da66175598 | 942 | break; |
| mbed_official | 237:f3da66175598 | 943 | |
| mbed_official | 237:f3da66175598 | 944 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 945 | { |
| mbed_official | 237:f3da66175598 | 946 | /* Disable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 947 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 237:f3da66175598 | 948 | } |
| mbed_official | 237:f3da66175598 | 949 | break; |
| mbed_official | 237:f3da66175598 | 950 | |
| mbed_official | 237:f3da66175598 | 951 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 952 | { |
| mbed_official | 237:f3da66175598 | 953 | /* Disable the TIM Output Compare DMA request */ |
| mbed_official | 237:f3da66175598 | 954 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 237:f3da66175598 | 955 | } |
| mbed_official | 237:f3da66175598 | 956 | break; |
| mbed_official | 237:f3da66175598 | 957 | |
| mbed_official | 237:f3da66175598 | 958 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 959 | { |
| mbed_official | 237:f3da66175598 | 960 | /* Disable the TIM Output Compare interrupt */ |
| mbed_official | 237:f3da66175598 | 961 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 237:f3da66175598 | 962 | } |
| mbed_official | 237:f3da66175598 | 963 | break; |
| mbed_official | 237:f3da66175598 | 964 | |
| mbed_official | 237:f3da66175598 | 965 | default: |
| mbed_official | 237:f3da66175598 | 966 | break; |
| mbed_official | 237:f3da66175598 | 967 | } |
| mbed_official | 237:f3da66175598 | 968 | |
| mbed_official | 237:f3da66175598 | 969 | /* Disable the Capture compare channel N */ |
| mbed_official | 237:f3da66175598 | 970 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 971 | |
| mbed_official | 237:f3da66175598 | 972 | /* Disable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 973 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 974 | |
| mbed_official | 237:f3da66175598 | 975 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 976 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 977 | |
| mbed_official | 237:f3da66175598 | 978 | /* Change the htim state */ |
| mbed_official | 237:f3da66175598 | 979 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 980 | |
| mbed_official | 237:f3da66175598 | 981 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 982 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 983 | } |
| mbed_official | 237:f3da66175598 | 984 | |
| mbed_official | 237:f3da66175598 | 985 | /** |
| mbed_official | 237:f3da66175598 | 986 | * @} |
| mbed_official | 237:f3da66175598 | 987 | */ |
| mbed_official | 237:f3da66175598 | 988 | |
| mbed_official | 375:3d36234a1087 | 989 | /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions |
| mbed_official | 237:f3da66175598 | 990 | * @brief Timer Complementary PWM functions |
| mbed_official | 237:f3da66175598 | 991 | * |
| mbed_official | 237:f3da66175598 | 992 | @verbatim |
| mbed_official | 237:f3da66175598 | 993 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 994 | ##### Timer Complementary PWM functions ##### |
| mbed_official | 237:f3da66175598 | 995 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 996 | [..] |
| mbed_official | 237:f3da66175598 | 997 | This section provides functions allowing to: |
| mbed_official | 237:f3da66175598 | 998 | (+) Start the Complementary PWM. |
| mbed_official | 237:f3da66175598 | 999 | (+) Stop the Complementary PWM. |
| mbed_official | 237:f3da66175598 | 1000 | (+) Start the Complementary PWM and enable interrupts. |
| mbed_official | 237:f3da66175598 | 1001 | (+) Stop the Complementary PWM and disable interrupts. |
| mbed_official | 237:f3da66175598 | 1002 | (+) Start the Complementary PWM and enable DMA transfers. |
| mbed_official | 237:f3da66175598 | 1003 | (+) Stop the Complementary PWM and disable DMA transfers. |
| mbed_official | 237:f3da66175598 | 1004 | (+) Start the Complementary Input Capture measurement. |
| mbed_official | 237:f3da66175598 | 1005 | (+) Stop the Complementary Input Capture. |
| mbed_official | 237:f3da66175598 | 1006 | (+) Start the Complementary Input Capture and enable interrupts. |
| mbed_official | 237:f3da66175598 | 1007 | (+) Stop the Complementary Input Capture and disable interrupts. |
| mbed_official | 237:f3da66175598 | 1008 | (+) Start the Complementary Input Capture and enable DMA transfers. |
| mbed_official | 237:f3da66175598 | 1009 | (+) Stop the Complementary Input Capture and disable DMA transfers. |
| mbed_official | 237:f3da66175598 | 1010 | (+) Start the Complementary One Pulse generation. |
| mbed_official | 237:f3da66175598 | 1011 | (+) Stop the Complementary One Pulse. |
| mbed_official | 237:f3da66175598 | 1012 | (+) Start the Complementary One Pulse and enable interrupts. |
| mbed_official | 237:f3da66175598 | 1013 | (+) Stop the Complementary One Pulse and disable interrupts. |
| mbed_official | 237:f3da66175598 | 1014 | |
| mbed_official | 237:f3da66175598 | 1015 | @endverbatim |
| mbed_official | 237:f3da66175598 | 1016 | * @{ |
| mbed_official | 237:f3da66175598 | 1017 | */ |
| mbed_official | 237:f3da66175598 | 1018 | |
| mbed_official | 237:f3da66175598 | 1019 | /** |
| mbed_official | 237:f3da66175598 | 1020 | * @brief Starts the PWM signal generation on the complementary output. |
| mbed_official | 237:f3da66175598 | 1021 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1022 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 1023 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1024 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1025 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1026 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1027 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1028 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1029 | */ |
| mbed_official | 237:f3da66175598 | 1030 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1031 | { |
| mbed_official | 237:f3da66175598 | 1032 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1033 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1034 | |
| mbed_official | 237:f3da66175598 | 1035 | /* Enable the complementary PWM output */ |
| mbed_official | 237:f3da66175598 | 1036 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 1037 | |
| mbed_official | 237:f3da66175598 | 1038 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1039 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1040 | |
| mbed_official | 237:f3da66175598 | 1041 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1042 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1043 | |
| mbed_official | 237:f3da66175598 | 1044 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1045 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1046 | } |
| mbed_official | 237:f3da66175598 | 1047 | |
| mbed_official | 237:f3da66175598 | 1048 | /** |
| mbed_official | 237:f3da66175598 | 1049 | * @brief Stops the PWM signal generation on the complementary output. |
| mbed_official | 237:f3da66175598 | 1050 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1051 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1052 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1053 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1054 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1055 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1056 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1057 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1058 | */ |
| mbed_official | 237:f3da66175598 | 1059 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1060 | { |
| mbed_official | 237:f3da66175598 | 1061 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1062 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1063 | |
| mbed_official | 237:f3da66175598 | 1064 | /* Disable the complementary PWM output */ |
| mbed_official | 237:f3da66175598 | 1065 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 1066 | |
| mbed_official | 237:f3da66175598 | 1067 | /* Disable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1068 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1069 | |
| mbed_official | 237:f3da66175598 | 1070 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1071 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1072 | |
| mbed_official | 237:f3da66175598 | 1073 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1074 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1075 | } |
| mbed_official | 237:f3da66175598 | 1076 | |
| mbed_official | 237:f3da66175598 | 1077 | /** |
| mbed_official | 237:f3da66175598 | 1078 | * @brief Starts the PWM signal generation in interrupt mode on the |
| mbed_official | 237:f3da66175598 | 1079 | * complementary output. |
| mbed_official | 237:f3da66175598 | 1080 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1081 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1082 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1083 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1084 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1085 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1086 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1087 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1088 | */ |
| mbed_official | 237:f3da66175598 | 1089 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1090 | { |
| mbed_official | 237:f3da66175598 | 1091 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1092 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1093 | |
| mbed_official | 237:f3da66175598 | 1094 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1095 | { |
| mbed_official | 237:f3da66175598 | 1096 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1097 | { |
| mbed_official | 237:f3da66175598 | 1098 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 237:f3da66175598 | 1099 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 1100 | } |
| mbed_official | 237:f3da66175598 | 1101 | break; |
| mbed_official | 237:f3da66175598 | 1102 | |
| mbed_official | 237:f3da66175598 | 1103 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1104 | { |
| mbed_official | 237:f3da66175598 | 1105 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 237:f3da66175598 | 1106 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 1107 | } |
| mbed_official | 237:f3da66175598 | 1108 | break; |
| mbed_official | 237:f3da66175598 | 1109 | |
| mbed_official | 237:f3da66175598 | 1110 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1111 | { |
| mbed_official | 237:f3da66175598 | 1112 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 237:f3da66175598 | 1113 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 237:f3da66175598 | 1114 | } |
| mbed_official | 237:f3da66175598 | 1115 | break; |
| mbed_official | 237:f3da66175598 | 1116 | |
| mbed_official | 237:f3da66175598 | 1117 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1118 | { |
| mbed_official | 237:f3da66175598 | 1119 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 237:f3da66175598 | 1120 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 237:f3da66175598 | 1121 | } |
| mbed_official | 237:f3da66175598 | 1122 | break; |
| mbed_official | 237:f3da66175598 | 1123 | |
| mbed_official | 237:f3da66175598 | 1124 | default: |
| mbed_official | 237:f3da66175598 | 1125 | break; |
| mbed_official | 237:f3da66175598 | 1126 | } |
| mbed_official | 237:f3da66175598 | 1127 | |
| mbed_official | 237:f3da66175598 | 1128 | /* Enable the TIM Break interrupt */ |
| mbed_official | 237:f3da66175598 | 1129 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
| mbed_official | 237:f3da66175598 | 1130 | |
| mbed_official | 237:f3da66175598 | 1131 | /* Enable the complementary PWM output */ |
| mbed_official | 237:f3da66175598 | 1132 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 1133 | |
| mbed_official | 237:f3da66175598 | 1134 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1135 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1136 | |
| mbed_official | 237:f3da66175598 | 1137 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1138 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1139 | |
| mbed_official | 237:f3da66175598 | 1140 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1141 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1142 | } |
| mbed_official | 237:f3da66175598 | 1143 | |
| mbed_official | 237:f3da66175598 | 1144 | /** |
| mbed_official | 237:f3da66175598 | 1145 | * @brief Stops the PWM signal generation in interrupt mode on the |
| mbed_official | 237:f3da66175598 | 1146 | * complementary output. |
| mbed_official | 237:f3da66175598 | 1147 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1148 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1149 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1150 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1151 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1152 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1153 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1154 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1155 | */ |
| mbed_official | 237:f3da66175598 | 1156 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1157 | { |
| mbed_official | 375:3d36234a1087 | 1158 | uint32_t tmpccer = 0; |
| mbed_official | 375:3d36234a1087 | 1159 | |
| mbed_official | 237:f3da66175598 | 1160 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1161 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1162 | |
| mbed_official | 237:f3da66175598 | 1163 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1164 | { |
| mbed_official | 237:f3da66175598 | 1165 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1166 | { |
| mbed_official | 237:f3da66175598 | 1167 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 237:f3da66175598 | 1168 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 1169 | } |
| mbed_official | 237:f3da66175598 | 1170 | break; |
| mbed_official | 237:f3da66175598 | 1171 | |
| mbed_official | 237:f3da66175598 | 1172 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1173 | { |
| mbed_official | 237:f3da66175598 | 1174 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 237:f3da66175598 | 1175 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 1176 | } |
| mbed_official | 237:f3da66175598 | 1177 | break; |
| mbed_official | 237:f3da66175598 | 1178 | |
| mbed_official | 237:f3da66175598 | 1179 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1180 | { |
| mbed_official | 237:f3da66175598 | 1181 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 237:f3da66175598 | 1182 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 237:f3da66175598 | 1183 | } |
| mbed_official | 237:f3da66175598 | 1184 | break; |
| mbed_official | 237:f3da66175598 | 1185 | |
| mbed_official | 237:f3da66175598 | 1186 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1187 | { |
| mbed_official | 237:f3da66175598 | 1188 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 237:f3da66175598 | 1189 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 237:f3da66175598 | 1190 | } |
| mbed_official | 237:f3da66175598 | 1191 | break; |
| mbed_official | 237:f3da66175598 | 1192 | |
| mbed_official | 237:f3da66175598 | 1193 | default: |
| mbed_official | 237:f3da66175598 | 1194 | break; |
| mbed_official | 237:f3da66175598 | 1195 | } |
| mbed_official | 237:f3da66175598 | 1196 | |
| mbed_official | 237:f3da66175598 | 1197 | /* Disable the complementary PWM output */ |
| mbed_official | 237:f3da66175598 | 1198 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 1199 | |
| mbed_official | 375:3d36234a1087 | 1200 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
| mbed_official | 375:3d36234a1087 | 1201 | tmpccer = htim->Instance->CCER; |
| mbed_official | 375:3d36234a1087 | 1202 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) |
| mbed_official | 375:3d36234a1087 | 1203 | { |
| mbed_official | 375:3d36234a1087 | 1204 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
| mbed_official | 375:3d36234a1087 | 1205 | } |
| mbed_official | 375:3d36234a1087 | 1206 | |
| mbed_official | 237:f3da66175598 | 1207 | /* Disable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1208 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1209 | |
| mbed_official | 237:f3da66175598 | 1210 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1211 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1212 | |
| mbed_official | 237:f3da66175598 | 1213 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1214 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1215 | } |
| mbed_official | 237:f3da66175598 | 1216 | |
| mbed_official | 237:f3da66175598 | 1217 | /** |
| mbed_official | 237:f3da66175598 | 1218 | * @brief Starts the TIM PWM signal generation in DMA mode on the |
| mbed_official | 237:f3da66175598 | 1219 | * complementary output |
| mbed_official | 237:f3da66175598 | 1220 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1221 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 1222 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1223 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1224 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1225 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1226 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1227 | * @param pData: The source Buffer address. |
| mbed_official | 237:f3da66175598 | 1228 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 237:f3da66175598 | 1229 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1230 | */ |
| mbed_official | 237:f3da66175598 | 1231 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 237:f3da66175598 | 1232 | { |
| mbed_official | 237:f3da66175598 | 1233 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1234 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1235 | |
| mbed_official | 237:f3da66175598 | 1236 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 237:f3da66175598 | 1237 | { |
| mbed_official | 237:f3da66175598 | 1238 | return HAL_BUSY; |
| mbed_official | 237:f3da66175598 | 1239 | } |
| mbed_official | 237:f3da66175598 | 1240 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 237:f3da66175598 | 1241 | { |
| mbed_official | 237:f3da66175598 | 1242 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 237:f3da66175598 | 1243 | { |
| mbed_official | 237:f3da66175598 | 1244 | return HAL_ERROR; |
| mbed_official | 237:f3da66175598 | 1245 | } |
| mbed_official | 237:f3da66175598 | 1246 | else |
| mbed_official | 237:f3da66175598 | 1247 | { |
| mbed_official | 237:f3da66175598 | 1248 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 1249 | } |
| mbed_official | 237:f3da66175598 | 1250 | } |
| mbed_official | 237:f3da66175598 | 1251 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1252 | { |
| mbed_official | 237:f3da66175598 | 1253 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1254 | { |
| mbed_official | 237:f3da66175598 | 1255 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 1256 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 1257 | |
| mbed_official | 237:f3da66175598 | 1258 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 1259 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 1260 | |
| mbed_official | 237:f3da66175598 | 1261 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 1262 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 237:f3da66175598 | 1263 | |
| mbed_official | 237:f3da66175598 | 1264 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 237:f3da66175598 | 1265 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 1266 | } |
| mbed_official | 237:f3da66175598 | 1267 | break; |
| mbed_official | 237:f3da66175598 | 1268 | |
| mbed_official | 237:f3da66175598 | 1269 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1270 | { |
| mbed_official | 237:f3da66175598 | 1271 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 1272 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 1273 | |
| mbed_official | 237:f3da66175598 | 1274 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 1275 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 1276 | |
| mbed_official | 237:f3da66175598 | 1277 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 1278 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 237:f3da66175598 | 1279 | |
| mbed_official | 237:f3da66175598 | 1280 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 237:f3da66175598 | 1281 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 237:f3da66175598 | 1282 | } |
| mbed_official | 237:f3da66175598 | 1283 | break; |
| mbed_official | 237:f3da66175598 | 1284 | |
| mbed_official | 237:f3da66175598 | 1285 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1286 | { |
| mbed_official | 237:f3da66175598 | 1287 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 1288 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 1289 | |
| mbed_official | 237:f3da66175598 | 1290 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 1291 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 1292 | |
| mbed_official | 237:f3da66175598 | 1293 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 1294 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 237:f3da66175598 | 1295 | |
| mbed_official | 237:f3da66175598 | 1296 | /* Enable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 237:f3da66175598 | 1297 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 237:f3da66175598 | 1298 | } |
| mbed_official | 237:f3da66175598 | 1299 | break; |
| mbed_official | 237:f3da66175598 | 1300 | |
| mbed_official | 237:f3da66175598 | 1301 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1302 | { |
| mbed_official | 237:f3da66175598 | 1303 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 237:f3da66175598 | 1304 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; |
| mbed_official | 237:f3da66175598 | 1305 | |
| mbed_official | 237:f3da66175598 | 1306 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 1307 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; |
| mbed_official | 237:f3da66175598 | 1308 | |
| mbed_official | 237:f3da66175598 | 1309 | /* Enable the DMA channel */ |
| mbed_official | 237:f3da66175598 | 1310 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 237:f3da66175598 | 1311 | |
| mbed_official | 237:f3da66175598 | 1312 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 237:f3da66175598 | 1313 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 237:f3da66175598 | 1314 | } |
| mbed_official | 237:f3da66175598 | 1315 | break; |
| mbed_official | 237:f3da66175598 | 1316 | |
| mbed_official | 237:f3da66175598 | 1317 | default: |
| mbed_official | 237:f3da66175598 | 1318 | break; |
| mbed_official | 237:f3da66175598 | 1319 | } |
| mbed_official | 237:f3da66175598 | 1320 | |
| mbed_official | 237:f3da66175598 | 1321 | /* Enable the complementary PWM output */ |
| mbed_official | 375:3d36234a1087 | 1322 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 1323 | |
| mbed_official | 237:f3da66175598 | 1324 | /* Enable the Main Ouput */ |
| mbed_official | 375:3d36234a1087 | 1325 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1326 | |
| mbed_official | 237:f3da66175598 | 1327 | /* Enable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1328 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1329 | |
| mbed_official | 237:f3da66175598 | 1330 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1331 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1332 | } |
| mbed_official | 237:f3da66175598 | 1333 | |
| mbed_official | 237:f3da66175598 | 1334 | /** |
| mbed_official | 237:f3da66175598 | 1335 | * @brief Stops the TIM PWM signal generation in DMA mode on the complementary |
| mbed_official | 237:f3da66175598 | 1336 | * output |
| mbed_official | 237:f3da66175598 | 1337 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 1338 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1339 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1340 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1341 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1342 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1343 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1344 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1345 | */ |
| mbed_official | 237:f3da66175598 | 1346 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1347 | { |
| mbed_official | 237:f3da66175598 | 1348 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1349 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 237:f3da66175598 | 1350 | |
| mbed_official | 237:f3da66175598 | 1351 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1352 | { |
| mbed_official | 237:f3da66175598 | 1353 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1354 | { |
| mbed_official | 237:f3da66175598 | 1355 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 237:f3da66175598 | 1356 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 237:f3da66175598 | 1357 | } |
| mbed_official | 237:f3da66175598 | 1358 | break; |
| mbed_official | 237:f3da66175598 | 1359 | |
| mbed_official | 237:f3da66175598 | 1360 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1361 | { |
| mbed_official | 237:f3da66175598 | 1362 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 237:f3da66175598 | 1363 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 237:f3da66175598 | 1364 | } |
| mbed_official | 237:f3da66175598 | 1365 | break; |
| mbed_official | 237:f3da66175598 | 1366 | |
| mbed_official | 237:f3da66175598 | 1367 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1368 | { |
| mbed_official | 237:f3da66175598 | 1369 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 237:f3da66175598 | 1370 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 237:f3da66175598 | 1371 | } |
| mbed_official | 237:f3da66175598 | 1372 | break; |
| mbed_official | 237:f3da66175598 | 1373 | |
| mbed_official | 237:f3da66175598 | 1374 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1375 | { |
| mbed_official | 237:f3da66175598 | 1376 | /* Disable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 237:f3da66175598 | 1377 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 237:f3da66175598 | 1378 | } |
| mbed_official | 237:f3da66175598 | 1379 | break; |
| mbed_official | 237:f3da66175598 | 1380 | |
| mbed_official | 237:f3da66175598 | 1381 | default: |
| mbed_official | 237:f3da66175598 | 1382 | break; |
| mbed_official | 237:f3da66175598 | 1383 | } |
| mbed_official | 237:f3da66175598 | 1384 | |
| mbed_official | 237:f3da66175598 | 1385 | /* Disable the complementary PWM output */ |
| mbed_official | 375:3d36234a1087 | 1386 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 1387 | |
| mbed_official | 237:f3da66175598 | 1388 | /* Disable the Main Ouput */ |
| mbed_official | 375:3d36234a1087 | 1389 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1390 | |
| mbed_official | 237:f3da66175598 | 1391 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1392 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1393 | |
| mbed_official | 237:f3da66175598 | 1394 | /* Change the htim state */ |
| mbed_official | 237:f3da66175598 | 1395 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 1396 | |
| mbed_official | 237:f3da66175598 | 1397 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1398 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1399 | } |
| mbed_official | 237:f3da66175598 | 1400 | |
| mbed_official | 237:f3da66175598 | 1401 | /** |
| mbed_official | 237:f3da66175598 | 1402 | * @} |
| mbed_official | 237:f3da66175598 | 1403 | */ |
| mbed_official | 237:f3da66175598 | 1404 | |
| mbed_official | 375:3d36234a1087 | 1405 | /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions |
| mbed_official | 237:f3da66175598 | 1406 | * @brief Timer Complementary One Pulse functions |
| mbed_official | 237:f3da66175598 | 1407 | * |
| mbed_official | 237:f3da66175598 | 1408 | @verbatim |
| mbed_official | 237:f3da66175598 | 1409 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 1410 | ##### Timer Complementary One Pulse functions ##### |
| mbed_official | 237:f3da66175598 | 1411 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 1412 | [..] |
| mbed_official | 237:f3da66175598 | 1413 | This section provides functions allowing to: |
| mbed_official | 237:f3da66175598 | 1414 | (+) Start the Complementary One Pulse generation. |
| mbed_official | 237:f3da66175598 | 1415 | (+) Stop the Complementary One Pulse. |
| mbed_official | 237:f3da66175598 | 1416 | (+) Start the Complementary One Pulse and enable interrupts. |
| mbed_official | 237:f3da66175598 | 1417 | (+) Stop the Complementary One Pulse and disable interrupts. |
| mbed_official | 237:f3da66175598 | 1418 | |
| mbed_official | 237:f3da66175598 | 1419 | @endverbatim |
| mbed_official | 237:f3da66175598 | 1420 | * @{ |
| mbed_official | 237:f3da66175598 | 1421 | */ |
| mbed_official | 237:f3da66175598 | 1422 | |
| mbed_official | 237:f3da66175598 | 1423 | /** |
| mbed_official | 237:f3da66175598 | 1424 | * @brief Starts the TIM One Pulse signal generation on the complemetary |
| mbed_official | 237:f3da66175598 | 1425 | * output. |
| mbed_official | 237:f3da66175598 | 1426 | * @param htim : TIM One Pulse handle |
| mbed_official | 237:f3da66175598 | 1427 | * @param OutputChannel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 1428 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1429 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1430 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1431 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1432 | */ |
| mbed_official | 237:f3da66175598 | 1433 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 237:f3da66175598 | 1434 | { |
| mbed_official | 237:f3da66175598 | 1435 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1436 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
| mbed_official | 237:f3da66175598 | 1437 | |
| mbed_official | 237:f3da66175598 | 1438 | /* Enable the complementary One Pulse output */ |
| mbed_official | 237:f3da66175598 | 1439 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 1440 | |
| mbed_official | 237:f3da66175598 | 1441 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1442 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1443 | |
| mbed_official | 237:f3da66175598 | 1444 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1445 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1446 | } |
| mbed_official | 237:f3da66175598 | 1447 | |
| mbed_official | 237:f3da66175598 | 1448 | /** |
| mbed_official | 237:f3da66175598 | 1449 | * @brief Stops the TIM One Pulse signal generation on the complementary |
| mbed_official | 237:f3da66175598 | 1450 | * output. |
| mbed_official | 237:f3da66175598 | 1451 | * @param htim : TIM One Pulse handle |
| mbed_official | 237:f3da66175598 | 1452 | * @param OutputChannel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1453 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1454 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1455 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1456 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1457 | */ |
| mbed_official | 237:f3da66175598 | 1458 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 237:f3da66175598 | 1459 | { |
| mbed_official | 237:f3da66175598 | 1460 | |
| mbed_official | 237:f3da66175598 | 1461 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1462 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
| mbed_official | 237:f3da66175598 | 1463 | |
| mbed_official | 237:f3da66175598 | 1464 | /* Disable the complementary One Pulse output */ |
| mbed_official | 375:3d36234a1087 | 1465 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 1466 | |
| mbed_official | 237:f3da66175598 | 1467 | /* Disable the Main Ouput */ |
| mbed_official | 375:3d36234a1087 | 1468 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1469 | |
| mbed_official | 237:f3da66175598 | 1470 | /* Disable the Peripheral */ |
| mbed_official | 237:f3da66175598 | 1471 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1472 | |
| mbed_official | 237:f3da66175598 | 1473 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1474 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1475 | } |
| mbed_official | 237:f3da66175598 | 1476 | |
| mbed_official | 237:f3da66175598 | 1477 | /** |
| mbed_official | 237:f3da66175598 | 1478 | * @brief Starts the TIM One Pulse signal generation in interrupt mode on the |
| mbed_official | 237:f3da66175598 | 1479 | * complementary channel. |
| mbed_official | 237:f3da66175598 | 1480 | * @param htim : TIM One Pulse handle |
| mbed_official | 237:f3da66175598 | 1481 | * @param OutputChannel : TIM Channel to be enabled |
| mbed_official | 237:f3da66175598 | 1482 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1483 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1484 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1485 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1486 | */ |
| mbed_official | 237:f3da66175598 | 1487 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 237:f3da66175598 | 1488 | { |
| mbed_official | 237:f3da66175598 | 1489 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1490 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
| mbed_official | 237:f3da66175598 | 1491 | |
| mbed_official | 237:f3da66175598 | 1492 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 237:f3da66175598 | 1493 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 1494 | |
| mbed_official | 237:f3da66175598 | 1495 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 237:f3da66175598 | 1496 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 1497 | |
| mbed_official | 237:f3da66175598 | 1498 | /* Enable the complementary One Pulse output */ |
| mbed_official | 237:f3da66175598 | 1499 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
| mbed_official | 237:f3da66175598 | 1500 | |
| mbed_official | 237:f3da66175598 | 1501 | /* Enable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1502 | __HAL_TIM_MOE_ENABLE(htim); |
| mbed_official | 237:f3da66175598 | 1503 | |
| mbed_official | 237:f3da66175598 | 1504 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1505 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1506 | } |
| mbed_official | 237:f3da66175598 | 1507 | |
| mbed_official | 237:f3da66175598 | 1508 | /** |
| mbed_official | 237:f3da66175598 | 1509 | * @brief Stops the TIM One Pulse signal generation in interrupt mode on the |
| mbed_official | 237:f3da66175598 | 1510 | * complementary channel. |
| mbed_official | 237:f3da66175598 | 1511 | * @param htim : TIM One Pulse handle |
| mbed_official | 237:f3da66175598 | 1512 | * @param OutputChannel : TIM Channel to be disabled |
| mbed_official | 237:f3da66175598 | 1513 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1514 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1515 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1516 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1517 | */ |
| mbed_official | 237:f3da66175598 | 1518 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 237:f3da66175598 | 1519 | { |
| mbed_official | 237:f3da66175598 | 1520 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1521 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
| mbed_official | 237:f3da66175598 | 1522 | |
| mbed_official | 237:f3da66175598 | 1523 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 237:f3da66175598 | 1524 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 237:f3da66175598 | 1525 | |
| mbed_official | 237:f3da66175598 | 1526 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 237:f3da66175598 | 1527 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 237:f3da66175598 | 1528 | |
| mbed_official | 237:f3da66175598 | 1529 | /* Disable the complementary One Pulse output */ |
| mbed_official | 237:f3da66175598 | 1530 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
| mbed_official | 237:f3da66175598 | 1531 | |
| mbed_official | 237:f3da66175598 | 1532 | /* Disable the Main Ouput */ |
| mbed_official | 237:f3da66175598 | 1533 | __HAL_TIM_MOE_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1534 | |
| mbed_official | 237:f3da66175598 | 1535 | /* Disable the Peripheral */ |
| mbed_official | 375:3d36234a1087 | 1536 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 237:f3da66175598 | 1537 | |
| mbed_official | 237:f3da66175598 | 1538 | /* Return function status */ |
| mbed_official | 237:f3da66175598 | 1539 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1540 | } |
| mbed_official | 237:f3da66175598 | 1541 | |
| mbed_official | 237:f3da66175598 | 1542 | |
| mbed_official | 237:f3da66175598 | 1543 | |
| mbed_official | 237:f3da66175598 | 1544 | /** |
| mbed_official | 237:f3da66175598 | 1545 | * @} |
| mbed_official | 237:f3da66175598 | 1546 | */ |
| mbed_official | 375:3d36234a1087 | 1547 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
| mbed_official | 237:f3da66175598 | 1548 | * @brief Peripheral Control functions |
| mbed_official | 237:f3da66175598 | 1549 | * |
| mbed_official | 237:f3da66175598 | 1550 | @verbatim |
| mbed_official | 237:f3da66175598 | 1551 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 1552 | ##### Peripheral Control functions ##### |
| mbed_official | 237:f3da66175598 | 1553 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 1554 | [..] |
| mbed_official | 237:f3da66175598 | 1555 | This section provides functions allowing to: |
| mbed_official | 237:f3da66175598 | 1556 | (+) Configure the commutation event in case of use of the Hall sensor interface. |
| mbed_official | 237:f3da66175598 | 1557 | (+) Configure Output channels for OC and PWM mode. |
| mbed_official | 237:f3da66175598 | 1558 | |
| mbed_official | 237:f3da66175598 | 1559 | (+) Configure Complementary channels, break features and dead time. |
| mbed_official | 237:f3da66175598 | 1560 | (+) Configure Master synchronization. |
| mbed_official | 237:f3da66175598 | 1561 | (+) Configure timer remapping capabilities. |
| mbed_official | 237:f3da66175598 | 1562 | (+) Enable or disable channel grouping |
| mbed_official | 237:f3da66175598 | 1563 | |
| mbed_official | 237:f3da66175598 | 1564 | @endverbatim |
| mbed_official | 237:f3da66175598 | 1565 | * @{ |
| mbed_official | 237:f3da66175598 | 1566 | */ |
| mbed_official | 375:3d36234a1087 | 1567 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 1568 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 1569 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 1570 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 237:f3da66175598 | 1571 | /** |
| mbed_official | 237:f3da66175598 | 1572 | * @brief Configure the TIM commutation event sequence. |
| mbed_official | 237:f3da66175598 | 1573 | * @note: this function is mandatory to use the commutation event in order to |
| mbed_official | 237:f3da66175598 | 1574 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
| mbed_official | 237:f3da66175598 | 1575 | * the typical use of this feature is with the use of another Timer(interface Timer) |
| mbed_official | 237:f3da66175598 | 1576 | * configured in Hall sensor interface, this interface Timer will generate the |
| mbed_official | 237:f3da66175598 | 1577 | * commutation at its TRGO output (connected to Timer used in this function) each time |
| mbed_official | 237:f3da66175598 | 1578 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
| mbed_official | 237:f3da66175598 | 1579 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 1580 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
| mbed_official | 237:f3da66175598 | 1581 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1582 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
| mbed_official | 237:f3da66175598 | 1583 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
| mbed_official | 237:f3da66175598 | 1584 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
| mbed_official | 237:f3da66175598 | 1585 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
| mbed_official | 237:f3da66175598 | 1586 | * @arg TIM_TS_NONE: No trigger is needed |
| mbed_official | 237:f3da66175598 | 1587 | * @param CommutationSource : the Commutation Event source |
| mbed_official | 237:f3da66175598 | 1588 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1589 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
| mbed_official | 237:f3da66175598 | 1590 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
| mbed_official | 237:f3da66175598 | 1591 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1592 | */ |
| mbed_official | 237:f3da66175598 | 1593 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| mbed_official | 237:f3da66175598 | 1594 | { |
| mbed_official | 237:f3da66175598 | 1595 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1596 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1597 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
| mbed_official | 237:f3da66175598 | 1598 | |
| mbed_official | 237:f3da66175598 | 1599 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 1600 | |
| mbed_official | 237:f3da66175598 | 1601 | if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || |
| mbed_official | 237:f3da66175598 | 1602 | (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) |
| mbed_official | 237:f3da66175598 | 1603 | { |
| mbed_official | 237:f3da66175598 | 1604 | /* Select the Input trigger */ |
| mbed_official | 237:f3da66175598 | 1605 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 237:f3da66175598 | 1606 | htim->Instance->SMCR |= InputTrigger; |
| mbed_official | 237:f3da66175598 | 1607 | } |
| mbed_official | 237:f3da66175598 | 1608 | |
| mbed_official | 237:f3da66175598 | 1609 | /* Select the Capture Compare preload feature */ |
| mbed_official | 237:f3da66175598 | 1610 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
| mbed_official | 237:f3da66175598 | 1611 | /* Select the Commutation event source */ |
| mbed_official | 237:f3da66175598 | 1612 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
| mbed_official | 237:f3da66175598 | 1613 | htim->Instance->CR2 |= CommutationSource; |
| mbed_official | 237:f3da66175598 | 1614 | |
| mbed_official | 237:f3da66175598 | 1615 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 1616 | |
| mbed_official | 237:f3da66175598 | 1617 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1618 | } |
| mbed_official | 237:f3da66175598 | 1619 | |
| mbed_official | 237:f3da66175598 | 1620 | /** |
| mbed_official | 237:f3da66175598 | 1621 | * @brief Configure the TIM commutation event sequence with interrupt. |
| mbed_official | 237:f3da66175598 | 1622 | * @note: this function is mandatory to use the commutation event in order to |
| mbed_official | 237:f3da66175598 | 1623 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
| mbed_official | 237:f3da66175598 | 1624 | * the typical use of this feature is with the use of another Timer(interface Timer) |
| mbed_official | 237:f3da66175598 | 1625 | * configured in Hall sensor interface, this interface Timer will generate the |
| mbed_official | 237:f3da66175598 | 1626 | * commutation at its TRGO output (connected to Timer used in this function) each time |
| mbed_official | 237:f3da66175598 | 1627 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
| mbed_official | 237:f3da66175598 | 1628 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 1629 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
| mbed_official | 237:f3da66175598 | 1630 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1631 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
| mbed_official | 237:f3da66175598 | 1632 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
| mbed_official | 237:f3da66175598 | 1633 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
| mbed_official | 237:f3da66175598 | 1634 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
| mbed_official | 237:f3da66175598 | 1635 | * @arg TIM_TS_NONE: No trigger is needed |
| mbed_official | 237:f3da66175598 | 1636 | * @param CommutationSource : the Commutation Event source |
| mbed_official | 237:f3da66175598 | 1637 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1638 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
| mbed_official | 237:f3da66175598 | 1639 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
| mbed_official | 237:f3da66175598 | 1640 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1641 | */ |
| mbed_official | 237:f3da66175598 | 1642 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| mbed_official | 237:f3da66175598 | 1643 | { |
| mbed_official | 237:f3da66175598 | 1644 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1645 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1646 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
| mbed_official | 237:f3da66175598 | 1647 | |
| mbed_official | 237:f3da66175598 | 1648 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 1649 | |
| mbed_official | 237:f3da66175598 | 1650 | if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || |
| mbed_official | 237:f3da66175598 | 1651 | (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) |
| mbed_official | 237:f3da66175598 | 1652 | { |
| mbed_official | 237:f3da66175598 | 1653 | /* Select the Input trigger */ |
| mbed_official | 237:f3da66175598 | 1654 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 237:f3da66175598 | 1655 | htim->Instance->SMCR |= InputTrigger; |
| mbed_official | 237:f3da66175598 | 1656 | } |
| mbed_official | 237:f3da66175598 | 1657 | |
| mbed_official | 237:f3da66175598 | 1658 | /* Select the Capture Compare preload feature */ |
| mbed_official | 237:f3da66175598 | 1659 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
| mbed_official | 237:f3da66175598 | 1660 | /* Select the Commutation event source */ |
| mbed_official | 237:f3da66175598 | 1661 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
| mbed_official | 237:f3da66175598 | 1662 | htim->Instance->CR2 |= CommutationSource; |
| mbed_official | 237:f3da66175598 | 1663 | |
| mbed_official | 237:f3da66175598 | 1664 | /* Enable the Commutation Interrupt Request */ |
| mbed_official | 237:f3da66175598 | 1665 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); |
| mbed_official | 237:f3da66175598 | 1666 | |
| mbed_official | 237:f3da66175598 | 1667 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 1668 | |
| mbed_official | 237:f3da66175598 | 1669 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1670 | } |
| mbed_official | 237:f3da66175598 | 1671 | |
| mbed_official | 237:f3da66175598 | 1672 | /** |
| mbed_official | 237:f3da66175598 | 1673 | * @brief Configure the TIM commutation event sequence with DMA. |
| mbed_official | 237:f3da66175598 | 1674 | * @note: this function is mandatory to use the commutation event in order to |
| mbed_official | 237:f3da66175598 | 1675 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
| mbed_official | 237:f3da66175598 | 1676 | * the typical use of this feature is with the use of another Timer(interface Timer) |
| mbed_official | 237:f3da66175598 | 1677 | * configured in Hall sensor interface, this interface Timer will generate the |
| mbed_official | 237:f3da66175598 | 1678 | * commutation at its TRGO output (connected to Timer used in this function) each time |
| mbed_official | 237:f3da66175598 | 1679 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
| mbed_official | 237:f3da66175598 | 1680 | * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set |
| mbed_official | 237:f3da66175598 | 1681 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 1682 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
| mbed_official | 237:f3da66175598 | 1683 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1684 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
| mbed_official | 237:f3da66175598 | 1685 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
| mbed_official | 237:f3da66175598 | 1686 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
| mbed_official | 237:f3da66175598 | 1687 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
| mbed_official | 237:f3da66175598 | 1688 | * @arg TIM_TS_NONE: No trigger is needed |
| mbed_official | 237:f3da66175598 | 1689 | * @param CommutationSource : the Commutation Event source |
| mbed_official | 237:f3da66175598 | 1690 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1691 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
| mbed_official | 237:f3da66175598 | 1692 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
| mbed_official | 237:f3da66175598 | 1693 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1694 | */ |
| mbed_official | 237:f3da66175598 | 1695 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| mbed_official | 237:f3da66175598 | 1696 | { |
| mbed_official | 237:f3da66175598 | 1697 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1698 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1699 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
| mbed_official | 237:f3da66175598 | 1700 | |
| mbed_official | 237:f3da66175598 | 1701 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 1702 | |
| mbed_official | 237:f3da66175598 | 1703 | if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || |
| mbed_official | 237:f3da66175598 | 1704 | (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) |
| mbed_official | 237:f3da66175598 | 1705 | { |
| mbed_official | 237:f3da66175598 | 1706 | /* Select the Input trigger */ |
| mbed_official | 237:f3da66175598 | 1707 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 237:f3da66175598 | 1708 | htim->Instance->SMCR |= InputTrigger; |
| mbed_official | 237:f3da66175598 | 1709 | } |
| mbed_official | 237:f3da66175598 | 1710 | |
| mbed_official | 237:f3da66175598 | 1711 | /* Select the Capture Compare preload feature */ |
| mbed_official | 237:f3da66175598 | 1712 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
| mbed_official | 237:f3da66175598 | 1713 | /* Select the Commutation event source */ |
| mbed_official | 237:f3da66175598 | 1714 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
| mbed_official | 237:f3da66175598 | 1715 | htim->Instance->CR2 |= CommutationSource; |
| mbed_official | 237:f3da66175598 | 1716 | |
| mbed_official | 237:f3da66175598 | 1717 | /* Enable the Commutation DMA Request */ |
| mbed_official | 237:f3da66175598 | 1718 | /* Set the DMA Commutation Callback */ |
| mbed_official | 237:f3da66175598 | 1719 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; |
| mbed_official | 237:f3da66175598 | 1720 | /* Set the DMA error callback */ |
| mbed_official | 237:f3da66175598 | 1721 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError; |
| mbed_official | 237:f3da66175598 | 1722 | |
| mbed_official | 237:f3da66175598 | 1723 | /* Enable the Commutation DMA Request */ |
| mbed_official | 237:f3da66175598 | 1724 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); |
| mbed_official | 237:f3da66175598 | 1725 | |
| mbed_official | 237:f3da66175598 | 1726 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 1727 | |
| mbed_official | 237:f3da66175598 | 1728 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1729 | } |
| mbed_official | 237:f3da66175598 | 1730 | |
| mbed_official | 237:f3da66175598 | 1731 | /** |
| mbed_official | 237:f3da66175598 | 1732 | * @brief Initializes the TIM Output Compare Channels according to the specified |
| mbed_official | 237:f3da66175598 | 1733 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 237:f3da66175598 | 1734 | * @param htim: TIM Output Compare handle |
| mbed_official | 237:f3da66175598 | 1735 | * @param sConfig: TIM Output Compare configuration structure |
| mbed_official | 237:f3da66175598 | 1736 | * @param Channel : TIM Channels to configure |
| mbed_official | 237:f3da66175598 | 1737 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1738 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1739 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1740 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1741 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1742 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| mbed_official | 237:f3da66175598 | 1743 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| mbed_official | 237:f3da66175598 | 1744 | * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected |
| mbed_official | 237:f3da66175598 | 1745 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1746 | */ |
| mbed_official | 237:f3da66175598 | 1747 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 1748 | TIM_OC_InitTypeDef* sConfig, |
| mbed_official | 237:f3da66175598 | 1749 | uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1750 | { |
| mbed_official | 237:f3da66175598 | 1751 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1752 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 237:f3da66175598 | 1753 | assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); |
| mbed_official | 237:f3da66175598 | 1754 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 237:f3da66175598 | 1755 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); |
| mbed_official | 237:f3da66175598 | 1756 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); |
| mbed_official | 237:f3da66175598 | 1757 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); |
| mbed_official | 237:f3da66175598 | 1758 | |
| mbed_official | 237:f3da66175598 | 1759 | /* Check input state */ |
| mbed_official | 237:f3da66175598 | 1760 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 1761 | |
| mbed_official | 237:f3da66175598 | 1762 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 1763 | |
| mbed_official | 237:f3da66175598 | 1764 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1765 | { |
| mbed_official | 237:f3da66175598 | 1766 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1767 | { |
| mbed_official | 237:f3da66175598 | 1768 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1769 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1770 | |
| mbed_official | 237:f3da66175598 | 1771 | /* Configure the TIM Channel 1 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1772 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1773 | } |
| mbed_official | 237:f3da66175598 | 1774 | break; |
| mbed_official | 237:f3da66175598 | 1775 | |
| mbed_official | 237:f3da66175598 | 1776 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1777 | { |
| mbed_official | 237:f3da66175598 | 1778 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1779 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1780 | |
| mbed_official | 237:f3da66175598 | 1781 | /* Configure the TIM Channel 2 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1782 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1783 | } |
| mbed_official | 237:f3da66175598 | 1784 | break; |
| mbed_official | 237:f3da66175598 | 1785 | |
| mbed_official | 237:f3da66175598 | 1786 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1787 | { |
| mbed_official | 237:f3da66175598 | 1788 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1789 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1790 | |
| mbed_official | 237:f3da66175598 | 1791 | /* Configure the TIM Channel 3 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1792 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1793 | } |
| mbed_official | 237:f3da66175598 | 1794 | break; |
| mbed_official | 237:f3da66175598 | 1795 | |
| mbed_official | 237:f3da66175598 | 1796 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1797 | { |
| mbed_official | 237:f3da66175598 | 1798 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1799 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1800 | |
| mbed_official | 237:f3da66175598 | 1801 | /* Configure the TIM Channel 4 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1802 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1803 | } |
| mbed_official | 237:f3da66175598 | 1804 | break; |
| mbed_official | 237:f3da66175598 | 1805 | |
| mbed_official | 237:f3da66175598 | 1806 | case TIM_CHANNEL_5: |
| mbed_official | 237:f3da66175598 | 1807 | { |
| mbed_official | 237:f3da66175598 | 1808 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1809 | assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1810 | |
| mbed_official | 237:f3da66175598 | 1811 | /* Configure the TIM Channel 5 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1812 | TIM_OC5_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1813 | } |
| mbed_official | 237:f3da66175598 | 1814 | break; |
| mbed_official | 237:f3da66175598 | 1815 | |
| mbed_official | 237:f3da66175598 | 1816 | case TIM_CHANNEL_6: |
| mbed_official | 237:f3da66175598 | 1817 | { |
| mbed_official | 237:f3da66175598 | 1818 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1819 | assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1820 | |
| mbed_official | 237:f3da66175598 | 1821 | /* Configure the TIM Channel 6 in Output Compare */ |
| mbed_official | 237:f3da66175598 | 1822 | TIM_OC6_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1823 | } |
| mbed_official | 237:f3da66175598 | 1824 | break; |
| mbed_official | 237:f3da66175598 | 1825 | |
| mbed_official | 237:f3da66175598 | 1826 | default: |
| mbed_official | 237:f3da66175598 | 1827 | break; |
| mbed_official | 237:f3da66175598 | 1828 | } |
| mbed_official | 237:f3da66175598 | 1829 | |
| mbed_official | 237:f3da66175598 | 1830 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 1831 | |
| mbed_official | 237:f3da66175598 | 1832 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 1833 | |
| mbed_official | 237:f3da66175598 | 1834 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1835 | } |
| mbed_official | 237:f3da66175598 | 1836 | |
| mbed_official | 237:f3da66175598 | 1837 | /** |
| mbed_official | 237:f3da66175598 | 1838 | * @brief Initializes the TIM PWM channels according to the specified |
| mbed_official | 237:f3da66175598 | 1839 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 237:f3da66175598 | 1840 | * @param htim: TIM PWM handle |
| mbed_official | 237:f3da66175598 | 1841 | * @param sConfig: TIM PWM configuration structure |
| mbed_official | 237:f3da66175598 | 1842 | * @param Channel : TIM Channels to be configured |
| mbed_official | 237:f3da66175598 | 1843 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1844 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 237:f3da66175598 | 1845 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 237:f3da66175598 | 1846 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 237:f3da66175598 | 1847 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 237:f3da66175598 | 1848 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| mbed_official | 237:f3da66175598 | 1849 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| mbed_official | 237:f3da66175598 | 1850 | * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected |
| mbed_official | 237:f3da66175598 | 1851 | * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 PWM channels can |
| mbed_official | 237:f3da66175598 | 1852 | * be configured |
| mbed_official | 237:f3da66175598 | 1853 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 1854 | */ |
| mbed_official | 237:f3da66175598 | 1855 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 1856 | TIM_OC_InitTypeDef* sConfig, |
| mbed_official | 237:f3da66175598 | 1857 | uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 1858 | { |
| mbed_official | 237:f3da66175598 | 1859 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1860 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 237:f3da66175598 | 1861 | assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); |
| mbed_official | 237:f3da66175598 | 1862 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 237:f3da66175598 | 1863 | assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); |
| mbed_official | 237:f3da66175598 | 1864 | assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); |
| mbed_official | 237:f3da66175598 | 1865 | assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); |
| mbed_official | 237:f3da66175598 | 1866 | assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); |
| mbed_official | 237:f3da66175598 | 1867 | |
| mbed_official | 237:f3da66175598 | 1868 | /* Check input state */ |
| mbed_official | 237:f3da66175598 | 1869 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 1870 | |
| mbed_official | 237:f3da66175598 | 1871 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 1872 | |
| mbed_official | 237:f3da66175598 | 1873 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 1874 | { |
| mbed_official | 237:f3da66175598 | 1875 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 1876 | { |
| mbed_official | 237:f3da66175598 | 1877 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1878 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1879 | |
| mbed_official | 237:f3da66175598 | 1880 | /* Configure the Channel 1 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1881 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1882 | |
| mbed_official | 237:f3da66175598 | 1883 | /* Set the Preload enable bit for channel1 */ |
| mbed_official | 237:f3da66175598 | 1884 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; |
| mbed_official | 237:f3da66175598 | 1885 | |
| mbed_official | 237:f3da66175598 | 1886 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1887 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; |
| mbed_official | 237:f3da66175598 | 1888 | htim->Instance->CCMR1 |= sConfig->OCFastMode; |
| mbed_official | 237:f3da66175598 | 1889 | } |
| mbed_official | 237:f3da66175598 | 1890 | break; |
| mbed_official | 237:f3da66175598 | 1891 | |
| mbed_official | 237:f3da66175598 | 1892 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 1893 | { |
| mbed_official | 237:f3da66175598 | 1894 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1895 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1896 | |
| mbed_official | 237:f3da66175598 | 1897 | /* Configure the Channel 2 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1898 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1899 | |
| mbed_official | 237:f3da66175598 | 1900 | /* Set the Preload enable bit for channel2 */ |
| mbed_official | 237:f3da66175598 | 1901 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; |
| mbed_official | 237:f3da66175598 | 1902 | |
| mbed_official | 237:f3da66175598 | 1903 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1904 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; |
| mbed_official | 237:f3da66175598 | 1905 | htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; |
| mbed_official | 237:f3da66175598 | 1906 | } |
| mbed_official | 237:f3da66175598 | 1907 | break; |
| mbed_official | 237:f3da66175598 | 1908 | |
| mbed_official | 237:f3da66175598 | 1909 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 1910 | { |
| mbed_official | 237:f3da66175598 | 1911 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1912 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1913 | |
| mbed_official | 237:f3da66175598 | 1914 | /* Configure the Channel 3 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1915 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1916 | |
| mbed_official | 237:f3da66175598 | 1917 | /* Set the Preload enable bit for channel3 */ |
| mbed_official | 237:f3da66175598 | 1918 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; |
| mbed_official | 237:f3da66175598 | 1919 | |
| mbed_official | 237:f3da66175598 | 1920 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1921 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; |
| mbed_official | 237:f3da66175598 | 1922 | htim->Instance->CCMR2 |= sConfig->OCFastMode; |
| mbed_official | 237:f3da66175598 | 1923 | } |
| mbed_official | 237:f3da66175598 | 1924 | break; |
| mbed_official | 237:f3da66175598 | 1925 | |
| mbed_official | 237:f3da66175598 | 1926 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 1927 | { |
| mbed_official | 237:f3da66175598 | 1928 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1929 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1930 | |
| mbed_official | 237:f3da66175598 | 1931 | /* Configure the Channel 4 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1932 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1933 | |
| mbed_official | 237:f3da66175598 | 1934 | /* Set the Preload enable bit for channel4 */ |
| mbed_official | 237:f3da66175598 | 1935 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; |
| mbed_official | 237:f3da66175598 | 1936 | |
| mbed_official | 237:f3da66175598 | 1937 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1938 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; |
| mbed_official | 237:f3da66175598 | 1939 | htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; |
| mbed_official | 237:f3da66175598 | 1940 | } |
| mbed_official | 237:f3da66175598 | 1941 | break; |
| mbed_official | 237:f3da66175598 | 1942 | |
| mbed_official | 237:f3da66175598 | 1943 | case TIM_CHANNEL_5: |
| mbed_official | 237:f3da66175598 | 1944 | { |
| mbed_official | 237:f3da66175598 | 1945 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1946 | assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1947 | |
| mbed_official | 237:f3da66175598 | 1948 | /* Configure the Channel 5 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1949 | TIM_OC5_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1950 | |
| mbed_official | 237:f3da66175598 | 1951 | /* Set the Preload enable bit for channel5*/ |
| mbed_official | 237:f3da66175598 | 1952 | htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; |
| mbed_official | 237:f3da66175598 | 1953 | |
| mbed_official | 237:f3da66175598 | 1954 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1955 | htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; |
| mbed_official | 237:f3da66175598 | 1956 | htim->Instance->CCMR3 |= sConfig->OCFastMode; |
| mbed_official | 237:f3da66175598 | 1957 | } |
| mbed_official | 237:f3da66175598 | 1958 | break; |
| mbed_official | 237:f3da66175598 | 1959 | |
| mbed_official | 237:f3da66175598 | 1960 | case TIM_CHANNEL_6: |
| mbed_official | 237:f3da66175598 | 1961 | { |
| mbed_official | 237:f3da66175598 | 1962 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 1963 | assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 1964 | |
| mbed_official | 237:f3da66175598 | 1965 | /* Configure the Channel 5 in PWM mode */ |
| mbed_official | 237:f3da66175598 | 1966 | TIM_OC6_SetConfig(htim->Instance, sConfig); |
| mbed_official | 237:f3da66175598 | 1967 | |
| mbed_official | 237:f3da66175598 | 1968 | /* Set the Preload enable bit for channel6 */ |
| mbed_official | 237:f3da66175598 | 1969 | htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; |
| mbed_official | 237:f3da66175598 | 1970 | |
| mbed_official | 237:f3da66175598 | 1971 | /* Configure the Output Fast mode */ |
| mbed_official | 237:f3da66175598 | 1972 | htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; |
| mbed_official | 237:f3da66175598 | 1973 | htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; |
| mbed_official | 237:f3da66175598 | 1974 | } |
| mbed_official | 237:f3da66175598 | 1975 | break; |
| mbed_official | 237:f3da66175598 | 1976 | |
| mbed_official | 237:f3da66175598 | 1977 | default: |
| mbed_official | 237:f3da66175598 | 1978 | break; |
| mbed_official | 237:f3da66175598 | 1979 | } |
| mbed_official | 237:f3da66175598 | 1980 | |
| mbed_official | 237:f3da66175598 | 1981 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 1982 | |
| mbed_official | 237:f3da66175598 | 1983 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 1984 | |
| mbed_official | 237:f3da66175598 | 1985 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 1986 | } |
| mbed_official | 237:f3da66175598 | 1987 | |
| mbed_official | 237:f3da66175598 | 1988 | /** |
| mbed_official | 237:f3da66175598 | 1989 | * @brief Configures the OCRef clear feature |
| mbed_official | 237:f3da66175598 | 1990 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 1991 | * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that |
| mbed_official | 237:f3da66175598 | 1992 | * contains the OCREF clear feature and parameters for the TIM peripheral. |
| mbed_official | 237:f3da66175598 | 1993 | * @param Channel: specifies the TIM Channel |
| mbed_official | 237:f3da66175598 | 1994 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 1995 | * @arg TIM_Channel_1: TIM Channel 1 |
| mbed_official | 237:f3da66175598 | 1996 | * @arg TIM_Channel_2: TIM Channel 2 |
| mbed_official | 237:f3da66175598 | 1997 | * @arg TIM_Channel_3: TIM Channel 3 |
| mbed_official | 237:f3da66175598 | 1998 | * @arg TIM_Channel_4: TIM Channel 4 |
| mbed_official | 237:f3da66175598 | 1999 | * @arg TIM_Channel_5: TIM Channel 5 |
| mbed_official | 237:f3da66175598 | 2000 | * @arg TIM_Channel_6: TIM Channel 6 |
| mbed_official | 237:f3da66175598 | 2001 | * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 OC channels can |
| mbed_official | 237:f3da66175598 | 2002 | * be configured |
| mbed_official | 237:f3da66175598 | 2003 | * @retval None |
| mbed_official | 237:f3da66175598 | 2004 | */ |
| mbed_official | 237:f3da66175598 | 2005 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 2006 | TIM_ClearInputConfigTypeDef *sClearInputConfig, |
| mbed_official | 237:f3da66175598 | 2007 | uint32_t Channel) |
| mbed_official | 237:f3da66175598 | 2008 | { |
| mbed_official | 237:f3da66175598 | 2009 | uint32_t tmpsmcr = 0; |
| mbed_official | 237:f3da66175598 | 2010 | |
| mbed_official | 237:f3da66175598 | 2011 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2012 | assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2013 | assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); |
| mbed_official | 237:f3da66175598 | 2014 | |
| mbed_official | 237:f3da66175598 | 2015 | /* Check input state */ |
| mbed_official | 237:f3da66175598 | 2016 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2017 | |
| mbed_official | 237:f3da66175598 | 2018 | switch (sClearInputConfig->ClearInputSource) |
| mbed_official | 237:f3da66175598 | 2019 | { |
| mbed_official | 237:f3da66175598 | 2020 | case TIM_CLEARINPUTSOURCE_NONE: |
| mbed_official | 237:f3da66175598 | 2021 | { |
| mbed_official | 237:f3da66175598 | 2022 | /* Clear the OCREF clear selection bit */ |
| mbed_official | 237:f3da66175598 | 2023 | tmpsmcr &= ~TIM_SMCR_OCCS; |
| mbed_official | 237:f3da66175598 | 2024 | |
| mbed_official | 237:f3da66175598 | 2025 | /* Clear the ETR Bits */ |
| mbed_official | 237:f3da66175598 | 2026 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); |
| mbed_official | 237:f3da66175598 | 2027 | |
| mbed_official | 237:f3da66175598 | 2028 | /* Set TIMx_SMCR */ |
| mbed_official | 237:f3da66175598 | 2029 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 237:f3da66175598 | 2030 | } |
| mbed_official | 237:f3da66175598 | 2031 | break; |
| mbed_official | 237:f3da66175598 | 2032 | |
| mbed_official | 237:f3da66175598 | 2033 | case TIM_CLEARINPUTSOURCE_OCREFCLR: |
| mbed_official | 237:f3da66175598 | 2034 | { |
| mbed_official | 237:f3da66175598 | 2035 | /* Clear the OCREF clear selection bit */ |
| mbed_official | 237:f3da66175598 | 2036 | htim->Instance->SMCR &= ~TIM_SMCR_OCCS; |
| mbed_official | 237:f3da66175598 | 2037 | } |
| mbed_official | 237:f3da66175598 | 2038 | break; |
| mbed_official | 237:f3da66175598 | 2039 | |
| mbed_official | 237:f3da66175598 | 2040 | case TIM_CLEARINPUTSOURCE_ETR: |
| mbed_official | 237:f3da66175598 | 2041 | { |
| mbed_official | 237:f3da66175598 | 2042 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2043 | assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); |
| mbed_official | 237:f3da66175598 | 2044 | assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); |
| mbed_official | 237:f3da66175598 | 2045 | assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); |
| mbed_official | 237:f3da66175598 | 2046 | |
| mbed_official | 237:f3da66175598 | 2047 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 237:f3da66175598 | 2048 | sClearInputConfig->ClearInputPrescaler, |
| mbed_official | 237:f3da66175598 | 2049 | sClearInputConfig->ClearInputPolarity, |
| mbed_official | 237:f3da66175598 | 2050 | sClearInputConfig->ClearInputFilter); |
| mbed_official | 237:f3da66175598 | 2051 | |
| mbed_official | 237:f3da66175598 | 2052 | /* Set the OCREF clear selection bit */ |
| mbed_official | 237:f3da66175598 | 2053 | htim->Instance->SMCR |= TIM_SMCR_OCCS; |
| mbed_official | 237:f3da66175598 | 2054 | } |
| mbed_official | 237:f3da66175598 | 2055 | break; |
| mbed_official | 237:f3da66175598 | 2056 | } |
| mbed_official | 237:f3da66175598 | 2057 | |
| mbed_official | 237:f3da66175598 | 2058 | switch (Channel) |
| mbed_official | 237:f3da66175598 | 2059 | { |
| mbed_official | 237:f3da66175598 | 2060 | case TIM_CHANNEL_1: |
| mbed_official | 237:f3da66175598 | 2061 | { |
| mbed_official | 237:f3da66175598 | 2062 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2063 | { |
| mbed_official | 237:f3da66175598 | 2064 | /* Enable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2065 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; |
| mbed_official | 237:f3da66175598 | 2066 | } |
| mbed_official | 237:f3da66175598 | 2067 | else |
| mbed_official | 237:f3da66175598 | 2068 | { |
| mbed_official | 237:f3da66175598 | 2069 | /* Disable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2070 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; |
| mbed_official | 237:f3da66175598 | 2071 | } |
| mbed_official | 237:f3da66175598 | 2072 | } |
| mbed_official | 237:f3da66175598 | 2073 | break; |
| mbed_official | 237:f3da66175598 | 2074 | case TIM_CHANNEL_2: |
| mbed_official | 237:f3da66175598 | 2075 | { |
| mbed_official | 237:f3da66175598 | 2076 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2077 | { |
| mbed_official | 237:f3da66175598 | 2078 | /* Enable the Ocref clear feature for Channel 2 */ |
| mbed_official | 237:f3da66175598 | 2079 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; |
| mbed_official | 237:f3da66175598 | 2080 | } |
| mbed_official | 237:f3da66175598 | 2081 | else |
| mbed_official | 237:f3da66175598 | 2082 | { |
| mbed_official | 237:f3da66175598 | 2083 | /* Disable the Ocref clear feature for Channel 2 */ |
| mbed_official | 237:f3da66175598 | 2084 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; |
| mbed_official | 237:f3da66175598 | 2085 | } |
| mbed_official | 237:f3da66175598 | 2086 | } |
| mbed_official | 237:f3da66175598 | 2087 | break; |
| mbed_official | 237:f3da66175598 | 2088 | case TIM_CHANNEL_3: |
| mbed_official | 237:f3da66175598 | 2089 | { |
| mbed_official | 237:f3da66175598 | 2090 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2091 | { |
| mbed_official | 237:f3da66175598 | 2092 | /* Enable the Ocref clear feature for Channel 3 */ |
| mbed_official | 237:f3da66175598 | 2093 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; |
| mbed_official | 237:f3da66175598 | 2094 | } |
| mbed_official | 237:f3da66175598 | 2095 | else |
| mbed_official | 237:f3da66175598 | 2096 | { |
| mbed_official | 237:f3da66175598 | 2097 | /* Disable the Ocref clear feature for Channel 3 */ |
| mbed_official | 237:f3da66175598 | 2098 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; |
| mbed_official | 237:f3da66175598 | 2099 | } |
| mbed_official | 237:f3da66175598 | 2100 | } |
| mbed_official | 237:f3da66175598 | 2101 | break; |
| mbed_official | 237:f3da66175598 | 2102 | case TIM_CHANNEL_4: |
| mbed_official | 237:f3da66175598 | 2103 | { |
| mbed_official | 237:f3da66175598 | 2104 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2105 | { |
| mbed_official | 237:f3da66175598 | 2106 | /* Enable the Ocref clear feature for Channel 4 */ |
| mbed_official | 237:f3da66175598 | 2107 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; |
| mbed_official | 237:f3da66175598 | 2108 | } |
| mbed_official | 237:f3da66175598 | 2109 | else |
| mbed_official | 237:f3da66175598 | 2110 | { |
| mbed_official | 237:f3da66175598 | 2111 | /* Disable the Ocref clear feature for Channel 4 */ |
| mbed_official | 237:f3da66175598 | 2112 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; |
| mbed_official | 237:f3da66175598 | 2113 | } |
| mbed_official | 237:f3da66175598 | 2114 | } |
| mbed_official | 237:f3da66175598 | 2115 | break; |
| mbed_official | 237:f3da66175598 | 2116 | case TIM_CHANNEL_5: |
| mbed_official | 237:f3da66175598 | 2117 | { |
| mbed_official | 237:f3da66175598 | 2118 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2119 | { |
| mbed_official | 237:f3da66175598 | 2120 | /* Enable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2121 | htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; |
| mbed_official | 237:f3da66175598 | 2122 | } |
| mbed_official | 237:f3da66175598 | 2123 | else |
| mbed_official | 237:f3da66175598 | 2124 | { |
| mbed_official | 237:f3da66175598 | 2125 | /* Disable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2126 | htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; |
| mbed_official | 237:f3da66175598 | 2127 | } |
| mbed_official | 237:f3da66175598 | 2128 | } |
| mbed_official | 237:f3da66175598 | 2129 | break; |
| mbed_official | 237:f3da66175598 | 2130 | case TIM_CHANNEL_6: |
| mbed_official | 237:f3da66175598 | 2131 | { |
| mbed_official | 237:f3da66175598 | 2132 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 237:f3da66175598 | 2133 | { |
| mbed_official | 237:f3da66175598 | 2134 | /* Enable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2135 | htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; |
| mbed_official | 237:f3da66175598 | 2136 | } |
| mbed_official | 237:f3da66175598 | 2137 | else |
| mbed_official | 237:f3da66175598 | 2138 | { |
| mbed_official | 237:f3da66175598 | 2139 | /* Disable the Ocref clear feature for Channel 1 */ |
| mbed_official | 237:f3da66175598 | 2140 | htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; |
| mbed_official | 237:f3da66175598 | 2141 | } |
| mbed_official | 237:f3da66175598 | 2142 | } |
| mbed_official | 237:f3da66175598 | 2143 | break; |
| mbed_official | 237:f3da66175598 | 2144 | default: |
| mbed_official | 237:f3da66175598 | 2145 | break; |
| mbed_official | 237:f3da66175598 | 2146 | } |
| mbed_official | 237:f3da66175598 | 2147 | |
| mbed_official | 237:f3da66175598 | 2148 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2149 | |
| mbed_official | 237:f3da66175598 | 2150 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2151 | } |
| mbed_official | 237:f3da66175598 | 2152 | |
| mbed_official | 237:f3da66175598 | 2153 | /** |
| mbed_official | 237:f3da66175598 | 2154 | * @brief Configures the TIM in master mode. |
| mbed_official | 237:f3da66175598 | 2155 | * @param htim: TIM handle. |
| mbed_official | 237:f3da66175598 | 2156 | * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that |
| mbed_official | 237:f3da66175598 | 2157 | * contains the selected trigger output (TRGO) and the Master/Slave |
| mbed_official | 237:f3da66175598 | 2158 | * mode. |
| mbed_official | 237:f3da66175598 | 2159 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2160 | */ |
| mbed_official | 237:f3da66175598 | 2161 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 2162 | TIM_MasterConfigTypeDef * sMasterConfig) |
| mbed_official | 237:f3da66175598 | 2163 | { |
| mbed_official | 237:f3da66175598 | 2164 | uint32_t tmpcr2; |
| mbed_official | 237:f3da66175598 | 2165 | uint32_t tmpsmcr; |
| mbed_official | 237:f3da66175598 | 2166 | |
| mbed_official | 237:f3da66175598 | 2167 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2168 | assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2169 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
| mbed_official | 237:f3da66175598 | 2170 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
| mbed_official | 237:f3da66175598 | 2171 | |
| mbed_official | 237:f3da66175598 | 2172 | /* Check input state */ |
| mbed_official | 237:f3da66175598 | 2173 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2174 | |
| mbed_official | 237:f3da66175598 | 2175 | /* Get the TIMx CR2 register value */ |
| mbed_official | 237:f3da66175598 | 2176 | tmpcr2 = htim->Instance->CR2; |
| mbed_official | 237:f3da66175598 | 2177 | |
| mbed_official | 237:f3da66175598 | 2178 | /* Get the TIMx SMCR register value */ |
| mbed_official | 237:f3da66175598 | 2179 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 237:f3da66175598 | 2180 | |
| mbed_official | 237:f3da66175598 | 2181 | /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ |
| mbed_official | 237:f3da66175598 | 2182 | if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) |
| mbed_official | 237:f3da66175598 | 2183 | { |
| mbed_official | 237:f3da66175598 | 2184 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2185 | assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); |
| mbed_official | 237:f3da66175598 | 2186 | |
| mbed_official | 237:f3da66175598 | 2187 | /* Clear the MMS2 bits */ |
| mbed_official | 237:f3da66175598 | 2188 | tmpcr2 &= ~TIM_CR2_MMS2; |
| mbed_official | 237:f3da66175598 | 2189 | /* Select the TRGO2 source*/ |
| mbed_official | 237:f3da66175598 | 2190 | tmpcr2 |= sMasterConfig->MasterOutputTrigger2; |
| mbed_official | 237:f3da66175598 | 2191 | } |
| mbed_official | 237:f3da66175598 | 2192 | |
| mbed_official | 237:f3da66175598 | 2193 | /* Reset the MMS Bits */ |
| mbed_official | 237:f3da66175598 | 2194 | tmpcr2 &= ~TIM_CR2_MMS; |
| mbed_official | 237:f3da66175598 | 2195 | /* Select the TRGO source */ |
| mbed_official | 237:f3da66175598 | 2196 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
| mbed_official | 237:f3da66175598 | 2197 | |
| mbed_official | 237:f3da66175598 | 2198 | /* Reset the MSM Bit */ |
| mbed_official | 237:f3da66175598 | 2199 | tmpsmcr &= ~TIM_SMCR_MSM; |
| mbed_official | 237:f3da66175598 | 2200 | /* Set master mode */ |
| mbed_official | 237:f3da66175598 | 2201 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
| mbed_official | 237:f3da66175598 | 2202 | |
| mbed_official | 237:f3da66175598 | 2203 | /* Update TIMx CR2 */ |
| mbed_official | 237:f3da66175598 | 2204 | htim->Instance->CR2 = tmpcr2; |
| mbed_official | 237:f3da66175598 | 2205 | |
| mbed_official | 237:f3da66175598 | 2206 | /* Update TIMx SMCR */ |
| mbed_official | 237:f3da66175598 | 2207 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 237:f3da66175598 | 2208 | |
| mbed_official | 237:f3da66175598 | 2209 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2210 | |
| mbed_official | 237:f3da66175598 | 2211 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2212 | } |
| mbed_official | 375:3d36234a1087 | 2213 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 2214 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 2215 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 2216 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 237:f3da66175598 | 2217 | |
| mbed_official | 237:f3da66175598 | 2218 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| mbed_official | 237:f3da66175598 | 2219 | /** |
| mbed_official | 237:f3da66175598 | 2220 | * @brief Configures the TIM in master mode. |
| mbed_official | 237:f3da66175598 | 2221 | * @param htim: TIM handle. |
| mbed_official | 237:f3da66175598 | 2222 | * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that |
| mbed_official | 237:f3da66175598 | 2223 | * contains the selected trigger output (TRGO) and the Master/Slave |
| mbed_official | 237:f3da66175598 | 2224 | * mode. |
| mbed_official | 237:f3da66175598 | 2225 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2226 | */ |
| mbed_official | 237:f3da66175598 | 2227 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) |
| mbed_official | 237:f3da66175598 | 2228 | { |
| mbed_official | 237:f3da66175598 | 2229 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2230 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2231 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
| mbed_official | 237:f3da66175598 | 2232 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
| mbed_official | 237:f3da66175598 | 2233 | |
| mbed_official | 237:f3da66175598 | 2234 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2235 | |
| mbed_official | 237:f3da66175598 | 2236 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 2237 | |
| mbed_official | 237:f3da66175598 | 2238 | /* Reset the MMS Bits */ |
| mbed_official | 237:f3da66175598 | 2239 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
| mbed_official | 237:f3da66175598 | 2240 | /* Select the TRGO source */ |
| mbed_official | 237:f3da66175598 | 2241 | htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; |
| mbed_official | 237:f3da66175598 | 2242 | |
| mbed_official | 237:f3da66175598 | 2243 | /* Reset the MSM Bit */ |
| mbed_official | 237:f3da66175598 | 2244 | htim->Instance->SMCR &= ~TIM_SMCR_MSM; |
| mbed_official | 237:f3da66175598 | 2245 | /* Set or Reset the MSM Bit */ |
| mbed_official | 237:f3da66175598 | 2246 | htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; |
| mbed_official | 237:f3da66175598 | 2247 | |
| mbed_official | 237:f3da66175598 | 2248 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2249 | |
| mbed_official | 237:f3da66175598 | 2250 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2251 | |
| mbed_official | 237:f3da66175598 | 2252 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2253 | } |
| mbed_official | 237:f3da66175598 | 2254 | #endif /* STM32F373xC || STM32F378xx */ |
| mbed_official | 237:f3da66175598 | 2255 | |
| mbed_official | 375:3d36234a1087 | 2256 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 2257 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 2258 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 2259 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 237:f3da66175598 | 2260 | /** |
| mbed_official | 237:f3da66175598 | 2261 | * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State |
| mbed_official | 237:f3da66175598 | 2262 | * and the AOE(automatic output enable). |
| mbed_official | 237:f3da66175598 | 2263 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 2264 | * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that |
| mbed_official | 237:f3da66175598 | 2265 | * contains the BDTR Register configuration information for the TIM peripheral. |
| mbed_official | 375:3d36234a1087 | 2266 | * @note For STM32F302xC, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx and STM32F303x8 two break inputs can be configured. |
| mbed_official | 237:f3da66175598 | 2267 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2268 | */ |
| mbed_official | 237:f3da66175598 | 2269 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 2270 | TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) |
| mbed_official | 237:f3da66175598 | 2271 | { |
| mbed_official | 237:f3da66175598 | 2272 | uint32_t tmpbdtr = 0; |
| mbed_official | 237:f3da66175598 | 2273 | |
| mbed_official | 237:f3da66175598 | 2274 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2275 | assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2276 | assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); |
| mbed_official | 237:f3da66175598 | 2277 | assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); |
| mbed_official | 237:f3da66175598 | 2278 | assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); |
| mbed_official | 375:3d36234a1087 | 2279 | assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); |
| mbed_official | 237:f3da66175598 | 2280 | assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); |
| mbed_official | 237:f3da66175598 | 2281 | assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); |
| mbed_official | 237:f3da66175598 | 2282 | assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); |
| mbed_official | 237:f3da66175598 | 2283 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); |
| mbed_official | 237:f3da66175598 | 2284 | |
| mbed_official | 237:f3da66175598 | 2285 | /* Check input state */ |
| mbed_official | 237:f3da66175598 | 2286 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2287 | |
| mbed_official | 237:f3da66175598 | 2288 | /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, |
| mbed_official | 237:f3da66175598 | 2289 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
| mbed_official | 237:f3da66175598 | 2290 | if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) |
| mbed_official | 237:f3da66175598 | 2291 | { |
| mbed_official | 237:f3da66175598 | 2292 | assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); |
| mbed_official | 237:f3da66175598 | 2293 | assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); |
| mbed_official | 237:f3da66175598 | 2294 | assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); |
| mbed_official | 237:f3da66175598 | 2295 | |
| mbed_official | 237:f3da66175598 | 2296 | /* Clear the BDTR bits */ |
| mbed_official | 237:f3da66175598 | 2297 | tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | |
| mbed_official | 237:f3da66175598 | 2298 | TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | |
| mbed_official | 237:f3da66175598 | 2299 | TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF | |
| mbed_official | 237:f3da66175598 | 2300 | TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P); |
| mbed_official | 237:f3da66175598 | 2301 | |
| mbed_official | 237:f3da66175598 | 2302 | /* Set the BDTR bits */ |
| mbed_official | 237:f3da66175598 | 2303 | tmpbdtr |= sBreakDeadTimeConfig->DeadTime; |
| mbed_official | 237:f3da66175598 | 2304 | tmpbdtr |= sBreakDeadTimeConfig->LockLevel; |
| mbed_official | 237:f3da66175598 | 2305 | tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; |
| mbed_official | 237:f3da66175598 | 2306 | tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; |
| mbed_official | 237:f3da66175598 | 2307 | tmpbdtr |= sBreakDeadTimeConfig->BreakState; |
| mbed_official | 237:f3da66175598 | 2308 | tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; |
| mbed_official | 237:f3da66175598 | 2309 | tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; |
| mbed_official | 237:f3da66175598 | 2310 | tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); |
| mbed_official | 237:f3da66175598 | 2311 | tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT); |
| mbed_official | 237:f3da66175598 | 2312 | tmpbdtr |= sBreakDeadTimeConfig->Break2State; |
| mbed_official | 237:f3da66175598 | 2313 | tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity; |
| mbed_official | 237:f3da66175598 | 2314 | } |
| mbed_official | 237:f3da66175598 | 2315 | else |
| mbed_official | 237:f3da66175598 | 2316 | { |
| mbed_official | 237:f3da66175598 | 2317 | /* Clear the BDTR bits */ |
| mbed_official | 237:f3da66175598 | 2318 | tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | |
| mbed_official | 237:f3da66175598 | 2319 | TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | |
| mbed_official | 237:f3da66175598 | 2320 | TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF); |
| mbed_official | 237:f3da66175598 | 2321 | |
| mbed_official | 237:f3da66175598 | 2322 | /* Set the BDTR bits */ |
| mbed_official | 237:f3da66175598 | 2323 | tmpbdtr |= sBreakDeadTimeConfig->DeadTime; |
| mbed_official | 237:f3da66175598 | 2324 | tmpbdtr |= sBreakDeadTimeConfig->LockLevel; |
| mbed_official | 237:f3da66175598 | 2325 | tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; |
| mbed_official | 237:f3da66175598 | 2326 | tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; |
| mbed_official | 237:f3da66175598 | 2327 | tmpbdtr |= sBreakDeadTimeConfig->BreakState; |
| mbed_official | 237:f3da66175598 | 2328 | tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; |
| mbed_official | 237:f3da66175598 | 2329 | tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; |
| mbed_official | 237:f3da66175598 | 2330 | tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); |
| mbed_official | 237:f3da66175598 | 2331 | } |
| mbed_official | 237:f3da66175598 | 2332 | |
| mbed_official | 237:f3da66175598 | 2333 | /* Set TIMx_BDTR */ |
| mbed_official | 237:f3da66175598 | 2334 | htim->Instance->BDTR = tmpbdtr; |
| mbed_official | 237:f3da66175598 | 2335 | |
| mbed_official | 237:f3da66175598 | 2336 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2337 | |
| mbed_official | 237:f3da66175598 | 2338 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2339 | } |
| mbed_official | 375:3d36234a1087 | 2340 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 2341 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 2342 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 2343 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 237:f3da66175598 | 2344 | |
| mbed_official | 237:f3da66175598 | 2345 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| mbed_official | 237:f3da66175598 | 2346 | /** |
| mbed_official | 237:f3da66175598 | 2347 | * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State |
| mbed_official | 237:f3da66175598 | 2348 | * and the AOE(automatic output enable). |
| mbed_official | 237:f3da66175598 | 2349 | * @param htim: TIM handle |
| mbed_official | 237:f3da66175598 | 2350 | * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that |
| mbed_official | 237:f3da66175598 | 2351 | * contains the BDTR Register configuration information for the TIM peripheral. |
| mbed_official | 237:f3da66175598 | 2352 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2353 | */ |
| mbed_official | 237:f3da66175598 | 2354 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
| mbed_official | 237:f3da66175598 | 2355 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) |
| mbed_official | 237:f3da66175598 | 2356 | { |
| mbed_official | 237:f3da66175598 | 2357 | /* Check the parameters */ |
| mbed_official | 237:f3da66175598 | 2358 | assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2359 | assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); |
| mbed_official | 237:f3da66175598 | 2360 | assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); |
| mbed_official | 237:f3da66175598 | 2361 | assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); |
| mbed_official | 375:3d36234a1087 | 2362 | assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); |
| mbed_official | 237:f3da66175598 | 2363 | assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); |
| mbed_official | 237:f3da66175598 | 2364 | assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); |
| mbed_official | 237:f3da66175598 | 2365 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); |
| mbed_official | 237:f3da66175598 | 2366 | |
| mbed_official | 237:f3da66175598 | 2367 | /* Process Locked */ |
| mbed_official | 237:f3da66175598 | 2368 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2369 | |
| mbed_official | 237:f3da66175598 | 2370 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 2371 | |
| mbed_official | 237:f3da66175598 | 2372 | /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, |
| mbed_official | 237:f3da66175598 | 2373 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
| mbed_official | 237:f3da66175598 | 2374 | htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | |
| mbed_official | 237:f3da66175598 | 2375 | sBreakDeadTimeConfig->OffStateIDLEMode | |
| mbed_official | 237:f3da66175598 | 2376 | sBreakDeadTimeConfig->LockLevel | |
| mbed_official | 237:f3da66175598 | 2377 | sBreakDeadTimeConfig->DeadTime | |
| mbed_official | 237:f3da66175598 | 2378 | sBreakDeadTimeConfig->BreakState | |
| mbed_official | 237:f3da66175598 | 2379 | sBreakDeadTimeConfig->BreakPolarity | |
| mbed_official | 237:f3da66175598 | 2380 | sBreakDeadTimeConfig->AutomaticOutput; |
| mbed_official | 237:f3da66175598 | 2381 | |
| mbed_official | 237:f3da66175598 | 2382 | |
| mbed_official | 237:f3da66175598 | 2383 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2384 | |
| mbed_official | 237:f3da66175598 | 2385 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2386 | |
| mbed_official | 237:f3da66175598 | 2387 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2388 | } |
| mbed_official | 237:f3da66175598 | 2389 | #endif /* STM32F373xC || STM32F378xx */ |
| mbed_official | 237:f3da66175598 | 2390 | |
| mbed_official | 375:3d36234a1087 | 2391 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 375:3d36234a1087 | 2392 | defined(STM32F303xC) || defined(STM32F358xx) |
| mbed_official | 375:3d36234a1087 | 2393 | #if defined(STM32F303xE) || defined(STM32F398xx) |
| mbed_official | 375:3d36234a1087 | 2394 | /** |
| mbed_official | 375:3d36234a1087 | 2395 | * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities. |
| mbed_official | 375:3d36234a1087 | 2396 | * @param htim: TIM handle. |
| mbed_official | 375:3d36234a1087 | 2397 | * @param Remap1: specifies the first TIM remapping source. |
| mbed_official | 375:3d36234a1087 | 2398 | * This parameter can be one of the following values: |
| mbed_official | 375:3d36234a1087 | 2399 | * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) |
| mbed_official | 375:3d36234a1087 | 2400 | * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 |
| mbed_official | 375:3d36234a1087 | 2401 | * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 |
| mbed_official | 375:3d36234a1087 | 2402 | * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 |
| mbed_official | 375:3d36234a1087 | 2403 | * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD |
| mbed_official | 375:3d36234a1087 | 2404 | * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 |
| mbed_official | 375:3d36234a1087 | 2405 | * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 |
| mbed_official | 375:3d36234a1087 | 2406 | * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 |
| mbed_official | 375:3d36234a1087 | 2407 | * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO |
| mbed_official | 375:3d36234a1087 | 2408 | * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock |
| mbed_official | 375:3d36234a1087 | 2409 | * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 |
| mbed_official | 375:3d36234a1087 | 2410 | * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO |
| mbed_official | 375:3d36234a1087 | 2411 | * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog) |
| mbed_official | 375:3d36234a1087 | 2412 | * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1 |
| mbed_official | 375:3d36234a1087 | 2413 | * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2 |
| mbed_official | 375:3d36234a1087 | 2414 | * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3 |
| mbed_official | 375:3d36234a1087 | 2415 | * @param Remap2: specifies the second TIMremapping source (if any). |
| mbed_official | 375:3d36234a1087 | 2416 | * This parameter can be one of the following values: |
| mbed_official | 375:3d36234a1087 | 2417 | * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog) |
| mbed_official | 375:3d36234a1087 | 2418 | * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 |
| mbed_official | 375:3d36234a1087 | 2419 | * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 |
| mbed_official | 375:3d36234a1087 | 2420 | * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 |
| mbed_official | 375:3d36234a1087 | 2421 | * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD |
| mbed_official | 375:3d36234a1087 | 2422 | * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 |
| mbed_official | 375:3d36234a1087 | 2423 | * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 |
| mbed_official | 375:3d36234a1087 | 2424 | * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 |
| mbed_official | 375:3d36234a1087 | 2425 | * @arg TIM_TIM16_NONE: Non significant value for TIM16 |
| mbed_official | 375:3d36234a1087 | 2426 | * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD |
| mbed_official | 375:3d36234a1087 | 2427 | * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1 |
| mbed_official | 375:3d36234a1087 | 2428 | * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2 |
| mbed_official | 375:3d36234a1087 | 2429 | * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3 |
| mbed_official | 375:3d36234a1087 | 2430 | * @retval HAL status |
| mbed_official | 375:3d36234a1087 | 2431 | */ |
| mbed_official | 375:3d36234a1087 | 2432 | #else /* STM32F303xC || STM32F358xx */ |
| mbed_official | 237:f3da66175598 | 2433 | /** |
| mbed_official | 237:f3da66175598 | 2434 | * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities. |
| mbed_official | 237:f3da66175598 | 2435 | * @param htim: TIM handle. |
| mbed_official | 237:f3da66175598 | 2436 | * @param Remap1: specifies the first TIM remapping source. |
| mbed_official | 237:f3da66175598 | 2437 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 2438 | * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) |
| mbed_official | 237:f3da66175598 | 2439 | * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 |
| mbed_official | 237:f3da66175598 | 2440 | * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 |
| mbed_official | 237:f3da66175598 | 2441 | * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 |
| mbed_official | 237:f3da66175598 | 2442 | * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD |
| mbed_official | 237:f3da66175598 | 2443 | * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 |
| mbed_official | 237:f3da66175598 | 2444 | * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 |
| mbed_official | 237:f3da66175598 | 2445 | * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 |
| mbed_official | 237:f3da66175598 | 2446 | * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO |
| mbed_official | 237:f3da66175598 | 2447 | * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock |
| mbed_official | 237:f3da66175598 | 2448 | * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 |
| mbed_official | 237:f3da66175598 | 2449 | * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO |
| mbed_official | 237:f3da66175598 | 2450 | * @param Remap2: specifies the second TIMremapping source (if any). |
| mbed_official | 237:f3da66175598 | 2451 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 2452 | * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) |
| mbed_official | 237:f3da66175598 | 2453 | * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 |
| mbed_official | 237:f3da66175598 | 2454 | * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 |
| mbed_official | 237:f3da66175598 | 2455 | * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 |
| mbed_official | 237:f3da66175598 | 2456 | * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD |
| mbed_official | 237:f3da66175598 | 2457 | * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 |
| mbed_official | 237:f3da66175598 | 2458 | * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 |
| mbed_official | 237:f3da66175598 | 2459 | * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 |
| mbed_official | 237:f3da66175598 | 2460 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2461 | */ |
| mbed_official | 375:3d36234a1087 | 2462 | #endif /* STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 2463 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2) |
| mbed_official | 237:f3da66175598 | 2464 | { |
| mbed_official | 237:f3da66175598 | 2465 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2466 | |
| mbed_official | 237:f3da66175598 | 2467 | /* Check parameters */ |
| mbed_official | 237:f3da66175598 | 2468 | assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2469 | assert_param(IS_TIM_REMAP(Remap1)); |
| mbed_official | 237:f3da66175598 | 2470 | assert_param(IS_TIM_REMAP2(Remap2)); |
| mbed_official | 237:f3da66175598 | 2471 | |
| mbed_official | 237:f3da66175598 | 2472 | /* Set the Timer remapping configuration */ |
| mbed_official | 237:f3da66175598 | 2473 | htim->Instance->OR = Remap1 | Remap2; |
| mbed_official | 237:f3da66175598 | 2474 | |
| mbed_official | 237:f3da66175598 | 2475 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2476 | |
| mbed_official | 237:f3da66175598 | 2477 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2478 | |
| mbed_official | 237:f3da66175598 | 2479 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2480 | } |
| mbed_official | 375:3d36234a1087 | 2481 | #endif /* STM32F303xE || STM32F398xx || */ |
| mbed_official | 375:3d36234a1087 | 2482 | /* STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 2483 | |
| mbed_official | 237:f3da66175598 | 2484 | |
| mbed_official | 375:3d36234a1087 | 2485 | #if defined(STM32F302xE) || \ |
| mbed_official | 375:3d36234a1087 | 2486 | defined(STM32F302xC) || \ |
| mbed_official | 375:3d36234a1087 | 2487 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 2488 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| mbed_official | 375:3d36234a1087 | 2489 | defined(STM32F373xC) || defined(STM32F378xx) |
| mbed_official | 375:3d36234a1087 | 2490 | #if defined(STM32F302xE) || \ |
| mbed_official | 375:3d36234a1087 | 2491 | defined(STM32F302xC) || \ |
| mbed_official | 237:f3da66175598 | 2492 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 2493 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 375:3d36234a1087 | 2494 | /** |
| mbed_official | 375:3d36234a1087 | 2495 | * @brief Configures the TIM1 and TIM16 Remapping input capabilities. |
| mbed_official | 375:3d36234a1087 | 2496 | * @param htim: TIM handle. |
| mbed_official | 375:3d36234a1087 | 2497 | * @param Remap: specifies the TIM remapping source. |
| mbed_official | 375:3d36234a1087 | 2498 | * This parameter can be one of the following values: |
| mbed_official | 375:3d36234a1087 | 2499 | * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) |
| mbed_official | 375:3d36234a1087 | 2500 | * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 |
| mbed_official | 375:3d36234a1087 | 2501 | * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 |
| mbed_official | 375:3d36234a1087 | 2502 | * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 |
| mbed_official | 375:3d36234a1087 | 2503 | * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO |
| mbed_official | 375:3d36234a1087 | 2504 | * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock |
| mbed_official | 375:3d36234a1087 | 2505 | * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 |
| mbed_official | 375:3d36234a1087 | 2506 | * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO |
| mbed_official | 375:3d36234a1087 | 2507 | * @retval HAL status |
| mbed_official | 375:3d36234a1087 | 2508 | */ |
| mbed_official | 375:3d36234a1087 | 2509 | #else /* STM32F373xC || STM32F378xx */ |
| mbed_official | 237:f3da66175598 | 2510 | /** |
| mbed_official | 237:f3da66175598 | 2511 | * @brief Configures the TIM2 and TIM14 Remapping input capabilities. |
| mbed_official | 237:f3da66175598 | 2512 | * @param htim: TIM handle. |
| mbed_official | 237:f3da66175598 | 2513 | * @param Remap: specifies the TIM remapping source. |
| mbed_official | 237:f3da66175598 | 2514 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 2515 | * STM32F373xC, STM32F378xx: |
| mbed_official | 237:f3da66175598 | 2516 | * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1 |
| mbed_official | 237:f3da66175598 | 2517 | * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1 |
| mbed_official | 237:f3da66175598 | 2518 | * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input |
| mbed_official | 237:f3da66175598 | 2519 | * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input |
| mbed_official | 237:f3da66175598 | 2520 | * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO |
| mbed_official | 237:f3da66175598 | 2521 | * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock |
| mbed_official | 237:f3da66175598 | 2522 | * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 |
| mbed_official | 237:f3da66175598 | 2523 | * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO |
| mbed_official | 237:f3da66175598 | 2524 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2525 | */ |
| mbed_official | 375:3d36234a1087 | 2526 | #endif /* STM32F302xE || */ |
| mbed_official | 375:3d36234a1087 | 2527 | /* STM32F302xC || */ |
| mbed_official | 375:3d36234a1087 | 2528 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 2529 | /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| mbed_official | 237:f3da66175598 | 2530 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
| mbed_official | 237:f3da66175598 | 2531 | { |
| mbed_official | 237:f3da66175598 | 2532 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2533 | |
| mbed_official | 237:f3da66175598 | 2534 | /* Check parameters */ |
| mbed_official | 237:f3da66175598 | 2535 | assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2536 | assert_param(IS_TIM_REMAP(Remap)); |
| mbed_official | 237:f3da66175598 | 2537 | |
| mbed_official | 237:f3da66175598 | 2538 | /* Set the Timer remapping configuration */ |
| mbed_official | 237:f3da66175598 | 2539 | htim->Instance->OR = Remap; |
| mbed_official | 237:f3da66175598 | 2540 | |
| mbed_official | 237:f3da66175598 | 2541 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2542 | |
| mbed_official | 237:f3da66175598 | 2543 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2544 | |
| mbed_official | 237:f3da66175598 | 2545 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2546 | } |
| mbed_official | 375:3d36234a1087 | 2547 | #endif /* STM32F302xE || */ |
| mbed_official | 375:3d36234a1087 | 2548 | /* STM32F302xC || */ |
| mbed_official | 237:f3da66175598 | 2549 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 2550 | /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| mbed_official | 375:3d36234a1087 | 2551 | /* STM32F373xC || STM32F378xx */ |
| mbed_official | 237:f3da66175598 | 2552 | |
| mbed_official | 237:f3da66175598 | 2553 | |
| mbed_official | 375:3d36234a1087 | 2554 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
| mbed_official | 237:f3da66175598 | 2555 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
| mbed_official | 375:3d36234a1087 | 2556 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| mbed_official | 375:3d36234a1087 | 2557 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| mbed_official | 237:f3da66175598 | 2558 | /** |
| mbed_official | 237:f3da66175598 | 2559 | * @brief Group channel 5 and channel 1, 2 or 3 |
| mbed_official | 237:f3da66175598 | 2560 | * @param htim: TIM handle. |
| mbed_official | 237:f3da66175598 | 2561 | * @param OCRef: specifies the reference signal(s) the OC5REF is combined with. |
| mbed_official | 237:f3da66175598 | 2562 | * This parameter can be any combination of the following values: |
| mbed_official | 237:f3da66175598 | 2563 | * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC |
| mbed_official | 237:f3da66175598 | 2564 | * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF |
| mbed_official | 237:f3da66175598 | 2565 | * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF |
| mbed_official | 237:f3da66175598 | 2566 | * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF |
| mbed_official | 237:f3da66175598 | 2567 | * @retval HAL status |
| mbed_official | 237:f3da66175598 | 2568 | */ |
| mbed_official | 237:f3da66175598 | 2569 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef) |
| mbed_official | 237:f3da66175598 | 2570 | { |
| mbed_official | 237:f3da66175598 | 2571 | /* Check parameters */ |
| mbed_official | 237:f3da66175598 | 2572 | assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); |
| mbed_official | 237:f3da66175598 | 2573 | assert_param(IS_TIM_GROUPCH5(OCRef)); |
| mbed_official | 237:f3da66175598 | 2574 | |
| mbed_official | 237:f3da66175598 | 2575 | /* Process Locked */ |
| mbed_official | 237:f3da66175598 | 2576 | __HAL_LOCK(htim); |
| mbed_official | 237:f3da66175598 | 2577 | |
| mbed_official | 237:f3da66175598 | 2578 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 237:f3da66175598 | 2579 | |
| mbed_official | 237:f3da66175598 | 2580 | /* Clear GC5Cx bit fields */ |
| mbed_official | 237:f3da66175598 | 2581 | htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); |
| mbed_official | 237:f3da66175598 | 2582 | |
| mbed_official | 237:f3da66175598 | 2583 | /* Set GC5Cx bit fields */ |
| mbed_official | 237:f3da66175598 | 2584 | htim->Instance->CCR5 |= OCRef; |
| mbed_official | 237:f3da66175598 | 2585 | |
| mbed_official | 237:f3da66175598 | 2586 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2587 | |
| mbed_official | 237:f3da66175598 | 2588 | __HAL_UNLOCK(htim); |
| mbed_official | 237:f3da66175598 | 2589 | |
| mbed_official | 237:f3da66175598 | 2590 | return HAL_OK; |
| mbed_official | 237:f3da66175598 | 2591 | } |
| mbed_official | 375:3d36234a1087 | 2592 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
| mbed_official | 237:f3da66175598 | 2593 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| mbed_official | 375:3d36234a1087 | 2594 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| mbed_official | 375:3d36234a1087 | 2595 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| mbed_official | 237:f3da66175598 | 2596 | |
| mbed_official | 237:f3da66175598 | 2597 | /** |
| mbed_official | 237:f3da66175598 | 2598 | * @} |
| mbed_official | 237:f3da66175598 | 2599 | */ |
| mbed_official | 237:f3da66175598 | 2600 | |
| mbed_official | 375:3d36234a1087 | 2601 | /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions |
| mbed_official | 375:3d36234a1087 | 2602 | * @brief Extended Callbacks functions |
| mbed_official | 237:f3da66175598 | 2603 | * |
| mbed_official | 237:f3da66175598 | 2604 | @verbatim |
| mbed_official | 237:f3da66175598 | 2605 | ============================================================================== |
| mbed_official | 375:3d36234a1087 | 2606 | ##### Extended Callbacks functions ##### |
| mbed_official | 237:f3da66175598 | 2607 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 2608 | [..] |
| mbed_official | 375:3d36234a1087 | 2609 | This section provides Extended TIM callback functions: |
| mbed_official | 237:f3da66175598 | 2610 | (+) Timer Commutation callback |
| mbed_official | 237:f3da66175598 | 2611 | (+) Timer Break callback |
| mbed_official | 237:f3da66175598 | 2612 | |
| mbed_official | 237:f3da66175598 | 2613 | @endverbatim |
| mbed_official | 237:f3da66175598 | 2614 | * @{ |
| mbed_official | 237:f3da66175598 | 2615 | */ |
| mbed_official | 237:f3da66175598 | 2616 | |
| mbed_official | 237:f3da66175598 | 2617 | /** |
| mbed_official | 237:f3da66175598 | 2618 | * @brief Hall commutation changed callback in non blocking mode |
| mbed_official | 237:f3da66175598 | 2619 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 2620 | * @retval None |
| mbed_official | 237:f3da66175598 | 2621 | */ |
| mbed_official | 237:f3da66175598 | 2622 | __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 2623 | { |
| mbed_official | 237:f3da66175598 | 2624 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 237:f3da66175598 | 2625 | the HAL_TIMEx_CommutationCallback could be implemented in the user file |
| mbed_official | 237:f3da66175598 | 2626 | */ |
| mbed_official | 237:f3da66175598 | 2627 | } |
| mbed_official | 237:f3da66175598 | 2628 | |
| mbed_official | 237:f3da66175598 | 2629 | /** |
| mbed_official | 237:f3da66175598 | 2630 | * @brief Hall Break detection callback in non blocking mode |
| mbed_official | 237:f3da66175598 | 2631 | * @param htim : TIM handle |
| mbed_official | 237:f3da66175598 | 2632 | * @retval None |
| mbed_official | 237:f3da66175598 | 2633 | */ |
| mbed_official | 237:f3da66175598 | 2634 | __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 2635 | { |
| mbed_official | 237:f3da66175598 | 2636 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 237:f3da66175598 | 2637 | the HAL_TIMEx_BreakCallback could be implemented in the user file |
| mbed_official | 237:f3da66175598 | 2638 | */ |
| mbed_official | 237:f3da66175598 | 2639 | } |
| mbed_official | 237:f3da66175598 | 2640 | |
| mbed_official | 237:f3da66175598 | 2641 | /** |
| mbed_official | 237:f3da66175598 | 2642 | * @} |
| mbed_official | 237:f3da66175598 | 2643 | */ |
| mbed_official | 237:f3da66175598 | 2644 | |
| mbed_official | 375:3d36234a1087 | 2645 | /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions |
| mbed_official | 375:3d36234a1087 | 2646 | * @brief Extended Peripheral State functions |
| mbed_official | 237:f3da66175598 | 2647 | * |
| mbed_official | 237:f3da66175598 | 2648 | @verbatim |
| mbed_official | 237:f3da66175598 | 2649 | ============================================================================== |
| mbed_official | 375:3d36234a1087 | 2650 | ##### Extended Peripheral State functions ##### |
| mbed_official | 237:f3da66175598 | 2651 | ============================================================================== |
| mbed_official | 237:f3da66175598 | 2652 | [..] |
| mbed_official | 237:f3da66175598 | 2653 | This subsection permit to get in run-time the status of the peripheral |
| mbed_official | 237:f3da66175598 | 2654 | and the data flow. |
| mbed_official | 237:f3da66175598 | 2655 | |
| mbed_official | 237:f3da66175598 | 2656 | @endverbatim |
| mbed_official | 237:f3da66175598 | 2657 | * @{ |
| mbed_official | 237:f3da66175598 | 2658 | */ |
| mbed_official | 237:f3da66175598 | 2659 | |
| mbed_official | 237:f3da66175598 | 2660 | /** |
| mbed_official | 237:f3da66175598 | 2661 | * @brief Return the TIM Hall Sensor interface state |
| mbed_official | 237:f3da66175598 | 2662 | * @param htim: TIM Hall Sensor handle |
| mbed_official | 237:f3da66175598 | 2663 | * @retval HAL state |
| mbed_official | 237:f3da66175598 | 2664 | */ |
| mbed_official | 237:f3da66175598 | 2665 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 237:f3da66175598 | 2666 | { |
| mbed_official | 237:f3da66175598 | 2667 | return htim->State; |
| mbed_official | 237:f3da66175598 | 2668 | } |
| mbed_official | 237:f3da66175598 | 2669 | |
| mbed_official | 237:f3da66175598 | 2670 | /** |
| mbed_official | 237:f3da66175598 | 2671 | * @} |
| mbed_official | 237:f3da66175598 | 2672 | */ |
| mbed_official | 237:f3da66175598 | 2673 | |
| mbed_official | 237:f3da66175598 | 2674 | /** |
| mbed_official | 237:f3da66175598 | 2675 | * @brief TIM DMA Commutation callback. |
| mbed_official | 237:f3da66175598 | 2676 | * @param hdma : pointer to DMA handle. |
| mbed_official | 237:f3da66175598 | 2677 | * @retval None |
| mbed_official | 237:f3da66175598 | 2678 | */ |
| mbed_official | 237:f3da66175598 | 2679 | void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 237:f3da66175598 | 2680 | { |
| mbed_official | 237:f3da66175598 | 2681 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 237:f3da66175598 | 2682 | |
| mbed_official | 237:f3da66175598 | 2683 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 237:f3da66175598 | 2684 | |
| mbed_official | 237:f3da66175598 | 2685 | HAL_TIMEx_CommutationCallback(htim); |
| mbed_official | 237:f3da66175598 | 2686 | } |
| mbed_official | 237:f3da66175598 | 2687 | |
| mbed_official | 237:f3da66175598 | 2688 | /** |
| mbed_official | 237:f3da66175598 | 2689 | * @brief Enables or disables the TIM Capture Compare Channel xN. |
| mbed_official | 237:f3da66175598 | 2690 | * @param TIMx to select the TIM peripheral |
| mbed_official | 237:f3da66175598 | 2691 | * @param Channel: specifies the TIM Channel |
| mbed_official | 237:f3da66175598 | 2692 | * This parameter can be one of the following values: |
| mbed_official | 237:f3da66175598 | 2693 | * @arg TIM_Channel_1: TIM Channel 1 |
| mbed_official | 237:f3da66175598 | 2694 | * @arg TIM_Channel_2: TIM Channel 2 |
| mbed_official | 237:f3da66175598 | 2695 | * @arg TIM_Channel_3: TIM Channel 3 |
| mbed_official | 237:f3da66175598 | 2696 | * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. |
| mbed_official | 237:f3da66175598 | 2697 | * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. |
| mbed_official | 237:f3da66175598 | 2698 | * @retval None |
| mbed_official | 237:f3da66175598 | 2699 | */ |
| mbed_official | 237:f3da66175598 | 2700 | static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) |
| mbed_official | 237:f3da66175598 | 2701 | { |
| mbed_official | 237:f3da66175598 | 2702 | uint32_t tmp = 0; |
| mbed_official | 237:f3da66175598 | 2703 | |
| mbed_official | 237:f3da66175598 | 2704 | tmp = TIM_CCER_CC1NE << Channel; |
| mbed_official | 237:f3da66175598 | 2705 | |
| mbed_official | 237:f3da66175598 | 2706 | /* Reset the CCxNE Bit */ |
| mbed_official | 237:f3da66175598 | 2707 | TIMx->CCER &= ~tmp; |
| mbed_official | 237:f3da66175598 | 2708 | |
| mbed_official | 237:f3da66175598 | 2709 | /* Set or reset the CCxNE Bit */ |
| mbed_official | 237:f3da66175598 | 2710 | TIMx->CCER |= (uint32_t)(ChannelNState << Channel); |
| mbed_official | 237:f3da66175598 | 2711 | } |
| mbed_official | 237:f3da66175598 | 2712 | |
| mbed_official | 237:f3da66175598 | 2713 | /** |
| mbed_official | 237:f3da66175598 | 2714 | * @} |
| mbed_official | 237:f3da66175598 | 2715 | */ |
| mbed_official | 237:f3da66175598 | 2716 | |
| mbed_official | 237:f3da66175598 | 2717 | #endif /* HAL_TIM_MODULE_ENABLED */ |
| mbed_official | 237:f3da66175598 | 2718 | /** |
| mbed_official | 237:f3da66175598 | 2719 | * @} |
| mbed_official | 237:f3da66175598 | 2720 | */ |
| mbed_official | 237:f3da66175598 | 2721 | |
| mbed_official | 237:f3da66175598 | 2722 | /** |
| mbed_official | 237:f3da66175598 | 2723 | * @} |
| mbed_official | 237:f3da66175598 | 2724 | */ |
| mbed_official | 237:f3da66175598 | 2725 | |
| mbed_official | 237:f3da66175598 | 2726 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
