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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c@632:7687fb9c4f91, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 14:00:11 2015 +0100
Revision:: 632:7687fb9c4f91
Parent:: 385:be64abf45658
Child:: 634:ac7d6880524d

Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0

Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/

NUCLEO_F303K8 - add support of the STM32F303K8

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	330:c80ac197fa6a	1	/**
mbed_official	330:c80ac197fa6a	2	******************************************************************************
mbed_official	330:c80ac197fa6a	3	* @file stm32f3xx_hal_spi.c
mbed_official	330:c80ac197fa6a	4	* @author MCD Application Team
mbed_official	632:7687fb9c4f91	5	* @version V1.1.1
mbed_official	632:7687fb9c4f91	6	* @date 19-June-2015
mbed_official	330:c80ac197fa6a	7	* @brief SPI HAL module driver.
mbed_official	330:c80ac197fa6a	8	*
mbed_official	330:c80ac197fa6a	9	* This file provides firmware functions to manage the following
mbed_official	330:c80ac197fa6a	10	* functionalities of the SPI peripheral:
mbed_official	330:c80ac197fa6a	11	* + Initialization/de-initialization functions
mbed_official	330:c80ac197fa6a	12	* + I/O operation functions
mbed_official	330:c80ac197fa6a	13	* + Peripheral Control functions
mbed_official	330:c80ac197fa6a	14	* + Peripheral State functions
mbed_official	330:c80ac197fa6a	15	*
mbed_official	330:c80ac197fa6a	16	@verbatim
mbed_official	330:c80ac197fa6a	17	===============================================================================
mbed_official	330:c80ac197fa6a	18	##### How to use this driver #####
mbed_official	330:c80ac197fa6a	19	===============================================================================
mbed_official	330:c80ac197fa6a	20	[..]
mbed_official	330:c80ac197fa6a	21	The SPI HAL driver can be used as follows:
mbed_official	330:c80ac197fa6a	22
mbed_official	330:c80ac197fa6a	23	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	330:c80ac197fa6a	24	SPI_HandleTypeDef hspi;
mbed_official	330:c80ac197fa6a	25
mbed_official	330:c80ac197fa6a	26	(#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official	330:c80ac197fa6a	27	(##) Enable the SPIx interface clock
mbed_official	330:c80ac197fa6a	28	(##) SPI pins configuration
mbed_official	330:c80ac197fa6a	29	(+) Enable the clock for the SPI GPIOs
mbed_official	330:c80ac197fa6a	30	(+) Configure these SPI pins as alternate function push-pull
mbed_official	330:c80ac197fa6a	31	(##) NVIC configuration if you need to use interrupt process
mbed_official	330:c80ac197fa6a	32	(+) Configure the SPIx interrupt priority
mbed_official	330:c80ac197fa6a	33	(+) Enable the NVIC SPI IRQ handle
mbed_official	330:c80ac197fa6a	34	(##) DMA Configuration if you need to use DMA process
mbed_official	330:c80ac197fa6a	35	(+) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
mbed_official	330:c80ac197fa6a	36	(+) Enable the DMAx interface clock using
mbed_official	330:c80ac197fa6a	37	(+) Configure the DMA handle parameters
mbed_official	330:c80ac197fa6a	38	(+) Configure the DMA Tx or Rx channel
mbed_official	330:c80ac197fa6a	39	(+) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	330:c80ac197fa6a	40	(+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
mbed_official	330:c80ac197fa6a	41
mbed_official	330:c80ac197fa6a	42	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official	330:c80ac197fa6a	43	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	330:c80ac197fa6a	44
mbed_official	330:c80ac197fa6a	45	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	330:c80ac197fa6a	46	(+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	330:c80ac197fa6a	47	by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official	330:c80ac197fa6a	48
mbed_official	330:c80ac197fa6a	49	[..]
mbed_official	330:c80ac197fa6a	50	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official	330:c80ac197fa6a	51	the following table resume the max SPI frequency reached with data size 8bits/16bits:
mbed_official	330:c80ac197fa6a	52	+-----------------------------------------------------------------------------------------+
mbed_official	330:c80ac197fa6a	53	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	330:c80ac197fa6a	54	\| Process \| Tranfert mode \|--------------------\|--------------------\|--------------------\|
mbed_official	330:c80ac197fa6a	55	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	330:c80ac197fa6a	56	\|=========================================================================================\|
mbed_official	330:c80ac197fa6a	57	\| T \| Polling \| Fcpu/4 \| Fcpu/8 \| NA \| NA \| NA \| NA \|
mbed_official	330:c80ac197fa6a	58	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	59	\| / \| Interrupt \| Fcpu/4 \| Fcpu/16 \| NA \| NA \| NA \| NA \|
mbed_official	330:c80ac197fa6a	60	\| R \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	61	\| X \| DMA \| Fcpu/2 \| Fcpu/2 \| NA \| NA \| NA \| NA \|
mbed_official	330:c80ac197fa6a	62	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	330:c80ac197fa6a	63	\| \| Polling \| Fcpu/4 \| Fcpu/8 \| Fcpu/16 \| Fcpu/8 \| Fcpu/8 \| Fcpu/8 \|
mbed_official	330:c80ac197fa6a	64	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	65	\| R \| Interrupt \| Fcpu/8 \| Fcpu/16 \| Fcpu/8 \| Fcpu/8 \| Fcpu/8 \| Fcpu/4 \|
mbed_official	330:c80ac197fa6a	66	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	67	\| \| DMA \| Fcpu/4 \| Fcpu/2 \| Fcpu/2 \| Fcpu/16 \| Fcpu/2 \| Fcpu/16 \|
mbed_official	330:c80ac197fa6a	68	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	330:c80ac197fa6a	69	\| \| Polling \| Fcpu/8 \| Fcpu/2 \| NA \| NA \| Fcpu/8 \| Fcpu/8 \|
mbed_official	330:c80ac197fa6a	70	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	71	\| T \| Interrupt \| Fcpu/2 \| Fcpu/4 \| NA \| NA \| Fcpu/16 \| Fcpu/8 \|
mbed_official	330:c80ac197fa6a	72	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	330:c80ac197fa6a	73	\| \| DMA \| Fcpu/2 \| Fcpu/2 \| NA \| NA \| Fcpu/8 \| Fcpu/16 \|
mbed_official	330:c80ac197fa6a	74	+-----------------------------------------------------------------------------------------+
mbed_official	330:c80ac197fa6a	75	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
mbed_official	330:c80ac197fa6a	76	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official	330:c80ac197fa6a	77	@note
mbed_official	330:c80ac197fa6a	78	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	330:c80ac197fa6a	79	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	330:c80ac197fa6a	80	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	330:c80ac197fa6a	81
mbed_official	330:c80ac197fa6a	82	@endverbatim
mbed_official	330:c80ac197fa6a	83	******************************************************************************
mbed_official	330:c80ac197fa6a	84	* @attention
mbed_official	330:c80ac197fa6a	85	*
mbed_official	632:7687fb9c4f91	86	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	330:c80ac197fa6a	87	*
mbed_official	330:c80ac197fa6a	88	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	330:c80ac197fa6a	89	* are permitted provided that the following conditions are met:
mbed_official	330:c80ac197fa6a	90	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	330:c80ac197fa6a	91	* this list of conditions and the following disclaimer.
mbed_official	330:c80ac197fa6a	92	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	330:c80ac197fa6a	93	* this list of conditions and the following disclaimer in the documentation
mbed_official	330:c80ac197fa6a	94	* and/or other materials provided with the distribution.
mbed_official	330:c80ac197fa6a	95	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	330:c80ac197fa6a	96	* may be used to endorse or promote products derived from this software
mbed_official	330:c80ac197fa6a	97	* without specific prior written permission.
mbed_official	330:c80ac197fa6a	98	*
mbed_official	330:c80ac197fa6a	99	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	330:c80ac197fa6a	100	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	330:c80ac197fa6a	101	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	330:c80ac197fa6a	102	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	330:c80ac197fa6a	103	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	330:c80ac197fa6a	104	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	330:c80ac197fa6a	105	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	330:c80ac197fa6a	106	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	330:c80ac197fa6a	107	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	330:c80ac197fa6a	108	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	330:c80ac197fa6a	109	*
mbed_official	330:c80ac197fa6a	110	******************************************************************************
mbed_official	330:c80ac197fa6a	111	*/
mbed_official	330:c80ac197fa6a	112
mbed_official	330:c80ac197fa6a	113	/* Includes ------------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	114	#include "stm32f3xx_hal.h"
mbed_official	330:c80ac197fa6a	115
mbed_official	330:c80ac197fa6a	116	/** @addtogroup STM32F3xx_HAL_Driver
mbed_official	330:c80ac197fa6a	117	* @{
mbed_official	330:c80ac197fa6a	118	*/
mbed_official	330:c80ac197fa6a	119
mbed_official	330:c80ac197fa6a	120	/** @defgroup SPI SPI HAL module driver
mbed_official	330:c80ac197fa6a	121	* @brief SPI HAL module driver
mbed_official	330:c80ac197fa6a	122	* @{
mbed_official	330:c80ac197fa6a	123	*/
mbed_official	330:c80ac197fa6a	124	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	330:c80ac197fa6a	125
mbed_official	330:c80ac197fa6a	126	/* Private typedef -----------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	127	/* Private define ------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	128	/** @defgroup SPI_Private_Define SPI Private Define
mbed_official	330:c80ac197fa6a	129	* @{
mbed_official	330:c80ac197fa6a	130	*/
mbed_official	330:c80ac197fa6a	131	#define SPI_DEFAULT_TIMEOUT 50
mbed_official	330:c80ac197fa6a	132	/**
mbed_official	330:c80ac197fa6a	133	* @}
mbed_official	330:c80ac197fa6a	134	*/
mbed_official	330:c80ac197fa6a	135
mbed_official	330:c80ac197fa6a	136	/* Private macro -------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	137	/* Private variables ---------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	138	/* Private function prototypes -----------------------------------------------*/
mbed_official	330:c80ac197fa6a	139	/** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official	330:c80ac197fa6a	140	* @{
mbed_official	330:c80ac197fa6a	141	*/
mbed_official	330:c80ac197fa6a	142
mbed_official	330:c80ac197fa6a	143	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	330:c80ac197fa6a	144	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	330:c80ac197fa6a	145	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	330:c80ac197fa6a	146	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	330:c80ac197fa6a	147	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official	330:c80ac197fa6a	148	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official	330:c80ac197fa6a	149	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	150	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	151	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	152	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	153	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	154	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	155	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	156	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	157	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	158	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	159	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	160	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	161	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	162	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	163	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	330:c80ac197fa6a	164	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official	330:c80ac197fa6a	165	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official	330:c80ac197fa6a	166	/**
mbed_official	330:c80ac197fa6a	167	* @}
mbed_official	330:c80ac197fa6a	168	*/
mbed_official	330:c80ac197fa6a	169
mbed_official	330:c80ac197fa6a	170	/* Exported functions ---------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	171
mbed_official	330:c80ac197fa6a	172	/** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official	330:c80ac197fa6a	173	* @{
mbed_official	330:c80ac197fa6a	174	*/
mbed_official	330:c80ac197fa6a	175
mbed_official	330:c80ac197fa6a	176	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official	330:c80ac197fa6a	177	* @brief Initialization and Configuration functions
mbed_official	330:c80ac197fa6a	178	*
mbed_official	330:c80ac197fa6a	179	@verbatim
mbed_official	330:c80ac197fa6a	180	===============================================================================
mbed_official	330:c80ac197fa6a	181	##### Initialization/de-initialization functions #####
mbed_official	330:c80ac197fa6a	182	===============================================================================
mbed_official	330:c80ac197fa6a	183	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	330:c80ac197fa6a	184	de-initialiaze the SPIx peripheral:
mbed_official	330:c80ac197fa6a	185
mbed_official	330:c80ac197fa6a	186	(+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official	330:c80ac197fa6a	187	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	330:c80ac197fa6a	188
mbed_official	330:c80ac197fa6a	189	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	330:c80ac197fa6a	190	the selected configuration:
mbed_official	330:c80ac197fa6a	191	(++) Mode
mbed_official	330:c80ac197fa6a	192	(++) Direction
mbed_official	330:c80ac197fa6a	193	(++) Data Size
mbed_official	330:c80ac197fa6a	194	(++) Clock Polarity and Phase
mbed_official	330:c80ac197fa6a	195	(++) NSS Management
mbed_official	330:c80ac197fa6a	196	(++) BaudRate Prescaler
mbed_official	330:c80ac197fa6a	197	(++) FirstBit
mbed_official	330:c80ac197fa6a	198	(++) TIMode
mbed_official	330:c80ac197fa6a	199	(++) CRC Calculation
mbed_official	330:c80ac197fa6a	200	(++) CRC Polynomial if CRC enabled
mbed_official	330:c80ac197fa6a	201	(++) CRC Length, used only with Data8 and Data16
mbed_official	330:c80ac197fa6a	202	(++) FIFO reception threshold
mbed_official	330:c80ac197fa6a	203
mbed_official	330:c80ac197fa6a	204	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	330:c80ac197fa6a	205	of the selected SPIx periperal.
mbed_official	330:c80ac197fa6a	206
mbed_official	330:c80ac197fa6a	207	@endverbatim
mbed_official	330:c80ac197fa6a	208	* @{
mbed_official	330:c80ac197fa6a	209	*/
mbed_official	330:c80ac197fa6a	210
mbed_official	330:c80ac197fa6a	211	/**
mbed_official	330:c80ac197fa6a	212	* @brief Initializes the SPI according to the specified parameters
mbed_official	330:c80ac197fa6a	213	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	330:c80ac197fa6a	214	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	215	* @retval HAL status
mbed_official	330:c80ac197fa6a	216	*/
mbed_official	330:c80ac197fa6a	217	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	218	{
mbed_official	330:c80ac197fa6a	219	uint32_t frxth;
mbed_official	330:c80ac197fa6a	220
mbed_official	330:c80ac197fa6a	221	/* Check the SPI handle allocation */
mbed_official	632:7687fb9c4f91	222	if(hspi == NULL)
mbed_official	330:c80ac197fa6a	223	{
mbed_official	330:c80ac197fa6a	224	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	225	}
mbed_official	330:c80ac197fa6a	226
mbed_official	330:c80ac197fa6a	227	/* Check the parameters */
mbed_official	330:c80ac197fa6a	228	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	330:c80ac197fa6a	229	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	330:c80ac197fa6a	230	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	231	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	330:c80ac197fa6a	232	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	330:c80ac197fa6a	233	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	330:c80ac197fa6a	234	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	330:c80ac197fa6a	235	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official	330:c80ac197fa6a	236	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	330:c80ac197fa6a	237	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	330:c80ac197fa6a	238	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	330:c80ac197fa6a	239	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	330:c80ac197fa6a	240	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	330:c80ac197fa6a	241	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official	330:c80ac197fa6a	242
mbed_official	330:c80ac197fa6a	243	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	330:c80ac197fa6a	244
mbed_official	330:c80ac197fa6a	245	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	330:c80ac197fa6a	246	HAL_SPI_MspInit(hspi);
mbed_official	330:c80ac197fa6a	247
mbed_official	330:c80ac197fa6a	248	/* Disable the selected SPI peripheral */
mbed_official	330:c80ac197fa6a	249	__HAL_SPI_DISABLE(hspi);
mbed_official	330:c80ac197fa6a	250
mbed_official	330:c80ac197fa6a	251	/* Align by default the rs fifo threshold on the data size */
mbed_official	330:c80ac197fa6a	252	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	253	{
mbed_official	330:c80ac197fa6a	254	frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official	330:c80ac197fa6a	255	}
mbed_official	330:c80ac197fa6a	256	else
mbed_official	330:c80ac197fa6a	257	{
mbed_official	330:c80ac197fa6a	258	frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official	330:c80ac197fa6a	259	}
mbed_official	330:c80ac197fa6a	260
mbed_official	330:c80ac197fa6a	261	/* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official	330:c80ac197fa6a	262	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official	330:c80ac197fa6a	263	{
mbed_official	330:c80ac197fa6a	264	/* CRC must be disabled */
mbed_official	330:c80ac197fa6a	265	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
mbed_official	330:c80ac197fa6a	266	}
mbed_official	330:c80ac197fa6a	267
mbed_official	330:c80ac197fa6a	268	/* Align the CRC Length on the data size */
mbed_official	330:c80ac197fa6a	269	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official	330:c80ac197fa6a	270	{
mbed_official	330:c80ac197fa6a	271	/* CRC Lengtht aligned on the data size : value set by default */
mbed_official	330:c80ac197fa6a	272	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	273	{
mbed_official	330:c80ac197fa6a	274	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official	330:c80ac197fa6a	275	}
mbed_official	330:c80ac197fa6a	276	else
mbed_official	330:c80ac197fa6a	277	{
mbed_official	330:c80ac197fa6a	278	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official	330:c80ac197fa6a	279	}
mbed_official	330:c80ac197fa6a	280	}
mbed_official	330:c80ac197fa6a	281
mbed_official	330:c80ac197fa6a	282	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
mbed_official	330:c80ac197fa6a	283	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official	330:c80ac197fa6a	284	Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official	330:c80ac197fa6a	285	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
mbed_official	330:c80ac197fa6a	286	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	330:c80ac197fa6a	287	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	330:c80ac197fa6a	288
mbed_official	330:c80ac197fa6a	289	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	330:c80ac197fa6a	290	{
mbed_official	330:c80ac197fa6a	291	hspi->Instance->CR1\|= SPI_CR1_CRCL;
mbed_official	330:c80ac197fa6a	292	}
mbed_official	330:c80ac197fa6a	293
mbed_official	330:c80ac197fa6a	294	/* Configure : NSS management */
mbed_official	330:c80ac197fa6a	295	/* Configure : Rx Fifo Threshold */
mbed_official	330:c80ac197fa6a	296	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
mbed_official	330:c80ac197fa6a	297	hspi->Init.DataSize ) \| frxth;
mbed_official	330:c80ac197fa6a	298
mbed_official	330:c80ac197fa6a	299	/---------------------------- SPIx CRCPOLY Configuration --------------------/
mbed_official	330:c80ac197fa6a	300	/* Configure : CRC Polynomial */
mbed_official	330:c80ac197fa6a	301	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	330:c80ac197fa6a	302
mbed_official	330:c80ac197fa6a	303	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	304	hspi->State= HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	305
mbed_official	330:c80ac197fa6a	306	return HAL_OK;
mbed_official	330:c80ac197fa6a	307	}
mbed_official	330:c80ac197fa6a	308
mbed_official	330:c80ac197fa6a	309	/**
mbed_official	330:c80ac197fa6a	310	* @brief DeInitializes the SPI peripheral
mbed_official	330:c80ac197fa6a	311	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	312	* @retval HAL status
mbed_official	330:c80ac197fa6a	313	*/
mbed_official	330:c80ac197fa6a	314	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	315	{
mbed_official	330:c80ac197fa6a	316	/* Check the SPI handle allocation */
mbed_official	632:7687fb9c4f91	317	if(hspi == NULL)
mbed_official	330:c80ac197fa6a	318	{
mbed_official	330:c80ac197fa6a	319	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	320	}
mbed_official	330:c80ac197fa6a	321
mbed_official	330:c80ac197fa6a	322	/* Check the parameters */
mbed_official	330:c80ac197fa6a	323	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	330:c80ac197fa6a	324
mbed_official	330:c80ac197fa6a	325	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	330:c80ac197fa6a	326
mbed_official	330:c80ac197fa6a	327	/* Disable the SPI Peripheral Clock */
mbed_official	330:c80ac197fa6a	328	__HAL_SPI_DISABLE(hspi);
mbed_official	330:c80ac197fa6a	329
mbed_official	330:c80ac197fa6a	330	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	330:c80ac197fa6a	331	HAL_SPI_MspDeInit(hspi);
mbed_official	330:c80ac197fa6a	332
mbed_official	330:c80ac197fa6a	333	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	334	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	330:c80ac197fa6a	335
mbed_official	330:c80ac197fa6a	336	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	337
mbed_official	330:c80ac197fa6a	338	return HAL_OK;
mbed_official	330:c80ac197fa6a	339	}
mbed_official	330:c80ac197fa6a	340
mbed_official	330:c80ac197fa6a	341	/**
mbed_official	330:c80ac197fa6a	342	* @brief SPI MSP Init
mbed_official	330:c80ac197fa6a	343	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	344	* @retval None
mbed_official	330:c80ac197fa6a	345	*/
mbed_official	330:c80ac197fa6a	346	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	347	{
mbed_official	330:c80ac197fa6a	348	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	349	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	330:c80ac197fa6a	350	*/
mbed_official	330:c80ac197fa6a	351	}
mbed_official	330:c80ac197fa6a	352
mbed_official	330:c80ac197fa6a	353	/**
mbed_official	330:c80ac197fa6a	354	* @brief SPI MSP DeInit
mbed_official	330:c80ac197fa6a	355	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	356	* @retval None
mbed_official	330:c80ac197fa6a	357	*/
mbed_official	330:c80ac197fa6a	358	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	359	{
mbed_official	330:c80ac197fa6a	360	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	361	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	330:c80ac197fa6a	362	*/
mbed_official	330:c80ac197fa6a	363	}
mbed_official	330:c80ac197fa6a	364
mbed_official	330:c80ac197fa6a	365	/**
mbed_official	330:c80ac197fa6a	366	* @}
mbed_official	330:c80ac197fa6a	367	*/
mbed_official	330:c80ac197fa6a	368
mbed_official	330:c80ac197fa6a	369	/** @defgroup SPI_Exported_Functions_Group2 Input and Output operation functions
mbed_official	330:c80ac197fa6a	370	* @brief Data transfers functions
mbed_official	330:c80ac197fa6a	371	*
mbed_official	330:c80ac197fa6a	372	@verbatim
mbed_official	330:c80ac197fa6a	373	===============================================================================
mbed_official	330:c80ac197fa6a	374	##### I/O operation functions #####
mbed_official	330:c80ac197fa6a	375	===============================================================================
mbed_official	330:c80ac197fa6a	376	This subsection provides a set of functions allowing to manage the SPI
mbed_official	330:c80ac197fa6a	377	data transfers.
mbed_official	330:c80ac197fa6a	378
mbed_official	330:c80ac197fa6a	379	[..] The SPI supports master and slave mode :
mbed_official	330:c80ac197fa6a	380
mbed_official	330:c80ac197fa6a	381	(#) There are two mode of transfer:
mbed_official	330:c80ac197fa6a	382	(+) Blocking mode: The communication is performed in polling mode.
mbed_official	330:c80ac197fa6a	383	The HAL status of all data processing is returned by the same function
mbed_official	330:c80ac197fa6a	384	after finishing transfer.
mbed_official	330:c80ac197fa6a	385	(+) No-Blocking mode: The communication is performed using Interrupts
mbed_official	330:c80ac197fa6a	386	or DMA, These API's return the HAL status.
mbed_official	330:c80ac197fa6a	387	The end of the data processing will be indicated through the
mbed_official	330:c80ac197fa6a	388	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	330:c80ac197fa6a	389	using DMA mode.
mbed_official	330:c80ac197fa6a	390	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	330:c80ac197fa6a	391	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	330:c80ac197fa6a	392	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	330:c80ac197fa6a	393
mbed_official	330:c80ac197fa6a	394	(#) Blocking mode API's are :
mbed_official	330:c80ac197fa6a	395	(+) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	396	(+) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	397	(+) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	330:c80ac197fa6a	398
mbed_official	330:c80ac197fa6a	399	(#) Non-Blocking mode API's with Interrupt are :
mbed_official	330:c80ac197fa6a	400	(+) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	401	(+) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	402	(+) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	330:c80ac197fa6a	403	(+) HAL_SPI_IRQHandler()
mbed_official	330:c80ac197fa6a	404
mbed_official	330:c80ac197fa6a	405	(#) No-Blocking mode functions with DMA are :
mbed_official	330:c80ac197fa6a	406	(+) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	407	(+) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	330:c80ac197fa6a	408	(+) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	330:c80ac197fa6a	409
mbed_official	330:c80ac197fa6a	410	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official	330:c80ac197fa6a	411	(+) HAL_SPI_TxCpltCallback()
mbed_official	330:c80ac197fa6a	412	(+) HAL_SPI_RxCpltCallback()
mbed_official	330:c80ac197fa6a	413	(+) HAL_SPI_ErrorCallback()
mbed_official	330:c80ac197fa6a	414	(+) HAL_SPI_TxRxCpltCallback()
mbed_official	330:c80ac197fa6a	415
mbed_official	330:c80ac197fa6a	416	@endverbatim
mbed_official	330:c80ac197fa6a	417	* @{
mbed_official	330:c80ac197fa6a	418	*/
mbed_official	330:c80ac197fa6a	419
mbed_official	330:c80ac197fa6a	420	/**
mbed_official	330:c80ac197fa6a	421	* @brief Transmit an amount of data in blocking mode
mbed_official	330:c80ac197fa6a	422	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	423	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	424	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	425	* @param Timeout: Timeout duration
mbed_official	330:c80ac197fa6a	426	* @retval HAL status
mbed_official	330:c80ac197fa6a	427	*/
mbed_official	330:c80ac197fa6a	428	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	429	{
mbed_official	330:c80ac197fa6a	430	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	431
mbed_official	330:c80ac197fa6a	432	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	433	{
mbed_official	330:c80ac197fa6a	434	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	435	}
mbed_official	330:c80ac197fa6a	436
mbed_official	632:7687fb9c4f91	437	if((pData == NULL ) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	438	{
mbed_official	330:c80ac197fa6a	439	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	440	}
mbed_official	330:c80ac197fa6a	441
mbed_official	330:c80ac197fa6a	442	/* Process Locked */
mbed_official	330:c80ac197fa6a	443	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	444
mbed_official	330:c80ac197fa6a	445	/* Set the transaction information */
mbed_official	330:c80ac197fa6a	446	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	330:c80ac197fa6a	447	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	448	hspi->pTxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	449	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	450	hspi->TxXferCount = Size;
mbed_official	632:7687fb9c4f91	451	hspi->pRxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	452	hspi->RxXferSize = 0;
mbed_official	330:c80ac197fa6a	453	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	454
mbed_official	330:c80ac197fa6a	455	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	456	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	457	{
mbed_official	330:c80ac197fa6a	458	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	459	}
mbed_official	330:c80ac197fa6a	460
mbed_official	330:c80ac197fa6a	461	/* Configure communication direction : 1Line */
mbed_official	330:c80ac197fa6a	462	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	463	{
mbed_official	330:c80ac197fa6a	464	__HAL_SPI_1LINE_TX(hspi);
mbed_official	330:c80ac197fa6a	465	}
mbed_official	330:c80ac197fa6a	466
mbed_official	330:c80ac197fa6a	467	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	468	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	469	{
mbed_official	330:c80ac197fa6a	470	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	471	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	472	}
mbed_official	330:c80ac197fa6a	473
mbed_official	330:c80ac197fa6a	474	/* Transmit data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	475	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	476	{
mbed_official	330:c80ac197fa6a	477	while (hspi->TxXferCount > 0)
mbed_official	330:c80ac197fa6a	478	{
mbed_official	330:c80ac197fa6a	479	/* Wait until TXE flag is set to send data */
mbed_official	330:c80ac197fa6a	480	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	481	{
mbed_official	330:c80ac197fa6a	482	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	483	}
mbed_official	330:c80ac197fa6a	484	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	485	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	486	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	487	}
mbed_official	330:c80ac197fa6a	488	}
mbed_official	330:c80ac197fa6a	489	/* Transmit data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	490	else
mbed_official	330:c80ac197fa6a	491	{
mbed_official	330:c80ac197fa6a	492	while (hspi->TxXferCount > 0)
mbed_official	330:c80ac197fa6a	493	{
mbed_official	330:c80ac197fa6a	494	if(hspi->TxXferCount != 0x1)
mbed_official	330:c80ac197fa6a	495	{
mbed_official	330:c80ac197fa6a	496	/* Wait until TXE flag is set to send data */
mbed_official	330:c80ac197fa6a	497	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	498	{
mbed_official	330:c80ac197fa6a	499	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	500	}
mbed_official	330:c80ac197fa6a	501	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	502	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	503	hspi->TxXferCount -= 2;
mbed_official	330:c80ac197fa6a	504	}
mbed_official	330:c80ac197fa6a	505	else
mbed_official	330:c80ac197fa6a	506	{
mbed_official	330:c80ac197fa6a	507	/* Wait until TXE flag is set to send data */
mbed_official	330:c80ac197fa6a	508	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	509	{
mbed_official	330:c80ac197fa6a	510	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	511	}
mbed_official	330:c80ac197fa6a	512	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official	330:c80ac197fa6a	513	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	514	}
mbed_official	330:c80ac197fa6a	515	}
mbed_official	330:c80ac197fa6a	516	}
mbed_official	330:c80ac197fa6a	517
mbed_official	330:c80ac197fa6a	518	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	519	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	520	{
mbed_official	330:c80ac197fa6a	521	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	522	}
mbed_official	330:c80ac197fa6a	523
mbed_official	330:c80ac197fa6a	524	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	525	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	526	{
mbed_official	330:c80ac197fa6a	527	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	528	}
mbed_official	330:c80ac197fa6a	529
mbed_official	330:c80ac197fa6a	530	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	330:c80ac197fa6a	531	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	330:c80ac197fa6a	532	{
mbed_official	330:c80ac197fa6a	533	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	330:c80ac197fa6a	534	}
mbed_official	330:c80ac197fa6a	535
mbed_official	330:c80ac197fa6a	536	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	537
mbed_official	330:c80ac197fa6a	538	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	539	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	540
mbed_official	330:c80ac197fa6a	541	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	542	{
mbed_official	330:c80ac197fa6a	543	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	544	}
mbed_official	330:c80ac197fa6a	545	else
mbed_official	330:c80ac197fa6a	546	{
mbed_official	330:c80ac197fa6a	547	return HAL_OK;
mbed_official	330:c80ac197fa6a	548	}
mbed_official	330:c80ac197fa6a	549	}
mbed_official	330:c80ac197fa6a	550
mbed_official	330:c80ac197fa6a	551	/**
mbed_official	330:c80ac197fa6a	552	* @brief Receive an amount of data in blocking mode
mbed_official	330:c80ac197fa6a	553	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	554	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	555	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	556	* @param Timeout: Timeout duration
mbed_official	330:c80ac197fa6a	557	* @retval HAL status
mbed_official	330:c80ac197fa6a	558	*/
mbed_official	330:c80ac197fa6a	559	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	560	{
mbed_official	330:c80ac197fa6a	561	__IO uint16_t tmpreg;
mbed_official	330:c80ac197fa6a	562
mbed_official	330:c80ac197fa6a	563	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	564	{
mbed_official	330:c80ac197fa6a	565	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	566	}
mbed_official	330:c80ac197fa6a	567
mbed_official	632:7687fb9c4f91	568	if((pData == NULL ) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	569	{
mbed_official	330:c80ac197fa6a	570	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	571	}
mbed_official	330:c80ac197fa6a	572
mbed_official	330:c80ac197fa6a	573	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	330:c80ac197fa6a	574	{
mbed_official	330:c80ac197fa6a	575	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	330:c80ac197fa6a	576	/* in this case we call the transmitReceive process */
mbed_official	330:c80ac197fa6a	577	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official	330:c80ac197fa6a	578	}
mbed_official	330:c80ac197fa6a	579
mbed_official	330:c80ac197fa6a	580	/* Process Locked */
mbed_official	330:c80ac197fa6a	581	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	582
mbed_official	330:c80ac197fa6a	583	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	330:c80ac197fa6a	584	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	585	hspi->pRxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	586	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	587	hspi->RxXferCount = Size;
mbed_official	632:7687fb9c4f91	588	hspi->pTxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	589	hspi->TxXferSize = 0;
mbed_official	330:c80ac197fa6a	590	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	591
mbed_official	330:c80ac197fa6a	592	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	593	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	594	{
mbed_official	330:c80ac197fa6a	595	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	596	}
mbed_official	330:c80ac197fa6a	597
mbed_official	330:c80ac197fa6a	598	/* Set the Rx Fido thresold */
mbed_official	330:c80ac197fa6a	599	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	600	{
mbed_official	330:c80ac197fa6a	601	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	330:c80ac197fa6a	602	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	603	}
mbed_official	330:c80ac197fa6a	604	else
mbed_official	330:c80ac197fa6a	605	{
mbed_official	330:c80ac197fa6a	606	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	330:c80ac197fa6a	607	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	608	}
mbed_official	330:c80ac197fa6a	609
mbed_official	330:c80ac197fa6a	610	/* Configure communication direction 1Line and enabled SPI if needed */
mbed_official	330:c80ac197fa6a	611	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	612	{
mbed_official	330:c80ac197fa6a	613	__HAL_SPI_1LINE_RX(hspi);
mbed_official	330:c80ac197fa6a	614	}
mbed_official	330:c80ac197fa6a	615
mbed_official	330:c80ac197fa6a	616	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	617	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	618	{
mbed_official	330:c80ac197fa6a	619	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	620	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	621	}
mbed_official	330:c80ac197fa6a	622
mbed_official	330:c80ac197fa6a	623	/* Receive data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	624	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	625	{
mbed_official	330:c80ac197fa6a	626	while(hspi->RxXferCount > 1)
mbed_official	330:c80ac197fa6a	627	{
mbed_official	330:c80ac197fa6a	628	/* Wait until the RXNE flag */
mbed_official	330:c80ac197fa6a	629	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	630	{
mbed_official	330:c80ac197fa6a	631	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	632	}
mbed_official	330:c80ac197fa6a	633	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	634	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	635	}
mbed_official	330:c80ac197fa6a	636	}
mbed_official	330:c80ac197fa6a	637	else /* Receive data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	638	{
mbed_official	330:c80ac197fa6a	639	while(hspi->RxXferCount > 1 )
mbed_official	330:c80ac197fa6a	640	{
mbed_official	330:c80ac197fa6a	641	/* Wait until RXNE flag is reset to read data */
mbed_official	330:c80ac197fa6a	642	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	643	{
mbed_official	330:c80ac197fa6a	644	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	645	}
mbed_official	330:c80ac197fa6a	646	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	647	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	648	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	649	}
mbed_official	330:c80ac197fa6a	650	}
mbed_official	330:c80ac197fa6a	651
mbed_official	330:c80ac197fa6a	652	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	653	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	654	{
mbed_official	330:c80ac197fa6a	655	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	656	}
mbed_official	330:c80ac197fa6a	657
mbed_official	330:c80ac197fa6a	658	/* Wait until RXNE flag is set */
mbed_official	330:c80ac197fa6a	659	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	660	{
mbed_official	330:c80ac197fa6a	661	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	662	}
mbed_official	330:c80ac197fa6a	663
mbed_official	330:c80ac197fa6a	664	/* Receive last data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	665	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	666	{
mbed_official	330:c80ac197fa6a	667	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	668	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	669	}
mbed_official	330:c80ac197fa6a	670	/* Receive last data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	671	else
mbed_official	330:c80ac197fa6a	672	{
mbed_official	330:c80ac197fa6a	673	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	674	}
mbed_official	330:c80ac197fa6a	675	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	676
mbed_official	330:c80ac197fa6a	677	/* Read CRC from DR to close CRC calculation process */
mbed_official	330:c80ac197fa6a	678	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	679	{
mbed_official	330:c80ac197fa6a	680	/* Wait until TXE flag */
mbed_official	330:c80ac197fa6a	681	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	682	{
mbed_official	330:c80ac197fa6a	683	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	684	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	685	}
mbed_official	330:c80ac197fa6a	686	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	687	{
mbed_official	330:c80ac197fa6a	688	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	689	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	690	}
mbed_official	330:c80ac197fa6a	691	else
mbed_official	330:c80ac197fa6a	692	{
mbed_official	330:c80ac197fa6a	693	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	694	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	632:7687fb9c4f91	695
mbed_official	330:c80ac197fa6a	696	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	330:c80ac197fa6a	697	{
mbed_official	330:c80ac197fa6a	698	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	699	{
mbed_official	330:c80ac197fa6a	700	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	701	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	702	}
mbed_official	330:c80ac197fa6a	703	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	704	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	705	}
mbed_official	330:c80ac197fa6a	706	}
mbed_official	330:c80ac197fa6a	707	}
mbed_official	330:c80ac197fa6a	708
mbed_official	330:c80ac197fa6a	709	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	710	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	711	{
mbed_official	330:c80ac197fa6a	712	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	713	}
mbed_official	330:c80ac197fa6a	714
mbed_official	330:c80ac197fa6a	715	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	716
mbed_official	330:c80ac197fa6a	717	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	718	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	719	{
mbed_official	330:c80ac197fa6a	720	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	721	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	722
mbed_official	330:c80ac197fa6a	723	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	724	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	725	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	726	}
mbed_official	330:c80ac197fa6a	727
mbed_official	330:c80ac197fa6a	728	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	729	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	730
mbed_official	330:c80ac197fa6a	731	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	732	{
mbed_official	330:c80ac197fa6a	733	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	734	}
mbed_official	330:c80ac197fa6a	735	else
mbed_official	330:c80ac197fa6a	736	{
mbed_official	330:c80ac197fa6a	737	return HAL_OK;
mbed_official	330:c80ac197fa6a	738	}
mbed_official	330:c80ac197fa6a	739	}
mbed_official	330:c80ac197fa6a	740
mbed_official	330:c80ac197fa6a	741	/**
mbed_official	330:c80ac197fa6a	742	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	330:c80ac197fa6a	743	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	744	* @param pTxData: pointer to transmission data buffer
mbed_official	330:c80ac197fa6a	745	* @param pRxData: pointer to reception data buffer to be
mbed_official	330:c80ac197fa6a	746	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	747	* @param Timeout: Timeout duration
mbed_official	330:c80ac197fa6a	748	* @retval HAL status
mbed_official	330:c80ac197fa6a	749	*/
mbed_official	330:c80ac197fa6a	750	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	751	{
mbed_official	330:c80ac197fa6a	752	__IO uint16_t tmpreg = 0;
mbed_official	330:c80ac197fa6a	753	uint32_t tickstart = 0;
mbed_official	330:c80ac197fa6a	754
mbed_official	330:c80ac197fa6a	755	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	756
mbed_official	330:c80ac197fa6a	757	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	758	{
mbed_official	330:c80ac197fa6a	759	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	760	}
mbed_official	330:c80ac197fa6a	761
mbed_official	632:7687fb9c4f91	762	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	763	{
mbed_official	330:c80ac197fa6a	764	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	765	}
mbed_official	330:c80ac197fa6a	766
mbed_official	330:c80ac197fa6a	767	tickstart = HAL_GetTick();
mbed_official	330:c80ac197fa6a	768
mbed_official	330:c80ac197fa6a	769	/* Process Locked */
mbed_official	330:c80ac197fa6a	770	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	771
mbed_official	330:c80ac197fa6a	772	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	330:c80ac197fa6a	773	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	774	hspi->pRxBuffPtr = pRxData;
mbed_official	330:c80ac197fa6a	775	hspi->RxXferCount = Size;
mbed_official	330:c80ac197fa6a	776	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	777	hspi->pTxBuffPtr = pTxData;
mbed_official	330:c80ac197fa6a	778	hspi->TxXferCount = Size;
mbed_official	330:c80ac197fa6a	779	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	780
mbed_official	330:c80ac197fa6a	781	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	782	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	783	{
mbed_official	330:c80ac197fa6a	784	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	785	}
mbed_official	330:c80ac197fa6a	786
mbed_official	330:c80ac197fa6a	787	/* Set the Rx Fido threshold */
mbed_official	330:c80ac197fa6a	788	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
mbed_official	330:c80ac197fa6a	789	{
mbed_official	330:c80ac197fa6a	790	/* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official	330:c80ac197fa6a	791	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	792	}
mbed_official	330:c80ac197fa6a	793	else
mbed_official	330:c80ac197fa6a	794	{
mbed_official	330:c80ac197fa6a	795	/* set fiforxthreshold according the reception data lenght: 8bit */
mbed_official	330:c80ac197fa6a	796	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	797	}
mbed_official	330:c80ac197fa6a	798
mbed_official	330:c80ac197fa6a	799	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	800	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	801	{
mbed_official	330:c80ac197fa6a	802	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	803	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	804	}
mbed_official	330:c80ac197fa6a	805
mbed_official	330:c80ac197fa6a	806	/* Transmit and Receive data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	807	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	808	{
mbed_official	330:c80ac197fa6a	809	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
mbed_official	330:c80ac197fa6a	810	{
mbed_official	330:c80ac197fa6a	811	/* Wait until TXE flag */
mbed_official	330:c80ac197fa6a	812	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official	330:c80ac197fa6a	813	{
mbed_official	330:c80ac197fa6a	814	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	815	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	816	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	817
mbed_official	330:c80ac197fa6a	818	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	819	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	330:c80ac197fa6a	820	{
mbed_official	330:c80ac197fa6a	821	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	330:c80ac197fa6a	822	}
mbed_official	330:c80ac197fa6a	823	}
mbed_official	330:c80ac197fa6a	824
mbed_official	330:c80ac197fa6a	825	/* Wait until RXNE flag */
mbed_official	330:c80ac197fa6a	826	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official	330:c80ac197fa6a	827	{
mbed_official	330:c80ac197fa6a	828	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	829	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	830	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	831	}
mbed_official	330:c80ac197fa6a	832	if(Timeout != HAL_MAX_DELAY)
mbed_official	330:c80ac197fa6a	833	{
mbed_official	330:c80ac197fa6a	834	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
mbed_official	330:c80ac197fa6a	835	{
mbed_official	330:c80ac197fa6a	836	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	837	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	838	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	839	}
mbed_official	330:c80ac197fa6a	840	}
mbed_official	330:c80ac197fa6a	841	}
mbed_official	330:c80ac197fa6a	842	}
mbed_official	330:c80ac197fa6a	843	/* Transmit and Receive data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	844	else
mbed_official	330:c80ac197fa6a	845	{
mbed_official	330:c80ac197fa6a	846	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
mbed_official	330:c80ac197fa6a	847	{
mbed_official	330:c80ac197fa6a	848	/* check if TXE flag is set to send data */
mbed_official	330:c80ac197fa6a	849	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official	330:c80ac197fa6a	850	{
mbed_official	330:c80ac197fa6a	851	if(hspi->TxXferCount > 2)
mbed_official	330:c80ac197fa6a	852	{
mbed_official	330:c80ac197fa6a	853	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	854	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	855	hspi->TxXferCount -= 2;
mbed_official	330:c80ac197fa6a	856	}
mbed_official	330:c80ac197fa6a	857	else
mbed_official	330:c80ac197fa6a	858	{
mbed_official	330:c80ac197fa6a	859	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	330:c80ac197fa6a	860	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	861	}
mbed_official	330:c80ac197fa6a	862
mbed_official	330:c80ac197fa6a	863	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	864	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	330:c80ac197fa6a	865	{
mbed_official	330:c80ac197fa6a	866	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	330:c80ac197fa6a	867	}
mbed_official	330:c80ac197fa6a	868	}
mbed_official	330:c80ac197fa6a	869
mbed_official	330:c80ac197fa6a	870	/* Wait until RXNE flag is reset */
mbed_official	330:c80ac197fa6a	871	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official	330:c80ac197fa6a	872	{
mbed_official	330:c80ac197fa6a	873	if(hspi->RxXferCount > 1)
mbed_official	330:c80ac197fa6a	874	{
mbed_official	330:c80ac197fa6a	875	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	876	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	877	hspi->RxXferCount -= 2;
mbed_official	330:c80ac197fa6a	878	if(hspi->RxXferCount <= 1)
mbed_official	330:c80ac197fa6a	879	{
mbed_official	330:c80ac197fa6a	880	/* set fiforxthresold before to switch on 8 bit data size */
mbed_official	330:c80ac197fa6a	881	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	882	}
mbed_official	330:c80ac197fa6a	883	}
mbed_official	330:c80ac197fa6a	884	else
mbed_official	330:c80ac197fa6a	885	{
mbed_official	330:c80ac197fa6a	886	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	887	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	888	}
mbed_official	330:c80ac197fa6a	889	}
mbed_official	330:c80ac197fa6a	890	if(Timeout != HAL_MAX_DELAY)
mbed_official	330:c80ac197fa6a	891	{
mbed_official	330:c80ac197fa6a	892	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
mbed_official	330:c80ac197fa6a	893	{
mbed_official	330:c80ac197fa6a	894	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	895	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	896	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	897	}
mbed_official	330:c80ac197fa6a	898	}
mbed_official	330:c80ac197fa6a	899	}
mbed_official	330:c80ac197fa6a	900	}
mbed_official	330:c80ac197fa6a	901
mbed_official	330:c80ac197fa6a	902	/* Read CRC from DR to close CRC calculation process */
mbed_official	330:c80ac197fa6a	903	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	904	{
mbed_official	330:c80ac197fa6a	905	/* Wait until TXE flag */
mbed_official	330:c80ac197fa6a	906	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	907	{
mbed_official	330:c80ac197fa6a	908	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	909	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	910	}
mbed_official	330:c80ac197fa6a	911
mbed_official	330:c80ac197fa6a	912	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	330:c80ac197fa6a	913	{
mbed_official	330:c80ac197fa6a	914	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	915	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	916	}
mbed_official	330:c80ac197fa6a	917	else
mbed_official	330:c80ac197fa6a	918	{
mbed_official	330:c80ac197fa6a	919	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	920	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	632:7687fb9c4f91	921
mbed_official	330:c80ac197fa6a	922	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	330:c80ac197fa6a	923	{
mbed_official	330:c80ac197fa6a	924	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	925	{
mbed_official	330:c80ac197fa6a	926	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	927	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	928	}
mbed_official	330:c80ac197fa6a	929	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	930	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	931	}
mbed_official	330:c80ac197fa6a	932	}
mbed_official	330:c80ac197fa6a	933	}
mbed_official	330:c80ac197fa6a	934
mbed_official	330:c80ac197fa6a	935	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	936	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	937	{
mbed_official	330:c80ac197fa6a	938	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	939	}
mbed_official	330:c80ac197fa6a	940
mbed_official	330:c80ac197fa6a	941	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	942
mbed_official	330:c80ac197fa6a	943	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	944	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	945	{
mbed_official	330:c80ac197fa6a	946	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	947	/* Clear CRC Flag */
mbed_official	330:c80ac197fa6a	948	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	949
mbed_official	330:c80ac197fa6a	950	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	951	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	952
mbed_official	330:c80ac197fa6a	953	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	954	}
mbed_official	330:c80ac197fa6a	955
mbed_official	330:c80ac197fa6a	956	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	957	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	958
mbed_official	330:c80ac197fa6a	959	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	960	{
mbed_official	330:c80ac197fa6a	961	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	962	}
mbed_official	330:c80ac197fa6a	963	else
mbed_official	330:c80ac197fa6a	964	{
mbed_official	330:c80ac197fa6a	965	return HAL_OK;
mbed_official	330:c80ac197fa6a	966	}
mbed_official	330:c80ac197fa6a	967	}
mbed_official	330:c80ac197fa6a	968
mbed_official	330:c80ac197fa6a	969	/**
mbed_official	330:c80ac197fa6a	970	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	330:c80ac197fa6a	971	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	972	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	973	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	974	* @retval HAL status
mbed_official	330:c80ac197fa6a	975	*/
mbed_official	330:c80ac197fa6a	976	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	330:c80ac197fa6a	977	{
mbed_official	330:c80ac197fa6a	978	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	979
mbed_official	330:c80ac197fa6a	980	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	981	{
mbed_official	632:7687fb9c4f91	982	if((pData == NULL) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	983	{
mbed_official	330:c80ac197fa6a	984	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	985	}
mbed_official	330:c80ac197fa6a	986
mbed_official	330:c80ac197fa6a	987	/* Process Locked */
mbed_official	330:c80ac197fa6a	988	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	989
mbed_official	330:c80ac197fa6a	990	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	330:c80ac197fa6a	991	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	992	hspi->pTxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	993	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	994	hspi->TxXferCount = Size;
mbed_official	632:7687fb9c4f91	995	hspi->pRxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	996	hspi->RxXferSize = 0;
mbed_official	330:c80ac197fa6a	997	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	998
mbed_official	330:c80ac197fa6a	999	/* Set the function for IT treatement */
mbed_official	330:c80ac197fa6a	1000	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	330:c80ac197fa6a	1001	{
mbed_official	632:7687fb9c4f91	1002	hspi->RxISR = NULL;
mbed_official	330:c80ac197fa6a	1003	hspi->TxISR = SPI_TxISR_16BIT;
mbed_official	330:c80ac197fa6a	1004	}
mbed_official	330:c80ac197fa6a	1005	else
mbed_official	330:c80ac197fa6a	1006	{
mbed_official	632:7687fb9c4f91	1007	hspi->RxISR = NULL;
mbed_official	330:c80ac197fa6a	1008	hspi->TxISR = SPI_TxISR_8BIT;
mbed_official	330:c80ac197fa6a	1009	}
mbed_official	330:c80ac197fa6a	1010
mbed_official	330:c80ac197fa6a	1011	/* Configure communication direction : 1Line */
mbed_official	330:c80ac197fa6a	1012	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	1013	{
mbed_official	330:c80ac197fa6a	1014	__HAL_SPI_1LINE_TX(hspi);
mbed_official	330:c80ac197fa6a	1015	}
mbed_official	330:c80ac197fa6a	1016
mbed_official	330:c80ac197fa6a	1017	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	1018	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1019	{
mbed_official	330:c80ac197fa6a	1020	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1021	}
mbed_official	330:c80ac197fa6a	1022
mbed_official	330:c80ac197fa6a	1023	/* Enable TXE and ERR interrupt */
mbed_official	330:c80ac197fa6a	1024	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official	330:c80ac197fa6a	1025
mbed_official	330:c80ac197fa6a	1026	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1027	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1028
mbed_official	330:c80ac197fa6a	1029	/* Note : The SPI must be enabled after unlocking current process
mbed_official	330:c80ac197fa6a	1030	to avoid the risk of SPI interrupt handle execution before current
mbed_official	330:c80ac197fa6a	1031	process unlock */
mbed_official	330:c80ac197fa6a	1032
mbed_official	330:c80ac197fa6a	1033	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1034	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1035	{
mbed_official	330:c80ac197fa6a	1036	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1037	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1038	}
mbed_official	330:c80ac197fa6a	1039
mbed_official	330:c80ac197fa6a	1040	return HAL_OK;
mbed_official	330:c80ac197fa6a	1041	}
mbed_official	330:c80ac197fa6a	1042	else
mbed_official	330:c80ac197fa6a	1043	{
mbed_official	330:c80ac197fa6a	1044	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1045	}
mbed_official	330:c80ac197fa6a	1046	}
mbed_official	330:c80ac197fa6a	1047
mbed_official	330:c80ac197fa6a	1048	/**
mbed_official	330:c80ac197fa6a	1049	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	330:c80ac197fa6a	1050	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1051	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	1052	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	1053	* @retval HAL status
mbed_official	330:c80ac197fa6a	1054	*/
mbed_official	330:c80ac197fa6a	1055	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	330:c80ac197fa6a	1056	{
mbed_official	330:c80ac197fa6a	1057	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	1058	{
mbed_official	632:7687fb9c4f91	1059	if((pData == NULL) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	1060	{
mbed_official	330:c80ac197fa6a	1061	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1062	}
mbed_official	330:c80ac197fa6a	1063
mbed_official	330:c80ac197fa6a	1064	/* Process Locked */
mbed_official	330:c80ac197fa6a	1065	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	1066
mbed_official	330:c80ac197fa6a	1067	/* Configure communication */
mbed_official	330:c80ac197fa6a	1068	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	330:c80ac197fa6a	1069	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	1070	hspi->pRxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	1071	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	1072	hspi->RxXferCount = Size;
mbed_official	632:7687fb9c4f91	1073	hspi->pTxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	1074	hspi->TxXferSize = 0;
mbed_official	330:c80ac197fa6a	1075	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	1076
mbed_official	330:c80ac197fa6a	1077	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	330:c80ac197fa6a	1078	{
mbed_official	330:c80ac197fa6a	1079	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1080	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1081	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	330:c80ac197fa6a	1082	/* in this we call the transmitReceive process */
mbed_official	330:c80ac197fa6a	1083	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official	330:c80ac197fa6a	1084	}
mbed_official	330:c80ac197fa6a	1085
mbed_official	330:c80ac197fa6a	1086	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1087	{
mbed_official	330:c80ac197fa6a	1088	hspi->CRCSize = 1;
mbed_official	330:c80ac197fa6a	1089	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	330:c80ac197fa6a	1090	{
mbed_official	330:c80ac197fa6a	1091	hspi->CRCSize = 2;
mbed_official	330:c80ac197fa6a	1092	}
mbed_official	330:c80ac197fa6a	1093	}
mbed_official	330:c80ac197fa6a	1094	else
mbed_official	330:c80ac197fa6a	1095	{
mbed_official	330:c80ac197fa6a	1096	hspi->CRCSize = 0;
mbed_official	330:c80ac197fa6a	1097	}
mbed_official	330:c80ac197fa6a	1098
mbed_official	330:c80ac197fa6a	1099	/* check the data size to adapt Rx threshold and the set the function for IT treatement */
mbed_official	330:c80ac197fa6a	1100	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	330:c80ac197fa6a	1101	{
mbed_official	330:c80ac197fa6a	1102	/* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official	330:c80ac197fa6a	1103	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1104	hspi->RxISR = SPI_RxISR_16BIT;
mbed_official	632:7687fb9c4f91	1105	hspi->TxISR = NULL;
mbed_official	330:c80ac197fa6a	1106	}
mbed_official	330:c80ac197fa6a	1107	else
mbed_official	330:c80ac197fa6a	1108	{
mbed_official	330:c80ac197fa6a	1109	/* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official	330:c80ac197fa6a	1110	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1111	hspi->RxISR = SPI_RxISR_8BIT;
mbed_official	632:7687fb9c4f91	1112	hspi->TxISR = NULL;
mbed_official	330:c80ac197fa6a	1113	}
mbed_official	330:c80ac197fa6a	1114
mbed_official	330:c80ac197fa6a	1115	/* Configure communication direction : 1Line */
mbed_official	330:c80ac197fa6a	1116	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	1117	{
mbed_official	330:c80ac197fa6a	1118	__HAL_SPI_1LINE_RX(hspi);
mbed_official	330:c80ac197fa6a	1119	}
mbed_official	330:c80ac197fa6a	1120
mbed_official	330:c80ac197fa6a	1121	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	1122	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1123	{
mbed_official	330:c80ac197fa6a	1124	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1125	}
mbed_official	330:c80ac197fa6a	1126
mbed_official	330:c80ac197fa6a	1127	/* Enable TXE and ERR interrupt */
mbed_official	330:c80ac197fa6a	1128	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	1129
mbed_official	330:c80ac197fa6a	1130	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1131	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1132
mbed_official	330:c80ac197fa6a	1133	/* Note : The SPI must be enabled after unlocking current process
mbed_official	330:c80ac197fa6a	1134	to avoid the risk of SPI interrupt handle execution before current
mbed_official	330:c80ac197fa6a	1135	process unlock */
mbed_official	330:c80ac197fa6a	1136
mbed_official	330:c80ac197fa6a	1137	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1138	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1139	{
mbed_official	330:c80ac197fa6a	1140	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1141	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1142	}
mbed_official	330:c80ac197fa6a	1143
mbed_official	330:c80ac197fa6a	1144	return HAL_OK;
mbed_official	330:c80ac197fa6a	1145	}
mbed_official	330:c80ac197fa6a	1146	else
mbed_official	330:c80ac197fa6a	1147	{
mbed_official	330:c80ac197fa6a	1148	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1149	}
mbed_official	330:c80ac197fa6a	1150	}
mbed_official	330:c80ac197fa6a	1151
mbed_official	330:c80ac197fa6a	1152	/**
mbed_official	330:c80ac197fa6a	1153	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	330:c80ac197fa6a	1154	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1155	* @param pTxData: pointer to transmission data buffer
mbed_official	330:c80ac197fa6a	1156	* @param pRxData: pointer to reception data buffer to be
mbed_official	330:c80ac197fa6a	1157	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	1158	* @retval HAL status
mbed_official	330:c80ac197fa6a	1159	*/
mbed_official	330:c80ac197fa6a	1160	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	330:c80ac197fa6a	1161	{
mbed_official	330:c80ac197fa6a	1162	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	1163
mbed_official	330:c80ac197fa6a	1164	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	330:c80ac197fa6a	1165	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	330:c80ac197fa6a	1166	{
mbed_official	632:7687fb9c4f91	1167	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	1168	{
mbed_official	330:c80ac197fa6a	1169	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1170	}
mbed_official	330:c80ac197fa6a	1171
mbed_official	330:c80ac197fa6a	1172	/* Process locked */
mbed_official	330:c80ac197fa6a	1173	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	1174
mbed_official	330:c80ac197fa6a	1175	hspi->CRCSize = 0;
mbed_official	330:c80ac197fa6a	1176	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1177	{
mbed_official	330:c80ac197fa6a	1178	hspi->CRCSize = 1;
mbed_official	330:c80ac197fa6a	1179	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	330:c80ac197fa6a	1180	{
mbed_official	330:c80ac197fa6a	1181	hspi->CRCSize = 2;
mbed_official	330:c80ac197fa6a	1182	}
mbed_official	330:c80ac197fa6a	1183	}
mbed_official	330:c80ac197fa6a	1184
mbed_official	330:c80ac197fa6a	1185	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	330:c80ac197fa6a	1186	{
mbed_official	330:c80ac197fa6a	1187	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	330:c80ac197fa6a	1188	}
mbed_official	330:c80ac197fa6a	1189
mbed_official	330:c80ac197fa6a	1190	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	1191	hspi->pTxBuffPtr = pTxData;
mbed_official	330:c80ac197fa6a	1192	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	1193	hspi->TxXferCount = Size;
mbed_official	330:c80ac197fa6a	1194	hspi->pRxBuffPtr = pRxData;
mbed_official	330:c80ac197fa6a	1195	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	1196	hspi->RxXferCount = Size;
mbed_official	330:c80ac197fa6a	1197
mbed_official	330:c80ac197fa6a	1198	/* Set the function for IT treatement */
mbed_official	330:c80ac197fa6a	1199	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	330:c80ac197fa6a	1200	{
mbed_official	330:c80ac197fa6a	1201	hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official	330:c80ac197fa6a	1202	hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official	330:c80ac197fa6a	1203	}
mbed_official	330:c80ac197fa6a	1204	else
mbed_official	330:c80ac197fa6a	1205	{
mbed_official	330:c80ac197fa6a	1206	hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official	330:c80ac197fa6a	1207	hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official	330:c80ac197fa6a	1208	}
mbed_official	330:c80ac197fa6a	1209
mbed_official	330:c80ac197fa6a	1210	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	1211	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1212	{
mbed_official	330:c80ac197fa6a	1213	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1214	}
mbed_official	330:c80ac197fa6a	1215
mbed_official	330:c80ac197fa6a	1216	/* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official	330:c80ac197fa6a	1217	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
mbed_official	330:c80ac197fa6a	1218	{
mbed_official	330:c80ac197fa6a	1219	/* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official	330:c80ac197fa6a	1220	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1221	}
mbed_official	330:c80ac197fa6a	1222	else
mbed_official	330:c80ac197fa6a	1223	{
mbed_official	330:c80ac197fa6a	1224	/* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official	330:c80ac197fa6a	1225	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1226	}
mbed_official	330:c80ac197fa6a	1227
mbed_official	330:c80ac197fa6a	1228	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	330:c80ac197fa6a	1229	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	1230
mbed_official	330:c80ac197fa6a	1231	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1232	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1233
mbed_official	330:c80ac197fa6a	1234	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1235	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1236	{
mbed_official	330:c80ac197fa6a	1237	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1238	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1239	}
mbed_official	330:c80ac197fa6a	1240
mbed_official	330:c80ac197fa6a	1241	return HAL_OK;
mbed_official	330:c80ac197fa6a	1242	}
mbed_official	330:c80ac197fa6a	1243	else
mbed_official	330:c80ac197fa6a	1244	{
mbed_official	330:c80ac197fa6a	1245	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1246	}
mbed_official	330:c80ac197fa6a	1247	}
mbed_official	330:c80ac197fa6a	1248
mbed_official	330:c80ac197fa6a	1249	/**
mbed_official	330:c80ac197fa6a	1250	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	330:c80ac197fa6a	1251	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1252	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	1253	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	1254	* @retval HAL status
mbed_official	330:c80ac197fa6a	1255	*/
mbed_official	330:c80ac197fa6a	1256	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	330:c80ac197fa6a	1257	{
mbed_official	330:c80ac197fa6a	1258	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	1259
mbed_official	330:c80ac197fa6a	1260	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	1261	{
mbed_official	330:c80ac197fa6a	1262	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1263	}
mbed_official	330:c80ac197fa6a	1264
mbed_official	632:7687fb9c4f91	1265	if((pData == NULL) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	1266	{
mbed_official	330:c80ac197fa6a	1267	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1268	}
mbed_official	330:c80ac197fa6a	1269
mbed_official	330:c80ac197fa6a	1270	/* Process Locked */
mbed_official	330:c80ac197fa6a	1271	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	1272
mbed_official	330:c80ac197fa6a	1273	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	330:c80ac197fa6a	1274	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	1275	hspi->pTxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	1276	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	1277	hspi->TxXferCount = Size;
mbed_official	632:7687fb9c4f91	1278	hspi->pRxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	1279	hspi->RxXferSize = 0;
mbed_official	330:c80ac197fa6a	1280	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	1281
mbed_official	330:c80ac197fa6a	1282	/* Configure communication direction : 1Line */
mbed_official	330:c80ac197fa6a	1283	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	1284	{
mbed_official	330:c80ac197fa6a	1285	__HAL_SPI_1LINE_TX(hspi);
mbed_official	330:c80ac197fa6a	1286	}
mbed_official	330:c80ac197fa6a	1287
mbed_official	330:c80ac197fa6a	1288	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	1289	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1290	{
mbed_official	330:c80ac197fa6a	1291	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1292	}
mbed_official	330:c80ac197fa6a	1293
mbed_official	330:c80ac197fa6a	1294	/* Set the SPI TxDMA transfer complete callback */
mbed_official	330:c80ac197fa6a	1295	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	330:c80ac197fa6a	1296
mbed_official	330:c80ac197fa6a	1297	/* Set the DMA error callback */
mbed_official	330:c80ac197fa6a	1298	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	330:c80ac197fa6a	1299
mbed_official	330:c80ac197fa6a	1300	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1301	/* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official	330:c80ac197fa6a	1302	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official	330:c80ac197fa6a	1303	{
mbed_official	330:c80ac197fa6a	1304	/* Check the even/odd of the data size + crc if enabled */
mbed_official	330:c80ac197fa6a	1305	if((hspi->TxXferCount & 0x1) == 0)
mbed_official	330:c80ac197fa6a	1306	{
mbed_official	330:c80ac197fa6a	1307	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1308	hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official	330:c80ac197fa6a	1309	}
mbed_official	330:c80ac197fa6a	1310	else
mbed_official	330:c80ac197fa6a	1311	{
mbed_official	330:c80ac197fa6a	1312	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1313	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official	330:c80ac197fa6a	1314	}
mbed_official	330:c80ac197fa6a	1315	}
mbed_official	330:c80ac197fa6a	1316
mbed_official	330:c80ac197fa6a	1317	/* Enable the Tx DMA channel */
mbed_official	330:c80ac197fa6a	1318	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	330:c80ac197fa6a	1319
mbed_official	330:c80ac197fa6a	1320	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1321	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1322	{
mbed_official	330:c80ac197fa6a	1323	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1324	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1325	}
mbed_official	330:c80ac197fa6a	1326
mbed_official	330:c80ac197fa6a	1327	/* Enable Tx DMA Request */
mbed_official	330:c80ac197fa6a	1328	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	330:c80ac197fa6a	1329
mbed_official	330:c80ac197fa6a	1330	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1331	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1332
mbed_official	330:c80ac197fa6a	1333	return HAL_OK;
mbed_official	330:c80ac197fa6a	1334	}
mbed_official	330:c80ac197fa6a	1335
mbed_official	330:c80ac197fa6a	1336	/**
mbed_official	330:c80ac197fa6a	1337	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	330:c80ac197fa6a	1338	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1339	* @param pData: pointer to data buffer
mbed_official	330:c80ac197fa6a	1340	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	1341	* @retval HAL status
mbed_official	330:c80ac197fa6a	1342	*/
mbed_official	330:c80ac197fa6a	1343	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	330:c80ac197fa6a	1344	{
mbed_official	330:c80ac197fa6a	1345	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	330:c80ac197fa6a	1346	{
mbed_official	330:c80ac197fa6a	1347	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1348	}
mbed_official	330:c80ac197fa6a	1349
mbed_official	632:7687fb9c4f91	1350	if((pData == NULL) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	1351	{
mbed_official	330:c80ac197fa6a	1352	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1353	}
mbed_official	330:c80ac197fa6a	1354
mbed_official	330:c80ac197fa6a	1355	/* Process Locked */
mbed_official	330:c80ac197fa6a	1356	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	1357
mbed_official	330:c80ac197fa6a	1358	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	330:c80ac197fa6a	1359	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	1360	hspi->pRxBuffPtr = pData;
mbed_official	330:c80ac197fa6a	1361	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	1362	hspi->RxXferCount = Size;
mbed_official	632:7687fb9c4f91	1363	hspi->pTxBuffPtr = NULL;
mbed_official	330:c80ac197fa6a	1364	hspi->TxXferSize = 0;
mbed_official	330:c80ac197fa6a	1365	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	1366
mbed_official	330:c80ac197fa6a	1367	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	330:c80ac197fa6a	1368	{
mbed_official	330:c80ac197fa6a	1369	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1370	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1371	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	330:c80ac197fa6a	1372	/* in this case we call the transmitReceive process */
mbed_official	330:c80ac197fa6a	1373	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official	330:c80ac197fa6a	1374	}
mbed_official	330:c80ac197fa6a	1375
mbed_official	330:c80ac197fa6a	1376	/* Configure communication direction : 1Line */
mbed_official	330:c80ac197fa6a	1377	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	330:c80ac197fa6a	1378	{
mbed_official	330:c80ac197fa6a	1379	__HAL_SPI_1LINE_RX(hspi);
mbed_official	330:c80ac197fa6a	1380	}
mbed_official	330:c80ac197fa6a	1381
mbed_official	330:c80ac197fa6a	1382	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	1383	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1384	{
mbed_official	330:c80ac197fa6a	1385	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1386	}
mbed_official	330:c80ac197fa6a	1387
mbed_official	330:c80ac197fa6a	1388	/* packing mode management is enabled by the DMA settings */
mbed_official	330:c80ac197fa6a	1389	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official	330:c80ac197fa6a	1390	{
mbed_official	330:c80ac197fa6a	1391	/* Process Locked */
mbed_official	330:c80ac197fa6a	1392	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1393	/* Restriction the DMA data received is not allowed in this mode */
mbed_official	330:c80ac197fa6a	1394	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1395	}
mbed_official	330:c80ac197fa6a	1396
mbed_official	330:c80ac197fa6a	1397	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	330:c80ac197fa6a	1398	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	1399	{
mbed_official	330:c80ac197fa6a	1400	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	330:c80ac197fa6a	1401	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1402	}
mbed_official	330:c80ac197fa6a	1403	else
mbed_official	330:c80ac197fa6a	1404	{
mbed_official	330:c80ac197fa6a	1405	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	330:c80ac197fa6a	1406	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1407	}
mbed_official	330:c80ac197fa6a	1408
mbed_official	330:c80ac197fa6a	1409	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	330:c80ac197fa6a	1410	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	330:c80ac197fa6a	1411
mbed_official	330:c80ac197fa6a	1412	/* Set the DMA error callback */
mbed_official	330:c80ac197fa6a	1413	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	330:c80ac197fa6a	1414
mbed_official	330:c80ac197fa6a	1415	/* Enable Rx DMA Request */
mbed_official	330:c80ac197fa6a	1416	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	330:c80ac197fa6a	1417
mbed_official	330:c80ac197fa6a	1418	/* Enable the Rx DMA channel */
mbed_official	330:c80ac197fa6a	1419	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	330:c80ac197fa6a	1420
mbed_official	330:c80ac197fa6a	1421	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1422	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1423
mbed_official	330:c80ac197fa6a	1424	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1425	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1426	{
mbed_official	330:c80ac197fa6a	1427	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1428	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1429	}
mbed_official	330:c80ac197fa6a	1430
mbed_official	330:c80ac197fa6a	1431	return HAL_OK;
mbed_official	330:c80ac197fa6a	1432	}
mbed_official	330:c80ac197fa6a	1433
mbed_official	330:c80ac197fa6a	1434	/**
mbed_official	330:c80ac197fa6a	1435	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	330:c80ac197fa6a	1436	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1437	* @param pTxData: pointer to transmission data buffer
mbed_official	330:c80ac197fa6a	1438	* @param pRxData: pointer to reception data buffer to be
mbed_official	330:c80ac197fa6a	1439	* @param Size: amount of data to be sent
mbed_official	330:c80ac197fa6a	1440	* @retval HAL status
mbed_official	330:c80ac197fa6a	1441	*/
mbed_official	330:c80ac197fa6a	1442	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	330:c80ac197fa6a	1443	{
mbed_official	330:c80ac197fa6a	1444	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	330:c80ac197fa6a	1445
mbed_official	330:c80ac197fa6a	1446	if((hspi->State == HAL_SPI_STATE_READY) \|\|
mbed_official	330:c80ac197fa6a	1447	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	330:c80ac197fa6a	1448	{
mbed_official	632:7687fb9c4f91	1449	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	330:c80ac197fa6a	1450	{
mbed_official	330:c80ac197fa6a	1451	return HAL_ERROR;
mbed_official	330:c80ac197fa6a	1452	}
mbed_official	330:c80ac197fa6a	1453
mbed_official	330:c80ac197fa6a	1454	/* Process locked */
mbed_official	330:c80ac197fa6a	1455	__HAL_LOCK(hspi);
mbed_official	330:c80ac197fa6a	1456
mbed_official	330:c80ac197fa6a	1457	/* check if the transmit Receive function is not called by a receive master */
mbed_official	330:c80ac197fa6a	1458	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	330:c80ac197fa6a	1459	{
mbed_official	330:c80ac197fa6a	1460	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	330:c80ac197fa6a	1461	}
mbed_official	330:c80ac197fa6a	1462
mbed_official	330:c80ac197fa6a	1463	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	330:c80ac197fa6a	1464	hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official	330:c80ac197fa6a	1465	hspi->TxXferSize = Size;
mbed_official	330:c80ac197fa6a	1466	hspi->TxXferCount = Size;
mbed_official	330:c80ac197fa6a	1467	hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official	330:c80ac197fa6a	1468	hspi->RxXferSize = Size;
mbed_official	330:c80ac197fa6a	1469	hspi->RxXferCount = Size;
mbed_official	330:c80ac197fa6a	1470
mbed_official	330:c80ac197fa6a	1471	/* Reset CRC Calculation + increase the rxsize */
mbed_official	330:c80ac197fa6a	1472	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1473	{
mbed_official	330:c80ac197fa6a	1474	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	1475	}
mbed_official	330:c80ac197fa6a	1476
mbed_official	330:c80ac197fa6a	1477	/* Reset the threshold bit */
mbed_official	330:c80ac197fa6a	1478	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1479	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	330:c80ac197fa6a	1480
mbed_official	330:c80ac197fa6a	1481	/* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official	330:c80ac197fa6a	1482	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	1483	{
mbed_official	330:c80ac197fa6a	1484	/* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official	330:c80ac197fa6a	1485	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1486	}
mbed_official	330:c80ac197fa6a	1487	else
mbed_official	330:c80ac197fa6a	1488	{
mbed_official	330:c80ac197fa6a	1489	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	330:c80ac197fa6a	1490	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1491
mbed_official	330:c80ac197fa6a	1492	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official	330:c80ac197fa6a	1493	{
mbed_official	330:c80ac197fa6a	1494	if((hspi->TxXferSize & 0x1) == 0x0 )
mbed_official	330:c80ac197fa6a	1495	{
mbed_official	330:c80ac197fa6a	1496	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1497	hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official	330:c80ac197fa6a	1498	}
mbed_official	330:c80ac197fa6a	1499	else
mbed_official	330:c80ac197fa6a	1500	{
mbed_official	330:c80ac197fa6a	1501	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	330:c80ac197fa6a	1502	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official	330:c80ac197fa6a	1503	}
mbed_official	330:c80ac197fa6a	1504	}
mbed_official	330:c80ac197fa6a	1505
mbed_official	330:c80ac197fa6a	1506	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official	330:c80ac197fa6a	1507	{
mbed_official	330:c80ac197fa6a	1508	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	330:c80ac197fa6a	1509	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1510
mbed_official	330:c80ac197fa6a	1511	/* Size must include the CRC lenght */
mbed_official	330:c80ac197fa6a	1512	if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official	330:c80ac197fa6a	1513	{
mbed_official	330:c80ac197fa6a	1514	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	330:c80ac197fa6a	1515	hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official	330:c80ac197fa6a	1516	}
mbed_official	330:c80ac197fa6a	1517	else
mbed_official	330:c80ac197fa6a	1518	{
mbed_official	330:c80ac197fa6a	1519	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	330:c80ac197fa6a	1520	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official	330:c80ac197fa6a	1521	}
mbed_official	330:c80ac197fa6a	1522	}
mbed_official	330:c80ac197fa6a	1523	}
mbed_official	330:c80ac197fa6a	1524
mbed_official	330:c80ac197fa6a	1525	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official	330:c80ac197fa6a	1526	the reception request (RXNE) */
mbed_official	330:c80ac197fa6a	1527	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	330:c80ac197fa6a	1528	{
mbed_official	330:c80ac197fa6a	1529	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	330:c80ac197fa6a	1530	}
mbed_official	330:c80ac197fa6a	1531	else
mbed_official	330:c80ac197fa6a	1532	{
mbed_official	330:c80ac197fa6a	1533	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	330:c80ac197fa6a	1534	}
mbed_official	330:c80ac197fa6a	1535	/* Set the DMA error callback */
mbed_official	330:c80ac197fa6a	1536	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	330:c80ac197fa6a	1537
mbed_official	330:c80ac197fa6a	1538	/* Enable Rx DMA Request */
mbed_official	330:c80ac197fa6a	1539	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	330:c80ac197fa6a	1540
mbed_official	330:c80ac197fa6a	1541	/* Enable the Rx DMA channel */
mbed_official	330:c80ac197fa6a	1542	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	330:c80ac197fa6a	1543
mbed_official	632:7687fb9c4f91	1544	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	330:c80ac197fa6a	1545	is performed in DMA reception complete callback */
mbed_official	632:7687fb9c4f91	1546	hspi->hdmatx->XferCpltCallback = NULL;
mbed_official	330:c80ac197fa6a	1547
mbed_official	330:c80ac197fa6a	1548	/* Set the DMA error callback */
mbed_official	330:c80ac197fa6a	1549	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	330:c80ac197fa6a	1550
mbed_official	330:c80ac197fa6a	1551	/* Enable the Tx DMA channel */
mbed_official	330:c80ac197fa6a	1552	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	330:c80ac197fa6a	1553
mbed_official	330:c80ac197fa6a	1554	/* Check if the SPI is already enabled */
mbed_official	330:c80ac197fa6a	1555	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	330:c80ac197fa6a	1556	{
mbed_official	330:c80ac197fa6a	1557	/* Enable SPI peripheral */
mbed_official	330:c80ac197fa6a	1558	__HAL_SPI_ENABLE(hspi);
mbed_official	330:c80ac197fa6a	1559	}
mbed_official	330:c80ac197fa6a	1560
mbed_official	330:c80ac197fa6a	1561	/* Enable Tx DMA Request */
mbed_official	330:c80ac197fa6a	1562	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	330:c80ac197fa6a	1563
mbed_official	330:c80ac197fa6a	1564	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	1565	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	1566
mbed_official	330:c80ac197fa6a	1567	return HAL_OK;
mbed_official	330:c80ac197fa6a	1568	}
mbed_official	330:c80ac197fa6a	1569	else
mbed_official	330:c80ac197fa6a	1570	{
mbed_official	330:c80ac197fa6a	1571	return HAL_BUSY;
mbed_official	330:c80ac197fa6a	1572	}
mbed_official	330:c80ac197fa6a	1573	}
mbed_official	330:c80ac197fa6a	1574
mbed_official	330:c80ac197fa6a	1575	/**
mbed_official	330:c80ac197fa6a	1576	* @brief This function handles SPI interrupt request.
mbed_official	330:c80ac197fa6a	1577	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1578	* @retval HAL status
mbed_official	330:c80ac197fa6a	1579	*/
mbed_official	330:c80ac197fa6a	1580	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1581	{
mbed_official	330:c80ac197fa6a	1582	/* SPI in mode Receiver ----------------------------------------------------*/
mbed_official	330:c80ac197fa6a	1583	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
mbed_official	330:c80ac197fa6a	1584	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
mbed_official	330:c80ac197fa6a	1585	{
mbed_official	330:c80ac197fa6a	1586	hspi->RxISR(hspi);
mbed_official	330:c80ac197fa6a	1587	return;
mbed_official	330:c80ac197fa6a	1588	}
mbed_official	330:c80ac197fa6a	1589
mbed_official	330:c80ac197fa6a	1590	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	330:c80ac197fa6a	1591	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
mbed_official	330:c80ac197fa6a	1592	{
mbed_official	330:c80ac197fa6a	1593	hspi->TxISR(hspi);
mbed_official	330:c80ac197fa6a	1594	return;
mbed_official	330:c80ac197fa6a	1595	}
mbed_official	330:c80ac197fa6a	1596
mbed_official	330:c80ac197fa6a	1597	/* SPI in Erreur Treatment ---------------------------------------------------*/
mbed_official	330:c80ac197fa6a	1598	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
mbed_official	330:c80ac197fa6a	1599	{
mbed_official	330:c80ac197fa6a	1600	/* SPI Overrun error interrupt occured -------------------------------------*/
mbed_official	330:c80ac197fa6a	1601	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	330:c80ac197fa6a	1602	{
mbed_official	330:c80ac197fa6a	1603	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	330:c80ac197fa6a	1604	{
mbed_official	330:c80ac197fa6a	1605	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	330:c80ac197fa6a	1606	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	330:c80ac197fa6a	1607	}
mbed_official	330:c80ac197fa6a	1608	else
mbed_official	330:c80ac197fa6a	1609	{
mbed_official	330:c80ac197fa6a	1610	return;
mbed_official	330:c80ac197fa6a	1611	}
mbed_official	330:c80ac197fa6a	1612	}
mbed_official	330:c80ac197fa6a	1613
mbed_official	330:c80ac197fa6a	1614	/* SPI Mode Fault error interrupt occured -------------------------------------*/
mbed_official	330:c80ac197fa6a	1615	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	330:c80ac197fa6a	1616	{
mbed_official	330:c80ac197fa6a	1617	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	330:c80ac197fa6a	1618	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	330:c80ac197fa6a	1619	}
mbed_official	330:c80ac197fa6a	1620
mbed_official	330:c80ac197fa6a	1621	/* SPI Frame error interrupt occured ----------------------------------------*/
mbed_official	330:c80ac197fa6a	1622	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	330:c80ac197fa6a	1623	{
mbed_official	330:c80ac197fa6a	1624	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	330:c80ac197fa6a	1625	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	330:c80ac197fa6a	1626	}
mbed_official	330:c80ac197fa6a	1627
mbed_official	330:c80ac197fa6a	1628	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
mbed_official	330:c80ac197fa6a	1629	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	1630	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1631
mbed_official	330:c80ac197fa6a	1632	return;
mbed_official	330:c80ac197fa6a	1633	}
mbed_official	330:c80ac197fa6a	1634	}
mbed_official	330:c80ac197fa6a	1635
mbed_official	330:c80ac197fa6a	1636	/**
mbed_official	330:c80ac197fa6a	1637	* @brief DMA SPI transmit process complete callback
mbed_official	330:c80ac197fa6a	1638	* @param hdma : DMA handle
mbed_official	330:c80ac197fa6a	1639	* @retval None
mbed_official	330:c80ac197fa6a	1640	*/
mbed_official	330:c80ac197fa6a	1641	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	330:c80ac197fa6a	1642	{
mbed_official	330:c80ac197fa6a	1643	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	330:c80ac197fa6a	1644
mbed_official	330:c80ac197fa6a	1645	/* Disable Tx DMA Request */
mbed_official	330:c80ac197fa6a	1646	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	330:c80ac197fa6a	1647
mbed_official	330:c80ac197fa6a	1648	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	1649	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	1650
mbed_official	330:c80ac197fa6a	1651	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
mbed_official	330:c80ac197fa6a	1652	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	330:c80ac197fa6a	1653	{
mbed_official	330:c80ac197fa6a	1654	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	330:c80ac197fa6a	1655	}
mbed_official	330:c80ac197fa6a	1656
mbed_official	330:c80ac197fa6a	1657	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	1658	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	1659
mbed_official	330:c80ac197fa6a	1660	/* Check if CRC error occurred or Error code */
mbed_official	330:c80ac197fa6a	1661	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	1662	{
mbed_official	330:c80ac197fa6a	1663	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1664	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	1665	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1666	}
mbed_official	330:c80ac197fa6a	1667	else
mbed_official	330:c80ac197fa6a	1668	{
mbed_official	330:c80ac197fa6a	1669	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	1670	{
mbed_official	330:c80ac197fa6a	1671	HAL_SPI_TxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	1672	}
mbed_official	330:c80ac197fa6a	1673	else
mbed_official	330:c80ac197fa6a	1674	{
mbed_official	330:c80ac197fa6a	1675	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1676	}
mbed_official	330:c80ac197fa6a	1677	}
mbed_official	330:c80ac197fa6a	1678	}
mbed_official	330:c80ac197fa6a	1679
mbed_official	330:c80ac197fa6a	1680	/**
mbed_official	330:c80ac197fa6a	1681	* @brief DMA SPI receive process complete callback
mbed_official	330:c80ac197fa6a	1682	* @param hdma : DMA handle
mbed_official	330:c80ac197fa6a	1683	* @retval None
mbed_official	330:c80ac197fa6a	1684	*/
mbed_official	330:c80ac197fa6a	1685	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	330:c80ac197fa6a	1686	{
mbed_official	330:c80ac197fa6a	1687	__IO uint16_t tmpreg;
mbed_official	330:c80ac197fa6a	1688	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	330:c80ac197fa6a	1689
mbed_official	330:c80ac197fa6a	1690	/* CRC handling */
mbed_official	330:c80ac197fa6a	1691	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1692	{
mbed_official	330:c80ac197fa6a	1693	/* Wait until TXE flag */
mbed_official	330:c80ac197fa6a	1694	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	330:c80ac197fa6a	1695	{
mbed_official	330:c80ac197fa6a	1696	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	1697	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1698	}
mbed_official	330:c80ac197fa6a	1699	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	330:c80ac197fa6a	1700	{
mbed_official	330:c80ac197fa6a	1701	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	1702	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	1703	}
mbed_official	330:c80ac197fa6a	1704	else
mbed_official	330:c80ac197fa6a	1705	{
mbed_official	330:c80ac197fa6a	1706	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	1707	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	632:7687fb9c4f91	1708
mbed_official	330:c80ac197fa6a	1709	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	330:c80ac197fa6a	1710	{
mbed_official	330:c80ac197fa6a	1711	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	330:c80ac197fa6a	1712	{
mbed_official	330:c80ac197fa6a	1713	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	1714	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1715	}
mbed_official	330:c80ac197fa6a	1716	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	1717	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	1718	}
mbed_official	330:c80ac197fa6a	1719	}
mbed_official	330:c80ac197fa6a	1720	}
mbed_official	330:c80ac197fa6a	1721
mbed_official	330:c80ac197fa6a	1722	/* Disable Rx DMA Request */
mbed_official	330:c80ac197fa6a	1723	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	330:c80ac197fa6a	1724	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official	330:c80ac197fa6a	1725	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	330:c80ac197fa6a	1726
mbed_official	330:c80ac197fa6a	1727	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	1728	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	1729
mbed_official	330:c80ac197fa6a	1730	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	1731	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	1732
mbed_official	330:c80ac197fa6a	1733	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	1734	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	1735	{
mbed_official	330:c80ac197fa6a	1736	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1737	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	1738	HAL_SPI_RxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	1739	}
mbed_official	330:c80ac197fa6a	1740	else
mbed_official	330:c80ac197fa6a	1741	{
mbed_official	330:c80ac197fa6a	1742	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	1743	{
mbed_official	330:c80ac197fa6a	1744	HAL_SPI_RxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	1745	}
mbed_official	330:c80ac197fa6a	1746	else
mbed_official	330:c80ac197fa6a	1747	{
mbed_official	330:c80ac197fa6a	1748	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1749	}
mbed_official	330:c80ac197fa6a	1750	}
mbed_official	330:c80ac197fa6a	1751	}
mbed_official	330:c80ac197fa6a	1752
mbed_official	330:c80ac197fa6a	1753	/**
mbed_official	330:c80ac197fa6a	1754	* @brief DMA SPI transmit receive process complete callback
mbed_official	330:c80ac197fa6a	1755	* @param hdma : DMA handle
mbed_official	330:c80ac197fa6a	1756	* @retval None
mbed_official	330:c80ac197fa6a	1757	*/
mbed_official	330:c80ac197fa6a	1758
mbed_official	330:c80ac197fa6a	1759	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	330:c80ac197fa6a	1760	{
mbed_official	330:c80ac197fa6a	1761	__IO int16_t tmpreg;
mbed_official	330:c80ac197fa6a	1762	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	330:c80ac197fa6a	1763
mbed_official	330:c80ac197fa6a	1764	/* CRC handling */
mbed_official	330:c80ac197fa6a	1765	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1766	{
mbed_official	330:c80ac197fa6a	1767	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official	330:c80ac197fa6a	1768	{
mbed_official	330:c80ac197fa6a	1769	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	330:c80ac197fa6a	1770	{
mbed_official	330:c80ac197fa6a	1771	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	1772	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1773	}
mbed_official	330:c80ac197fa6a	1774	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	1775	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	1776	}
mbed_official	330:c80ac197fa6a	1777	else
mbed_official	330:c80ac197fa6a	1778	{
mbed_official	330:c80ac197fa6a	1779	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	330:c80ac197fa6a	1780	{
mbed_official	330:c80ac197fa6a	1781	/* Erreur on the CRC reception */
mbed_official	330:c80ac197fa6a	1782	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1783	}
mbed_official	330:c80ac197fa6a	1784	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	1785	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	1786	}
mbed_official	330:c80ac197fa6a	1787	}
mbed_official	330:c80ac197fa6a	1788
mbed_official	330:c80ac197fa6a	1789	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	1790	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	1791
mbed_official	330:c80ac197fa6a	1792	/* Disable Tx DMA Request */
mbed_official	330:c80ac197fa6a	1793	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	330:c80ac197fa6a	1794
mbed_official	330:c80ac197fa6a	1795	/* Disable Rx DMA Request */
mbed_official	330:c80ac197fa6a	1796	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	330:c80ac197fa6a	1797
mbed_official	330:c80ac197fa6a	1798	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	1799	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	1800	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	1801
mbed_official	330:c80ac197fa6a	1802	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	1803	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	1804	{
mbed_official	330:c80ac197fa6a	1805	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	1806	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	1807	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1808	}
mbed_official	330:c80ac197fa6a	1809	else
mbed_official	330:c80ac197fa6a	1810	{
mbed_official	330:c80ac197fa6a	1811	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	1812	{
mbed_official	330:c80ac197fa6a	1813	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	1814	}
mbed_official	330:c80ac197fa6a	1815	else
mbed_official	330:c80ac197fa6a	1816	{
mbed_official	330:c80ac197fa6a	1817	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1818	}
mbed_official	330:c80ac197fa6a	1819	}
mbed_official	330:c80ac197fa6a	1820	}
mbed_official	330:c80ac197fa6a	1821
mbed_official	330:c80ac197fa6a	1822	/**
mbed_official	330:c80ac197fa6a	1823	* @brief DMA SPI communication error callback
mbed_official	330:c80ac197fa6a	1824	* @param hdma : DMA handle
mbed_official	330:c80ac197fa6a	1825	* @retval None
mbed_official	330:c80ac197fa6a	1826	*/
mbed_official	330:c80ac197fa6a	1827	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	330:c80ac197fa6a	1828	{
mbed_official	330:c80ac197fa6a	1829	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	330:c80ac197fa6a	1830	hspi->TxXferCount = 0;
mbed_official	330:c80ac197fa6a	1831	hspi->RxXferCount = 0;
mbed_official	330:c80ac197fa6a	1832	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
mbed_official	330:c80ac197fa6a	1833	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	1834	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	1835	}
mbed_official	330:c80ac197fa6a	1836
mbed_official	330:c80ac197fa6a	1837	/**
mbed_official	330:c80ac197fa6a	1838	* @brief Tx Transfer completed callbacks
mbed_official	330:c80ac197fa6a	1839	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1840	* @retval None
mbed_official	330:c80ac197fa6a	1841	*/
mbed_official	330:c80ac197fa6a	1842	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1843	{
mbed_official	330:c80ac197fa6a	1844	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	1845	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	330:c80ac197fa6a	1846	*/
mbed_official	330:c80ac197fa6a	1847	}
mbed_official	330:c80ac197fa6a	1848
mbed_official	330:c80ac197fa6a	1849	/**
mbed_official	330:c80ac197fa6a	1850	* @brief Rx Transfer completed callbacks
mbed_official	330:c80ac197fa6a	1851	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1852	* @retval None
mbed_official	330:c80ac197fa6a	1853	*/
mbed_official	330:c80ac197fa6a	1854	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1855	{
mbed_official	330:c80ac197fa6a	1856	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	1857	the HAL_SPI_RxCpltCallback could be implenetd in the user file
mbed_official	330:c80ac197fa6a	1858	*/
mbed_official	330:c80ac197fa6a	1859	}
mbed_official	330:c80ac197fa6a	1860
mbed_official	330:c80ac197fa6a	1861	/**
mbed_official	330:c80ac197fa6a	1862	* @brief Tx and Rx Transfer completed callbacks
mbed_official	330:c80ac197fa6a	1863	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1864	* @retval None
mbed_official	330:c80ac197fa6a	1865	*/
mbed_official	330:c80ac197fa6a	1866	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1867	{
mbed_official	330:c80ac197fa6a	1868	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	1869	the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
mbed_official	330:c80ac197fa6a	1870	*/
mbed_official	330:c80ac197fa6a	1871	}
mbed_official	330:c80ac197fa6a	1872
mbed_official	330:c80ac197fa6a	1873	/**
mbed_official	330:c80ac197fa6a	1874	* @brief SPI error callbacks
mbed_official	330:c80ac197fa6a	1875	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1876	* @retval None
mbed_official	330:c80ac197fa6a	1877	*/
mbed_official	330:c80ac197fa6a	1878	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1879	{
mbed_official	330:c80ac197fa6a	1880	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	330:c80ac197fa6a	1881	the HAL_SPI_ErrorCallback could be implenetd in the user file
mbed_official	330:c80ac197fa6a	1882	*/
mbed_official	330:c80ac197fa6a	1883	}
mbed_official	330:c80ac197fa6a	1884
mbed_official	330:c80ac197fa6a	1885	/**
mbed_official	330:c80ac197fa6a	1886	* @}
mbed_official	330:c80ac197fa6a	1887	*/
mbed_official	330:c80ac197fa6a	1888
mbed_official	330:c80ac197fa6a	1889	/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions
mbed_official	330:c80ac197fa6a	1890	* @brief SPI control functions
mbed_official	330:c80ac197fa6a	1891	*
mbed_official	330:c80ac197fa6a	1892	@verbatim
mbed_official	330:c80ac197fa6a	1893	===============================================================================
mbed_official	330:c80ac197fa6a	1894	##### Peripheral Control functions #####
mbed_official	330:c80ac197fa6a	1895	===============================================================================
mbed_official	330:c80ac197fa6a	1896	[..]
mbed_official	330:c80ac197fa6a	1897	This subsection provides a set of functions allowing to control the SPI.
mbed_official	330:c80ac197fa6a	1898	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
mbed_official	330:c80ac197fa6a	1899	(+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter)
mbed_official	330:c80ac197fa6a	1900	without calling the HAL_SPI_Init() API
mbed_official	330:c80ac197fa6a	1901	@endverbatim
mbed_official	330:c80ac197fa6a	1902	* @{
mbed_official	330:c80ac197fa6a	1903	*/
mbed_official	330:c80ac197fa6a	1904
mbed_official	330:c80ac197fa6a	1905	/**
mbed_official	330:c80ac197fa6a	1906	* @brief Return the SPI state
mbed_official	330:c80ac197fa6a	1907	* @param hspi : SPI handle
mbed_official	330:c80ac197fa6a	1908	* @retval HAL state
mbed_official	330:c80ac197fa6a	1909	*/
mbed_official	330:c80ac197fa6a	1910	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1911	{
mbed_official	330:c80ac197fa6a	1912	return hspi->State;
mbed_official	330:c80ac197fa6a	1913	}
mbed_official	330:c80ac197fa6a	1914	/**
mbed_official	330:c80ac197fa6a	1915	* @}
mbed_official	330:c80ac197fa6a	1916	*/
mbed_official	330:c80ac197fa6a	1917
mbed_official	330:c80ac197fa6a	1918	/**
mbed_official	330:c80ac197fa6a	1919	* @}
mbed_official	330:c80ac197fa6a	1920	*/
mbed_official	330:c80ac197fa6a	1921
mbed_official	330:c80ac197fa6a	1922	/** @addtogroup SPI_Private_Functions SPI Private Functions
mbed_official	330:c80ac197fa6a	1923	* @brief Data transfers Private functions
mbed_official	330:c80ac197fa6a	1924	* @{
mbed_official	330:c80ac197fa6a	1925	*/
mbed_official	330:c80ac197fa6a	1926
mbed_official	330:c80ac197fa6a	1927	/**
mbed_official	330:c80ac197fa6a	1928	* @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	1929	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1930	*/
mbed_official	330:c80ac197fa6a	1931	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1932	{
mbed_official	330:c80ac197fa6a	1933	/* Receive data in packing mode */
mbed_official	330:c80ac197fa6a	1934	if(hspi->RxXferCount > 1)
mbed_official	330:c80ac197fa6a	1935	{
mbed_official	330:c80ac197fa6a	1936	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	1937	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	1938	hspi->RxXferCount -= 2;
mbed_official	330:c80ac197fa6a	1939	if(hspi->RxXferCount == 1)
mbed_official	330:c80ac197fa6a	1940	{
mbed_official	330:c80ac197fa6a	1941	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	330:c80ac197fa6a	1942	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	330:c80ac197fa6a	1943	}
mbed_official	330:c80ac197fa6a	1944	}
mbed_official	330:c80ac197fa6a	1945	/* Receive data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	1946	else
mbed_official	330:c80ac197fa6a	1947	{
mbed_official	330:c80ac197fa6a	1948	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
mbed_official	330:c80ac197fa6a	1949	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	1950	}
mbed_official	330:c80ac197fa6a	1951
mbed_official	330:c80ac197fa6a	1952	/* check end of the reception */
mbed_official	330:c80ac197fa6a	1953	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	1954	{
mbed_official	330:c80ac197fa6a	1955	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	1956	{
mbed_official	330:c80ac197fa6a	1957	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official	330:c80ac197fa6a	1958	return;
mbed_official	330:c80ac197fa6a	1959	}
mbed_official	330:c80ac197fa6a	1960
mbed_official	330:c80ac197fa6a	1961	/* Disable RXNE interrupt */
mbed_official	330:c80ac197fa6a	1962	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	330:c80ac197fa6a	1963
mbed_official	330:c80ac197fa6a	1964	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	1965	{
mbed_official	330:c80ac197fa6a	1966	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	1967	}
mbed_official	330:c80ac197fa6a	1968	}
mbed_official	330:c80ac197fa6a	1969	}
mbed_official	330:c80ac197fa6a	1970
mbed_official	330:c80ac197fa6a	1971	/**
mbed_official	330:c80ac197fa6a	1972	* @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	1973	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	1974	*/
mbed_official	330:c80ac197fa6a	1975	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	1976	{
mbed_official	330:c80ac197fa6a	1977	__IO uint8_t tmpreg;
mbed_official	330:c80ac197fa6a	1978
mbed_official	330:c80ac197fa6a	1979	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
mbed_official	632:7687fb9c4f91	1980	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	632:7687fb9c4f91	1981
mbed_official	330:c80ac197fa6a	1982	hspi->CRCSize--;
mbed_official	330:c80ac197fa6a	1983
mbed_official	330:c80ac197fa6a	1984	/* check end of the reception */
mbed_official	330:c80ac197fa6a	1985	if(hspi->CRCSize == 0)
mbed_official	330:c80ac197fa6a	1986	{
mbed_official	330:c80ac197fa6a	1987	/* Disable RXNE interrupt */
mbed_official	330:c80ac197fa6a	1988	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	330:c80ac197fa6a	1989
mbed_official	330:c80ac197fa6a	1990	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	1991	{
mbed_official	330:c80ac197fa6a	1992	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	1993	}
mbed_official	330:c80ac197fa6a	1994	}
mbed_official	330:c80ac197fa6a	1995	}
mbed_official	330:c80ac197fa6a	1996
mbed_official	330:c80ac197fa6a	1997	/**
mbed_official	330:c80ac197fa6a	1998	* @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	1999	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2000	*/
mbed_official	330:c80ac197fa6a	2001	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2002	{
mbed_official	330:c80ac197fa6a	2003	/* Transmit data in packing Bit mode */
mbed_official	330:c80ac197fa6a	2004	if(hspi->TxXferCount >= 2)
mbed_official	330:c80ac197fa6a	2005	{
mbed_official	330:c80ac197fa6a	2006	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	2007	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	2008	hspi->TxXferCount -= 2;
mbed_official	330:c80ac197fa6a	2009	}
mbed_official	330:c80ac197fa6a	2010	/* Transmit data in 8 Bit mode */
mbed_official	330:c80ac197fa6a	2011	else
mbed_official	330:c80ac197fa6a	2012	{
mbed_official	330:c80ac197fa6a	2013	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	330:c80ac197fa6a	2014	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	2015	}
mbed_official	330:c80ac197fa6a	2016
mbed_official	330:c80ac197fa6a	2017	/* check the end of the transmission */
mbed_official	330:c80ac197fa6a	2018	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	2019	{
mbed_official	330:c80ac197fa6a	2020	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2021	{
mbed_official	330:c80ac197fa6a	2022	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2023	}
mbed_official	330:c80ac197fa6a	2024	/* Disable TXE interrupt */
mbed_official	330:c80ac197fa6a	2025	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official	330:c80ac197fa6a	2026
mbed_official	330:c80ac197fa6a	2027	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	2028	{
mbed_official	330:c80ac197fa6a	2029	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2030	}
mbed_official	330:c80ac197fa6a	2031	}
mbed_official	330:c80ac197fa6a	2032	}
mbed_official	330:c80ac197fa6a	2033
mbed_official	330:c80ac197fa6a	2034	/**
mbed_official	330:c80ac197fa6a	2035	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	2036	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2037	*/
mbed_official	330:c80ac197fa6a	2038	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2039	{
mbed_official	330:c80ac197fa6a	2040	/* Receive data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	2041	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	2042	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	2043	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	2044
mbed_official	330:c80ac197fa6a	2045	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	2046	{
mbed_official	330:c80ac197fa6a	2047	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2048	{
mbed_official	330:c80ac197fa6a	2049	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official	330:c80ac197fa6a	2050	return;
mbed_official	330:c80ac197fa6a	2051	}
mbed_official	330:c80ac197fa6a	2052
mbed_official	330:c80ac197fa6a	2053	/* Disable RXNE interrupt */
mbed_official	330:c80ac197fa6a	2054	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	330:c80ac197fa6a	2055
mbed_official	330:c80ac197fa6a	2056	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	2057	{
mbed_official	330:c80ac197fa6a	2058	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2059	}
mbed_official	330:c80ac197fa6a	2060	}
mbed_official	330:c80ac197fa6a	2061	}
mbed_official	330:c80ac197fa6a	2062
mbed_official	330:c80ac197fa6a	2063	/**
mbed_official	330:c80ac197fa6a	2064	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	2065	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2066	*/
mbed_official	330:c80ac197fa6a	2067	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2068	{
mbed_official	330:c80ac197fa6a	2069	__IO uint16_t tmpreg;
mbed_official	330:c80ac197fa6a	2070	/* Receive data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	2071	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	2072	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	2073
mbed_official	330:c80ac197fa6a	2074	/* Disable RXNE interrupt */
mbed_official	330:c80ac197fa6a	2075	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	330:c80ac197fa6a	2076
mbed_official	330:c80ac197fa6a	2077	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2078	}
mbed_official	330:c80ac197fa6a	2079
mbed_official	330:c80ac197fa6a	2080	/**
mbed_official	330:c80ac197fa6a	2081	* @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official	330:c80ac197fa6a	2082	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2083	*/
mbed_official	330:c80ac197fa6a	2084	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2085	{
mbed_official	330:c80ac197fa6a	2086	/* Transmit data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	2087	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	2088	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	2089	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	2090
mbed_official	330:c80ac197fa6a	2091	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	2092	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	2093	{
mbed_official	330:c80ac197fa6a	2094	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2095	{
mbed_official	330:c80ac197fa6a	2096	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2097	}
mbed_official	330:c80ac197fa6a	2098	/* Disable TXE interrupt */
mbed_official	330:c80ac197fa6a	2099	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official	330:c80ac197fa6a	2100
mbed_official	330:c80ac197fa6a	2101	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	2102	{
mbed_official	330:c80ac197fa6a	2103	SPI_CloseRxTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2104	}
mbed_official	330:c80ac197fa6a	2105	}
mbed_official	330:c80ac197fa6a	2106	}
mbed_official	330:c80ac197fa6a	2107
mbed_official	330:c80ac197fa6a	2108	/**
mbed_official	330:c80ac197fa6a	2109	* @brief Manage the CRC receive in Interrupt context
mbed_official	330:c80ac197fa6a	2110	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2111	*/
mbed_official	330:c80ac197fa6a	2112	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2113	{
mbed_official	330:c80ac197fa6a	2114	__IO uint8_t tmpreg;
mbed_official	330:c80ac197fa6a	2115	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
mbed_official	632:7687fb9c4f91	2116	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	632:7687fb9c4f91	2117
mbed_official	330:c80ac197fa6a	2118	hspi->CRCSize--;
mbed_official	330:c80ac197fa6a	2119
mbed_official	330:c80ac197fa6a	2120	if(hspi->CRCSize == 0)
mbed_official	330:c80ac197fa6a	2121	{
mbed_official	330:c80ac197fa6a	2122	SPI_CloseRx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2123	}
mbed_official	330:c80ac197fa6a	2124	}
mbed_official	330:c80ac197fa6a	2125
mbed_official	330:c80ac197fa6a	2126	/**
mbed_official	330:c80ac197fa6a	2127	* @brief Manage the recieve in Interrupt context
mbed_official	330:c80ac197fa6a	2128	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2129	*/
mbed_official	330:c80ac197fa6a	2130	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2131	{
mbed_official	330:c80ac197fa6a	2132	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
mbed_official	330:c80ac197fa6a	2133	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	2134
mbed_official	330:c80ac197fa6a	2135	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	2136	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	330:c80ac197fa6a	2137	{
mbed_official	330:c80ac197fa6a	2138	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2139	}
mbed_official	330:c80ac197fa6a	2140
mbed_official	330:c80ac197fa6a	2141	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	2142	{
mbed_official	330:c80ac197fa6a	2143	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2144	{
mbed_official	330:c80ac197fa6a	2145	hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official	330:c80ac197fa6a	2146	return;
mbed_official	330:c80ac197fa6a	2147	}
mbed_official	330:c80ac197fa6a	2148	SPI_CloseRx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2149	}
mbed_official	330:c80ac197fa6a	2150	}
mbed_official	330:c80ac197fa6a	2151
mbed_official	330:c80ac197fa6a	2152	/**
mbed_official	330:c80ac197fa6a	2153	* @brief Manage the CRC 16bit recieve in Interrupt context
mbed_official	330:c80ac197fa6a	2154	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2155	*/
mbed_official	330:c80ac197fa6a	2156	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2157	{
mbed_official	330:c80ac197fa6a	2158	__IO uint16_t tmpreg;
mbed_official	330:c80ac197fa6a	2159
mbed_official	330:c80ac197fa6a	2160	tmpreg = hspi->Instance->DR;
mbed_official	632:7687fb9c4f91	2161	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	2162
mbed_official	330:c80ac197fa6a	2163	/* Disable RXNE and ERR interrupt */
mbed_official	330:c80ac197fa6a	2164	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	2165
mbed_official	330:c80ac197fa6a	2166	SPI_CloseRx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2167	}
mbed_official	330:c80ac197fa6a	2168
mbed_official	330:c80ac197fa6a	2169	/**
mbed_official	330:c80ac197fa6a	2170	* @brief Manage the 16Bit recieve in Interrupt context
mbed_official	330:c80ac197fa6a	2171	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2172	*/
mbed_official	330:c80ac197fa6a	2173	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2174	{
mbed_official	330:c80ac197fa6a	2175	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	330:c80ac197fa6a	2176	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	2177	hspi->RxXferCount--;
mbed_official	330:c80ac197fa6a	2178
mbed_official	330:c80ac197fa6a	2179	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	2180	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	330:c80ac197fa6a	2181	{
mbed_official	330:c80ac197fa6a	2182	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2183	}
mbed_official	330:c80ac197fa6a	2184
mbed_official	330:c80ac197fa6a	2185	if(hspi->RxXferCount == 0)
mbed_official	330:c80ac197fa6a	2186	{
mbed_official	330:c80ac197fa6a	2187	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2188	{
mbed_official	330:c80ac197fa6a	2189	hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official	330:c80ac197fa6a	2190	return;
mbed_official	330:c80ac197fa6a	2191	}
mbed_official	330:c80ac197fa6a	2192	SPI_CloseRx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2193	}
mbed_official	330:c80ac197fa6a	2194	}
mbed_official	330:c80ac197fa6a	2195
mbed_official	330:c80ac197fa6a	2196	/**
mbed_official	330:c80ac197fa6a	2197	* @brief Handle the data 8Bit transmit in Interrupt mode
mbed_official	330:c80ac197fa6a	2198	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2199	*/
mbed_official	330:c80ac197fa6a	2200	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2201	{
mbed_official	330:c80ac197fa6a	2202	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	330:c80ac197fa6a	2203	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	2204
mbed_official	330:c80ac197fa6a	2205	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	2206	{
mbed_official	330:c80ac197fa6a	2207	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2208	{
mbed_official	330:c80ac197fa6a	2209	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	2210	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2211	}
mbed_official	330:c80ac197fa6a	2212	SPI_CloseTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2213	}
mbed_official	330:c80ac197fa6a	2214	}
mbed_official	330:c80ac197fa6a	2215
mbed_official	330:c80ac197fa6a	2216	/**
mbed_official	330:c80ac197fa6a	2217	* @brief Handle the data 16Bit transmit in Interrupt mode
mbed_official	330:c80ac197fa6a	2218	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2219	*/
mbed_official	330:c80ac197fa6a	2220	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2221	{
mbed_official	330:c80ac197fa6a	2222	/* Transmit data in 16 Bit mode */
mbed_official	330:c80ac197fa6a	2223	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	330:c80ac197fa6a	2224	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	330:c80ac197fa6a	2225	hspi->TxXferCount--;
mbed_official	330:c80ac197fa6a	2226
mbed_official	330:c80ac197fa6a	2227	if(hspi->TxXferCount == 0)
mbed_official	330:c80ac197fa6a	2228	{
mbed_official	330:c80ac197fa6a	2229	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2230	{
mbed_official	330:c80ac197fa6a	2231	/* Enable CRC Transmission */
mbed_official	330:c80ac197fa6a	2232	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	330:c80ac197fa6a	2233	}
mbed_official	330:c80ac197fa6a	2234	SPI_CloseTx_ISR(hspi);
mbed_official	330:c80ac197fa6a	2235	}
mbed_official	330:c80ac197fa6a	2236	}
mbed_official	330:c80ac197fa6a	2237
mbed_official	330:c80ac197fa6a	2238	/**
mbed_official	330:c80ac197fa6a	2239	* @brief This function handles SPI Communication Timeout.
mbed_official	330:c80ac197fa6a	2240	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2241	* @param Flag : SPI flag to check
mbed_official	330:c80ac197fa6a	2242	* @param State : flag state to check
mbed_official	330:c80ac197fa6a	2243	* @param Timeout : Timeout duration
mbed_official	330:c80ac197fa6a	2244	* @retval HAL status
mbed_official	330:c80ac197fa6a	2245	*/
mbed_official	330:c80ac197fa6a	2246	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	2247	{
mbed_official	330:c80ac197fa6a	2248	uint32_t tickstart = HAL_GetTick();
mbed_official	330:c80ac197fa6a	2249
mbed_official	330:c80ac197fa6a	2250	while((hspi->Instance->SR & Flag) != State)
mbed_official	330:c80ac197fa6a	2251	{
mbed_official	330:c80ac197fa6a	2252	if(Timeout != HAL_MAX_DELAY)
mbed_official	330:c80ac197fa6a	2253	{
mbed_official	330:c80ac197fa6a	2254	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
mbed_official	330:c80ac197fa6a	2255	{
mbed_official	330:c80ac197fa6a	2256	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	330:c80ac197fa6a	2257	on both master and slave sides in order to resynchronize the master
mbed_official	330:c80ac197fa6a	2258	and slave for their respective CRC calculation */
mbed_official	330:c80ac197fa6a	2259
mbed_official	330:c80ac197fa6a	2260	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	330:c80ac197fa6a	2261	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	2262
mbed_official	330:c80ac197fa6a	2263	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	330:c80ac197fa6a	2264	{
mbed_official	330:c80ac197fa6a	2265	/* Disable SPI peripheral */
mbed_official	330:c80ac197fa6a	2266	__HAL_SPI_DISABLE(hspi);
mbed_official	330:c80ac197fa6a	2267	}
mbed_official	330:c80ac197fa6a	2268
mbed_official	330:c80ac197fa6a	2269	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	2270	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2271	{
mbed_official	330:c80ac197fa6a	2272	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	2273	}
mbed_official	330:c80ac197fa6a	2274
mbed_official	330:c80ac197fa6a	2275	hspi->State= HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2276
mbed_official	330:c80ac197fa6a	2277	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	2278	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	2279
mbed_official	330:c80ac197fa6a	2280	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2281	}
mbed_official	330:c80ac197fa6a	2282	}
mbed_official	330:c80ac197fa6a	2283	}
mbed_official	330:c80ac197fa6a	2284
mbed_official	330:c80ac197fa6a	2285	return HAL_OK;
mbed_official	330:c80ac197fa6a	2286	}
mbed_official	330:c80ac197fa6a	2287
mbed_official	330:c80ac197fa6a	2288	/**
mbed_official	330:c80ac197fa6a	2289	* @brief This function handles SPI Communication Timeout.
mbed_official	330:c80ac197fa6a	2290	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2291	* @param Flag: Fifo flag to check
mbed_official	330:c80ac197fa6a	2292	* @param State: Fifo state to check
mbed_official	330:c80ac197fa6a	2293	* @param Timeout : Timeout duration
mbed_official	330:c80ac197fa6a	2294	* @retval HAL status
mbed_official	330:c80ac197fa6a	2295	*/
mbed_official	330:c80ac197fa6a	2296	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	2297	{
mbed_official	330:c80ac197fa6a	2298	__IO uint8_t tmpreg;
mbed_official	330:c80ac197fa6a	2299	uint32_t tickstart = HAL_GetTick();
mbed_official	330:c80ac197fa6a	2300
mbed_official	330:c80ac197fa6a	2301	while((hspi->Instance->SR & Flag) != State)
mbed_official	330:c80ac197fa6a	2302	{
mbed_official	330:c80ac197fa6a	2303	if((Flag == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official	330:c80ac197fa6a	2304	{
mbed_official	330:c80ac197fa6a	2305	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
mbed_official	632:7687fb9c4f91	2306	UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official	330:c80ac197fa6a	2307	}
mbed_official	330:c80ac197fa6a	2308	if(Timeout != HAL_MAX_DELAY)
mbed_official	330:c80ac197fa6a	2309	{
mbed_official	330:c80ac197fa6a	2310	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
mbed_official	330:c80ac197fa6a	2311	{
mbed_official	330:c80ac197fa6a	2312	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	330:c80ac197fa6a	2313	on both master and slave sides in order to resynchronize the master
mbed_official	330:c80ac197fa6a	2314	and slave for their respective CRC calculation */
mbed_official	330:c80ac197fa6a	2315
mbed_official	330:c80ac197fa6a	2316	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	330:c80ac197fa6a	2317	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	2318
mbed_official	330:c80ac197fa6a	2319	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	330:c80ac197fa6a	2320	{
mbed_official	330:c80ac197fa6a	2321	/* Disable SPI peripheral */
mbed_official	330:c80ac197fa6a	2322	__HAL_SPI_DISABLE(hspi);
mbed_official	330:c80ac197fa6a	2323	}
mbed_official	330:c80ac197fa6a	2324
mbed_official	330:c80ac197fa6a	2325	/* Reset CRC Calculation */
mbed_official	330:c80ac197fa6a	2326	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	330:c80ac197fa6a	2327	{
mbed_official	330:c80ac197fa6a	2328	__HAL_SPI_RESET_CRC(hspi);
mbed_official	330:c80ac197fa6a	2329	}
mbed_official	330:c80ac197fa6a	2330
mbed_official	330:c80ac197fa6a	2331	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2332
mbed_official	330:c80ac197fa6a	2333	/* Process Unlocked */
mbed_official	330:c80ac197fa6a	2334	__HAL_UNLOCK(hspi);
mbed_official	330:c80ac197fa6a	2335
mbed_official	330:c80ac197fa6a	2336	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2337	}
mbed_official	330:c80ac197fa6a	2338	}
mbed_official	330:c80ac197fa6a	2339	}
mbed_official	330:c80ac197fa6a	2340
mbed_official	330:c80ac197fa6a	2341	return HAL_OK;
mbed_official	330:c80ac197fa6a	2342	}
mbed_official	330:c80ac197fa6a	2343
mbed_official	330:c80ac197fa6a	2344	/**
mbed_official	330:c80ac197fa6a	2345	* @brief This function handles the check of the RX transaction complete.
mbed_official	330:c80ac197fa6a	2346	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2347	* @param Timeout : Timeout duration
mbed_official	330:c80ac197fa6a	2348	*/
mbed_official	330:c80ac197fa6a	2349	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	2350	{
mbed_official	330:c80ac197fa6a	2351	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	330:c80ac197fa6a	2352	{
mbed_official	330:c80ac197fa6a	2353	/* Disable SPI peripheral */
mbed_official	330:c80ac197fa6a	2354	__HAL_SPI_DISABLE(hspi);
mbed_official	330:c80ac197fa6a	2355	}
mbed_official	330:c80ac197fa6a	2356	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	2357	{
mbed_official	330:c80ac197fa6a	2358	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	330:c80ac197fa6a	2359	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2360	}
mbed_official	330:c80ac197fa6a	2361	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	2362	{
mbed_official	330:c80ac197fa6a	2363	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	330:c80ac197fa6a	2364	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2365	}
mbed_official	330:c80ac197fa6a	2366
mbed_official	330:c80ac197fa6a	2367	return HAL_OK;
mbed_official	330:c80ac197fa6a	2368	}
mbed_official	330:c80ac197fa6a	2369
mbed_official	330:c80ac197fa6a	2370	/**
mbed_official	330:c80ac197fa6a	2371	* @brief This function handles the check of the RXTX or TX transaction complete.
mbed_official	330:c80ac197fa6a	2372	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2373	* @param Timeout : Timeout duration
mbed_official	330:c80ac197fa6a	2374	*/
mbed_official	330:c80ac197fa6a	2375	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official	330:c80ac197fa6a	2376	{
mbed_official	330:c80ac197fa6a	2377	/* Procedure to check the transaction complete */
mbed_official	330:c80ac197fa6a	2378	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	2379	{
mbed_official	330:c80ac197fa6a	2380	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	330:c80ac197fa6a	2381	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2382	}
mbed_official	330:c80ac197fa6a	2383	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	2384	{
mbed_official	330:c80ac197fa6a	2385	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	330:c80ac197fa6a	2386	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2387	}
mbed_official	330:c80ac197fa6a	2388	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	330:c80ac197fa6a	2389	{
mbed_official	330:c80ac197fa6a	2390	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	330:c80ac197fa6a	2391	return HAL_TIMEOUT;
mbed_official	330:c80ac197fa6a	2392	}
mbed_official	330:c80ac197fa6a	2393	return HAL_OK;
mbed_official	330:c80ac197fa6a	2394	}
mbed_official	330:c80ac197fa6a	2395
mbed_official	330:c80ac197fa6a	2396	/**
mbed_official	330:c80ac197fa6a	2397	* @brief This function handles the close of the RXTX transaction.
mbed_official	330:c80ac197fa6a	2398	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2399	*/
mbed_official	330:c80ac197fa6a	2400	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2401	{
mbed_official	330:c80ac197fa6a	2402	/* Disable ERR interrupt */
mbed_official	330:c80ac197fa6a	2403	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official	330:c80ac197fa6a	2404
mbed_official	330:c80ac197fa6a	2405	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	2406	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	2407
mbed_official	330:c80ac197fa6a	2408	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	2409	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	2410	{
mbed_official	330:c80ac197fa6a	2411	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2412	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	2413	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	2414	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	2415	}
mbed_official	330:c80ac197fa6a	2416	else
mbed_official	330:c80ac197fa6a	2417	{
mbed_official	330:c80ac197fa6a	2418	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	2419	{
mbed_official	330:c80ac197fa6a	2420	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	330:c80ac197fa6a	2421	{
mbed_official	330:c80ac197fa6a	2422	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2423	HAL_SPI_RxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	2424	}
mbed_official	330:c80ac197fa6a	2425	else
mbed_official	330:c80ac197fa6a	2426	{
mbed_official	330:c80ac197fa6a	2427	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2428	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	2429	}
mbed_official	330:c80ac197fa6a	2430	}
mbed_official	330:c80ac197fa6a	2431	else
mbed_official	330:c80ac197fa6a	2432	{
mbed_official	330:c80ac197fa6a	2433	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2434	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	2435	}
mbed_official	330:c80ac197fa6a	2436	}
mbed_official	330:c80ac197fa6a	2437	}
mbed_official	330:c80ac197fa6a	2438
mbed_official	330:c80ac197fa6a	2439	/**
mbed_official	330:c80ac197fa6a	2440	* @brief This function handles the close of the RX transaction.
mbed_official	330:c80ac197fa6a	2441	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2442	*/
mbed_official	330:c80ac197fa6a	2443	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2444	{
mbed_official	330:c80ac197fa6a	2445	/* Disable RXNE and ERR interrupt */
mbed_official	330:c80ac197fa6a	2446	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	2447
mbed_official	330:c80ac197fa6a	2448	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	2449	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	2450
mbed_official	330:c80ac197fa6a	2451	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2452
mbed_official	330:c80ac197fa6a	2453	/* Check if CRC error occurred */
mbed_official	330:c80ac197fa6a	2454	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	330:c80ac197fa6a	2455	{
mbed_official	330:c80ac197fa6a	2456	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	330:c80ac197fa6a	2457	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	330:c80ac197fa6a	2458	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	2459	}
mbed_official	330:c80ac197fa6a	2460	else
mbed_official	330:c80ac197fa6a	2461	{
mbed_official	330:c80ac197fa6a	2462	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	2463	{
mbed_official	330:c80ac197fa6a	2464	HAL_SPI_RxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	2465	}
mbed_official	330:c80ac197fa6a	2466	else
mbed_official	330:c80ac197fa6a	2467	{
mbed_official	330:c80ac197fa6a	2468	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	2469	}
mbed_official	330:c80ac197fa6a	2470	}
mbed_official	330:c80ac197fa6a	2471	}
mbed_official	330:c80ac197fa6a	2472
mbed_official	330:c80ac197fa6a	2473	/**
mbed_official	330:c80ac197fa6a	2474	* @brief This function handles the close of the TX transaction.
mbed_official	330:c80ac197fa6a	2475	* @param hspi: SPI handle
mbed_official	330:c80ac197fa6a	2476	*/
mbed_official	330:c80ac197fa6a	2477	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	330:c80ac197fa6a	2478	{
mbed_official	330:c80ac197fa6a	2479	/* Disable TXE and ERR interrupt */
mbed_official	330:c80ac197fa6a	2480	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	330:c80ac197fa6a	2481
mbed_official	330:c80ac197fa6a	2482	/* Check the end of the transaction */
mbed_official	330:c80ac197fa6a	2483	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	330:c80ac197fa6a	2484
mbed_official	330:c80ac197fa6a	2485	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	330:c80ac197fa6a	2486	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	330:c80ac197fa6a	2487	{
mbed_official	330:c80ac197fa6a	2488	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	330:c80ac197fa6a	2489	}
mbed_official	330:c80ac197fa6a	2490
mbed_official	330:c80ac197fa6a	2491	hspi->State = HAL_SPI_STATE_READY;
mbed_official	330:c80ac197fa6a	2492	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	330:c80ac197fa6a	2493	{
mbed_official	330:c80ac197fa6a	2494	HAL_SPI_ErrorCallback(hspi);
mbed_official	330:c80ac197fa6a	2495	}
mbed_official	330:c80ac197fa6a	2496	else
mbed_official	330:c80ac197fa6a	2497	{
mbed_official	330:c80ac197fa6a	2498	HAL_SPI_TxCpltCallback(hspi);
mbed_official	330:c80ac197fa6a	2499	}
mbed_official	330:c80ac197fa6a	2500	}
mbed_official	330:c80ac197fa6a	2501
mbed_official	330:c80ac197fa6a	2502	/**
mbed_official	330:c80ac197fa6a	2503	* @}
mbed_official	330:c80ac197fa6a	2504	*/
mbed_official	330:c80ac197fa6a	2505
mbed_official	330:c80ac197fa6a	2506	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	330:c80ac197fa6a	2507	/**
mbed_official	330:c80ac197fa6a	2508	* @}
mbed_official	330:c80ac197fa6a	2509	*/
mbed_official	330:c80ac197fa6a	2510
mbed_official	330:c80ac197fa6a	2511	/**
mbed_official	330:c80ac197fa6a	2512	* @}
mbed_official	330:c80ac197fa6a	2513	*/
mbed_official	330:c80ac197fa6a	2514
mbed_official	330:c80ac197fa6a	2515	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/