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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c@632:7687fb9c4f91, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 14:00:11 2015 +0100
Revision:
632:7687fb9c4f91
Parent:
385:be64abf45658
Child:
634:ac7d6880524d
Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0



Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/



NUCLEO_F303K8 - add support of the STM32F303K8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 330:c80ac197fa6a 1 /**
mbed_official 330:c80ac197fa6a 2 ******************************************************************************
mbed_official 330:c80ac197fa6a 3 * @file stm32f3xx_hal_rcc.c
mbed_official 330:c80ac197fa6a 4 * @author MCD Application Team
mbed_official 632:7687fb9c4f91 5 * @version V1.1.1
mbed_official 632:7687fb9c4f91 6 * @date 19-June-2015
mbed_official 330:c80ac197fa6a 7 * @brief RCC HAL module driver.
mbed_official 330:c80ac197fa6a 8 * This file provides firmware functions to manage the following
mbed_official 330:c80ac197fa6a 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official 330:c80ac197fa6a 10 * + Initialization and de-initialization functions
mbed_official 330:c80ac197fa6a 11 * + Peripheral Control functions
mbed_official 330:c80ac197fa6a 12 *
mbed_official 330:c80ac197fa6a 13 @verbatim
mbed_official 330:c80ac197fa6a 14 ==============================================================================
mbed_official 330:c80ac197fa6a 15 ##### RCC specific features #####
mbed_official 330:c80ac197fa6a 16 ==============================================================================
mbed_official 330:c80ac197fa6a 17 [..]
mbed_official 330:c80ac197fa6a 18 After reset the device is running from Internal High Speed oscillator
mbed_official 330:c80ac197fa6a 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
mbed_official 330:c80ac197fa6a 20 and all peripherals are off except internal SRAM, Flash and JTAG.
mbed_official 330:c80ac197fa6a 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 330:c80ac197fa6a 22 all peripherals mapped on these busses are running at HSI speed.
mbed_official 330:c80ac197fa6a 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official 330:c80ac197fa6a 24 (+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official 330:c80ac197fa6a 25 are assigned to be used for debug purpose.
mbed_official 330:c80ac197fa6a 26
mbed_official 330:c80ac197fa6a 27 [..]
mbed_official 330:c80ac197fa6a 28 Once the device started from reset, the user application has to:
mbed_official 330:c80ac197fa6a 29 (+) Configure the clock source to be used to drive the System clock
mbed_official 330:c80ac197fa6a 30 (if the application needs higher frequency/performance)
mbed_official 330:c80ac197fa6a 31 (+) Configure the System clock frequency and Flash settings
mbed_official 330:c80ac197fa6a 32 (+) Configure the AHB and APB busses prescalers
mbed_official 330:c80ac197fa6a 33 (+) Enable the clock for the peripheral(s) to be used
mbed_official 330:c80ac197fa6a 34 (+) Configure the clock source(s) for peripherals which clocks are not
mbed_official 330:c80ac197fa6a 35 derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
mbed_official 330:c80ac197fa6a 36 @endverbatim
mbed_official 330:c80ac197fa6a 37 ******************************************************************************
mbed_official 330:c80ac197fa6a 38 * @attention
mbed_official 330:c80ac197fa6a 39 *
mbed_official 632:7687fb9c4f91 40 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 330:c80ac197fa6a 41 *
mbed_official 330:c80ac197fa6a 42 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 330:c80ac197fa6a 43 * are permitted provided that the following conditions are met:
mbed_official 330:c80ac197fa6a 44 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 330:c80ac197fa6a 45 * this list of conditions and the following disclaimer.
mbed_official 330:c80ac197fa6a 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 330:c80ac197fa6a 47 * this list of conditions and the following disclaimer in the documentation
mbed_official 330:c80ac197fa6a 48 * and/or other materials provided with the distribution.
mbed_official 330:c80ac197fa6a 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 330:c80ac197fa6a 50 * may be used to endorse or promote products derived from this software
mbed_official 330:c80ac197fa6a 51 * without specific prior written permission.
mbed_official 330:c80ac197fa6a 52 *
mbed_official 330:c80ac197fa6a 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 330:c80ac197fa6a 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 330:c80ac197fa6a 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 330:c80ac197fa6a 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 330:c80ac197fa6a 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 330:c80ac197fa6a 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 330:c80ac197fa6a 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 330:c80ac197fa6a 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 330:c80ac197fa6a 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 330:c80ac197fa6a 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 330:c80ac197fa6a 63 *
mbed_official 330:c80ac197fa6a 64 ******************************************************************************
mbed_official 330:c80ac197fa6a 65 */
mbed_official 330:c80ac197fa6a 66
mbed_official 330:c80ac197fa6a 67 /* Includes ------------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 68 #include "stm32f3xx_hal.h"
mbed_official 330:c80ac197fa6a 69
mbed_official 330:c80ac197fa6a 70 /** @addtogroup STM32F3xx_HAL_Driver
mbed_official 330:c80ac197fa6a 71 * @{
mbed_official 330:c80ac197fa6a 72 */
mbed_official 330:c80ac197fa6a 73
mbed_official 330:c80ac197fa6a 74 /** @defgroup RCC RCC HAL module driver
mbed_official 330:c80ac197fa6a 75 * @brief RCC HAL module driver
mbed_official 330:c80ac197fa6a 76 * @{
mbed_official 330:c80ac197fa6a 77 */
mbed_official 330:c80ac197fa6a 78
mbed_official 330:c80ac197fa6a 79 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 330:c80ac197fa6a 80
mbed_official 330:c80ac197fa6a 81 /* Private typedef -----------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 82 /* Private define ------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 83 /** @defgroup RCC_Private_Define RCC Private Define
mbed_official 330:c80ac197fa6a 84 * @{
mbed_official 330:c80ac197fa6a 85 */
mbed_official 330:c80ac197fa6a 86 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official 330:c80ac197fa6a 87 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 330:c80ac197fa6a 88 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 330:c80ac197fa6a 89 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 330:c80ac197fa6a 90 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official 330:c80ac197fa6a 91 /**
mbed_official 330:c80ac197fa6a 92 * @}
mbed_official 330:c80ac197fa6a 93 */
mbed_official 330:c80ac197fa6a 94
mbed_official 330:c80ac197fa6a 95 /* Private macro -------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 96 /** @defgroup RCC_Private_Macros RCC Private Macros
mbed_official 330:c80ac197fa6a 97 * @{
mbed_official 330:c80ac197fa6a 98 */
mbed_official 330:c80ac197fa6a 99 #define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official 330:c80ac197fa6a 100 #define MCO_GPIO_PORT GPIOA
mbed_official 330:c80ac197fa6a 101 #define MCO_PIN GPIO_PIN_8
mbed_official 330:c80ac197fa6a 102 /**
mbed_official 330:c80ac197fa6a 103 * @}
mbed_official 330:c80ac197fa6a 104 */
mbed_official 330:c80ac197fa6a 105
mbed_official 330:c80ac197fa6a 106 /* Private variables ---------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 107 /** @defgroup RCC_Private_Variables RCC Private Variables
mbed_official 330:c80ac197fa6a 108 * @{
mbed_official 330:c80ac197fa6a 109 */
mbed_official 330:c80ac197fa6a 110 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 330:c80ac197fa6a 111 /**
mbed_official 330:c80ac197fa6a 112 * @}
mbed_official 330:c80ac197fa6a 113 */
mbed_official 330:c80ac197fa6a 114
mbed_official 330:c80ac197fa6a 115 /* Private function prototypes -----------------------------------------------*/
mbed_official 330:c80ac197fa6a 116 /* Exported functions ---------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 117
mbed_official 330:c80ac197fa6a 118 /** @defgroup RCC_Exported_Functions RCC Exported Functions
mbed_official 330:c80ac197fa6a 119 * @{
mbed_official 330:c80ac197fa6a 120 */
mbed_official 330:c80ac197fa6a 121
mbed_official 330:c80ac197fa6a 122 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 330:c80ac197fa6a 123 * @brief Initialization and Configuration functions
mbed_official 330:c80ac197fa6a 124 *
mbed_official 330:c80ac197fa6a 125 @verbatim
mbed_official 330:c80ac197fa6a 126 ===============================================================================
mbed_official 330:c80ac197fa6a 127 ##### Initialization and de-initialization functions #####
mbed_official 330:c80ac197fa6a 128 ===============================================================================
mbed_official 330:c80ac197fa6a 129 [..]
mbed_official 330:c80ac197fa6a 130 This section provide functions allowing to configure the internal/external oscillators
mbed_official 330:c80ac197fa6a 131 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
mbed_official 330:c80ac197fa6a 132 and APB2).
mbed_official 330:c80ac197fa6a 133
mbed_official 330:c80ac197fa6a 134 [..] Internal/external clock and PLL configuration
mbed_official 330:c80ac197fa6a 135 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
mbed_official 330:c80ac197fa6a 136 the PLL as System clock source.
mbed_official 330:c80ac197fa6a 137 The HSI clock can be used also to clock the USART and I2C peripherals.
mbed_official 330:c80ac197fa6a 138
mbed_official 330:c80ac197fa6a 139 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
mbed_official 330:c80ac197fa6a 140 clock source.
mbed_official 330:c80ac197fa6a 141
mbed_official 330:c80ac197fa6a 142 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
mbed_official 330:c80ac197fa6a 143 through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official 330:c80ac197fa6a 144
mbed_official 330:c80ac197fa6a 145 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 330:c80ac197fa6a 146
mbed_official 330:c80ac197fa6a 147 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
mbed_official 330:c80ac197fa6a 148 (+@) The first output is used to generate the high speed system clock (up to 72 MHz)
mbed_official 330:c80ac197fa6a 149 (+@) The second output is used to generate the clock for the USB FS (48 MHz)
mbed_official 330:c80ac197fa6a 150 (+@) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
mbed_official 330:c80ac197fa6a 151 (+@) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
mbed_official 330:c80ac197fa6a 152
mbed_official 330:c80ac197fa6a 153 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official 330:c80ac197fa6a 154 and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official 330:c80ac197fa6a 155 clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official 330:c80ac197fa6a 156 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
mbed_official 330:c80ac197fa6a 157 (Non-Maskable Interrupt) exception vector.
mbed_official 330:c80ac197fa6a 158
mbed_official 330:c80ac197fa6a 159 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
mbed_official 330:c80ac197fa6a 160 clock (divided by 2) output on pin (such as PA8 pin).
mbed_official 330:c80ac197fa6a 161
mbed_official 330:c80ac197fa6a 162 [..] System, AHB and APB busses clocks configuration
mbed_official 330:c80ac197fa6a 163 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official 330:c80ac197fa6a 164 HSE and PLL.
mbed_official 330:c80ac197fa6a 165 The AHB clock (HCLK) is derived from System clock through configurable
mbed_official 330:c80ac197fa6a 166 prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official 330:c80ac197fa6a 167 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official 330:c80ac197fa6a 168 from AHB clock through configurable prescalers and used to clock
mbed_official 330:c80ac197fa6a 169 the peripherals mapped on these busses. You can use
mbed_official 330:c80ac197fa6a 170 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official 330:c80ac197fa6a 171
mbed_official 330:c80ac197fa6a 172 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official 330:c80ac197fa6a 173 (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
mbed_official 330:c80ac197fa6a 174 (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
mbed_official 330:c80ac197fa6a 175 (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
mbed_official 330:c80ac197fa6a 176 (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
mbed_official 330:c80ac197fa6a 177 (+@) The ADC clock which is derived from PLL output.
mbed_official 330:c80ac197fa6a 178 (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
mbed_official 330:c80ac197fa6a 179 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
mbed_official 330:c80ac197fa6a 180 frequency must be higher or equal to the RTC clock frequency.
mbed_official 330:c80ac197fa6a 181 (+@) IWDG clock which is always the LSI clock.
mbed_official 330:c80ac197fa6a 182
mbed_official 330:c80ac197fa6a 183 (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
mbed_official 330:c80ac197fa6a 184 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
mbed_official 330:c80ac197fa6a 185 +-----------------------------------------------+
mbed_official 330:c80ac197fa6a 186 | Latency | SYSCLK clock frequency (MHz) |
mbed_official 330:c80ac197fa6a 187 |---------------|-------------------------------|
mbed_official 330:c80ac197fa6a 188 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
mbed_official 330:c80ac197fa6a 189 |---------------|-------------------------------|
mbed_official 330:c80ac197fa6a 190 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
mbed_official 330:c80ac197fa6a 191 |---------------|-------------------------------|
mbed_official 330:c80ac197fa6a 192 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
mbed_official 330:c80ac197fa6a 193 +-----------------------------------------------+
mbed_official 330:c80ac197fa6a 194
mbed_official 330:c80ac197fa6a 195 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
mbed_official 330:c80ac197fa6a 196 prefetch is disabled.
mbed_official 330:c80ac197fa6a 197
mbed_official 330:c80ac197fa6a 198 @endverbatim
mbed_official 330:c80ac197fa6a 199 * @{
mbed_official 330:c80ac197fa6a 200 */
mbed_official 330:c80ac197fa6a 201
mbed_official 330:c80ac197fa6a 202 /**
mbed_official 330:c80ac197fa6a 203 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 330:c80ac197fa6a 204 * @note The default reset state of the clock configuration is given below:
mbed_official 330:c80ac197fa6a 205 * - HSI ON and used as system clock source
mbed_official 330:c80ac197fa6a 206 * - HSE and PLL OFF
mbed_official 330:c80ac197fa6a 207 * - AHB, APB1 and APB2 prescaler set to 1.
mbed_official 330:c80ac197fa6a 208 * - CSS, MCO OFF
mbed_official 330:c80ac197fa6a 209 * - All interrupts disabled
mbed_official 330:c80ac197fa6a 210 * @note This function doesn't modify the configuration of the
mbed_official 330:c80ac197fa6a 211 * - Peripheral clocks
mbed_official 330:c80ac197fa6a 212 * - LSI, LSE and RTC clocks
mbed_official 330:c80ac197fa6a 213 * @retval None
mbed_official 330:c80ac197fa6a 214 */
mbed_official 330:c80ac197fa6a 215 void HAL_RCC_DeInit(void)
mbed_official 330:c80ac197fa6a 216 {
mbed_official 330:c80ac197fa6a 217 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
mbed_official 330:c80ac197fa6a 218 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
mbed_official 330:c80ac197fa6a 219
mbed_official 330:c80ac197fa6a 220 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
mbed_official 330:c80ac197fa6a 221 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
mbed_official 330:c80ac197fa6a 222
mbed_official 330:c80ac197fa6a 223 /* Reset HSEON, CSSON, PLLON bits */
mbed_official 330:c80ac197fa6a 224 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
mbed_official 330:c80ac197fa6a 225
mbed_official 330:c80ac197fa6a 226 /* Reset HSEBYP bit */
mbed_official 330:c80ac197fa6a 227 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official 330:c80ac197fa6a 228
mbed_official 330:c80ac197fa6a 229 /* Reset CFGR register */
mbed_official 330:c80ac197fa6a 230 CLEAR_REG(RCC->CFGR);
mbed_official 330:c80ac197fa6a 231
mbed_official 330:c80ac197fa6a 232 /* Reset CFGR2 register */
mbed_official 330:c80ac197fa6a 233 CLEAR_REG(RCC->CFGR2);
mbed_official 330:c80ac197fa6a 234
mbed_official 330:c80ac197fa6a 235 /* Reset CFGR3 register */
mbed_official 330:c80ac197fa6a 236 CLEAR_REG(RCC->CFGR3);
mbed_official 330:c80ac197fa6a 237
mbed_official 330:c80ac197fa6a 238 /* Disable all interrupts */
mbed_official 330:c80ac197fa6a 239 CLEAR_REG(RCC->CIR);
mbed_official 330:c80ac197fa6a 240 }
mbed_official 330:c80ac197fa6a 241
mbed_official 330:c80ac197fa6a 242 /**
mbed_official 330:c80ac197fa6a 243 * @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official 330:c80ac197fa6a 244 * RCC_OscInitTypeDef.
mbed_official 330:c80ac197fa6a 245 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 330:c80ac197fa6a 246 * contains the configuration information for the RCC Oscillators.
mbed_official 330:c80ac197fa6a 247 * @note The PLL is not disabled when used as system clock.
mbed_official 330:c80ac197fa6a 248 * @retval HAL status
mbed_official 330:c80ac197fa6a 249 */
mbed_official 330:c80ac197fa6a 250 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 330:c80ac197fa6a 251 {
mbed_official 330:c80ac197fa6a 252 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 253 }
mbed_official 330:c80ac197fa6a 254
mbed_official 330:c80ac197fa6a 255 /**
mbed_official 330:c80ac197fa6a 256 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official 330:c80ac197fa6a 257 * parameters in the RCC_ClkInitStruct.
mbed_official 330:c80ac197fa6a 258 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 330:c80ac197fa6a 259 * contains the configuration information for the RCC peripheral.
mbed_official 330:c80ac197fa6a 260 * @param FLatency: FLASH Latency
mbed_official 330:c80ac197fa6a 261 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 262 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
mbed_official 330:c80ac197fa6a 263 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
mbed_official 330:c80ac197fa6a 264 * @arg FLASH_LATENCY_2: FLASH 2 Latency cycle
mbed_official 330:c80ac197fa6a 265 *
mbed_official 330:c80ac197fa6a 266 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 330:c80ac197fa6a 267 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official 330:c80ac197fa6a 268 *
mbed_official 330:c80ac197fa6a 269 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 330:c80ac197fa6a 270 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 330:c80ac197fa6a 271 * of failure of the HSE used directly or indirectly as system clock
mbed_official 330:c80ac197fa6a 272 * (if the Clock Security System CSS is enabled).
mbed_official 330:c80ac197fa6a 273 *
mbed_official 330:c80ac197fa6a 274 * @note A switch from one clock source to another occurs only if the target
mbed_official 330:c80ac197fa6a 275 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 330:c80ac197fa6a 276 * If a clock source which is not yet ready is selected, the switch will
mbed_official 330:c80ac197fa6a 277 * occur when the clock source will be ready.
mbed_official 330:c80ac197fa6a 278 * @retval HAL status
mbed_official 330:c80ac197fa6a 279 */
mbed_official 330:c80ac197fa6a 280 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official 330:c80ac197fa6a 281 {
mbed_official 330:c80ac197fa6a 282 uint32_t tickstart = 0;
mbed_official 330:c80ac197fa6a 283
mbed_official 330:c80ac197fa6a 284 /* Check the parameters */
mbed_official 632:7687fb9c4f91 285 assert_param(RCC_ClkInitStruct != NULL);
mbed_official 330:c80ac197fa6a 286 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official 330:c80ac197fa6a 287 assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official 330:c80ac197fa6a 288
mbed_official 330:c80ac197fa6a 289 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official 330:c80ac197fa6a 290 must be correctly programmed according to the frequency of the CPU clock
mbed_official 330:c80ac197fa6a 291 (HCLK) of the device. */
mbed_official 330:c80ac197fa6a 292
mbed_official 330:c80ac197fa6a 293 /* Increasing the CPU frequency */
mbed_official 330:c80ac197fa6a 294 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official 330:c80ac197fa6a 295 {
mbed_official 330:c80ac197fa6a 296 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 330:c80ac197fa6a 297 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 330:c80ac197fa6a 298
mbed_official 330:c80ac197fa6a 299 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 330:c80ac197fa6a 300 memory by reading the FLASH_ACR register */
mbed_official 330:c80ac197fa6a 301 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 330:c80ac197fa6a 302 {
mbed_official 330:c80ac197fa6a 303 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 304 }
mbed_official 330:c80ac197fa6a 305
mbed_official 330:c80ac197fa6a 306 /*-------------------------- HCLK Configuration ----------------------------*/
mbed_official 330:c80ac197fa6a 307 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 330:c80ac197fa6a 308 {
mbed_official 330:c80ac197fa6a 309 assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 330:c80ac197fa6a 310 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 330:c80ac197fa6a 311 }
mbed_official 330:c80ac197fa6a 312
mbed_official 330:c80ac197fa6a 313 /*------------------------- SYSCLK Configuration ---------------------------*/
mbed_official 330:c80ac197fa6a 314 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 330:c80ac197fa6a 315 {
mbed_official 330:c80ac197fa6a 316 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 330:c80ac197fa6a 317
mbed_official 330:c80ac197fa6a 318 /* HSE is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 319 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 330:c80ac197fa6a 320 {
mbed_official 330:c80ac197fa6a 321 /* Check the HSE ready flag */
mbed_official 330:c80ac197fa6a 322 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 330:c80ac197fa6a 323 {
mbed_official 330:c80ac197fa6a 324 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 325 }
mbed_official 330:c80ac197fa6a 326 }
mbed_official 330:c80ac197fa6a 327 /* PLL is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 328 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 330:c80ac197fa6a 329 {
mbed_official 330:c80ac197fa6a 330 /* Check the PLL ready flag */
mbed_official 330:c80ac197fa6a 331 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 330:c80ac197fa6a 332 {
mbed_official 330:c80ac197fa6a 333 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 334 }
mbed_official 330:c80ac197fa6a 335 }
mbed_official 330:c80ac197fa6a 336 /* HSI is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 337 else
mbed_official 330:c80ac197fa6a 338 {
mbed_official 330:c80ac197fa6a 339 /* Check the HSI ready flag */
mbed_official 330:c80ac197fa6a 340 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 330:c80ac197fa6a 341 {
mbed_official 330:c80ac197fa6a 342 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 343 }
mbed_official 330:c80ac197fa6a 344 }
mbed_official 330:c80ac197fa6a 345 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 330:c80ac197fa6a 346
mbed_official 330:c80ac197fa6a 347 /* Get timeout */
mbed_official 330:c80ac197fa6a 348 tickstart = HAL_GetTick();
mbed_official 330:c80ac197fa6a 349
mbed_official 330:c80ac197fa6a 350 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 330:c80ac197fa6a 351 {
mbed_official 330:c80ac197fa6a 352 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
mbed_official 330:c80ac197fa6a 353 {
mbed_official 330:c80ac197fa6a 354 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 355 {
mbed_official 330:c80ac197fa6a 356 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 357 }
mbed_official 330:c80ac197fa6a 358 }
mbed_official 330:c80ac197fa6a 359 }
mbed_official 330:c80ac197fa6a 360 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 330:c80ac197fa6a 361 {
mbed_official 330:c80ac197fa6a 362 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
mbed_official 330:c80ac197fa6a 363 {
mbed_official 330:c80ac197fa6a 364 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 365 {
mbed_official 330:c80ac197fa6a 366 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 367 }
mbed_official 330:c80ac197fa6a 368 }
mbed_official 330:c80ac197fa6a 369 }
mbed_official 330:c80ac197fa6a 370 else
mbed_official 330:c80ac197fa6a 371 {
mbed_official 330:c80ac197fa6a 372 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
mbed_official 330:c80ac197fa6a 373 {
mbed_official 330:c80ac197fa6a 374 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 375 {
mbed_official 330:c80ac197fa6a 376 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 377 }
mbed_official 330:c80ac197fa6a 378 }
mbed_official 330:c80ac197fa6a 379 }
mbed_official 330:c80ac197fa6a 380 }
mbed_official 330:c80ac197fa6a 381 }
mbed_official 330:c80ac197fa6a 382 /* Decreasing the CPU frequency */
mbed_official 330:c80ac197fa6a 383 else
mbed_official 330:c80ac197fa6a 384 {
mbed_official 330:c80ac197fa6a 385 /*-------------------------- HCLK Configuration ----------------------------*/
mbed_official 330:c80ac197fa6a 386 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 330:c80ac197fa6a 387 {
mbed_official 330:c80ac197fa6a 388 assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 330:c80ac197fa6a 389 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 330:c80ac197fa6a 390 }
mbed_official 330:c80ac197fa6a 391
mbed_official 330:c80ac197fa6a 392 /*------------------------- SYSCLK Configuration ---------------------------*/
mbed_official 330:c80ac197fa6a 393 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 330:c80ac197fa6a 394 {
mbed_official 330:c80ac197fa6a 395 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 330:c80ac197fa6a 396
mbed_official 330:c80ac197fa6a 397 /* HSE is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 398 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 330:c80ac197fa6a 399 {
mbed_official 330:c80ac197fa6a 400 /* Check the HSE ready flag */
mbed_official 330:c80ac197fa6a 401 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 330:c80ac197fa6a 402 {
mbed_official 330:c80ac197fa6a 403 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 404 }
mbed_official 330:c80ac197fa6a 405 }
mbed_official 330:c80ac197fa6a 406 /* PLL is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 407 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 330:c80ac197fa6a 408 {
mbed_official 330:c80ac197fa6a 409 /* Check the PLL ready flag */
mbed_official 330:c80ac197fa6a 410 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 330:c80ac197fa6a 411 {
mbed_official 330:c80ac197fa6a 412 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 413 }
mbed_official 330:c80ac197fa6a 414 }
mbed_official 330:c80ac197fa6a 415 /* HSI is selected as System Clock Source */
mbed_official 330:c80ac197fa6a 416 else
mbed_official 330:c80ac197fa6a 417 {
mbed_official 330:c80ac197fa6a 418 /* Check the HSI ready flag */
mbed_official 330:c80ac197fa6a 419 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 330:c80ac197fa6a 420 {
mbed_official 330:c80ac197fa6a 421 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 422 }
mbed_official 330:c80ac197fa6a 423 }
mbed_official 330:c80ac197fa6a 424 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 330:c80ac197fa6a 425
mbed_official 330:c80ac197fa6a 426 /* Get timeout */
mbed_official 330:c80ac197fa6a 427 tickstart = HAL_GetTick();
mbed_official 330:c80ac197fa6a 428
mbed_official 330:c80ac197fa6a 429 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 330:c80ac197fa6a 430 {
mbed_official 330:c80ac197fa6a 431 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
mbed_official 330:c80ac197fa6a 432 {
mbed_official 330:c80ac197fa6a 433 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 434 {
mbed_official 330:c80ac197fa6a 435 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 436 }
mbed_official 330:c80ac197fa6a 437 }
mbed_official 330:c80ac197fa6a 438 }
mbed_official 330:c80ac197fa6a 439 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 330:c80ac197fa6a 440 {
mbed_official 330:c80ac197fa6a 441 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
mbed_official 330:c80ac197fa6a 442 {
mbed_official 330:c80ac197fa6a 443 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 444 {
mbed_official 330:c80ac197fa6a 445 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 446 }
mbed_official 330:c80ac197fa6a 447 }
mbed_official 330:c80ac197fa6a 448 }
mbed_official 330:c80ac197fa6a 449 else
mbed_official 330:c80ac197fa6a 450 {
mbed_official 330:c80ac197fa6a 451 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
mbed_official 330:c80ac197fa6a 452 {
mbed_official 330:c80ac197fa6a 453 if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 330:c80ac197fa6a 454 {
mbed_official 330:c80ac197fa6a 455 return HAL_TIMEOUT;
mbed_official 330:c80ac197fa6a 456 }
mbed_official 330:c80ac197fa6a 457 }
mbed_official 330:c80ac197fa6a 458 }
mbed_official 330:c80ac197fa6a 459 }
mbed_official 330:c80ac197fa6a 460
mbed_official 330:c80ac197fa6a 461 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 330:c80ac197fa6a 462 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 330:c80ac197fa6a 463
mbed_official 330:c80ac197fa6a 464 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 330:c80ac197fa6a 465 memory by reading the FLASH_ACR register */
mbed_official 330:c80ac197fa6a 466 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 330:c80ac197fa6a 467 {
mbed_official 330:c80ac197fa6a 468 return HAL_ERROR;
mbed_official 330:c80ac197fa6a 469 }
mbed_official 330:c80ac197fa6a 470 }
mbed_official 330:c80ac197fa6a 471
mbed_official 330:c80ac197fa6a 472 /*-------------------------- PCLK1 Configuration ---------------------------*/
mbed_official 330:c80ac197fa6a 473 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official 330:c80ac197fa6a 474 {
mbed_official 330:c80ac197fa6a 475 assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official 330:c80ac197fa6a 476 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official 330:c80ac197fa6a 477 }
mbed_official 330:c80ac197fa6a 478
mbed_official 330:c80ac197fa6a 479 /*-------------------------- PCLK2 Configuration ---------------------------*/
mbed_official 330:c80ac197fa6a 480 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official 330:c80ac197fa6a 481 {
mbed_official 330:c80ac197fa6a 482 assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official 330:c80ac197fa6a 483 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official 330:c80ac197fa6a 484 }
mbed_official 330:c80ac197fa6a 485
mbed_official 330:c80ac197fa6a 486 /* Configure the source of time base considering new system clocks settings*/
mbed_official 330:c80ac197fa6a 487 HAL_InitTick (TICK_INT_PRIORITY);
mbed_official 330:c80ac197fa6a 488
mbed_official 330:c80ac197fa6a 489 return HAL_OK;
mbed_official 330:c80ac197fa6a 490 }
mbed_official 330:c80ac197fa6a 491
mbed_official 330:c80ac197fa6a 492 /**
mbed_official 330:c80ac197fa6a 493 * @}
mbed_official 330:c80ac197fa6a 494 */
mbed_official 330:c80ac197fa6a 495
mbed_official 330:c80ac197fa6a 496 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
mbed_official 330:c80ac197fa6a 497 * @brief RCC clocks control functions
mbed_official 330:c80ac197fa6a 498 *
mbed_official 330:c80ac197fa6a 499 @verbatim
mbed_official 330:c80ac197fa6a 500 ===============================================================================
mbed_official 330:c80ac197fa6a 501 ##### Peripheral Control functions #####
mbed_official 330:c80ac197fa6a 502 ===============================================================================
mbed_official 330:c80ac197fa6a 503 [..]
mbed_official 330:c80ac197fa6a 504 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 330:c80ac197fa6a 505 frequencies.
mbed_official 330:c80ac197fa6a 506
mbed_official 330:c80ac197fa6a 507 @endverbatim
mbed_official 330:c80ac197fa6a 508 * @{
mbed_official 330:c80ac197fa6a 509 */
mbed_official 330:c80ac197fa6a 510
mbed_official 330:c80ac197fa6a 511 /**
mbed_official 330:c80ac197fa6a 512 * @brief Selects the clock source to output on MCO pin(such as PA8).
mbed_official 330:c80ac197fa6a 513 * @note MCO pin (such as PA8) should be configured in alternate function mode.
mbed_official 330:c80ac197fa6a 514 * @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official 330:c80ac197fa6a 515 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 516 * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
mbed_official 330:c80ac197fa6a 517 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 330:c80ac197fa6a 518 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 519 * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
mbed_official 330:c80ac197fa6a 520 * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
mbed_official 330:c80ac197fa6a 521 * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
mbed_official 330:c80ac197fa6a 522 * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
mbed_official 330:c80ac197fa6a 523 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
mbed_official 330:c80ac197fa6a 524 * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
mbed_official 330:c80ac197fa6a 525 * @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official 330:c80ac197fa6a 526 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 527 * @arg RCC_MCO_NODIV: no division applied to MCO clock
mbed_official 330:c80ac197fa6a 528 * @retval None
mbed_official 330:c80ac197fa6a 529 */
mbed_official 330:c80ac197fa6a 530 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official 330:c80ac197fa6a 531 {
mbed_official 330:c80ac197fa6a 532 GPIO_InitTypeDef gpio;
mbed_official 330:c80ac197fa6a 533 /* Check the parameters */
mbed_official 330:c80ac197fa6a 534 assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official 330:c80ac197fa6a 535 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official 330:c80ac197fa6a 536 /* RCC_MCO */
mbed_official 330:c80ac197fa6a 537 assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
mbed_official 330:c80ac197fa6a 538
mbed_official 330:c80ac197fa6a 539 /* MCO Clock Enable */
mbed_official 330:c80ac197fa6a 540 __MCO_CLK_ENABLE();
mbed_official 330:c80ac197fa6a 541
mbed_official 330:c80ac197fa6a 542 /* Configue the MCO pin in alternate function mode */
mbed_official 330:c80ac197fa6a 543 gpio.Pin = MCO_PIN;
mbed_official 330:c80ac197fa6a 544 gpio.Mode = GPIO_MODE_AF_PP;
mbed_official 330:c80ac197fa6a 545 gpio.Speed = GPIO_SPEED_HIGH;
mbed_official 330:c80ac197fa6a 546 gpio.Pull = GPIO_NOPULL;
mbed_official 330:c80ac197fa6a 547 gpio.Alternate = GPIO_AF0_MCO;
mbed_official 330:c80ac197fa6a 548 HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
mbed_official 330:c80ac197fa6a 549
mbed_official 330:c80ac197fa6a 550 /* Configure the MCO clock source */
mbed_official 330:c80ac197fa6a 551 __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
mbed_official 330:c80ac197fa6a 552 }
mbed_official 330:c80ac197fa6a 553
mbed_official 330:c80ac197fa6a 554 /**
mbed_official 330:c80ac197fa6a 555 * @brief Enables the Clock Security System.
mbed_official 330:c80ac197fa6a 556 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 330:c80ac197fa6a 557 * is automatically disabled and an interrupt is generated to inform the
mbed_official 330:c80ac197fa6a 558 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 330:c80ac197fa6a 559 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 330:c80ac197fa6a 560 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 330:c80ac197fa6a 561 * @retval None
mbed_official 330:c80ac197fa6a 562 */
mbed_official 330:c80ac197fa6a 563 void HAL_RCC_EnableCSS(void)
mbed_official 330:c80ac197fa6a 564 {
mbed_official 330:c80ac197fa6a 565 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
mbed_official 330:c80ac197fa6a 566 }
mbed_official 330:c80ac197fa6a 567
mbed_official 330:c80ac197fa6a 568 /**
mbed_official 330:c80ac197fa6a 569 * @brief Disables the Clock Security System.
mbed_official 330:c80ac197fa6a 570 * @retval None
mbed_official 330:c80ac197fa6a 571 */
mbed_official 330:c80ac197fa6a 572 void HAL_RCC_DisableCSS(void)
mbed_official 330:c80ac197fa6a 573 {
mbed_official 330:c80ac197fa6a 574 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
mbed_official 330:c80ac197fa6a 575 }
mbed_official 330:c80ac197fa6a 576
mbed_official 330:c80ac197fa6a 577 /**
mbed_official 330:c80ac197fa6a 578 * @brief Returns the SYSCLK frequency
mbed_official 330:c80ac197fa6a 579 * @note The system frequency computed by this function is not the real
mbed_official 330:c80ac197fa6a 580 * frequency in the chip. It is calculated based on the predefined
mbed_official 330:c80ac197fa6a 581 * constant and the selected clock source:
mbed_official 330:c80ac197fa6a 582 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official 330:c80ac197fa6a 583 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
mbed_official 330:c80ac197fa6a 584 * divided by PREDIV factor(**)
mbed_official 330:c80ac197fa6a 585 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
mbed_official 330:c80ac197fa6a 586 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
mbed_official 330:c80ac197fa6a 587 * @note (*) HSI_VALUE is a constant defined in stm32f3xx.h file (default value
mbed_official 330:c80ac197fa6a 588 * 8 MHz).
mbed_official 330:c80ac197fa6a 589 * @note (**) HSE_VALUE is a constant defined in stm32f3xx.h file (default value
mbed_official 330:c80ac197fa6a 590 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 330:c80ac197fa6a 591 * frequency of the crystal used. Otherwise, this function may
mbed_official 330:c80ac197fa6a 592 * have wrong result.
mbed_official 330:c80ac197fa6a 593 *
mbed_official 330:c80ac197fa6a 594 * @note The result of this function could be not correct when using fractional
mbed_official 330:c80ac197fa6a 595 * value for HSE crystal.
mbed_official 330:c80ac197fa6a 596 *
mbed_official 330:c80ac197fa6a 597 * @note This function can be used by the user application to compute the
mbed_official 330:c80ac197fa6a 598 * baudrate for the communication peripherals or configure other parameters.
mbed_official 330:c80ac197fa6a 599 *
mbed_official 330:c80ac197fa6a 600 * @note Each time SYSCLK changes, this function must be called to update the
mbed_official 330:c80ac197fa6a 601 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 330:c80ac197fa6a 602 *
mbed_official 330:c80ac197fa6a 603 * @retval SYSCLK frequency
mbed_official 330:c80ac197fa6a 604 */
mbed_official 330:c80ac197fa6a 605 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official 330:c80ac197fa6a 606 {
mbed_official 330:c80ac197fa6a 607 return 0;
mbed_official 330:c80ac197fa6a 608 }
mbed_official 330:c80ac197fa6a 609
mbed_official 330:c80ac197fa6a 610 /**
mbed_official 330:c80ac197fa6a 611 * @brief Returns the HCLK frequency
mbed_official 330:c80ac197fa6a 612 * @note Each time HCLK changes, this function must be called to update the
mbed_official 330:c80ac197fa6a 613 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 330:c80ac197fa6a 614 *
mbed_official 330:c80ac197fa6a 615 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 330:c80ac197fa6a 616 * and updated within this function
mbed_official 330:c80ac197fa6a 617 *
mbed_official 330:c80ac197fa6a 618 * @retval HCLK frequency
mbed_official 330:c80ac197fa6a 619 */
mbed_official 330:c80ac197fa6a 620 uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official 330:c80ac197fa6a 621 {
mbed_official 330:c80ac197fa6a 622 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
mbed_official 330:c80ac197fa6a 623 return SystemCoreClock;
mbed_official 330:c80ac197fa6a 624 }
mbed_official 330:c80ac197fa6a 625
mbed_official 330:c80ac197fa6a 626 /**
mbed_official 330:c80ac197fa6a 627 * @brief Returns the PCLK1 frequency
mbed_official 330:c80ac197fa6a 628 * @note Each time PCLK1 changes, this function must be called to update the
mbed_official 330:c80ac197fa6a 629 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 330:c80ac197fa6a 630 * @retval PCLK1 frequency
mbed_official 330:c80ac197fa6a 631 */
mbed_official 330:c80ac197fa6a 632 uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official 330:c80ac197fa6a 633 {
mbed_official 330:c80ac197fa6a 634 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official 330:c80ac197fa6a 635 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
mbed_official 330:c80ac197fa6a 636 }
mbed_official 330:c80ac197fa6a 637
mbed_official 330:c80ac197fa6a 638 /**
mbed_official 330:c80ac197fa6a 639 * @brief Returns the PCLK2 frequency
mbed_official 330:c80ac197fa6a 640 * @note Each time PCLK2 changes, this function must be called to update the
mbed_official 330:c80ac197fa6a 641 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 330:c80ac197fa6a 642 * @retval PCLK2 frequency
mbed_official 330:c80ac197fa6a 643 */
mbed_official 330:c80ac197fa6a 644 uint32_t HAL_RCC_GetPCLK2Freq(void)
mbed_official 330:c80ac197fa6a 645 {
mbed_official 330:c80ac197fa6a 646 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official 330:c80ac197fa6a 647 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
mbed_official 330:c80ac197fa6a 648 }
mbed_official 330:c80ac197fa6a 649
mbed_official 330:c80ac197fa6a 650 /**
mbed_official 330:c80ac197fa6a 651 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 330:c80ac197fa6a 652 * RCC configuration registers.
mbed_official 330:c80ac197fa6a 653 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 330:c80ac197fa6a 654 * will be configured.
mbed_official 330:c80ac197fa6a 655 * @retval None
mbed_official 330:c80ac197fa6a 656 */
mbed_official 330:c80ac197fa6a 657 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 330:c80ac197fa6a 658 {
mbed_official 330:c80ac197fa6a 659 }
mbed_official 330:c80ac197fa6a 660
mbed_official 330:c80ac197fa6a 661 /**
mbed_official 330:c80ac197fa6a 662 * @brief Get the RCC_ClkInitStruct according to the internal
mbed_official 330:c80ac197fa6a 663 * RCC configuration registers.
mbed_official 330:c80ac197fa6a 664 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official 330:c80ac197fa6a 665 * contains the current clock configuration.
mbed_official 330:c80ac197fa6a 666 * @param pFLatency: Pointer on the Flash Latency.
mbed_official 330:c80ac197fa6a 667 * @retval None
mbed_official 330:c80ac197fa6a 668 */
mbed_official 330:c80ac197fa6a 669 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
mbed_official 330:c80ac197fa6a 670 {
mbed_official 330:c80ac197fa6a 671 /* Check the parameters */
mbed_official 632:7687fb9c4f91 672 assert_param(RCC_ClkInitStruct != NULL);
mbed_official 632:7687fb9c4f91 673 assert_param(pFLatency != NULL);
mbed_official 330:c80ac197fa6a 674
mbed_official 330:c80ac197fa6a 675 /* Set all possible values for the Clock type parameter --------------------*/
mbed_official 330:c80ac197fa6a 676 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
mbed_official 330:c80ac197fa6a 677
mbed_official 330:c80ac197fa6a 678 /* Get the SYSCLK configuration --------------------------------------------*/
mbed_official 330:c80ac197fa6a 679 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official 330:c80ac197fa6a 680
mbed_official 330:c80ac197fa6a 681 /* Get the HCLK configuration ----------------------------------------------*/
mbed_official 330:c80ac197fa6a 682 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official 330:c80ac197fa6a 683
mbed_official 330:c80ac197fa6a 684 /* Get the APB1 configuration ----------------------------------------------*/
mbed_official 330:c80ac197fa6a 685 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official 330:c80ac197fa6a 686
mbed_official 330:c80ac197fa6a 687 /* Get the APB2 configuration ----------------------------------------------*/
mbed_official 330:c80ac197fa6a 688 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official 330:c80ac197fa6a 689
mbed_official 330:c80ac197fa6a 690 /* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official 330:c80ac197fa6a 691 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official 330:c80ac197fa6a 692 }
mbed_official 330:c80ac197fa6a 693
mbed_official 330:c80ac197fa6a 694 /**
mbed_official 330:c80ac197fa6a 695 * @brief This function handles the RCC CSS interrupt request.
mbed_official 330:c80ac197fa6a 696 * @note This API should be called under the NMI_Handler().
mbed_official 330:c80ac197fa6a 697 * @retval None
mbed_official 330:c80ac197fa6a 698 */
mbed_official 330:c80ac197fa6a 699 void HAL_RCC_NMI_IRQHandler(void)
mbed_official 330:c80ac197fa6a 700 {
mbed_official 330:c80ac197fa6a 701 /* Check RCC CSSF flag */
mbed_official 330:c80ac197fa6a 702 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official 330:c80ac197fa6a 703 {
mbed_official 330:c80ac197fa6a 704 /* RCC Clock Security System interrupt user callback */
mbed_official 330:c80ac197fa6a 705 HAL_RCC_CCSCallback();
mbed_official 330:c80ac197fa6a 706
mbed_official 330:c80ac197fa6a 707 /* Clear RCC CSS pending bit */
mbed_official 330:c80ac197fa6a 708 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official 330:c80ac197fa6a 709 }
mbed_official 330:c80ac197fa6a 710 }
mbed_official 330:c80ac197fa6a 711
mbed_official 330:c80ac197fa6a 712 /**
mbed_official 330:c80ac197fa6a 713 * @brief RCC Clock Security System interrupt callback
mbed_official 330:c80ac197fa6a 714 * @retval None
mbed_official 330:c80ac197fa6a 715 */
mbed_official 330:c80ac197fa6a 716 __weak void HAL_RCC_CCSCallback(void)
mbed_official 330:c80ac197fa6a 717 {
mbed_official 330:c80ac197fa6a 718 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 330:c80ac197fa6a 719 the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official 330:c80ac197fa6a 720 */
mbed_official 330:c80ac197fa6a 721 }
mbed_official 330:c80ac197fa6a 722
mbed_official 330:c80ac197fa6a 723 /**
mbed_official 330:c80ac197fa6a 724 * @}
mbed_official 330:c80ac197fa6a 725 */
mbed_official 330:c80ac197fa6a 726
mbed_official 330:c80ac197fa6a 727 /**
mbed_official 330:c80ac197fa6a 728 * @}
mbed_official 330:c80ac197fa6a 729 */
mbed_official 330:c80ac197fa6a 730
mbed_official 330:c80ac197fa6a 731 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 330:c80ac197fa6a 732 /**
mbed_official 330:c80ac197fa6a 733 * @}
mbed_official 330:c80ac197fa6a 734 */
mbed_official 330:c80ac197fa6a 735
mbed_official 330:c80ac197fa6a 736 /**
mbed_official 330:c80ac197fa6a 737 * @}
mbed_official 330:c80ac197fa6a 738 */
mbed_official 330:c80ac197fa6a 739
mbed_official 330:c80ac197fa6a 740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/