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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/stm32f303x8.h@632:7687fb9c4f91, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 14:00:11 2015 +0100
Revision:
632:7687fb9c4f91
Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0



Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/



NUCLEO_F303K8 - add support of the STM32F303K8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 632:7687fb9c4f91 1 /**
mbed_official 632:7687fb9c4f91 2 ******************************************************************************
mbed_official 632:7687fb9c4f91 3 * @file stm32f303x8.h
mbed_official 632:7687fb9c4f91 4 * @author MCD Application Team
mbed_official 632:7687fb9c4f91 5 * @version $VERSION$
mbed_official 632:7687fb9c4f91 6 * @date 12-Sept-2014
mbed_official 632:7687fb9c4f91 7 * @brief CMSIS STM32F303x6/STM32F303x8 Devices Peripheral Access Layer Header File.
mbed_official 632:7687fb9c4f91 8 *
mbed_official 632:7687fb9c4f91 9 * This file contains:
mbed_official 632:7687fb9c4f91 10 * - Data structures and the address mapping for all peripherals
mbed_official 632:7687fb9c4f91 11 * - Peripheral's registers declarations and bits definition
mbed_official 632:7687fb9c4f91 12 * - Macros to access peripheral’s registers hardware
mbed_official 632:7687fb9c4f91 13 *
mbed_official 632:7687fb9c4f91 14 ******************************************************************************
mbed_official 632:7687fb9c4f91 15 * @attention
mbed_official 632:7687fb9c4f91 16 *
mbed_official 632:7687fb9c4f91 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 632:7687fb9c4f91 18 *
mbed_official 632:7687fb9c4f91 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 632:7687fb9c4f91 20 * are permitted provided that the following conditions are met:
mbed_official 632:7687fb9c4f91 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 632:7687fb9c4f91 22 * this list of conditions and the following disclaimer.
mbed_official 632:7687fb9c4f91 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 632:7687fb9c4f91 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 632:7687fb9c4f91 25 * and/or other materials provided with the distribution.
mbed_official 632:7687fb9c4f91 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 632:7687fb9c4f91 27 * may be used to endorse or promote products derived from this software
mbed_official 632:7687fb9c4f91 28 * without specific prior written permission.
mbed_official 632:7687fb9c4f91 29 *
mbed_official 632:7687fb9c4f91 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 632:7687fb9c4f91 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 632:7687fb9c4f91 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 632:7687fb9c4f91 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 632:7687fb9c4f91 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 632:7687fb9c4f91 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 632:7687fb9c4f91 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 632:7687fb9c4f91 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 632:7687fb9c4f91 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 632:7687fb9c4f91 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 632:7687fb9c4f91 40 *
mbed_official 632:7687fb9c4f91 41 ******************************************************************************
mbed_official 632:7687fb9c4f91 42 */
mbed_official 632:7687fb9c4f91 43
mbed_official 632:7687fb9c4f91 44 /** @addtogroup CMSIS_Device
mbed_official 632:7687fb9c4f91 45 * @{
mbed_official 632:7687fb9c4f91 46 */
mbed_official 632:7687fb9c4f91 47
mbed_official 632:7687fb9c4f91 48 /** @addtogroup stm32f303x8
mbed_official 632:7687fb9c4f91 49 * @{
mbed_official 632:7687fb9c4f91 50 */
mbed_official 632:7687fb9c4f91 51
mbed_official 632:7687fb9c4f91 52 #ifndef __STM32F303x8_H
mbed_official 632:7687fb9c4f91 53 #define __STM32F303x8_H
mbed_official 632:7687fb9c4f91 54
mbed_official 632:7687fb9c4f91 55 #ifdef __cplusplus
mbed_official 632:7687fb9c4f91 56 extern "C" {
mbed_official 632:7687fb9c4f91 57 #endif /* __cplusplus */
mbed_official 632:7687fb9c4f91 58
mbed_official 632:7687fb9c4f91 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 632:7687fb9c4f91 60 * @{
mbed_official 632:7687fb9c4f91 61 */
mbed_official 632:7687fb9c4f91 62
mbed_official 632:7687fb9c4f91 63 /**
mbed_official 632:7687fb9c4f91 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 632:7687fb9c4f91 65 */
mbed_official 632:7687fb9c4f91 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 632:7687fb9c4f91 67 #define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */
mbed_official 632:7687fb9c4f91 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */
mbed_official 632:7687fb9c4f91 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 632:7687fb9c4f91 70 #define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */
mbed_official 632:7687fb9c4f91 71
mbed_official 632:7687fb9c4f91 72 /**
mbed_official 632:7687fb9c4f91 73 * @}
mbed_official 632:7687fb9c4f91 74 */
mbed_official 632:7687fb9c4f91 75
mbed_official 632:7687fb9c4f91 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 632:7687fb9c4f91 77 * @{
mbed_official 632:7687fb9c4f91 78 */
mbed_official 632:7687fb9c4f91 79
mbed_official 632:7687fb9c4f91 80 /**
mbed_official 632:7687fb9c4f91 81 * @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device
mbed_official 632:7687fb9c4f91 82 * in @ref Library_configuration_section
mbed_official 632:7687fb9c4f91 83 */
mbed_official 632:7687fb9c4f91 84 typedef enum
mbed_official 632:7687fb9c4f91 85 {
mbed_official 632:7687fb9c4f91 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 632:7687fb9c4f91 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 632:7687fb9c4f91 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 632:7687fb9c4f91 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 632:7687fb9c4f91 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 632:7687fb9c4f91 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 632:7687fb9c4f91 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 632:7687fb9c4f91 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 632:7687fb9c4f91 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 632:7687fb9c4f91 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 632:7687fb9c4f91 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 632:7687fb9c4f91 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 632:7687fb9c4f91 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
mbed_official 632:7687fb9c4f91 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
mbed_official 632:7687fb9c4f91 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 632:7687fb9c4f91 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 632:7687fb9c4f91 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 632:7687fb9c4f91 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 632:7687fb9c4f91 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
mbed_official 632:7687fb9c4f91 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 632:7687fb9c4f91 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 632:7687fb9c4f91 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 632:7687fb9c4f91 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 632:7687fb9c4f91 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 632:7687fb9c4f91 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 632:7687fb9c4f91 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 632:7687fb9c4f91 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 632:7687fb9c4f91 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 632:7687fb9c4f91 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
mbed_official 632:7687fb9c4f91 115 CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
mbed_official 632:7687fb9c4f91 116 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
mbed_official 632:7687fb9c4f91 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
mbed_official 632:7687fb9c4f91 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
mbed_official 632:7687fb9c4f91 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 632:7687fb9c4f91 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 632:7687fb9c4f91 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 632:7687fb9c4f91 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 632:7687fb9c4f91 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 632:7687fb9c4f91 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 632:7687fb9c4f91 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 632:7687fb9c4f91 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 632:7687fb9c4f91 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 632:7687fb9c4f91 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 632:7687fb9c4f91 129 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 632:7687fb9c4f91 130 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 632:7687fb9c4f91 131 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
mbed_official 632:7687fb9c4f91 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 632:7687fb9c4f91 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
mbed_official 632:7687fb9c4f91 134 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
mbed_official 632:7687fb9c4f91 135 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
mbed_official 632:7687fb9c4f91 136 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
mbed_official 632:7687fb9c4f91 137 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
mbed_official 632:7687fb9c4f91 138 FPU_IRQn = 81 /*!< Floating point Interrupt */
mbed_official 632:7687fb9c4f91 139 } IRQn_Type;
mbed_official 632:7687fb9c4f91 140
mbed_official 632:7687fb9c4f91 141 /**
mbed_official 632:7687fb9c4f91 142 * @}
mbed_official 632:7687fb9c4f91 143 */
mbed_official 632:7687fb9c4f91 144
mbed_official 632:7687fb9c4f91 145 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 632:7687fb9c4f91 146 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
mbed_official 632:7687fb9c4f91 147 #include <stdint.h>
mbed_official 632:7687fb9c4f91 148
mbed_official 632:7687fb9c4f91 149 /** @addtogroup Peripheral_registers_structures
mbed_official 632:7687fb9c4f91 150 * @{
mbed_official 632:7687fb9c4f91 151 */
mbed_official 632:7687fb9c4f91 152
mbed_official 632:7687fb9c4f91 153 /**
mbed_official 632:7687fb9c4f91 154 * @brief Analog to Digital Converter
mbed_official 632:7687fb9c4f91 155 */
mbed_official 632:7687fb9c4f91 156
mbed_official 632:7687fb9c4f91 157 typedef struct
mbed_official 632:7687fb9c4f91 158 {
mbed_official 632:7687fb9c4f91 159 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 160 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 161 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 162 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 163 uint32_t RESERVED0; /*!< Reserved, 0x010 */
mbed_official 632:7687fb9c4f91 164 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 165 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 166 uint32_t RESERVED1; /*!< Reserved, 0x01C */
mbed_official 632:7687fb9c4f91 167 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 168 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 169 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 170 uint32_t RESERVED2; /*!< Reserved, 0x02C */
mbed_official 632:7687fb9c4f91 171 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 172 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 632:7687fb9c4f91 173 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 632:7687fb9c4f91 174 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 632:7687fb9c4f91 175 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
mbed_official 632:7687fb9c4f91 176 uint32_t RESERVED3; /*!< Reserved, 0x044 */
mbed_official 632:7687fb9c4f91 177 uint32_t RESERVED4; /*!< Reserved, 0x048 */
mbed_official 632:7687fb9c4f91 178 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
mbed_official 632:7687fb9c4f91 179 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
mbed_official 632:7687fb9c4f91 180 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
mbed_official 632:7687fb9c4f91 181 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
mbed_official 632:7687fb9c4f91 182 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
mbed_official 632:7687fb9c4f91 183 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
mbed_official 632:7687fb9c4f91 184 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
mbed_official 632:7687fb9c4f91 185 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
mbed_official 632:7687fb9c4f91 186 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
mbed_official 632:7687fb9c4f91 187 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
mbed_official 632:7687fb9c4f91 188 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
mbed_official 632:7687fb9c4f91 189 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
mbed_official 632:7687fb9c4f91 190 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
mbed_official 632:7687fb9c4f91 191 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
mbed_official 632:7687fb9c4f91 192 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
mbed_official 632:7687fb9c4f91 193 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
mbed_official 632:7687fb9c4f91 194 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
mbed_official 632:7687fb9c4f91 195 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
mbed_official 632:7687fb9c4f91 196
mbed_official 632:7687fb9c4f91 197 } ADC_TypeDef;
mbed_official 632:7687fb9c4f91 198
mbed_official 632:7687fb9c4f91 199 typedef struct
mbed_official 632:7687fb9c4f91 200 {
mbed_official 632:7687fb9c4f91 201 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
mbed_official 632:7687fb9c4f91 202 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
mbed_official 632:7687fb9c4f91 203 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
mbed_official 632:7687fb9c4f91 204 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 632:7687fb9c4f91 205 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
mbed_official 632:7687fb9c4f91 206 } ADC_Common_TypeDef;
mbed_official 632:7687fb9c4f91 207
mbed_official 632:7687fb9c4f91 208 /**
mbed_official 632:7687fb9c4f91 209 * @brief Controller Area Network TxMailBox
mbed_official 632:7687fb9c4f91 210 */
mbed_official 632:7687fb9c4f91 211 typedef struct
mbed_official 632:7687fb9c4f91 212 {
mbed_official 632:7687fb9c4f91 213 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 632:7687fb9c4f91 214 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 632:7687fb9c4f91 215 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 632:7687fb9c4f91 216 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 632:7687fb9c4f91 217 } CAN_TxMailBox_TypeDef;
mbed_official 632:7687fb9c4f91 218
mbed_official 632:7687fb9c4f91 219 /**
mbed_official 632:7687fb9c4f91 220 * @brief Controller Area Network FIFOMailBox
mbed_official 632:7687fb9c4f91 221 */
mbed_official 632:7687fb9c4f91 222 typedef struct
mbed_official 632:7687fb9c4f91 223 {
mbed_official 632:7687fb9c4f91 224 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 632:7687fb9c4f91 225 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 632:7687fb9c4f91 226 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 632:7687fb9c4f91 227 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 632:7687fb9c4f91 228 } CAN_FIFOMailBox_TypeDef;
mbed_official 632:7687fb9c4f91 229
mbed_official 632:7687fb9c4f91 230 /**
mbed_official 632:7687fb9c4f91 231 * @brief Controller Area Network FilterRegister
mbed_official 632:7687fb9c4f91 232 */
mbed_official 632:7687fb9c4f91 233 typedef struct
mbed_official 632:7687fb9c4f91 234 {
mbed_official 632:7687fb9c4f91 235 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 632:7687fb9c4f91 236 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 632:7687fb9c4f91 237 } CAN_FilterRegister_TypeDef;
mbed_official 632:7687fb9c4f91 238
mbed_official 632:7687fb9c4f91 239 /**
mbed_official 632:7687fb9c4f91 240 * @brief Controller Area Network
mbed_official 632:7687fb9c4f91 241 */
mbed_official 632:7687fb9c4f91 242 typedef struct
mbed_official 632:7687fb9c4f91 243 {
mbed_official 632:7687fb9c4f91 244 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 245 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 246 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 247 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 248 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 249 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 250 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 251 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 252 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 632:7687fb9c4f91 253 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 632:7687fb9c4f91 254 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 632:7687fb9c4f91 255 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 632:7687fb9c4f91 256 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 632:7687fb9c4f91 257 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 632:7687fb9c4f91 258 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 632:7687fb9c4f91 259 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 632:7687fb9c4f91 260 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 632:7687fb9c4f91 261 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 632:7687fb9c4f91 262 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 632:7687fb9c4f91 263 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 632:7687fb9c4f91 264 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 632:7687fb9c4f91 265 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 632:7687fb9c4f91 266 } CAN_TypeDef;
mbed_official 632:7687fb9c4f91 267
mbed_official 632:7687fb9c4f91 268 /**
mbed_official 632:7687fb9c4f91 269 * @brief Analog Comparators
mbed_official 632:7687fb9c4f91 270 */
mbed_official 632:7687fb9c4f91 271
mbed_official 632:7687fb9c4f91 272 typedef struct
mbed_official 632:7687fb9c4f91 273 {
mbed_official 632:7687fb9c4f91 274 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 275 } COMP_TypeDef;
mbed_official 632:7687fb9c4f91 276
mbed_official 632:7687fb9c4f91 277 /**
mbed_official 632:7687fb9c4f91 278 * @brief CRC calculation unit
mbed_official 632:7687fb9c4f91 279 */
mbed_official 632:7687fb9c4f91 280
mbed_official 632:7687fb9c4f91 281 typedef struct
mbed_official 632:7687fb9c4f91 282 {
mbed_official 632:7687fb9c4f91 283 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 284 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 285 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 632:7687fb9c4f91 286 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 632:7687fb9c4f91 287 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 288 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 632:7687fb9c4f91 289 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 290 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 291 } CRC_TypeDef;
mbed_official 632:7687fb9c4f91 292
mbed_official 632:7687fb9c4f91 293 /**
mbed_official 632:7687fb9c4f91 294 * @brief Digital to Analog Converter
mbed_official 632:7687fb9c4f91 295 */
mbed_official 632:7687fb9c4f91 296
mbed_official 632:7687fb9c4f91 297 typedef struct
mbed_official 632:7687fb9c4f91 298 {
mbed_official 632:7687fb9c4f91 299 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 300 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 301 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 302 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 303 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 304 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 305 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 306 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 307 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 308 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 309 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 310 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 311 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 312 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 632:7687fb9c4f91 313 } DAC_TypeDef;
mbed_official 632:7687fb9c4f91 314
mbed_official 632:7687fb9c4f91 315 /**
mbed_official 632:7687fb9c4f91 316 * @brief Debug MCU
mbed_official 632:7687fb9c4f91 317 */
mbed_official 632:7687fb9c4f91 318
mbed_official 632:7687fb9c4f91 319 typedef struct
mbed_official 632:7687fb9c4f91 320 {
mbed_official 632:7687fb9c4f91 321 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 322 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 323 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 324 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 325 }DBGMCU_TypeDef;
mbed_official 632:7687fb9c4f91 326
mbed_official 632:7687fb9c4f91 327 /**
mbed_official 632:7687fb9c4f91 328 * @brief DMA Controller
mbed_official 632:7687fb9c4f91 329 */
mbed_official 632:7687fb9c4f91 330
mbed_official 632:7687fb9c4f91 331 typedef struct
mbed_official 632:7687fb9c4f91 332 {
mbed_official 632:7687fb9c4f91 333 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 632:7687fb9c4f91 334 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 632:7687fb9c4f91 335 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 632:7687fb9c4f91 336 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 632:7687fb9c4f91 337 } DMA_Channel_TypeDef;
mbed_official 632:7687fb9c4f91 338
mbed_official 632:7687fb9c4f91 339 typedef struct
mbed_official 632:7687fb9c4f91 340 {
mbed_official 632:7687fb9c4f91 341 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 342 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 343 } DMA_TypeDef;
mbed_official 632:7687fb9c4f91 344
mbed_official 632:7687fb9c4f91 345 /**
mbed_official 632:7687fb9c4f91 346 * @brief External Interrupt/Event Controller
mbed_official 632:7687fb9c4f91 347 */
mbed_official 632:7687fb9c4f91 348
mbed_official 632:7687fb9c4f91 349 typedef struct
mbed_official 632:7687fb9c4f91 350 {
mbed_official 632:7687fb9c4f91 351 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 352 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 353 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 354 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 355 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 356 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 357 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 632:7687fb9c4f91 358 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 632:7687fb9c4f91 359 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 360 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 361 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 362 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 363 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 364 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
mbed_official 632:7687fb9c4f91 365 }EXTI_TypeDef;
mbed_official 632:7687fb9c4f91 366
mbed_official 632:7687fb9c4f91 367 /**
mbed_official 632:7687fb9c4f91 368 * @brief FLASH Registers
mbed_official 632:7687fb9c4f91 369 */
mbed_official 632:7687fb9c4f91 370
mbed_official 632:7687fb9c4f91 371 typedef struct
mbed_official 632:7687fb9c4f91 372 {
mbed_official 632:7687fb9c4f91 373 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 374 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 375 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 376 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 377 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 378 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 379 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 632:7687fb9c4f91 380 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 381 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 382
mbed_official 632:7687fb9c4f91 383 } FLASH_TypeDef;
mbed_official 632:7687fb9c4f91 384
mbed_official 632:7687fb9c4f91 385 /**
mbed_official 632:7687fb9c4f91 386 * @brief Option Bytes Registers
mbed_official 632:7687fb9c4f91 387 */
mbed_official 632:7687fb9c4f91 388 typedef struct
mbed_official 632:7687fb9c4f91 389 {
mbed_official 632:7687fb9c4f91 390 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 391 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
mbed_official 632:7687fb9c4f91 392 uint16_t RESERVED0; /*!< Reserved, 0x04 */
mbed_official 632:7687fb9c4f91 393 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 632:7687fb9c4f91 394 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 395 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 396 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 397 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
mbed_official 632:7687fb9c4f91 398 } OB_TypeDef;
mbed_official 632:7687fb9c4f91 399
mbed_official 632:7687fb9c4f91 400 /**
mbed_official 632:7687fb9c4f91 401 * @brief General Purpose I/O
mbed_official 632:7687fb9c4f91 402 */
mbed_official 632:7687fb9c4f91 403
mbed_official 632:7687fb9c4f91 404 typedef struct
mbed_official 632:7687fb9c4f91 405 {
mbed_official 632:7687fb9c4f91 406 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 407 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 408 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 409 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 410 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 411 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 412 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 413 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
mbed_official 632:7687fb9c4f91 414 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 415 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 632:7687fb9c4f91 416 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 417 }GPIO_TypeDef;
mbed_official 632:7687fb9c4f91 418
mbed_official 632:7687fb9c4f91 419 /**
mbed_official 632:7687fb9c4f91 420 * @brief Operational Amplifier (OPAMP)
mbed_official 632:7687fb9c4f91 421 */
mbed_official 632:7687fb9c4f91 422
mbed_official 632:7687fb9c4f91 423 typedef struct
mbed_official 632:7687fb9c4f91 424 {
mbed_official 632:7687fb9c4f91 425 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 426 } OPAMP_TypeDef;
mbed_official 632:7687fb9c4f91 427
mbed_official 632:7687fb9c4f91 428 /**
mbed_official 632:7687fb9c4f91 429 * @brief System configuration controller
mbed_official 632:7687fb9c4f91 430 */
mbed_official 632:7687fb9c4f91 431
mbed_official 632:7687fb9c4f91 432 typedef struct
mbed_official 632:7687fb9c4f91 433 {
mbed_official 632:7687fb9c4f91 434 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 435 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 436 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
mbed_official 632:7687fb9c4f91 437 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 438 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 632:7687fb9c4f91 439 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
mbed_official 632:7687fb9c4f91 440 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
mbed_official 632:7687fb9c4f91 441 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
mbed_official 632:7687fb9c4f91 442 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
mbed_official 632:7687fb9c4f91 443 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
mbed_official 632:7687fb9c4f91 444 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
mbed_official 632:7687fb9c4f91 445 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
mbed_official 632:7687fb9c4f91 446 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
mbed_official 632:7687fb9c4f91 447 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
mbed_official 632:7687fb9c4f91 448 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
mbed_official 632:7687fb9c4f91 449 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
mbed_official 632:7687fb9c4f91 450 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
mbed_official 632:7687fb9c4f91 451 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
mbed_official 632:7687fb9c4f91 452 } SYSCFG_TypeDef;
mbed_official 632:7687fb9c4f91 453
mbed_official 632:7687fb9c4f91 454 /**
mbed_official 632:7687fb9c4f91 455 * @brief Inter-integrated Circuit Interface
mbed_official 632:7687fb9c4f91 456 */
mbed_official 632:7687fb9c4f91 457
mbed_official 632:7687fb9c4f91 458 typedef struct
mbed_official 632:7687fb9c4f91 459 {
mbed_official 632:7687fb9c4f91 460 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 461 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 462 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 463 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 464 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 465 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 466 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 467 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 468 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 469 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 470 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 471 }I2C_TypeDef;
mbed_official 632:7687fb9c4f91 472
mbed_official 632:7687fb9c4f91 473 /**
mbed_official 632:7687fb9c4f91 474 * @brief Independent WATCHDOG
mbed_official 632:7687fb9c4f91 475 */
mbed_official 632:7687fb9c4f91 476
mbed_official 632:7687fb9c4f91 477 typedef struct
mbed_official 632:7687fb9c4f91 478 {
mbed_official 632:7687fb9c4f91 479 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 480 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 481 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 482 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 483 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 484 } IWDG_TypeDef;
mbed_official 632:7687fb9c4f91 485
mbed_official 632:7687fb9c4f91 486 /**
mbed_official 632:7687fb9c4f91 487 * @brief Power Control
mbed_official 632:7687fb9c4f91 488 */
mbed_official 632:7687fb9c4f91 489
mbed_official 632:7687fb9c4f91 490 typedef struct
mbed_official 632:7687fb9c4f91 491 {
mbed_official 632:7687fb9c4f91 492 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 493 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 494 } PWR_TypeDef;
mbed_official 632:7687fb9c4f91 495
mbed_official 632:7687fb9c4f91 496 /**
mbed_official 632:7687fb9c4f91 497 * @brief Reset and Clock Control
mbed_official 632:7687fb9c4f91 498 */
mbed_official 632:7687fb9c4f91 499 typedef struct
mbed_official 632:7687fb9c4f91 500 {
mbed_official 632:7687fb9c4f91 501 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 502 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 503 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 504 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 505 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 506 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 507 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 508 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 509 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 510 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 511 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 512 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 513 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 514 } RCC_TypeDef;
mbed_official 632:7687fb9c4f91 515
mbed_official 632:7687fb9c4f91 516 /**
mbed_official 632:7687fb9c4f91 517 * @brief Real-Time Clock
mbed_official 632:7687fb9c4f91 518 */
mbed_official 632:7687fb9c4f91 519
mbed_official 632:7687fb9c4f91 520 typedef struct
mbed_official 632:7687fb9c4f91 521 {
mbed_official 632:7687fb9c4f91 522 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 523 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 524 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 525 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 526 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 527 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 528 uint32_t RESERVED0; /*!< Reserved, 0x18 */
mbed_official 632:7687fb9c4f91 529 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 530 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 531 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 532 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 533 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 534 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 535 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 632:7687fb9c4f91 536 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 632:7687fb9c4f91 537 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 632:7687fb9c4f91 538 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 632:7687fb9c4f91 539 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 632:7687fb9c4f91 540 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 632:7687fb9c4f91 541 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 632:7687fb9c4f91 542 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 632:7687fb9c4f91 543 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 632:7687fb9c4f91 544 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 632:7687fb9c4f91 545 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 632:7687fb9c4f91 546 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 632:7687fb9c4f91 547 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 632:7687fb9c4f91 548 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 632:7687fb9c4f91 549 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 632:7687fb9c4f91 550 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 632:7687fb9c4f91 551 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 632:7687fb9c4f91 552 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 632:7687fb9c4f91 553 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 632:7687fb9c4f91 554 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 632:7687fb9c4f91 555 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 632:7687fb9c4f91 556 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 632:7687fb9c4f91 557 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 632:7687fb9c4f91 558 } RTC_TypeDef;
mbed_official 632:7687fb9c4f91 559
mbed_official 632:7687fb9c4f91 560
mbed_official 632:7687fb9c4f91 561 /**
mbed_official 632:7687fb9c4f91 562 * @brief Serial Peripheral Interface
mbed_official 632:7687fb9c4f91 563 */
mbed_official 632:7687fb9c4f91 564
mbed_official 632:7687fb9c4f91 565 typedef struct
mbed_official 632:7687fb9c4f91 566 {
mbed_official 632:7687fb9c4f91 567 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 568 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 569 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 570 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 571 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 572 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 573 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 574 } SPI_TypeDef;
mbed_official 632:7687fb9c4f91 575
mbed_official 632:7687fb9c4f91 576 /**
mbed_official 632:7687fb9c4f91 577 * @brief TIM
mbed_official 632:7687fb9c4f91 578 */
mbed_official 632:7687fb9c4f91 579 typedef struct
mbed_official 632:7687fb9c4f91 580 {
mbed_official 632:7687fb9c4f91 581 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 582 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 583 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 584 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 585 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 586 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 587 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 588 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 589 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 590 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 591 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 592 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 593 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 594 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 632:7687fb9c4f91 595 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 632:7687fb9c4f91 596 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 632:7687fb9c4f91 597 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 632:7687fb9c4f91 598 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 632:7687fb9c4f91 599 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 632:7687fb9c4f91 600 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 632:7687fb9c4f91 601 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 632:7687fb9c4f91 602 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 632:7687fb9c4f91 603 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
mbed_official 632:7687fb9c4f91 604 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
mbed_official 632:7687fb9c4f91 605 } TIM_TypeDef;
mbed_official 632:7687fb9c4f91 606
mbed_official 632:7687fb9c4f91 607 /**
mbed_official 632:7687fb9c4f91 608 * @brief Touch Sensing Controller (TSC)
mbed_official 632:7687fb9c4f91 609 */
mbed_official 632:7687fb9c4f91 610 typedef struct
mbed_official 632:7687fb9c4f91 611 {
mbed_official 632:7687fb9c4f91 612 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 613 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 614 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 615 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 616 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 617 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 618 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 619 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 620 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 621 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 622 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 623 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 632:7687fb9c4f91 624 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 632:7687fb9c4f91 625 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 632:7687fb9c4f91 626 } TSC_TypeDef;
mbed_official 632:7687fb9c4f91 627
mbed_official 632:7687fb9c4f91 628 /**
mbed_official 632:7687fb9c4f91 629 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 632:7687fb9c4f91 630 */
mbed_official 632:7687fb9c4f91 631
mbed_official 632:7687fb9c4f91 632 typedef struct
mbed_official 632:7687fb9c4f91 633 {
mbed_official 632:7687fb9c4f91 634 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 635 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 636 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 637 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 632:7687fb9c4f91 638 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 632:7687fb9c4f91 639 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 632:7687fb9c4f91 640 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 632:7687fb9c4f91 641 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 632:7687fb9c4f91 642 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 632:7687fb9c4f91 643 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 632:7687fb9c4f91 644 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 632:7687fb9c4f91 645 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 632:7687fb9c4f91 646 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 632:7687fb9c4f91 647 } USART_TypeDef;
mbed_official 632:7687fb9c4f91 648
mbed_official 632:7687fb9c4f91 649 /**
mbed_official 632:7687fb9c4f91 650 * @brief Window WATCHDOG
mbed_official 632:7687fb9c4f91 651 */
mbed_official 632:7687fb9c4f91 652 typedef struct
mbed_official 632:7687fb9c4f91 653 {
mbed_official 632:7687fb9c4f91 654 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 632:7687fb9c4f91 655 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 632:7687fb9c4f91 656 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 632:7687fb9c4f91 657 } WWDG_TypeDef;
mbed_official 632:7687fb9c4f91 658
mbed_official 632:7687fb9c4f91 659 /** @addtogroup Peripheral_memory_map
mbed_official 632:7687fb9c4f91 660 * @{
mbed_official 632:7687fb9c4f91 661 */
mbed_official 632:7687fb9c4f91 662
mbed_official 632:7687fb9c4f91 663 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
mbed_official 632:7687fb9c4f91 664 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
mbed_official 632:7687fb9c4f91 665 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
mbed_official 632:7687fb9c4f91 666 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 632:7687fb9c4f91 667
mbed_official 632:7687fb9c4f91 668 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
mbed_official 632:7687fb9c4f91 669 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
mbed_official 632:7687fb9c4f91 670 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 632:7687fb9c4f91 671
mbed_official 632:7687fb9c4f91 672
mbed_official 632:7687fb9c4f91 673 /*!< Peripheral memory map */
mbed_official 632:7687fb9c4f91 674 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 632:7687fb9c4f91 675 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 632:7687fb9c4f91 676 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 632:7687fb9c4f91 677 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 632:7687fb9c4f91 678 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 632:7687fb9c4f91 679
mbed_official 632:7687fb9c4f91 680 /*!< APB1 peripherals */
mbed_official 632:7687fb9c4f91 681 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 632:7687fb9c4f91 682 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 632:7687fb9c4f91 683 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 632:7687fb9c4f91 684 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 632:7687fb9c4f91 685 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 632:7687fb9c4f91 686 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 632:7687fb9c4f91 687 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 632:7687fb9c4f91 688 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 632:7687fb9c4f91 689 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 632:7687fb9c4f91 690 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 632:7687fb9c4f91 691 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
mbed_official 632:7687fb9c4f91 692 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 632:7687fb9c4f91 693 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 632:7687fb9c4f91 694 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
mbed_official 632:7687fb9c4f91 695 #define DAC_BASE DAC1_BASE
mbed_official 632:7687fb9c4f91 696
mbed_official 632:7687fb9c4f91 697 /*!< APB2 peripherals */
mbed_official 632:7687fb9c4f91 698 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 632:7687fb9c4f91 699 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
mbed_official 632:7687fb9c4f91 700 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
mbed_official 632:7687fb9c4f91 701 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
mbed_official 632:7687fb9c4f91 702 #define COMP_BASE COMP2_BASE
mbed_official 632:7687fb9c4f91 703 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
mbed_official 632:7687fb9c4f91 704 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
mbed_official 632:7687fb9c4f91 705 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
mbed_official 632:7687fb9c4f91 706 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
mbed_official 632:7687fb9c4f91 707 #define OPAMP_BASE OPAMP1_BASE
mbed_official 632:7687fb9c4f91 708 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 632:7687fb9c4f91 709 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
mbed_official 632:7687fb9c4f91 710 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 632:7687fb9c4f91 711 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 632:7687fb9c4f91 712 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
mbed_official 632:7687fb9c4f91 713 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
mbed_official 632:7687fb9c4f91 714 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
mbed_official 632:7687fb9c4f91 715
mbed_official 632:7687fb9c4f91 716 /*!< AHB1 peripherals */
mbed_official 632:7687fb9c4f91 717 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
mbed_official 632:7687fb9c4f91 718 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
mbed_official 632:7687fb9c4f91 719 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
mbed_official 632:7687fb9c4f91 720 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
mbed_official 632:7687fb9c4f91 721 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
mbed_official 632:7687fb9c4f91 722 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
mbed_official 632:7687fb9c4f91 723 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
mbed_official 632:7687fb9c4f91 724 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
mbed_official 632:7687fb9c4f91 725 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
mbed_official 632:7687fb9c4f91 726 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
mbed_official 632:7687fb9c4f91 727 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
mbed_official 632:7687fb9c4f91 728 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
mbed_official 632:7687fb9c4f91 729 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
mbed_official 632:7687fb9c4f91 730
mbed_official 632:7687fb9c4f91 731 /*!< AHB2 peripherals */
mbed_official 632:7687fb9c4f91 732 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 632:7687fb9c4f91 733 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 632:7687fb9c4f91 734 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 632:7687fb9c4f91 735 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 632:7687fb9c4f91 736 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 632:7687fb9c4f91 737
mbed_official 632:7687fb9c4f91 738 /*!< AHB3 peripherals */
mbed_official 632:7687fb9c4f91 739 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
mbed_official 632:7687fb9c4f91 740 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
mbed_official 632:7687fb9c4f91 741 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
mbed_official 632:7687fb9c4f91 742
mbed_official 632:7687fb9c4f91 743 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 632:7687fb9c4f91 744 /**
mbed_official 632:7687fb9c4f91 745 * @}
mbed_official 632:7687fb9c4f91 746 */
mbed_official 632:7687fb9c4f91 747
mbed_official 632:7687fb9c4f91 748 /** @addtogroup Peripheral_declaration
mbed_official 632:7687fb9c4f91 749 * @{
mbed_official 632:7687fb9c4f91 750 */
mbed_official 632:7687fb9c4f91 751 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 632:7687fb9c4f91 752 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 632:7687fb9c4f91 753 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 632:7687fb9c4f91 754 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 632:7687fb9c4f91 755 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 632:7687fb9c4f91 756 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 632:7687fb9c4f91 757 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 632:7687fb9c4f91 758 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 632:7687fb9c4f91 759 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 632:7687fb9c4f91 760 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 632:7687fb9c4f91 761 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 632:7687fb9c4f91 762 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 632:7687fb9c4f91 763 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
mbed_official 632:7687fb9c4f91 764 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
mbed_official 632:7687fb9c4f91 765 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 632:7687fb9c4f91 766 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 632:7687fb9c4f91 767 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official 632:7687fb9c4f91 768 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
mbed_official 632:7687fb9c4f91 769 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
mbed_official 632:7687fb9c4f91 770 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 632:7687fb9c4f91 771 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
mbed_official 632:7687fb9c4f91 772 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 632:7687fb9c4f91 773 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 632:7687fb9c4f91 774 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 632:7687fb9c4f91 775 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 632:7687fb9c4f91 776 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 632:7687fb9c4f91 777 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 632:7687fb9c4f91 778 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 632:7687fb9c4f91 779 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 632:7687fb9c4f91 780 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 632:7687fb9c4f91 781 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 632:7687fb9c4f91 782 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 632:7687fb9c4f91 783 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 632:7687fb9c4f91 784 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 632:7687fb9c4f91 785 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 632:7687fb9c4f91 786 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 632:7687fb9c4f91 787 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 632:7687fb9c4f91 788 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 632:7687fb9c4f91 789 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 632:7687fb9c4f91 790 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 632:7687fb9c4f91 791 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 632:7687fb9c4f91 792 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 632:7687fb9c4f91 793 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 632:7687fb9c4f91 794 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 632:7687fb9c4f91 795 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 632:7687fb9c4f91 796 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 632:7687fb9c4f91 797 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 632:7687fb9c4f91 798 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 632:7687fb9c4f91 799 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 632:7687fb9c4f91 800 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 632:7687fb9c4f91 801 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
mbed_official 632:7687fb9c4f91 802 /**
mbed_official 632:7687fb9c4f91 803 * @}
mbed_official 632:7687fb9c4f91 804 */
mbed_official 632:7687fb9c4f91 805
mbed_official 632:7687fb9c4f91 806 /** @addtogroup Exported_constants
mbed_official 632:7687fb9c4f91 807 * @{
mbed_official 632:7687fb9c4f91 808 */
mbed_official 632:7687fb9c4f91 809
mbed_official 632:7687fb9c4f91 810 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 632:7687fb9c4f91 811 * @{
mbed_official 632:7687fb9c4f91 812 */
mbed_official 632:7687fb9c4f91 813
mbed_official 632:7687fb9c4f91 814 /******************************************************************************/
mbed_official 632:7687fb9c4f91 815 /* Peripheral Registers_Bits_Definition */
mbed_official 632:7687fb9c4f91 816 /******************************************************************************/
mbed_official 632:7687fb9c4f91 817
mbed_official 632:7687fb9c4f91 818 /******************************************************************************/
mbed_official 632:7687fb9c4f91 819 /* */
mbed_official 632:7687fb9c4f91 820 /* Analog to Digital Converter SAR (ADC) */
mbed_official 632:7687fb9c4f91 821 /* */
mbed_official 632:7687fb9c4f91 822 /******************************************************************************/
mbed_official 632:7687fb9c4f91 823 /******************** Bit definition for ADC_ISR register ********************/
mbed_official 632:7687fb9c4f91 824 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
mbed_official 632:7687fb9c4f91 825 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
mbed_official 632:7687fb9c4f91 826 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
mbed_official 632:7687fb9c4f91 827 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
mbed_official 632:7687fb9c4f91 828 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
mbed_official 632:7687fb9c4f91 829 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
mbed_official 632:7687fb9c4f91 830 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
mbed_official 632:7687fb9c4f91 831 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
mbed_official 632:7687fb9c4f91 832 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
mbed_official 632:7687fb9c4f91 833 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
mbed_official 632:7687fb9c4f91 834 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
mbed_official 632:7687fb9c4f91 835
mbed_official 632:7687fb9c4f91 836 /******************** Bit definition for ADC_IER register ********************/
mbed_official 632:7687fb9c4f91 837 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
mbed_official 632:7687fb9c4f91 838 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
mbed_official 632:7687fb9c4f91 839 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
mbed_official 632:7687fb9c4f91 840 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
mbed_official 632:7687fb9c4f91 841 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
mbed_official 632:7687fb9c4f91 842 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
mbed_official 632:7687fb9c4f91 843 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
mbed_official 632:7687fb9c4f91 844 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
mbed_official 632:7687fb9c4f91 845 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
mbed_official 632:7687fb9c4f91 846 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
mbed_official 632:7687fb9c4f91 847 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
mbed_official 632:7687fb9c4f91 848
mbed_official 632:7687fb9c4f91 849 /******************** Bit definition for ADC_CR register ********************/
mbed_official 632:7687fb9c4f91 850 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
mbed_official 632:7687fb9c4f91 851 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
mbed_official 632:7687fb9c4f91 852 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
mbed_official 632:7687fb9c4f91 853 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
mbed_official 632:7687fb9c4f91 854 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
mbed_official 632:7687fb9c4f91 855 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
mbed_official 632:7687fb9c4f91 856 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
mbed_official 632:7687fb9c4f91 857 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
mbed_official 632:7687fb9c4f91 858 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
mbed_official 632:7687fb9c4f91 859 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
mbed_official 632:7687fb9c4f91 860 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
mbed_official 632:7687fb9c4f91 861
mbed_official 632:7687fb9c4f91 862 /******************** Bit definition for ADC_CFGR register ********************/
mbed_official 632:7687fb9c4f91 863 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
mbed_official 632:7687fb9c4f91 864 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
mbed_official 632:7687fb9c4f91 865
mbed_official 632:7687fb9c4f91 866 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
mbed_official 632:7687fb9c4f91 867 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
mbed_official 632:7687fb9c4f91 868 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
mbed_official 632:7687fb9c4f91 869
mbed_official 632:7687fb9c4f91 870 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
mbed_official 632:7687fb9c4f91 871
mbed_official 632:7687fb9c4f91 872 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
mbed_official 632:7687fb9c4f91 873 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
mbed_official 632:7687fb9c4f91 874 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
mbed_official 632:7687fb9c4f91 875 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
mbed_official 632:7687fb9c4f91 876 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
mbed_official 632:7687fb9c4f91 877
mbed_official 632:7687fb9c4f91 878 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
mbed_official 632:7687fb9c4f91 879 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
mbed_official 632:7687fb9c4f91 880 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
mbed_official 632:7687fb9c4f91 881
mbed_official 632:7687fb9c4f91 882 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
mbed_official 632:7687fb9c4f91 883 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
mbed_official 632:7687fb9c4f91 884 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
mbed_official 632:7687fb9c4f91 885 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
mbed_official 632:7687fb9c4f91 886 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
mbed_official 632:7687fb9c4f91 887
mbed_official 632:7687fb9c4f91 888 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
mbed_official 632:7687fb9c4f91 889 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
mbed_official 632:7687fb9c4f91 890 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
mbed_official 632:7687fb9c4f91 891 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
mbed_official 632:7687fb9c4f91 892
mbed_official 632:7687fb9c4f91 893 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
mbed_official 632:7687fb9c4f91 894 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
mbed_official 632:7687fb9c4f91 895 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
mbed_official 632:7687fb9c4f91 896 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
mbed_official 632:7687fb9c4f91 897 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
mbed_official 632:7687fb9c4f91 898 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
mbed_official 632:7687fb9c4f91 899
mbed_official 632:7687fb9c4f91 900 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
mbed_official 632:7687fb9c4f91 901 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
mbed_official 632:7687fb9c4f91 902 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
mbed_official 632:7687fb9c4f91 903 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
mbed_official 632:7687fb9c4f91 904 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
mbed_official 632:7687fb9c4f91 905 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
mbed_official 632:7687fb9c4f91 906
mbed_official 632:7687fb9c4f91 907 /******************** Bit definition for ADC_SMPR1 register ********************/
mbed_official 632:7687fb9c4f91 908 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
mbed_official 632:7687fb9c4f91 909 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
mbed_official 632:7687fb9c4f91 910 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
mbed_official 632:7687fb9c4f91 911 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
mbed_official 632:7687fb9c4f91 912
mbed_official 632:7687fb9c4f91 913 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
mbed_official 632:7687fb9c4f91 914 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
mbed_official 632:7687fb9c4f91 915 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
mbed_official 632:7687fb9c4f91 916 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
mbed_official 632:7687fb9c4f91 917
mbed_official 632:7687fb9c4f91 918 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
mbed_official 632:7687fb9c4f91 919 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
mbed_official 632:7687fb9c4f91 920 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
mbed_official 632:7687fb9c4f91 921 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
mbed_official 632:7687fb9c4f91 922
mbed_official 632:7687fb9c4f91 923 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
mbed_official 632:7687fb9c4f91 924 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
mbed_official 632:7687fb9c4f91 925 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
mbed_official 632:7687fb9c4f91 926 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
mbed_official 632:7687fb9c4f91 927
mbed_official 632:7687fb9c4f91 928 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
mbed_official 632:7687fb9c4f91 929 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
mbed_official 632:7687fb9c4f91 930 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
mbed_official 632:7687fb9c4f91 931 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
mbed_official 632:7687fb9c4f91 932
mbed_official 632:7687fb9c4f91 933 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
mbed_official 632:7687fb9c4f91 934 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
mbed_official 632:7687fb9c4f91 935 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
mbed_official 632:7687fb9c4f91 936 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
mbed_official 632:7687fb9c4f91 937
mbed_official 632:7687fb9c4f91 938 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
mbed_official 632:7687fb9c4f91 939 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
mbed_official 632:7687fb9c4f91 940 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
mbed_official 632:7687fb9c4f91 941 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
mbed_official 632:7687fb9c4f91 942
mbed_official 632:7687fb9c4f91 943 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
mbed_official 632:7687fb9c4f91 944 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
mbed_official 632:7687fb9c4f91 945 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
mbed_official 632:7687fb9c4f91 946 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
mbed_official 632:7687fb9c4f91 947
mbed_official 632:7687fb9c4f91 948 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
mbed_official 632:7687fb9c4f91 949 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
mbed_official 632:7687fb9c4f91 950 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
mbed_official 632:7687fb9c4f91 951 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
mbed_official 632:7687fb9c4f91 952
mbed_official 632:7687fb9c4f91 953 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
mbed_official 632:7687fb9c4f91 954 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
mbed_official 632:7687fb9c4f91 955 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
mbed_official 632:7687fb9c4f91 956 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
mbed_official 632:7687fb9c4f91 957
mbed_official 632:7687fb9c4f91 958 /******************** Bit definition for ADC_SMPR2 register ********************/
mbed_official 632:7687fb9c4f91 959 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
mbed_official 632:7687fb9c4f91 960 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
mbed_official 632:7687fb9c4f91 961 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
mbed_official 632:7687fb9c4f91 962 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
mbed_official 632:7687fb9c4f91 963
mbed_official 632:7687fb9c4f91 964 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
mbed_official 632:7687fb9c4f91 965 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
mbed_official 632:7687fb9c4f91 966 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
mbed_official 632:7687fb9c4f91 967 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
mbed_official 632:7687fb9c4f91 968
mbed_official 632:7687fb9c4f91 969 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
mbed_official 632:7687fb9c4f91 970 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
mbed_official 632:7687fb9c4f91 971 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
mbed_official 632:7687fb9c4f91 972 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
mbed_official 632:7687fb9c4f91 973
mbed_official 632:7687fb9c4f91 974 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
mbed_official 632:7687fb9c4f91 975 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
mbed_official 632:7687fb9c4f91 976 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
mbed_official 632:7687fb9c4f91 977 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
mbed_official 632:7687fb9c4f91 978
mbed_official 632:7687fb9c4f91 979 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
mbed_official 632:7687fb9c4f91 980 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
mbed_official 632:7687fb9c4f91 981 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
mbed_official 632:7687fb9c4f91 982 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
mbed_official 632:7687fb9c4f91 983
mbed_official 632:7687fb9c4f91 984 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
mbed_official 632:7687fb9c4f91 985 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
mbed_official 632:7687fb9c4f91 986 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
mbed_official 632:7687fb9c4f91 987 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
mbed_official 632:7687fb9c4f91 988
mbed_official 632:7687fb9c4f91 989 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
mbed_official 632:7687fb9c4f91 990 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
mbed_official 632:7687fb9c4f91 991 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
mbed_official 632:7687fb9c4f91 992 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
mbed_official 632:7687fb9c4f91 993
mbed_official 632:7687fb9c4f91 994 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
mbed_official 632:7687fb9c4f91 995 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
mbed_official 632:7687fb9c4f91 996 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
mbed_official 632:7687fb9c4f91 997 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
mbed_official 632:7687fb9c4f91 998
mbed_official 632:7687fb9c4f91 999 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
mbed_official 632:7687fb9c4f91 1000 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
mbed_official 632:7687fb9c4f91 1001 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
mbed_official 632:7687fb9c4f91 1002 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
mbed_official 632:7687fb9c4f91 1003
mbed_official 632:7687fb9c4f91 1004 /******************** Bit definition for ADC_TR1 register ********************/
mbed_official 632:7687fb9c4f91 1005 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
mbed_official 632:7687fb9c4f91 1006 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
mbed_official 632:7687fb9c4f91 1007 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
mbed_official 632:7687fb9c4f91 1008 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
mbed_official 632:7687fb9c4f91 1009 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
mbed_official 632:7687fb9c4f91 1010 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
mbed_official 632:7687fb9c4f91 1011 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
mbed_official 632:7687fb9c4f91 1012 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
mbed_official 632:7687fb9c4f91 1013 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
mbed_official 632:7687fb9c4f91 1014 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
mbed_official 632:7687fb9c4f91 1015 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
mbed_official 632:7687fb9c4f91 1016 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
mbed_official 632:7687fb9c4f91 1017 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
mbed_official 632:7687fb9c4f91 1018
mbed_official 632:7687fb9c4f91 1019 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
mbed_official 632:7687fb9c4f91 1020 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
mbed_official 632:7687fb9c4f91 1021 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
mbed_official 632:7687fb9c4f91 1022 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
mbed_official 632:7687fb9c4f91 1023 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
mbed_official 632:7687fb9c4f91 1024 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
mbed_official 632:7687fb9c4f91 1025 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
mbed_official 632:7687fb9c4f91 1026 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
mbed_official 632:7687fb9c4f91 1027 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
mbed_official 632:7687fb9c4f91 1028 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
mbed_official 632:7687fb9c4f91 1029 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
mbed_official 632:7687fb9c4f91 1030 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
mbed_official 632:7687fb9c4f91 1031 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
mbed_official 632:7687fb9c4f91 1032
mbed_official 632:7687fb9c4f91 1033 /******************** Bit definition for ADC_TR2 register ********************/
mbed_official 632:7687fb9c4f91 1034 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
mbed_official 632:7687fb9c4f91 1035 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
mbed_official 632:7687fb9c4f91 1036 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
mbed_official 632:7687fb9c4f91 1037 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
mbed_official 632:7687fb9c4f91 1038 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
mbed_official 632:7687fb9c4f91 1039 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
mbed_official 632:7687fb9c4f91 1040 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
mbed_official 632:7687fb9c4f91 1041 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
mbed_official 632:7687fb9c4f91 1042 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
mbed_official 632:7687fb9c4f91 1043
mbed_official 632:7687fb9c4f91 1044 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
mbed_official 632:7687fb9c4f91 1045 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
mbed_official 632:7687fb9c4f91 1046 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
mbed_official 632:7687fb9c4f91 1047 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
mbed_official 632:7687fb9c4f91 1048 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
mbed_official 632:7687fb9c4f91 1049 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
mbed_official 632:7687fb9c4f91 1050 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
mbed_official 632:7687fb9c4f91 1051 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
mbed_official 632:7687fb9c4f91 1052 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
mbed_official 632:7687fb9c4f91 1053
mbed_official 632:7687fb9c4f91 1054 /******************** Bit definition for ADC_TR3 register ********************/
mbed_official 632:7687fb9c4f91 1055 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
mbed_official 632:7687fb9c4f91 1056 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
mbed_official 632:7687fb9c4f91 1057 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
mbed_official 632:7687fb9c4f91 1058 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
mbed_official 632:7687fb9c4f91 1059 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
mbed_official 632:7687fb9c4f91 1060 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
mbed_official 632:7687fb9c4f91 1061 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
mbed_official 632:7687fb9c4f91 1062 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
mbed_official 632:7687fb9c4f91 1063 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
mbed_official 632:7687fb9c4f91 1064
mbed_official 632:7687fb9c4f91 1065 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
mbed_official 632:7687fb9c4f91 1066 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
mbed_official 632:7687fb9c4f91 1067 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
mbed_official 632:7687fb9c4f91 1068 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
mbed_official 632:7687fb9c4f91 1069 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
mbed_official 632:7687fb9c4f91 1070 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
mbed_official 632:7687fb9c4f91 1071 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
mbed_official 632:7687fb9c4f91 1072 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
mbed_official 632:7687fb9c4f91 1073 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
mbed_official 632:7687fb9c4f91 1074
mbed_official 632:7687fb9c4f91 1075 /******************** Bit definition for ADC_SQR1 register ********************/
mbed_official 632:7687fb9c4f91 1076 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
mbed_official 632:7687fb9c4f91 1077 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
mbed_official 632:7687fb9c4f91 1078 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
mbed_official 632:7687fb9c4f91 1079 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
mbed_official 632:7687fb9c4f91 1080 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
mbed_official 632:7687fb9c4f91 1081
mbed_official 632:7687fb9c4f91 1082 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1083 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
mbed_official 632:7687fb9c4f91 1084 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
mbed_official 632:7687fb9c4f91 1085 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
mbed_official 632:7687fb9c4f91 1086 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
mbed_official 632:7687fb9c4f91 1087 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
mbed_official 632:7687fb9c4f91 1088
mbed_official 632:7687fb9c4f91 1089 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1090 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
mbed_official 632:7687fb9c4f91 1091 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
mbed_official 632:7687fb9c4f91 1092 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
mbed_official 632:7687fb9c4f91 1093 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
mbed_official 632:7687fb9c4f91 1094 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
mbed_official 632:7687fb9c4f91 1095
mbed_official 632:7687fb9c4f91 1096 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1097 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
mbed_official 632:7687fb9c4f91 1098 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
mbed_official 632:7687fb9c4f91 1099 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
mbed_official 632:7687fb9c4f91 1100 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
mbed_official 632:7687fb9c4f91 1101 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
mbed_official 632:7687fb9c4f91 1102
mbed_official 632:7687fb9c4f91 1103 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1104 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
mbed_official 632:7687fb9c4f91 1105 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
mbed_official 632:7687fb9c4f91 1106 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
mbed_official 632:7687fb9c4f91 1107 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
mbed_official 632:7687fb9c4f91 1108 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
mbed_official 632:7687fb9c4f91 1109
mbed_official 632:7687fb9c4f91 1110 /******************** Bit definition for ADC_SQR2 register ********************/
mbed_official 632:7687fb9c4f91 1111 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1112 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
mbed_official 632:7687fb9c4f91 1113 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
mbed_official 632:7687fb9c4f91 1114 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
mbed_official 632:7687fb9c4f91 1115 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
mbed_official 632:7687fb9c4f91 1116 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
mbed_official 632:7687fb9c4f91 1117
mbed_official 632:7687fb9c4f91 1118 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1119 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
mbed_official 632:7687fb9c4f91 1120 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
mbed_official 632:7687fb9c4f91 1121 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
mbed_official 632:7687fb9c4f91 1122 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
mbed_official 632:7687fb9c4f91 1123 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
mbed_official 632:7687fb9c4f91 1124
mbed_official 632:7687fb9c4f91 1125 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1126 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
mbed_official 632:7687fb9c4f91 1127 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
mbed_official 632:7687fb9c4f91 1128 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
mbed_official 632:7687fb9c4f91 1129 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
mbed_official 632:7687fb9c4f91 1130 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
mbed_official 632:7687fb9c4f91 1131
mbed_official 632:7687fb9c4f91 1132 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1133 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
mbed_official 632:7687fb9c4f91 1134 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
mbed_official 632:7687fb9c4f91 1135 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
mbed_official 632:7687fb9c4f91 1136 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
mbed_official 632:7687fb9c4f91 1137 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
mbed_official 632:7687fb9c4f91 1138
mbed_official 632:7687fb9c4f91 1139 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1140 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
mbed_official 632:7687fb9c4f91 1141 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
mbed_official 632:7687fb9c4f91 1142 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
mbed_official 632:7687fb9c4f91 1143 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
mbed_official 632:7687fb9c4f91 1144 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
mbed_official 632:7687fb9c4f91 1145
mbed_official 632:7687fb9c4f91 1146 /******************** Bit definition for ADC_SQR3 register ********************/
mbed_official 632:7687fb9c4f91 1147 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1148 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
mbed_official 632:7687fb9c4f91 1149 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
mbed_official 632:7687fb9c4f91 1150 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
mbed_official 632:7687fb9c4f91 1151 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
mbed_official 632:7687fb9c4f91 1152 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
mbed_official 632:7687fb9c4f91 1153
mbed_official 632:7687fb9c4f91 1154 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1155 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
mbed_official 632:7687fb9c4f91 1156 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
mbed_official 632:7687fb9c4f91 1157 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
mbed_official 632:7687fb9c4f91 1158 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
mbed_official 632:7687fb9c4f91 1159 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
mbed_official 632:7687fb9c4f91 1160
mbed_official 632:7687fb9c4f91 1161 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1162 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
mbed_official 632:7687fb9c4f91 1163 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
mbed_official 632:7687fb9c4f91 1164 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
mbed_official 632:7687fb9c4f91 1165 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
mbed_official 632:7687fb9c4f91 1166 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
mbed_official 632:7687fb9c4f91 1167
mbed_official 632:7687fb9c4f91 1168 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1169 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
mbed_official 632:7687fb9c4f91 1170 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
mbed_official 632:7687fb9c4f91 1171 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
mbed_official 632:7687fb9c4f91 1172 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
mbed_official 632:7687fb9c4f91 1173 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
mbed_official 632:7687fb9c4f91 1174
mbed_official 632:7687fb9c4f91 1175 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1176 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
mbed_official 632:7687fb9c4f91 1177 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
mbed_official 632:7687fb9c4f91 1178 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
mbed_official 632:7687fb9c4f91 1179 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
mbed_official 632:7687fb9c4f91 1180 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
mbed_official 632:7687fb9c4f91 1181
mbed_official 632:7687fb9c4f91 1182 /******************** Bit definition for ADC_SQR4 register ********************/
mbed_official 632:7687fb9c4f91 1183 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1184 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
mbed_official 632:7687fb9c4f91 1185 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
mbed_official 632:7687fb9c4f91 1186 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
mbed_official 632:7687fb9c4f91 1187 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
mbed_official 632:7687fb9c4f91 1188 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
mbed_official 632:7687fb9c4f91 1189
mbed_official 632:7687fb9c4f91 1190 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
mbed_official 632:7687fb9c4f91 1191 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
mbed_official 632:7687fb9c4f91 1192 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
mbed_official 632:7687fb9c4f91 1193 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
mbed_official 632:7687fb9c4f91 1194 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
mbed_official 632:7687fb9c4f91 1195 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
mbed_official 632:7687fb9c4f91 1196 /******************** Bit definition for ADC_DR register ********************/
mbed_official 632:7687fb9c4f91 1197 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
mbed_official 632:7687fb9c4f91 1198 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
mbed_official 632:7687fb9c4f91 1199 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
mbed_official 632:7687fb9c4f91 1200 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
mbed_official 632:7687fb9c4f91 1201 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
mbed_official 632:7687fb9c4f91 1202 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
mbed_official 632:7687fb9c4f91 1203 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
mbed_official 632:7687fb9c4f91 1204 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
mbed_official 632:7687fb9c4f91 1205 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
mbed_official 632:7687fb9c4f91 1206 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
mbed_official 632:7687fb9c4f91 1207 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
mbed_official 632:7687fb9c4f91 1208 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
mbed_official 632:7687fb9c4f91 1209 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
mbed_official 632:7687fb9c4f91 1210 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
mbed_official 632:7687fb9c4f91 1211 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
mbed_official 632:7687fb9c4f91 1212 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
mbed_official 632:7687fb9c4f91 1213 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
mbed_official 632:7687fb9c4f91 1214
mbed_official 632:7687fb9c4f91 1215 /******************** Bit definition for ADC_JSQR register ********************/
mbed_official 632:7687fb9c4f91 1216 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
mbed_official 632:7687fb9c4f91 1217 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
mbed_official 632:7687fb9c4f91 1218 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
mbed_official 632:7687fb9c4f91 1219
mbed_official 632:7687fb9c4f91 1220 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
mbed_official 632:7687fb9c4f91 1221 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
mbed_official 632:7687fb9c4f91 1222 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
mbed_official 632:7687fb9c4f91 1223 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
mbed_official 632:7687fb9c4f91 1224 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
mbed_official 632:7687fb9c4f91 1225
mbed_official 632:7687fb9c4f91 1226 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
mbed_official 632:7687fb9c4f91 1227 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
mbed_official 632:7687fb9c4f91 1228 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
mbed_official 632:7687fb9c4f91 1229
mbed_official 632:7687fb9c4f91 1230 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
mbed_official 632:7687fb9c4f91 1231 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
mbed_official 632:7687fb9c4f91 1232 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
mbed_official 632:7687fb9c4f91 1233 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
mbed_official 632:7687fb9c4f91 1234 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
mbed_official 632:7687fb9c4f91 1235 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
mbed_official 632:7687fb9c4f91 1236
mbed_official 632:7687fb9c4f91 1237 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
mbed_official 632:7687fb9c4f91 1238 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
mbed_official 632:7687fb9c4f91 1239 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
mbed_official 632:7687fb9c4f91 1240 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
mbed_official 632:7687fb9c4f91 1241 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
mbed_official 632:7687fb9c4f91 1242 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
mbed_official 632:7687fb9c4f91 1243
mbed_official 632:7687fb9c4f91 1244 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
mbed_official 632:7687fb9c4f91 1245 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
mbed_official 632:7687fb9c4f91 1246 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
mbed_official 632:7687fb9c4f91 1247 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
mbed_official 632:7687fb9c4f91 1248 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
mbed_official 632:7687fb9c4f91 1249 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
mbed_official 632:7687fb9c4f91 1250
mbed_official 632:7687fb9c4f91 1251 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
mbed_official 632:7687fb9c4f91 1252 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
mbed_official 632:7687fb9c4f91 1253 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
mbed_official 632:7687fb9c4f91 1254 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
mbed_official 632:7687fb9c4f91 1255 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
mbed_official 632:7687fb9c4f91 1256 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
mbed_official 632:7687fb9c4f91 1257
mbed_official 632:7687fb9c4f91 1258 /******************** Bit definition for ADC_OFR1 register ********************/
mbed_official 632:7687fb9c4f91 1259 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
mbed_official 632:7687fb9c4f91 1260 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
mbed_official 632:7687fb9c4f91 1261 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
mbed_official 632:7687fb9c4f91 1262 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
mbed_official 632:7687fb9c4f91 1263 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
mbed_official 632:7687fb9c4f91 1264 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
mbed_official 632:7687fb9c4f91 1265 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
mbed_official 632:7687fb9c4f91 1266 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
mbed_official 632:7687fb9c4f91 1267 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
mbed_official 632:7687fb9c4f91 1268 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
mbed_official 632:7687fb9c4f91 1269 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
mbed_official 632:7687fb9c4f91 1270 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
mbed_official 632:7687fb9c4f91 1271 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
mbed_official 632:7687fb9c4f91 1272
mbed_official 632:7687fb9c4f91 1273 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
mbed_official 632:7687fb9c4f91 1274 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
mbed_official 632:7687fb9c4f91 1275 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
mbed_official 632:7687fb9c4f91 1276 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
mbed_official 632:7687fb9c4f91 1277 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
mbed_official 632:7687fb9c4f91 1278 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
mbed_official 632:7687fb9c4f91 1279
mbed_official 632:7687fb9c4f91 1280 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
mbed_official 632:7687fb9c4f91 1281
mbed_official 632:7687fb9c4f91 1282 /******************** Bit definition for ADC_OFR2 register ********************/
mbed_official 632:7687fb9c4f91 1283 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
mbed_official 632:7687fb9c4f91 1284 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
mbed_official 632:7687fb9c4f91 1285 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
mbed_official 632:7687fb9c4f91 1286 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
mbed_official 632:7687fb9c4f91 1287 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
mbed_official 632:7687fb9c4f91 1288 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
mbed_official 632:7687fb9c4f91 1289 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
mbed_official 632:7687fb9c4f91 1290 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
mbed_official 632:7687fb9c4f91 1291 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
mbed_official 632:7687fb9c4f91 1292 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
mbed_official 632:7687fb9c4f91 1293 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
mbed_official 632:7687fb9c4f91 1294 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
mbed_official 632:7687fb9c4f91 1295 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
mbed_official 632:7687fb9c4f91 1296
mbed_official 632:7687fb9c4f91 1297 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
mbed_official 632:7687fb9c4f91 1298 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
mbed_official 632:7687fb9c4f91 1299 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
mbed_official 632:7687fb9c4f91 1300 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
mbed_official 632:7687fb9c4f91 1301 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
mbed_official 632:7687fb9c4f91 1302 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
mbed_official 632:7687fb9c4f91 1303
mbed_official 632:7687fb9c4f91 1304 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
mbed_official 632:7687fb9c4f91 1305
mbed_official 632:7687fb9c4f91 1306 /******************** Bit definition for ADC_OFR3 register ********************/
mbed_official 632:7687fb9c4f91 1307 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
mbed_official 632:7687fb9c4f91 1308 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
mbed_official 632:7687fb9c4f91 1309 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
mbed_official 632:7687fb9c4f91 1310 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
mbed_official 632:7687fb9c4f91 1311 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
mbed_official 632:7687fb9c4f91 1312 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
mbed_official 632:7687fb9c4f91 1313 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
mbed_official 632:7687fb9c4f91 1314 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
mbed_official 632:7687fb9c4f91 1315 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
mbed_official 632:7687fb9c4f91 1316 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
mbed_official 632:7687fb9c4f91 1317 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
mbed_official 632:7687fb9c4f91 1318 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
mbed_official 632:7687fb9c4f91 1319 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
mbed_official 632:7687fb9c4f91 1320
mbed_official 632:7687fb9c4f91 1321 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
mbed_official 632:7687fb9c4f91 1322 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
mbed_official 632:7687fb9c4f91 1323 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
mbed_official 632:7687fb9c4f91 1324 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
mbed_official 632:7687fb9c4f91 1325 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
mbed_official 632:7687fb9c4f91 1326 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
mbed_official 632:7687fb9c4f91 1327
mbed_official 632:7687fb9c4f91 1328 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
mbed_official 632:7687fb9c4f91 1329
mbed_official 632:7687fb9c4f91 1330 /******************** Bit definition for ADC_OFR4 register ********************/
mbed_official 632:7687fb9c4f91 1331 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
mbed_official 632:7687fb9c4f91 1332 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
mbed_official 632:7687fb9c4f91 1333 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
mbed_official 632:7687fb9c4f91 1334 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
mbed_official 632:7687fb9c4f91 1335 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
mbed_official 632:7687fb9c4f91 1336 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
mbed_official 632:7687fb9c4f91 1337 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
mbed_official 632:7687fb9c4f91 1338 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
mbed_official 632:7687fb9c4f91 1339 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
mbed_official 632:7687fb9c4f91 1340 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
mbed_official 632:7687fb9c4f91 1341 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
mbed_official 632:7687fb9c4f91 1342 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
mbed_official 632:7687fb9c4f91 1343 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
mbed_official 632:7687fb9c4f91 1344
mbed_official 632:7687fb9c4f91 1345 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
mbed_official 632:7687fb9c4f91 1346 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
mbed_official 632:7687fb9c4f91 1347 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
mbed_official 632:7687fb9c4f91 1348 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
mbed_official 632:7687fb9c4f91 1349 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
mbed_official 632:7687fb9c4f91 1350 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
mbed_official 632:7687fb9c4f91 1351
mbed_official 632:7687fb9c4f91 1352 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
mbed_official 632:7687fb9c4f91 1353
mbed_official 632:7687fb9c4f91 1354 /******************** Bit definition for ADC_JDR1 register ********************/
mbed_official 632:7687fb9c4f91 1355 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 632:7687fb9c4f91 1356 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 632:7687fb9c4f91 1357 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 632:7687fb9c4f91 1358 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 632:7687fb9c4f91 1359 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 632:7687fb9c4f91 1360 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 632:7687fb9c4f91 1361 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 632:7687fb9c4f91 1362 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 632:7687fb9c4f91 1363 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 632:7687fb9c4f91 1364 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 632:7687fb9c4f91 1365 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 632:7687fb9c4f91 1366 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 632:7687fb9c4f91 1367 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 632:7687fb9c4f91 1368 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 632:7687fb9c4f91 1369 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 632:7687fb9c4f91 1370 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 632:7687fb9c4f91 1371 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 632:7687fb9c4f91 1372
mbed_official 632:7687fb9c4f91 1373 /******************** Bit definition for ADC_JDR2 register ********************/
mbed_official 632:7687fb9c4f91 1374 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 632:7687fb9c4f91 1375 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 632:7687fb9c4f91 1376 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 632:7687fb9c4f91 1377 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 632:7687fb9c4f91 1378 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 632:7687fb9c4f91 1379 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 632:7687fb9c4f91 1380 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 632:7687fb9c4f91 1381 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 632:7687fb9c4f91 1382 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 632:7687fb9c4f91 1383 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 632:7687fb9c4f91 1384 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 632:7687fb9c4f91 1385 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 632:7687fb9c4f91 1386 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 632:7687fb9c4f91 1387 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 632:7687fb9c4f91 1388 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 632:7687fb9c4f91 1389 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 632:7687fb9c4f91 1390 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 632:7687fb9c4f91 1391
mbed_official 632:7687fb9c4f91 1392 /******************** Bit definition for ADC_JDR3 register ********************/
mbed_official 632:7687fb9c4f91 1393 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 632:7687fb9c4f91 1394 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 632:7687fb9c4f91 1395 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 632:7687fb9c4f91 1396 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 632:7687fb9c4f91 1397 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 632:7687fb9c4f91 1398 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 632:7687fb9c4f91 1399 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 632:7687fb9c4f91 1400 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 632:7687fb9c4f91 1401 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 632:7687fb9c4f91 1402 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 632:7687fb9c4f91 1403 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 632:7687fb9c4f91 1404 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 632:7687fb9c4f91 1405 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 632:7687fb9c4f91 1406 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 632:7687fb9c4f91 1407 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 632:7687fb9c4f91 1408 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 632:7687fb9c4f91 1409 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 632:7687fb9c4f91 1410
mbed_official 632:7687fb9c4f91 1411 /******************** Bit definition for ADC_JDR4 register ********************/
mbed_official 632:7687fb9c4f91 1412 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 632:7687fb9c4f91 1413 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 632:7687fb9c4f91 1414 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 632:7687fb9c4f91 1415 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 632:7687fb9c4f91 1416 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 632:7687fb9c4f91 1417 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 632:7687fb9c4f91 1418 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 632:7687fb9c4f91 1419 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 632:7687fb9c4f91 1420 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 632:7687fb9c4f91 1421 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 632:7687fb9c4f91 1422 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 632:7687fb9c4f91 1423 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 632:7687fb9c4f91 1424 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 632:7687fb9c4f91 1425 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 632:7687fb9c4f91 1426 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 632:7687fb9c4f91 1427 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 632:7687fb9c4f91 1428 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 632:7687fb9c4f91 1429
mbed_official 632:7687fb9c4f91 1430 /******************** Bit definition for ADC_AWD2CR register ********************/
mbed_official 632:7687fb9c4f91 1431 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 632:7687fb9c4f91 1432 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
mbed_official 632:7687fb9c4f91 1433 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
mbed_official 632:7687fb9c4f91 1434 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
mbed_official 632:7687fb9c4f91 1435 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
mbed_official 632:7687fb9c4f91 1436 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
mbed_official 632:7687fb9c4f91 1437 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
mbed_official 632:7687fb9c4f91 1438 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
mbed_official 632:7687fb9c4f91 1439 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
mbed_official 632:7687fb9c4f91 1440 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
mbed_official 632:7687fb9c4f91 1441 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
mbed_official 632:7687fb9c4f91 1442 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
mbed_official 632:7687fb9c4f91 1443 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
mbed_official 632:7687fb9c4f91 1444 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
mbed_official 632:7687fb9c4f91 1445 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
mbed_official 632:7687fb9c4f91 1446 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
mbed_official 632:7687fb9c4f91 1447 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
mbed_official 632:7687fb9c4f91 1448 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
mbed_official 632:7687fb9c4f91 1449 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
mbed_official 632:7687fb9c4f91 1450
mbed_official 632:7687fb9c4f91 1451 /******************** Bit definition for ADC_AWD3CR register ********************/
mbed_official 632:7687fb9c4f91 1452 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 632:7687fb9c4f91 1453 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
mbed_official 632:7687fb9c4f91 1454 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
mbed_official 632:7687fb9c4f91 1455 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
mbed_official 632:7687fb9c4f91 1456 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
mbed_official 632:7687fb9c4f91 1457 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
mbed_official 632:7687fb9c4f91 1458 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
mbed_official 632:7687fb9c4f91 1459 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
mbed_official 632:7687fb9c4f91 1460 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
mbed_official 632:7687fb9c4f91 1461 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
mbed_official 632:7687fb9c4f91 1462 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
mbed_official 632:7687fb9c4f91 1463 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
mbed_official 632:7687fb9c4f91 1464 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
mbed_official 632:7687fb9c4f91 1465 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
mbed_official 632:7687fb9c4f91 1466 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
mbed_official 632:7687fb9c4f91 1467 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
mbed_official 632:7687fb9c4f91 1468 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
mbed_official 632:7687fb9c4f91 1469 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
mbed_official 632:7687fb9c4f91 1470 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
mbed_official 632:7687fb9c4f91 1471
mbed_official 632:7687fb9c4f91 1472 /******************** Bit definition for ADC_DIFSEL register ********************/
mbed_official 632:7687fb9c4f91 1473 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
mbed_official 632:7687fb9c4f91 1474 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
mbed_official 632:7687fb9c4f91 1475 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
mbed_official 632:7687fb9c4f91 1476 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
mbed_official 632:7687fb9c4f91 1477 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
mbed_official 632:7687fb9c4f91 1478 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
mbed_official 632:7687fb9c4f91 1479 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
mbed_official 632:7687fb9c4f91 1480 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
mbed_official 632:7687fb9c4f91 1481 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
mbed_official 632:7687fb9c4f91 1482 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
mbed_official 632:7687fb9c4f91 1483 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
mbed_official 632:7687fb9c4f91 1484 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
mbed_official 632:7687fb9c4f91 1485 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
mbed_official 632:7687fb9c4f91 1486 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
mbed_official 632:7687fb9c4f91 1487 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
mbed_official 632:7687fb9c4f91 1488 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
mbed_official 632:7687fb9c4f91 1489 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
mbed_official 632:7687fb9c4f91 1490 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
mbed_official 632:7687fb9c4f91 1491 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
mbed_official 632:7687fb9c4f91 1492
mbed_official 632:7687fb9c4f91 1493 /******************** Bit definition for ADC_CALFACT register ********************/
mbed_official 632:7687fb9c4f91 1494 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
mbed_official 632:7687fb9c4f91 1495 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
mbed_official 632:7687fb9c4f91 1496 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
mbed_official 632:7687fb9c4f91 1497 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
mbed_official 632:7687fb9c4f91 1498 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
mbed_official 632:7687fb9c4f91 1499 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
mbed_official 632:7687fb9c4f91 1500 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
mbed_official 632:7687fb9c4f91 1501 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
mbed_official 632:7687fb9c4f91 1502 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
mbed_official 632:7687fb9c4f91 1503 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
mbed_official 632:7687fb9c4f91 1504 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
mbed_official 632:7687fb9c4f91 1505 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
mbed_official 632:7687fb9c4f91 1506 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
mbed_official 632:7687fb9c4f91 1507 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
mbed_official 632:7687fb9c4f91 1508 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
mbed_official 632:7687fb9c4f91 1509 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
mbed_official 632:7687fb9c4f91 1510
mbed_official 632:7687fb9c4f91 1511 /************************* ADC Common registers *****************************/
mbed_official 632:7687fb9c4f91 1512 /******************** Bit definition for ADC12_CSR register ********************/
mbed_official 632:7687fb9c4f91 1513 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 632:7687fb9c4f91 1514 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 632:7687fb9c4f91 1515 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 632:7687fb9c4f91 1516 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 632:7687fb9c4f91 1517 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 632:7687fb9c4f91 1518 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 632:7687fb9c4f91 1519 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 632:7687fb9c4f91 1520 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 632:7687fb9c4f91 1521 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 632:7687fb9c4f91 1522 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 632:7687fb9c4f91 1523 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 632:7687fb9c4f91 1524 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 632:7687fb9c4f91 1525 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1526 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 632:7687fb9c4f91 1527 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1528 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1529 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 632:7687fb9c4f91 1530 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1531 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1532 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1533 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1534 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 632:7687fb9c4f91 1535
mbed_official 632:7687fb9c4f91 1536 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 632:7687fb9c4f91 1537 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 632:7687fb9c4f91 1538 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 632:7687fb9c4f91 1539 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 632:7687fb9c4f91 1540 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 632:7687fb9c4f91 1541 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 632:7687fb9c4f91 1542 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 632:7687fb9c4f91 1543 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 632:7687fb9c4f91 1544 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 632:7687fb9c4f91 1545 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 632:7687fb9c4f91 1546 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 632:7687fb9c4f91 1547 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 632:7687fb9c4f91 1548 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 632:7687fb9c4f91 1549 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 632:7687fb9c4f91 1550 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 632:7687fb9c4f91 1551 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 632:7687fb9c4f91 1552 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 632:7687fb9c4f91 1553 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 632:7687fb9c4f91 1554 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 632:7687fb9c4f91 1555 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 632:7687fb9c4f91 1556 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 632:7687fb9c4f91 1557 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 632:7687fb9c4f91 1558
mbed_official 632:7687fb9c4f91 1559 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 632:7687fb9c4f91 1560 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 632:7687fb9c4f91 1561 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 632:7687fb9c4f91 1562 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 632:7687fb9c4f91 1563 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 632:7687fb9c4f91 1564 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 632:7687fb9c4f91 1565 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 632:7687fb9c4f91 1566 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 632:7687fb9c4f91 1567 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 632:7687fb9c4f91 1568 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 632:7687fb9c4f91 1569 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 632:7687fb9c4f91 1570 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 632:7687fb9c4f91 1571 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 632:7687fb9c4f91 1572 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 632:7687fb9c4f91 1573 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 632:7687fb9c4f91 1574 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 632:7687fb9c4f91 1575 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 632:7687fb9c4f91 1576 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 632:7687fb9c4f91 1577
mbed_official 632:7687fb9c4f91 1578 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 632:7687fb9c4f91 1579 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 632:7687fb9c4f91 1580 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 632:7687fb9c4f91 1581 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 632:7687fb9c4f91 1582 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 632:7687fb9c4f91 1583 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 632:7687fb9c4f91 1584 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 632:7687fb9c4f91 1585 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 632:7687fb9c4f91 1586 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 632:7687fb9c4f91 1587 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 632:7687fb9c4f91 1588 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 632:7687fb9c4f91 1589 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 632:7687fb9c4f91 1590 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 632:7687fb9c4f91 1591 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 632:7687fb9c4f91 1592 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 632:7687fb9c4f91 1593 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 632:7687fb9c4f91 1594 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 632:7687fb9c4f91 1595
mbed_official 632:7687fb9c4f91 1596 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1597 /* */
mbed_official 632:7687fb9c4f91 1598 /* Analog Comparators (COMP) */
mbed_official 632:7687fb9c4f91 1599 /* */
mbed_official 632:7687fb9c4f91 1600 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1601 /********************** Bit definition for COMP2_CSR register ***************/
mbed_official 632:7687fb9c4f91 1602 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
mbed_official 632:7687fb9c4f91 1603 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
mbed_official 632:7687fb9c4f91 1604 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
mbed_official 632:7687fb9c4f91 1605 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
mbed_official 632:7687fb9c4f91 1606 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
mbed_official 632:7687fb9c4f91 1607 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
mbed_official 632:7687fb9c4f91 1608 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
mbed_official 632:7687fb9c4f91 1609 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
mbed_official 632:7687fb9c4f91 1610 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
mbed_official 632:7687fb9c4f91 1611 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
mbed_official 632:7687fb9c4f91 1612 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
mbed_official 632:7687fb9c4f91 1613 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
mbed_official 632:7687fb9c4f91 1614 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
mbed_official 632:7687fb9c4f91 1615 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
mbed_official 632:7687fb9c4f91 1616 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
mbed_official 632:7687fb9c4f91 1617 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
mbed_official 632:7687fb9c4f91 1618 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 632:7687fb9c4f91 1619 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 632:7687fb9c4f91 1620
mbed_official 632:7687fb9c4f91 1621 /********************** Bit definition for COMP4_CSR register ***************/
mbed_official 632:7687fb9c4f91 1622 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
mbed_official 632:7687fb9c4f91 1623 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
mbed_official 632:7687fb9c4f91 1624 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
mbed_official 632:7687fb9c4f91 1625 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
mbed_official 632:7687fb9c4f91 1626 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
mbed_official 632:7687fb9c4f91 1627 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
mbed_official 632:7687fb9c4f91 1628 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
mbed_official 632:7687fb9c4f91 1629 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
mbed_official 632:7687fb9c4f91 1630 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
mbed_official 632:7687fb9c4f91 1631 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
mbed_official 632:7687fb9c4f91 1632 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
mbed_official 632:7687fb9c4f91 1633 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
mbed_official 632:7687fb9c4f91 1634 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
mbed_official 632:7687fb9c4f91 1635 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
mbed_official 632:7687fb9c4f91 1636 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
mbed_official 632:7687fb9c4f91 1637 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
mbed_official 632:7687fb9c4f91 1638 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
mbed_official 632:7687fb9c4f91 1639 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
mbed_official 632:7687fb9c4f91 1640
mbed_official 632:7687fb9c4f91 1641 /********************** Bit definition for COMP6_CSR register ***************/
mbed_official 632:7687fb9c4f91 1642 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
mbed_official 632:7687fb9c4f91 1643 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
mbed_official 632:7687fb9c4f91 1644 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
mbed_official 632:7687fb9c4f91 1645 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
mbed_official 632:7687fb9c4f91 1646 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
mbed_official 632:7687fb9c4f91 1647 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
mbed_official 632:7687fb9c4f91 1648 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
mbed_official 632:7687fb9c4f91 1649 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
mbed_official 632:7687fb9c4f91 1650 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
mbed_official 632:7687fb9c4f91 1651 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
mbed_official 632:7687fb9c4f91 1652 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
mbed_official 632:7687fb9c4f91 1653 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
mbed_official 632:7687fb9c4f91 1654 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
mbed_official 632:7687fb9c4f91 1655 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
mbed_official 632:7687fb9c4f91 1656 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
mbed_official 632:7687fb9c4f91 1657 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
mbed_official 632:7687fb9c4f91 1658 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
mbed_official 632:7687fb9c4f91 1659 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
mbed_official 632:7687fb9c4f91 1660
mbed_official 632:7687fb9c4f91 1661 /********************** Bit definition for COMP_CSR register ****************/
mbed_official 632:7687fb9c4f91 1662 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 632:7687fb9c4f91 1663 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
mbed_official 632:7687fb9c4f91 1664 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 632:7687fb9c4f91 1665 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 632:7687fb9c4f91 1666 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 632:7687fb9c4f91 1667 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
mbed_official 632:7687fb9c4f91 1668 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
mbed_official 632:7687fb9c4f91 1669 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
mbed_official 632:7687fb9c4f91 1670 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
mbed_official 632:7687fb9c4f91 1671 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
mbed_official 632:7687fb9c4f91 1672 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
mbed_official 632:7687fb9c4f91 1673 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
mbed_official 632:7687fb9c4f91 1674 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
mbed_official 632:7687fb9c4f91 1675 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
mbed_official 632:7687fb9c4f91 1676 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
mbed_official 632:7687fb9c4f91 1677 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
mbed_official 632:7687fb9c4f91 1678 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
mbed_official 632:7687fb9c4f91 1679 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
mbed_official 632:7687fb9c4f91 1680
mbed_official 632:7687fb9c4f91 1681 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1682 /* */
mbed_official 632:7687fb9c4f91 1683 /* Operational Amplifier (OPAMP) */
mbed_official 632:7687fb9c4f91 1684 /* */
mbed_official 632:7687fb9c4f91 1685 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1686 /********************* Bit definition for OPAMP2_CSR register ***************/
mbed_official 632:7687fb9c4f91 1687 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
mbed_official 632:7687fb9c4f91 1688 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 632:7687fb9c4f91 1689 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 632:7687fb9c4f91 1690 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1691 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1692 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 632:7687fb9c4f91 1693 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1694 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1695 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 632:7687fb9c4f91 1696 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 632:7687fb9c4f91 1697 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 632:7687fb9c4f91 1698 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1699 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1700 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 632:7687fb9c4f91 1701 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 632:7687fb9c4f91 1702 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1703 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1704 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 632:7687fb9c4f91 1705 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1706 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1707 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 1708 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 1709 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 632:7687fb9c4f91 1710 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 632:7687fb9c4f91 1711 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 632:7687fb9c4f91 1712 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 632:7687fb9c4f91 1713 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 632:7687fb9c4f91 1714 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 632:7687fb9c4f91 1715
mbed_official 632:7687fb9c4f91 1716 /********************* Bit definition for OPAMPx_CSR register ***************/
mbed_official 632:7687fb9c4f91 1717 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
mbed_official 632:7687fb9c4f91 1718 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 632:7687fb9c4f91 1719 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 632:7687fb9c4f91 1720 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1721 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1722 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 632:7687fb9c4f91 1723 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1724 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1725 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 632:7687fb9c4f91 1726 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 632:7687fb9c4f91 1727 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 632:7687fb9c4f91 1728 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1729 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1730 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 632:7687fb9c4f91 1731 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 632:7687fb9c4f91 1732 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1733 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1734 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 632:7687fb9c4f91 1735 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 1736 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 1737 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 1738 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 1739 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 632:7687fb9c4f91 1740 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 632:7687fb9c4f91 1741 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 632:7687fb9c4f91 1742 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 632:7687fb9c4f91 1743 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 632:7687fb9c4f91 1744 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 632:7687fb9c4f91 1745
mbed_official 632:7687fb9c4f91 1746 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1747 /* */
mbed_official 632:7687fb9c4f91 1748 /* Controller Area Network (CAN ) */
mbed_official 632:7687fb9c4f91 1749 /* */
mbed_official 632:7687fb9c4f91 1750 /******************************************************************************/
mbed_official 632:7687fb9c4f91 1751 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 632:7687fb9c4f91 1752 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 632:7687fb9c4f91 1753 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 632:7687fb9c4f91 1754 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 632:7687fb9c4f91 1755 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 632:7687fb9c4f91 1756 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 632:7687fb9c4f91 1757 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 632:7687fb9c4f91 1758 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 632:7687fb9c4f91 1759 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 632:7687fb9c4f91 1760 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 632:7687fb9c4f91 1761
mbed_official 632:7687fb9c4f91 1762 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 632:7687fb9c4f91 1763 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 632:7687fb9c4f91 1764 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 632:7687fb9c4f91 1765 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 632:7687fb9c4f91 1766 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 632:7687fb9c4f91 1767 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 632:7687fb9c4f91 1768 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 632:7687fb9c4f91 1769 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 632:7687fb9c4f91 1770 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 632:7687fb9c4f91 1771 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 632:7687fb9c4f91 1772
mbed_official 632:7687fb9c4f91 1773 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 632:7687fb9c4f91 1774 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 632:7687fb9c4f91 1775 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 632:7687fb9c4f91 1776 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 632:7687fb9c4f91 1777 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 632:7687fb9c4f91 1778 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 632:7687fb9c4f91 1779 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 632:7687fb9c4f91 1780 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 632:7687fb9c4f91 1781 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 632:7687fb9c4f91 1782 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 632:7687fb9c4f91 1783 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 632:7687fb9c4f91 1784 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 632:7687fb9c4f91 1785 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 632:7687fb9c4f91 1786 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 632:7687fb9c4f91 1787 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 632:7687fb9c4f91 1788 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 632:7687fb9c4f91 1789 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 632:7687fb9c4f91 1790
mbed_official 632:7687fb9c4f91 1791 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 632:7687fb9c4f91 1792 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 632:7687fb9c4f91 1793 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 632:7687fb9c4f91 1794 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 632:7687fb9c4f91 1795
mbed_official 632:7687fb9c4f91 1796 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 632:7687fb9c4f91 1797 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 632:7687fb9c4f91 1798 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 632:7687fb9c4f91 1799 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 632:7687fb9c4f91 1800
mbed_official 632:7687fb9c4f91 1801 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 632:7687fb9c4f91 1802 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 632:7687fb9c4f91 1803 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 632:7687fb9c4f91 1804 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 632:7687fb9c4f91 1805 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 632:7687fb9c4f91 1806
mbed_official 632:7687fb9c4f91 1807 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 632:7687fb9c4f91 1808 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 632:7687fb9c4f91 1809 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 632:7687fb9c4f91 1810 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 632:7687fb9c4f91 1811 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 632:7687fb9c4f91 1812
mbed_official 632:7687fb9c4f91 1813 /******************** Bit definition for CAN_IER register *******************/
mbed_official 632:7687fb9c4f91 1814 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 632:7687fb9c4f91 1815 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 632:7687fb9c4f91 1816 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 632:7687fb9c4f91 1817 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 632:7687fb9c4f91 1818 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 632:7687fb9c4f91 1819 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 632:7687fb9c4f91 1820 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 632:7687fb9c4f91 1821 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 632:7687fb9c4f91 1822 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 632:7687fb9c4f91 1823 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 632:7687fb9c4f91 1824 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 632:7687fb9c4f91 1825 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 632:7687fb9c4f91 1826 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 632:7687fb9c4f91 1827 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 632:7687fb9c4f91 1828
mbed_official 632:7687fb9c4f91 1829 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 632:7687fb9c4f91 1830 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 632:7687fb9c4f91 1831 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 632:7687fb9c4f91 1832 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 632:7687fb9c4f91 1833
mbed_official 632:7687fb9c4f91 1834 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 632:7687fb9c4f91 1835 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 1836 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 1837 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 1838
mbed_official 632:7687fb9c4f91 1839 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 632:7687fb9c4f91 1840 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 632:7687fb9c4f91 1841
mbed_official 632:7687fb9c4f91 1842 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 632:7687fb9c4f91 1843 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 632:7687fb9c4f91 1844 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 632:7687fb9c4f91 1845 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 632:7687fb9c4f91 1846 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 632:7687fb9c4f91 1847 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 632:7687fb9c4f91 1848 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 632:7687fb9c4f91 1849 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 632:7687fb9c4f91 1850 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 632:7687fb9c4f91 1851 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 632:7687fb9c4f91 1852 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 632:7687fb9c4f91 1853 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 632:7687fb9c4f91 1854 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 632:7687fb9c4f91 1855 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 632:7687fb9c4f91 1856 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 632:7687fb9c4f91 1857 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 632:7687fb9c4f91 1858
mbed_official 632:7687fb9c4f91 1859 /*!<Mailbox registers */
mbed_official 632:7687fb9c4f91 1860 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 632:7687fb9c4f91 1861 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 632:7687fb9c4f91 1862 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 632:7687fb9c4f91 1863 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 632:7687fb9c4f91 1864 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 632:7687fb9c4f91 1865 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 632:7687fb9c4f91 1866
mbed_official 632:7687fb9c4f91 1867 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 632:7687fb9c4f91 1868 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 632:7687fb9c4f91 1869 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 632:7687fb9c4f91 1870 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 632:7687fb9c4f91 1871
mbed_official 632:7687fb9c4f91 1872 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 632:7687fb9c4f91 1873 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 632:7687fb9c4f91 1874 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 632:7687fb9c4f91 1875 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 632:7687fb9c4f91 1876 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 632:7687fb9c4f91 1877
mbed_official 632:7687fb9c4f91 1878 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 632:7687fb9c4f91 1879 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 632:7687fb9c4f91 1880 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 632:7687fb9c4f91 1881 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 632:7687fb9c4f91 1882 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 632:7687fb9c4f91 1883
mbed_official 632:7687fb9c4f91 1884 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 632:7687fb9c4f91 1885 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 632:7687fb9c4f91 1886 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 632:7687fb9c4f91 1887 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 632:7687fb9c4f91 1888 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 632:7687fb9c4f91 1889 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 632:7687fb9c4f91 1890
mbed_official 632:7687fb9c4f91 1891 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 632:7687fb9c4f91 1892 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 632:7687fb9c4f91 1893 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 632:7687fb9c4f91 1894 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 632:7687fb9c4f91 1895
mbed_official 632:7687fb9c4f91 1896 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 632:7687fb9c4f91 1897 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 632:7687fb9c4f91 1898 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 632:7687fb9c4f91 1899 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 632:7687fb9c4f91 1900 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 632:7687fb9c4f91 1901
mbed_official 632:7687fb9c4f91 1902 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 632:7687fb9c4f91 1903 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 632:7687fb9c4f91 1904 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 632:7687fb9c4f91 1905 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 632:7687fb9c4f91 1906 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 632:7687fb9c4f91 1907
mbed_official 632:7687fb9c4f91 1908 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 632:7687fb9c4f91 1909 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 632:7687fb9c4f91 1910 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 632:7687fb9c4f91 1911 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 632:7687fb9c4f91 1912 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 632:7687fb9c4f91 1913 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 632:7687fb9c4f91 1914
mbed_official 632:7687fb9c4f91 1915 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 632:7687fb9c4f91 1916 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 632:7687fb9c4f91 1917 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 632:7687fb9c4f91 1918 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 632:7687fb9c4f91 1919
mbed_official 632:7687fb9c4f91 1920 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 632:7687fb9c4f91 1921 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 632:7687fb9c4f91 1922 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 632:7687fb9c4f91 1923 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 632:7687fb9c4f91 1924 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 632:7687fb9c4f91 1925
mbed_official 632:7687fb9c4f91 1926 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 632:7687fb9c4f91 1927 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 632:7687fb9c4f91 1928 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 632:7687fb9c4f91 1929 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 632:7687fb9c4f91 1930 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 632:7687fb9c4f91 1931
mbed_official 632:7687fb9c4f91 1932 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 632:7687fb9c4f91 1933 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 632:7687fb9c4f91 1934 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 632:7687fb9c4f91 1935 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 632:7687fb9c4f91 1936 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 632:7687fb9c4f91 1937
mbed_official 632:7687fb9c4f91 1938 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 632:7687fb9c4f91 1939 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 632:7687fb9c4f91 1940 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 632:7687fb9c4f91 1941 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 632:7687fb9c4f91 1942
mbed_official 632:7687fb9c4f91 1943 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 632:7687fb9c4f91 1944 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 632:7687fb9c4f91 1945 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 632:7687fb9c4f91 1946 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 632:7687fb9c4f91 1947 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 632:7687fb9c4f91 1948
mbed_official 632:7687fb9c4f91 1949 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 632:7687fb9c4f91 1950 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 632:7687fb9c4f91 1951 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 632:7687fb9c4f91 1952 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 632:7687fb9c4f91 1953 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 632:7687fb9c4f91 1954
mbed_official 632:7687fb9c4f91 1955 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 632:7687fb9c4f91 1956 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 632:7687fb9c4f91 1957 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 632:7687fb9c4f91 1958 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 632:7687fb9c4f91 1959 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 632:7687fb9c4f91 1960
mbed_official 632:7687fb9c4f91 1961 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 632:7687fb9c4f91 1962 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 632:7687fb9c4f91 1963 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 632:7687fb9c4f91 1964 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 632:7687fb9c4f91 1965
mbed_official 632:7687fb9c4f91 1966 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 632:7687fb9c4f91 1967 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 632:7687fb9c4f91 1968 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 632:7687fb9c4f91 1969 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 632:7687fb9c4f91 1970 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 632:7687fb9c4f91 1971
mbed_official 632:7687fb9c4f91 1972 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 632:7687fb9c4f91 1973 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 632:7687fb9c4f91 1974 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 632:7687fb9c4f91 1975 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 632:7687fb9c4f91 1976 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 632:7687fb9c4f91 1977
mbed_official 632:7687fb9c4f91 1978 /*!<CAN filter registers */
mbed_official 632:7687fb9c4f91 1979 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 632:7687fb9c4f91 1980 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
mbed_official 632:7687fb9c4f91 1981
mbed_official 632:7687fb9c4f91 1982 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 632:7687fb9c4f91 1983 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
mbed_official 632:7687fb9c4f91 1984 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 632:7687fb9c4f91 1985 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 632:7687fb9c4f91 1986 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 632:7687fb9c4f91 1987 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 632:7687fb9c4f91 1988 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 632:7687fb9c4f91 1989 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 632:7687fb9c4f91 1990 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 632:7687fb9c4f91 1991 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 632:7687fb9c4f91 1992 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 632:7687fb9c4f91 1993 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 632:7687fb9c4f91 1994 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 632:7687fb9c4f91 1995 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 632:7687fb9c4f91 1996 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 632:7687fb9c4f91 1997 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 632:7687fb9c4f91 1998
mbed_official 632:7687fb9c4f91 1999 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 632:7687fb9c4f91 2000 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
mbed_official 632:7687fb9c4f91 2001 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 632:7687fb9c4f91 2002 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 632:7687fb9c4f91 2003 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 632:7687fb9c4f91 2004 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 632:7687fb9c4f91 2005 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 632:7687fb9c4f91 2006 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 632:7687fb9c4f91 2007 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 632:7687fb9c4f91 2008 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 632:7687fb9c4f91 2009 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 632:7687fb9c4f91 2010 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 632:7687fb9c4f91 2011 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 632:7687fb9c4f91 2012 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 632:7687fb9c4f91 2013 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 632:7687fb9c4f91 2014 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 632:7687fb9c4f91 2015
mbed_official 632:7687fb9c4f91 2016 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 632:7687fb9c4f91 2017 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
mbed_official 632:7687fb9c4f91 2018 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 632:7687fb9c4f91 2019 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 632:7687fb9c4f91 2020 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 632:7687fb9c4f91 2021 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 632:7687fb9c4f91 2022 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 632:7687fb9c4f91 2023 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 632:7687fb9c4f91 2024 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 632:7687fb9c4f91 2025 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 632:7687fb9c4f91 2026 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 632:7687fb9c4f91 2027 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 632:7687fb9c4f91 2028 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 632:7687fb9c4f91 2029 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 632:7687fb9c4f91 2030 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 632:7687fb9c4f91 2031 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 632:7687fb9c4f91 2032
mbed_official 632:7687fb9c4f91 2033 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 632:7687fb9c4f91 2034 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
mbed_official 632:7687fb9c4f91 2035 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
mbed_official 632:7687fb9c4f91 2036 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
mbed_official 632:7687fb9c4f91 2037 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
mbed_official 632:7687fb9c4f91 2038 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
mbed_official 632:7687fb9c4f91 2039 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
mbed_official 632:7687fb9c4f91 2040 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
mbed_official 632:7687fb9c4f91 2041 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
mbed_official 632:7687fb9c4f91 2042 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
mbed_official 632:7687fb9c4f91 2043 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
mbed_official 632:7687fb9c4f91 2044 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
mbed_official 632:7687fb9c4f91 2045 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
mbed_official 632:7687fb9c4f91 2046 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
mbed_official 632:7687fb9c4f91 2047 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
mbed_official 632:7687fb9c4f91 2048 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
mbed_official 632:7687fb9c4f91 2049
mbed_official 632:7687fb9c4f91 2050 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 632:7687fb9c4f91 2051 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2052 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2053 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2054 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2055 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2056 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2057 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2058 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2059 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2060 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2061 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2062 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2063 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2064 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2065 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2066 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2067 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2068 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2069 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2070 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2071 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2072 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2073 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2074 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2075 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2076 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2077 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2078 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2079 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2080 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2081 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2082 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2083
mbed_official 632:7687fb9c4f91 2084 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 632:7687fb9c4f91 2085 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2086 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2087 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2088 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2089 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2090 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2091 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2092 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2093 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2094 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2095 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2096 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2097 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2098 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2099 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2100 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2101 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2102 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2103 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2104 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2105 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2106 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2107 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2108 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2109 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2110 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2111 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2112 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2113 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2114 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2115 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2116 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2117
mbed_official 632:7687fb9c4f91 2118 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 632:7687fb9c4f91 2119 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2120 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2121 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2122 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2123 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2124 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2125 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2126 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2127 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2128 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2129 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2130 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2131 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2132 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2133 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2134 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2135 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2136 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2137 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2138 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2139 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2140 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2141 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2142 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2143 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2144 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2145 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2146 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2147 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2148 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2149 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2150 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2151
mbed_official 632:7687fb9c4f91 2152 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 632:7687fb9c4f91 2153 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2154 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2155 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2156 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2157 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2158 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2159 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2160 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2161 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2162 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2163 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2164 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2165 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2166 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2167 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2168 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2169 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2170 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2171 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2172 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2173 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2174 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2175 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2176 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2177 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2178 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2179 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2180 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2181 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2182 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2183 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2184 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2185
mbed_official 632:7687fb9c4f91 2186 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 632:7687fb9c4f91 2187 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2188 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2189 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2190 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2191 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2192 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2193 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2194 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2195 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2196 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2197 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2198 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2199 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2200 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2201 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2202 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2203 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2204 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2205 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2206 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2207 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2208 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2209 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2210 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2211 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2212 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2213 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2214 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2215 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2216 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2217 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2218 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2219
mbed_official 632:7687fb9c4f91 2220 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 632:7687fb9c4f91 2221 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2222 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2223 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2224 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2225 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2226 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2227 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2228 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2229 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2230 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2231 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2232 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2233 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2234 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2235 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2236 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2237 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2238 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2239 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2240 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2241 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2242 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2243 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2244 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2245 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2246 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2247 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2248 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2249 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2250 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2251 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2252 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2253
mbed_official 632:7687fb9c4f91 2254 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 632:7687fb9c4f91 2255 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2256 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2257 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2258 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2259 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2260 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2261 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2262 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2263 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2264 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2265 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2266 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2267 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2268 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2269 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2270 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2271 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2272 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2273 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2274 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2275 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2276 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2277 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2278 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2279 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2280 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2281 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2282 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2283 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2284 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2285 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2286 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2287
mbed_official 632:7687fb9c4f91 2288 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 632:7687fb9c4f91 2289 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2290 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2291 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2292 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2293 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2294 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2295 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2296 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2297 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2298 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2299 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2300 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2301 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2302 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2303 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2304 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2305 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2306 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2307 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2308 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2309 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2310 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2311 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2312 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2313 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2314 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2315 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2316 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2317 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2318 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2319 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2320 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2321
mbed_official 632:7687fb9c4f91 2322 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 632:7687fb9c4f91 2323 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2324 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2325 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2326 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2327 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2328 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2329 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2330 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2331 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2332 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2333 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2334 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2335 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2336 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2337 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2338 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2339 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2340 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2341 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2342 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2343 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2344 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2345 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2346 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2347 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2348 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2349 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2350 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2351 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2352 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2353 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2354 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2355
mbed_official 632:7687fb9c4f91 2356 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 632:7687fb9c4f91 2357 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2358 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2359 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2360 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2361 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2362 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2363 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2364 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2365 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2366 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2367 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2368 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2369 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2370 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2371 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2372 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2373 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2374 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2375 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2376 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2377 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2378 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2379 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2380 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2381 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2382 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2383 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2384 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2385 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2386 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2387 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2388 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2389
mbed_official 632:7687fb9c4f91 2390 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 632:7687fb9c4f91 2391 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2392 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2393 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2394 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2395 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2396 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2397 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2398 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2399 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2400 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2401 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2402 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2403 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2404 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2405 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2406 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2407 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2408 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2409 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2410 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2411 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2412 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2413 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2414 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2415 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2416 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2417 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2418 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2419 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2420 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2421 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2422 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2423
mbed_official 632:7687fb9c4f91 2424 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 632:7687fb9c4f91 2425 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2426 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2427 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2428 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2429 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2430 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2431 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2432 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2433 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2434 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2435 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2436 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2437 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2438 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2439 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2440 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2441 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2442 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2443 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2444 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2445 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2446 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2447 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2448 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2449 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2450 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2451 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2452 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2453 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2454 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2455 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2456 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2457
mbed_official 632:7687fb9c4f91 2458 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 632:7687fb9c4f91 2459 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2460 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2461 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2462 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2463 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2464 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2465 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2466 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2467 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2468 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2469 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2470 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2471 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2472 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2473 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2474 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2475 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2476 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2477 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2478 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2479 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2480 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2481 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2482 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2483 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2484 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2485 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2486 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2487 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2488 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2489 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2490 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2491
mbed_official 632:7687fb9c4f91 2492 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 632:7687fb9c4f91 2493 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2494 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2495 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2496 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2497 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2498 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2499 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2500 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2501 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2502 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2503 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2504 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2505 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2506 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2507 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2508 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2509 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2510 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2511 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2512 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2513 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2514 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2515 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2516 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2517 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2518 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2519 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2520 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2521 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2522 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2523 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2524 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2525
mbed_official 632:7687fb9c4f91 2526 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 632:7687fb9c4f91 2527 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2528 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2529 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2530 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2531 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2532 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2533 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2534 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2535 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2536 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2537 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2538 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2539 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2540 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2541 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2542 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2543 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2544 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2545 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2546 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2547 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2548 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2549 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2550 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2551 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2552 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2553 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2554 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2555 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2556 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2557 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2558 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2559
mbed_official 632:7687fb9c4f91 2560 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 632:7687fb9c4f91 2561 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2562 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2563 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2564 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2565 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2566 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2567 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2568 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2569 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2570 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2571 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2572 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2573 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2574 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2575 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2576 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2577 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2578 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2579 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2580 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2581 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2582 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2583 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2584 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2585 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2586 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2587 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2588 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2589 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2590 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2591 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2592 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2593
mbed_official 632:7687fb9c4f91 2594 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 632:7687fb9c4f91 2595 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2596 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2597 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2598 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2599 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2600 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2601 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2602 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2603 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2604 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2605 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2606 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2607 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2608 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2609 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2610 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2611 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2612 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2613 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2614 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2615 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2616 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2617 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2618 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2619 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2620 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2621 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2622 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2623 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2624 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2625 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2626 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2627
mbed_official 632:7687fb9c4f91 2628 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 632:7687fb9c4f91 2629 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2630 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2631 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2632 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2633 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2634 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2635 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2636 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2637 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2638 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2639 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2640 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2641 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2642 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2643 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2644 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2645 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2646 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2647 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2648 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2649 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2650 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2651 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2652 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2653 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2654 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2655 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2656 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2657 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2658 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2659 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2660 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2661
mbed_official 632:7687fb9c4f91 2662 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 632:7687fb9c4f91 2663 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2664 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2665 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2666 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2667 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2668 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2669 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2670 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2671 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2672 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2673 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2674 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2675 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2676 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2677 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2678 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2679 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2680 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2681 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2682 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2683 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2684 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2685 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2686 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2687 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2688 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2689 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2690 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2691 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2692 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2693 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2694 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2695
mbed_official 632:7687fb9c4f91 2696 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 632:7687fb9c4f91 2697 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2698 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2699 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2700 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2701 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2702 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2703 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2704 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2705 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2706 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2707 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2708 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2709 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2710 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2711 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2712 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2713 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2714 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2715 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2716 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2717 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2718 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2719 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2720 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2721 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2722 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2723 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2724 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2725 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2726 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2727 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2728 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2729
mbed_official 632:7687fb9c4f91 2730 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 632:7687fb9c4f91 2731 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2732 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2733 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2734 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2735 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2736 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2737 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2738 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2739 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2740 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2741 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2742 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2743 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2744 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2745 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2746 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2747 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2748 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2749 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2750 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2751 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2752 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2753 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2754 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2755 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2756 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2757 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2758 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2759 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2760 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2761 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2762 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2763
mbed_official 632:7687fb9c4f91 2764 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 632:7687fb9c4f91 2765 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2766 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2767 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2768 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2769 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2770 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2771 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2772 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2773 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2774 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2775 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2776 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2777 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2778 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2779 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2780 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2781 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2782 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2783 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2784 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2785 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2786 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2787 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2788 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2789 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2790 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2791 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2792 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2793 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2794 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2795 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2796 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2797
mbed_official 632:7687fb9c4f91 2798 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 632:7687fb9c4f91 2799 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2800 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2801 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2802 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2803 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2804 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2805 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2806 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2807 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2808 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2809 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2810 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2811 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2812 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2813 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2814 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2815 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2816 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2817 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2818 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2819 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2820 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2821 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2822 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2823 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2824 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2825 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2826 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2827 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2828 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2829 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2830 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2831
mbed_official 632:7687fb9c4f91 2832 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 632:7687fb9c4f91 2833 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2834 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2835 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2836 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2837 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2838 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2839 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2840 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2841 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2842 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2843 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2844 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2845 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2846 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2847 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2848 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2849 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2850 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2851 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2852 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2853 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2854 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2855 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2856 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2857 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2858 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2859 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2860 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2861 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2862 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2863 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2864 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2865
mbed_official 632:7687fb9c4f91 2866 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 632:7687fb9c4f91 2867 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2868 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2869 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2870 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2871 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2872 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2873 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2874 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2875 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2876 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2877 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2878 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2879 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2880 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2881 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2882 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2883 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2884 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2885 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2886 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2887 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2888 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2889 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2890 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2891 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2892 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2893 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2894 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2895 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2896 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2897 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2898 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2899
mbed_official 632:7687fb9c4f91 2900 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 632:7687fb9c4f91 2901 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2902 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2903 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2904 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2905 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2906 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2907 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2908 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2909 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2910 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2911 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2912 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2913 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2914 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2915 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2916 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2917 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2918 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2919 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2920 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2921 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2922 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2923 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2924 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2925 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2926 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2927 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2928 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2929 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2930 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2931 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2932 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2933
mbed_official 632:7687fb9c4f91 2934 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 632:7687fb9c4f91 2935 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2936 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2937 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2938 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2939 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2940 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2941 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2942 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2943 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2944 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2945 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2946 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2947 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2948 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2949 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2950 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2951 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2952 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2953 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2954 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2955 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2956 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2957 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2958 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2959 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2960 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2961 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2962 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2963 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2964 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2965 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 2966 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 2967
mbed_official 632:7687fb9c4f91 2968 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 632:7687fb9c4f91 2969 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 632:7687fb9c4f91 2970 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 632:7687fb9c4f91 2971 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 632:7687fb9c4f91 2972 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 632:7687fb9c4f91 2973 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 632:7687fb9c4f91 2974 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 632:7687fb9c4f91 2975 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 632:7687fb9c4f91 2976 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 632:7687fb9c4f91 2977 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 632:7687fb9c4f91 2978 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 632:7687fb9c4f91 2979 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 632:7687fb9c4f91 2980 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 632:7687fb9c4f91 2981 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 632:7687fb9c4f91 2982 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 632:7687fb9c4f91 2983 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 632:7687fb9c4f91 2984 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 632:7687fb9c4f91 2985 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 632:7687fb9c4f91 2986 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 632:7687fb9c4f91 2987 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 632:7687fb9c4f91 2988 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 632:7687fb9c4f91 2989 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 632:7687fb9c4f91 2990 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 632:7687fb9c4f91 2991 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 632:7687fb9c4f91 2992 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 632:7687fb9c4f91 2993 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 632:7687fb9c4f91 2994 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 632:7687fb9c4f91 2995 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 632:7687fb9c4f91 2996 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 632:7687fb9c4f91 2997 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 632:7687fb9c4f91 2998 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 632:7687fb9c4f91 2999 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 632:7687fb9c4f91 3000 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 632:7687fb9c4f91 3001
mbed_official 632:7687fb9c4f91 3002 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3003 /* */
mbed_official 632:7687fb9c4f91 3004 /* CRC calculation unit (CRC) */
mbed_official 632:7687fb9c4f91 3005 /* */
mbed_official 632:7687fb9c4f91 3006 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3007 /******************* Bit definition for CRC_DR register *********************/
mbed_official 632:7687fb9c4f91 3008 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 632:7687fb9c4f91 3009
mbed_official 632:7687fb9c4f91 3010 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 632:7687fb9c4f91 3011 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 632:7687fb9c4f91 3012
mbed_official 632:7687fb9c4f91 3013 /******************** Bit definition for CRC_CR register ********************/
mbed_official 632:7687fb9c4f91 3014 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 632:7687fb9c4f91 3015 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 632:7687fb9c4f91 3016 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 632:7687fb9c4f91 3017 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 632:7687fb9c4f91 3018 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 632:7687fb9c4f91 3019 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3020 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3021 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 632:7687fb9c4f91 3022
mbed_official 632:7687fb9c4f91 3023 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 632:7687fb9c4f91 3024 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 632:7687fb9c4f91 3025
mbed_official 632:7687fb9c4f91 3026 /******************* Bit definition for CRC_POL register ********************/
mbed_official 632:7687fb9c4f91 3027 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 632:7687fb9c4f91 3028
mbed_official 632:7687fb9c4f91 3029 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3030 /* */
mbed_official 632:7687fb9c4f91 3031 /* Digital to Analog Converter (DAC) */
mbed_official 632:7687fb9c4f91 3032 /* */
mbed_official 632:7687fb9c4f91 3033 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3034 /******************** Bit definition for DAC_CR register ********************/
mbed_official 632:7687fb9c4f91 3035 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 632:7687fb9c4f91 3036 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 632:7687fb9c4f91 3037 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 632:7687fb9c4f91 3038
mbed_official 632:7687fb9c4f91 3039 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 632:7687fb9c4f91 3040 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3041 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3042 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3043
mbed_official 632:7687fb9c4f91 3044 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 632:7687fb9c4f91 3045 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3046 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3047
mbed_official 632:7687fb9c4f91 3048 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 632:7687fb9c4f91 3049 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3050 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3051 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3052 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 3053
mbed_official 632:7687fb9c4f91 3054 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 632:7687fb9c4f91 3055 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
mbed_official 632:7687fb9c4f91 3056 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 632:7687fb9c4f91 3057 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 632:7687fb9c4f91 3058 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 632:7687fb9c4f91 3059
mbed_official 632:7687fb9c4f91 3060 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 632:7687fb9c4f91 3061 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3062 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3063 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3064
mbed_official 632:7687fb9c4f91 3065 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 632:7687fb9c4f91 3066 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3067 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3068
mbed_official 632:7687fb9c4f91 3069 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 632:7687fb9c4f91 3070 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3071 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3072 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3073 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 3074
mbed_official 632:7687fb9c4f91 3075 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 632:7687fb9c4f91 3076 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
mbed_official 632:7687fb9c4f91 3077
mbed_official 632:7687fb9c4f91 3078 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 632:7687fb9c4f91 3079 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 632:7687fb9c4f91 3080 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 632:7687fb9c4f91 3081
mbed_official 632:7687fb9c4f91 3082 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 632:7687fb9c4f91 3083 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3084
mbed_official 632:7687fb9c4f91 3085 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 632:7687fb9c4f91 3086 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 632:7687fb9c4f91 3087
mbed_official 632:7687fb9c4f91 3088 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 632:7687fb9c4f91 3089 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3090
mbed_official 632:7687fb9c4f91 3091 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 632:7687fb9c4f91 3092 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3093
mbed_official 632:7687fb9c4f91 3094 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 632:7687fb9c4f91 3095 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 632:7687fb9c4f91 3096
mbed_official 632:7687fb9c4f91 3097 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 632:7687fb9c4f91 3098 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3099
mbed_official 632:7687fb9c4f91 3100 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 632:7687fb9c4f91 3101 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3102 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3103
mbed_official 632:7687fb9c4f91 3104 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 632:7687fb9c4f91 3105 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 632:7687fb9c4f91 3106 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 632:7687fb9c4f91 3107
mbed_official 632:7687fb9c4f91 3108 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 632:7687fb9c4f91 3109 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3110 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 632:7687fb9c4f91 3111
mbed_official 632:7687fb9c4f91 3112 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 632:7687fb9c4f91 3113 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 632:7687fb9c4f91 3114
mbed_official 632:7687fb9c4f91 3115 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 632:7687fb9c4f91 3116 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 632:7687fb9c4f91 3117
mbed_official 632:7687fb9c4f91 3118 /******************** Bit definition for DAC_SR register ********************/
mbed_official 632:7687fb9c4f91 3119 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 632:7687fb9c4f91 3120 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 632:7687fb9c4f91 3121
mbed_official 632:7687fb9c4f91 3122 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3123 /* */
mbed_official 632:7687fb9c4f91 3124 /* Debug MCU (DBGMCU) */
mbed_official 632:7687fb9c4f91 3125 /* */
mbed_official 632:7687fb9c4f91 3126 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3127 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 632:7687fb9c4f91 3128 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 632:7687fb9c4f91 3129 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 632:7687fb9c4f91 3130
mbed_official 632:7687fb9c4f91 3131 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 632:7687fb9c4f91 3132 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3133 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3134 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3135 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3136
mbed_official 632:7687fb9c4f91 3137 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 632:7687fb9c4f91 3138 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 632:7687fb9c4f91 3139 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 632:7687fb9c4f91 3140
mbed_official 632:7687fb9c4f91 3141 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 632:7687fb9c4f91 3142 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3143 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3144 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3145 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3146 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3147 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3148 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3149 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 3150 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 3151
mbed_official 632:7687fb9c4f91 3152 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 632:7687fb9c4f91 3153 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3154 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3155 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3156 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3157
mbed_official 632:7687fb9c4f91 3158 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3159 /* */
mbed_official 632:7687fb9c4f91 3160 /* DMA Controller (DMA) */
mbed_official 632:7687fb9c4f91 3161 /* */
mbed_official 632:7687fb9c4f91 3162 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3163 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 632:7687fb9c4f91 3164 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3165 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3166 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3167 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3168 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3169 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3170 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3171 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3172 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3173 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3174 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3175 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3176 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3177 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3178 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3179 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3180 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3181 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3182 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3183 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3184 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3185 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3186 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3187 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3188 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 632:7687fb9c4f91 3189 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 632:7687fb9c4f91 3190 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 632:7687fb9c4f91 3191 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 632:7687fb9c4f91 3192
mbed_official 632:7687fb9c4f91 3193 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 632:7687fb9c4f91 3194 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3195 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3196 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3197 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3198 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3199 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3200 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3201 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3202 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3203 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3204 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3205 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3206 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3207 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3208 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3209 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3210 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3211 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3212 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3213 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3214 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3215 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3216 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3217 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3218 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 632:7687fb9c4f91 3219 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 632:7687fb9c4f91 3220 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 632:7687fb9c4f91 3221 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 632:7687fb9c4f91 3222
mbed_official 632:7687fb9c4f91 3223 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 632:7687fb9c4f91 3224 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 632:7687fb9c4f91 3225 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 632:7687fb9c4f91 3226 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 632:7687fb9c4f91 3227 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 632:7687fb9c4f91 3228 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 632:7687fb9c4f91 3229 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 632:7687fb9c4f91 3230 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 632:7687fb9c4f91 3231 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 632:7687fb9c4f91 3232
mbed_official 632:7687fb9c4f91 3233 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 632:7687fb9c4f91 3234 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3235 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3236
mbed_official 632:7687fb9c4f91 3237 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 632:7687fb9c4f91 3238 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3239 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3240
mbed_official 632:7687fb9c4f91 3241 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 632:7687fb9c4f91 3242 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3243 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3244
mbed_official 632:7687fb9c4f91 3245 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 632:7687fb9c4f91 3246
mbed_official 632:7687fb9c4f91 3247 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 632:7687fb9c4f91 3248 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 632:7687fb9c4f91 3249
mbed_official 632:7687fb9c4f91 3250 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 632:7687fb9c4f91 3251 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 632:7687fb9c4f91 3252
mbed_official 632:7687fb9c4f91 3253 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 632:7687fb9c4f91 3254 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 632:7687fb9c4f91 3255
mbed_official 632:7687fb9c4f91 3256 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3257 /* */
mbed_official 632:7687fb9c4f91 3258 /* External Interrupt/Event Controller (EXTI) */
mbed_official 632:7687fb9c4f91 3259 /* */
mbed_official 632:7687fb9c4f91 3260 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3261 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
mbed_official 632:7687fb9c4f91 3262 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 632:7687fb9c4f91 3263 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 632:7687fb9c4f91 3264 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 632:7687fb9c4f91 3265 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 632:7687fb9c4f91 3266 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 632:7687fb9c4f91 3267 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 632:7687fb9c4f91 3268 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 632:7687fb9c4f91 3269 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 632:7687fb9c4f91 3270 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 632:7687fb9c4f91 3271 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 632:7687fb9c4f91 3272 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 632:7687fb9c4f91 3273 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 632:7687fb9c4f91 3274 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 632:7687fb9c4f91 3275 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 632:7687fb9c4f91 3276 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 632:7687fb9c4f91 3277 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 632:7687fb9c4f91 3278 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 632:7687fb9c4f91 3279 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 632:7687fb9c4f91 3280 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 632:7687fb9c4f91 3281 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 632:7687fb9c4f91 3282 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 632:7687fb9c4f91 3283 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 632:7687fb9c4f91 3284 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 632:7687fb9c4f91 3285 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 632:7687fb9c4f91 3286 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
mbed_official 632:7687fb9c4f91 3287 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 632:7687fb9c4f91 3288 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 632:7687fb9c4f91 3289 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 632:7687fb9c4f91 3290 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 632:7687fb9c4f91 3291
mbed_official 632:7687fb9c4f91 3292 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
mbed_official 632:7687fb9c4f91 3293 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 632:7687fb9c4f91 3294 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 632:7687fb9c4f91 3295 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 632:7687fb9c4f91 3296 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 632:7687fb9c4f91 3297 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 632:7687fb9c4f91 3298 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 632:7687fb9c4f91 3299 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 632:7687fb9c4f91 3300 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 632:7687fb9c4f91 3301 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 632:7687fb9c4f91 3302 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 632:7687fb9c4f91 3303 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 632:7687fb9c4f91 3304 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 632:7687fb9c4f91 3305 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 632:7687fb9c4f91 3306 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 632:7687fb9c4f91 3307 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 632:7687fb9c4f91 3308 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 632:7687fb9c4f91 3309 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 632:7687fb9c4f91 3310 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 632:7687fb9c4f91 3311 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 632:7687fb9c4f91 3312 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 632:7687fb9c4f91 3313 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 632:7687fb9c4f91 3314 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 632:7687fb9c4f91 3315 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 632:7687fb9c4f91 3316 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 632:7687fb9c4f91 3317 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
mbed_official 632:7687fb9c4f91 3318 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 632:7687fb9c4f91 3319 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 632:7687fb9c4f91 3320 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 632:7687fb9c4f91 3321 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 632:7687fb9c4f91 3322
mbed_official 632:7687fb9c4f91 3323 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
mbed_official 632:7687fb9c4f91 3324 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 632:7687fb9c4f91 3325 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 632:7687fb9c4f91 3326 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 632:7687fb9c4f91 3327 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 632:7687fb9c4f91 3328 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 632:7687fb9c4f91 3329 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 632:7687fb9c4f91 3330 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 632:7687fb9c4f91 3331 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 632:7687fb9c4f91 3332 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 632:7687fb9c4f91 3333 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 632:7687fb9c4f91 3334 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 632:7687fb9c4f91 3335 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 632:7687fb9c4f91 3336 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 632:7687fb9c4f91 3337 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 632:7687fb9c4f91 3338 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 632:7687fb9c4f91 3339 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 632:7687fb9c4f91 3340 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 632:7687fb9c4f91 3341 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 632:7687fb9c4f91 3342 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 632:7687fb9c4f91 3343 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 632:7687fb9c4f91 3344 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 632:7687fb9c4f91 3345 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 632:7687fb9c4f91 3346 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 632:7687fb9c4f91 3347 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 632:7687fb9c4f91 3348 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
mbed_official 632:7687fb9c4f91 3349 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
mbed_official 632:7687fb9c4f91 3350 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
mbed_official 632:7687fb9c4f91 3351 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
mbed_official 632:7687fb9c4f91 3352 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
mbed_official 632:7687fb9c4f91 3353
mbed_official 632:7687fb9c4f91 3354 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
mbed_official 632:7687fb9c4f91 3355 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 632:7687fb9c4f91 3356 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 632:7687fb9c4f91 3357 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 632:7687fb9c4f91 3358 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 632:7687fb9c4f91 3359 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 632:7687fb9c4f91 3360 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 632:7687fb9c4f91 3361 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 632:7687fb9c4f91 3362 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 632:7687fb9c4f91 3363 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 632:7687fb9c4f91 3364 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 632:7687fb9c4f91 3365 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 632:7687fb9c4f91 3366 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 632:7687fb9c4f91 3367 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 632:7687fb9c4f91 3368 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 632:7687fb9c4f91 3369 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 632:7687fb9c4f91 3370 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 632:7687fb9c4f91 3371 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 632:7687fb9c4f91 3372 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 632:7687fb9c4f91 3373 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 632:7687fb9c4f91 3374 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 632:7687fb9c4f91 3375 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 632:7687fb9c4f91 3376 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 632:7687fb9c4f91 3377 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 632:7687fb9c4f91 3378 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 632:7687fb9c4f91 3379 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
mbed_official 632:7687fb9c4f91 3380 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
mbed_official 632:7687fb9c4f91 3381 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
mbed_official 632:7687fb9c4f91 3382 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
mbed_official 632:7687fb9c4f91 3383 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
mbed_official 632:7687fb9c4f91 3384
mbed_official 632:7687fb9c4f91 3385 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
mbed_official 632:7687fb9c4f91 3386 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 632:7687fb9c4f91 3387 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 632:7687fb9c4f91 3388 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 632:7687fb9c4f91 3389 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 632:7687fb9c4f91 3390 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 632:7687fb9c4f91 3391 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 632:7687fb9c4f91 3392 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 632:7687fb9c4f91 3393 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 632:7687fb9c4f91 3394 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 632:7687fb9c4f91 3395 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 632:7687fb9c4f91 3396 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 632:7687fb9c4f91 3397 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 632:7687fb9c4f91 3398 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 632:7687fb9c4f91 3399 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 632:7687fb9c4f91 3400 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 632:7687fb9c4f91 3401 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 632:7687fb9c4f91 3402 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 632:7687fb9c4f91 3403 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 632:7687fb9c4f91 3404 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 632:7687fb9c4f91 3405 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 632:7687fb9c4f91 3406 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 632:7687fb9c4f91 3407 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 632:7687fb9c4f91 3408 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 632:7687fb9c4f91 3409 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 632:7687fb9c4f91 3410 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
mbed_official 632:7687fb9c4f91 3411 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
mbed_official 632:7687fb9c4f91 3412 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
mbed_official 632:7687fb9c4f91 3413 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
mbed_official 632:7687fb9c4f91 3414 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
mbed_official 632:7687fb9c4f91 3415
mbed_official 632:7687fb9c4f91 3416 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
mbed_official 632:7687fb9c4f91 3417 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 632:7687fb9c4f91 3418 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 632:7687fb9c4f91 3419 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 632:7687fb9c4f91 3420 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 632:7687fb9c4f91 3421 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 632:7687fb9c4f91 3422 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 632:7687fb9c4f91 3423 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 632:7687fb9c4f91 3424 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 632:7687fb9c4f91 3425 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 632:7687fb9c4f91 3426 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 632:7687fb9c4f91 3427 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 632:7687fb9c4f91 3428 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 632:7687fb9c4f91 3429 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 632:7687fb9c4f91 3430 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 632:7687fb9c4f91 3431 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 632:7687fb9c4f91 3432 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 632:7687fb9c4f91 3433 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 632:7687fb9c4f91 3434 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 632:7687fb9c4f91 3435 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 632:7687fb9c4f91 3436 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 632:7687fb9c4f91 3437 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 632:7687fb9c4f91 3438 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 632:7687fb9c4f91 3439 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 632:7687fb9c4f91 3440 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 632:7687fb9c4f91 3441 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
mbed_official 632:7687fb9c4f91 3442 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
mbed_official 632:7687fb9c4f91 3443 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
mbed_official 632:7687fb9c4f91 3444 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
mbed_official 632:7687fb9c4f91 3445 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
mbed_official 632:7687fb9c4f91 3446
mbed_official 632:7687fb9c4f91 3447 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3448 /* */
mbed_official 632:7687fb9c4f91 3449 /* FLASH */
mbed_official 632:7687fb9c4f91 3450 /* */
mbed_official 632:7687fb9c4f91 3451 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3452 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 632:7687fb9c4f91 3453 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
mbed_official 632:7687fb9c4f91 3454 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3455 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3456 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3457
mbed_official 632:7687fb9c4f91 3458 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
mbed_official 632:7687fb9c4f91 3459 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 632:7687fb9c4f91 3460 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 632:7687fb9c4f91 3461
mbed_official 632:7687fb9c4f91 3462 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 632:7687fb9c4f91 3463 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 632:7687fb9c4f91 3464
mbed_official 632:7687fb9c4f91 3465 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
mbed_official 632:7687fb9c4f91 3466 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
mbed_official 632:7687fb9c4f91 3467 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
mbed_official 632:7687fb9c4f91 3468
mbed_official 632:7687fb9c4f91 3469 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 632:7687fb9c4f91 3470 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 632:7687fb9c4f91 3471
mbed_official 632:7687fb9c4f91 3472 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
mbed_official 632:7687fb9c4f91 3473 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
mbed_official 632:7687fb9c4f91 3474
mbed_official 632:7687fb9c4f91 3475 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 632:7687fb9c4f91 3476 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 632:7687fb9c4f91 3477 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 632:7687fb9c4f91 3478 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 632:7687fb9c4f91 3479 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 632:7687fb9c4f91 3480
mbed_official 632:7687fb9c4f91 3481 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 632:7687fb9c4f91 3482 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 632:7687fb9c4f91 3483 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 632:7687fb9c4f91 3484 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 632:7687fb9c4f91 3485 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 632:7687fb9c4f91 3486 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 632:7687fb9c4f91 3487 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 632:7687fb9c4f91 3488 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 632:7687fb9c4f91 3489 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 632:7687fb9c4f91 3490 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 632:7687fb9c4f91 3491 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 632:7687fb9c4f91 3492 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
mbed_official 632:7687fb9c4f91 3493
mbed_official 632:7687fb9c4f91 3494 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 632:7687fb9c4f91 3495 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 632:7687fb9c4f91 3496
mbed_official 632:7687fb9c4f91 3497 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 632:7687fb9c4f91 3498 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 632:7687fb9c4f91 3499 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
mbed_official 632:7687fb9c4f91 3500 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 632:7687fb9c4f91 3501 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
mbed_official 632:7687fb9c4f91 3502
mbed_official 632:7687fb9c4f91 3503 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
mbed_official 632:7687fb9c4f91 3504 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 632:7687fb9c4f91 3505 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 632:7687fb9c4f91 3506 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 632:7687fb9c4f91 3507 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 632:7687fb9c4f91 3508 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
mbed_official 632:7687fb9c4f91 3509 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
mbed_official 632:7687fb9c4f91 3510
mbed_official 632:7687fb9c4f91 3511 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 632:7687fb9c4f91 3512 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 632:7687fb9c4f91 3513
mbed_official 632:7687fb9c4f91 3514 /*----------------------------------------------------------------------------*/
mbed_official 632:7687fb9c4f91 3515
mbed_official 632:7687fb9c4f91 3516 /****************** Bit definition for OB_RDP register **********************/
mbed_official 632:7687fb9c4f91 3517 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 632:7687fb9c4f91 3518 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 632:7687fb9c4f91 3519
mbed_official 632:7687fb9c4f91 3520 /****************** Bit definition for OB_USER register *********************/
mbed_official 632:7687fb9c4f91 3521 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 632:7687fb9c4f91 3522 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 632:7687fb9c4f91 3523
mbed_official 632:7687fb9c4f91 3524 /****************** Bit definition for FLASH_WRP0 register ******************/
mbed_official 632:7687fb9c4f91 3525 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 632:7687fb9c4f91 3526 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 632:7687fb9c4f91 3527
mbed_official 632:7687fb9c4f91 3528 /****************** Bit definition for FLASH_WRP1 register ******************/
mbed_official 632:7687fb9c4f91 3529 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 632:7687fb9c4f91 3530 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 632:7687fb9c4f91 3531
mbed_official 632:7687fb9c4f91 3532 /****************** Bit definition for FLASH_WRP2 register ******************/
mbed_official 632:7687fb9c4f91 3533 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 632:7687fb9c4f91 3534 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 632:7687fb9c4f91 3535
mbed_official 632:7687fb9c4f91 3536 /****************** Bit definition for FLASH_WRP3 register ******************/
mbed_official 632:7687fb9c4f91 3537 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 632:7687fb9c4f91 3538 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 632:7687fb9c4f91 3539 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3540 /* */
mbed_official 632:7687fb9c4f91 3541 /* General Purpose I/O (GPIO) */
mbed_official 632:7687fb9c4f91 3542 /* */
mbed_official 632:7687fb9c4f91 3543 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3544 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 632:7687fb9c4f91 3545 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 632:7687fb9c4f91 3546 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3547 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3548 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 632:7687fb9c4f91 3549 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3550 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3551 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 632:7687fb9c4f91 3552 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3553 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3554 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 632:7687fb9c4f91 3555 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3556 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3557 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 632:7687fb9c4f91 3558 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3559 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3560 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 632:7687fb9c4f91 3561 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3562 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3563 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 632:7687fb9c4f91 3564 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3565 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3566 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 632:7687fb9c4f91 3567 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3568 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3569 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 632:7687fb9c4f91 3570 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 3571 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 3572 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 632:7687fb9c4f91 3573 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 3574 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 3575 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 3576 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 3577 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 3578 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 632:7687fb9c4f91 3579 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 3580 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 3581 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 632:7687fb9c4f91 3582 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 3583 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 3584 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 632:7687fb9c4f91 3585 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 3586 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 3587 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 632:7687fb9c4f91 3588 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 3589 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 3590 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 632:7687fb9c4f91 3591 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 3592 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 3593
mbed_official 632:7687fb9c4f91 3594 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 632:7687fb9c4f91 3595 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3596 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3597 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3598 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3599 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3600 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3601 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3602 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3603 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3604 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3605 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3606 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3607 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3608 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3609 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3610 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3611
mbed_official 632:7687fb9c4f91 3612 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 632:7687fb9c4f91 3613 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 632:7687fb9c4f91 3614 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3615 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3616 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 632:7687fb9c4f91 3617 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3618 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3619 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 632:7687fb9c4f91 3620 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3621 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3622 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 632:7687fb9c4f91 3623 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3624 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3625 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 632:7687fb9c4f91 3626 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3627 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3628 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 632:7687fb9c4f91 3629 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3630 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3631 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 632:7687fb9c4f91 3632 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3633 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3634 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 632:7687fb9c4f91 3635 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3636 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3637 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 632:7687fb9c4f91 3638 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 3639 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 3640 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 632:7687fb9c4f91 3641 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 3642 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 3643 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 3644 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 3645 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 3646 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 632:7687fb9c4f91 3647 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 3648 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 3649 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 632:7687fb9c4f91 3650 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 3651 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 3652 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 632:7687fb9c4f91 3653 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 3654 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 3655 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 632:7687fb9c4f91 3656 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 3657 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 3658 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 632:7687fb9c4f91 3659 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 3660 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 3661
mbed_official 632:7687fb9c4f91 3662 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 632:7687fb9c4f91 3663 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 632:7687fb9c4f91 3664 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3665 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3666 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 632:7687fb9c4f91 3667 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3668 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3669 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 632:7687fb9c4f91 3670 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3671 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3672 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 632:7687fb9c4f91 3673 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3674 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3675 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 632:7687fb9c4f91 3676 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3677 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3678 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 632:7687fb9c4f91 3679 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3680 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3681 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 632:7687fb9c4f91 3682 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3683 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3684 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 632:7687fb9c4f91 3685 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3686 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3687 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 632:7687fb9c4f91 3688 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 3689 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 3690 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 632:7687fb9c4f91 3691 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 3692 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 3693 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 3694 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 3695 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 3696 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 632:7687fb9c4f91 3697 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 3698 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 3699 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 632:7687fb9c4f91 3700 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 3701 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 3702 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 632:7687fb9c4f91 3703 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 3704 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 3705 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 632:7687fb9c4f91 3706 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 3707 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 3708 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 632:7687fb9c4f91 3709 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 3710 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 3711
mbed_official 632:7687fb9c4f91 3712 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 632:7687fb9c4f91 3713 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3714 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3715 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3716 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3717 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3718 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3719 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3720 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3721 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3722 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3723 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3724 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3725 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3726 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3727 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3728 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3729
mbed_official 632:7687fb9c4f91 3730 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 632:7687fb9c4f91 3731 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3732 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3733 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3734 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3735 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3736 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3737 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3738 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3739 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3740 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3741 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3742 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3743 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3744 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3745 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3746 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3747
mbed_official 632:7687fb9c4f91 3748 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 632:7687fb9c4f91 3749 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3750 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3751 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3752 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3753 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3754 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3755 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3756 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3757 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3758 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3759 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3760 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3761 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3762 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3763 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3764 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3765 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 3766 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 3767 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 3768 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 3769 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 3770 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 3771 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 3772 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 3773 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 3774 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 3775 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 3776 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 3777 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 3778 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 3779 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 3780 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 3781
mbed_official 632:7687fb9c4f91 3782 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 632:7687fb9c4f91 3783 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3784 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3785 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3786 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3787 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3788 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3789 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3790 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3791 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3792 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3793 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3794 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3795 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3796 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3797 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3798 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3799 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 3800
mbed_official 632:7687fb9c4f91 3801 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 632:7687fb9c4f91 3802 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 3803 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 632:7687fb9c4f91 3804 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 3805 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 632:7687fb9c4f91 3806 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 3807 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 632:7687fb9c4f91 3808 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 3809 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 632:7687fb9c4f91 3810
mbed_official 632:7687fb9c4f91 3811 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 632:7687fb9c4f91 3812 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 3813 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 632:7687fb9c4f91 3814 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 3815 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 632:7687fb9c4f91 3816 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 3817 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 632:7687fb9c4f91 3818 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 3819 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 632:7687fb9c4f91 3820
mbed_official 632:7687fb9c4f91 3821 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 632:7687fb9c4f91 3822 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 3823 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 3824 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 3825 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 3826 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 3827 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 3828 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 3829 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 3830 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 3831 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 3832 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 3833 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 3834 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 3835 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 3836 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 3837 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 3838
mbed_official 632:7687fb9c4f91 3839 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3840 /* */
mbed_official 632:7687fb9c4f91 3841 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 632:7687fb9c4f91 3842 /* */
mbed_official 632:7687fb9c4f91 3843 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3844 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 632:7687fb9c4f91 3845 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 632:7687fb9c4f91 3846 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 632:7687fb9c4f91 3847 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 632:7687fb9c4f91 3848 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 632:7687fb9c4f91 3849 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 632:7687fb9c4f91 3850 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 632:7687fb9c4f91 3851 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 632:7687fb9c4f91 3852 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 632:7687fb9c4f91 3853 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 632:7687fb9c4f91 3854 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 632:7687fb9c4f91 3855 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 632:7687fb9c4f91 3856 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 632:7687fb9c4f91 3857 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 632:7687fb9c4f91 3858 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 632:7687fb9c4f91 3859 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 632:7687fb9c4f91 3860 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 632:7687fb9c4f91 3861 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 632:7687fb9c4f91 3862 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 632:7687fb9c4f91 3863 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 632:7687fb9c4f91 3864 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 632:7687fb9c4f91 3865 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 632:7687fb9c4f91 3866
mbed_official 632:7687fb9c4f91 3867 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 632:7687fb9c4f91 3868 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 632:7687fb9c4f91 3869 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 632:7687fb9c4f91 3870 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 632:7687fb9c4f91 3871 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 632:7687fb9c4f91 3872 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 632:7687fb9c4f91 3873 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 632:7687fb9c4f91 3874 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 632:7687fb9c4f91 3875 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 632:7687fb9c4f91 3876 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 632:7687fb9c4f91 3877 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 632:7687fb9c4f91 3878 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 632:7687fb9c4f91 3879
mbed_official 632:7687fb9c4f91 3880 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 632:7687fb9c4f91 3881 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 632:7687fb9c4f91 3882 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 632:7687fb9c4f91 3883 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 632:7687fb9c4f91 3884
mbed_official 632:7687fb9c4f91 3885 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 632:7687fb9c4f91 3886 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 632:7687fb9c4f91 3887 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 632:7687fb9c4f91 3888 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 632:7687fb9c4f91 3889
mbed_official 632:7687fb9c4f91 3890 /******************* Bit definition for I2C_TIMINGR register *****************/
mbed_official 632:7687fb9c4f91 3891 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 632:7687fb9c4f91 3892 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 632:7687fb9c4f91 3893 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 632:7687fb9c4f91 3894 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 632:7687fb9c4f91 3895 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 632:7687fb9c4f91 3896
mbed_official 632:7687fb9c4f91 3897 /******************* Bit definition for I2C_TIMEOUTR register *****************/
mbed_official 632:7687fb9c4f91 3898 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 632:7687fb9c4f91 3899 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 632:7687fb9c4f91 3900 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 632:7687fb9c4f91 3901 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 632:7687fb9c4f91 3902 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 632:7687fb9c4f91 3903
mbed_official 632:7687fb9c4f91 3904 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 632:7687fb9c4f91 3905 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 632:7687fb9c4f91 3906 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 632:7687fb9c4f91 3907 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 632:7687fb9c4f91 3908 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 632:7687fb9c4f91 3909 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 632:7687fb9c4f91 3910 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 632:7687fb9c4f91 3911 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 632:7687fb9c4f91 3912 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 632:7687fb9c4f91 3913 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 632:7687fb9c4f91 3914 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 632:7687fb9c4f91 3915 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 632:7687fb9c4f91 3916 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 632:7687fb9c4f91 3917 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 632:7687fb9c4f91 3918 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 632:7687fb9c4f91 3919 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 632:7687fb9c4f91 3920 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 632:7687fb9c4f91 3921 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 632:7687fb9c4f91 3922
mbed_official 632:7687fb9c4f91 3923 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 632:7687fb9c4f91 3924 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 632:7687fb9c4f91 3925 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 632:7687fb9c4f91 3926 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 632:7687fb9c4f91 3927 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 632:7687fb9c4f91 3928 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 632:7687fb9c4f91 3929 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 632:7687fb9c4f91 3930 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 632:7687fb9c4f91 3931 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 632:7687fb9c4f91 3932 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 632:7687fb9c4f91 3933
mbed_official 632:7687fb9c4f91 3934 /****************** Bit definition for I2C_PECR register ********************/
mbed_official 632:7687fb9c4f91 3935 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 632:7687fb9c4f91 3936
mbed_official 632:7687fb9c4f91 3937 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 632:7687fb9c4f91 3938 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 632:7687fb9c4f91 3939
mbed_official 632:7687fb9c4f91 3940 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 632:7687fb9c4f91 3941 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 632:7687fb9c4f91 3942
mbed_official 632:7687fb9c4f91 3943
mbed_official 632:7687fb9c4f91 3944 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3945 /* */
mbed_official 632:7687fb9c4f91 3946 /* Independent WATCHDOG (IWDG) */
mbed_official 632:7687fb9c4f91 3947 /* */
mbed_official 632:7687fb9c4f91 3948 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3949 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 632:7687fb9c4f91 3950 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 632:7687fb9c4f91 3951
mbed_official 632:7687fb9c4f91 3952 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 632:7687fb9c4f91 3953 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 632:7687fb9c4f91 3954 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3955 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3956 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3957
mbed_official 632:7687fb9c4f91 3958 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 632:7687fb9c4f91 3959 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 632:7687fb9c4f91 3960
mbed_official 632:7687fb9c4f91 3961 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 632:7687fb9c4f91 3962 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 632:7687fb9c4f91 3963 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 632:7687fb9c4f91 3964 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
mbed_official 632:7687fb9c4f91 3965
mbed_official 632:7687fb9c4f91 3966 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 632:7687fb9c4f91 3967 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
mbed_official 632:7687fb9c4f91 3968
mbed_official 632:7687fb9c4f91 3969 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3970 /* */
mbed_official 632:7687fb9c4f91 3971 /* Power Control */
mbed_official 632:7687fb9c4f91 3972 /* */
mbed_official 632:7687fb9c4f91 3973 /******************************************************************************/
mbed_official 632:7687fb9c4f91 3974 /******************** Bit definition for PWR_CR register ********************/
mbed_official 632:7687fb9c4f91 3975 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 632:7687fb9c4f91 3976 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 632:7687fb9c4f91 3977 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 632:7687fb9c4f91 3978 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 632:7687fb9c4f91 3979 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 632:7687fb9c4f91 3980
mbed_official 632:7687fb9c4f91 3981 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 632:7687fb9c4f91 3982 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 3983 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 3984 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 3985
mbed_official 632:7687fb9c4f91 3986 /*!< PVD level configuration */
mbed_official 632:7687fb9c4f91 3987 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 632:7687fb9c4f91 3988 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 632:7687fb9c4f91 3989 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 632:7687fb9c4f91 3990 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 632:7687fb9c4f91 3991 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 632:7687fb9c4f91 3992 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 632:7687fb9c4f91 3993 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 632:7687fb9c4f91 3994 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 632:7687fb9c4f91 3995
mbed_official 632:7687fb9c4f91 3996 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 632:7687fb9c4f91 3997
mbed_official 632:7687fb9c4f91 3998 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 632:7687fb9c4f91 3999 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 632:7687fb9c4f91 4000 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 632:7687fb9c4f91 4001 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 632:7687fb9c4f91 4002
mbed_official 632:7687fb9c4f91 4003 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 632:7687fb9c4f91 4004 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 632:7687fb9c4f91 4005 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 632:7687fb9c4f91 4006
mbed_official 632:7687fb9c4f91 4007 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4008 /* */
mbed_official 632:7687fb9c4f91 4009 /* Reset and Clock Control */
mbed_official 632:7687fb9c4f91 4010 /* */
mbed_official 632:7687fb9c4f91 4011 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4012 /******************** Bit definition for RCC_CR register ********************/
mbed_official 632:7687fb9c4f91 4013 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4014 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4015
mbed_official 632:7687fb9c4f91 4016 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 632:7687fb9c4f91 4017 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 632:7687fb9c4f91 4018 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 632:7687fb9c4f91 4019 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 632:7687fb9c4f91 4020 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 632:7687fb9c4f91 4021 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 632:7687fb9c4f91 4022
mbed_official 632:7687fb9c4f91 4023 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 632:7687fb9c4f91 4024 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 632:7687fb9c4f91 4025 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 632:7687fb9c4f91 4026 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 632:7687fb9c4f91 4027 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 632:7687fb9c4f91 4028 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 632:7687fb9c4f91 4029 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 632:7687fb9c4f91 4030 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 632:7687fb9c4f91 4031 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 632:7687fb9c4f91 4032
mbed_official 632:7687fb9c4f91 4033 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4034 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4035 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4036 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4037 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 4038 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 4039
mbed_official 632:7687fb9c4f91 4040 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 632:7687fb9c4f91 4041 /*!< SW configuration */
mbed_official 632:7687fb9c4f91 4042 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 632:7687fb9c4f91 4043 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4044 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4045
mbed_official 632:7687fb9c4f91 4046 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 632:7687fb9c4f91 4047 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 632:7687fb9c4f91 4048 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 632:7687fb9c4f91 4049
mbed_official 632:7687fb9c4f91 4050 /*!< SWS configuration */
mbed_official 632:7687fb9c4f91 4051 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 632:7687fb9c4f91 4052 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4053 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4054
mbed_official 632:7687fb9c4f91 4055 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 632:7687fb9c4f91 4056 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 632:7687fb9c4f91 4057 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 632:7687fb9c4f91 4058
mbed_official 632:7687fb9c4f91 4059 /*!< HPRE configuration */
mbed_official 632:7687fb9c4f91 4060 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 632:7687fb9c4f91 4061 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4062 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4063 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4064 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 4065
mbed_official 632:7687fb9c4f91 4066 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 632:7687fb9c4f91 4067 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 632:7687fb9c4f91 4068 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 632:7687fb9c4f91 4069 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 632:7687fb9c4f91 4070 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 632:7687fb9c4f91 4071 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 632:7687fb9c4f91 4072 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 632:7687fb9c4f91 4073 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 632:7687fb9c4f91 4074 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 632:7687fb9c4f91 4075
mbed_official 632:7687fb9c4f91 4076 /*!< PPRE1 configuration */
mbed_official 632:7687fb9c4f91 4077 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 632:7687fb9c4f91 4078 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4079 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4080 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4081
mbed_official 632:7687fb9c4f91 4082 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 632:7687fb9c4f91 4083 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 632:7687fb9c4f91 4084 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 632:7687fb9c4f91 4085 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 632:7687fb9c4f91 4086 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 632:7687fb9c4f91 4087
mbed_official 632:7687fb9c4f91 4088 /*!< PPRE2 configuration */
mbed_official 632:7687fb9c4f91 4089 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 632:7687fb9c4f91 4090 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4091 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4092 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4093
mbed_official 632:7687fb9c4f91 4094 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 632:7687fb9c4f91 4095 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 632:7687fb9c4f91 4096 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 632:7687fb9c4f91 4097 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 632:7687fb9c4f91 4098 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 632:7687fb9c4f91 4099
mbed_official 632:7687fb9c4f91 4100 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 632:7687fb9c4f91 4101 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 632:7687fb9c4f91 4102 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 632:7687fb9c4f91 4103
mbed_official 632:7687fb9c4f91 4104 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 632:7687fb9c4f91 4105 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 632:7687fb9c4f91 4106 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 632:7687fb9c4f91 4107
mbed_official 632:7687fb9c4f91 4108 /*!< PLLMUL configuration */
mbed_official 632:7687fb9c4f91 4109 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 632:7687fb9c4f91 4110 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4111 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4112 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4113 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 4114
mbed_official 632:7687fb9c4f91 4115 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 632:7687fb9c4f91 4116 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 632:7687fb9c4f91 4117 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 632:7687fb9c4f91 4118 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 632:7687fb9c4f91 4119 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 632:7687fb9c4f91 4120 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 632:7687fb9c4f91 4121 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 632:7687fb9c4f91 4122 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 632:7687fb9c4f91 4123 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 632:7687fb9c4f91 4124 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 632:7687fb9c4f91 4125 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 632:7687fb9c4f91 4126 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 632:7687fb9c4f91 4127 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 632:7687fb9c4f91 4128 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 632:7687fb9c4f91 4129 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 632:7687fb9c4f91 4130
mbed_official 632:7687fb9c4f91 4131 /*!< MCO configuration */
mbed_official 632:7687fb9c4f91 4132 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 632:7687fb9c4f91 4133 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4134 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4135 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4136
mbed_official 632:7687fb9c4f91 4137 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 632:7687fb9c4f91 4138 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 632:7687fb9c4f91 4139 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 632:7687fb9c4f91 4140 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 632:7687fb9c4f91 4141 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 632:7687fb9c4f91 4142 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 632:7687fb9c4f91 4143 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 632:7687fb9c4f91 4144
mbed_official 632:7687fb9c4f91 4145 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 632:7687fb9c4f91 4146 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 632:7687fb9c4f91 4147 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 632:7687fb9c4f91 4148 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 632:7687fb9c4f91 4149 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 632:7687fb9c4f91 4150 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 632:7687fb9c4f91 4151 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 632:7687fb9c4f91 4152 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 632:7687fb9c4f91 4153 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 632:7687fb9c4f91 4154
mbed_official 632:7687fb9c4f91 4155 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 632:7687fb9c4f91 4156
mbed_official 632:7687fb9c4f91 4157 /********************* Bit definition for RCC_CIR register ********************/
mbed_official 632:7687fb9c4f91 4158 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 632:7687fb9c4f91 4159 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 632:7687fb9c4f91 4160 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 632:7687fb9c4f91 4161 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 632:7687fb9c4f91 4162 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 632:7687fb9c4f91 4163 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 632:7687fb9c4f91 4164 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 632:7687fb9c4f91 4165 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 632:7687fb9c4f91 4166 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 632:7687fb9c4f91 4167 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 632:7687fb9c4f91 4168 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 632:7687fb9c4f91 4169 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 632:7687fb9c4f91 4170 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 632:7687fb9c4f91 4171 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 632:7687fb9c4f91 4172 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 632:7687fb9c4f91 4173 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 632:7687fb9c4f91 4174 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 632:7687fb9c4f91 4175
mbed_official 632:7687fb9c4f91 4176 /****************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 632:7687fb9c4f91 4177 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
mbed_official 632:7687fb9c4f91 4178 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
mbed_official 632:7687fb9c4f91 4179 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 632:7687fb9c4f91 4180 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 632:7687fb9c4f91 4181 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
mbed_official 632:7687fb9c4f91 4182 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
mbed_official 632:7687fb9c4f91 4183 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
mbed_official 632:7687fb9c4f91 4184
mbed_official 632:7687fb9c4f91 4185 /****************** Bit definition for RCC_APB1RSTR register ******************/
mbed_official 632:7687fb9c4f91 4186 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 632:7687fb9c4f91 4187 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 632:7687fb9c4f91 4188 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 632:7687fb9c4f91 4189 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 632:7687fb9c4f91 4190 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 632:7687fb9c4f91 4191 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 632:7687fb9c4f91 4192 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 632:7687fb9c4f91 4193 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 632:7687fb9c4f91 4194 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
mbed_official 632:7687fb9c4f91 4195 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
mbed_official 632:7687fb9c4f91 4196 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
mbed_official 632:7687fb9c4f91 4197 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
mbed_official 632:7687fb9c4f91 4198
mbed_official 632:7687fb9c4f91 4199 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 632:7687fb9c4f91 4200 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 632:7687fb9c4f91 4201 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 632:7687fb9c4f91 4202 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 632:7687fb9c4f91 4203 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 632:7687fb9c4f91 4204 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 632:7687fb9c4f91 4205 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 632:7687fb9c4f91 4206 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 632:7687fb9c4f91 4207 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 632:7687fb9c4f91 4208 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 632:7687fb9c4f91 4209 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
mbed_official 632:7687fb9c4f91 4210 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
mbed_official 632:7687fb9c4f91 4211
mbed_official 632:7687fb9c4f91 4212 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 632:7687fb9c4f91 4213 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
mbed_official 632:7687fb9c4f91 4214 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 632:7687fb9c4f91 4215 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 632:7687fb9c4f91 4216 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 632:7687fb9c4f91 4217 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 632:7687fb9c4f91 4218 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 632:7687fb9c4f91 4219 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 632:7687fb9c4f91 4220
mbed_official 632:7687fb9c4f91 4221 /****************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 632:7687fb9c4f91 4222 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 632:7687fb9c4f91 4223 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 632:7687fb9c4f91 4224 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 632:7687fb9c4f91 4225 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 632:7687fb9c4f91 4226 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 632:7687fb9c4f91 4227 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 632:7687fb9c4f91 4228 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 632:7687fb9c4f91 4229 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 632:7687fb9c4f91 4230 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 632:7687fb9c4f91 4231 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
mbed_official 632:7687fb9c4f91 4232 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 632:7687fb9c4f91 4233 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
mbed_official 632:7687fb9c4f91 4234
mbed_official 632:7687fb9c4f91 4235 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 632:7687fb9c4f91 4236 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
mbed_official 632:7687fb9c4f91 4237 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 632:7687fb9c4f91 4238 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 632:7687fb9c4f91 4239 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 632:7687fb9c4f91 4240
mbed_official 632:7687fb9c4f91 4241 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 632:7687fb9c4f91 4242 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4243 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4244
mbed_official 632:7687fb9c4f91 4245 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 632:7687fb9c4f91 4246 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4247 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4248
mbed_official 632:7687fb9c4f91 4249 /*!< RTC configuration */
mbed_official 632:7687fb9c4f91 4250 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 632:7687fb9c4f91 4251 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 632:7687fb9c4f91 4252 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 632:7687fb9c4f91 4253 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
mbed_official 632:7687fb9c4f91 4254
mbed_official 632:7687fb9c4f91 4255 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 632:7687fb9c4f91 4256 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 632:7687fb9c4f91 4257
mbed_official 632:7687fb9c4f91 4258 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 632:7687fb9c4f91 4259 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 632:7687fb9c4f91 4260 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 632:7687fb9c4f91 4261 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 632:7687fb9c4f91 4262 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 632:7687fb9c4f91 4263 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 632:7687fb9c4f91 4264 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 632:7687fb9c4f91 4265 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 632:7687fb9c4f91 4266 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 632:7687fb9c4f91 4267 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 632:7687fb9c4f91 4268 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 632:7687fb9c4f91 4269
mbed_official 632:7687fb9c4f91 4270 /******************* Bit definition for RCC_AHBRSTR register ****************/
mbed_official 632:7687fb9c4f91 4271 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
mbed_official 632:7687fb9c4f91 4272 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
mbed_official 632:7687fb9c4f91 4273 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
mbed_official 632:7687fb9c4f91 4274 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
mbed_official 632:7687fb9c4f91 4275 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
mbed_official 632:7687fb9c4f91 4276 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
mbed_official 632:7687fb9c4f91 4277 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
mbed_official 632:7687fb9c4f91 4278
mbed_official 632:7687fb9c4f91 4279 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 632:7687fb9c4f91 4280 /*!< PREDIV configuration */
mbed_official 632:7687fb9c4f91 4281 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 632:7687fb9c4f91 4282 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4283 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4284 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4285 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 4286
mbed_official 632:7687fb9c4f91 4287 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 632:7687fb9c4f91 4288 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 632:7687fb9c4f91 4289 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 632:7687fb9c4f91 4290 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 632:7687fb9c4f91 4291 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 632:7687fb9c4f91 4292 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 632:7687fb9c4f91 4293 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 632:7687fb9c4f91 4294 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 632:7687fb9c4f91 4295 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 632:7687fb9c4f91 4296 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 632:7687fb9c4f91 4297 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 632:7687fb9c4f91 4298 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 632:7687fb9c4f91 4299 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 632:7687fb9c4f91 4300 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 632:7687fb9c4f91 4301 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 632:7687fb9c4f91 4302 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 632:7687fb9c4f91 4303
mbed_official 632:7687fb9c4f91 4304 /*!< ADCPRE12 configuration */
mbed_official 632:7687fb9c4f91 4305 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
mbed_official 632:7687fb9c4f91 4306 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4307 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4308 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4309 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 4310 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
mbed_official 632:7687fb9c4f91 4311
mbed_official 632:7687fb9c4f91 4312 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
mbed_official 632:7687fb9c4f91 4313 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
mbed_official 632:7687fb9c4f91 4314 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
mbed_official 632:7687fb9c4f91 4315 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
mbed_official 632:7687fb9c4f91 4316 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
mbed_official 632:7687fb9c4f91 4317 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
mbed_official 632:7687fb9c4f91 4318 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
mbed_official 632:7687fb9c4f91 4319 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
mbed_official 632:7687fb9c4f91 4320 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
mbed_official 632:7687fb9c4f91 4321 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
mbed_official 632:7687fb9c4f91 4322 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
mbed_official 632:7687fb9c4f91 4323 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
mbed_official 632:7687fb9c4f91 4324 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
mbed_official 632:7687fb9c4f91 4325
mbed_official 632:7687fb9c4f91 4326 /******************* Bit definition for RCC_CFGR3 register ******************/
mbed_official 632:7687fb9c4f91 4327 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 632:7687fb9c4f91 4328 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4329 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4330
mbed_official 632:7687fb9c4f91 4331 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
mbed_official 632:7687fb9c4f91 4332 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 632:7687fb9c4f91 4333 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 632:7687fb9c4f91 4334 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 632:7687fb9c4f91 4335
mbed_official 632:7687fb9c4f91 4336 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
mbed_official 632:7687fb9c4f91 4337 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 632:7687fb9c4f91 4338
mbed_official 632:7687fb9c4f91 4339 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 632:7687fb9c4f91 4340 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 632:7687fb9c4f91 4341
mbed_official 632:7687fb9c4f91 4342 #define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
mbed_official 632:7687fb9c4f91 4343 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
mbed_official 632:7687fb9c4f91 4344
mbed_official 632:7687fb9c4f91 4345 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
mbed_official 632:7687fb9c4f91 4346 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
mbed_official 632:7687fb9c4f91 4347
mbed_official 632:7687fb9c4f91 4348 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 632:7687fb9c4f91 4349 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4350 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4351
mbed_official 632:7687fb9c4f91 4352 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
mbed_official 632:7687fb9c4f91 4353 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 632:7687fb9c4f91 4354 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 632:7687fb9c4f91 4355 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 632:7687fb9c4f91 4356
mbed_official 632:7687fb9c4f91 4357 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
mbed_official 632:7687fb9c4f91 4358 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4359 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4360
mbed_official 632:7687fb9c4f91 4361 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
mbed_official 632:7687fb9c4f91 4362 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
mbed_official 632:7687fb9c4f91 4363 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
mbed_official 632:7687fb9c4f91 4364 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
mbed_official 632:7687fb9c4f91 4365
mbed_official 632:7687fb9c4f91 4366 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4367 /* */
mbed_official 632:7687fb9c4f91 4368 /* Real-Time Clock (RTC) */
mbed_official 632:7687fb9c4f91 4369 /* */
mbed_official 632:7687fb9c4f91 4370 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4371 /******************** Bits definition for RTC_TR register *******************/
mbed_official 632:7687fb9c4f91 4372 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4373 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 4374 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4375 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4376 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 4377 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4378 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4379 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4380 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4381 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 632:7687fb9c4f91 4382 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4383 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4384 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4385 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4386 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4387 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4388 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4389 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4390 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 632:7687fb9c4f91 4391 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4392 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4393 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4394 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4395 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4396 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4397 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4398 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4399
mbed_official 632:7687fb9c4f91 4400 /******************** Bits definition for RTC_DR register *******************/
mbed_official 632:7687fb9c4f91 4401 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 632:7687fb9c4f91 4402 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4403 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4404 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4405 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 4406 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 4407 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4408 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4409 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4410 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4411 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 632:7687fb9c4f91 4412 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4413 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4414 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4415 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4416 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4417 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4418 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4419 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4420 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4421 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 632:7687fb9c4f91 4422 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4423 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4424 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4425 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4426 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4427 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4428 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4429
mbed_official 632:7687fb9c4f91 4430 /******************** Bits definition for RTC_CR register *******************/
mbed_official 632:7687fb9c4f91 4431 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 4432 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 632:7687fb9c4f91 4433 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4434 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4435 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4436 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4437 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4438 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4439 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4440 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4441 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4442 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4443 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4444 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4445 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4446 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4447 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4448 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4449 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4450 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4451 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4452 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 632:7687fb9c4f91 4453 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4454 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4455 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4456
mbed_official 632:7687fb9c4f91 4457 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 632:7687fb9c4f91 4458 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4459 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4460 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4461 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4462 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4463 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4464 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4465 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4466 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4467 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 4468 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4469 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4470 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4471 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4472 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4473 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4474 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4475
mbed_official 632:7687fb9c4f91 4476 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 632:7687fb9c4f91 4477 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 632:7687fb9c4f91 4478 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 632:7687fb9c4f91 4479
mbed_official 632:7687fb9c4f91 4480 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 632:7687fb9c4f91 4481 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 632:7687fb9c4f91 4482
mbed_official 632:7687fb9c4f91 4483 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 632:7687fb9c4f91 4484 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 4485 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 4486 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 632:7687fb9c4f91 4487 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 4488 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 4489 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 4490 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 4491 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 4492 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 4493 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 4494 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 4495 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4496 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 4497 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4498 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4499 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 4500 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4501 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4502 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4503 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4504 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4505 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 632:7687fb9c4f91 4506 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4507 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4508 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4509 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4510 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4511 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4512 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4513 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4514 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 4515 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 632:7687fb9c4f91 4516 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4517 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4518 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4519 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4520 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4521 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4522 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4523 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4524
mbed_official 632:7687fb9c4f91 4525 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 632:7687fb9c4f91 4526 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 4527 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 632:7687fb9c4f91 4528 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 632:7687fb9c4f91 4529 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 632:7687fb9c4f91 4530 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 632:7687fb9c4f91 4531 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 4532 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 4533 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 4534 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 4535 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 4536 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 632:7687fb9c4f91 4537 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4538 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 4539 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4540 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4541 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 4542 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4543 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4544 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4545 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4546 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4547 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 632:7687fb9c4f91 4548 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4549 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4550 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4551 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4552 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4553 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4554 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4555 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4556 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 4557 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 632:7687fb9c4f91 4558 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4559 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4560 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4561 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4562 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4563 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4564 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4565 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4566
mbed_official 632:7687fb9c4f91 4567 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 632:7687fb9c4f91 4568 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 632:7687fb9c4f91 4569
mbed_official 632:7687fb9c4f91 4570 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 632:7687fb9c4f91 4571 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 632:7687fb9c4f91 4572
mbed_official 632:7687fb9c4f91 4573 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 632:7687fb9c4f91 4574 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 632:7687fb9c4f91 4575 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 632:7687fb9c4f91 4576
mbed_official 632:7687fb9c4f91 4577 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 632:7687fb9c4f91 4578 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 632:7687fb9c4f91 4579 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 632:7687fb9c4f91 4580 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 632:7687fb9c4f91 4581 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 632:7687fb9c4f91 4582 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 632:7687fb9c4f91 4583 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 632:7687fb9c4f91 4584 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 632:7687fb9c4f91 4585 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4586 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 632:7687fb9c4f91 4587 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 632:7687fb9c4f91 4588 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4589 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4590 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4591 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4592 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4593 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4594 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4595 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4596 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 632:7687fb9c4f91 4597 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4598 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4599 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4600 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4601 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4602 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4603 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4604 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4605
mbed_official 632:7687fb9c4f91 4606 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 632:7687fb9c4f91 4607 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 632:7687fb9c4f91 4608 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4609 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4610 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4611 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4612 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 632:7687fb9c4f91 4613 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4614 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4615 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4616 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4617 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 632:7687fb9c4f91 4618 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4619 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4620 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 632:7687fb9c4f91 4621 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4622 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4623 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4624 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4625
mbed_official 632:7687fb9c4f91 4626 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 632:7687fb9c4f91 4627 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 632:7687fb9c4f91 4628
mbed_official 632:7687fb9c4f91 4629 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 632:7687fb9c4f91 4630 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4631 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4632 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4633 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 632:7687fb9c4f91 4634 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4635 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4636 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4637 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4638 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4639 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4640 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4641 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 4642 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4643
mbed_official 632:7687fb9c4f91 4644 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 632:7687fb9c4f91 4645 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 632:7687fb9c4f91 4646 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 632:7687fb9c4f91 4647 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 632:7687fb9c4f91 4648 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 632:7687fb9c4f91 4649 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 632:7687fb9c4f91 4650 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 632:7687fb9c4f91 4651 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 632:7687fb9c4f91 4652 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 632:7687fb9c4f91 4653 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 632:7687fb9c4f91 4654 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 632:7687fb9c4f91 4655 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 632:7687fb9c4f91 4656 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 632:7687fb9c4f91 4657 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 632:7687fb9c4f91 4658 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 632:7687fb9c4f91 4659 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 632:7687fb9c4f91 4660 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4661 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 632:7687fb9c4f91 4662 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 632:7687fb9c4f91 4663 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 632:7687fb9c4f91 4664 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 632:7687fb9c4f91 4665
mbed_official 632:7687fb9c4f91 4666 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 632:7687fb9c4f91 4667 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 4668 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 4669 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 4670 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 4671 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 4672 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 632:7687fb9c4f91 4673
mbed_official 632:7687fb9c4f91 4674 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 632:7687fb9c4f91 4675 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 632:7687fb9c4f91 4676 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 632:7687fb9c4f91 4677 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 632:7687fb9c4f91 4678 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 632:7687fb9c4f91 4679 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 632:7687fb9c4f91 4680 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 632:7687fb9c4f91 4681
mbed_official 632:7687fb9c4f91 4682 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 632:7687fb9c4f91 4683 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4684
mbed_official 632:7687fb9c4f91 4685 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 632:7687fb9c4f91 4686 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4687
mbed_official 632:7687fb9c4f91 4688 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 632:7687fb9c4f91 4689 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4690
mbed_official 632:7687fb9c4f91 4691 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 632:7687fb9c4f91 4692 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4693
mbed_official 632:7687fb9c4f91 4694 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 632:7687fb9c4f91 4695 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4696
mbed_official 632:7687fb9c4f91 4697 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 632:7687fb9c4f91 4698 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4699
mbed_official 632:7687fb9c4f91 4700 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 632:7687fb9c4f91 4701 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4702
mbed_official 632:7687fb9c4f91 4703 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 632:7687fb9c4f91 4704 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4705
mbed_official 632:7687fb9c4f91 4706 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 632:7687fb9c4f91 4707 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4708
mbed_official 632:7687fb9c4f91 4709 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 632:7687fb9c4f91 4710 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4711
mbed_official 632:7687fb9c4f91 4712 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 632:7687fb9c4f91 4713 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4714
mbed_official 632:7687fb9c4f91 4715 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 632:7687fb9c4f91 4716 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4717
mbed_official 632:7687fb9c4f91 4718 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 632:7687fb9c4f91 4719 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4720
mbed_official 632:7687fb9c4f91 4721 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 632:7687fb9c4f91 4722 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4723
mbed_official 632:7687fb9c4f91 4724 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 632:7687fb9c4f91 4725 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4726
mbed_official 632:7687fb9c4f91 4727 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 632:7687fb9c4f91 4728 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 632:7687fb9c4f91 4729
mbed_official 632:7687fb9c4f91 4730 /******************** Number of backup registers ******************************/
mbed_official 632:7687fb9c4f91 4731 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
mbed_official 632:7687fb9c4f91 4732
mbed_official 632:7687fb9c4f91 4733 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4734 /* */
mbed_official 632:7687fb9c4f91 4735 /* Serial Peripheral Interface (SPI) */
mbed_official 632:7687fb9c4f91 4736 /* */
mbed_official 632:7687fb9c4f91 4737 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4738 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 632:7687fb9c4f91 4739 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 632:7687fb9c4f91 4740 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 632:7687fb9c4f91 4741 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 632:7687fb9c4f91 4742 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 632:7687fb9c4f91 4743 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4744 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4745 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4746 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 632:7687fb9c4f91 4747 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 632:7687fb9c4f91 4748 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 632:7687fb9c4f91 4749 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 632:7687fb9c4f91 4750 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 632:7687fb9c4f91 4751 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 632:7687fb9c4f91 4752 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 632:7687fb9c4f91 4753 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 632:7687fb9c4f91 4754 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 632:7687fb9c4f91 4755 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 632:7687fb9c4f91 4756
mbed_official 632:7687fb9c4f91 4757 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 632:7687fb9c4f91 4758 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 632:7687fb9c4f91 4759 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 632:7687fb9c4f91 4760 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 632:7687fb9c4f91 4761 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 632:7687fb9c4f91 4762 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 632:7687fb9c4f91 4763 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 632:7687fb9c4f91 4764 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 632:7687fb9c4f91 4765 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 632:7687fb9c4f91 4766 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 632:7687fb9c4f91 4767 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4768 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4769 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 4770 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 4771 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 632:7687fb9c4f91 4772 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 632:7687fb9c4f91 4773 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 632:7687fb9c4f91 4774
mbed_official 632:7687fb9c4f91 4775 /******************** Bit definition for SPI_SR register ********************/
mbed_official 632:7687fb9c4f91 4776 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 632:7687fb9c4f91 4777 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 632:7687fb9c4f91 4778 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 632:7687fb9c4f91 4779 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 632:7687fb9c4f91 4780 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 632:7687fb9c4f91 4781 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 632:7687fb9c4f91 4782 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 632:7687fb9c4f91 4783 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 632:7687fb9c4f91 4784 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 632:7687fb9c4f91 4785 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 632:7687fb9c4f91 4786 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4787 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4788 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 632:7687fb9c4f91 4789 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4790 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4791
mbed_official 632:7687fb9c4f91 4792 /******************** Bit definition for SPI_DR register ********************/
mbed_official 632:7687fb9c4f91 4793 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 632:7687fb9c4f91 4794
mbed_official 632:7687fb9c4f91 4795 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 632:7687fb9c4f91 4796 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 632:7687fb9c4f91 4797
mbed_official 632:7687fb9c4f91 4798 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 632:7687fb9c4f91 4799 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 632:7687fb9c4f91 4800
mbed_official 632:7687fb9c4f91 4801 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 632:7687fb9c4f91 4802 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 632:7687fb9c4f91 4803
mbed_official 632:7687fb9c4f91 4804 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4805 /* */
mbed_official 632:7687fb9c4f91 4806 /* System Configuration(SYSCFG) */
mbed_official 632:7687fb9c4f91 4807 /* */
mbed_official 632:7687fb9c4f91 4808 /******************************************************************************/
mbed_official 632:7687fb9c4f91 4809 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
mbed_official 632:7687fb9c4f91 4810 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 632:7687fb9c4f91 4811 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 4812 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 4813 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
mbed_official 632:7687fb9c4f91 4814 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
mbed_official 632:7687fb9c4f91 4815 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
mbed_official 632:7687fb9c4f91 4816 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 632:7687fb9c4f91 4817 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 632:7687fb9c4f91 4818 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
mbed_official 632:7687fb9c4f91 4819 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
mbed_official 632:7687fb9c4f91 4820 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
mbed_official 632:7687fb9c4f91 4821 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 632:7687fb9c4f91 4822 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 632:7687fb9c4f91 4823 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 632:7687fb9c4f91 4824 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 632:7687fb9c4f91 4825 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
mbed_official 632:7687fb9c4f91 4826 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
mbed_official 632:7687fb9c4f91 4827 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
mbed_official 632:7687fb9c4f91 4828 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
mbed_official 632:7687fb9c4f91 4829 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
mbed_official 632:7687fb9c4f91 4830 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
mbed_official 632:7687fb9c4f91 4831 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
mbed_official 632:7687fb9c4f91 4832 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
mbed_official 632:7687fb9c4f91 4833 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
mbed_official 632:7687fb9c4f91 4834 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
mbed_official 632:7687fb9c4f91 4835 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
mbed_official 632:7687fb9c4f91 4836
mbed_official 632:7687fb9c4f91 4837 /***************** Bit definition for SYSCFG_RCR register *******************/
mbed_official 632:7687fb9c4f91 4838 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
mbed_official 632:7687fb9c4f91 4839 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
mbed_official 632:7687fb9c4f91 4840 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
mbed_official 632:7687fb9c4f91 4841 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
mbed_official 632:7687fb9c4f91 4842
mbed_official 632:7687fb9c4f91 4843 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 632:7687fb9c4f91 4844 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 632:7687fb9c4f91 4845 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 632:7687fb9c4f91 4846 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 632:7687fb9c4f91 4847 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 632:7687fb9c4f91 4848
mbed_official 632:7687fb9c4f91 4849 /*!<*
mbed_official 632:7687fb9c4f91 4850 * @brief EXTI0 configuration
mbed_official 632:7687fb9c4f91 4851 */
mbed_official 632:7687fb9c4f91 4852 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 632:7687fb9c4f91 4853 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 632:7687fb9c4f91 4854 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 632:7687fb9c4f91 4855 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 632:7687fb9c4f91 4856 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 632:7687fb9c4f91 4857 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 632:7687fb9c4f91 4858
mbed_official 632:7687fb9c4f91 4859 /*!<*
mbed_official 632:7687fb9c4f91 4860 * @brief EXTI1 configuration
mbed_official 632:7687fb9c4f91 4861 */
mbed_official 632:7687fb9c4f91 4862 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 632:7687fb9c4f91 4863 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 632:7687fb9c4f91 4864 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 632:7687fb9c4f91 4865 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 632:7687fb9c4f91 4866 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 632:7687fb9c4f91 4867 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 632:7687fb9c4f91 4868
mbed_official 632:7687fb9c4f91 4869 /*!<*
mbed_official 632:7687fb9c4f91 4870 * @brief EXTI2 configuration
mbed_official 632:7687fb9c4f91 4871 */
mbed_official 632:7687fb9c4f91 4872 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 632:7687fb9c4f91 4873 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 632:7687fb9c4f91 4874 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 632:7687fb9c4f91 4875 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 632:7687fb9c4f91 4876 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 632:7687fb9c4f91 4877 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 632:7687fb9c4f91 4878
mbed_official 632:7687fb9c4f91 4879 /*!<*
mbed_official 632:7687fb9c4f91 4880 * @brief EXTI3 configuration
mbed_official 632:7687fb9c4f91 4881 */
mbed_official 632:7687fb9c4f91 4882 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 632:7687fb9c4f91 4883 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 632:7687fb9c4f91 4884 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 632:7687fb9c4f91 4885 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 632:7687fb9c4f91 4886 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 632:7687fb9c4f91 4887
mbed_official 632:7687fb9c4f91 4888 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 632:7687fb9c4f91 4889 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 632:7687fb9c4f91 4890 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 632:7687fb9c4f91 4891 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 632:7687fb9c4f91 4892 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 632:7687fb9c4f91 4893
mbed_official 632:7687fb9c4f91 4894 /*!<*
mbed_official 632:7687fb9c4f91 4895 * @brief EXTI4 configuration
mbed_official 632:7687fb9c4f91 4896 */
mbed_official 632:7687fb9c4f91 4897 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 632:7687fb9c4f91 4898 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 632:7687fb9c4f91 4899 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 632:7687fb9c4f91 4900 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 632:7687fb9c4f91 4901 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 632:7687fb9c4f91 4902 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 632:7687fb9c4f91 4903
mbed_official 632:7687fb9c4f91 4904 /*!<*
mbed_official 632:7687fb9c4f91 4905 * @brief EXTI5 configuration
mbed_official 632:7687fb9c4f91 4906 */
mbed_official 632:7687fb9c4f91 4907 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 632:7687fb9c4f91 4908 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 632:7687fb9c4f91 4909 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 632:7687fb9c4f91 4910 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 632:7687fb9c4f91 4911 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 632:7687fb9c4f91 4912 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 632:7687fb9c4f91 4913
mbed_official 632:7687fb9c4f91 4914 /*!<*
mbed_official 632:7687fb9c4f91 4915 * @brief EXTI6 configuration
mbed_official 632:7687fb9c4f91 4916 */
mbed_official 632:7687fb9c4f91 4917 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 632:7687fb9c4f91 4918 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 632:7687fb9c4f91 4919 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 632:7687fb9c4f91 4920 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 632:7687fb9c4f91 4921 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 632:7687fb9c4f91 4922 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 632:7687fb9c4f91 4923
mbed_official 632:7687fb9c4f91 4924 /*!<*
mbed_official 632:7687fb9c4f91 4925 * @brief EXTI7 configuration
mbed_official 632:7687fb9c4f91 4926 */
mbed_official 632:7687fb9c4f91 4927 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 632:7687fb9c4f91 4928 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 632:7687fb9c4f91 4929 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 632:7687fb9c4f91 4930 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 632:7687fb9c4f91 4931 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 632:7687fb9c4f91 4932
mbed_official 632:7687fb9c4f91 4933 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 632:7687fb9c4f91 4934 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 632:7687fb9c4f91 4935 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 632:7687fb9c4f91 4936 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 632:7687fb9c4f91 4937 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 632:7687fb9c4f91 4938
mbed_official 632:7687fb9c4f91 4939 /*!<*
mbed_official 632:7687fb9c4f91 4940 * @brief EXTI8 configuration
mbed_official 632:7687fb9c4f91 4941 */
mbed_official 632:7687fb9c4f91 4942 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 632:7687fb9c4f91 4943 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 632:7687fb9c4f91 4944 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 632:7687fb9c4f91 4945 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 632:7687fb9c4f91 4946 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 632:7687fb9c4f91 4947
mbed_official 632:7687fb9c4f91 4948 /*!<*
mbed_official 632:7687fb9c4f91 4949 * @brief EXTI9 configuration
mbed_official 632:7687fb9c4f91 4950 */
mbed_official 632:7687fb9c4f91 4951 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 632:7687fb9c4f91 4952 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 632:7687fb9c4f91 4953 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 632:7687fb9c4f91 4954 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 632:7687fb9c4f91 4955 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 632:7687fb9c4f91 4956 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 632:7687fb9c4f91 4957
mbed_official 632:7687fb9c4f91 4958 /*!<*
mbed_official 632:7687fb9c4f91 4959 * @brief EXTI10 configuration
mbed_official 632:7687fb9c4f91 4960 */
mbed_official 632:7687fb9c4f91 4961 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 632:7687fb9c4f91 4962 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 632:7687fb9c4f91 4963 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 632:7687fb9c4f91 4964 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 632:7687fb9c4f91 4965 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 632:7687fb9c4f91 4966 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 632:7687fb9c4f91 4967
mbed_official 632:7687fb9c4f91 4968 /*!<*
mbed_official 632:7687fb9c4f91 4969 * @brief EXTI11 configuration
mbed_official 632:7687fb9c4f91 4970 */
mbed_official 632:7687fb9c4f91 4971 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 632:7687fb9c4f91 4972 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 632:7687fb9c4f91 4973 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 632:7687fb9c4f91 4974 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 632:7687fb9c4f91 4975 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 632:7687fb9c4f91 4976
mbed_official 632:7687fb9c4f91 4977 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 632:7687fb9c4f91 4978 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 632:7687fb9c4f91 4979 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 632:7687fb9c4f91 4980 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 632:7687fb9c4f91 4981 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 632:7687fb9c4f91 4982
mbed_official 632:7687fb9c4f91 4983 /*!<*
mbed_official 632:7687fb9c4f91 4984 * @brief EXTI12 configuration
mbed_official 632:7687fb9c4f91 4985 */
mbed_official 632:7687fb9c4f91 4986 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 632:7687fb9c4f91 4987 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 632:7687fb9c4f91 4988 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 632:7687fb9c4f91 4989 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 632:7687fb9c4f91 4990 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 632:7687fb9c4f91 4991
mbed_official 632:7687fb9c4f91 4992 /*!<*
mbed_official 632:7687fb9c4f91 4993 * @brief EXTI13 configuration
mbed_official 632:7687fb9c4f91 4994 */
mbed_official 632:7687fb9c4f91 4995 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 632:7687fb9c4f91 4996 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 632:7687fb9c4f91 4997 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 632:7687fb9c4f91 4998 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 632:7687fb9c4f91 4999 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 632:7687fb9c4f91 5000
mbed_official 632:7687fb9c4f91 5001 /*!<*
mbed_official 632:7687fb9c4f91 5002 * @brief EXTI14 configuration
mbed_official 632:7687fb9c4f91 5003 */
mbed_official 632:7687fb9c4f91 5004 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 632:7687fb9c4f91 5005 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 632:7687fb9c4f91 5006 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 632:7687fb9c4f91 5007 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 632:7687fb9c4f91 5008 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 632:7687fb9c4f91 5009
mbed_official 632:7687fb9c4f91 5010 /*!<*
mbed_official 632:7687fb9c4f91 5011 * @brief EXTI15 configuration
mbed_official 632:7687fb9c4f91 5012 */
mbed_official 632:7687fb9c4f91 5013 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 632:7687fb9c4f91 5014 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 632:7687fb9c4f91 5015 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 632:7687fb9c4f91 5016 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 632:7687fb9c4f91 5017 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 632:7687fb9c4f91 5018
mbed_official 632:7687fb9c4f91 5019 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
mbed_official 632:7687fb9c4f91 5020 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
mbed_official 632:7687fb9c4f91 5021 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
mbed_official 632:7687fb9c4f91 5022 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
mbed_official 632:7687fb9c4f91 5023 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
mbed_official 632:7687fb9c4f91 5024 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 632:7687fb9c4f91 5025
mbed_official 632:7687fb9c4f91 5026 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
mbed_official 632:7687fb9c4f91 5027 #define SYSCFG_CFGR3_DMA_RMP ((uint32_t)0x000003FF) /*!< DMA remap mask */
mbed_official 632:7687fb9c4f91 5028 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
mbed_official 632:7687fb9c4f91 5029 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
mbed_official 632:7687fb9c4f91 5030 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
mbed_official 632:7687fb9c4f91 5031 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
mbed_official 632:7687fb9c4f91 5032 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
mbed_official 632:7687fb9c4f91 5033 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
mbed_official 632:7687fb9c4f91 5034 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
mbed_official 632:7687fb9c4f91 5035 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
mbed_official 632:7687fb9c4f91 5036 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
mbed_official 632:7687fb9c4f91 5037 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
mbed_official 632:7687fb9c4f91 5038 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
mbed_official 632:7687fb9c4f91 5039 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
mbed_official 632:7687fb9c4f91 5040 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
mbed_official 632:7687fb9c4f91 5041 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
mbed_official 632:7687fb9c4f91 5042 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
mbed_official 632:7687fb9c4f91 5043
mbed_official 632:7687fb9c4f91 5044 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5045 /* */
mbed_official 632:7687fb9c4f91 5046 /* TIM */
mbed_official 632:7687fb9c4f91 5047 /* */
mbed_official 632:7687fb9c4f91 5048 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5049 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 632:7687fb9c4f91 5050 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 632:7687fb9c4f91 5051 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 632:7687fb9c4f91 5052 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 632:7687fb9c4f91 5053 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 632:7687fb9c4f91 5054 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 632:7687fb9c4f91 5055
mbed_official 632:7687fb9c4f91 5056 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 632:7687fb9c4f91 5057 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5058 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5059
mbed_official 632:7687fb9c4f91 5060 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 632:7687fb9c4f91 5061
mbed_official 632:7687fb9c4f91 5062 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 632:7687fb9c4f91 5063 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5064 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5065
mbed_official 632:7687fb9c4f91 5066 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
mbed_official 632:7687fb9c4f91 5067
mbed_official 632:7687fb9c4f91 5068 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 632:7687fb9c4f91 5069 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 632:7687fb9c4f91 5070 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 632:7687fb9c4f91 5071 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 632:7687fb9c4f91 5072
mbed_official 632:7687fb9c4f91 5073 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 632:7687fb9c4f91 5074 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5075 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5076 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5077
mbed_official 632:7687fb9c4f91 5078 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 632:7687fb9c4f91 5079 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 632:7687fb9c4f91 5080 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 632:7687fb9c4f91 5081 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 632:7687fb9c4f91 5082 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 632:7687fb9c4f91 5083 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 632:7687fb9c4f91 5084 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 632:7687fb9c4f91 5085 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 632:7687fb9c4f91 5086 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 632:7687fb9c4f91 5087 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 632:7687fb9c4f91 5088
mbed_official 632:7687fb9c4f91 5089 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 632:7687fb9c4f91 5090 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5091 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5092 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5093 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5094
mbed_official 632:7687fb9c4f91 5095 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 632:7687fb9c4f91 5096 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 632:7687fb9c4f91 5097 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5098 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5099 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5100 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5101
mbed_official 632:7687fb9c4f91 5102 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 632:7687fb9c4f91 5103
mbed_official 632:7687fb9c4f91 5104 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 632:7687fb9c4f91 5105 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5106 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5107 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5108
mbed_official 632:7687fb9c4f91 5109 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 632:7687fb9c4f91 5110
mbed_official 632:7687fb9c4f91 5111 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 632:7687fb9c4f91 5112 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5113 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5114 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5115 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5116
mbed_official 632:7687fb9c4f91 5117 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 632:7687fb9c4f91 5118 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5119 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5120
mbed_official 632:7687fb9c4f91 5121 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 632:7687fb9c4f91 5122 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 632:7687fb9c4f91 5123
mbed_official 632:7687fb9c4f91 5124 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 632:7687fb9c4f91 5125 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 632:7687fb9c4f91 5126 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 632:7687fb9c4f91 5127 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 632:7687fb9c4f91 5128 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 632:7687fb9c4f91 5129 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 632:7687fb9c4f91 5130 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 632:7687fb9c4f91 5131 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 632:7687fb9c4f91 5132 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 632:7687fb9c4f91 5133 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 632:7687fb9c4f91 5134 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 632:7687fb9c4f91 5135 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 632:7687fb9c4f91 5136 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 632:7687fb9c4f91 5137 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 632:7687fb9c4f91 5138 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 632:7687fb9c4f91 5139 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 632:7687fb9c4f91 5140
mbed_official 632:7687fb9c4f91 5141 /******************** Bit definition for TIM_SR register ********************/
mbed_official 632:7687fb9c4f91 5142 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 632:7687fb9c4f91 5143 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 632:7687fb9c4f91 5144 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 632:7687fb9c4f91 5145 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 632:7687fb9c4f91 5146 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 632:7687fb9c4f91 5147 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 632:7687fb9c4f91 5148 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 632:7687fb9c4f91 5149 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 632:7687fb9c4f91 5150 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
mbed_official 632:7687fb9c4f91 5151 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 632:7687fb9c4f91 5152 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 632:7687fb9c4f91 5153 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 632:7687fb9c4f91 5154 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 632:7687fb9c4f91 5155 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
mbed_official 632:7687fb9c4f91 5156 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
mbed_official 632:7687fb9c4f91 5157
mbed_official 632:7687fb9c4f91 5158 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 632:7687fb9c4f91 5159 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 632:7687fb9c4f91 5160 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 632:7687fb9c4f91 5161 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 632:7687fb9c4f91 5162 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 632:7687fb9c4f91 5163 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 632:7687fb9c4f91 5164 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 632:7687fb9c4f91 5165 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 632:7687fb9c4f91 5166 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 632:7687fb9c4f91 5167 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
mbed_official 632:7687fb9c4f91 5168
mbed_official 632:7687fb9c4f91 5169 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 632:7687fb9c4f91 5170 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 632:7687fb9c4f91 5171 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5172 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5173
mbed_official 632:7687fb9c4f91 5174 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 632:7687fb9c4f91 5175 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 632:7687fb9c4f91 5176
mbed_official 632:7687fb9c4f91 5177 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 632:7687fb9c4f91 5178 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5179 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5180 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5181 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5182
mbed_official 632:7687fb9c4f91 5183 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 632:7687fb9c4f91 5184
mbed_official 632:7687fb9c4f91 5185 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 632:7687fb9c4f91 5186 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5187 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5188
mbed_official 632:7687fb9c4f91 5189 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 632:7687fb9c4f91 5190 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 632:7687fb9c4f91 5191
mbed_official 632:7687fb9c4f91 5192 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 632:7687fb9c4f91 5193 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5194 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5195 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5196 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5197
mbed_official 632:7687fb9c4f91 5198 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 632:7687fb9c4f91 5199
mbed_official 632:7687fb9c4f91 5200 /*----------------------------------------------------------------------------*/
mbed_official 632:7687fb9c4f91 5201
mbed_official 632:7687fb9c4f91 5202 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 632:7687fb9c4f91 5203 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5204 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5205
mbed_official 632:7687fb9c4f91 5206 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 632:7687fb9c4f91 5207 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5208 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5209 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5210 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5211
mbed_official 632:7687fb9c4f91 5212 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 632:7687fb9c4f91 5213 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5214 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5215
mbed_official 632:7687fb9c4f91 5216 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 632:7687fb9c4f91 5217 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5218 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5219 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5220 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5221
mbed_official 632:7687fb9c4f91 5222 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 632:7687fb9c4f91 5223 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 632:7687fb9c4f91 5224 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5225 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5226
mbed_official 632:7687fb9c4f91 5227 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 632:7687fb9c4f91 5228 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 632:7687fb9c4f91 5229
mbed_official 632:7687fb9c4f91 5230 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 632:7687fb9c4f91 5231 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5232 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5233 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5234 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5235
mbed_official 632:7687fb9c4f91 5236 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 632:7687fb9c4f91 5237
mbed_official 632:7687fb9c4f91 5238 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 632:7687fb9c4f91 5239 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5240 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5241
mbed_official 632:7687fb9c4f91 5242 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 632:7687fb9c4f91 5243 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 632:7687fb9c4f91 5244
mbed_official 632:7687fb9c4f91 5245 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 632:7687fb9c4f91 5246 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5247 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5248 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5249 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5250
mbed_official 632:7687fb9c4f91 5251 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 632:7687fb9c4f91 5252
mbed_official 632:7687fb9c4f91 5253 /*----------------------------------------------------------------------------*/
mbed_official 632:7687fb9c4f91 5254
mbed_official 632:7687fb9c4f91 5255 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 632:7687fb9c4f91 5256 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5257 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5258
mbed_official 632:7687fb9c4f91 5259 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 632:7687fb9c4f91 5260 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5261 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5262 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5263 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5264
mbed_official 632:7687fb9c4f91 5265 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 632:7687fb9c4f91 5266 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5267 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5268
mbed_official 632:7687fb9c4f91 5269 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 632:7687fb9c4f91 5270 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5271 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5272 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5273 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5274
mbed_official 632:7687fb9c4f91 5275 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 632:7687fb9c4f91 5276 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 632:7687fb9c4f91 5277 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 632:7687fb9c4f91 5278 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 632:7687fb9c4f91 5279 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 632:7687fb9c4f91 5280 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 632:7687fb9c4f91 5281 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 632:7687fb9c4f91 5282 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 632:7687fb9c4f91 5283 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 632:7687fb9c4f91 5284 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 632:7687fb9c4f91 5285 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 632:7687fb9c4f91 5286 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 632:7687fb9c4f91 5287 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 632:7687fb9c4f91 5288 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 632:7687fb9c4f91 5289 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 632:7687fb9c4f91 5290 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 632:7687fb9c4f91 5291 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
mbed_official 632:7687fb9c4f91 5292 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
mbed_official 632:7687fb9c4f91 5293 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
mbed_official 632:7687fb9c4f91 5294 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
mbed_official 632:7687fb9c4f91 5295
mbed_official 632:7687fb9c4f91 5296 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 632:7687fb9c4f91 5297 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 632:7687fb9c4f91 5298 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
mbed_official 632:7687fb9c4f91 5299
mbed_official 632:7687fb9c4f91 5300 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 632:7687fb9c4f91 5301 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 632:7687fb9c4f91 5302
mbed_official 632:7687fb9c4f91 5303 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 632:7687fb9c4f91 5304 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 632:7687fb9c4f91 5305
mbed_official 632:7687fb9c4f91 5306 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 632:7687fb9c4f91 5307 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 632:7687fb9c4f91 5308
mbed_official 632:7687fb9c4f91 5309 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 632:7687fb9c4f91 5310 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 632:7687fb9c4f91 5311
mbed_official 632:7687fb9c4f91 5312 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 632:7687fb9c4f91 5313 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 632:7687fb9c4f91 5314
mbed_official 632:7687fb9c4f91 5315 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 632:7687fb9c4f91 5316 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 632:7687fb9c4f91 5317
mbed_official 632:7687fb9c4f91 5318 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 632:7687fb9c4f91 5319 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 632:7687fb9c4f91 5320
mbed_official 632:7687fb9c4f91 5321 /******************* Bit definition for TIM_CCR5 register *******************/
mbed_official 632:7687fb9c4f91 5322 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
mbed_official 632:7687fb9c4f91 5323 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
mbed_official 632:7687fb9c4f91 5324 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
mbed_official 632:7687fb9c4f91 5325 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
mbed_official 632:7687fb9c4f91 5326
mbed_official 632:7687fb9c4f91 5327 /******************* Bit definition for TIM_CCR6 register *******************/
mbed_official 632:7687fb9c4f91 5328 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
mbed_official 632:7687fb9c4f91 5329
mbed_official 632:7687fb9c4f91 5330 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 632:7687fb9c4f91 5331 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 632:7687fb9c4f91 5332 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5333 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5334 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5335 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5336 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5337 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 632:7687fb9c4f91 5338 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 632:7687fb9c4f91 5339 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 632:7687fb9c4f91 5340
mbed_official 632:7687fb9c4f91 5341 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 632:7687fb9c4f91 5342 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5343 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5344
mbed_official 632:7687fb9c4f91 5345 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 632:7687fb9c4f91 5346 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 632:7687fb9c4f91 5347 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
mbed_official 632:7687fb9c4f91 5348 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
mbed_official 632:7687fb9c4f91 5349 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 632:7687fb9c4f91 5350 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 632:7687fb9c4f91 5351
mbed_official 632:7687fb9c4f91 5352 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
mbed_official 632:7687fb9c4f91 5353 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
mbed_official 632:7687fb9c4f91 5354
mbed_official 632:7687fb9c4f91 5355 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
mbed_official 632:7687fb9c4f91 5356 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
mbed_official 632:7687fb9c4f91 5357
mbed_official 632:7687fb9c4f91 5358 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 632:7687fb9c4f91 5359 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 632:7687fb9c4f91 5360 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5361 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5362 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5363 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5364 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5365
mbed_official 632:7687fb9c4f91 5366 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 632:7687fb9c4f91 5367 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5368 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5369 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5370 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5371 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5372
mbed_official 632:7687fb9c4f91 5373 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 632:7687fb9c4f91 5374 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 632:7687fb9c4f91 5375
mbed_official 632:7687fb9c4f91 5376 /******************* Bit definition for TIM16_OR register *********************/
mbed_official 632:7687fb9c4f91 5377 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
mbed_official 632:7687fb9c4f91 5378 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5379 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5380
mbed_official 632:7687fb9c4f91 5381 /******************* Bit definition for TIM1_OR register *********************/
mbed_official 632:7687fb9c4f91 5382 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
mbed_official 632:7687fb9c4f91 5383 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5384 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5385 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5386 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5387
mbed_official 632:7687fb9c4f91 5388 /****************** Bit definition for TIM_CCMR3 register *******************/
mbed_official 632:7687fb9c4f91 5389 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
mbed_official 632:7687fb9c4f91 5390 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
mbed_official 632:7687fb9c4f91 5391
mbed_official 632:7687fb9c4f91 5392 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
mbed_official 632:7687fb9c4f91 5393 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5394 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5395 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5396 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5397
mbed_official 632:7687fb9c4f91 5398 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
mbed_official 632:7687fb9c4f91 5399
mbed_official 632:7687fb9c4f91 5400 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
mbed_official 632:7687fb9c4f91 5401 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
mbed_official 632:7687fb9c4f91 5402
mbed_official 632:7687fb9c4f91 5403 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
mbed_official 632:7687fb9c4f91 5404 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5405 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5406 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5407 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5408
mbed_official 632:7687fb9c4f91 5409 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
mbed_official 632:7687fb9c4f91 5410
mbed_official 632:7687fb9c4f91 5411 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5412 /* */
mbed_official 632:7687fb9c4f91 5413 /* Touch Sensing Controller (TSC) */
mbed_official 632:7687fb9c4f91 5414 /* */
mbed_official 632:7687fb9c4f91 5415 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5416 /******************* Bit definition for TSC_CR register *********************/
mbed_official 632:7687fb9c4f91 5417 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 632:7687fb9c4f91 5418 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 632:7687fb9c4f91 5419 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 632:7687fb9c4f91 5420 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 632:7687fb9c4f91 5421 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 632:7687fb9c4f91 5422
mbed_official 632:7687fb9c4f91 5423 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 632:7687fb9c4f91 5424 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5425 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5426 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5427
mbed_official 632:7687fb9c4f91 5428 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 632:7687fb9c4f91 5429 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5430 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5431 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5432
mbed_official 632:7687fb9c4f91 5433 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 632:7687fb9c4f91 5434 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 632:7687fb9c4f91 5435
mbed_official 632:7687fb9c4f91 5436 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 632:7687fb9c4f91 5437 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5438 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5439 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5440 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5441 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5442 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 632:7687fb9c4f91 5443 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 632:7687fb9c4f91 5444
mbed_official 632:7687fb9c4f91 5445 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 632:7687fb9c4f91 5446 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5447 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5448 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5449 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5450
mbed_official 632:7687fb9c4f91 5451 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 632:7687fb9c4f91 5452 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5453 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5454 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5455 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5456
mbed_official 632:7687fb9c4f91 5457 /******************* Bit definition for TSC_IER register ********************/
mbed_official 632:7687fb9c4f91 5458 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 632:7687fb9c4f91 5459 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 632:7687fb9c4f91 5460
mbed_official 632:7687fb9c4f91 5461 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 632:7687fb9c4f91 5462 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 632:7687fb9c4f91 5463 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 632:7687fb9c4f91 5464
mbed_official 632:7687fb9c4f91 5465 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 632:7687fb9c4f91 5466 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 632:7687fb9c4f91 5467 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 632:7687fb9c4f91 5468
mbed_official 632:7687fb9c4f91 5469 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 632:7687fb9c4f91 5470 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5471 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5472 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5473 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5474 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5475 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5476 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5477 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5478 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5479 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5480 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5481 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5482 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5483 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5484 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5485 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5486 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5487 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5488 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5489 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5490 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5491 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5492 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5493 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5494 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5495 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5496 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5497 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5498 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5499 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5500 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5501 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 632:7687fb9c4f91 5502
mbed_official 632:7687fb9c4f91 5503 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 632:7687fb9c4f91 5504 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5505 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5506 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5507 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5508 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5509 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5510 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5511 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5512 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5513 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5514 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5515 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5516 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5517 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5518 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5519 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5520 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5521 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5522 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5523 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5524 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5525 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5526 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5527 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5528 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5529 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5530 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5531 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5532 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 632:7687fb9c4f91 5533 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 632:7687fb9c4f91 5534 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 632:7687fb9c4f91 5535 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 632:7687fb9c4f91 5536
mbed_official 632:7687fb9c4f91 5537 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 632:7687fb9c4f91 5538 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5539 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5540 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5541 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5542 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5543 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5544 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5545 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5546 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5547 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5548 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5549 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5550 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5551 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5552 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5553 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5554 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5555 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5556 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5557 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5558 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5559 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5560 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5561 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5562 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5563 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5564 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5565 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5566 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 632:7687fb9c4f91 5567 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 632:7687fb9c4f91 5568 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 632:7687fb9c4f91 5569 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 632:7687fb9c4f91 5570
mbed_official 632:7687fb9c4f91 5571 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 632:7687fb9c4f91 5572 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5573 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5574 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5575 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5576 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5577 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5578 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5579 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5580 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5581 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5582 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5583 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5584 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5585 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5586 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5587 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5588 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5589 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5590 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5591 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5592 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5593 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5594 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5595 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5596 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5597 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5598 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5599 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5600 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 632:7687fb9c4f91 5601 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 632:7687fb9c4f91 5602 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 632:7687fb9c4f91 5603 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 632:7687fb9c4f91 5604
mbed_official 632:7687fb9c4f91 5605 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 632:7687fb9c4f91 5606 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 632:7687fb9c4f91 5607 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 632:7687fb9c4f91 5608 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 632:7687fb9c4f91 5609 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 632:7687fb9c4f91 5610 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 632:7687fb9c4f91 5611 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 632:7687fb9c4f91 5612 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 632:7687fb9c4f91 5613 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 632:7687fb9c4f91 5614 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 632:7687fb9c4f91 5615 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 632:7687fb9c4f91 5616 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 632:7687fb9c4f91 5617 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 632:7687fb9c4f91 5618 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 632:7687fb9c4f91 5619 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 632:7687fb9c4f91 5620 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 632:7687fb9c4f91 5621 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 632:7687fb9c4f91 5622
mbed_official 632:7687fb9c4f91 5623 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 632:7687fb9c4f91 5624 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 632:7687fb9c4f91 5625
mbed_official 632:7687fb9c4f91 5626 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5627 /* */
mbed_official 632:7687fb9c4f91 5628 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 632:7687fb9c4f91 5629 /* */
mbed_official 632:7687fb9c4f91 5630 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5631 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 632:7687fb9c4f91 5632 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 632:7687fb9c4f91 5633 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 632:7687fb9c4f91 5634 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 632:7687fb9c4f91 5635 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 632:7687fb9c4f91 5636 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 632:7687fb9c4f91 5637 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 632:7687fb9c4f91 5638 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 632:7687fb9c4f91 5639 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 632:7687fb9c4f91 5640 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 632:7687fb9c4f91 5641 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 632:7687fb9c4f91 5642 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 632:7687fb9c4f91 5643 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 632:7687fb9c4f91 5644 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 632:7687fb9c4f91 5645 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 632:7687fb9c4f91 5646 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 632:7687fb9c4f91 5647 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 632:7687fb9c4f91 5648 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 632:7687fb9c4f91 5649 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5650 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5651 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 5652 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 5653 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 632:7687fb9c4f91 5654 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 632:7687fb9c4f91 5655 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5656 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5657 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 5658 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 632:7687fb9c4f91 5659 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 632:7687fb9c4f91 5660 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 632:7687fb9c4f91 5661 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 632:7687fb9c4f91 5662 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
mbed_official 632:7687fb9c4f91 5663 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
mbed_official 632:7687fb9c4f91 5664
mbed_official 632:7687fb9c4f91 5665 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 632:7687fb9c4f91 5666 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 632:7687fb9c4f91 5667 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 632:7687fb9c4f91 5668 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 632:7687fb9c4f91 5669 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 632:7687fb9c4f91 5670 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 632:7687fb9c4f91 5671 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 632:7687fb9c4f91 5672 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 632:7687fb9c4f91 5673 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 632:7687fb9c4f91 5674 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5675 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5676 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 632:7687fb9c4f91 5677 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 632:7687fb9c4f91 5678 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 632:7687fb9c4f91 5679 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 632:7687fb9c4f91 5680 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 632:7687fb9c4f91 5681 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 632:7687fb9c4f91 5682 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 632:7687fb9c4f91 5683 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 632:7687fb9c4f91 5684 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5685 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5686 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 632:7687fb9c4f91 5687 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 632:7687fb9c4f91 5688
mbed_official 632:7687fb9c4f91 5689 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 632:7687fb9c4f91 5690 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 632:7687fb9c4f91 5691 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 632:7687fb9c4f91 5692 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 632:7687fb9c4f91 5693 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 632:7687fb9c4f91 5694 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 632:7687fb9c4f91 5695 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 632:7687fb9c4f91 5696 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 632:7687fb9c4f91 5697 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 632:7687fb9c4f91 5698 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 632:7687fb9c4f91 5699 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 632:7687fb9c4f91 5700 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 632:7687fb9c4f91 5701 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 632:7687fb9c4f91 5702 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 632:7687fb9c4f91 5703 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 632:7687fb9c4f91 5704 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 632:7687fb9c4f91 5705 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 632:7687fb9c4f91 5706 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 632:7687fb9c4f91 5707 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5708 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5709 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 632:7687fb9c4f91 5710 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 632:7687fb9c4f91 5711 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 632:7687fb9c4f91 5712 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 632:7687fb9c4f91 5713 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 632:7687fb9c4f91 5714
mbed_official 632:7687fb9c4f91 5715 /****************** Bit definition for USART_BRR register *******************/
mbed_official 632:7687fb9c4f91 5716 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 632:7687fb9c4f91 5717 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 632:7687fb9c4f91 5718
mbed_official 632:7687fb9c4f91 5719 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 632:7687fb9c4f91 5720 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 632:7687fb9c4f91 5721 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 632:7687fb9c4f91 5722
mbed_official 632:7687fb9c4f91 5723
mbed_official 632:7687fb9c4f91 5724 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 632:7687fb9c4f91 5725 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 632:7687fb9c4f91 5726 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 632:7687fb9c4f91 5727
mbed_official 632:7687fb9c4f91 5728 /******************* Bit definition for USART_RQR register ******************/
mbed_official 632:7687fb9c4f91 5729 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 632:7687fb9c4f91 5730 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 632:7687fb9c4f91 5731 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 632:7687fb9c4f91 5732 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 632:7687fb9c4f91 5733 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 632:7687fb9c4f91 5734
mbed_official 632:7687fb9c4f91 5735 /******************* Bit definition for USART_ISR register ******************/
mbed_official 632:7687fb9c4f91 5736 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 632:7687fb9c4f91 5737 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 632:7687fb9c4f91 5738 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 632:7687fb9c4f91 5739 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 632:7687fb9c4f91 5740 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 632:7687fb9c4f91 5741 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 632:7687fb9c4f91 5742 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 632:7687fb9c4f91 5743 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 632:7687fb9c4f91 5744 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 632:7687fb9c4f91 5745 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 632:7687fb9c4f91 5746 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 632:7687fb9c4f91 5747 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 632:7687fb9c4f91 5748 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 632:7687fb9c4f91 5749 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 632:7687fb9c4f91 5750 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 632:7687fb9c4f91 5751 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 632:7687fb9c4f91 5752 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 632:7687fb9c4f91 5753 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 632:7687fb9c4f91 5754 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 632:7687fb9c4f91 5755 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 632:7687fb9c4f91 5756 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 632:7687fb9c4f91 5757 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 632:7687fb9c4f91 5758
mbed_official 632:7687fb9c4f91 5759 /******************* Bit definition for USART_ICR register ******************/
mbed_official 632:7687fb9c4f91 5760 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 632:7687fb9c4f91 5761 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 632:7687fb9c4f91 5762 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 632:7687fb9c4f91 5763 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 632:7687fb9c4f91 5764 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 632:7687fb9c4f91 5765 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 632:7687fb9c4f91 5766 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 632:7687fb9c4f91 5767 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 632:7687fb9c4f91 5768 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 632:7687fb9c4f91 5769 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 632:7687fb9c4f91 5770 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 632:7687fb9c4f91 5771 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 632:7687fb9c4f91 5772
mbed_official 632:7687fb9c4f91 5773 /******************* Bit definition for USART_RDR register ******************/
mbed_official 632:7687fb9c4f91 5774 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 632:7687fb9c4f91 5775
mbed_official 632:7687fb9c4f91 5776 /******************* Bit definition for USART_TDR register ******************/
mbed_official 632:7687fb9c4f91 5777 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 632:7687fb9c4f91 5778
mbed_official 632:7687fb9c4f91 5779 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5780 /* */
mbed_official 632:7687fb9c4f91 5781 /* Window WATCHDOG */
mbed_official 632:7687fb9c4f91 5782 /* */
mbed_official 632:7687fb9c4f91 5783 /******************************************************************************/
mbed_official 632:7687fb9c4f91 5784 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 632:7687fb9c4f91 5785 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 632:7687fb9c4f91 5786 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5787 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5788 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5789 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5790 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5791 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 632:7687fb9c4f91 5792 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 632:7687fb9c4f91 5793
mbed_official 632:7687fb9c4f91 5794 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
mbed_official 632:7687fb9c4f91 5795
mbed_official 632:7687fb9c4f91 5796 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 632:7687fb9c4f91 5797 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 632:7687fb9c4f91 5798 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5799 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5800 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 632:7687fb9c4f91 5801 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 632:7687fb9c4f91 5802 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 632:7687fb9c4f91 5803 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 632:7687fb9c4f91 5804 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 632:7687fb9c4f91 5805
mbed_official 632:7687fb9c4f91 5806 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 632:7687fb9c4f91 5807 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 632:7687fb9c4f91 5808 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 632:7687fb9c4f91 5809
mbed_official 632:7687fb9c4f91 5810 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
mbed_official 632:7687fb9c4f91 5811
mbed_official 632:7687fb9c4f91 5812 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 632:7687fb9c4f91 5813 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
mbed_official 632:7687fb9c4f91 5814
mbed_official 632:7687fb9c4f91 5815 /**
mbed_official 632:7687fb9c4f91 5816 * @}
mbed_official 632:7687fb9c4f91 5817 */
mbed_official 632:7687fb9c4f91 5818
mbed_official 632:7687fb9c4f91 5819 /**
mbed_official 632:7687fb9c4f91 5820 * @}
mbed_official 632:7687fb9c4f91 5821 */
mbed_official 632:7687fb9c4f91 5822
mbed_official 632:7687fb9c4f91 5823 /** @addtogroup Exported_macros
mbed_official 632:7687fb9c4f91 5824 * @{
mbed_official 632:7687fb9c4f91 5825 */
mbed_official 632:7687fb9c4f91 5826
mbed_official 632:7687fb9c4f91 5827 /****************************** ADC Instances *********************************/
mbed_official 632:7687fb9c4f91 5828 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 632:7687fb9c4f91 5829 ((INSTANCE) == ADC2))
mbed_official 632:7687fb9c4f91 5830
mbed_official 632:7687fb9c4f91 5831 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
mbed_official 632:7687fb9c4f91 5832
mbed_official 632:7687fb9c4f91 5833 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
mbed_official 632:7687fb9c4f91 5834
mbed_official 632:7687fb9c4f91 5835 /****************************** CAN Instances *********************************/
mbed_official 632:7687fb9c4f91 5836 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 632:7687fb9c4f91 5837
mbed_official 632:7687fb9c4f91 5838 /****************************** COMP Instances ********************************/
mbed_official 632:7687fb9c4f91 5839 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
mbed_official 632:7687fb9c4f91 5840 ((INSTANCE) == COMP4) || \
mbed_official 632:7687fb9c4f91 5841 ((INSTANCE) == COMP6))
mbed_official 632:7687fb9c4f91 5842
mbed_official 632:7687fb9c4f91 5843 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
mbed_official 632:7687fb9c4f91 5844 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0)
mbed_official 632:7687fb9c4f91 5845
mbed_official 632:7687fb9c4f91 5846 /******************** COMP Instances with window mode capability **************/
mbed_official 632:7687fb9c4f91 5847 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0)
mbed_official 632:7687fb9c4f91 5848
mbed_official 632:7687fb9c4f91 5849 /****************************** CRC Instances *********************************/
mbed_official 632:7687fb9c4f91 5850 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 632:7687fb9c4f91 5851
mbed_official 632:7687fb9c4f91 5852 /****************************** DAC Instances *********************************/
mbed_official 632:7687fb9c4f91 5853 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
mbed_official 632:7687fb9c4f91 5854 ((INSTANCE) == DAC2))
mbed_official 632:7687fb9c4f91 5855
mbed_official 632:7687fb9c4f91 5856 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 632:7687fb9c4f91 5857 ((((INSTANCE) == DAC1) && \
mbed_official 632:7687fb9c4f91 5858 (((CHANNEL) == DAC_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 5859 ((CHANNEL) == DAC_CHANNEL_2))) \
mbed_official 632:7687fb9c4f91 5860 || \
mbed_official 632:7687fb9c4f91 5861 (((INSTANCE) == DAC2) && \
mbed_official 632:7687fb9c4f91 5862 (((CHANNEL) == DAC_CHANNEL_1))))
mbed_official 632:7687fb9c4f91 5863
mbed_official 632:7687fb9c4f91 5864 /****************************** DMA Instances *********************************/
mbed_official 632:7687fb9c4f91 5865 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 632:7687fb9c4f91 5866 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 632:7687fb9c4f91 5867 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 632:7687fb9c4f91 5868 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 632:7687fb9c4f91 5869 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 632:7687fb9c4f91 5870 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 632:7687fb9c4f91 5871 ((INSTANCE) == DMA1_Channel7))
mbed_official 632:7687fb9c4f91 5872
mbed_official 632:7687fb9c4f91 5873 /****************************** GPIO Instances ********************************/
mbed_official 632:7687fb9c4f91 5874 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 632:7687fb9c4f91 5875 ((INSTANCE) == GPIOB) || \
mbed_official 632:7687fb9c4f91 5876 ((INSTANCE) == GPIOC) || \
mbed_official 632:7687fb9c4f91 5877 ((INSTANCE) == GPIOD) || \
mbed_official 632:7687fb9c4f91 5878 ((INSTANCE) == GPIOF))
mbed_official 632:7687fb9c4f91 5879
mbed_official 632:7687fb9c4f91 5880 /****************************** I2C Instances *********************************/
mbed_official 632:7687fb9c4f91 5881 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
mbed_official 632:7687fb9c4f91 5882
mbed_official 632:7687fb9c4f91 5883 /****************************** IWDG Instances ********************************/
mbed_official 632:7687fb9c4f91 5884 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 632:7687fb9c4f91 5885
mbed_official 632:7687fb9c4f91 5886 /****************************** OPAMP Instances *******************************/
mbed_official 632:7687fb9c4f91 5887 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
mbed_official 632:7687fb9c4f91 5888
mbed_official 632:7687fb9c4f91 5889 /****************************** RTC Instances *********************************/
mbed_official 632:7687fb9c4f91 5890 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 632:7687fb9c4f91 5891
mbed_official 632:7687fb9c4f91 5892 /****************************** SMBUS Instances *******************************/
mbed_official 632:7687fb9c4f91 5893 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
mbed_official 632:7687fb9c4f91 5894
mbed_official 632:7687fb9c4f91 5895 /****************************** SPI Instances *********************************/
mbed_official 632:7687fb9c4f91 5896 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
mbed_official 632:7687fb9c4f91 5897
mbed_official 632:7687fb9c4f91 5898 /******************* TIM Instances : All supported instances ******************/
mbed_official 632:7687fb9c4f91 5899 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5900 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5901 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5902 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5903 ((INSTANCE) == TIM6) || \
mbed_official 632:7687fb9c4f91 5904 ((INSTANCE) == TIM7) || \
mbed_official 632:7687fb9c4f91 5905 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 5906 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 5907 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 5908
mbed_official 632:7687fb9c4f91 5909 /******************* TIM Instances : at least 1 capture/compare channel *******/
mbed_official 632:7687fb9c4f91 5910 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5911 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5912 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5913 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5914 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 5915 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 5916 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 5917
mbed_official 632:7687fb9c4f91 5918 /****************** TIM Instances : at least 2 capture/compare channels *******/
mbed_official 632:7687fb9c4f91 5919 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5920 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5921 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5922 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5923 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 5924
mbed_official 632:7687fb9c4f91 5925 /****************** TIM Instances : at least 3 capture/compare channels *******/
mbed_official 632:7687fb9c4f91 5926 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5927 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5928 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5929 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5930
mbed_official 632:7687fb9c4f91 5931 /****************** TIM Instances : at least 4 capture/compare channels *******/
mbed_official 632:7687fb9c4f91 5932 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5933 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5934 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5935 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5936
mbed_official 632:7687fb9c4f91 5937 /****************** TIM Instances : at least 5 capture/compare channels *******/
mbed_official 632:7687fb9c4f91 5938 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5939 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 5940
mbed_official 632:7687fb9c4f91 5941 /****************** TIM Instances : at least 6 capture/compare channels *******/
mbed_official 632:7687fb9c4f91 5942 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5943 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 5944
mbed_official 632:7687fb9c4f91 5945 /************************** TIM Instances : Advanced-control timers ***********/
mbed_official 632:7687fb9c4f91 5946
mbed_official 632:7687fb9c4f91 5947 /****************** TIM Instances : supporting clock selection ****************/
mbed_official 632:7687fb9c4f91 5948 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5949 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5950 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5951 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5952 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 5953
mbed_official 632:7687fb9c4f91 5954 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
mbed_official 632:7687fb9c4f91 5955 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5956 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5957 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5958 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5959
mbed_official 632:7687fb9c4f91 5960 /****************** TIM Instances : supporting external clock mode 2 **********/
mbed_official 632:7687fb9c4f91 5961 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5962 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5963 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5964 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5965
mbed_official 632:7687fb9c4f91 5966 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 632:7687fb9c4f91 5967 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5968 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5969 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5970 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5971 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 5972
mbed_official 632:7687fb9c4f91 5973 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 632:7687fb9c4f91 5974 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5975 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5976 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5977 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 5978 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 5979
mbed_official 632:7687fb9c4f91 5980 /****************** TIM Instances : supporting OCxREF clear *******************/
mbed_official 632:7687fb9c4f91 5981 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5982 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5983 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5984 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5985
mbed_official 632:7687fb9c4f91 5986 /****************** TIM Instances : supporting encoder interface **************/
mbed_official 632:7687fb9c4f91 5987 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5988 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5989 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 5990 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 5991
mbed_official 632:7687fb9c4f91 5992 /****************** TIM Instances : supporting Hall interface *****************/
mbed_official 632:7687fb9c4f91 5993 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5994 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 5995
mbed_official 632:7687fb9c4f91 5996 /****************** TIM Instances : supporting input XOR function *************/
mbed_official 632:7687fb9c4f91 5997 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 5998 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 5999 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6000 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6001 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 6002
mbed_official 632:7687fb9c4f91 6003 /****************** TIM Instances : supporting master mode ********************/
mbed_official 632:7687fb9c4f91 6004 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6005 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6006 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6007 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6008 ((INSTANCE) == TIM6) || \
mbed_official 632:7687fb9c4f91 6009 ((INSTANCE) == TIM7) || \
mbed_official 632:7687fb9c4f91 6010 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 6011
mbed_official 632:7687fb9c4f91 6012 /****************** TIM Instances : supporting slave mode *********************/
mbed_official 632:7687fb9c4f91 6013 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6014 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6015 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6016 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6017 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 6018
mbed_official 632:7687fb9c4f91 6019 /****************** TIM Instances : supporting synchronization ****************/
mbed_official 632:7687fb9c4f91 6020 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6021 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6022 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6023 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6024 ((INSTANCE) == TIM6) || \
mbed_official 632:7687fb9c4f91 6025 ((INSTANCE) == TIM7) || \
mbed_official 632:7687fb9c4f91 6026 ((INSTANCE) == TIM15))
mbed_official 632:7687fb9c4f91 6027
mbed_official 632:7687fb9c4f91 6028 /****************** TIM Instances : supporting 32 bits counter ****************/
mbed_official 632:7687fb9c4f91 6029 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6030 ((INSTANCE) == TIM2)
mbed_official 632:7687fb9c4f91 6031
mbed_official 632:7687fb9c4f91 6032 /****************** TIM Instances : supporting DMA burst **********************/
mbed_official 632:7687fb9c4f91 6033 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6034 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6035 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6036 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6037 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6038 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6039 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6040
mbed_official 632:7687fb9c4f91 6041 /****************** TIM Instances : supporting the break function *************/
mbed_official 632:7687fb9c4f91 6042 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6043 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6044 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6045 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6046 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6047
mbed_official 632:7687fb9c4f91 6048 /****************** TIM Instances : supporting input/output channel(s) ********/
mbed_official 632:7687fb9c4f91 6049 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 632:7687fb9c4f91 6050 ((((INSTANCE) == TIM1) && \
mbed_official 632:7687fb9c4f91 6051 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 6052 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 632:7687fb9c4f91 6053 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 632:7687fb9c4f91 6054 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 632:7687fb9c4f91 6055 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 632:7687fb9c4f91 6056 ((CHANNEL) == TIM_CHANNEL_6))) \
mbed_official 632:7687fb9c4f91 6057 || \
mbed_official 632:7687fb9c4f91 6058 (((INSTANCE) == TIM2) && \
mbed_official 632:7687fb9c4f91 6059 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 6060 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 632:7687fb9c4f91 6061 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 632:7687fb9c4f91 6062 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 632:7687fb9c4f91 6063 || \
mbed_official 632:7687fb9c4f91 6064 (((INSTANCE) == TIM3) && \
mbed_official 632:7687fb9c4f91 6065 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 6066 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 632:7687fb9c4f91 6067 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 632:7687fb9c4f91 6068 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 632:7687fb9c4f91 6069 || \
mbed_official 632:7687fb9c4f91 6070 (((INSTANCE) == TIM15) && \
mbed_official 632:7687fb9c4f91 6071 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 6072 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 632:7687fb9c4f91 6073 || \
mbed_official 632:7687fb9c4f91 6074 (((INSTANCE) == TIM16) && \
mbed_official 632:7687fb9c4f91 6075 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 632:7687fb9c4f91 6076 || \
mbed_official 632:7687fb9c4f91 6077 (((INSTANCE) == TIM17) && \
mbed_official 632:7687fb9c4f91 6078 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 632:7687fb9c4f91 6079
mbed_official 632:7687fb9c4f91 6080 /****************** TIM Instances : supporting complementary output(s) ********/
mbed_official 632:7687fb9c4f91 6081 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 632:7687fb9c4f91 6082 ((((INSTANCE) == TIM1) && \
mbed_official 632:7687fb9c4f91 6083 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 632:7687fb9c4f91 6084 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 632:7687fb9c4f91 6085 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 632:7687fb9c4f91 6086 || \
mbed_official 632:7687fb9c4f91 6087 (((INSTANCE) == TIM15) && \
mbed_official 632:7687fb9c4f91 6088 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 632:7687fb9c4f91 6089 || \
mbed_official 632:7687fb9c4f91 6090 (((INSTANCE) == TIM16) && \
mbed_official 632:7687fb9c4f91 6091 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 632:7687fb9c4f91 6092 || \
mbed_official 632:7687fb9c4f91 6093 (((INSTANCE) == TIM17) && \
mbed_official 632:7687fb9c4f91 6094 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 632:7687fb9c4f91 6095
mbed_official 632:7687fb9c4f91 6096 /****************** TIM Instances : supporting counting mode selection ********/
mbed_official 632:7687fb9c4f91 6097 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6098 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6099 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6100 ((INSTANCE) == TIM3))
mbed_official 632:7687fb9c4f91 6101
mbed_official 632:7687fb9c4f91 6102 /****************** TIM Instances : supporting repetition counter *************/
mbed_official 632:7687fb9c4f91 6103 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6104 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6105 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6106 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6107 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6108
mbed_official 632:7687fb9c4f91 6109 /****************** TIM Instances : supporting clock division *****************/
mbed_official 632:7687fb9c4f91 6110 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6111 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6112 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6113 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6114 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6115 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6116 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6117
mbed_official 632:7687fb9c4f91 6118 /****************** TIM Instances : supporting 2 break inputs *****************/
mbed_official 632:7687fb9c4f91 6119 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6120 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 6121
mbed_official 632:7687fb9c4f91 6122 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
mbed_official 632:7687fb9c4f91 6123 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6124 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 6125
mbed_official 632:7687fb9c4f91 6126 /****************** TIM Instances : supporting DMA generation on Update events*/
mbed_official 632:7687fb9c4f91 6127 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6128 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6129 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6130 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6131 ((INSTANCE) == TIM6) || \
mbed_official 632:7687fb9c4f91 6132 ((INSTANCE) == TIM7) || \
mbed_official 632:7687fb9c4f91 6133 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6134 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6135 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6136
mbed_official 632:7687fb9c4f91 6137 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
mbed_official 632:7687fb9c4f91 6138 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6139 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6140 ((INSTANCE) == TIM2) || \
mbed_official 632:7687fb9c4f91 6141 ((INSTANCE) == TIM3) || \
mbed_official 632:7687fb9c4f91 6142 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6143 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6144 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6145
mbed_official 632:7687fb9c4f91 6146 /****************** TIM Instances : supporting commutation event generation ***/
mbed_official 632:7687fb9c4f91 6147 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6148 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6149 ((INSTANCE) == TIM15) || \
mbed_official 632:7687fb9c4f91 6150 ((INSTANCE) == TIM16) || \
mbed_official 632:7687fb9c4f91 6151 ((INSTANCE) == TIM17))
mbed_official 632:7687fb9c4f91 6152
mbed_official 632:7687fb9c4f91 6153 /****************** TIM Instances : supporting remapping capability ***********/
mbed_official 632:7687fb9c4f91 6154 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 632:7687fb9c4f91 6155 (((INSTANCE) == TIM1) || \
mbed_official 632:7687fb9c4f91 6156 ((INSTANCE) == TIM16))
mbed_official 632:7687fb9c4f91 6157
mbed_official 632:7687fb9c4f91 6158 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
mbed_official 632:7687fb9c4f91 6159 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
mbed_official 632:7687fb9c4f91 6160 (((INSTANCE) == TIM1))
mbed_official 632:7687fb9c4f91 6161
mbed_official 632:7687fb9c4f91 6162 /****************************** TSC Instances *********************************/
mbed_official 632:7687fb9c4f91 6163 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 632:7687fb9c4f91 6164
mbed_official 632:7687fb9c4f91 6165 /******************** USART Instances : Synchronous mode **********************/
mbed_official 632:7687fb9c4f91 6166 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 632:7687fb9c4f91 6167 ((INSTANCE) == USART2) || \
mbed_official 632:7687fb9c4f91 6168 ((INSTANCE) == USART3))
mbed_official 632:7687fb9c4f91 6169
mbed_official 632:7687fb9c4f91 6170 /****************** USART Instances : Auto Baud Rate detection ****************/
mbed_official 632:7687fb9c4f91 6171 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6172
mbed_official 632:7687fb9c4f91 6173 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 632:7687fb9c4f91 6174 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 632:7687fb9c4f91 6175 ((INSTANCE) == USART2) || \
mbed_official 632:7687fb9c4f91 6176 ((INSTANCE) == USART3))
mbed_official 632:7687fb9c4f91 6177
mbed_official 632:7687fb9c4f91 6178 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 632:7687fb9c4f91 6179 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 632:7687fb9c4f91 6180 ((INSTANCE) == USART2) || \
mbed_official 632:7687fb9c4f91 6181 ((INSTANCE) == USART3))
mbed_official 632:7687fb9c4f91 6182
mbed_official 632:7687fb9c4f91 6183 /******************** UART Instances : LIN mode **********************/
mbed_official 632:7687fb9c4f91 6184 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6185
mbed_official 632:7687fb9c4f91 6186 /******************** UART Instances : Wake-up from Stop mode **********************/
mbed_official 632:7687fb9c4f91 6187 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6188
mbed_official 632:7687fb9c4f91 6189 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 632:7687fb9c4f91 6190 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 632:7687fb9c4f91 6191 ((INSTANCE) == USART2) || \
mbed_official 632:7687fb9c4f91 6192 ((INSTANCE) == USART3))
mbed_official 632:7687fb9c4f91 6193
mbed_official 632:7687fb9c4f91 6194 /****************** UART Instances : Auto Baud Rate detection *****************/
mbed_official 632:7687fb9c4f91 6195 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6196
mbed_official 632:7687fb9c4f91 6197 /****************** UART Instances : Driver Enable ****************************/
mbed_official 632:7687fb9c4f91 6198 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 632:7687fb9c4f91 6199 ((INSTANCE) == USART2) || \
mbed_official 632:7687fb9c4f91 6200 ((INSTANCE) == USART3))
mbed_official 632:7687fb9c4f91 6201
mbed_official 632:7687fb9c4f91 6202 /********************* UART Instances : Smard card mode ***********************/
mbed_official 632:7687fb9c4f91 6203 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6204
mbed_official 632:7687fb9c4f91 6205 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 632:7687fb9c4f91 6206 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 632:7687fb9c4f91 6207
mbed_official 632:7687fb9c4f91 6208 /****************************** WWDG Instances ********************************/
mbed_official 632:7687fb9c4f91 6209 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 632:7687fb9c4f91 6210
mbed_official 632:7687fb9c4f91 6211 /**
mbed_official 632:7687fb9c4f91 6212 * @}
mbed_official 632:7687fb9c4f91 6213 */
mbed_official 632:7687fb9c4f91 6214
mbed_official 632:7687fb9c4f91 6215
mbed_official 632:7687fb9c4f91 6216 /******************************************************************************/
mbed_official 632:7687fb9c4f91 6217 /* For a painless codes migration between the STM32F3xx device product */
mbed_official 632:7687fb9c4f91 6218 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 632:7687fb9c4f91 6219 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 632:7687fb9c4f91 6220 /* No need to update developed interrupt code when moving across */
mbed_official 632:7687fb9c4f91 6221 /* product lines within the same STM32F3 Family */
mbed_official 632:7687fb9c4f91 6222 /******************************************************************************/
mbed_official 632:7687fb9c4f91 6223
mbed_official 632:7687fb9c4f91 6224 /* Aliases for __IRQn */
mbed_official 632:7687fb9c4f91 6225
mbed_official 632:7687fb9c4f91 6226 #define ADC1_IRQn ADC1_2_IRQn
mbed_official 632:7687fb9c4f91 6227 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
mbed_official 632:7687fb9c4f91 6228 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
mbed_official 632:7687fb9c4f91 6229 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 632:7687fb9c4f91 6230 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
mbed_official 632:7687fb9c4f91 6231 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 632:7687fb9c4f91 6232 #define COMP_IRQn COMP2_IRQn
mbed_official 632:7687fb9c4f91 6233 #define COMP1_2_3_IRQn COMP2_IRQn
mbed_official 632:7687fb9c4f91 6234 #define COMP1_2_IRQn COMP2_IRQn
mbed_official 632:7687fb9c4f91 6235 #define COMP4_5_6_IRQn COMP4_6_IRQn
mbed_official 632:7687fb9c4f91 6236 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn
mbed_official 632:7687fb9c4f91 6237
mbed_official 632:7687fb9c4f91 6238 /* Aliases for __IRQHandler */
mbed_official 632:7687fb9c4f91 6239 #define ADC1_IRQHandler ADC1_2_IRQHandler
mbed_official 632:7687fb9c4f91 6240 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
mbed_official 632:7687fb9c4f91 6241 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
mbed_official 632:7687fb9c4f91 6242 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 632:7687fb9c4f91 6243 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 632:7687fb9c4f91 6244 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 632:7687fb9c4f91 6245 #define COMP_IRQHandler COMP2_IRQHandler
mbed_official 632:7687fb9c4f91 6246 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
mbed_official 632:7687fb9c4f91 6247 #define COMP1_2_IRQHandler COMP2_IRQHandler
mbed_official 632:7687fb9c4f91 6248 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
mbed_official 632:7687fb9c4f91 6249 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
mbed_official 632:7687fb9c4f91 6250
mbed_official 632:7687fb9c4f91 6251 #ifdef __cplusplus
mbed_official 632:7687fb9c4f91 6252 }
mbed_official 632:7687fb9c4f91 6253 #endif /* __cplusplus */
mbed_official 632:7687fb9c4f91 6254
mbed_official 632:7687fb9c4f91 6255 #endif /* __STM32F303x8_H */
mbed_official 632:7687fb9c4f91 6256
mbed_official 632:7687fb9c4f91 6257 /**
mbed_official 632:7687fb9c4f91 6258 * @}
mbed_official 632:7687fb9c4f91 6259 */
mbed_official 632:7687fb9c4f91 6260
mbed_official 632:7687fb9c4f91 6261 /**
mbed_official 632:7687fb9c4f91 6262 * @}
mbed_official 632:7687fb9c4f91 6263 */
mbed_official 632:7687fb9c4f91 6264
mbed_official 632:7687fb9c4f91 6265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/