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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@274:6937b19af361, 2014-08-06 (annotated)

Committer:
mbed_official
Date:
Wed Aug 06 08:15:07 2014 +0100
Revision:
274:6937b19af361
Parent:
226:b062af740e40
Child:
369:2e96f1b71984
Synchronized with git revision 5b145e4f6c509376173c3ea2aa35a6da879a2124



Full URL: https://github.com/mbedmicro/mbed/commit/5b145e4f6c509376173c3ea2aa35a6da879a2124/



[TARGET_LPC11UXX] PeripheralNames.h and PinMap definitions separation for LPC11UXX platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_rcc_ex.h
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V1.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief Header file of RCC HAL Extension module.
mbed_official 87:085cde657901 8 ******************************************************************************
mbed_official 87:085cde657901 9 * @attention
mbed_official 87:085cde657901 10 *
mbed_official 87:085cde657901 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 14 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 16 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 19 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 21 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 22 * without specific prior written permission.
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 ******************************************************************************
mbed_official 87:085cde657901 36 */
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 87:085cde657901 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
mbed_official 87:085cde657901 40 #define __STM32F4xx_HAL_RCC_EX_H
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 #ifdef __cplusplus
mbed_official 87:085cde657901 43 extern "C" {
mbed_official 87:085cde657901 44 #endif
mbed_official 87:085cde657901 45
mbed_official 87:085cde657901 46 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 47 #include "stm32f4xx_hal_def.h"
mbed_official 87:085cde657901 48
mbed_official 87:085cde657901 49 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 50 * @{
mbed_official 87:085cde657901 51 */
mbed_official 87:085cde657901 52
mbed_official 87:085cde657901 53 /** @addtogroup RCCEx
mbed_official 87:085cde657901 54 * @{
mbed_official 87:085cde657901 55 */
mbed_official 87:085cde657901 56
mbed_official 87:085cde657901 57 /* Exported types ------------------------------------------------------------*/
mbed_official 87:085cde657901 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 59 /**
mbed_official 87:085cde657901 60 * @brief PLLI2S Clock structure definition
mbed_official 87:085cde657901 61 */
mbed_official 87:085cde657901 62 typedef struct
mbed_official 87:085cde657901 63 {
mbed_official 226:b062af740e40 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 226:b062af740e40 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 67
mbed_official 226:b062af740e40 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official 226:b062af740e40 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 71
mbed_official 87:085cde657901 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 226:b062af740e40 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 87:085cde657901 75 }RCC_PLLI2SInitTypeDef;
mbed_official 87:085cde657901 76
mbed_official 87:085cde657901 77 /**
mbed_official 87:085cde657901 78 * @brief PLLSAI Clock structure definition
mbed_official 87:085cde657901 79 */
mbed_official 87:085cde657901 80 typedef struct
mbed_official 87:085cde657901 81 {
mbed_official 87:085cde657901 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 226:b062af740e40 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 85
mbed_official 87:085cde657901 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 226:b062af740e40 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 89
mbed_official 87:085cde657901 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
mbed_official 226:b062af740e40 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
mbed_official 87:085cde657901 93
mbed_official 87:085cde657901 94 }RCC_PLLSAIInitTypeDef;
mbed_official 87:085cde657901 95 /**
mbed_official 87:085cde657901 96 * @brief RCC extended clocks structure definition
mbed_official 87:085cde657901 97 */
mbed_official 87:085cde657901 98 typedef struct
mbed_official 87:085cde657901 99 {
mbed_official 87:085cde657901 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official 87:085cde657901 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official 87:085cde657901 102
mbed_official 226:b062af740e40 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official 87:085cde657901 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 105
mbed_official 226:b062af740e40 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official 87:085cde657901 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 108
mbed_official 226:b062af740e40 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 87:085cde657901 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 87:085cde657901 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 87:085cde657901 112
mbed_official 87:085cde657901 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 87:085cde657901 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 87:085cde657901 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official 87:085cde657901 116
mbed_official 87:085cde657901 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
mbed_official 87:085cde657901 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
mbed_official 87:085cde657901 119
mbed_official 226:b062af740e40 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official 87:085cde657901 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official 87:085cde657901 122
mbed_official 226:b062af740e40 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
mbed_official 87:085cde657901 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
mbed_official 87:085cde657901 125
mbed_official 87:085cde657901 126 }RCC_PeriphCLKInitTypeDef;
mbed_official 87:085cde657901 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 128
mbed_official 87:085cde657901 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
mbed_official 87:085cde657901 130 /**
mbed_official 87:085cde657901 131 * @brief PLLI2S Clock structure definition
mbed_official 87:085cde657901 132 */
mbed_official 87:085cde657901 133 typedef struct
mbed_official 87:085cde657901 134 {
mbed_official 226:b062af740e40 135 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 87:085cde657901 136 This parameter must be a number between Min_Data = 192 and Max_Data = 432
mbed_official 87:085cde657901 137 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 138
mbed_official 226:b062af740e40 139 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official 226:b062af740e40 140 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 141 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 142
mbed_official 87:085cde657901 143 }RCC_PLLI2SInitTypeDef;
mbed_official 87:085cde657901 144
mbed_official 87:085cde657901 145
mbed_official 87:085cde657901 146 /**
mbed_official 87:085cde657901 147 * @brief RCC extended clocks structure definition
mbed_official 87:085cde657901 148 */
mbed_official 87:085cde657901 149 typedef struct
mbed_official 87:085cde657901 150 {
mbed_official 87:085cde657901 151 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official 87:085cde657901 152 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official 87:085cde657901 153
mbed_official 226:b062af740e40 154 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official 87:085cde657901 155 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 156
mbed_official 226:b062af740e40 157 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official 87:085cde657901 158 This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official 87:085cde657901 159
mbed_official 87:085cde657901 160 }RCC_PeriphCLKInitTypeDef;
mbed_official 87:085cde657901 161 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
mbed_official 87:085cde657901 162 /* Exported constants --------------------------------------------------------*/
mbed_official 87:085cde657901 163 /** @defgroup RCCEx_Exported_Constants
mbed_official 87:085cde657901 164 * @{
mbed_official 87:085cde657901 165 */
mbed_official 87:085cde657901 166
mbed_official 87:085cde657901 167 /** @defgroup RCCEx_Periph_Clock_Selection
mbed_official 87:085cde657901 168 * @{
mbed_official 87:085cde657901 169 */
mbed_official 87:085cde657901 170 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 171 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official 87:085cde657901 172 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
mbed_official 87:085cde657901 173 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
mbed_official 87:085cde657901 174 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official 87:085cde657901 175 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official 87:085cde657901 176 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official 87:085cde657901 177 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
mbed_official 87:085cde657901 178 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 179
mbed_official 87:085cde657901 180 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
mbed_official 87:085cde657901 181 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official 87:085cde657901 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
mbed_official 87:085cde657901 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
mbed_official 87:085cde657901 184 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
mbed_official 87:085cde657901 185
mbed_official 87:085cde657901 186 /**
mbed_official 87:085cde657901 187 * @}
mbed_official 87:085cde657901 188 */
mbed_official 87:085cde657901 189
mbed_official 87:085cde657901 190 /** @defgroup RCCEx_BitAddress_AliasRegion
mbed_official 87:085cde657901 191 * @brief RCC registers bit address in the alias region
mbed_official 87:085cde657901 192 * @{
mbed_official 87:085cde657901 193 */
mbed_official 87:085cde657901 194 /* --- CR Register ---*/
mbed_official 87:085cde657901 195 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 196 /* Alias word address of PLLSAION bit */
mbed_official 87:085cde657901 197 #define PLLSAION_BitNumber 0x1C
mbed_official 87:085cde657901 198 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
mbed_official 87:085cde657901 199
mbed_official 87:085cde657901 200 /* --- DCKCFGR Register ---*/
mbed_official 87:085cde657901 201 /* Alias word address of TIMPRE bit */
mbed_official 87:085cde657901 202 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
mbed_official 87:085cde657901 203 #define TIMPRE_BitNumber 0x18
mbed_official 87:085cde657901 204 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
mbed_official 87:085cde657901 205 /**
mbed_official 87:085cde657901 206 * @}
mbed_official 87:085cde657901 207 */
mbed_official 87:085cde657901 208
mbed_official 87:085cde657901 209 /** @defgroup RCCEx_PLLI2S_Clock_Source
mbed_official 87:085cde657901 210 * @{
mbed_official 87:085cde657901 211 */
mbed_official 87:085cde657901 212 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 87:085cde657901 213 /**
mbed_official 87:085cde657901 214 * @}
mbed_official 87:085cde657901 215 */
mbed_official 87:085cde657901 216
mbed_official 87:085cde657901 217 /** @defgroup RCCEx_PLLSAI_Clock_Source
mbed_official 87:085cde657901 218 * @{
mbed_official 87:085cde657901 219 */
mbed_official 87:085cde657901 220 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 87:085cde657901 221 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 87:085cde657901 222 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official 87:085cde657901 223 /**
mbed_official 87:085cde657901 224 * @}
mbed_official 87:085cde657901 225 */
mbed_official 87:085cde657901 226
mbed_official 87:085cde657901 227 /** @defgroup RCCEx_PLLSAI_DIVQ
mbed_official 87:085cde657901 228 * @{
mbed_official 87:085cde657901 229 */
mbed_official 87:085cde657901 230 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 87:085cde657901 231 /**
mbed_official 87:085cde657901 232 * @}
mbed_official 87:085cde657901 233 */
mbed_official 87:085cde657901 234
mbed_official 87:085cde657901 235 /** @defgroup RCCEx_PLLI2S_DIVQ
mbed_official 87:085cde657901 236 * @{
mbed_official 87:085cde657901 237 */
mbed_official 87:085cde657901 238 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 87:085cde657901 239
mbed_official 87:085cde657901 240 /**
mbed_official 87:085cde657901 241 * @}
mbed_official 87:085cde657901 242 */
mbed_official 87:085cde657901 243
mbed_official 87:085cde657901 244 /** @defgroup RCCEx_PLLSAI_DIVR
mbed_official 87:085cde657901 245 * @{
mbed_official 87:085cde657901 246 */
mbed_official 87:085cde657901 247 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 248 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
mbed_official 87:085cde657901 249 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
mbed_official 87:085cde657901 250 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
mbed_official 87:085cde657901 251 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
mbed_official 87:085cde657901 252 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
mbed_official 87:085cde657901 253 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
mbed_official 87:085cde657901 254 ((VALUE) == RCC_PLLSAIDIVR_16))
mbed_official 87:085cde657901 255
mbed_official 87:085cde657901 256 /**
mbed_official 87:085cde657901 257 * @}
mbed_official 87:085cde657901 258 */
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
mbed_official 87:085cde657901 261 * @{
mbed_official 87:085cde657901 262 */
mbed_official 87:085cde657901 263 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 87:085cde657901 264 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
mbed_official 87:085cde657901 265 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
mbed_official 87:085cde657901 266 /**
mbed_official 87:085cde657901 267 * @}
mbed_official 87:085cde657901 268 */
mbed_official 87:085cde657901 269
mbed_official 87:085cde657901 270 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
mbed_official 87:085cde657901 271 * @{
mbed_official 87:085cde657901 272 */
mbed_official 87:085cde657901 273 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 87:085cde657901 274 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
mbed_official 87:085cde657901 275 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
mbed_official 87:085cde657901 276 /**
mbed_official 87:085cde657901 277 * @}
mbed_official 87:085cde657901 278 */
mbed_official 87:085cde657901 279
mbed_official 87:085cde657901 280 /** @defgroup RCCEx_TIM_PRescaler_Selection
mbed_official 87:085cde657901 281 * @{
mbed_official 87:085cde657901 282 */
mbed_official 87:085cde657901 283 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
mbed_official 87:085cde657901 284 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
mbed_official 87:085cde657901 285 /**
mbed_official 87:085cde657901 286 * @}
mbed_official 87:085cde657901 287 */
mbed_official 87:085cde657901 288 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 289 /**
mbed_official 87:085cde657901 290 * @}
mbed_official 87:085cde657901 291 */
mbed_official 87:085cde657901 292
mbed_official 87:085cde657901 293 /**
mbed_official 87:085cde657901 294 * @}
mbed_official 87:085cde657901 295 */
mbed_official 87:085cde657901 296
mbed_official 87:085cde657901 297 /* Exported macro ------------------------------------------------------------*/
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 /** @brief Enables or disables the AHB1 peripheral clock.
mbed_official 87:085cde657901 300 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 301 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 302 * using it.
mbed_official 87:085cde657901 303 */
mbed_official 87:085cde657901 304
mbed_official 87:085cde657901 305 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 306 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
mbed_official 87:085cde657901 307 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
mbed_official 87:085cde657901 308 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
mbed_official 87:085cde657901 309 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
mbed_official 87:085cde657901 310 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
mbed_official 87:085cde657901 311 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
mbed_official 87:085cde657901 312 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 87:085cde657901 313 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
mbed_official 87:085cde657901 314 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 87:085cde657901 315
mbed_official 87:085cde657901 316 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official 87:085cde657901 317 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official 87:085cde657901 318 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official 87:085cde657901 319 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official 87:085cde657901 320 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official 87:085cde657901 321 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official 87:085cde657901 322 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 87:085cde657901 323 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official 87:085cde657901 324 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 87:085cde657901 325 #endif /* !(STM32F401xC && STM32F401xE) */
mbed_official 87:085cde657901 326
mbed_official 87:085cde657901 327 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 328 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
mbed_official 87:085cde657901 329 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
mbed_official 87:085cde657901 330 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
mbed_official 87:085cde657901 331
mbed_official 87:085cde657901 332 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
mbed_official 87:085cde657901 333 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
mbed_official 87:085cde657901 334 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
mbed_official 87:085cde657901 335 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
mbed_official 87:085cde657901 336
mbed_official 87:085cde657901 337 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 338 /**
mbed_official 87:085cde657901 339 * @brief Enable ETHERNET clock.
mbed_official 87:085cde657901 340 */
mbed_official 87:085cde657901 341 #define __ETH_CLK_ENABLE() do { \
mbed_official 87:085cde657901 342 __ETHMAC_CLK_ENABLE(); \
mbed_official 87:085cde657901 343 __ETHMACTX_CLK_ENABLE(); \
mbed_official 87:085cde657901 344 __ETHMACRX_CLK_ENABLE(); \
mbed_official 87:085cde657901 345 } while(0)
mbed_official 87:085cde657901 346
mbed_official 87:085cde657901 347 /**
mbed_official 87:085cde657901 348 * @brief Disable ETHERNET clock.
mbed_official 87:085cde657901 349 */
mbed_official 87:085cde657901 350 #define __ETH_CLK_DISABLE() do { \
mbed_official 87:085cde657901 351 __ETHMACTX_CLK_DISABLE(); \
mbed_official 87:085cde657901 352 __ETHMACRX_CLK_DISABLE(); \
mbed_official 87:085cde657901 353 __ETHMAC_CLK_DISABLE(); \
mbed_official 87:085cde657901 354 } while(0)
mbed_official 87:085cde657901 355 #endif /* !(STM32F401xC && STM32F401xE) */
mbed_official 87:085cde657901 356
mbed_official 87:085cde657901 357 /** @brief Enable or disable the AHB2 peripheral clock.
mbed_official 87:085cde657901 358 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 359 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 360 * using it.
mbed_official 87:085cde657901 361 */
mbed_official 87:085cde657901 362 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 363 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
mbed_official 87:085cde657901 364 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official 87:085cde657901 365 #endif /* !(STM32F401xC && STM32F401xE) */
mbed_official 87:085cde657901 366
mbed_official 87:085cde657901 367 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 368 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
mbed_official 87:085cde657901 369 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
mbed_official 87:085cde657901 370
mbed_official 87:085cde657901 371 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official 87:085cde657901 372 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official 87:085cde657901 373
mbed_official 87:085cde657901 374 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
mbed_official 87:085cde657901 375
mbed_official 87:085cde657901 376 /** @brief Enables or disables the AHB3 peripheral clock.
mbed_official 87:085cde657901 377 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 378 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 379 * using it.
mbed_official 87:085cde657901 380 */
mbed_official 87:085cde657901 381 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 382 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
mbed_official 87:085cde657901 383 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
mbed_official 87:085cde657901 384 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 385
mbed_official 87:085cde657901 386 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 387 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
mbed_official 87:085cde657901 388 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official 87:085cde657901 389 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391
mbed_official 87:085cde657901 392 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official 87:085cde657901 393 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 394 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 395 * using it.
mbed_official 87:085cde657901 396 */
mbed_official 87:085cde657901 397 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 398 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
mbed_official 87:085cde657901 399 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
mbed_official 87:085cde657901 400 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
mbed_official 87:085cde657901 401 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
mbed_official 87:085cde657901 402 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
mbed_official 87:085cde657901 403 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 404 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
mbed_official 87:085cde657901 405 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
mbed_official 87:085cde657901 406 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
mbed_official 87:085cde657901 407 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
mbed_official 87:085cde657901 408 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
mbed_official 87:085cde657901 409 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
mbed_official 87:085cde657901 410
mbed_official 87:085cde657901 411 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official 87:085cde657901 412 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official 87:085cde657901 413 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official 87:085cde657901 414 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official 87:085cde657901 415 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official 87:085cde657901 416 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 417 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official 87:085cde657901 418 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official 87:085cde657901 419 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official 87:085cde657901 420 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official 87:085cde657901 421 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official 87:085cde657901 422 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official 87:085cde657901 423 #endif /* !(STM32F401xC && STM32F401xE) */
mbed_official 87:085cde657901 424
mbed_official 87:085cde657901 425 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 426 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
mbed_official 87:085cde657901 427 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
mbed_official 87:085cde657901 428
mbed_official 87:085cde657901 429 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
mbed_official 87:085cde657901 430 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
mbed_official 87:085cde657901 431 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
mbed_official 87:085cde657901 432
mbed_official 87:085cde657901 433 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 87:085cde657901 434 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 435 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 436 * using it.
mbed_official 87:085cde657901 437 */
mbed_official 87:085cde657901 438 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
mbed_official 87:085cde657901 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
mbed_official 87:085cde657901 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
mbed_official 87:085cde657901 442
mbed_official 87:085cde657901 443 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official 87:085cde657901 444 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official 87:085cde657901 445 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official 87:085cde657901 446 #endif /* !(STM32F401xC && STM32F401xE) */
mbed_official 87:085cde657901 447
mbed_official 87:085cde657901 448 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 449 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
mbed_official 87:085cde657901 450 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
mbed_official 87:085cde657901 451 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
mbed_official 87:085cde657901 452 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
mbed_official 87:085cde657901 453
mbed_official 87:085cde657901 454 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official 87:085cde657901 455 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
mbed_official 87:085cde657901 456 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official 87:085cde657901 457 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official 87:085cde657901 458 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 459
mbed_official 87:085cde657901 460 /** @brief Force or release AHB1 peripheral reset.
mbed_official 87:085cde657901 461 */
mbed_official 87:085cde657901 462 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 463 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
mbed_official 87:085cde657901 464 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
mbed_official 87:085cde657901 465 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
mbed_official 87:085cde657901 466 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
mbed_official 87:085cde657901 467 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
mbed_official 87:085cde657901 468
mbed_official 87:085cde657901 469 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official 87:085cde657901 470 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official 87:085cde657901 471 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official 87:085cde657901 472 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official 87:085cde657901 473 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official 87:085cde657901 474 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 475
mbed_official 87:085cde657901 476 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 477 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
mbed_official 87:085cde657901 478 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
mbed_official 87:085cde657901 479 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
mbed_official 87:085cde657901 480
mbed_official 87:085cde657901 481 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
mbed_official 87:085cde657901 482 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
mbed_official 87:085cde657901 483 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
mbed_official 87:085cde657901 484 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 485
mbed_official 87:085cde657901 486 /** @brief Force or release AHB2 peripheral reset.
mbed_official 87:085cde657901 487 */
mbed_official 87:085cde657901 488 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 489 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
mbed_official 87:085cde657901 490 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official 87:085cde657901 491 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 492
mbed_official 87:085cde657901 493 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 494 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
mbed_official 87:085cde657901 495 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
mbed_official 87:085cde657901 496
mbed_official 87:085cde657901 497 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official 87:085cde657901 498 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official 87:085cde657901 499
mbed_official 87:085cde657901 500 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
mbed_official 87:085cde657901 501
mbed_official 87:085cde657901 502 /** @brief Force or release AHB3 peripheral reset
mbed_official 87:085cde657901 503 */
mbed_official 87:085cde657901 504 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 505 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
mbed_official 87:085cde657901 506 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
mbed_official 87:085cde657901 507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 508
mbed_official 87:085cde657901 509 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 510 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
mbed_official 87:085cde657901 511 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official 87:085cde657901 512 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 513
mbed_official 87:085cde657901 514 /** @brief Force or release APB1 peripheral reset.
mbed_official 87:085cde657901 515 */
mbed_official 87:085cde657901 516 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 517 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
mbed_official 87:085cde657901 518 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
mbed_official 87:085cde657901 519 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
mbed_official 87:085cde657901 520 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
mbed_official 87:085cde657901 521 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
mbed_official 87:085cde657901 522 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
mbed_official 87:085cde657901 523 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
mbed_official 87:085cde657901 524 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
mbed_official 87:085cde657901 525 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
mbed_official 87:085cde657901 526 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
mbed_official 87:085cde657901 527 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
mbed_official 87:085cde657901 528
mbed_official 87:085cde657901 529 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official 87:085cde657901 530 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official 87:085cde657901 531 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official 87:085cde657901 532 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official 87:085cde657901 533 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official 87:085cde657901 534 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official 87:085cde657901 535 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official 87:085cde657901 536 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official 87:085cde657901 537 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official 87:085cde657901 538 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official 87:085cde657901 539 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official 87:085cde657901 540 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 541
mbed_official 87:085cde657901 542 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 543 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
mbed_official 87:085cde657901 544 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
mbed_official 87:085cde657901 545
mbed_official 87:085cde657901 546 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
mbed_official 87:085cde657901 547 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
mbed_official 87:085cde657901 548 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 549
mbed_official 87:085cde657901 550 /** @brief Force or release APB2 peripheral reset.
mbed_official 87:085cde657901 551 */
mbed_official 87:085cde657901 552 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 553 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
mbed_official 87:085cde657901 554 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official 87:085cde657901 555 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 556
mbed_official 87:085cde657901 557 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 558 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
mbed_official 87:085cde657901 559 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
mbed_official 87:085cde657901 560 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
mbed_official 87:085cde657901 561 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
mbed_official 87:085cde657901 562
mbed_official 87:085cde657901 563 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official 87:085cde657901 564 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
mbed_official 87:085cde657901 565 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official 87:085cde657901 566 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official 87:085cde657901 567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 568
mbed_official 87:085cde657901 569
mbed_official 87:085cde657901 570 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 572 * power consumption.
mbed_official 87:085cde657901 573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 574 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 575 */
mbed_official 87:085cde657901 576 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 577 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 87:085cde657901 578 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 87:085cde657901 579 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official 87:085cde657901 580 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 87:085cde657901 581 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 87:085cde657901 582 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 87:085cde657901 583 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 87:085cde657901 584 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 87:085cde657901 585 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 87:085cde657901 586 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 87:085cde657901 587
mbed_official 87:085cde657901 588 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 87:085cde657901 589 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 87:085cde657901 590 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official 87:085cde657901 591 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 87:085cde657901 592 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 87:085cde657901 593 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 87:085cde657901 594 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 87:085cde657901 595 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 87:085cde657901 596 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 87:085cde657901 597 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 87:085cde657901 598 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 599
mbed_official 87:085cde657901 600 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 601 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 87:085cde657901 602 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 87:085cde657901 603 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
mbed_official 87:085cde657901 604 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 87:085cde657901 605
mbed_official 87:085cde657901 606 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 87:085cde657901 607 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 87:085cde657901 608 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 87:085cde657901 609 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 610
mbed_official 87:085cde657901 611 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 612 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 613 * power consumption.
mbed_official 87:085cde657901 614 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 615 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 616 */
mbed_official 87:085cde657901 617 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 618 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
mbed_official 87:085cde657901 619 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official 87:085cde657901 620 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 623 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official 87:085cde657901 624 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
mbed_official 87:085cde657901 625
mbed_official 87:085cde657901 626 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official 87:085cde657901 627 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official 87:085cde657901 628
mbed_official 87:085cde657901 629 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
mbed_official 87:085cde657901 630
mbed_official 87:085cde657901 631 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 633 * power consumption.
mbed_official 87:085cde657901 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 636 */
mbed_official 87:085cde657901 637 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 638 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
mbed_official 87:085cde657901 639 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
mbed_official 87:085cde657901 640 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 641
mbed_official 87:085cde657901 642 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 643 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
mbed_official 87:085cde657901 644 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official 87:085cde657901 645 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 646
mbed_official 87:085cde657901 647 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 648 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 649 * power consumption.
mbed_official 87:085cde657901 650 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 651 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 652 */
mbed_official 87:085cde657901 653 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 654 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
mbed_official 87:085cde657901 655 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
mbed_official 87:085cde657901 656 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
mbed_official 87:085cde657901 657 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
mbed_official 87:085cde657901 658 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
mbed_official 87:085cde657901 659 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
mbed_official 87:085cde657901 660 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
mbed_official 87:085cde657901 661 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
mbed_official 87:085cde657901 662 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
mbed_official 87:085cde657901 663 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
mbed_official 87:085cde657901 664 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
mbed_official 87:085cde657901 665
mbed_official 87:085cde657901 666 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official 87:085cde657901 667 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official 87:085cde657901 668 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official 87:085cde657901 669 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official 87:085cde657901 670 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official 87:085cde657901 671 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official 87:085cde657901 672 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official 87:085cde657901 673 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official 87:085cde657901 674 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official 87:085cde657901 675 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official 87:085cde657901 676 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official 87:085cde657901 677 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 678
mbed_official 87:085cde657901 679 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 680 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
mbed_official 87:085cde657901 681 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
mbed_official 87:085cde657901 682
mbed_official 87:085cde657901 683 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official 87:085cde657901 684 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
mbed_official 87:085cde657901 685 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 686
mbed_official 87:085cde657901 687 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 688 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 689 * power consumption.
mbed_official 87:085cde657901 690 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 691 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 692 */
mbed_official 87:085cde657901 693 #if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official 87:085cde657901 694 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
mbed_official 87:085cde657901 695 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
mbed_official 87:085cde657901 696 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
mbed_official 87:085cde657901 697
mbed_official 87:085cde657901 698 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official 87:085cde657901 699 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official 87:085cde657901 700 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official 87:085cde657901 701 #endif /* !STM32F401xC && STM32F401xE */
mbed_official 87:085cde657901 702
mbed_official 87:085cde657901 703 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 704 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
mbed_official 87:085cde657901 705 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
mbed_official 87:085cde657901 706 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
mbed_official 87:085cde657901 707 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
mbed_official 87:085cde657901 708
mbed_official 87:085cde657901 709 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official 87:085cde657901 710 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
mbed_official 87:085cde657901 711 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official 87:085cde657901 712 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official 87:085cde657901 713 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 714
mbed_official 87:085cde657901 715 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 716
mbed_official 87:085cde657901 717 /** @brief Macro to configure the Timers clocks prescalers
mbed_official 87:085cde657901 718 * @note This feature is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 719 * @param __PRESC__ : specifies the Timers clocks prescalers selection
mbed_official 87:085cde657901 720 * This parameter can be one of the following values:
mbed_official 87:085cde657901 721 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
mbed_official 87:085cde657901 722 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
mbed_official 87:085cde657901 723 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
mbed_official 87:085cde657901 724 * division by 4 or more.
mbed_official 87:085cde657901 725 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
mbed_official 87:085cde657901 726 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
mbed_official 87:085cde657901 727 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
mbed_official 87:085cde657901 728 * to division by 8 or more.
mbed_official 87:085cde657901 729 */
mbed_official 87:085cde657901 730 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
mbed_official 87:085cde657901 731
mbed_official 87:085cde657901 732 /** @brief Macros to Enable or Disable the PLLISAI.
mbed_official 87:085cde657901 733 * @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 734 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 735 */
mbed_official 87:085cde657901 736 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
mbed_official 87:085cde657901 737 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
mbed_official 87:085cde657901 738
mbed_official 87:085cde657901 739 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official 87:085cde657901 740 * @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 741 * @note This function must be used only when the PLLSAI is disabled.
mbed_official 87:085cde657901 742 * @note PLLSAI clock source is common with the main PLL (configured in
mbed_official 87:085cde657901 743 * RCC_PLLConfig function )
mbed_official 87:085cde657901 744 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official 87:085cde657901 745 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 746 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 747 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 87:085cde657901 748 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
mbed_official 87:085cde657901 749 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 750 * @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official 87:085cde657901 751 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 752 */
mbed_official 87:085cde657901 753 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
mbed_official 87:085cde657901 754
mbed_official 87:085cde657901 755 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
mbed_official 87:085cde657901 756 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 87:085cde657901 757 * @note PLLI2S clock source is common with the main PLL (configured in
mbed_official 87:085cde657901 758 * HAL_RCC_ClockConfig() API)
mbed_official 87:085cde657901 759 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 87:085cde657901 760 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 761 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 762 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 87:085cde657901 763 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
mbed_official 87:085cde657901 764 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 765 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
mbed_official 87:085cde657901 766 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
mbed_official 87:085cde657901 767 * @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official 87:085cde657901 768 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 769 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official 87:085cde657901 770 * on the I2S clock frequency.
mbed_official 87:085cde657901 771 */
mbed_official 87:085cde657901 772 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
mbed_official 87:085cde657901 773
mbed_official 87:085cde657901 774 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
mbed_official 87:085cde657901 775 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 776 * @note This function must be called before enabling the PLLI2S.
mbed_official 87:085cde657901 777 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
mbed_official 87:085cde657901 778 * This parameter must be a number between 1 and 32.
mbed_official 87:085cde657901 779 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
mbed_official 87:085cde657901 780 */
mbed_official 87:085cde657901 781 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
mbed_official 87:085cde657901 782
mbed_official 87:085cde657901 783 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
mbed_official 87:085cde657901 784 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 785 * @note This function must be called before enabling the PLLSAI.
mbed_official 87:085cde657901 786 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
mbed_official 87:085cde657901 787 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
mbed_official 87:085cde657901 788 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
mbed_official 87:085cde657901 789 */
mbed_official 87:085cde657901 790 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
mbed_official 87:085cde657901 791
mbed_official 87:085cde657901 792 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
mbed_official 87:085cde657901 793 *
mbed_official 87:085cde657901 794 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 795 * @note This function must be called before enabling the PLLSAI.
mbed_official 87:085cde657901 796 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official 87:085cde657901 797 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
mbed_official 87:085cde657901 798 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
mbed_official 87:085cde657901 799 */
mbed_official 87:085cde657901 800 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
mbed_official 87:085cde657901 801
mbed_official 87:085cde657901 802 /** @brief Macro to configure SAI1BlockA clock source selection.
mbed_official 87:085cde657901 803 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 804 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 87:085cde657901 805 * the SAI clock.
mbed_official 87:085cde657901 806 * @param __SOURCE__: specifies the SAI Block A clock source.
mbed_official 87:085cde657901 807 * This parameter can be one of the following values:
mbed_official 87:085cde657901 808 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 87:085cde657901 809 * as SAI1 Block A clock.
mbed_official 87:085cde657901 810 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 87:085cde657901 811 * as SAI1 Block A clock.
mbed_official 87:085cde657901 812 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official 87:085cde657901 813 * used as SAI1 Block A clock.
mbed_official 87:085cde657901 814 */
mbed_official 87:085cde657901 815 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
mbed_official 87:085cde657901 816
mbed_official 87:085cde657901 817 /** @brief Macro to configure SAI1BlockB clock source selection.
mbed_official 87:085cde657901 818 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 819 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 87:085cde657901 820 * the SAI clock.
mbed_official 87:085cde657901 821 * @param __SOURCE__: specifies the SAI Block B clock source.
mbed_official 87:085cde657901 822 * This parameter can be one of the following values:
mbed_official 87:085cde657901 823 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 87:085cde657901 824 * as SAI1 Block B clock.
mbed_official 87:085cde657901 825 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 87:085cde657901 826 * as SAI1 Block B clock.
mbed_official 87:085cde657901 827 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official 87:085cde657901 828 * used as SAI1 Block B clock.
mbed_official 87:085cde657901 829 */
mbed_official 87:085cde657901 830 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
mbed_official 87:085cde657901 831
mbed_official 87:085cde657901 832 /** @brief Enable PLLSAI_RDY interrupt.
mbed_official 87:085cde657901 833 */
mbed_official 87:085cde657901 834 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 835
mbed_official 87:085cde657901 836 /** @brief Disable PLLSAI_RDY interrupt.
mbed_official 87:085cde657901 837 */
mbed_official 87:085cde657901 838 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 839
mbed_official 87:085cde657901 840 /** @brief Clear the PLLSAI RDY interrupt pending bits.
mbed_official 87:085cde657901 841 */
mbed_official 87:085cde657901 842 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
mbed_official 87:085cde657901 843
mbed_official 87:085cde657901 844 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
mbed_official 87:085cde657901 845 * @retval The new state (TRUE or FALSE).
mbed_official 87:085cde657901 846 */
mbed_official 87:085cde657901 847 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 848
mbed_official 87:085cde657901 849 /** @brief Check PLLSAI RDY flag is set or not.
mbed_official 87:085cde657901 850 * @retval The new state (TRUE or FALSE).
mbed_official 87:085cde657901 851 */
mbed_official 87:085cde657901 852 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
mbed_official 87:085cde657901 853
mbed_official 87:085cde657901 854 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 855
mbed_official 87:085cde657901 856 /* Exported functions --------------------------------------------------------*/
mbed_official 87:085cde657901 857 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 87:085cde657901 858 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 87:085cde657901 859
mbed_official 87:085cde657901 860 /**
mbed_official 87:085cde657901 861 * @}
mbed_official 87:085cde657901 862 */
mbed_official 87:085cde657901 863
mbed_official 87:085cde657901 864 /**
mbed_official 87:085cde657901 865 * @}
mbed_official 87:085cde657901 866 */
mbed_official 87:085cde657901 867
mbed_official 87:085cde657901 868 #ifdef __cplusplus
mbed_official 87:085cde657901 869 }
mbed_official 87:085cde657901 870 #endif
mbed_official 87:085cde657901 871
mbed_official 87:085cde657901 872 #endif /* __STM32F4xx_HAL_RCC_EX_H */
mbed_official 87:085cde657901 873
mbed_official 87:085cde657901 874 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/