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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h@274:6937b19af361, 2014-08-06 (annotated)

Committer:
mbed_official
Date:
Wed Aug 06 08:15:07 2014 +0100
Revision:
274:6937b19af361
Parent:
226:b062af740e40
Child:
369:2e96f1b71984
Synchronized with git revision 5b145e4f6c509376173c3ea2aa35a6da879a2124



Full URL: https://github.com/mbedmicro/mbed/commit/5b145e4f6c509376173c3ea2aa35a6da879a2124/



[TARGET_LPC11UXX] PeripheralNames.h and PinMap definitions separation for LPC11UXX platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_rcc.h
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V1.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief Header file of RCC HAL module.
mbed_official 87:085cde657901 8 ******************************************************************************
mbed_official 87:085cde657901 9 * @attention
mbed_official 87:085cde657901 10 *
mbed_official 87:085cde657901 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 14 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 16 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 19 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 21 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 22 * without specific prior written permission.
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 ******************************************************************************
mbed_official 87:085cde657901 36 */
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 87:085cde657901 39 #ifndef __STM32F4xx_HAL_RCC_H
mbed_official 87:085cde657901 40 #define __STM32F4xx_HAL_RCC_H
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 #ifdef __cplusplus
mbed_official 87:085cde657901 43 extern "C" {
mbed_official 87:085cde657901 44 #endif
mbed_official 87:085cde657901 45
mbed_official 87:085cde657901 46 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 47 #include "stm32f4xx_hal_def.h"
mbed_official 87:085cde657901 48
mbed_official 87:085cde657901 49 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 50 * @{
mbed_official 87:085cde657901 51 */
mbed_official 87:085cde657901 52
mbed_official 87:085cde657901 53 /** @addtogroup RCC
mbed_official 87:085cde657901 54 * @{
mbed_official 87:085cde657901 55 */
mbed_official 87:085cde657901 56
mbed_official 87:085cde657901 57 /* Exported types ------------------------------------------------------------*/
mbed_official 87:085cde657901 58
mbed_official 87:085cde657901 59 /**
mbed_official 87:085cde657901 60 * @brief RCC PLL configuration structure definition
mbed_official 87:085cde657901 61 */
mbed_official 87:085cde657901 62 typedef struct
mbed_official 87:085cde657901 63 {
mbed_official 87:085cde657901 64 uint32_t PLLState; /*!< The new state of the PLL.
mbed_official 87:085cde657901 65 This parameter can be a value of @ref RCC_PLL_Config */
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official 87:085cde657901 68 This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official 87:085cde657901 69
mbed_official 226:b062af740e40 70 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
mbed_official 87:085cde657901 71 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official 87:085cde657901 72
mbed_official 226:b062af740e40 73 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official 87:085cde657901 74 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official 87:085cde657901 75
mbed_official 226:b062af740e40 76 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
mbed_official 226:b062af740e40 77 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
mbed_official 87:085cde657901 78
mbed_official 226:b062af740e40 79 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
mbed_official 87:085cde657901 80 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official 87:085cde657901 81
mbed_official 87:085cde657901 82 }RCC_PLLInitTypeDef;
mbed_official 87:085cde657901 83
mbed_official 87:085cde657901 84 /**
mbed_official 87:085cde657901 85 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official 87:085cde657901 86 */
mbed_official 87:085cde657901 87 typedef struct
mbed_official 87:085cde657901 88 {
mbed_official 87:085cde657901 89 uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official 87:085cde657901 90 This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official 87:085cde657901 91
mbed_official 87:085cde657901 92 uint32_t HSEState; /*!< The new state of the HSE.
mbed_official 87:085cde657901 93 This parameter can be a value of @ref RCC_HSE_Config */
mbed_official 87:085cde657901 94
mbed_official 87:085cde657901 95 uint32_t LSEState; /*!< The new state of the LSE.
mbed_official 87:085cde657901 96 This parameter can be a value of @ref RCC_LSE_Config */
mbed_official 87:085cde657901 97
mbed_official 87:085cde657901 98 uint32_t HSIState; /*!< The new state of the HSI.
mbed_official 87:085cde657901 99 This parameter can be a value of @ref RCC_HSI_Config */
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official 87:085cde657901 102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official 87:085cde657901 103
mbed_official 87:085cde657901 104 uint32_t LSIState; /*!< The new state of the LSI.
mbed_official 87:085cde657901 105 This parameter can be a value of @ref RCC_LSI_Config */
mbed_official 87:085cde657901 106
mbed_official 87:085cde657901 107 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
mbed_official 87:085cde657901 108
mbed_official 87:085cde657901 109 }RCC_OscInitTypeDef;
mbed_official 87:085cde657901 110
mbed_official 87:085cde657901 111 /**
mbed_official 87:085cde657901 112 * @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official 87:085cde657901 113 */
mbed_official 87:085cde657901 114 typedef struct
mbed_official 87:085cde657901 115 {
mbed_official 87:085cde657901 116 uint32_t ClockType; /*!< The clock to be configured.
mbed_official 87:085cde657901 117 This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official 87:085cde657901 118
mbed_official 87:085cde657901 119 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official 87:085cde657901 120 This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official 87:085cde657901 121
mbed_official 87:085cde657901 122 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official 87:085cde657901 123 This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official 87:085cde657901 124
mbed_official 87:085cde657901 125 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official 87:085cde657901 126 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official 87:085cde657901 127
mbed_official 87:085cde657901 128 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official 87:085cde657901 129 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official 87:085cde657901 130
mbed_official 87:085cde657901 131 }RCC_ClkInitTypeDef;
mbed_official 87:085cde657901 132
mbed_official 87:085cde657901 133 /* Exported constants --------------------------------------------------------*/
mbed_official 87:085cde657901 134 /** @defgroup RCC_Exported_Constants
mbed_official 87:085cde657901 135 * @{
mbed_official 87:085cde657901 136 */
mbed_official 87:085cde657901 137
mbed_official 87:085cde657901 138 /** @defgroup RCC_BitAddress_AliasRegion
mbed_official 87:085cde657901 139 * @brief RCC registers bit address in the alias region
mbed_official 87:085cde657901 140 * @{
mbed_official 87:085cde657901 141 */
mbed_official 87:085cde657901 142 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official 87:085cde657901 143 /* --- CR Register ---*/
mbed_official 87:085cde657901 144 /* Alias word address of HSION bit */
mbed_official 87:085cde657901 145 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official 87:085cde657901 146 #define HSION_BitNumber 0x00
mbed_official 87:085cde657901 147 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official 87:085cde657901 148 /* Alias word address of CSSON bit */
mbed_official 87:085cde657901 149 #define CSSON_BitNumber 0x13
mbed_official 87:085cde657901 150 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official 87:085cde657901 151 /* Alias word address of PLLON bit */
mbed_official 87:085cde657901 152 #define PLLON_BitNumber 0x18
mbed_official 87:085cde657901 153 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official 87:085cde657901 154 /* Alias word address of PLLI2SON bit */
mbed_official 87:085cde657901 155 #define PLLI2SON_BitNumber 0x1A
mbed_official 87:085cde657901 156 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
mbed_official 87:085cde657901 157
mbed_official 87:085cde657901 158 /* --- CFGR Register ---*/
mbed_official 87:085cde657901 159 /* Alias word address of I2SSRC bit */
mbed_official 87:085cde657901 160 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official 87:085cde657901 161 #define I2SSRC_BitNumber 0x17
mbed_official 87:085cde657901 162 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
mbed_official 87:085cde657901 163
mbed_official 87:085cde657901 164 /* --- BDCR Register ---*/
mbed_official 87:085cde657901 165 /* Alias word address of RTCEN bit */
mbed_official 87:085cde657901 166 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
mbed_official 87:085cde657901 167 #define RTCEN_BitNumber 0x0F
mbed_official 87:085cde657901 168 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official 87:085cde657901 169 /* Alias word address of BDRST bit */
mbed_official 87:085cde657901 170 #define BDRST_BitNumber 0x10
mbed_official 87:085cde657901 171 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
mbed_official 87:085cde657901 172
mbed_official 87:085cde657901 173 /* --- CSR Register ---*/
mbed_official 87:085cde657901 174 /* Alias word address of LSION bit */
mbed_official 87:085cde657901 175 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official 87:085cde657901 176 #define LSION_BitNumber 0x00
mbed_official 87:085cde657901 177 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official 87:085cde657901 178
mbed_official 87:085cde657901 179 /* CR register byte 3 (Bits[23:16]) base address */
mbed_official 87:085cde657901 180 #define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official 87:085cde657901 181
mbed_official 87:085cde657901 182 /* CIR register byte 2 (Bits[15:8]) base address */
mbed_official 87:085cde657901 183 #define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
mbed_official 87:085cde657901 184
mbed_official 87:085cde657901 185 /* CIR register byte 3 (Bits[23:16]) base address */
mbed_official 87:085cde657901 186 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
mbed_official 87:085cde657901 187
mbed_official 87:085cde657901 188 /* BDCR register base address */
mbed_official 106:ced8cbb51063 189 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
mbed_official 106:ced8cbb51063 190
mbed_official 87:085cde657901 191
mbed_official 106:ced8cbb51063 192 #define DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official 226:b062af740e40 193 #define LSE_TIMEOUT_VALUE ((uint32_t)500)
mbed_official 87:085cde657901 194 /**
mbed_official 87:085cde657901 195 * @}
mbed_official 87:085cde657901 196 */
mbed_official 87:085cde657901 197
mbed_official 87:085cde657901 198 /** @defgroup RCC_Oscillator_Type
mbed_official 87:085cde657901 199 * @{
mbed_official 87:085cde657901 200 */
mbed_official 106:ced8cbb51063 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official 87:085cde657901 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official 87:085cde657901 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official 87:085cde657901 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
mbed_official 87:085cde657901 208 /**
mbed_official 87:085cde657901 209 * @}
mbed_official 87:085cde657901 210 */
mbed_official 87:085cde657901 211
mbed_official 87:085cde657901 212 /** @defgroup RCC_HSE_Config
mbed_official 87:085cde657901 213 * @{
mbed_official 87:085cde657901 214 */
mbed_official 87:085cde657901 215 #define RCC_HSE_OFF ((uint8_t)0x00)
mbed_official 87:085cde657901 216 #define RCC_HSE_ON ((uint8_t)0x01)
mbed_official 87:085cde657901 217 #define RCC_HSE_BYPASS ((uint8_t)0x05)
mbed_official 87:085cde657901 218
mbed_official 87:085cde657901 219 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
mbed_official 87:085cde657901 220 ((HSE) == RCC_HSE_BYPASS))
mbed_official 87:085cde657901 221 /**
mbed_official 87:085cde657901 222 * @}
mbed_official 87:085cde657901 223 */
mbed_official 87:085cde657901 224
mbed_official 87:085cde657901 225 /** @defgroup RCC_LSE_Config
mbed_official 87:085cde657901 226 * @{
mbed_official 87:085cde657901 227 */
mbed_official 87:085cde657901 228 #define RCC_LSE_OFF ((uint8_t)0x00)
mbed_official 87:085cde657901 229 #define RCC_LSE_ON ((uint8_t)0x01)
mbed_official 87:085cde657901 230 #define RCC_LSE_BYPASS ((uint8_t)0x05)
mbed_official 87:085cde657901 231
mbed_official 87:085cde657901 232 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
mbed_official 87:085cde657901 233 ((LSE) == RCC_LSE_BYPASS))
mbed_official 87:085cde657901 234 /**
mbed_official 87:085cde657901 235 * @}
mbed_official 87:085cde657901 236 */
mbed_official 87:085cde657901 237
mbed_official 87:085cde657901 238 /** @defgroup RCC_HSI_Config
mbed_official 87:085cde657901 239 * @{
mbed_official 87:085cde657901 240 */
mbed_official 87:085cde657901 241 #define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official 87:085cde657901 242 #define RCC_HSI_ON ((uint8_t)0x01)
mbed_official 87:085cde657901 243
mbed_official 87:085cde657901 244 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
mbed_official 87:085cde657901 245 /**
mbed_official 87:085cde657901 246 * @}
mbed_official 87:085cde657901 247 */
mbed_official 87:085cde657901 248
mbed_official 87:085cde657901 249 /** @defgroup RCC_LSI_Config
mbed_official 87:085cde657901 250 * @{
mbed_official 87:085cde657901 251 */
mbed_official 87:085cde657901 252 #define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official 87:085cde657901 253 #define RCC_LSI_ON ((uint8_t)0x01)
mbed_official 87:085cde657901 254
mbed_official 87:085cde657901 255 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
mbed_official 87:085cde657901 256 /**
mbed_official 87:085cde657901 257 * @}
mbed_official 87:085cde657901 258 */
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 /** @defgroup RCC_PLL_Config
mbed_official 87:085cde657901 261 * @{
mbed_official 87:085cde657901 262 */
mbed_official 87:085cde657901 263 #define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official 87:085cde657901 264 #define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official 87:085cde657901 265 #define RCC_PLL_ON ((uint8_t)0x02)
mbed_official 87:085cde657901 266
mbed_official 87:085cde657901 267 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
mbed_official 87:085cde657901 268 /**
mbed_official 87:085cde657901 269 * @}
mbed_official 87:085cde657901 270 */
mbed_official 87:085cde657901 271
mbed_official 87:085cde657901 272 /** @defgroup RCC_PLLP_Clock_Divider
mbed_official 87:085cde657901 273 * @{
mbed_official 87:085cde657901 274 */
mbed_official 87:085cde657901 275 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
mbed_official 87:085cde657901 276 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
mbed_official 87:085cde657901 277 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
mbed_official 87:085cde657901 278 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
mbed_official 87:085cde657901 279 /**
mbed_official 87:085cde657901 280 * @}
mbed_official 87:085cde657901 281 */
mbed_official 87:085cde657901 282
mbed_official 87:085cde657901 283 /** @defgroup RCC_PLL_Clock_Source
mbed_official 87:085cde657901 284 * @{
mbed_official 87:085cde657901 285 */
mbed_official 87:085cde657901 286 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
mbed_official 87:085cde657901 287 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
mbed_official 87:085cde657901 288
mbed_official 87:085cde657901 289 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
mbed_official 87:085cde657901 290 ((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official 87:085cde657901 291 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official 87:085cde657901 292 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 87:085cde657901 293 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
mbed_official 87:085cde657901 294 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 87:085cde657901 295
mbed_official 87:085cde657901 296 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 87:085cde657901 297 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 /**
mbed_official 87:085cde657901 300 * @}
mbed_official 87:085cde657901 301 */
mbed_official 87:085cde657901 302
mbed_official 87:085cde657901 303 /** @defgroup RCC_System_Clock_Type
mbed_official 87:085cde657901 304 * @{
mbed_official 87:085cde657901 305 */
mbed_official 87:085cde657901 306 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official 87:085cde657901 307 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official 87:085cde657901 308 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official 87:085cde657901 309 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official 87:085cde657901 310
mbed_official 87:085cde657901 311 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official 87:085cde657901 312 /**
mbed_official 87:085cde657901 313 * @}
mbed_official 87:085cde657901 314 */
mbed_official 87:085cde657901 315
mbed_official 87:085cde657901 316 /** @defgroup RCC_System_Clock_Source
mbed_official 87:085cde657901 317 * @{
mbed_official 87:085cde657901 318 */
mbed_official 87:085cde657901 319 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official 87:085cde657901 320 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official 87:085cde657901 321 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official 87:085cde657901 322
mbed_official 87:085cde657901 323 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
mbed_official 87:085cde657901 324 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
mbed_official 87:085cde657901 325 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official 87:085cde657901 326 /**
mbed_official 87:085cde657901 327 * @}
mbed_official 87:085cde657901 328 */
mbed_official 87:085cde657901 329
mbed_official 87:085cde657901 330 /** @defgroup RCC_AHB_Clock_Source
mbed_official 87:085cde657901 331 * @{
mbed_official 87:085cde657901 332 */
mbed_official 87:085cde657901 333 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official 87:085cde657901 334 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official 87:085cde657901 335 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official 87:085cde657901 336 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official 87:085cde657901 337 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official 87:085cde657901 338 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official 87:085cde657901 339 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official 87:085cde657901 340 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official 87:085cde657901 341 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official 87:085cde657901 342
mbed_official 87:085cde657901 343 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
mbed_official 87:085cde657901 344 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
mbed_official 87:085cde657901 345 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
mbed_official 87:085cde657901 346 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
mbed_official 87:085cde657901 347 ((HCLK) == RCC_SYSCLK_DIV512))
mbed_official 87:085cde657901 348 /**
mbed_official 87:085cde657901 349 * @}
mbed_official 87:085cde657901 350 */
mbed_official 87:085cde657901 351
mbed_official 87:085cde657901 352 /** @defgroup RCC_APB1_APB2_Clock_Source
mbed_official 87:085cde657901 353 * @{
mbed_official 87:085cde657901 354 */
mbed_official 87:085cde657901 355 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official 87:085cde657901 356 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official 87:085cde657901 357 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official 87:085cde657901 358 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official 87:085cde657901 359 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official 87:085cde657901 360
mbed_official 87:085cde657901 361 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
mbed_official 87:085cde657901 362 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
mbed_official 87:085cde657901 363 ((PCLK) == RCC_HCLK_DIV16))
mbed_official 87:085cde657901 364 /**
mbed_official 87:085cde657901 365 * @}
mbed_official 87:085cde657901 366 */
mbed_official 87:085cde657901 367
mbed_official 87:085cde657901 368 /** @defgroup RCC_RTC_Clock_Source
mbed_official 87:085cde657901 369 * @{
mbed_official 87:085cde657901 370 */
mbed_official 87:085cde657901 371 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
mbed_official 87:085cde657901 372 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
mbed_official 87:085cde657901 373 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
mbed_official 87:085cde657901 374 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
mbed_official 87:085cde657901 375 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
mbed_official 87:085cde657901 376 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
mbed_official 87:085cde657901 377 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
mbed_official 87:085cde657901 378 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
mbed_official 87:085cde657901 379 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
mbed_official 87:085cde657901 380 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
mbed_official 87:085cde657901 381 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
mbed_official 87:085cde657901 382 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
mbed_official 87:085cde657901 383 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
mbed_official 87:085cde657901 384 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
mbed_official 87:085cde657901 385 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
mbed_official 87:085cde657901 386 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
mbed_official 87:085cde657901 387 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
mbed_official 87:085cde657901 388 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
mbed_official 87:085cde657901 389 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
mbed_official 87:085cde657901 390 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
mbed_official 87:085cde657901 391 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
mbed_official 87:085cde657901 392 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
mbed_official 87:085cde657901 393 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
mbed_official 87:085cde657901 394 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
mbed_official 87:085cde657901 395 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
mbed_official 87:085cde657901 396 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
mbed_official 87:085cde657901 397 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
mbed_official 87:085cde657901 398 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
mbed_official 87:085cde657901 399 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
mbed_official 87:085cde657901 400 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
mbed_official 87:085cde657901 401 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
mbed_official 87:085cde657901 402 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
mbed_official 87:085cde657901 403 /**
mbed_official 87:085cde657901 404 * @}
mbed_official 87:085cde657901 405 */
mbed_official 87:085cde657901 406
mbed_official 87:085cde657901 407 /** @defgroup RCC_I2S_Clock_Source
mbed_official 87:085cde657901 408 * @{
mbed_official 87:085cde657901 409 */
mbed_official 87:085cde657901 410 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official 87:085cde657901 411 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
mbed_official 87:085cde657901 412 /**
mbed_official 87:085cde657901 413 * @}
mbed_official 87:085cde657901 414 */
mbed_official 87:085cde657901 415
mbed_official 87:085cde657901 416 /** @defgroup RCC_MCO_Index
mbed_official 87:085cde657901 417 * @{
mbed_official 87:085cde657901 418 */
mbed_official 87:085cde657901 419 #define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 420 #define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official 87:085cde657901 421
mbed_official 87:085cde657901 422 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
mbed_official 87:085cde657901 423 /**
mbed_official 87:085cde657901 424 * @}
mbed_official 87:085cde657901 425 */
mbed_official 87:085cde657901 426
mbed_official 87:085cde657901 427 /** @defgroup RCC_MCO1_Clock_Source
mbed_official 87:085cde657901 428 * @{
mbed_official 87:085cde657901 429 */
mbed_official 87:085cde657901 430 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
mbed_official 87:085cde657901 431 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
mbed_official 87:085cde657901 432 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
mbed_official 87:085cde657901 433 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
mbed_official 87:085cde657901 434
mbed_official 87:085cde657901 435 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
mbed_official 87:085cde657901 436 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
mbed_official 87:085cde657901 437 /**
mbed_official 87:085cde657901 438 * @}
mbed_official 87:085cde657901 439 */
mbed_official 87:085cde657901 440
mbed_official 87:085cde657901 441 /** @defgroup RCC_MCO2_Clock_Source
mbed_official 87:085cde657901 442 * @{
mbed_official 87:085cde657901 443 */
mbed_official 87:085cde657901 444 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official 87:085cde657901 445 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
mbed_official 87:085cde657901 446 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
mbed_official 87:085cde657901 447 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
mbed_official 87:085cde657901 448
mbed_official 87:085cde657901 449 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
mbed_official 87:085cde657901 450 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
mbed_official 87:085cde657901 451 /**
mbed_official 87:085cde657901 452 * @}
mbed_official 87:085cde657901 453 */
mbed_official 87:085cde657901 454
mbed_official 87:085cde657901 455 /** @defgroup RCC_MCOx_Clock_Prescaler
mbed_official 87:085cde657901 456 * @{
mbed_official 87:085cde657901 457 */
mbed_official 87:085cde657901 458 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 459 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
mbed_official 87:085cde657901 460 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
mbed_official 87:085cde657901 461 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
mbed_official 87:085cde657901 462 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
mbed_official 87:085cde657901 463
mbed_official 87:085cde657901 464 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
mbed_official 87:085cde657901 465 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
mbed_official 87:085cde657901 466 ((DIV) == RCC_MCODIV_5))
mbed_official 87:085cde657901 467 /**
mbed_official 87:085cde657901 468 * @}
mbed_official 87:085cde657901 469 */
mbed_official 87:085cde657901 470
mbed_official 87:085cde657901 471 /** @defgroup RCC_Interrupt
mbed_official 87:085cde657901 472 * @{
mbed_official 87:085cde657901 473 */
mbed_official 87:085cde657901 474 #define RCC_IT_LSIRDY ((uint8_t)0x01)
mbed_official 87:085cde657901 475 #define RCC_IT_LSERDY ((uint8_t)0x02)
mbed_official 87:085cde657901 476 #define RCC_IT_HSIRDY ((uint8_t)0x04)
mbed_official 87:085cde657901 477 #define RCC_IT_HSERDY ((uint8_t)0x08)
mbed_official 87:085cde657901 478 #define RCC_IT_PLLRDY ((uint8_t)0x10)
mbed_official 87:085cde657901 479 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
mbed_official 87:085cde657901 480 #define RCC_IT_CSS ((uint8_t)0x80)
mbed_official 87:085cde657901 481 /**
mbed_official 87:085cde657901 482 * @}
mbed_official 87:085cde657901 483 */
mbed_official 87:085cde657901 484
mbed_official 87:085cde657901 485 /** @defgroup RCC_Flag
mbed_official 87:085cde657901 486 * Elements values convention: 0XXYYYYYb
mbed_official 87:085cde657901 487 * - YYYYY : Flag position in the register
mbed_official 87:085cde657901 488 * - 0XX : Register index
mbed_official 87:085cde657901 489 * - 01: CR register
mbed_official 87:085cde657901 490 * - 10: BDCR register
mbed_official 87:085cde657901 491 * - 11: CSR register
mbed_official 87:085cde657901 492 * @{
mbed_official 87:085cde657901 493 */
mbed_official 87:085cde657901 494 /* Flags in the CR register */
mbed_official 87:085cde657901 495 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
mbed_official 87:085cde657901 496 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official 87:085cde657901 497 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official 87:085cde657901 498 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
mbed_official 87:085cde657901 499
mbed_official 87:085cde657901 500 /* Flags in the BDCR register */
mbed_official 87:085cde657901 501 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
mbed_official 87:085cde657901 502
mbed_official 87:085cde657901 503 /* Flags in the CSR register */
mbed_official 87:085cde657901 504 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
mbed_official 87:085cde657901 505 #define RCC_FLAG_BORRST ((uint8_t)0x79)
mbed_official 87:085cde657901 506 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
mbed_official 87:085cde657901 507 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
mbed_official 87:085cde657901 508 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
mbed_official 87:085cde657901 509 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
mbed_official 87:085cde657901 510 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
mbed_official 87:085cde657901 511 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official 87:085cde657901 514 /**
mbed_official 87:085cde657901 515 * @}
mbed_official 87:085cde657901 516 */
mbed_official 87:085cde657901 517
mbed_official 87:085cde657901 518 /**
mbed_official 87:085cde657901 519 * @}
mbed_official 87:085cde657901 520 */
mbed_official 87:085cde657901 521 /* Exported macro ------------------------------------------------------------*/
mbed_official 87:085cde657901 522
mbed_official 87:085cde657901 523 /** @brief Enable or disable the AHB1 peripheral clock.
mbed_official 87:085cde657901 524 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 525 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 526 * using it.
mbed_official 87:085cde657901 527 */
mbed_official 87:085cde657901 528 #define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
mbed_official 87:085cde657901 529 #define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
mbed_official 87:085cde657901 530 #define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
mbed_official 87:085cde657901 531 #define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
mbed_official 87:085cde657901 532 #define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
mbed_official 87:085cde657901 533 #define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
mbed_official 87:085cde657901 534 #define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
mbed_official 87:085cde657901 535 #define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
mbed_official 87:085cde657901 536 #define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
mbed_official 87:085cde657901 537 #define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
mbed_official 87:085cde657901 538 #define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
mbed_official 87:085cde657901 539
mbed_official 87:085cde657901 540 #define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
mbed_official 87:085cde657901 541 #define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
mbed_official 87:085cde657901 542 #define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
mbed_official 87:085cde657901 543 #define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
mbed_official 87:085cde657901 544 #define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
mbed_official 87:085cde657901 545 #define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
mbed_official 87:085cde657901 546 #define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
mbed_official 87:085cde657901 547 #define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
mbed_official 87:085cde657901 548 #define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
mbed_official 87:085cde657901 549 #define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
mbed_official 87:085cde657901 550 #define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
mbed_official 87:085cde657901 551
mbed_official 87:085cde657901 552 /** @brief Enable or disable the AHB2 peripheral clock.
mbed_official 87:085cde657901 553 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 554 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 555 * using it.
mbed_official 87:085cde657901 556 */
mbed_official 87:085cde657901 557 #define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
mbed_official 87:085cde657901 558 __SYSCFG_CLK_ENABLE();\
mbed_official 87:085cde657901 559 }while(0)
mbed_official 87:085cde657901 560
mbed_official 87:085cde657901 561
mbed_official 87:085cde657901 562 #define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
mbed_official 87:085cde657901 563 __SYSCFG_CLK_DISABLE();\
mbed_official 87:085cde657901 564 }while(0)
mbed_official 87:085cde657901 565
mbed_official 87:085cde657901 566 #define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
mbed_official 87:085cde657901 567 #define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
mbed_official 87:085cde657901 568 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official 87:085cde657901 569 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 570 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 571 * using it.
mbed_official 87:085cde657901 572 */
mbed_official 87:085cde657901 573 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
mbed_official 87:085cde657901 574 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
mbed_official 87:085cde657901 575 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
mbed_official 87:085cde657901 576 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
mbed_official 87:085cde657901 577 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 578 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
mbed_official 87:085cde657901 579 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
mbed_official 87:085cde657901 580 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
mbed_official 87:085cde657901 581 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
mbed_official 87:085cde657901 582 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
mbed_official 87:085cde657901 583 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
mbed_official 87:085cde657901 584 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
mbed_official 87:085cde657901 585
mbed_official 87:085cde657901 586 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official 87:085cde657901 587 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official 87:085cde657901 588 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official 87:085cde657901 589 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official 87:085cde657901 590 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 591 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official 87:085cde657901 592 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official 87:085cde657901 593 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official 87:085cde657901 594 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official 87:085cde657901 595 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official 87:085cde657901 596 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official 87:085cde657901 597 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official 87:085cde657901 598
mbed_official 87:085cde657901 599 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 87:085cde657901 600 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 601 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 602 * using it.
mbed_official 87:085cde657901 603 */
mbed_official 87:085cde657901 604 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
mbed_official 87:085cde657901 605 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
mbed_official 87:085cde657901 606 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
mbed_official 87:085cde657901 607 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
mbed_official 87:085cde657901 608 #define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
mbed_official 87:085cde657901 609 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
mbed_official 87:085cde657901 610 #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
mbed_official 87:085cde657901 611 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
mbed_official 87:085cde657901 612 #define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
mbed_official 87:085cde657901 613 #define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
mbed_official 87:085cde657901 614 #define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
mbed_official 87:085cde657901 615
mbed_official 87:085cde657901 616 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official 87:085cde657901 617 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official 87:085cde657901 618 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official 87:085cde657901 619 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official 87:085cde657901 620 #define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
mbed_official 87:085cde657901 621 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official 87:085cde657901 622 #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official 87:085cde657901 623 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official 87:085cde657901 624 #define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official 87:085cde657901 625 #define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official 87:085cde657901 626 #define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official 87:085cde657901 627
mbed_official 87:085cde657901 628 /** @brief Force or release AHB1 peripheral reset.
mbed_official 87:085cde657901 629 */
mbed_official 87:085cde657901 630 #define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
mbed_official 87:085cde657901 631 #define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
mbed_official 87:085cde657901 632 #define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
mbed_official 87:085cde657901 633 #define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
mbed_official 87:085cde657901 634 #define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
mbed_official 87:085cde657901 635 #define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
mbed_official 87:085cde657901 636 #define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
mbed_official 87:085cde657901 637 #define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
mbed_official 87:085cde657901 638 #define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
mbed_official 87:085cde657901 639 #define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
mbed_official 87:085cde657901 640
mbed_official 87:085cde657901 641 #define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
mbed_official 87:085cde657901 642 #define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
mbed_official 87:085cde657901 643 #define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
mbed_official 87:085cde657901 644 #define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
mbed_official 87:085cde657901 645 #define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
mbed_official 87:085cde657901 646 #define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
mbed_official 87:085cde657901 647 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official 87:085cde657901 648 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official 87:085cde657901 649 #define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
mbed_official 87:085cde657901 650 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official 87:085cde657901 651 #define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
mbed_official 87:085cde657901 652 #define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
mbed_official 87:085cde657901 653 #define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
mbed_official 87:085cde657901 654
mbed_official 87:085cde657901 655 /** @brief Force or release AHB2 peripheral reset.
mbed_official 87:085cde657901 656 */
mbed_official 87:085cde657901 657 #define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
mbed_official 87:085cde657901 658 #define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
mbed_official 87:085cde657901 659
mbed_official 87:085cde657901 660 #define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
mbed_official 87:085cde657901 661 #define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
mbed_official 87:085cde657901 662
mbed_official 87:085cde657901 663 #define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
mbed_official 87:085cde657901 664 #define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
mbed_official 87:085cde657901 665
mbed_official 87:085cde657901 666 /** @brief Force or release APB1 peripheral reset.
mbed_official 87:085cde657901 667 */
mbed_official 87:085cde657901 668 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official 87:085cde657901 669 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
mbed_official 87:085cde657901 670 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
mbed_official 87:085cde657901 671 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
mbed_official 87:085cde657901 672 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
mbed_official 87:085cde657901 673 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
mbed_official 87:085cde657901 674 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
mbed_official 87:085cde657901 675 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
mbed_official 87:085cde657901 676 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
mbed_official 87:085cde657901 677 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
mbed_official 87:085cde657901 678 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
mbed_official 87:085cde657901 679 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
mbed_official 87:085cde657901 680 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
mbed_official 87:085cde657901 681
mbed_official 87:085cde657901 682 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official 87:085cde657901 683 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official 87:085cde657901 684 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official 87:085cde657901 685 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official 87:085cde657901 686 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official 87:085cde657901 687 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official 87:085cde657901 688 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official 87:085cde657901 689 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official 87:085cde657901 690 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official 87:085cde657901 691 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official 87:085cde657901 692 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official 87:085cde657901 693 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official 87:085cde657901 694 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official 87:085cde657901 695
mbed_official 87:085cde657901 696 /** @brief Force or release APB2 peripheral reset.
mbed_official 87:085cde657901 697 */
mbed_official 87:085cde657901 698 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official 87:085cde657901 699 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
mbed_official 87:085cde657901 700 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
mbed_official 87:085cde657901 701 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
mbed_official 87:085cde657901 702 #define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
mbed_official 87:085cde657901 703 #define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
mbed_official 87:085cde657901 704 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
mbed_official 87:085cde657901 705 #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
mbed_official 87:085cde657901 706 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
mbed_official 87:085cde657901 707 #define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
mbed_official 87:085cde657901 708 #define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
mbed_official 87:085cde657901 709 #define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
mbed_official 87:085cde657901 710
mbed_official 87:085cde657901 711 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official 87:085cde657901 712 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official 87:085cde657901 713 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official 87:085cde657901 714 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official 87:085cde657901 715 #define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
mbed_official 87:085cde657901 716 #define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
mbed_official 87:085cde657901 717 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official 87:085cde657901 718 #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official 87:085cde657901 719 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official 87:085cde657901 720 #define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official 87:085cde657901 721 #define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official 87:085cde657901 722 #define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official 87:085cde657901 723
mbed_official 87:085cde657901 724 /** @brief Force or release AHB3 peripheral reset.
mbed_official 87:085cde657901 725 */
mbed_official 87:085cde657901 726 #define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
mbed_official 87:085cde657901 727 #define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
mbed_official 87:085cde657901 728
mbed_official 87:085cde657901 729 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 730 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 731 * power consumption.
mbed_official 87:085cde657901 732 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 733 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 734 */
mbed_official 87:085cde657901 735 #define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
mbed_official 87:085cde657901 736 #define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
mbed_official 87:085cde657901 737 #define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
mbed_official 87:085cde657901 738 #define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
mbed_official 87:085cde657901 739 #define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
mbed_official 87:085cde657901 740 #define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
mbed_official 87:085cde657901 741 #define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
mbed_official 87:085cde657901 742 #define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
mbed_official 87:085cde657901 743 #define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
mbed_official 87:085cde657901 744 #define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official 87:085cde657901 745 #define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
mbed_official 87:085cde657901 746 #define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
mbed_official 87:085cde657901 747
mbed_official 87:085cde657901 748 #define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
mbed_official 87:085cde657901 749 #define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
mbed_official 87:085cde657901 750 #define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
mbed_official 87:085cde657901 751 #define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
mbed_official 87:085cde657901 752 #define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
mbed_official 87:085cde657901 753 #define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
mbed_official 87:085cde657901 754 #define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
mbed_official 87:085cde657901 755 #define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
mbed_official 87:085cde657901 756 #define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
mbed_official 87:085cde657901 757 #define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official 87:085cde657901 758 #define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
mbed_official 87:085cde657901 759 #define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
mbed_official 87:085cde657901 760
mbed_official 87:085cde657901 761 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 762 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 763 * power consumption.
mbed_official 87:085cde657901 764 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 765 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 766 */
mbed_official 87:085cde657901 767 #define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
mbed_official 87:085cde657901 768
mbed_official 87:085cde657901 769 #define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
mbed_official 87:085cde657901 770
mbed_official 87:085cde657901 771 #define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
mbed_official 87:085cde657901 772 #define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
mbed_official 87:085cde657901 773
mbed_official 87:085cde657901 774 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 775 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 776 * power consumption.
mbed_official 87:085cde657901 777 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 778 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 779 */
mbed_official 87:085cde657901 780 #define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
mbed_official 87:085cde657901 781 #define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
mbed_official 87:085cde657901 782 #define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
mbed_official 87:085cde657901 783 #define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
mbed_official 87:085cde657901 784 #define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
mbed_official 87:085cde657901 785 #define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
mbed_official 87:085cde657901 786 #define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
mbed_official 87:085cde657901 787 #define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
mbed_official 87:085cde657901 788 #define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
mbed_official 87:085cde657901 789 #define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
mbed_official 87:085cde657901 790 #define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
mbed_official 87:085cde657901 791 #define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
mbed_official 87:085cde657901 792
mbed_official 87:085cde657901 793 #define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official 87:085cde657901 794 #define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official 87:085cde657901 795 #define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official 87:085cde657901 796 #define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
mbed_official 87:085cde657901 797 #define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
mbed_official 87:085cde657901 798 #define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official 87:085cde657901 799 #define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
mbed_official 87:085cde657901 800 #define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official 87:085cde657901 801 #define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official 87:085cde657901 802 #define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official 87:085cde657901 803 #define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
mbed_official 87:085cde657901 804 #define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
mbed_official 87:085cde657901 805
mbed_official 87:085cde657901 806 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 807 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 808 * power consumption.
mbed_official 87:085cde657901 809 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 810 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 811 */
mbed_official 87:085cde657901 812 #define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
mbed_official 87:085cde657901 813 #define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
mbed_official 87:085cde657901 814 #define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
mbed_official 87:085cde657901 815 #define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
mbed_official 87:085cde657901 816 #define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
mbed_official 87:085cde657901 817 #define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
mbed_official 87:085cde657901 818 #define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
mbed_official 87:085cde657901 819 #define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
mbed_official 87:085cde657901 820 #define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
mbed_official 87:085cde657901 821 #define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
mbed_official 87:085cde657901 822 #define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
mbed_official 87:085cde657901 823
mbed_official 87:085cde657901 824 #define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
mbed_official 87:085cde657901 825 #define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official 87:085cde657901 826 #define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
mbed_official 87:085cde657901 827 #define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official 87:085cde657901 828 #define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
mbed_official 87:085cde657901 829 #define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official 87:085cde657901 830 #define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
mbed_official 87:085cde657901 831 #define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
mbed_official 87:085cde657901 832 #define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official 87:085cde657901 833 #define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official 87:085cde657901 834 #define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official 87:085cde657901 835
mbed_official 87:085cde657901 836 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official 87:085cde657901 837 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 838 * It is used (enabled by hardware) as system clock source after startup
mbed_official 87:085cde657901 839 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official 87:085cde657901 840 * of the HSE used directly or indirectly as system clock (if the Clock
mbed_official 87:085cde657901 841 * Security System CSS is enabled).
mbed_official 87:085cde657901 842 * @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official 87:085cde657901 843 * you have to select another source of the system clock then stop the HSI.
mbed_official 87:085cde657901 844 * @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official 87:085cde657901 845 * flag to be set indicating that HSI clock is stable and can be used as
mbed_official 87:085cde657901 846 * system clock source.
mbed_official 87:085cde657901 847 * This parameter can be: ENABLE or DISABLE.
mbed_official 87:085cde657901 848 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official 87:085cde657901 849 * clock cycles.
mbed_official 87:085cde657901 850 */
mbed_official 87:085cde657901 851 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
mbed_official 87:085cde657901 852 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
mbed_official 87:085cde657901 853
mbed_official 87:085cde657901 854 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official 87:085cde657901 855 * @note The calibration is used to compensate for the variations in voltage
mbed_official 87:085cde657901 856 * and temperature that influence the frequency of the internal HSI RC.
mbed_official 87:085cde657901 857 * @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official 87:085cde657901 858 * This parameter must be a number between 0 and 0x1F.
mbed_official 87:085cde657901 859 */
mbed_official 87:085cde657901 860 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
mbed_official 87:085cde657901 861 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
mbed_official 87:085cde657901 862
mbed_official 87:085cde657901 863 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official 87:085cde657901 864 * @note After enabling the LSI, the application software should wait on
mbed_official 87:085cde657901 865 * LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official 87:085cde657901 866 * be used to clock the IWDG and/or the RTC.
mbed_official 87:085cde657901 867 * @note LSI can not be disabled if the IWDG is running.
mbed_official 87:085cde657901 868 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official 87:085cde657901 869 * clock cycles.
mbed_official 87:085cde657901 870 */
mbed_official 87:085cde657901 871 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
mbed_official 87:085cde657901 872 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
mbed_official 87:085cde657901 873
mbed_official 87:085cde657901 874 /**
mbed_official 87:085cde657901 875 * @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official 87:085cde657901 876 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official 87:085cde657901 877 * software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official 87:085cde657901 878 * is stable and can be used to clock the PLL and/or system clock.
mbed_official 87:085cde657901 879 * @note HSE state can not be changed if it is used directly or through the
mbed_official 87:085cde657901 880 * PLL as system clock. In this case, you have to select another source
mbed_official 87:085cde657901 881 * of the system clock then change the HSE state (ex. disable it).
mbed_official 87:085cde657901 882 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 883 * @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official 87:085cde657901 884 * was previously enabled you have to enable it again after calling this
mbed_official 87:085cde657901 885 * function.
mbed_official 87:085cde657901 886 * @param __STATE__: specifies the new state of the HSE.
mbed_official 87:085cde657901 887 * This parameter can be one of the following values:
mbed_official 87:085cde657901 888 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official 87:085cde657901 889 * 6 HSE oscillator clock cycles.
mbed_official 87:085cde657901 890 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official 87:085cde657901 891 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official 87:085cde657901 892 */
mbed_official 87:085cde657901 893 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
mbed_official 87:085cde657901 894
mbed_official 87:085cde657901 895 /**
mbed_official 87:085cde657901 896 * @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official 87:085cde657901 897 * @note As the LSE is in the Backup domain and write access is denied to
mbed_official 87:085cde657901 898 * this domain after reset, you have to enable write access using
mbed_official 87:085cde657901 899 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official 87:085cde657901 900 * (to be done once after reset).
mbed_official 87:085cde657901 901 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official 87:085cde657901 902 * software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official 87:085cde657901 903 * is stable and can be used to clock the RTC.
mbed_official 87:085cde657901 904 * @param __STATE__: specifies the new state of the LSE.
mbed_official 87:085cde657901 905 * This parameter can be one of the following values:
mbed_official 87:085cde657901 906 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official 87:085cde657901 907 * 6 LSE oscillator clock cycles.
mbed_official 87:085cde657901 908 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official 87:085cde657901 909 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official 87:085cde657901 910 */
mbed_official 87:085cde657901 911 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
mbed_official 87:085cde657901 912
mbed_official 87:085cde657901 913 /** @brief Macros to enable or disable the the RTC clock.
mbed_official 87:085cde657901 914 * @note These macros must be used only after the RTC clock source was selected.
mbed_official 87:085cde657901 915 */
mbed_official 87:085cde657901 916 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
mbed_official 87:085cde657901 917 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
mbed_official 87:085cde657901 918
mbed_official 87:085cde657901 919 /** @brief Macros to configure the RTC clock (RTCCLK).
mbed_official 87:085cde657901 920 * @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official 87:085cde657901 921 * access is denied to this domain after reset, you have to enable write
mbed_official 87:085cde657901 922 * access using the Power Backup Access macro before to configure
mbed_official 87:085cde657901 923 * the RTC clock source (to be done once after reset).
mbed_official 87:085cde657901 924 * @note Once the RTC clock is configured it can't be changed unless the
mbed_official 87:085cde657901 925 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
mbed_official 87:085cde657901 926 * a Power On Reset (POR).
mbed_official 87:085cde657901 927 * @param __RTCCLKSource__: specifies the RTC clock source.
mbed_official 87:085cde657901 928 * This parameter can be one of the following values:
mbed_official 87:085cde657901 929 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official 87:085cde657901 930 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official 87:085cde657901 931 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
mbed_official 87:085cde657901 932 * as RTC clock, where x:[2,31]
mbed_official 87:085cde657901 933 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official 87:085cde657901 934 * work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official 87:085cde657901 935 * However, when the HSE clock is used as RTC clock source, the RTC
mbed_official 87:085cde657901 936 * cannot be used in STOP and STANDBY modes.
mbed_official 87:085cde657901 937 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official 87:085cde657901 938 * RTC clock source).
mbed_official 87:085cde657901 939 */
mbed_official 87:085cde657901 940 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
mbed_official 106:ced8cbb51063 941 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
mbed_official 106:ced8cbb51063 942
mbed_official 87:085cde657901 943 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official 87:085cde657901 944 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
mbed_official 87:085cde657901 945 } while (0)
mbed_official 87:085cde657901 946
mbed_official 87:085cde657901 947 /** @brief Macros to force or release the Backup domain reset.
mbed_official 87:085cde657901 948 * @note This function resets the RTC peripheral (including the backup registers)
mbed_official 87:085cde657901 949 * and the RTC clock source selection in RCC_CSR register.
mbed_official 87:085cde657901 950 * @note The BKPSRAM is not affected by this reset.
mbed_official 87:085cde657901 951 */
mbed_official 87:085cde657901 952 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
mbed_official 87:085cde657901 953 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
mbed_official 87:085cde657901 954
mbed_official 87:085cde657901 955 /** @brief Macros to enable or disable the main PLL.
mbed_official 87:085cde657901 956 * @note After enabling the main PLL, the application software should wait on
mbed_official 87:085cde657901 957 * PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official 87:085cde657901 958 * be used as system clock source.
mbed_official 87:085cde657901 959 * @note The main PLL can not be disabled if it is used as system clock source
mbed_official 87:085cde657901 960 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 961 */
mbed_official 87:085cde657901 962 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
mbed_official 87:085cde657901 963 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
mbed_official 87:085cde657901 964
mbed_official 87:085cde657901 965 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official 87:085cde657901 966 * @note This function must be used only when the main PLL is disabled.
mbed_official 87:085cde657901 967 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official 87:085cde657901 968 * This parameter can be one of the following values:
mbed_official 87:085cde657901 969 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official 87:085cde657901 970 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official 87:085cde657901 971 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
mbed_official 87:085cde657901 972 * @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official 87:085cde657901 973 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official 87:085cde657901 974 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official 87:085cde657901 975 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official 87:085cde657901 976 * of 2 MHz to limit PLL jitter.
mbed_official 87:085cde657901 977 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official 87:085cde657901 978 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 979 * @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 980 * output frequency is between 192 and 432 MHz.
mbed_official 87:085cde657901 981 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
mbed_official 87:085cde657901 982 * This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official 87:085cde657901 983 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
mbed_official 87:085cde657901 984 * the System clock frequency.
mbed_official 87:085cde657901 985 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
mbed_official 87:085cde657901 986 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 987 * @note If the USB OTG FS is used in your application, you have to set the
mbed_official 87:085cde657901 988 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official 87:085cde657901 989 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official 87:085cde657901 990 * correctly.
mbed_official 87:085cde657901 991 */
mbed_official 87:085cde657901 992 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
mbed_official 87:085cde657901 993 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
mbed_official 87:085cde657901 994 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
mbed_official 87:085cde657901 995 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
mbed_official 87:085cde657901 996
mbed_official 87:085cde657901 997 /** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official 87:085cde657901 998 * @note This function must be called before enabling the I2S APB clock.
mbed_official 87:085cde657901 999 * @param __SOURCE__: specifies the I2S clock source.
mbed_official 87:085cde657901 1000 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1001 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
mbed_official 87:085cde657901 1002 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official 87:085cde657901 1003 * used as I2S clock source.
mbed_official 87:085cde657901 1004 */
mbed_official 87:085cde657901 1005 #define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
mbed_official 87:085cde657901 1006
mbed_official 87:085cde657901 1007 /** @brief Macros to enable or disable the PLLI2S.
mbed_official 87:085cde657901 1008 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 1009 */
mbed_official 87:085cde657901 1010 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
mbed_official 87:085cde657901 1011 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
mbed_official 87:085cde657901 1012
mbed_official 87:085cde657901 1013 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official 87:085cde657901 1014 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 87:085cde657901 1015 * @note PLLI2S clock source is common with the main PLL (configured in
mbed_official 87:085cde657901 1016 * HAL_RCC_ClockConfig() API).
mbed_official 87:085cde657901 1017 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official 87:085cde657901 1018 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 1019 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 1020 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 87:085cde657901 1021 * @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official 87:085cde657901 1022 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 1023 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official 87:085cde657901 1024 * on the I2S clock frequency.
mbed_official 87:085cde657901 1025 */
mbed_official 87:085cde657901 1026 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
mbed_official 87:085cde657901 1027
mbed_official 87:085cde657901 1028 /** @brief Macro to get the clock source used as system clock.
mbed_official 87:085cde657901 1029 * @retval The clock source used as system clock. The returned value can be one
mbed_official 87:085cde657901 1030 * of the following:
mbed_official 87:085cde657901 1031 * - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official 87:085cde657901 1032 * - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official 87:085cde657901 1033 * - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official 87:085cde657901 1034 */
mbed_official 87:085cde657901 1035 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official 87:085cde657901 1036
mbed_official 87:085cde657901 1037 /** @brief Macro to get the oscillator used as PLL clock source.
mbed_official 87:085cde657901 1038 * @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official 87:085cde657901 1039 * of the following:
mbed_official 87:085cde657901 1040 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official 87:085cde657901 1041 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official 87:085cde657901 1042 */
mbed_official 87:085cde657901 1043 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
mbed_official 87:085cde657901 1044
mbed_official 87:085cde657901 1045 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official 87:085cde657901 1046 * the selected interrupts).
mbed_official 87:085cde657901 1047 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official 87:085cde657901 1048 * This parameter can be any combination of the following values:
mbed_official 87:085cde657901 1049 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official 87:085cde657901 1050 * @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official 87:085cde657901 1051 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official 87:085cde657901 1052 * @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official 87:085cde657901 1053 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official 87:085cde657901 1054 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official 87:085cde657901 1055 */
mbed_official 87:085cde657901 1056 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
mbed_official 87:085cde657901 1057
mbed_official 87:085cde657901 1058 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official 87:085cde657901 1059 * the selected interrupts).
mbed_official 87:085cde657901 1060 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official 87:085cde657901 1061 * This parameter can be any combination of the following values:
mbed_official 87:085cde657901 1062 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official 87:085cde657901 1063 * @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official 87:085cde657901 1064 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official 87:085cde657901 1065 * @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official 87:085cde657901 1066 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official 87:085cde657901 1067 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official 87:085cde657901 1068 */
mbed_official 87:085cde657901 1069 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official 87:085cde657901 1070
mbed_official 87:085cde657901 1071 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official 87:085cde657901 1072 * bits to clear the selected interrupt pending bits.
mbed_official 87:085cde657901 1073 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official 87:085cde657901 1074 * This parameter can be any combination of the following values:
mbed_official 87:085cde657901 1075 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official 87:085cde657901 1076 * @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official 87:085cde657901 1077 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official 87:085cde657901 1078 * @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official 87:085cde657901 1079 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official 87:085cde657901 1080 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official 87:085cde657901 1081 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 87:085cde657901 1082 */
mbed_official 87:085cde657901 1083 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official 87:085cde657901 1084
mbed_official 87:085cde657901 1085 /** @brief Check the RCC's interrupt has occurred or not.
mbed_official 87:085cde657901 1086 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official 87:085cde657901 1087 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1088 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official 87:085cde657901 1089 * @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official 87:085cde657901 1090 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official 87:085cde657901 1091 * @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official 87:085cde657901 1092 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official 87:085cde657901 1093 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official 87:085cde657901 1094 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 87:085cde657901 1095 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official 87:085cde657901 1096 */
mbed_official 87:085cde657901 1097 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official 87:085cde657901 1098
mbed_official 87:085cde657901 1099 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official 87:085cde657901 1100 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
mbed_official 87:085cde657901 1101 */
mbed_official 106:ced8cbb51063 1102 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
mbed_official 87:085cde657901 1103
mbed_official 87:085cde657901 1104 /** @brief Check RCC flag is set or not.
mbed_official 87:085cde657901 1105 * @param __FLAG__: specifies the flag to check.
mbed_official 87:085cde657901 1106 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1107 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official 87:085cde657901 1108 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official 87:085cde657901 1109 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official 87:085cde657901 1110 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
mbed_official 87:085cde657901 1111 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official 87:085cde657901 1112 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official 87:085cde657901 1113 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
mbed_official 87:085cde657901 1114 * @arg RCC_FLAG_PINRST: Pin reset.
mbed_official 87:085cde657901 1115 * @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official 87:085cde657901 1116 * @arg RCC_FLAG_SFTRST: Software reset.
mbed_official 87:085cde657901 1117 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official 87:085cde657901 1118 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official 87:085cde657901 1119 * @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official 87:085cde657901 1120 * @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official 87:085cde657901 1121 */
mbed_official 87:085cde657901 1122 #define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official 87:085cde657901 1123 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
mbed_official 87:085cde657901 1124
mbed_official 87:085cde657901 1125 #define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
mbed_official 87:085cde657901 1126
mbed_official 87:085cde657901 1127
mbed_official 87:085cde657901 1128 /* Include RCC HAL Extension module */
mbed_official 87:085cde657901 1129 #include "stm32f4xx_hal_rcc_ex.h"
mbed_official 87:085cde657901 1130
mbed_official 87:085cde657901 1131 /* Exported functions --------------------------------------------------------*/
mbed_official 87:085cde657901 1132
mbed_official 87:085cde657901 1133 /* Initialization and de-initialization functions ******************************/
mbed_official 87:085cde657901 1134 void HAL_RCC_DeInit(void);
mbed_official 87:085cde657901 1135 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official 87:085cde657901 1136 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official 87:085cde657901 1137
mbed_official 87:085cde657901 1138 /* Peripheral Control functions ************************************************/
mbed_official 87:085cde657901 1139 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official 87:085cde657901 1140 void HAL_RCC_EnableCSS(void);
mbed_official 87:085cde657901 1141 void HAL_RCC_DisableCSS(void);
mbed_official 87:085cde657901 1142 uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official 87:085cde657901 1143 uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official 87:085cde657901 1144 uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official 87:085cde657901 1145 uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official 87:085cde657901 1146 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official 87:085cde657901 1147 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
mbed_official 87:085cde657901 1148
mbed_official 87:085cde657901 1149 /* CSS NMI IRQ handler */
mbed_official 87:085cde657901 1150 void HAL_RCC_NMI_IRQHandler(void);
mbed_official 87:085cde657901 1151
mbed_official 87:085cde657901 1152 /* User Callbacks in non blocking mode (IT mode) */
mbed_official 106:ced8cbb51063 1153 void HAL_RCC_CCSCallback(void);
mbed_official 87:085cde657901 1154
mbed_official 87:085cde657901 1155 /**
mbed_official 87:085cde657901 1156 * @}
mbed_official 87:085cde657901 1157 */
mbed_official 87:085cde657901 1158
mbed_official 87:085cde657901 1159 /**
mbed_official 87:085cde657901 1160 * @}
mbed_official 87:085cde657901 1161 */
mbed_official 87:085cde657901 1162
mbed_official 87:085cde657901 1163 #ifdef __cplusplus
mbed_official 87:085cde657901 1164 }
mbed_official 87:085cde657901 1165 #endif
mbed_official 87:085cde657901 1166
mbed_official 87:085cde657901 1167 #endif /* __STM32F4xx_HAL_RCC_H */
mbed_official 87:085cde657901 1168
mbed_official 87:085cde657901 1169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/