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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c@274:6937b19af361, 2014-08-06 (annotated)

Committer:
mbed_official
Date:
Wed Aug 06 08:15:07 2014 +0100
Revision:
274:6937b19af361
Parent:
226:b062af740e40
Child:
369:2e96f1b71984
Synchronized with git revision 5b145e4f6c509376173c3ea2aa35a6da879a2124



Full URL: https://github.com/mbedmicro/mbed/commit/5b145e4f6c509376173c3ea2aa35a6da879a2124/



[TARGET_LPC11UXX] PeripheralNames.h and PinMap definitions separation for LPC11UXX platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_eth.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V1.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief ETH HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 87:085cde657901 10 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 11 * + IO operation functions
mbed_official 87:085cde657901 12 * + Peripheral Control functions
mbed_official 87:085cde657901 13 * + Peripheral State and Errors functions
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### How to use this driver #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..]
mbed_official 87:085cde657901 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 87:085cde657901 21 ETH_HandleTypeDef heth;
mbed_official 87:085cde657901 22
mbed_official 87:085cde657901 23 (#)Fill parameters of Init structure in heth handle
mbed_official 87:085cde657901 24
mbed_official 87:085cde657901 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 87:085cde657901 26
mbed_official 87:085cde657901 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 87:085cde657901 28 (##) Enable the Ethernet interface clock using
mbed_official 87:085cde657901 29 (+++) __ETHMAC_CLK_ENABLE();
mbed_official 87:085cde657901 30 (+++) __ETHMACTX_CLK_ENABLE();
mbed_official 87:085cde657901 31 (+++) __ETHMACRX_CLK_ENABLE();
mbed_official 87:085cde657901 32
mbed_official 87:085cde657901 33 (##) Initialize the related GPIO clocks
mbed_official 87:085cde657901 34 (##) Configure Ethernet pin-out
mbed_official 87:085cde657901 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 87:085cde657901 36
mbed_official 87:085cde657901 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 87:085cde657901 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 87:085cde657901 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 87:085cde657901 40
mbed_official 87:085cde657901 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 87:085cde657901 42 (##) HAL_ETH_Start();
mbed_official 87:085cde657901 43
mbed_official 87:085cde657901 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 87:085cde657901 45 the frame to MAC TX FIFO:
mbed_official 87:085cde657901 46 (##) HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 47
mbed_official 87:085cde657901 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 87:085cde657901 49 frame parameters
mbed_official 87:085cde657901 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 87:085cde657901 51
mbed_official 87:085cde657901 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 87:085cde657901 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 87:085cde657901 54
mbed_official 87:085cde657901 55 (#) Communicate with external PHY device:
mbed_official 87:085cde657901 56 (##) Read a specific register from the PHY
mbed_official 87:085cde657901 57 HAL_ETH_ReadPHYRegister();
mbed_official 87:085cde657901 58 (##) Write data to a specific RHY register:
mbed_official 87:085cde657901 59 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 60
mbed_official 87:085cde657901 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 87:085cde657901 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 87:085cde657901 63
mbed_official 87:085cde657901 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 87:085cde657901 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 @endverbatim
mbed_official 87:085cde657901 68 ******************************************************************************
mbed_official 87:085cde657901 69 * @attention
mbed_official 87:085cde657901 70 *
mbed_official 87:085cde657901 71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 72 *
mbed_official 87:085cde657901 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 74 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 76 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 79 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 81 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 82 * without specific prior written permission.
mbed_official 87:085cde657901 83 *
mbed_official 87:085cde657901 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 94 *
mbed_official 87:085cde657901 95 ******************************************************************************
mbed_official 87:085cde657901 96 */
mbed_official 87:085cde657901 97
mbed_official 87:085cde657901 98 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 99 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 102 * @{
mbed_official 87:085cde657901 103 */
mbed_official 87:085cde657901 104
mbed_official 87:085cde657901 105 /** @defgroup ETH
mbed_official 87:085cde657901 106 * @brief ETH HAL module driver
mbed_official 87:085cde657901 107 * @{
mbed_official 87:085cde657901 108 */
mbed_official 87:085cde657901 109
mbed_official 87:085cde657901 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 87:085cde657901 111
mbed_official 87:085cde657901 112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 113
mbed_official 87:085cde657901 114 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 115 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 116 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 117 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 118 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 119 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 87:085cde657901 120 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 87:085cde657901 121 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 122 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 123 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 124 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 125 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 126 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 127 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 128 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 129 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 130
mbed_official 87:085cde657901 131 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 132
mbed_official 87:085cde657901 133 /** @defgroup ETH_Private_Functions
mbed_official 87:085cde657901 134 * @{
mbed_official 87:085cde657901 135 */
mbed_official 87:085cde657901 136
mbed_official 87:085cde657901 137 /** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official 87:085cde657901 138 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 139 *
mbed_official 87:085cde657901 140 @verbatim
mbed_official 87:085cde657901 141 ===============================================================================
mbed_official 87:085cde657901 142 ##### Initialization and de-initialization functions #####
mbed_official 87:085cde657901 143 ===============================================================================
mbed_official 87:085cde657901 144 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 145 (+) Initialize and configure the Ethernet peripheral
mbed_official 87:085cde657901 146 (+) De-initialize the Ethernet peripheral
mbed_official 87:085cde657901 147
mbed_official 87:085cde657901 148 @endverbatim
mbed_official 87:085cde657901 149 * @{
mbed_official 87:085cde657901 150 */
mbed_official 87:085cde657901 151
mbed_official 87:085cde657901 152 /**
mbed_official 87:085cde657901 153 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 87:085cde657901 154 * parameters.
mbed_official 226:b062af740e40 155 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 156 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 157 * @retval HAL status
mbed_official 87:085cde657901 158 */
mbed_official 87:085cde657901 159 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 160 {
mbed_official 87:085cde657901 161 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 87:085cde657901 162 uint32_t hclk = 60000000;
mbed_official 87:085cde657901 163 uint32_t timeout = 0;
mbed_official 87:085cde657901 164 uint32_t err = ETH_SUCCESS;
mbed_official 87:085cde657901 165
mbed_official 87:085cde657901 166 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 167 if(heth == NULL)
mbed_official 87:085cde657901 168 {
mbed_official 87:085cde657901 169 return HAL_ERROR;
mbed_official 87:085cde657901 170 }
mbed_official 87:085cde657901 171
mbed_official 87:085cde657901 172 /* Check parameters */
mbed_official 87:085cde657901 173 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 87:085cde657901 174 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 87:085cde657901 175 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 87:085cde657901 176 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 87:085cde657901 177
mbed_official 87:085cde657901 178 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 87:085cde657901 179 {
mbed_official 87:085cde657901 180 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 181 HAL_ETH_MspInit(heth);
mbed_official 87:085cde657901 182 }
mbed_official 87:085cde657901 183
mbed_official 87:085cde657901 184 /* Enable SYSCFG Clock */
mbed_official 87:085cde657901 185 __SYSCFG_CLK_ENABLE();
mbed_official 87:085cde657901 186
mbed_official 87:085cde657901 187 /* Select MII or RMII Mode*/
mbed_official 87:085cde657901 188 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 87:085cde657901 189 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 87:085cde657901 190
mbed_official 87:085cde657901 191 /* Ethernet Software reset */
mbed_official 87:085cde657901 192 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 87:085cde657901 193 /* After reset all the registers holds their respective reset values */
mbed_official 87:085cde657901 194 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 87:085cde657901 195
mbed_official 87:085cde657901 196 /* Wait for software reset */
mbed_official 87:085cde657901 197 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 87:085cde657901 198 {
mbed_official 87:085cde657901 199 }
mbed_official 87:085cde657901 200
mbed_official 87:085cde657901 201 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 87:085cde657901 202 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 203 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 87:085cde657901 204 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 87:085cde657901 205 tmpreg &= MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 /* Get hclk frequency value */
mbed_official 87:085cde657901 208 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 87:085cde657901 209
mbed_official 87:085cde657901 210 /* Set CR bits depending on hclk value */
mbed_official 87:085cde657901 211 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 87:085cde657901 212 {
mbed_official 87:085cde657901 213 /* CSR Clock Range between 20-35 MHz */
mbed_official 87:085cde657901 214 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 87:085cde657901 215 }
mbed_official 87:085cde657901 216 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 87:085cde657901 217 {
mbed_official 87:085cde657901 218 /* CSR Clock Range between 35-60 MHz */
mbed_official 87:085cde657901 219 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 87:085cde657901 220 }
mbed_official 87:085cde657901 221 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 87:085cde657901 222 {
mbed_official 87:085cde657901 223 /* CSR Clock Range between 60-100 MHz */
mbed_official 87:085cde657901 224 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 87:085cde657901 225 }
mbed_official 87:085cde657901 226 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 87:085cde657901 227 {
mbed_official 87:085cde657901 228 /* CSR Clock Range between 100-150 MHz */
mbed_official 87:085cde657901 229 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 87:085cde657901 230 }
mbed_official 87:085cde657901 231 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 87:085cde657901 232 {
mbed_official 87:085cde657901 233 /* CSR Clock Range between 150-168 MHz */
mbed_official 87:085cde657901 234 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 87:085cde657901 235 }
mbed_official 87:085cde657901 236
mbed_official 87:085cde657901 237 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 87:085cde657901 238 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 239
mbed_official 87:085cde657901 240 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 87:085cde657901 241 /* Put the PHY in reset mode */
mbed_official 87:085cde657901 242 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 87:085cde657901 243 {
mbed_official 87:085cde657901 244 /* In case of write timeout */
mbed_official 87:085cde657901 245 err = ETH_ERROR;
mbed_official 87:085cde657901 246
mbed_official 87:085cde657901 247 /* Config MAC and DMA */
mbed_official 87:085cde657901 248 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 249
mbed_official 87:085cde657901 250 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 251 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 252
mbed_official 87:085cde657901 253 /* Return HAL_ERROR */
mbed_official 87:085cde657901 254 return HAL_ERROR;
mbed_official 87:085cde657901 255 }
mbed_official 87:085cde657901 256
mbed_official 87:085cde657901 257 /* Delay to assure PHY reset */
mbed_official 87:085cde657901 258 HAL_Delay(PHY_RESET_DELAY);
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 87:085cde657901 261 {
mbed_official 87:085cde657901 262 /* We wait for linked status */
mbed_official 87:085cde657901 263 do
mbed_official 87:085cde657901 264 {
mbed_official 87:085cde657901 265 timeout++;
mbed_official 87:085cde657901 266 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 87:085cde657901 267 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 268
mbed_official 87:085cde657901 269 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 270 {
mbed_official 87:085cde657901 271 /* In case of write timeout */
mbed_official 87:085cde657901 272 err = ETH_ERROR;
mbed_official 87:085cde657901 273
mbed_official 87:085cde657901 274 /* Config MAC and DMA */
mbed_official 87:085cde657901 275 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 276
mbed_official 87:085cde657901 277 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 278 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 279
mbed_official 87:085cde657901 280 /* Return HAL_ERROR */
mbed_official 87:085cde657901 281 return HAL_ERROR;
mbed_official 87:085cde657901 282 }
mbed_official 87:085cde657901 283
mbed_official 87:085cde657901 284 /* Reset Timeout counter */
mbed_official 87:085cde657901 285 timeout = 0;
mbed_official 87:085cde657901 286
mbed_official 87:085cde657901 287 /* Enable Auto-Negotiation */
mbed_official 87:085cde657901 288 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 87:085cde657901 289 {
mbed_official 87:085cde657901 290 /* In case of write timeout */
mbed_official 87:085cde657901 291 err = ETH_ERROR;
mbed_official 87:085cde657901 292
mbed_official 87:085cde657901 293 /* Config MAC and DMA */
mbed_official 87:085cde657901 294 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 295
mbed_official 87:085cde657901 296 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 297 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 /* Return HAL_ERROR */
mbed_official 87:085cde657901 300 return HAL_ERROR;
mbed_official 87:085cde657901 301 }
mbed_official 87:085cde657901 302
mbed_official 87:085cde657901 303 /* Wait until the auto-negotiation will be completed */
mbed_official 87:085cde657901 304 do
mbed_official 87:085cde657901 305 {
mbed_official 87:085cde657901 306 timeout++;
mbed_official 87:085cde657901 307 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 87:085cde657901 308 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 309
mbed_official 87:085cde657901 310 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 311 {
mbed_official 87:085cde657901 312 /* In case of timeout */
mbed_official 87:085cde657901 313 err = ETH_ERROR;
mbed_official 87:085cde657901 314
mbed_official 87:085cde657901 315 /* Config MAC and DMA */
mbed_official 87:085cde657901 316 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 317
mbed_official 87:085cde657901 318 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 319 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 320
mbed_official 87:085cde657901 321 /* Return HAL_ERROR */
mbed_official 87:085cde657901 322 return HAL_ERROR;
mbed_official 87:085cde657901 323 }
mbed_official 87:085cde657901 324
mbed_official 87:085cde657901 325 /* Reset Timeout counter */
mbed_official 87:085cde657901 326 timeout = 0;
mbed_official 87:085cde657901 327
mbed_official 87:085cde657901 328 /* Read the result of the auto-negotiation */
mbed_official 87:085cde657901 329 HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
mbed_official 87:085cde657901 330
mbed_official 87:085cde657901 331 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 87:085cde657901 332 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 333 {
mbed_official 87:085cde657901 334 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 87:085cde657901 335 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 336 }
mbed_official 87:085cde657901 337 else
mbed_official 87:085cde657901 338 {
mbed_official 87:085cde657901 339 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 87:085cde657901 340 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 87:085cde657901 341 }
mbed_official 87:085cde657901 342 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 87:085cde657901 343 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 87:085cde657901 344 {
mbed_official 87:085cde657901 345 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 87:085cde657901 346 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 87:085cde657901 347 }
mbed_official 87:085cde657901 348 else
mbed_official 87:085cde657901 349 {
mbed_official 87:085cde657901 350 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 87:085cde657901 351 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 352 }
mbed_official 87:085cde657901 353 }
mbed_official 87:085cde657901 354 else /* AutoNegotiation Disable */
mbed_official 87:085cde657901 355 {
mbed_official 87:085cde657901 356 /* Check parameters */
mbed_official 87:085cde657901 357 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 358 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 359
mbed_official 87:085cde657901 360 /* Set MAC Speed and Duplex Mode */
mbed_official 87:085cde657901 361 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 87:085cde657901 362 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 87:085cde657901 363 {
mbed_official 87:085cde657901 364 /* In case of write timeout */
mbed_official 87:085cde657901 365 err = ETH_ERROR;
mbed_official 87:085cde657901 366
mbed_official 87:085cde657901 367 /* Config MAC and DMA */
mbed_official 87:085cde657901 368 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 369
mbed_official 87:085cde657901 370 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 371 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 372
mbed_official 87:085cde657901 373 /* Return HAL_ERROR */
mbed_official 87:085cde657901 374 return HAL_ERROR;
mbed_official 87:085cde657901 375 }
mbed_official 87:085cde657901 376
mbed_official 87:085cde657901 377 /* Delay to assure PHY configuration */
mbed_official 87:085cde657901 378 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 87:085cde657901 379 }
mbed_official 87:085cde657901 380
mbed_official 87:085cde657901 381 /* Config MAC and DMA */
mbed_official 87:085cde657901 382 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 383
mbed_official 87:085cde657901 384 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 385 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 /* Return function status */
mbed_official 87:085cde657901 388 return HAL_OK;
mbed_official 87:085cde657901 389 }
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391 /**
mbed_official 87:085cde657901 392 * @brief De-Initializes the ETH peripheral.
mbed_official 226:b062af740e40 393 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 394 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 395 * @retval HAL status
mbed_official 87:085cde657901 396 */
mbed_official 87:085cde657901 397 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 398 {
mbed_official 87:085cde657901 399 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 400 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 401
mbed_official 87:085cde657901 402 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 403 HAL_ETH_MspDeInit(heth);
mbed_official 87:085cde657901 404
mbed_official 87:085cde657901 405 /* Set ETH HAL state to Disabled */
mbed_official 87:085cde657901 406 heth->State= HAL_ETH_STATE_RESET;
mbed_official 106:ced8cbb51063 407
mbed_official 106:ced8cbb51063 408 /* Release Lock */
mbed_official 106:ced8cbb51063 409 __HAL_UNLOCK(heth);
mbed_official 106:ced8cbb51063 410
mbed_official 87:085cde657901 411 /* Return function status */
mbed_official 87:085cde657901 412 return HAL_OK;
mbed_official 87:085cde657901 413 }
mbed_official 87:085cde657901 414
mbed_official 87:085cde657901 415 /**
mbed_official 87:085cde657901 416 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 226:b062af740e40 417 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 418 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 419 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 87:085cde657901 420 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 87:085cde657901 421 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 87:085cde657901 422 * @retval HAL status
mbed_official 87:085cde657901 423 */
mbed_official 87:085cde657901 424 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 87:085cde657901 425 {
mbed_official 87:085cde657901 426 uint32_t i = 0;
mbed_official 87:085cde657901 427 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 87:085cde657901 428
mbed_official 87:085cde657901 429 /* Process Locked */
mbed_official 87:085cde657901 430 __HAL_LOCK(heth);
mbed_official 87:085cde657901 431
mbed_official 87:085cde657901 432 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 433 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 434
mbed_official 87:085cde657901 435 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 87:085cde657901 436 heth->TxDesc = DMATxDescTab;
mbed_official 87:085cde657901 437
mbed_official 87:085cde657901 438 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 87:085cde657901 439 for(i=0; i < TxBuffCount; i++)
mbed_official 87:085cde657901 440 {
mbed_official 87:085cde657901 441 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 87:085cde657901 442 dmatxdesc = DMATxDescTab + i;
mbed_official 87:085cde657901 443
mbed_official 87:085cde657901 444 /* Set Second Address Chained bit */
mbed_official 87:085cde657901 445 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 87:085cde657901 446
mbed_official 87:085cde657901 447 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 448 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 87:085cde657901 449
mbed_official 87:085cde657901 450 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 451 {
mbed_official 87:085cde657901 452 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 87:085cde657901 453 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 87:085cde657901 454 }
mbed_official 87:085cde657901 455
mbed_official 87:085cde657901 456 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 457 if(i < (TxBuffCount-1))
mbed_official 87:085cde657901 458 {
mbed_official 87:085cde657901 459 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 460 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 87:085cde657901 461 }
mbed_official 87:085cde657901 462 else
mbed_official 87:085cde657901 463 {
mbed_official 87:085cde657901 464 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 465 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 466 }
mbed_official 87:085cde657901 467 }
mbed_official 87:085cde657901 468
mbed_official 87:085cde657901 469 /* Set Transmit Descriptor List Address Register */
mbed_official 87:085cde657901 470 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 471
mbed_official 87:085cde657901 472 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 473 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 474
mbed_official 87:085cde657901 475 /* Process Unlocked */
mbed_official 87:085cde657901 476 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 477
mbed_official 87:085cde657901 478 /* Return function status */
mbed_official 87:085cde657901 479 return HAL_OK;
mbed_official 87:085cde657901 480 }
mbed_official 87:085cde657901 481
mbed_official 87:085cde657901 482 /**
mbed_official 87:085cde657901 483 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 226:b062af740e40 484 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 485 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 486 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 87:085cde657901 487 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 87:085cde657901 488 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 87:085cde657901 489 * @retval HAL status
mbed_official 87:085cde657901 490 */
mbed_official 87:085cde657901 491 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 87:085cde657901 492 {
mbed_official 87:085cde657901 493 uint32_t i = 0;
mbed_official 87:085cde657901 494 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 87:085cde657901 495
mbed_official 87:085cde657901 496 /* Process Locked */
mbed_official 87:085cde657901 497 __HAL_LOCK(heth);
mbed_official 87:085cde657901 498
mbed_official 87:085cde657901 499 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 500 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 501
mbed_official 87:085cde657901 502 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 87:085cde657901 503 heth->RxDesc = DMARxDescTab;
mbed_official 87:085cde657901 504
mbed_official 87:085cde657901 505 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 87:085cde657901 506 for(i=0; i < RxBuffCount; i++)
mbed_official 87:085cde657901 507 {
mbed_official 87:085cde657901 508 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 87:085cde657901 509 DMARxDesc = DMARxDescTab+i;
mbed_official 87:085cde657901 510
mbed_official 87:085cde657901 511 /* Set Own bit of the Rx descriptor Status */
mbed_official 87:085cde657901 512 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 87:085cde657901 513
mbed_official 87:085cde657901 514 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 87:085cde657901 515 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 87:085cde657901 516
mbed_official 87:085cde657901 517 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 518 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 87:085cde657901 519
mbed_official 87:085cde657901 520 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 521 {
mbed_official 87:085cde657901 522 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 87:085cde657901 523 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 87:085cde657901 524 }
mbed_official 87:085cde657901 525
mbed_official 87:085cde657901 526 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 527 if(i < (RxBuffCount-1))
mbed_official 87:085cde657901 528 {
mbed_official 87:085cde657901 529 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 530 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 87:085cde657901 531 }
mbed_official 87:085cde657901 532 else
mbed_official 87:085cde657901 533 {
mbed_official 87:085cde657901 534 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 535 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 87:085cde657901 536 }
mbed_official 87:085cde657901 537 }
mbed_official 87:085cde657901 538
mbed_official 87:085cde657901 539 /* Set Receive Descriptor List Address Register */
mbed_official 87:085cde657901 540 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 87:085cde657901 541
mbed_official 87:085cde657901 542 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 543 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 544
mbed_official 87:085cde657901 545 /* Process Unlocked */
mbed_official 87:085cde657901 546 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 547
mbed_official 87:085cde657901 548 /* Return function status */
mbed_official 87:085cde657901 549 return HAL_OK;
mbed_official 87:085cde657901 550 }
mbed_official 87:085cde657901 551
mbed_official 87:085cde657901 552 /**
mbed_official 87:085cde657901 553 * @brief Initializes the ETH MSP.
mbed_official 226:b062af740e40 554 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 555 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 556 * @retval None
mbed_official 87:085cde657901 557 */
mbed_official 87:085cde657901 558 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 559 {
mbed_official 87:085cde657901 560 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 561 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 87:085cde657901 562 */
mbed_official 87:085cde657901 563 }
mbed_official 87:085cde657901 564
mbed_official 87:085cde657901 565 /**
mbed_official 87:085cde657901 566 * @brief DeInitializes ETH MSP.
mbed_official 226:b062af740e40 567 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 568 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 569 * @retval None
mbed_official 87:085cde657901 570 */
mbed_official 87:085cde657901 571 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 572 {
mbed_official 87:085cde657901 573 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 574 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 575 */
mbed_official 87:085cde657901 576 }
mbed_official 87:085cde657901 577
mbed_official 87:085cde657901 578 /**
mbed_official 87:085cde657901 579 * @}
mbed_official 87:085cde657901 580 */
mbed_official 87:085cde657901 581
mbed_official 87:085cde657901 582 /** @defgroup ETH_Group2 IO operation functions
mbed_official 87:085cde657901 583 * @brief Data transfers functions
mbed_official 87:085cde657901 584 *
mbed_official 87:085cde657901 585 @verbatim
mbed_official 87:085cde657901 586 ==============================================================================
mbed_official 87:085cde657901 587 ##### IO operation functions #####
mbed_official 87:085cde657901 588 ==============================================================================
mbed_official 87:085cde657901 589 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 590 (+) Transmit a frame
mbed_official 87:085cde657901 591 HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 592 (+) Receive a frame
mbed_official 87:085cde657901 593 HAL_ETH_GetReceivedFrame();
mbed_official 87:085cde657901 594 HAL_ETH_GetReceivedFrame_IT();
mbed_official 87:085cde657901 595 (+) Read from an External PHY register
mbed_official 87:085cde657901 596 HAL_ETH_ReadPHYRegister();
mbed_official 226:b062af740e40 597 (+) Write to an External PHY register
mbed_official 87:085cde657901 598 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 599
mbed_official 87:085cde657901 600 @endverbatim
mbed_official 87:085cde657901 601
mbed_official 87:085cde657901 602 * @{
mbed_official 87:085cde657901 603 */
mbed_official 87:085cde657901 604
mbed_official 87:085cde657901 605 /**
mbed_official 87:085cde657901 606 * @brief Sends an Ethernet frame.
mbed_official 226:b062af740e40 607 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 608 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 609 * @param FrameLength: Amount of data to be sent
mbed_official 87:085cde657901 610 * @retval HAL status
mbed_official 87:085cde657901 611 */
mbed_official 87:085cde657901 612 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 87:085cde657901 613 {
mbed_official 87:085cde657901 614 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 87:085cde657901 615
mbed_official 87:085cde657901 616 /* Process Locked */
mbed_official 87:085cde657901 617 __HAL_LOCK(heth);
mbed_official 87:085cde657901 618
mbed_official 87:085cde657901 619 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 620 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 if (FrameLength == 0)
mbed_official 87:085cde657901 623 {
mbed_official 87:085cde657901 624 /* Set ETH HAL state to READY */
mbed_official 87:085cde657901 625 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 626
mbed_official 87:085cde657901 627 /* Process Unlocked */
mbed_official 87:085cde657901 628 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 629
mbed_official 87:085cde657901 630 return HAL_ERROR;
mbed_official 87:085cde657901 631 }
mbed_official 87:085cde657901 632
mbed_official 87:085cde657901 633 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 87:085cde657901 634 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 87:085cde657901 635 {
mbed_official 87:085cde657901 636 /* OWN bit set */
mbed_official 87:085cde657901 637 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 87:085cde657901 638
mbed_official 87:085cde657901 639 /* Process Unlocked */
mbed_official 87:085cde657901 640 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 641
mbed_official 87:085cde657901 642 return HAL_ERROR;
mbed_official 87:085cde657901 643 }
mbed_official 87:085cde657901 644
mbed_official 87:085cde657901 645 /* Get the number of needed Tx buffers for the current frame */
mbed_official 87:085cde657901 646 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 647 {
mbed_official 87:085cde657901 648 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 649 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 650 {
mbed_official 87:085cde657901 651 bufcount++;
mbed_official 87:085cde657901 652 }
mbed_official 87:085cde657901 653 }
mbed_official 87:085cde657901 654 else
mbed_official 87:085cde657901 655 {
mbed_official 87:085cde657901 656 bufcount = 1;
mbed_official 87:085cde657901 657 }
mbed_official 87:085cde657901 658 if (bufcount == 1)
mbed_official 87:085cde657901 659 {
mbed_official 87:085cde657901 660 /* Set LAST and FIRST segment */
mbed_official 87:085cde657901 661 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 662 /* Set frame size */
mbed_official 87:085cde657901 663 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 664 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 665 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 666 /* Point to next descriptor */
mbed_official 87:085cde657901 667 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 668 }
mbed_official 87:085cde657901 669 else
mbed_official 87:085cde657901 670 {
mbed_official 87:085cde657901 671 for (i=0; i< bufcount; i++)
mbed_official 87:085cde657901 672 {
mbed_official 87:085cde657901 673 /* Clear FIRST and LAST segment bits */
mbed_official 87:085cde657901 674 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 87:085cde657901 675
mbed_official 87:085cde657901 676 if (i == 0)
mbed_official 87:085cde657901 677 {
mbed_official 87:085cde657901 678 /* Setting the first segment bit */
mbed_official 87:085cde657901 679 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 87:085cde657901 680 }
mbed_official 87:085cde657901 681
mbed_official 87:085cde657901 682 /* Program size */
mbed_official 87:085cde657901 683 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 684
mbed_official 87:085cde657901 685 if (i == (bufcount-1))
mbed_official 87:085cde657901 686 {
mbed_official 87:085cde657901 687 /* Setting the last segment bit */
mbed_official 87:085cde657901 688 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 689 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 690 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 691 }
mbed_official 87:085cde657901 692
mbed_official 87:085cde657901 693 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 694 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 695 /* point to next descriptor */
mbed_official 87:085cde657901 696 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 697 }
mbed_official 87:085cde657901 698 }
mbed_official 87:085cde657901 699
mbed_official 87:085cde657901 700 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 87:085cde657901 701 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 702 {
mbed_official 87:085cde657901 703 /* Clear TBUS ETHERNET DMA flag */
mbed_official 87:085cde657901 704 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 87:085cde657901 705 /* Resume DMA transmission*/
mbed_official 87:085cde657901 706 (heth->Instance)->DMATPDR = 0;
mbed_official 87:085cde657901 707 }
mbed_official 87:085cde657901 708
mbed_official 87:085cde657901 709 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 710 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 711
mbed_official 87:085cde657901 712 /* Process Unlocked */
mbed_official 87:085cde657901 713 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 714
mbed_official 87:085cde657901 715 /* Return function status */
mbed_official 87:085cde657901 716 return HAL_OK;
mbed_official 87:085cde657901 717 }
mbed_official 87:085cde657901 718
mbed_official 87:085cde657901 719 /**
mbed_official 87:085cde657901 720 * @brief Checks for received frames.
mbed_official 226:b062af740e40 721 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 722 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 723 * @retval HAL status
mbed_official 87:085cde657901 724 */
mbed_official 87:085cde657901 725 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 726 {
mbed_official 87:085cde657901 727 uint32_t framelength = 0;
mbed_official 87:085cde657901 728
mbed_official 87:085cde657901 729 /* Process Locked */
mbed_official 87:085cde657901 730 __HAL_LOCK(heth);
mbed_official 87:085cde657901 731
mbed_official 87:085cde657901 732 /* Check the ETH state to BUSY */
mbed_official 87:085cde657901 733 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 734
mbed_official 87:085cde657901 735 /* Check if segment is not owned by DMA */
mbed_official 87:085cde657901 736 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 87:085cde657901 737 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 87:085cde657901 738 {
mbed_official 87:085cde657901 739 /* Check if last segment */
mbed_official 87:085cde657901 740 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 87:085cde657901 741 {
mbed_official 87:085cde657901 742 /* increment segment count */
mbed_official 87:085cde657901 743 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 744
mbed_official 87:085cde657901 745 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 746 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 87:085cde657901 747 {
mbed_official 87:085cde657901 748 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 87:085cde657901 749 }
mbed_official 87:085cde657901 750
mbed_official 87:085cde657901 751 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 752
mbed_official 87:085cde657901 753 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 754 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 755 heth->RxFrameInfos.length = framelength;
mbed_official 87:085cde657901 756
mbed_official 87:085cde657901 757 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 758 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 759 /* point to next descriptor */
mbed_official 87:085cde657901 760 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 87:085cde657901 761
mbed_official 87:085cde657901 762 /* Set HAL State to Ready */
mbed_official 87:085cde657901 763 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 764
mbed_official 87:085cde657901 765 /* Process Unlocked */
mbed_official 87:085cde657901 766 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 767
mbed_official 87:085cde657901 768 /* Return function status */
mbed_official 87:085cde657901 769 return HAL_OK;
mbed_official 87:085cde657901 770 }
mbed_official 87:085cde657901 771 /* Check if first segment */
mbed_official 87:085cde657901 772 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 87:085cde657901 773 {
mbed_official 87:085cde657901 774 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 775 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 87:085cde657901 776 (heth->RxFrameInfos).SegCount = 1;
mbed_official 87:085cde657901 777 /* Point to next descriptor */
mbed_official 87:085cde657901 778 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 779 }
mbed_official 87:085cde657901 780 /* Check if intermediate segment */
mbed_official 87:085cde657901 781 else
mbed_official 87:085cde657901 782 {
mbed_official 87:085cde657901 783 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 784 /* Point to next descriptor */
mbed_official 87:085cde657901 785 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 786 }
mbed_official 87:085cde657901 787 }
mbed_official 87:085cde657901 788
mbed_official 87:085cde657901 789 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 790 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 791
mbed_official 87:085cde657901 792 /* Process Unlocked */
mbed_official 87:085cde657901 793 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 794
mbed_official 87:085cde657901 795 return HAL_ERROR;
mbed_official 87:085cde657901 796 }
mbed_official 87:085cde657901 797
mbed_official 87:085cde657901 798 /**
mbed_official 87:085cde657901 799 * @brief Gets the Received frame in interrupt mode.
mbed_official 226:b062af740e40 800 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 801 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 802 * @retval HAL status
mbed_official 87:085cde657901 803 */
mbed_official 87:085cde657901 804 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 805 {
mbed_official 87:085cde657901 806 uint32_t descriptorscancounter = 0;
mbed_official 87:085cde657901 807
mbed_official 87:085cde657901 808 /* Process Locked */
mbed_official 87:085cde657901 809 __HAL_LOCK(heth);
mbed_official 87:085cde657901 810
mbed_official 87:085cde657901 811 /* Set ETH HAL State to BUSY */
mbed_official 87:085cde657901 812 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 813
mbed_official 87:085cde657901 814 /* Scan descriptors owned by CPU */
mbed_official 87:085cde657901 815 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 87:085cde657901 816 {
mbed_official 87:085cde657901 817 /* Just for security */
mbed_official 87:085cde657901 818 descriptorscancounter++;
mbed_official 87:085cde657901 819
mbed_official 87:085cde657901 820 /* Check if first segment in frame */
mbed_official 87:085cde657901 821 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 822 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 87:085cde657901 823 {
mbed_official 87:085cde657901 824 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 825 heth->RxFrameInfos.SegCount = 1;
mbed_official 87:085cde657901 826 /* Point to next descriptor */
mbed_official 87:085cde657901 827 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 828 }
mbed_official 87:085cde657901 829 /* Check if intermediate segment */
mbed_official 87:085cde657901 830 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 831 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 87:085cde657901 832 {
mbed_official 87:085cde657901 833 /* Increment segment count */
mbed_official 87:085cde657901 834 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 835 /* Point to next descriptor */
mbed_official 87:085cde657901 836 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 837 }
mbed_official 87:085cde657901 838 /* Should be last segment */
mbed_official 87:085cde657901 839 else
mbed_official 87:085cde657901 840 {
mbed_official 87:085cde657901 841 /* Last segment */
mbed_official 87:085cde657901 842 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 843
mbed_official 87:085cde657901 844 /* Increment segment count */
mbed_official 87:085cde657901 845 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 846
mbed_official 87:085cde657901 847 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 848 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 87:085cde657901 849 {
mbed_official 87:085cde657901 850 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 851 }
mbed_official 87:085cde657901 852
mbed_official 87:085cde657901 853 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 854 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 855
mbed_official 87:085cde657901 856 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 857 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 858
mbed_official 87:085cde657901 859 /* Point to next descriptor */
mbed_official 87:085cde657901 860 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 861
mbed_official 87:085cde657901 862 /* Set HAL State to Ready */
mbed_official 87:085cde657901 863 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 864
mbed_official 87:085cde657901 865 /* Process Unlocked */
mbed_official 87:085cde657901 866 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 867
mbed_official 87:085cde657901 868 /* Return function status */
mbed_official 87:085cde657901 869 return HAL_OK;
mbed_official 87:085cde657901 870 }
mbed_official 87:085cde657901 871 }
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 /* Set HAL State to Ready */
mbed_official 87:085cde657901 874 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 875
mbed_official 87:085cde657901 876 /* Process Unlocked */
mbed_official 87:085cde657901 877 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 878
mbed_official 87:085cde657901 879 /* Return function status */
mbed_official 87:085cde657901 880 return HAL_OK;
mbed_official 87:085cde657901 881 }
mbed_official 87:085cde657901 882
mbed_official 87:085cde657901 883 /**
mbed_official 87:085cde657901 884 * @brief This function handles ETH interrupt request.
mbed_official 226:b062af740e40 885 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 886 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 887 * @retval HAL status
mbed_official 87:085cde657901 888 */
mbed_official 87:085cde657901 889 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 890 {
mbed_official 87:085cde657901 891 /* Frame received */
mbed_official 87:085cde657901 892 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 87:085cde657901 893 {
mbed_official 87:085cde657901 894 /* Receive complete callback */
mbed_official 87:085cde657901 895 HAL_ETH_RxCpltCallback(heth);
mbed_official 87:085cde657901 896
mbed_official 87:085cde657901 897 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 106:ced8cbb51063 898 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 87:085cde657901 899
mbed_official 87:085cde657901 900 /* Set HAL State to Ready */
mbed_official 87:085cde657901 901 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 902
mbed_official 87:085cde657901 903 /* Process Unlocked */
mbed_official 87:085cde657901 904 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 905
mbed_official 87:085cde657901 906 }
mbed_official 87:085cde657901 907 /* Frame transmitted */
mbed_official 87:085cde657901 908 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 87:085cde657901 909 {
mbed_official 87:085cde657901 910 /* Transfer complete callback */
mbed_official 87:085cde657901 911 HAL_ETH_TxCpltCallback(heth);
mbed_official 87:085cde657901 912
mbed_official 87:085cde657901 913 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 106:ced8cbb51063 914 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 87:085cde657901 915
mbed_official 87:085cde657901 916 /* Set HAL State to Ready */
mbed_official 87:085cde657901 917 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 918
mbed_official 87:085cde657901 919 /* Process Unlocked */
mbed_official 87:085cde657901 920 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 921 }
mbed_official 87:085cde657901 922
mbed_official 87:085cde657901 923 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 924 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 87:085cde657901 925
mbed_official 87:085cde657901 926 /* ETH DMA Error */
mbed_official 87:085cde657901 927 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 87:085cde657901 928 {
mbed_official 87:085cde657901 929 /* Ethernet Error callback */
mbed_official 87:085cde657901 930 HAL_ETH_ErrorCallback(heth);
mbed_official 87:085cde657901 931
mbed_official 87:085cde657901 932 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 933 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 87:085cde657901 934
mbed_official 87:085cde657901 935 /* Set HAL State to Ready */
mbed_official 87:085cde657901 936 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 937
mbed_official 87:085cde657901 938 /* Process Unlocked */
mbed_official 87:085cde657901 939 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 940 }
mbed_official 87:085cde657901 941 }
mbed_official 87:085cde657901 942
mbed_official 87:085cde657901 943 /**
mbed_official 87:085cde657901 944 * @brief Tx Transfer completed callbacks.
mbed_official 226:b062af740e40 945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 946 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 947 * @retval None
mbed_official 87:085cde657901 948 */
mbed_official 87:085cde657901 949 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 950 {
mbed_official 87:085cde657901 951 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 952 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 953 */
mbed_official 87:085cde657901 954 }
mbed_official 87:085cde657901 955
mbed_official 87:085cde657901 956 /**
mbed_official 87:085cde657901 957 * @brief Rx Transfer completed callbacks.
mbed_official 226:b062af740e40 958 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 959 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 960 * @retval None
mbed_official 87:085cde657901 961 */
mbed_official 87:085cde657901 962 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 963 {
mbed_official 87:085cde657901 964 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 965 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 966 */
mbed_official 87:085cde657901 967 }
mbed_official 87:085cde657901 968
mbed_official 87:085cde657901 969 /**
mbed_official 87:085cde657901 970 * @brief Ethernet transfer error callbacks
mbed_official 226:b062af740e40 971 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 972 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 973 * @retval None
mbed_official 87:085cde657901 974 */
mbed_official 87:085cde657901 975 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 976 {
mbed_official 87:085cde657901 977 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 978 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 979 */
mbed_official 87:085cde657901 980 }
mbed_official 87:085cde657901 981
mbed_official 87:085cde657901 982 /**
mbed_official 87:085cde657901 983 * @brief Reads a PHY register
mbed_official 226:b062af740e40 984 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 985 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 986 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 987 * This parameter can be one of the following values:
mbed_official 226:b062af740e40 988 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 226:b062af740e40 989 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 226:b062af740e40 990 * More PHY register could be read depending on the used PHY
mbed_official 87:085cde657901 991 * @param RegValue: PHY register value
mbed_official 226:b062af740e40 992 * @retval HAL status
mbed_official 87:085cde657901 993 */
mbed_official 87:085cde657901 994 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 87:085cde657901 995 {
mbed_official 87:085cde657901 996 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 997 uint32_t timeout = 0;
mbed_official 87:085cde657901 998
mbed_official 87:085cde657901 999 /* Check parameters */
mbed_official 87:085cde657901 1000 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 1001
mbed_official 87:085cde657901 1002 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 1003 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 87:085cde657901 1004 {
mbed_official 87:085cde657901 1005 return HAL_BUSY;
mbed_official 87:085cde657901 1006 }
mbed_official 87:085cde657901 1007 /* Set ETH HAL State to BUSY_RD */
mbed_official 87:085cde657901 1008 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 87:085cde657901 1009
mbed_official 87:085cde657901 1010 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 1011 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1012
mbed_official 87:085cde657901 1013 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1014 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1015
mbed_official 87:085cde657901 1016 /* Prepare the MII address register value */
mbed_official 87:085cde657901 1017 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1018 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1019 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 87:085cde657901 1020 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1021
mbed_official 87:085cde657901 1022 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1023 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1024
mbed_official 87:085cde657901 1025 /* Check for the Busy flag */
mbed_official 87:085cde657901 1026 do
mbed_official 87:085cde657901 1027 {
mbed_official 87:085cde657901 1028 timeout++;
mbed_official 87:085cde657901 1029 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1030 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 1031
mbed_official 87:085cde657901 1032 /* Return ERROR in case of timeout */
mbed_official 87:085cde657901 1033 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 1034 {
mbed_official 87:085cde657901 1035 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1036 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1037 /* Return HAL_TIMEOUT */
mbed_official 87:085cde657901 1038 return HAL_TIMEOUT;
mbed_official 87:085cde657901 1039 }
mbed_official 87:085cde657901 1040
mbed_official 87:085cde657901 1041 /* Get MACMIIDR value */
mbed_official 87:085cde657901 1042 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 87:085cde657901 1043
mbed_official 87:085cde657901 1044 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1045 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1046
mbed_official 87:085cde657901 1047 /* Return function status */
mbed_official 87:085cde657901 1048 return HAL_OK;
mbed_official 87:085cde657901 1049 }
mbed_official 87:085cde657901 1050
mbed_official 87:085cde657901 1051 /**
mbed_official 87:085cde657901 1052 * @brief Writes to a PHY register.
mbed_official 226:b062af740e40 1053 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1054 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1055 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 1056 * This parameter can be one of the following values:
mbed_official 226:b062af740e40 1057 * PHY_BCR: Transceiver Control Register.
mbed_official 226:b062af740e40 1058 * More PHY register could be written depending on the used PHY
mbed_official 87:085cde657901 1059 * @param RegValue: the value to write
mbed_official 87:085cde657901 1060 * @retval HAL status
mbed_official 87:085cde657901 1061 */
mbed_official 87:085cde657901 1062 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 87:085cde657901 1063 {
mbed_official 87:085cde657901 1064 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1065 uint32_t timeout = 0;
mbed_official 87:085cde657901 1066
mbed_official 87:085cde657901 1067 /* Check parameters */
mbed_official 87:085cde657901 1068 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 1069
mbed_official 87:085cde657901 1070 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 1071 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 87:085cde657901 1072 {
mbed_official 87:085cde657901 1073 return HAL_BUSY;
mbed_official 87:085cde657901 1074 }
mbed_official 87:085cde657901 1075 /* Set ETH HAL State to BUSY_WR */
mbed_official 87:085cde657901 1076 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 87:085cde657901 1077
mbed_official 87:085cde657901 1078 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 1079 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1080
mbed_official 87:085cde657901 1081 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1082 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1083
mbed_official 87:085cde657901 1084 /* Prepare the MII register address value */
mbed_official 87:085cde657901 1085 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1086 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1087 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 87:085cde657901 1088 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1089
mbed_official 87:085cde657901 1090 /* Give the value to the MII data register */
mbed_official 87:085cde657901 1091 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 87:085cde657901 1092
mbed_official 87:085cde657901 1093 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1094 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1095
mbed_official 87:085cde657901 1096 /* Check for the Busy flag */
mbed_official 87:085cde657901 1097 do
mbed_official 87:085cde657901 1098 {
mbed_official 87:085cde657901 1099 timeout++;
mbed_official 87:085cde657901 1100 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1101 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
mbed_official 87:085cde657901 1102
mbed_official 87:085cde657901 1103 /* Return TIMETOUT in case of timeout */
mbed_official 87:085cde657901 1104 if(timeout == PHY_WRITE_TO)
mbed_official 87:085cde657901 1105 {
mbed_official 87:085cde657901 1106 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1107 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1108
mbed_official 87:085cde657901 1109 return HAL_TIMEOUT;
mbed_official 87:085cde657901 1110 }
mbed_official 87:085cde657901 1111
mbed_official 87:085cde657901 1112 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1113 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1114
mbed_official 87:085cde657901 1115 /* Return function status */
mbed_official 87:085cde657901 1116 return HAL_OK;
mbed_official 87:085cde657901 1117 }
mbed_official 87:085cde657901 1118
mbed_official 87:085cde657901 1119 /**
mbed_official 87:085cde657901 1120 * @}
mbed_official 87:085cde657901 1121 */
mbed_official 87:085cde657901 1122
mbed_official 87:085cde657901 1123 /** @defgroup ETH_Group3 Peripheral Control functions
mbed_official 87:085cde657901 1124 * @brief Peripheral Control functions
mbed_official 87:085cde657901 1125 *
mbed_official 87:085cde657901 1126 @verbatim
mbed_official 87:085cde657901 1127 ===============================================================================
mbed_official 87:085cde657901 1128 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 1129 ===============================================================================
mbed_official 87:085cde657901 1130 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 1131 (+) Enable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1132 HAL_ETH_Start();
mbed_official 87:085cde657901 1133 (+) Disable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1134 HAL_ETH_Stop();
mbed_official 87:085cde657901 1135 (+) Set the MAC configuration in runtime mode
mbed_official 87:085cde657901 1136 HAL_ETH_ConfigMAC();
mbed_official 87:085cde657901 1137 (+) Set the DMA configuration in runtime mode
mbed_official 87:085cde657901 1138 HAL_ETH_ConfigDMA();
mbed_official 87:085cde657901 1139
mbed_official 87:085cde657901 1140 @endverbatim
mbed_official 87:085cde657901 1141 * @{
mbed_official 87:085cde657901 1142 */
mbed_official 87:085cde657901 1143
mbed_official 87:085cde657901 1144 /**
mbed_official 87:085cde657901 1145 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 226:b062af740e40 1146 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1147 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1148 * @retval HAL status
mbed_official 87:085cde657901 1149 */
mbed_official 87:085cde657901 1150 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1151 {
mbed_official 87:085cde657901 1152 /* Process Locked */
mbed_official 87:085cde657901 1153 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1154
mbed_official 87:085cde657901 1155 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1156 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1157
mbed_official 87:085cde657901 1158 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1159 ETH_MACTransmissionEnable(heth);
mbed_official 87:085cde657901 1160
mbed_official 87:085cde657901 1161 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1162 ETH_MACReceptionEnable(heth);
mbed_official 87:085cde657901 1163
mbed_official 87:085cde657901 1164 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1165 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1166
mbed_official 87:085cde657901 1167 /* Start DMA transmission */
mbed_official 87:085cde657901 1168 ETH_DMATransmissionEnable(heth);
mbed_official 87:085cde657901 1169
mbed_official 87:085cde657901 1170 /* Start DMA reception */
mbed_official 87:085cde657901 1171 ETH_DMAReceptionEnable(heth);
mbed_official 87:085cde657901 1172
mbed_official 87:085cde657901 1173 /* Set the ETH state to READY*/
mbed_official 87:085cde657901 1174 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1175
mbed_official 87:085cde657901 1176 /* Process Unlocked */
mbed_official 87:085cde657901 1177 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1178
mbed_official 87:085cde657901 1179 /* Return function status */
mbed_official 87:085cde657901 1180 return HAL_OK;
mbed_official 87:085cde657901 1181 }
mbed_official 87:085cde657901 1182
mbed_official 87:085cde657901 1183 /**
mbed_official 87:085cde657901 1184 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 226:b062af740e40 1185 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1186 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1187 * @retval HAL status
mbed_official 87:085cde657901 1188 */
mbed_official 87:085cde657901 1189 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1190 {
mbed_official 87:085cde657901 1191 /* Process Locked */
mbed_official 87:085cde657901 1192 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1193
mbed_official 87:085cde657901 1194 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1195 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1196
mbed_official 87:085cde657901 1197 /* Stop DMA transmission */
mbed_official 87:085cde657901 1198 ETH_DMATransmissionDisable(heth);
mbed_official 87:085cde657901 1199
mbed_official 87:085cde657901 1200 /* Stop DMA reception */
mbed_official 87:085cde657901 1201 ETH_DMAReceptionDisable(heth);
mbed_official 87:085cde657901 1202
mbed_official 87:085cde657901 1203 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1204 ETH_MACReceptionDisable(heth);
mbed_official 87:085cde657901 1205
mbed_official 87:085cde657901 1206 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1207 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1208
mbed_official 87:085cde657901 1209 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1210 ETH_MACTransmissionDisable(heth);
mbed_official 87:085cde657901 1211
mbed_official 87:085cde657901 1212 /* Set the ETH state*/
mbed_official 87:085cde657901 1213 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1214
mbed_official 87:085cde657901 1215 /* Process Unlocked */
mbed_official 87:085cde657901 1216 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1217
mbed_official 87:085cde657901 1218 /* Return function status */
mbed_official 87:085cde657901 1219 return HAL_OK;
mbed_official 87:085cde657901 1220 }
mbed_official 87:085cde657901 1221
mbed_official 87:085cde657901 1222 /**
mbed_official 87:085cde657901 1223 * @brief Set ETH MAC Configuration.
mbed_official 226:b062af740e40 1224 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1225 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1226 * @param macconf: MAC Configuration structure
mbed_official 87:085cde657901 1227 * @retval HAL status
mbed_official 87:085cde657901 1228 */
mbed_official 87:085cde657901 1229 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 87:085cde657901 1230 {
mbed_official 87:085cde657901 1231 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1232
mbed_official 87:085cde657901 1233 /* Process Locked */
mbed_official 87:085cde657901 1234 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1235
mbed_official 87:085cde657901 1236 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1237 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1238
mbed_official 87:085cde657901 1239 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 1240 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 1241
mbed_official 87:085cde657901 1242 if (macconf != NULL)
mbed_official 87:085cde657901 1243 {
mbed_official 87:085cde657901 1244 /* Check the parameters */
mbed_official 87:085cde657901 1245 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 87:085cde657901 1246 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 87:085cde657901 1247 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 87:085cde657901 1248 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 87:085cde657901 1249 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 87:085cde657901 1250 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 87:085cde657901 1251 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 87:085cde657901 1252 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 87:085cde657901 1253 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 87:085cde657901 1254 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 87:085cde657901 1255 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 87:085cde657901 1256 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 87:085cde657901 1257 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 87:085cde657901 1258 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 87:085cde657901 1259 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 87:085cde657901 1260 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 87:085cde657901 1261 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official 87:085cde657901 1262 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 87:085cde657901 1263 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 87:085cde657901 1264 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 87:085cde657901 1265 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 87:085cde657901 1266 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 87:085cde657901 1267 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 87:085cde657901 1268 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 87:085cde657901 1269 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 87:085cde657901 1270 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 87:085cde657901 1271 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 87:085cde657901 1272
mbed_official 87:085cde657901 1273 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1274 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1275 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1276 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1277 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1278
mbed_official 87:085cde657901 1279 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 87:085cde657901 1280 macconf->Jabber |
mbed_official 87:085cde657901 1281 macconf->InterFrameGap |
mbed_official 87:085cde657901 1282 macconf->CarrierSense |
mbed_official 87:085cde657901 1283 (heth->Init).Speed |
mbed_official 87:085cde657901 1284 macconf->ReceiveOwn |
mbed_official 87:085cde657901 1285 macconf->LoopbackMode |
mbed_official 87:085cde657901 1286 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1287 macconf->ChecksumOffload |
mbed_official 87:085cde657901 1288 macconf->RetryTransmission |
mbed_official 87:085cde657901 1289 macconf->AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1290 macconf->BackOffLimit |
mbed_official 87:085cde657901 1291 macconf->DeferralCheck);
mbed_official 87:085cde657901 1292
mbed_official 87:085cde657901 1293 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1294 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1295
mbed_official 87:085cde657901 1296 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1297 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1298 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1299 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1300 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1301
mbed_official 87:085cde657901 1302 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1303 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1304 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 87:085cde657901 1305 macconf->SourceAddrFilter |
mbed_official 87:085cde657901 1306 macconf->PassControlFrames |
mbed_official 87:085cde657901 1307 macconf->BroadcastFramesReception |
mbed_official 87:085cde657901 1308 macconf->DestinationAddrFilter |
mbed_official 87:085cde657901 1309 macconf->PromiscuousMode |
mbed_official 87:085cde657901 1310 macconf->MulticastFramesFilter |
mbed_official 87:085cde657901 1311 macconf->UnicastFramesFilter);
mbed_official 87:085cde657901 1312
mbed_official 87:085cde657901 1313 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1314 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1315 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1316 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1317 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1318
mbed_official 87:085cde657901 1319 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 87:085cde657901 1320 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1321 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 87:085cde657901 1322
mbed_official 87:085cde657901 1323 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1324 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 87:085cde657901 1325 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 87:085cde657901 1326
mbed_official 87:085cde657901 1327 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1328 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1329 /* Clear xx bits */
mbed_official 87:085cde657901 1330 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1331
mbed_official 87:085cde657901 1332 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 87:085cde657901 1333 macconf->ZeroQuantaPause |
mbed_official 87:085cde657901 1334 macconf->PauseLowThreshold |
mbed_official 87:085cde657901 1335 macconf->UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1336 macconf->ReceiveFlowControl |
mbed_official 87:085cde657901 1337 macconf->TransmitFlowControl);
mbed_official 87:085cde657901 1338
mbed_official 87:085cde657901 1339 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1340 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1341
mbed_official 87:085cde657901 1342 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1343 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1344 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1346 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1347
mbed_official 87:085cde657901 1348 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 87:085cde657901 1349 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 87:085cde657901 1350 macconf->VLANTagIdentifier);
mbed_official 87:085cde657901 1351
mbed_official 87:085cde657901 1352 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1353 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1354 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1355 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1356 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1357 }
mbed_official 87:085cde657901 1358 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 87:085cde657901 1359 {
mbed_official 87:085cde657901 1360 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1361 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1362 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1363
mbed_official 87:085cde657901 1364 /* Clear FES and DM bits */
mbed_official 87:085cde657901 1365 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 87:085cde657901 1366
mbed_official 87:085cde657901 1367 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 87:085cde657901 1368
mbed_official 87:085cde657901 1369 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1370 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1371
mbed_official 87:085cde657901 1372 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1373 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1374 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1375 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1376 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1377 }
mbed_official 87:085cde657901 1378
mbed_official 87:085cde657901 1379 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1380 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1381
mbed_official 87:085cde657901 1382 /* Process Unlocked */
mbed_official 87:085cde657901 1383 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1384
mbed_official 87:085cde657901 1385 /* Return function status */
mbed_official 87:085cde657901 1386 return HAL_OK;
mbed_official 87:085cde657901 1387 }
mbed_official 87:085cde657901 1388
mbed_official 87:085cde657901 1389 /**
mbed_official 87:085cde657901 1390 * @brief Sets ETH DMA Configuration.
mbed_official 226:b062af740e40 1391 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1392 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1393 * @param dmaconf: DMA Configuration structure
mbed_official 87:085cde657901 1394 * @retval HAL status
mbed_official 87:085cde657901 1395 */
mbed_official 87:085cde657901 1396 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 87:085cde657901 1397 {
mbed_official 87:085cde657901 1398 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1399
mbed_official 87:085cde657901 1400 /* Process Locked */
mbed_official 87:085cde657901 1401 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1402
mbed_official 87:085cde657901 1403 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1404 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1405
mbed_official 87:085cde657901 1406 /* Check parameters */
mbed_official 87:085cde657901 1407 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 87:085cde657901 1408 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 87:085cde657901 1409 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 87:085cde657901 1410 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 87:085cde657901 1411 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 87:085cde657901 1412 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 87:085cde657901 1413 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 87:085cde657901 1414 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 87:085cde657901 1415 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 87:085cde657901 1416 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 87:085cde657901 1417 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 87:085cde657901 1418 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 87:085cde657901 1419 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 87:085cde657901 1420 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 87:085cde657901 1421 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 87:085cde657901 1422 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 87:085cde657901 1423
mbed_official 87:085cde657901 1424 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 87:085cde657901 1425 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1426 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1427 /* Clear xx bits */
mbed_official 87:085cde657901 1428 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1429
mbed_official 87:085cde657901 1430 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1431 dmaconf->ReceiveStoreForward |
mbed_official 87:085cde657901 1432 dmaconf->FlushReceivedFrame |
mbed_official 87:085cde657901 1433 dmaconf->TransmitStoreForward |
mbed_official 87:085cde657901 1434 dmaconf->TransmitThresholdControl |
mbed_official 87:085cde657901 1435 dmaconf->ForwardErrorFrames |
mbed_official 87:085cde657901 1436 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1437 dmaconf->ReceiveThresholdControl |
mbed_official 87:085cde657901 1438 dmaconf->SecondFrameOperate);
mbed_official 87:085cde657901 1439
mbed_official 87:085cde657901 1440 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1441 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1442
mbed_official 87:085cde657901 1443 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1444 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1445 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1446 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1447 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1448
mbed_official 87:085cde657901 1449 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 87:085cde657901 1450 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 87:085cde657901 1451 dmaconf->FixedBurst |
mbed_official 87:085cde657901 1452 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1453 dmaconf->TxDMABurstLength |
mbed_official 87:085cde657901 1454 dmaconf->EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1455 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1456 dmaconf->DMAArbitration |
mbed_official 87:085cde657901 1457 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1458
mbed_official 87:085cde657901 1459 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1460 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1461 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1462 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1463 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1464
mbed_official 87:085cde657901 1465 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1466 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1467
mbed_official 87:085cde657901 1468 /* Process Unlocked */
mbed_official 87:085cde657901 1469 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1470
mbed_official 87:085cde657901 1471 /* Return function status */
mbed_official 87:085cde657901 1472 return HAL_OK;
mbed_official 87:085cde657901 1473 }
mbed_official 87:085cde657901 1474
mbed_official 87:085cde657901 1475 /**
mbed_official 87:085cde657901 1476 * @}
mbed_official 87:085cde657901 1477 */
mbed_official 87:085cde657901 1478
mbed_official 87:085cde657901 1479 /** @defgroup ETH_Group4 Peripheral State functions
mbed_official 87:085cde657901 1480 * @brief Peripheral State functions
mbed_official 87:085cde657901 1481 *
mbed_official 87:085cde657901 1482 @verbatim
mbed_official 87:085cde657901 1483 ===============================================================================
mbed_official 87:085cde657901 1484 ##### Peripheral State functions #####
mbed_official 87:085cde657901 1485 ===============================================================================
mbed_official 87:085cde657901 1486 [..]
mbed_official 87:085cde657901 1487 This subsection permits to get in run-time the status of the peripheral
mbed_official 87:085cde657901 1488 and the data flow.
mbed_official 87:085cde657901 1489 (+) Get the ETH handle state:
mbed_official 87:085cde657901 1490 HAL_ETH_GetState();
mbed_official 87:085cde657901 1491
mbed_official 87:085cde657901 1492
mbed_official 87:085cde657901 1493 @endverbatim
mbed_official 87:085cde657901 1494 * @{
mbed_official 87:085cde657901 1495 */
mbed_official 87:085cde657901 1496
mbed_official 87:085cde657901 1497 /**
mbed_official 87:085cde657901 1498 * @brief Return the ETH HAL state
mbed_official 226:b062af740e40 1499 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1500 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1501 * @retval HAL state
mbed_official 87:085cde657901 1502 */
mbed_official 87:085cde657901 1503 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1504 {
mbed_official 87:085cde657901 1505 /* Return ETH state */
mbed_official 87:085cde657901 1506 return heth->State;
mbed_official 87:085cde657901 1507 }
mbed_official 87:085cde657901 1508
mbed_official 87:085cde657901 1509 /**
mbed_official 87:085cde657901 1510 * @}
mbed_official 87:085cde657901 1511 */
mbed_official 87:085cde657901 1512
mbed_official 87:085cde657901 1513 /**
mbed_official 87:085cde657901 1514 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 226:b062af740e40 1515 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1516 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1517 * @param err: Ethernet Init error
mbed_official 87:085cde657901 1518 * @retval HAL status
mbed_official 87:085cde657901 1519 */
mbed_official 87:085cde657901 1520 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 87:085cde657901 1521 {
mbed_official 87:085cde657901 1522 ETH_MACInitTypeDef macinit;
mbed_official 87:085cde657901 1523 ETH_DMAInitTypeDef dmainit;
mbed_official 87:085cde657901 1524 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1525
mbed_official 87:085cde657901 1526 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 87:085cde657901 1527 {
mbed_official 87:085cde657901 1528 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 87:085cde657901 1529 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 1530
mbed_official 87:085cde657901 1531 /* Set Ethernet speed to 100M */
mbed_official 87:085cde657901 1532 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 1533 }
mbed_official 87:085cde657901 1534
mbed_official 87:085cde657901 1535 /* Ethernet MAC default initialization **************************************/
mbed_official 87:085cde657901 1536 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 87:085cde657901 1537 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 87:085cde657901 1538 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 87:085cde657901 1539 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 87:085cde657901 1540 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 87:085cde657901 1541 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 87:085cde657901 1542 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 1543 {
mbed_official 87:085cde657901 1544 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 87:085cde657901 1545 }
mbed_official 87:085cde657901 1546 else
mbed_official 87:085cde657901 1547 {
mbed_official 87:085cde657901 1548 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 87:085cde657901 1549 }
mbed_official 87:085cde657901 1550 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 87:085cde657901 1551 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 87:085cde657901 1552 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 87:085cde657901 1553 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 87:085cde657901 1554 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 87:085cde657901 1555 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 87:085cde657901 1556 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 87:085cde657901 1557 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 87:085cde657901 1558 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 87:085cde657901 1559 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official 87:085cde657901 1560 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1561 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1562 macinit.HashTableHigh = 0x0;
mbed_official 87:085cde657901 1563 macinit.HashTableLow = 0x0;
mbed_official 87:085cde657901 1564 macinit.PauseTime = 0x0;
mbed_official 87:085cde657901 1565 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 87:085cde657901 1566 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 87:085cde657901 1567 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 87:085cde657901 1568 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1569 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1570 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 87:085cde657901 1571 macinit.VLANTagIdentifier = 0x0;
mbed_official 87:085cde657901 1572
mbed_official 87:085cde657901 1573 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1574 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1575 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1576 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1577 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1578 /* Set the WD bit according to ETH Watchdog value */
mbed_official 87:085cde657901 1579 /* Set the JD: bit according to ETH Jabber value */
mbed_official 87:085cde657901 1580 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 87:085cde657901 1581 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 87:085cde657901 1582 /* Set the FES bit according to ETH Speed value */
mbed_official 87:085cde657901 1583 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 87:085cde657901 1584 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 87:085cde657901 1585 /* Set the DM bit according to ETH Mode value */
mbed_official 87:085cde657901 1586 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 87:085cde657901 1587 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 87:085cde657901 1588 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 87:085cde657901 1589 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 87:085cde657901 1590 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 87:085cde657901 1591 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 87:085cde657901 1592 macinit.Jabber |
mbed_official 87:085cde657901 1593 macinit.InterFrameGap |
mbed_official 87:085cde657901 1594 macinit.CarrierSense |
mbed_official 87:085cde657901 1595 (heth->Init).Speed |
mbed_official 87:085cde657901 1596 macinit.ReceiveOwn |
mbed_official 87:085cde657901 1597 macinit.LoopbackMode |
mbed_official 87:085cde657901 1598 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1599 macinit.ChecksumOffload |
mbed_official 87:085cde657901 1600 macinit.RetryTransmission |
mbed_official 87:085cde657901 1601 macinit.AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1602 macinit.BackOffLimit |
mbed_official 87:085cde657901 1603 macinit.DeferralCheck);
mbed_official 87:085cde657901 1604
mbed_official 87:085cde657901 1605 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1606 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1607
mbed_official 87:085cde657901 1608 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1609 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1610 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1611 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1612 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1613
mbed_official 87:085cde657901 1614 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1615 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 87:085cde657901 1616 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 87:085cde657901 1617 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 87:085cde657901 1618 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 87:085cde657901 1619 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 87:085cde657901 1620 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 87:085cde657901 1621 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 87:085cde657901 1622 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 87:085cde657901 1623 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1624 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 87:085cde657901 1625 macinit.SourceAddrFilter |
mbed_official 87:085cde657901 1626 macinit.PassControlFrames |
mbed_official 87:085cde657901 1627 macinit.BroadcastFramesReception |
mbed_official 87:085cde657901 1628 macinit.DestinationAddrFilter |
mbed_official 87:085cde657901 1629 macinit.PromiscuousMode |
mbed_official 87:085cde657901 1630 macinit.MulticastFramesFilter |
mbed_official 87:085cde657901 1631 macinit.UnicastFramesFilter);
mbed_official 87:085cde657901 1632
mbed_official 87:085cde657901 1633 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1634 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1635 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1636 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1637 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1638
mbed_official 87:085cde657901 1639 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 87:085cde657901 1640 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1641 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 87:085cde657901 1642
mbed_official 87:085cde657901 1643 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1644 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 87:085cde657901 1645 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 87:085cde657901 1646
mbed_official 87:085cde657901 1647 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1648 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1649 /* Clear xx bits */
mbed_official 87:085cde657901 1650 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1651
mbed_official 87:085cde657901 1652 /* Set the PT bit according to ETH PauseTime value */
mbed_official 87:085cde657901 1653 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 87:085cde657901 1654 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 87:085cde657901 1655 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 87:085cde657901 1656 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 87:085cde657901 1657 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 87:085cde657901 1658 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 87:085cde657901 1659 macinit.ZeroQuantaPause |
mbed_official 87:085cde657901 1660 macinit.PauseLowThreshold |
mbed_official 87:085cde657901 1661 macinit.UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1662 macinit.ReceiveFlowControl |
mbed_official 87:085cde657901 1663 macinit.TransmitFlowControl);
mbed_official 87:085cde657901 1664
mbed_official 87:085cde657901 1665 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1666 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1667
mbed_official 87:085cde657901 1668 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1669 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1670 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1671 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1672 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1673
mbed_official 87:085cde657901 1674 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 87:085cde657901 1675 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 87:085cde657901 1676 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 87:085cde657901 1677 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 87:085cde657901 1678 macinit.VLANTagIdentifier);
mbed_official 87:085cde657901 1679
mbed_official 87:085cde657901 1680 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1681 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1682 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1683 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1684 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1685
mbed_official 87:085cde657901 1686 /* Ethernet DMA default initialization ************************************/
mbed_official 87:085cde657901 1687 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 87:085cde657901 1688 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1689 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 87:085cde657901 1690 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1691 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1692 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 87:085cde657901 1693 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 87:085cde657901 1694 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1695 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 87:085cde657901 1696 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 87:085cde657901 1697 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 87:085cde657901 1698 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1699 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1700 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 87:085cde657901 1701 dmainit.DescriptorSkipLength = 0x0;
mbed_official 87:085cde657901 1702 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 87:085cde657901 1703
mbed_official 87:085cde657901 1704 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1705 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1706 /* Clear xx bits */
mbed_official 87:085cde657901 1707 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1708
mbed_official 87:085cde657901 1709 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 87:085cde657901 1710 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 87:085cde657901 1711 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 87:085cde657901 1712 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 87:085cde657901 1713 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 87:085cde657901 1714 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 87:085cde657901 1715 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 87:085cde657901 1716 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 87:085cde657901 1717 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 87:085cde657901 1718 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1719 dmainit.ReceiveStoreForward |
mbed_official 87:085cde657901 1720 dmainit.FlushReceivedFrame |
mbed_official 87:085cde657901 1721 dmainit.TransmitStoreForward |
mbed_official 87:085cde657901 1722 dmainit.TransmitThresholdControl |
mbed_official 87:085cde657901 1723 dmainit.ForwardErrorFrames |
mbed_official 87:085cde657901 1724 dmainit.ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1725 dmainit.ReceiveThresholdControl |
mbed_official 87:085cde657901 1726 dmainit.SecondFrameOperate);
mbed_official 87:085cde657901 1727
mbed_official 87:085cde657901 1728 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1729 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1730
mbed_official 87:085cde657901 1731 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1732 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1733 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1734 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1735 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1736
mbed_official 87:085cde657901 1737 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 87:085cde657901 1738 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 87:085cde657901 1739 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 87:085cde657901 1740 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 87:085cde657901 1741 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 87:085cde657901 1742 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 87:085cde657901 1743 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 87:085cde657901 1744 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 87:085cde657901 1745 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 87:085cde657901 1746 dmainit.FixedBurst |
mbed_official 87:085cde657901 1747 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1748 dmainit.TxDMABurstLength |
mbed_official 87:085cde657901 1749 dmainit.EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1750 (dmainit.DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1751 dmainit.DMAArbitration |
mbed_official 87:085cde657901 1752 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1753
mbed_official 87:085cde657901 1754 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1755 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1756 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1757 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1758 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1759
mbed_official 87:085cde657901 1760 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 1761 {
mbed_official 87:085cde657901 1762 /* Enable the Ethernet Rx Interrupt */
mbed_official 87:085cde657901 1763 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 87:085cde657901 1764 }
mbed_official 87:085cde657901 1765
mbed_official 87:085cde657901 1766 /* Initialize MAC address in ethernet MAC */
mbed_official 87:085cde657901 1767 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 87:085cde657901 1768 }
mbed_official 87:085cde657901 1769
mbed_official 87:085cde657901 1770 /**
mbed_official 87:085cde657901 1771 * @brief Configures the selected MAC address.
mbed_official 226:b062af740e40 1772 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1773 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1774 * @param MacAddr: The MAC address to configure
mbed_official 87:085cde657901 1775 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1776 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 87:085cde657901 1777 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 87:085cde657901 1778 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 87:085cde657901 1779 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 87:085cde657901 1780 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 87:085cde657901 1781 * @retval HAL status
mbed_official 87:085cde657901 1782 */
mbed_official 87:085cde657901 1783 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 87:085cde657901 1784 {
mbed_official 87:085cde657901 1785 uint32_t tmpreg;
mbed_official 87:085cde657901 1786
mbed_official 87:085cde657901 1787 /* Check the parameters */
mbed_official 87:085cde657901 1788 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 87:085cde657901 1789
mbed_official 87:085cde657901 1790 /* Calculate the selected MAC address high register */
mbed_official 87:085cde657901 1791 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 87:085cde657901 1792 /* Load the selected MAC address high register */
mbed_official 87:085cde657901 1793 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1794 /* Calculate the selected MAC address low register */
mbed_official 87:085cde657901 1795 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 87:085cde657901 1796
mbed_official 87:085cde657901 1797 /* Load the selected MAC address low register */
mbed_official 87:085cde657901 1798 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1799 }
mbed_official 87:085cde657901 1800
mbed_official 87:085cde657901 1801 /**
mbed_official 87:085cde657901 1802 * @brief Enables the MAC transmission.
mbed_official 226:b062af740e40 1803 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1804 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1805 * @retval None
mbed_official 87:085cde657901 1806 */
mbed_official 87:085cde657901 1807 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1808 {
mbed_official 87:085cde657901 1809 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1810
mbed_official 87:085cde657901 1811 /* Enable the MAC transmission */
mbed_official 87:085cde657901 1812 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 87:085cde657901 1813
mbed_official 87:085cde657901 1814 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1815 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1816 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1817 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1818 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1819 }
mbed_official 87:085cde657901 1820
mbed_official 87:085cde657901 1821 /**
mbed_official 87:085cde657901 1822 * @brief Disables the MAC transmission.
mbed_official 226:b062af740e40 1823 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1824 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1825 * @retval None
mbed_official 87:085cde657901 1826 */
mbed_official 87:085cde657901 1827 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1828 {
mbed_official 87:085cde657901 1829 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1830
mbed_official 87:085cde657901 1831 /* Disable the MAC transmission */
mbed_official 87:085cde657901 1832 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 87:085cde657901 1833
mbed_official 87:085cde657901 1834 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1835 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1836 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1837 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1838 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1839 }
mbed_official 87:085cde657901 1840
mbed_official 87:085cde657901 1841 /**
mbed_official 87:085cde657901 1842 * @brief Enables the MAC reception.
mbed_official 226:b062af740e40 1843 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1844 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1845 * @retval None
mbed_official 87:085cde657901 1846 */
mbed_official 87:085cde657901 1847 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1848 {
mbed_official 87:085cde657901 1849 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1850
mbed_official 87:085cde657901 1851 /* Enable the MAC reception */
mbed_official 87:085cde657901 1852 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 87:085cde657901 1853
mbed_official 87:085cde657901 1854 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1855 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1856 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1857 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1858 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1859 }
mbed_official 87:085cde657901 1860
mbed_official 87:085cde657901 1861 /**
mbed_official 87:085cde657901 1862 * @brief Disables the MAC reception.
mbed_official 226:b062af740e40 1863 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1864 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1865 * @retval None
mbed_official 87:085cde657901 1866 */
mbed_official 87:085cde657901 1867 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1868 {
mbed_official 87:085cde657901 1869 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1870
mbed_official 87:085cde657901 1871 /* Disable the MAC reception */
mbed_official 87:085cde657901 1872 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 87:085cde657901 1873
mbed_official 87:085cde657901 1874 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1875 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1876 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1877 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1878 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1879 }
mbed_official 87:085cde657901 1880
mbed_official 87:085cde657901 1881 /**
mbed_official 87:085cde657901 1882 * @brief Enables the DMA transmission.
mbed_official 226:b062af740e40 1883 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1884 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1885 * @retval None
mbed_official 87:085cde657901 1886 */
mbed_official 87:085cde657901 1887 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1888 {
mbed_official 87:085cde657901 1889 /* Enable the DMA transmission */
mbed_official 87:085cde657901 1890 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1891 }
mbed_official 87:085cde657901 1892
mbed_official 87:085cde657901 1893 /**
mbed_official 87:085cde657901 1894 * @brief Disables the DMA transmission.
mbed_official 226:b062af740e40 1895 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1896 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1897 * @retval None
mbed_official 87:085cde657901 1898 */
mbed_official 87:085cde657901 1899 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1900 {
mbed_official 87:085cde657901 1901 /* Disable the DMA transmission */
mbed_official 87:085cde657901 1902 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1903 }
mbed_official 87:085cde657901 1904
mbed_official 87:085cde657901 1905 /**
mbed_official 87:085cde657901 1906 * @brief Enables the DMA reception.
mbed_official 226:b062af740e40 1907 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1908 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1909 * @retval None
mbed_official 87:085cde657901 1910 */
mbed_official 87:085cde657901 1911 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1912 {
mbed_official 87:085cde657901 1913 /* Enable the DMA reception */
mbed_official 87:085cde657901 1914 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1915 }
mbed_official 87:085cde657901 1916
mbed_official 87:085cde657901 1917 /**
mbed_official 87:085cde657901 1918 * @brief Disables the DMA reception.
mbed_official 226:b062af740e40 1919 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1920 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1921 * @retval None
mbed_official 87:085cde657901 1922 */
mbed_official 87:085cde657901 1923 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1924 {
mbed_official 87:085cde657901 1925 /* Disable the DMA reception */
mbed_official 87:085cde657901 1926 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1927 }
mbed_official 87:085cde657901 1928
mbed_official 87:085cde657901 1929 /**
mbed_official 87:085cde657901 1930 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 226:b062af740e40 1931 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1932 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1933 * @retval None
mbed_official 87:085cde657901 1934 */
mbed_official 87:085cde657901 1935 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1936 {
mbed_official 87:085cde657901 1937 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1938
mbed_official 87:085cde657901 1939 /* Set the Flush Transmit FIFO bit */
mbed_official 87:085cde657901 1940 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 87:085cde657901 1941
mbed_official 87:085cde657901 1942 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1943 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1944 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1945 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1946 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1947 }
mbed_official 87:085cde657901 1948
mbed_official 87:085cde657901 1949 /**
mbed_official 87:085cde657901 1950 * @}
mbed_official 87:085cde657901 1951 */
mbed_official 87:085cde657901 1952
mbed_official 87:085cde657901 1953 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1954 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 87:085cde657901 1955 /**
mbed_official 87:085cde657901 1956 * @}
mbed_official 87:085cde657901 1957 */
mbed_official 87:085cde657901 1958
mbed_official 87:085cde657901 1959 /**
mbed_official 87:085cde657901 1960 * @}
mbed_official 87:085cde657901 1961 */
mbed_official 87:085cde657901 1962
mbed_official 87:085cde657901 1963 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/