mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c@625:6502bcae5f2c, 2015-09-25 (annotated)

Committer:
mbed_official
Date:
Fri Sep 25 12:00:11 2015 +0100
Revision:
625:6502bcae5f2c
Synchronized with git revision 724c07935c2d3e3d8a1b3e7274b29ba5dcbed7ad



Full URL: https://github.com/mbedmicro/mbed/commit/724c07935c2d3e3d8a1b3e7274b29ba5dcbed7ad/



Changes contains only "Copyright year information" and "KR styling". Safe to merge.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 625:6502bcae5f2c 1 /**
mbed_official 625:6502bcae5f2c 2 ******************************************************************************
mbed_official 625:6502bcae5f2c 3 * @file system_stm32f4xx.c
mbed_official 625:6502bcae5f2c 4 * @author MCD Application Team
mbed_official 625:6502bcae5f2c 5 * @version V2.1.0
mbed_official 625:6502bcae5f2c 6 * @date 19-June-2014
mbed_official 625:6502bcae5f2c 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 625:6502bcae5f2c 8 *
mbed_official 625:6502bcae5f2c 9 * This file provides two functions and one global variable to be called from
mbed_official 625:6502bcae5f2c 10 * user application:
mbed_official 625:6502bcae5f2c 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 625:6502bcae5f2c 12 * before branch to main program. This call is made inside
mbed_official 625:6502bcae5f2c 13 * the "startup_stm32f4xx.s" file.
mbed_official 625:6502bcae5f2c 14 *
mbed_official 625:6502bcae5f2c 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 625:6502bcae5f2c 16 * by the user application to setup the SysTick
mbed_official 625:6502bcae5f2c 17 * timer or configure other parameters.
mbed_official 625:6502bcae5f2c 18 *
mbed_official 625:6502bcae5f2c 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 625:6502bcae5f2c 20 * be called whenever the core clock is changed
mbed_official 625:6502bcae5f2c 21 * during program execution.
mbed_official 625:6502bcae5f2c 22 *
mbed_official 625:6502bcae5f2c 23 * This file configures the system clock as follows:
mbed_official 625:6502bcae5f2c 24 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 625:6502bcae5f2c 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 625:6502bcae5f2c 27 * | 2- PLL_HSE_XTAL |
mbed_official 625:6502bcae5f2c 28 * | (external 8 MHz xtal) |
mbed_official 625:6502bcae5f2c 29 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 30 * SYSCLK(MHz) | 96 | 96
mbed_official 625:6502bcae5f2c 31 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 32 * AHBCLK (MHz) | 96 | 96
mbed_official 625:6502bcae5f2c 33 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 34 * APB1CLK (MHz) | 48 | 48
mbed_official 625:6502bcae5f2c 35 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 36 * APB2CLK (MHz) | 96 | 96
mbed_official 625:6502bcae5f2c 37 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 38 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 625:6502bcae5f2c 39 *-----------------------------------------------------------------------------
mbed_official 625:6502bcae5f2c 40 ******************************************************************************
mbed_official 625:6502bcae5f2c 41 * @attention
mbed_official 625:6502bcae5f2c 42 *
mbed_official 625:6502bcae5f2c 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 625:6502bcae5f2c 44 *
mbed_official 625:6502bcae5f2c 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 625:6502bcae5f2c 46 * are permitted provided that the following conditions are met:
mbed_official 625:6502bcae5f2c 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 625:6502bcae5f2c 48 * this list of conditions and the following disclaimer.
mbed_official 625:6502bcae5f2c 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 625:6502bcae5f2c 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 625:6502bcae5f2c 51 * and/or other materials provided with the distribution.
mbed_official 625:6502bcae5f2c 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 625:6502bcae5f2c 53 * may be used to endorse or promote products derived from this software
mbed_official 625:6502bcae5f2c 54 * without specific prior written permission.
mbed_official 625:6502bcae5f2c 55 *
mbed_official 625:6502bcae5f2c 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 625:6502bcae5f2c 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 625:6502bcae5f2c 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 625:6502bcae5f2c 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 625:6502bcae5f2c 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 625:6502bcae5f2c 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 625:6502bcae5f2c 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 625:6502bcae5f2c 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 625:6502bcae5f2c 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 625:6502bcae5f2c 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 625:6502bcae5f2c 66 *
mbed_official 625:6502bcae5f2c 67 ******************************************************************************
mbed_official 625:6502bcae5f2c 68 */
mbed_official 625:6502bcae5f2c 69
mbed_official 625:6502bcae5f2c 70 /** @addtogroup CMSIS
mbed_official 625:6502bcae5f2c 71 * @{
mbed_official 625:6502bcae5f2c 72 */
mbed_official 625:6502bcae5f2c 73
mbed_official 625:6502bcae5f2c 74 /** @addtogroup stm32f4xx_system
mbed_official 625:6502bcae5f2c 75 * @{
mbed_official 625:6502bcae5f2c 76 */
mbed_official 625:6502bcae5f2c 77
mbed_official 625:6502bcae5f2c 78 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 625:6502bcae5f2c 79 * @{
mbed_official 625:6502bcae5f2c 80 */
mbed_official 625:6502bcae5f2c 81
mbed_official 625:6502bcae5f2c 82
mbed_official 625:6502bcae5f2c 83 #include "stm32f4xx.h"
mbed_official 625:6502bcae5f2c 84 #include "hal_tick.h"
mbed_official 625:6502bcae5f2c 85
mbed_official 625:6502bcae5f2c 86 #if !defined (HSE_VALUE)
mbed_official 625:6502bcae5f2c 87 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
mbed_official 625:6502bcae5f2c 88 #endif /* HSE_VALUE */
mbed_official 625:6502bcae5f2c 89
mbed_official 625:6502bcae5f2c 90 #if !defined (HSI_VALUE)
mbed_official 625:6502bcae5f2c 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 625:6502bcae5f2c 92 #endif /* HSI_VALUE */
mbed_official 625:6502bcae5f2c 93
mbed_official 625:6502bcae5f2c 94 /**
mbed_official 625:6502bcae5f2c 95 * @}
mbed_official 625:6502bcae5f2c 96 */
mbed_official 625:6502bcae5f2c 97
mbed_official 625:6502bcae5f2c 98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 625:6502bcae5f2c 99 * @{
mbed_official 625:6502bcae5f2c 100 */
mbed_official 625:6502bcae5f2c 101
mbed_official 625:6502bcae5f2c 102 /**
mbed_official 625:6502bcae5f2c 103 * @}
mbed_official 625:6502bcae5f2c 104 */
mbed_official 625:6502bcae5f2c 105
mbed_official 625:6502bcae5f2c 106 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 625:6502bcae5f2c 107 * @{
mbed_official 625:6502bcae5f2c 108 */
mbed_official 625:6502bcae5f2c 109
mbed_official 625:6502bcae5f2c 110 /************************* Miscellaneous Configuration ************************/
mbed_official 625:6502bcae5f2c 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 625:6502bcae5f2c 112 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 625:6502bcae5f2c 113 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 625:6502bcae5f2c 114 /* #define DATA_IN_ExtSRAM */
mbed_official 625:6502bcae5f2c 115 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 625:6502bcae5f2c 116
mbed_official 625:6502bcae5f2c 117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 625:6502bcae5f2c 118 /* #define DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 119 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 625:6502bcae5f2c 120
mbed_official 625:6502bcae5f2c 121 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 625:6502bcae5f2c 122 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 625:6502bcae5f2c 123 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 124
mbed_official 625:6502bcae5f2c 125 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 625:6502bcae5f2c 126 Internal SRAM. */
mbed_official 625:6502bcae5f2c 127 /* #define VECT_TAB_SRAM */
mbed_official 625:6502bcae5f2c 128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 625:6502bcae5f2c 129 This value must be a multiple of 0x200. */
mbed_official 625:6502bcae5f2c 130 /******************************************************************************/
mbed_official 625:6502bcae5f2c 131
mbed_official 625:6502bcae5f2c 132 /**
mbed_official 625:6502bcae5f2c 133 * @}
mbed_official 625:6502bcae5f2c 134 */
mbed_official 625:6502bcae5f2c 135
mbed_official 625:6502bcae5f2c 136 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 625:6502bcae5f2c 137 * @{
mbed_official 625:6502bcae5f2c 138 */
mbed_official 625:6502bcae5f2c 139
mbed_official 625:6502bcae5f2c 140 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 625:6502bcae5f2c 141 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official 625:6502bcae5f2c 142 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 625:6502bcae5f2c 143
mbed_official 625:6502bcae5f2c 144 /**
mbed_official 625:6502bcae5f2c 145 * @}
mbed_official 625:6502bcae5f2c 146 */
mbed_official 625:6502bcae5f2c 147
mbed_official 625:6502bcae5f2c 148 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 625:6502bcae5f2c 149 * @{
mbed_official 625:6502bcae5f2c 150 */
mbed_official 625:6502bcae5f2c 151 /* This variable is updated in three ways:
mbed_official 625:6502bcae5f2c 152 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 625:6502bcae5f2c 153 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 625:6502bcae5f2c 154 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 625:6502bcae5f2c 155 Note: If you use this function to configure the system clock; then there
mbed_official 625:6502bcae5f2c 156 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 625:6502bcae5f2c 157 variable is updated automatically.
mbed_official 625:6502bcae5f2c 158 */
mbed_official 625:6502bcae5f2c 159 uint32_t SystemCoreClock = 16000000;
mbed_official 625:6502bcae5f2c 160 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 625:6502bcae5f2c 161
mbed_official 625:6502bcae5f2c 162 /**
mbed_official 625:6502bcae5f2c 163 * @}
mbed_official 625:6502bcae5f2c 164 */
mbed_official 625:6502bcae5f2c 165
mbed_official 625:6502bcae5f2c 166 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 625:6502bcae5f2c 167 * @{
mbed_official 625:6502bcae5f2c 168 */
mbed_official 625:6502bcae5f2c 169
mbed_official 625:6502bcae5f2c 170 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 625:6502bcae5f2c 171 static void SystemInit_ExtMemCtl(void);
mbed_official 625:6502bcae5f2c 172 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 173
mbed_official 625:6502bcae5f2c 174 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 625:6502bcae5f2c 175 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 625:6502bcae5f2c 176 #endif
mbed_official 625:6502bcae5f2c 177
mbed_official 625:6502bcae5f2c 178 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 625:6502bcae5f2c 179
mbed_official 625:6502bcae5f2c 180 /**
mbed_official 625:6502bcae5f2c 181 * @}
mbed_official 625:6502bcae5f2c 182 */
mbed_official 625:6502bcae5f2c 183
mbed_official 625:6502bcae5f2c 184 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 625:6502bcae5f2c 185 * @{
mbed_official 625:6502bcae5f2c 186 */
mbed_official 625:6502bcae5f2c 187
mbed_official 625:6502bcae5f2c 188 /**
mbed_official 625:6502bcae5f2c 189 * @brief Setup the microcontroller system
mbed_official 625:6502bcae5f2c 190 * Initialize the FPU setting, vector table location and External memory
mbed_official 625:6502bcae5f2c 191 * configuration.
mbed_official 625:6502bcae5f2c 192 * @param None
mbed_official 625:6502bcae5f2c 193 * @retval None
mbed_official 625:6502bcae5f2c 194 */
mbed_official 625:6502bcae5f2c 195 void SystemInit(void)
mbed_official 625:6502bcae5f2c 196 {
mbed_official 625:6502bcae5f2c 197 /* FPU settings ------------------------------------------------------------*/
mbed_official 625:6502bcae5f2c 198 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 625:6502bcae5f2c 199 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 625:6502bcae5f2c 200 #endif
mbed_official 625:6502bcae5f2c 201 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 625:6502bcae5f2c 202 /* Set HSION bit */
mbed_official 625:6502bcae5f2c 203 RCC->CR |= (uint32_t)0x00000001;
mbed_official 625:6502bcae5f2c 204
mbed_official 625:6502bcae5f2c 205 /* Reset CFGR register */
mbed_official 625:6502bcae5f2c 206 RCC->CFGR = 0x00000000;
mbed_official 625:6502bcae5f2c 207
mbed_official 625:6502bcae5f2c 208 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 625:6502bcae5f2c 209 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 625:6502bcae5f2c 210
mbed_official 625:6502bcae5f2c 211 /* Reset PLLCFGR register */
mbed_official 625:6502bcae5f2c 212 RCC->PLLCFGR = 0x24003010;
mbed_official 625:6502bcae5f2c 213
mbed_official 625:6502bcae5f2c 214 /* Reset HSEBYP bit */
mbed_official 625:6502bcae5f2c 215 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 625:6502bcae5f2c 216
mbed_official 625:6502bcae5f2c 217 /* Disable all interrupts */
mbed_official 625:6502bcae5f2c 218 RCC->CIR = 0x00000000;
mbed_official 625:6502bcae5f2c 219
mbed_official 625:6502bcae5f2c 220 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 625:6502bcae5f2c 221 SystemInit_ExtMemCtl();
mbed_official 625:6502bcae5f2c 222 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 223
mbed_official 625:6502bcae5f2c 224 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 625:6502bcae5f2c 225 #ifdef VECT_TAB_SRAM
mbed_official 625:6502bcae5f2c 226 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 625:6502bcae5f2c 227 #else
mbed_official 625:6502bcae5f2c 228 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 625:6502bcae5f2c 229 #endif
mbed_official 625:6502bcae5f2c 230
mbed_official 625:6502bcae5f2c 231 /* Configure the Cube driver */
mbed_official 625:6502bcae5f2c 232 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official 625:6502bcae5f2c 233 HAL_Init();
mbed_official 625:6502bcae5f2c 234
mbed_official 625:6502bcae5f2c 235 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 625:6502bcae5f2c 236 AHB/APBx prescalers and Flash settings */
mbed_official 625:6502bcae5f2c 237 SetSysClock();
mbed_official 625:6502bcae5f2c 238
mbed_official 625:6502bcae5f2c 239 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 625:6502bcae5f2c 240 TIM_MST_RESET_ON;
mbed_official 625:6502bcae5f2c 241 TIM_MST_RESET_OFF;
mbed_official 625:6502bcae5f2c 242 }
mbed_official 625:6502bcae5f2c 243
mbed_official 625:6502bcae5f2c 244 /**
mbed_official 625:6502bcae5f2c 245 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 625:6502bcae5f2c 246 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 625:6502bcae5f2c 247 * be used by the user application to setup the SysTick timer or configure
mbed_official 625:6502bcae5f2c 248 * other parameters.
mbed_official 625:6502bcae5f2c 249 *
mbed_official 625:6502bcae5f2c 250 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 625:6502bcae5f2c 251 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 625:6502bcae5f2c 252 * based on this variable will be incorrect.
mbed_official 625:6502bcae5f2c 253 *
mbed_official 625:6502bcae5f2c 254 * @note - The system frequency computed by this function is not the real
mbed_official 625:6502bcae5f2c 255 * frequency in the chip. It is calculated based on the predefined
mbed_official 625:6502bcae5f2c 256 * constant and the selected clock source:
mbed_official 625:6502bcae5f2c 257 *
mbed_official 625:6502bcae5f2c 258 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 625:6502bcae5f2c 259 *
mbed_official 625:6502bcae5f2c 260 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 625:6502bcae5f2c 261 *
mbed_official 625:6502bcae5f2c 262 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 625:6502bcae5f2c 263 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 625:6502bcae5f2c 264 *
mbed_official 625:6502bcae5f2c 265 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 625:6502bcae5f2c 266 * 16 MHz) but the real value may vary depending on the variations
mbed_official 625:6502bcae5f2c 267 * in voltage and temperature.
mbed_official 625:6502bcae5f2c 268 *
mbed_official 625:6502bcae5f2c 269 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 625:6502bcae5f2c 270 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 625:6502bcae5f2c 271 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 625:6502bcae5f2c 272 * may have wrong result.
mbed_official 625:6502bcae5f2c 273 *
mbed_official 625:6502bcae5f2c 274 * - The result of this function could be not correct when using fractional
mbed_official 625:6502bcae5f2c 275 * value for HSE crystal.
mbed_official 625:6502bcae5f2c 276 *
mbed_official 625:6502bcae5f2c 277 * @param None
mbed_official 625:6502bcae5f2c 278 * @retval None
mbed_official 625:6502bcae5f2c 279 */
mbed_official 625:6502bcae5f2c 280 void SystemCoreClockUpdate(void)
mbed_official 625:6502bcae5f2c 281 {
mbed_official 625:6502bcae5f2c 282 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 625:6502bcae5f2c 283
mbed_official 625:6502bcae5f2c 284 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 625:6502bcae5f2c 285 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 625:6502bcae5f2c 286
mbed_official 625:6502bcae5f2c 287 switch (tmp)
mbed_official 625:6502bcae5f2c 288 {
mbed_official 625:6502bcae5f2c 289 case 0x00: /* HSI used as system clock source */
mbed_official 625:6502bcae5f2c 290 SystemCoreClock = HSI_VALUE;
mbed_official 625:6502bcae5f2c 291 break;
mbed_official 625:6502bcae5f2c 292 case 0x04: /* HSE used as system clock source */
mbed_official 625:6502bcae5f2c 293 SystemCoreClock = HSE_VALUE;
mbed_official 625:6502bcae5f2c 294 break;
mbed_official 625:6502bcae5f2c 295 case 0x08: /* PLL used as system clock source */
mbed_official 625:6502bcae5f2c 296
mbed_official 625:6502bcae5f2c 297 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 625:6502bcae5f2c 298 SYSCLK = PLL_VCO / PLL_P
mbed_official 625:6502bcae5f2c 299 */
mbed_official 625:6502bcae5f2c 300 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 625:6502bcae5f2c 301 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 625:6502bcae5f2c 302
mbed_official 625:6502bcae5f2c 303 if (pllsource != 0)
mbed_official 625:6502bcae5f2c 304 {
mbed_official 625:6502bcae5f2c 305 /* HSE used as PLL clock source */
mbed_official 625:6502bcae5f2c 306 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 625:6502bcae5f2c 307 }
mbed_official 625:6502bcae5f2c 308 else
mbed_official 625:6502bcae5f2c 309 {
mbed_official 625:6502bcae5f2c 310 /* HSI used as PLL clock source */
mbed_official 625:6502bcae5f2c 311 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 625:6502bcae5f2c 312 }
mbed_official 625:6502bcae5f2c 313
mbed_official 625:6502bcae5f2c 314 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 625:6502bcae5f2c 315 SystemCoreClock = pllvco/pllp;
mbed_official 625:6502bcae5f2c 316 break;
mbed_official 625:6502bcae5f2c 317 default:
mbed_official 625:6502bcae5f2c 318 SystemCoreClock = HSI_VALUE;
mbed_official 625:6502bcae5f2c 319 break;
mbed_official 625:6502bcae5f2c 320 }
mbed_official 625:6502bcae5f2c 321 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 625:6502bcae5f2c 322 /* Get HCLK prescaler */
mbed_official 625:6502bcae5f2c 323 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 625:6502bcae5f2c 324 /* HCLK frequency */
mbed_official 625:6502bcae5f2c 325 SystemCoreClock >>= tmp;
mbed_official 625:6502bcae5f2c 326 }
mbed_official 625:6502bcae5f2c 327
mbed_official 625:6502bcae5f2c 328 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 625:6502bcae5f2c 329 /**
mbed_official 625:6502bcae5f2c 330 * @brief Setup the external memory controller.
mbed_official 625:6502bcae5f2c 331 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 625:6502bcae5f2c 332 * This function configures the external memories (SRAM/SDRAM)
mbed_official 625:6502bcae5f2c 333 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 625:6502bcae5f2c 334 * @param None
mbed_official 625:6502bcae5f2c 335 * @retval None
mbed_official 625:6502bcae5f2c 336 */
mbed_official 625:6502bcae5f2c 337 void SystemInit_ExtMemCtl(void)
mbed_official 625:6502bcae5f2c 338 {
mbed_official 625:6502bcae5f2c 339 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 625:6502bcae5f2c 340 #if defined (DATA_IN_ExtSDRAM)
mbed_official 625:6502bcae5f2c 341 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 625:6502bcae5f2c 342 register uint32_t index;
mbed_official 625:6502bcae5f2c 343
mbed_official 625:6502bcae5f2c 344 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 625:6502bcae5f2c 345 clock */
mbed_official 625:6502bcae5f2c 346 RCC->AHB1ENR |= 0x000001F8;
mbed_official 625:6502bcae5f2c 347
mbed_official 625:6502bcae5f2c 348 /* Connect PDx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 349 GPIOD->AFR[0] = 0x000000CC;
mbed_official 625:6502bcae5f2c 350 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 625:6502bcae5f2c 351 /* Configure PDx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 352 GPIOD->MODER = 0xA02A000A;
mbed_official 625:6502bcae5f2c 353 /* Configure PDx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 354 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 625:6502bcae5f2c 355 /* Configure PDx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 356 GPIOD->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 357 /* No pull-up, pull-down for PDx pins */
mbed_official 625:6502bcae5f2c 358 GPIOD->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 359
mbed_official 625:6502bcae5f2c 360 /* Connect PEx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 361 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 625:6502bcae5f2c 362 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 363 /* Configure PEx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 364 GPIOE->MODER = 0xAAAA800A;
mbed_official 625:6502bcae5f2c 365 /* Configure PEx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 366 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 625:6502bcae5f2c 367 /* Configure PEx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 368 GPIOE->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 369 /* No pull-up, pull-down for PEx pins */
mbed_official 625:6502bcae5f2c 370 GPIOE->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 371
mbed_official 625:6502bcae5f2c 372 /* Connect PFx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 373 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 374 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 375 /* Configure PFx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 376 GPIOF->MODER = 0xAA800AAA;
mbed_official 625:6502bcae5f2c 377 /* Configure PFx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 378 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 625:6502bcae5f2c 379 /* Configure PFx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 380 GPIOF->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 381 /* No pull-up, pull-down for PFx pins */
mbed_official 625:6502bcae5f2c 382 GPIOF->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 383
mbed_official 625:6502bcae5f2c 384 /* Connect PGx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 385 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 386 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 387 /* Configure PGx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 388 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 625:6502bcae5f2c 389 /* Configure PGx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 390 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 625:6502bcae5f2c 391 /* Configure PGx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 392 GPIOG->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 393 /* No pull-up, pull-down for PGx pins */
mbed_official 625:6502bcae5f2c 394 GPIOG->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 395
mbed_official 625:6502bcae5f2c 396 /* Connect PHx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 397 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 625:6502bcae5f2c 398 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 399 /* Configure PHx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 400 GPIOH->MODER = 0xAAAA08A0;
mbed_official 625:6502bcae5f2c 401 /* Configure PHx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 402 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 625:6502bcae5f2c 403 /* Configure PHx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 404 GPIOH->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 405 /* No pull-up, pull-down for PHx pins */
mbed_official 625:6502bcae5f2c 406 GPIOH->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 407
mbed_official 625:6502bcae5f2c 408 /* Connect PIx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 409 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 410 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 625:6502bcae5f2c 411 /* Configure PIx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 412 GPIOI->MODER = 0x0028AAAA;
mbed_official 625:6502bcae5f2c 413 /* Configure PIx pins speed to 50 MHz */
mbed_official 625:6502bcae5f2c 414 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 625:6502bcae5f2c 415 /* Configure PIx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 416 GPIOI->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 417 /* No pull-up, pull-down for PIx pins */
mbed_official 625:6502bcae5f2c 418 GPIOI->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 419
mbed_official 625:6502bcae5f2c 420 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 625:6502bcae5f2c 421 /* Enable the FMC interface clock */
mbed_official 625:6502bcae5f2c 422 RCC->AHB3ENR |= 0x00000001;
mbed_official 625:6502bcae5f2c 423
mbed_official 625:6502bcae5f2c 424 /* Configure and enable SDRAM bank1 */
mbed_official 625:6502bcae5f2c 425 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 625:6502bcae5f2c 426 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 625:6502bcae5f2c 427
mbed_official 625:6502bcae5f2c 428 /* SDRAM initialization sequence */
mbed_official 625:6502bcae5f2c 429 /* Clock enable command */
mbed_official 625:6502bcae5f2c 430 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 625:6502bcae5f2c 431 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 625:6502bcae5f2c 432 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 625:6502bcae5f2c 433 {
mbed_official 625:6502bcae5f2c 434 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 625:6502bcae5f2c 435 }
mbed_official 625:6502bcae5f2c 436
mbed_official 625:6502bcae5f2c 437 /* Delay */
mbed_official 625:6502bcae5f2c 438 for (index = 0; index<1000; index++);
mbed_official 625:6502bcae5f2c 439
mbed_official 625:6502bcae5f2c 440 /* PALL command */
mbed_official 625:6502bcae5f2c 441 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 625:6502bcae5f2c 442 timeout = 0xFFFF;
mbed_official 625:6502bcae5f2c 443 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 625:6502bcae5f2c 444 {
mbed_official 625:6502bcae5f2c 445 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 625:6502bcae5f2c 446 }
mbed_official 625:6502bcae5f2c 447
mbed_official 625:6502bcae5f2c 448 /* Auto refresh command */
mbed_official 625:6502bcae5f2c 449 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 625:6502bcae5f2c 450 timeout = 0xFFFF;
mbed_official 625:6502bcae5f2c 451 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 625:6502bcae5f2c 452 {
mbed_official 625:6502bcae5f2c 453 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 625:6502bcae5f2c 454 }
mbed_official 625:6502bcae5f2c 455
mbed_official 625:6502bcae5f2c 456 /* MRD register program */
mbed_official 625:6502bcae5f2c 457 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 625:6502bcae5f2c 458 timeout = 0xFFFF;
mbed_official 625:6502bcae5f2c 459 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 625:6502bcae5f2c 460 {
mbed_official 625:6502bcae5f2c 461 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 625:6502bcae5f2c 462 }
mbed_official 625:6502bcae5f2c 463
mbed_official 625:6502bcae5f2c 464 /* Set refresh count */
mbed_official 625:6502bcae5f2c 465 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 625:6502bcae5f2c 466 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 625:6502bcae5f2c 467
mbed_official 625:6502bcae5f2c 468 /* Disable write protection */
mbed_official 625:6502bcae5f2c 469 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 625:6502bcae5f2c 470 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 625:6502bcae5f2c 471 #endif /* DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 472 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 625:6502bcae5f2c 473
mbed_official 625:6502bcae5f2c 474 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 625:6502bcae5f2c 475 #if defined(DATA_IN_ExtSRAM)
mbed_official 625:6502bcae5f2c 476 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 625:6502bcae5f2c 477 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 625:6502bcae5f2c 478 RCC->AHB1ENR |= 0x00000078;
mbed_official 625:6502bcae5f2c 479
mbed_official 625:6502bcae5f2c 480 /* Connect PDx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 481 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 625:6502bcae5f2c 482 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 483 /* Configure PDx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 484 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 625:6502bcae5f2c 485 /* Configure PDx pins speed to 100 MHz */
mbed_official 625:6502bcae5f2c 486 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 625:6502bcae5f2c 487 /* Configure PDx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 488 GPIOD->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 489 /* No pull-up, pull-down for PDx pins */
mbed_official 625:6502bcae5f2c 490 GPIOD->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 491
mbed_official 625:6502bcae5f2c 492 /* Connect PEx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 493 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 625:6502bcae5f2c 494 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 625:6502bcae5f2c 495 /* Configure PEx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 496 GPIOE->MODER = 0xAAAA828A;
mbed_official 625:6502bcae5f2c 497 /* Configure PEx pins speed to 100 MHz */
mbed_official 625:6502bcae5f2c 498 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 625:6502bcae5f2c 499 /* Configure PEx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 500 GPIOE->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 501 /* No pull-up, pull-down for PEx pins */
mbed_official 625:6502bcae5f2c 502 GPIOE->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 503
mbed_official 625:6502bcae5f2c 504 /* Connect PFx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 505 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 625:6502bcae5f2c 506 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 625:6502bcae5f2c 507 /* Configure PFx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 508 GPIOF->MODER = 0xAA000AAA;
mbed_official 625:6502bcae5f2c 509 /* Configure PFx pins speed to 100 MHz */
mbed_official 625:6502bcae5f2c 510 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 625:6502bcae5f2c 511 /* Configure PFx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 512 GPIOF->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 513 /* No pull-up, pull-down for PFx pins */
mbed_official 625:6502bcae5f2c 514 GPIOF->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 515
mbed_official 625:6502bcae5f2c 516 /* Connect PGx pins to FMC Alternate function */
mbed_official 625:6502bcae5f2c 517 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 625:6502bcae5f2c 518 GPIOG->AFR[1] = 0x000000C0;
mbed_official 625:6502bcae5f2c 519 /* Configure PGx pins in Alternate function mode */
mbed_official 625:6502bcae5f2c 520 GPIOG->MODER = 0x00085AAA;
mbed_official 625:6502bcae5f2c 521 /* Configure PGx pins speed to 100 MHz */
mbed_official 625:6502bcae5f2c 522 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 625:6502bcae5f2c 523 /* Configure PGx pins Output type to push-pull */
mbed_official 625:6502bcae5f2c 524 GPIOG->OTYPER = 0x00000000;
mbed_official 625:6502bcae5f2c 525 /* No pull-up, pull-down for PGx pins */
mbed_official 625:6502bcae5f2c 526 GPIOG->PUPDR = 0x00000000;
mbed_official 625:6502bcae5f2c 527
mbed_official 625:6502bcae5f2c 528 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 625:6502bcae5f2c 529 /* Enable the FMC/FSMC interface clock */
mbed_official 625:6502bcae5f2c 530 RCC->AHB3ENR |= 0x00000001;
mbed_official 625:6502bcae5f2c 531
mbed_official 625:6502bcae5f2c 532 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 625:6502bcae5f2c 533 /* Configure and enable Bank1_SRAM2 */
mbed_official 625:6502bcae5f2c 534 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 625:6502bcae5f2c 535 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 625:6502bcae5f2c 536 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 625:6502bcae5f2c 537 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 625:6502bcae5f2c 538
mbed_official 625:6502bcae5f2c 539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 625:6502bcae5f2c 540 /* Configure and enable Bank1_SRAM2 */
mbed_official 625:6502bcae5f2c 541 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 625:6502bcae5f2c 542 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 625:6502bcae5f2c 543 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 625:6502bcae5f2c 544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 625:6502bcae5f2c 545
mbed_official 625:6502bcae5f2c 546 #endif /* DATA_IN_ExtSRAM */
mbed_official 625:6502bcae5f2c 547 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 625:6502bcae5f2c 548 }
mbed_official 625:6502bcae5f2c 549 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 625:6502bcae5f2c 550
mbed_official 625:6502bcae5f2c 551 /**
mbed_official 625:6502bcae5f2c 552 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 625:6502bcae5f2c 553 * AHB/APBx prescalers and Flash settings
mbed_official 625:6502bcae5f2c 554 * @note This function should be called only once the RCC clock configuration
mbed_official 625:6502bcae5f2c 555 * is reset to the default reset state (done in SystemInit() function).
mbed_official 625:6502bcae5f2c 556 * @param None
mbed_official 625:6502bcae5f2c 557 * @retval None
mbed_official 625:6502bcae5f2c 558 */
mbed_official 625:6502bcae5f2c 559 void SetSysClock(void)
mbed_official 625:6502bcae5f2c 560 {
mbed_official 625:6502bcae5f2c 561 /* 1- Try to start with HSE and external clock */
mbed_official 625:6502bcae5f2c 562 #if USE_PLL_HSE_EXTC != 0
mbed_official 625:6502bcae5f2c 563 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 625:6502bcae5f2c 564 #endif
mbed_official 625:6502bcae5f2c 565 {
mbed_official 625:6502bcae5f2c 566 /* 2- If fail try to start with HSE and external xtal */
mbed_official 625:6502bcae5f2c 567 #if USE_PLL_HSE_XTAL != 0
mbed_official 625:6502bcae5f2c 568 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 625:6502bcae5f2c 569 #endif
mbed_official 625:6502bcae5f2c 570 {
mbed_official 625:6502bcae5f2c 571 /* 3- If fail start with HSI clock */
mbed_official 625:6502bcae5f2c 572 if (SetSysClock_PLL_HSI() == 0)
mbed_official 625:6502bcae5f2c 573 {
mbed_official 625:6502bcae5f2c 574 while(1)
mbed_official 625:6502bcae5f2c 575 {
mbed_official 625:6502bcae5f2c 576 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 625:6502bcae5f2c 577 }
mbed_official 625:6502bcae5f2c 578 }
mbed_official 625:6502bcae5f2c 579 }
mbed_official 625:6502bcae5f2c 580 }
mbed_official 625:6502bcae5f2c 581
mbed_official 625:6502bcae5f2c 582 /* Output clock on MCO2 pin(PC9) for debugging purpose */
mbed_official 625:6502bcae5f2c 583 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
mbed_official 625:6502bcae5f2c 584 }
mbed_official 625:6502bcae5f2c 585
mbed_official 625:6502bcae5f2c 586 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 625:6502bcae5f2c 587 /******************************************************************************/
mbed_official 625:6502bcae5f2c 588 /* PLL (clocked by HSE) used as System clock source */
mbed_official 625:6502bcae5f2c 589 /******************************************************************************/
mbed_official 625:6502bcae5f2c 590 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 625:6502bcae5f2c 591 {
mbed_official 625:6502bcae5f2c 592 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 625:6502bcae5f2c 593 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 625:6502bcae5f2c 594
mbed_official 625:6502bcae5f2c 595 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 625:6502bcae5f2c 596 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 625:6502bcae5f2c 597 regarding system frequency refer to product datasheet. */
mbed_official 625:6502bcae5f2c 598 __PWR_CLK_ENABLE();
mbed_official 625:6502bcae5f2c 599 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 625:6502bcae5f2c 600
mbed_official 625:6502bcae5f2c 601 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 625:6502bcae5f2c 602 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 625:6502bcae5f2c 603 if (bypass == 0)
mbed_official 625:6502bcae5f2c 604 {
mbed_official 625:6502bcae5f2c 605 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 625:6502bcae5f2c 606 }
mbed_official 625:6502bcae5f2c 607 else
mbed_official 625:6502bcae5f2c 608 {
mbed_official 625:6502bcae5f2c 609 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 625:6502bcae5f2c 610 }
mbed_official 625:6502bcae5f2c 611 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 625:6502bcae5f2c 612 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 625:6502bcae5f2c 613 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 625:6502bcae5f2c 614 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
mbed_official 625:6502bcae5f2c 615 //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
mbed_official 625:6502bcae5f2c 616 //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
mbed_official 625:6502bcae5f2c 617
mbed_official 625:6502bcae5f2c 618 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4)
mbed_official 625:6502bcae5f2c 619 RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192)
mbed_official 625:6502bcae5f2c 620
mbed_official 625:6502bcae5f2c 621
mbed_official 625:6502bcae5f2c 622 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
mbed_official 625:6502bcae5f2c 623 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
mbed_official 625:6502bcae5f2c 624 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 625:6502bcae5f2c 625 {
mbed_official 625:6502bcae5f2c 626 return 0; // FAIL
mbed_official 625:6502bcae5f2c 627 }
mbed_official 625:6502bcae5f2c 628
mbed_official 625:6502bcae5f2c 629 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 625:6502bcae5f2c 630 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 625:6502bcae5f2c 631 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
mbed_official 625:6502bcae5f2c 632 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
mbed_official 625:6502bcae5f2c 633 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
mbed_official 625:6502bcae5f2c 634 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
mbed_official 625:6502bcae5f2c 635 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 625:6502bcae5f2c 636 {
mbed_official 625:6502bcae5f2c 637 return 0; // FAIL
mbed_official 625:6502bcae5f2c 638 }
mbed_official 625:6502bcae5f2c 639
mbed_official 625:6502bcae5f2c 640 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 625:6502bcae5f2c 641
mbed_official 625:6502bcae5f2c 642 //if (bypass == 0)
mbed_official 625:6502bcae5f2c 643 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
mbed_official 625:6502bcae5f2c 644 //else
mbed_official 625:6502bcae5f2c 645 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
mbed_official 625:6502bcae5f2c 646
mbed_official 625:6502bcae5f2c 647 return 1; // OK
mbed_official 625:6502bcae5f2c 648 }
mbed_official 625:6502bcae5f2c 649 #endif
mbed_official 625:6502bcae5f2c 650
mbed_official 625:6502bcae5f2c 651 /******************************************************************************/
mbed_official 625:6502bcae5f2c 652 /* PLL (clocked by HSI) used as System clock source */
mbed_official 625:6502bcae5f2c 653 /******************************************************************************/
mbed_official 625:6502bcae5f2c 654 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 625:6502bcae5f2c 655 {
mbed_official 625:6502bcae5f2c 656 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 625:6502bcae5f2c 657 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 625:6502bcae5f2c 658
mbed_official 625:6502bcae5f2c 659 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 625:6502bcae5f2c 660 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 625:6502bcae5f2c 661 regarding system frequency refer to product datasheet. */
mbed_official 625:6502bcae5f2c 662 __PWR_CLK_ENABLE();
mbed_official 625:6502bcae5f2c 663 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 625:6502bcae5f2c 664
mbed_official 625:6502bcae5f2c 665 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 625:6502bcae5f2c 666 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 625:6502bcae5f2c 667 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 625:6502bcae5f2c 668 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 625:6502bcae5f2c 669 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 625:6502bcae5f2c 670 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 625:6502bcae5f2c 671 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 625:6502bcae5f2c 672 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 625:6502bcae5f2c 673 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
mbed_official 625:6502bcae5f2c 674 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
mbed_official 625:6502bcae5f2c 675 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
mbed_official 625:6502bcae5f2c 676 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
mbed_official 625:6502bcae5f2c 677 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
mbed_official 625:6502bcae5f2c 678 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 625:6502bcae5f2c 679 {
mbed_official 625:6502bcae5f2c 680 return 0; // FAIL
mbed_official 625:6502bcae5f2c 681 }
mbed_official 625:6502bcae5f2c 682
mbed_official 625:6502bcae5f2c 683 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 625:6502bcae5f2c 684 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 625:6502bcae5f2c 685 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
mbed_official 625:6502bcae5f2c 686 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
mbed_official 625:6502bcae5f2c 687 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
mbed_official 625:6502bcae5f2c 688 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
mbed_official 625:6502bcae5f2c 689 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 625:6502bcae5f2c 690 {
mbed_official 625:6502bcae5f2c 691 return 0; // FAIL
mbed_official 625:6502bcae5f2c 692 }
mbed_official 625:6502bcae5f2c 693
mbed_official 625:6502bcae5f2c 694 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 625:6502bcae5f2c 695 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 625:6502bcae5f2c 696
mbed_official 625:6502bcae5f2c 697 return 1; // OK
mbed_official 625:6502bcae5f2c 698 }
mbed_official 625:6502bcae5f2c 699
mbed_official 625:6502bcae5f2c 700 /**
mbed_official 625:6502bcae5f2c 701 * @}
mbed_official 625:6502bcae5f2c 702 */
mbed_official 625:6502bcae5f2c 703
mbed_official 625:6502bcae5f2c 704 /**
mbed_official 625:6502bcae5f2c 705 * @}
mbed_official 625:6502bcae5f2c 706 */
mbed_official 625:6502bcae5f2c 707
mbed_official 625:6502bcae5f2c 708 /**
mbed_official 625:6502bcae5f2c 709 * @}
mbed_official 625:6502bcae5f2c 710 */
mbed_official 625:6502bcae5f2c 711 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/