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Committer:
bogdanm
Date:
Wed Aug 07 16:43:59 2013 +0300
Revision:
15:4892fe388435
Child:
66:64ad953ee6c3
Added LPC4088 target and interrupt chaining code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 15:4892fe388435 1 /* KL25Z startup ARM GCC
bogdanm 15:4892fe388435 2 * Purpose: startup file for Cortex-M0 devices. Should use with
bogdanm 15:4892fe388435 3 * GCC for ARM Embedded Processors
bogdanm 15:4892fe388435 4 * Version: V1.2
bogdanm 15:4892fe388435 5 * Date: 15 Nov 2011
bogdanm 15:4892fe388435 6 *
bogdanm 15:4892fe388435 7 * Copyright (c) 2011, ARM Limited
bogdanm 15:4892fe388435 8 * All rights reserved.
bogdanm 15:4892fe388435 9 *
bogdanm 15:4892fe388435 10 * Redistribution and use in source and binary forms, with or without
bogdanm 15:4892fe388435 11 * modification, are permitted provided that the following conditions are met:
bogdanm 15:4892fe388435 12 * Redistributions of source code must retain the above copyright
bogdanm 15:4892fe388435 13 notice, this list of conditions and the following disclaimer.
bogdanm 15:4892fe388435 14 * Redistributions in binary form must reproduce the above copyright
bogdanm 15:4892fe388435 15 notice, this list of conditions and the following disclaimer in the
bogdanm 15:4892fe388435 16 documentation and/or other materials provided with the distribution.
bogdanm 15:4892fe388435 17 * Neither the name of the ARM Limited nor the
bogdanm 15:4892fe388435 18 names of its contributors may be used to endorse or promote products
bogdanm 15:4892fe388435 19 derived from this software without specific prior written permission.
bogdanm 15:4892fe388435 20 *
bogdanm 15:4892fe388435 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 15:4892fe388435 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 15:4892fe388435 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 15:4892fe388435 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
bogdanm 15:4892fe388435 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 15:4892fe388435 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 15:4892fe388435 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
bogdanm 15:4892fe388435 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 15:4892fe388435 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 15:4892fe388435 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 15:4892fe388435 31 */
bogdanm 15:4892fe388435 32 .syntax unified
bogdanm 15:4892fe388435 33 .arch armv6-m
bogdanm 15:4892fe388435 34
bogdanm 15:4892fe388435 35 /* Memory Model
bogdanm 15:4892fe388435 36 The HEAP starts at the end of the DATA section and grows upward.
bogdanm 15:4892fe388435 37
bogdanm 15:4892fe388435 38 The STACK starts at the end of the RAM and grows downward.
bogdanm 15:4892fe388435 39
bogdanm 15:4892fe388435 40 The HEAP and stack STACK are only checked at compile time:
bogdanm 15:4892fe388435 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
bogdanm 15:4892fe388435 42
bogdanm 15:4892fe388435 43 This is just a check for the bare minimum for the Heap+Stack area before
bogdanm 15:4892fe388435 44 aborting compilation, it is not the run time limit:
bogdanm 15:4892fe388435 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
bogdanm 15:4892fe388435 46 */
bogdanm 15:4892fe388435 47 .section .stack
bogdanm 15:4892fe388435 48 .align 3
bogdanm 15:4892fe388435 49 #ifdef __STACK_SIZE
bogdanm 15:4892fe388435 50 .equ Stack_Size, __STACK_SIZE
bogdanm 15:4892fe388435 51 #else
bogdanm 15:4892fe388435 52 .equ Stack_Size, 0x80
bogdanm 15:4892fe388435 53 #endif
bogdanm 15:4892fe388435 54 .globl __StackTop
bogdanm 15:4892fe388435 55 .globl __StackLimit
bogdanm 15:4892fe388435 56 __StackLimit:
bogdanm 15:4892fe388435 57 .space Stack_Size
bogdanm 15:4892fe388435 58 .size __StackLimit, . - __StackLimit
bogdanm 15:4892fe388435 59 __StackTop:
bogdanm 15:4892fe388435 60 .size __StackTop, . - __StackTop
bogdanm 15:4892fe388435 61
bogdanm 15:4892fe388435 62 .section .heap
bogdanm 15:4892fe388435 63 .align 3
bogdanm 15:4892fe388435 64 #ifdef __HEAP_SIZE
bogdanm 15:4892fe388435 65 .equ Heap_Size, __HEAP_SIZE
bogdanm 15:4892fe388435 66 #else
bogdanm 15:4892fe388435 67 .equ Heap_Size, 0x80
bogdanm 15:4892fe388435 68 #endif
bogdanm 15:4892fe388435 69 .globl __HeapBase
bogdanm 15:4892fe388435 70 .globl __HeapLimit
bogdanm 15:4892fe388435 71 __HeapBase:
bogdanm 15:4892fe388435 72 .space Heap_Size
bogdanm 15:4892fe388435 73 .size __HeapBase, . - __HeapBase
bogdanm 15:4892fe388435 74 __HeapLimit:
bogdanm 15:4892fe388435 75 .size __HeapLimit, . - __HeapLimit
bogdanm 15:4892fe388435 76
bogdanm 15:4892fe388435 77 .section .vector_table,"a",%progbits
bogdanm 15:4892fe388435 78 .align 2
bogdanm 15:4892fe388435 79 .globl __isr_vector
bogdanm 15:4892fe388435 80 __isr_vector:
bogdanm 15:4892fe388435 81 .long __StackTop /* Top of Stack */
bogdanm 15:4892fe388435 82 .long Reset_Handler /* Reset Handler */
bogdanm 15:4892fe388435 83 .long NMI_Handler /* NMI Handler */
bogdanm 15:4892fe388435 84 .long HardFault_Handler /* Hard Fault Handler */
bogdanm 15:4892fe388435 85 .long 0 /* Reserved */
bogdanm 15:4892fe388435 86 .long 0 /* Reserved */
bogdanm 15:4892fe388435 87 .long 0 /* Reserved */
bogdanm 15:4892fe388435 88 .long 0 /* Reserved */
bogdanm 15:4892fe388435 89 .long 0 /* Reserved */
bogdanm 15:4892fe388435 90 .long 0 /* Reserved */
bogdanm 15:4892fe388435 91 .long 0 /* Reserved */
bogdanm 15:4892fe388435 92 .long SVC_Handler /* SVCall Handler */
bogdanm 15:4892fe388435 93 .long 0 /* Reserved */
bogdanm 15:4892fe388435 94 .long 0 /* Reserved */
bogdanm 15:4892fe388435 95 .long PendSV_Handler /* PendSV Handler */
bogdanm 15:4892fe388435 96 .long SysTick_Handler /* SysTick Handler */
bogdanm 15:4892fe388435 97
bogdanm 15:4892fe388435 98 /* External interrupts */
bogdanm 15:4892fe388435 99 .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
bogdanm 15:4892fe388435 100 .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
bogdanm 15:4892fe388435 101 .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
bogdanm 15:4892fe388435 102 .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
bogdanm 15:4892fe388435 103 .long Default_Handler /* Reserved interrupt 20 */
bogdanm 15:4892fe388435 104 .long FTFA_IRQHandler /* FTFA interrupt */
bogdanm 15:4892fe388435 105 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
bogdanm 15:4892fe388435 106 .long LLW_IRQHandler /* Low Leakage Wakeup */
bogdanm 15:4892fe388435 107 .long I2C0_IRQHandler /* I2C0 interrupt */
bogdanm 15:4892fe388435 108 .long I2C1_IRQHandler /* I2C0 interrupt 25 */
bogdanm 15:4892fe388435 109 .long SPI0_IRQHandler /* SPI0 interrupt */
bogdanm 15:4892fe388435 110 .long SPI1_IRQHandler /* SPI1 interrupt */
bogdanm 15:4892fe388435 111 .long UART0_IRQHandler /* UART0 status/error interrupt */
bogdanm 15:4892fe388435 112 .long UART1_IRQHandler /* UART1 status/error interrupt */
bogdanm 15:4892fe388435 113 .long UART2_IRQHandler /* UART2 status/error interrupt */
bogdanm 15:4892fe388435 114 .long ADC0_IRQHandler /* ADC0 interrupt */
bogdanm 15:4892fe388435 115 .long CMP0_IRQHandler /* CMP0 interrupt */
bogdanm 15:4892fe388435 116 .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
bogdanm 15:4892fe388435 117 .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
bogdanm 15:4892fe388435 118 .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
bogdanm 15:4892fe388435 119 .long RTC_IRQHandler /* RTC interrupt */
bogdanm 15:4892fe388435 120 .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
bogdanm 15:4892fe388435 121 .long PIT_IRQHandler /* PIT timer interrupt */
bogdanm 15:4892fe388435 122 .long Default_Handler /* Reserved interrupt 39 */
bogdanm 15:4892fe388435 123 .long USB0_IRQHandler /* USB0 interrupt */
bogdanm 15:4892fe388435 124 .long DAC0_IRQHandler /* DAC interrupt */
bogdanm 15:4892fe388435 125 .long TSI0_IRQHandler /* TSI0 interrupt */
bogdanm 15:4892fe388435 126 .long MCG_IRQHandler /* MCG interrupt */
bogdanm 15:4892fe388435 127 .long LPTimer_IRQHandler /* LPTimer interrupt */
bogdanm 15:4892fe388435 128 .long Default_Handler /* Reserved interrupt 45 */
bogdanm 15:4892fe388435 129 .long PORTA_IRQHandler /* Port A interrupt */
bogdanm 15:4892fe388435 130 .long PORTD_IRQHandler /* Port D interrupt */
bogdanm 15:4892fe388435 131
bogdanm 15:4892fe388435 132 .size __isr_vector, . - __isr_vector
bogdanm 15:4892fe388435 133
bogdanm 15:4892fe388435 134 .section .text.Reset_Handler
bogdanm 15:4892fe388435 135 .thumb
bogdanm 15:4892fe388435 136 .thumb_func
bogdanm 15:4892fe388435 137 .align 2
bogdanm 15:4892fe388435 138 .globl Reset_Handler
bogdanm 15:4892fe388435 139 .type Reset_Handler, %function
bogdanm 15:4892fe388435 140 Reset_Handler:
bogdanm 15:4892fe388435 141 /* Loop to copy data from read only memory to RAM. The ranges
bogdanm 15:4892fe388435 142 * of copy from/to are specified by following symbols evaluated in
bogdanm 15:4892fe388435 143 * linker script.
bogdanm 15:4892fe388435 144 * __etext: End of code section, i.e., begin of data sections to copy from.
bogdanm 15:4892fe388435 145 * __data_start__/__data_end__: RAM address range that data should be
bogdanm 15:4892fe388435 146 * copied to. Both must be aligned to 4 bytes boundary. */
bogdanm 15:4892fe388435 147
bogdanm 15:4892fe388435 148 ldr r1, =__etext
bogdanm 15:4892fe388435 149 ldr r2, =__data_start__
bogdanm 15:4892fe388435 150 ldr r3, =__data_end__
bogdanm 15:4892fe388435 151
bogdanm 15:4892fe388435 152 subs r3, r2
bogdanm 15:4892fe388435 153 ble .flash_to_ram_loop_end
bogdanm 15:4892fe388435 154
bogdanm 15:4892fe388435 155 movs r4, 0
bogdanm 15:4892fe388435 156 .flash_to_ram_loop:
bogdanm 15:4892fe388435 157 ldr r0, [r1,r4]
bogdanm 15:4892fe388435 158 str r0, [r2,r4]
bogdanm 15:4892fe388435 159 adds r4, 4
bogdanm 15:4892fe388435 160 cmp r4, r3
bogdanm 15:4892fe388435 161 blt .flash_to_ram_loop
bogdanm 15:4892fe388435 162 .flash_to_ram_loop_end:
bogdanm 15:4892fe388435 163
bogdanm 15:4892fe388435 164 ldr r0, =SystemInit
bogdanm 15:4892fe388435 165 blx r0
bogdanm 15:4892fe388435 166 ldr r0, =_start
bogdanm 15:4892fe388435 167 bx r0
bogdanm 15:4892fe388435 168 .pool
bogdanm 15:4892fe388435 169 .size Reset_Handler, . - Reset_Handler
bogdanm 15:4892fe388435 170
bogdanm 15:4892fe388435 171 .text
bogdanm 15:4892fe388435 172 /* Macro to define default handlers. Default handler
bogdanm 15:4892fe388435 173 * will be weak symbol and just dead loops. They can be
bogdanm 15:4892fe388435 174 * overwritten by other handlers */
bogdanm 15:4892fe388435 175 .macro def_default_handler handler_name
bogdanm 15:4892fe388435 176 .align 1
bogdanm 15:4892fe388435 177 .thumb_func
bogdanm 15:4892fe388435 178 .weak \handler_name
bogdanm 15:4892fe388435 179 .type \handler_name, %function
bogdanm 15:4892fe388435 180 \handler_name :
bogdanm 15:4892fe388435 181 b .
bogdanm 15:4892fe388435 182 .size \handler_name, . - \handler_name
bogdanm 15:4892fe388435 183 .endm
bogdanm 15:4892fe388435 184
bogdanm 15:4892fe388435 185 def_default_handler NMI_Handler
bogdanm 15:4892fe388435 186 def_default_handler HardFault_Handler
bogdanm 15:4892fe388435 187 def_default_handler SVC_Handler
bogdanm 15:4892fe388435 188 def_default_handler PendSV_Handler
bogdanm 15:4892fe388435 189 def_default_handler SysTick_Handler
bogdanm 15:4892fe388435 190 def_default_handler Default_Handler
bogdanm 15:4892fe388435 191
bogdanm 15:4892fe388435 192 def_default_handler DMA0_IRQHandler
bogdanm 15:4892fe388435 193 def_default_handler DMA1_IRQHandler
bogdanm 15:4892fe388435 194 def_default_handler DMA2_IRQHandler
bogdanm 15:4892fe388435 195 def_default_handler DMA3_IRQHandler
bogdanm 15:4892fe388435 196 def_default_handler FTFA_IRQHandler
bogdanm 15:4892fe388435 197 def_default_handler LVD_LVW_IRQHandler
bogdanm 15:4892fe388435 198 def_default_handler LLW_IRQHandler
bogdanm 15:4892fe388435 199 def_default_handler I2C0_IRQHandler
bogdanm 15:4892fe388435 200 def_default_handler I2C1_IRQHandler
bogdanm 15:4892fe388435 201 def_default_handler SPI0_IRQHandler
bogdanm 15:4892fe388435 202 def_default_handler SPI1_IRQHandler
bogdanm 15:4892fe388435 203 def_default_handler UART0_IRQHandler
bogdanm 15:4892fe388435 204 def_default_handler UART1_IRQHandler
bogdanm 15:4892fe388435 205 def_default_handler UART2_IRQHandler
bogdanm 15:4892fe388435 206 def_default_handler ADC0_IRQHandler
bogdanm 15:4892fe388435 207 def_default_handler CMP0_IRQHandler
bogdanm 15:4892fe388435 208 def_default_handler TPM0_IRQHandler
bogdanm 15:4892fe388435 209 def_default_handler TPM1_IRQHandler
bogdanm 15:4892fe388435 210 def_default_handler TPM2_IRQHandler
bogdanm 15:4892fe388435 211 def_default_handler RTC_IRQHandler
bogdanm 15:4892fe388435 212 def_default_handler RTC_Seconds_IRQHandler
bogdanm 15:4892fe388435 213 def_default_handler PIT_IRQHandler
bogdanm 15:4892fe388435 214 def_default_handler USB0_IRQHandler
bogdanm 15:4892fe388435 215 def_default_handler DAC0_IRQHandler
bogdanm 15:4892fe388435 216 def_default_handler TSI0_IRQHandler
bogdanm 15:4892fe388435 217 def_default_handler MCG_IRQHandler
bogdanm 15:4892fe388435 218 def_default_handler LPTimer_IRQHandler
bogdanm 15:4892fe388435 219 def_default_handler PORTA_IRQHandler
bogdanm 15:4892fe388435 220 def_default_handler PORTD_IRQHandler
bogdanm 15:4892fe388435 221
bogdanm 15:4892fe388435 222 .weak DEF_IRQHandler
bogdanm 15:4892fe388435 223 .set DEF_IRQHandler, Default_Handler
bogdanm 15:4892fe388435 224
bogdanm 15:4892fe388435 225 /* Flash protection region, placed at 0x400 */
bogdanm 15:4892fe388435 226 .text
bogdanm 15:4892fe388435 227 .thumb
bogdanm 15:4892fe388435 228 .align 2
bogdanm 15:4892fe388435 229 .section .kinetis_flash_config_field,"a",%progbits
bogdanm 15:4892fe388435 230 kinetis_flash_config:
bogdanm 15:4892fe388435 231 .long 0xffffffff
bogdanm 15:4892fe388435 232 .long 0xffffffff
bogdanm 15:4892fe388435 233 .long 0xffffffff
bogdanm 15:4892fe388435 234 .long 0xfffffffe
bogdanm 15:4892fe388435 235
bogdanm 15:4892fe388435 236 .end