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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c@110:410346174f7a, 2014-03-04 (annotated)

Committer:: mbed_official
Date:: Tue Mar 04 10:30:06 2014 +0000
Revision:: 110:410346174f7a
Parent:: 84:f54042cbc282
Child:: 139:e3413eddde57

Synchronized with git revision 6d794061129a95b908b534cbddf5e6fe741b5ced

Full URL: https://github.com/mbedmicro/mbed/commit/6d794061129a95b908b534cbddf5e6fe741b5ced/

Added LPC11U35_501 target support

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	52:a51c77007319	1	/**
mbed_official	52:a51c77007319	2	******************************************************************************
mbed_official	52:a51c77007319	3	* @file system_stm32f10x.c
mbed_official	52:a51c77007319	4	* @author MCD Application Team
mbed_official	84:f54042cbc282	5	* @version V3.6.1
mbed_official	84:f54042cbc282	6	* @date 05-March-2012
mbed_official	52:a51c77007319	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official	52:a51c77007319	8	*
mbed_official	52:a51c77007319	9	* 1. This file provides two functions and one global variable to be called from
mbed_official	52:a51c77007319	10	* user application:
mbed_official	52:a51c77007319	11	* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official	52:a51c77007319	12	* factors, AHB/APBx prescalers and Flash settings).
mbed_official	52:a51c77007319	13	* This function is called at startup just after reset and
mbed_official	52:a51c77007319	14	* before branch to main program. This call is made inside
mbed_official	52:a51c77007319	15	* the "startup_stm32f10x_xx.s" file.
mbed_official	52:a51c77007319	16	*
mbed_official	52:a51c77007319	17	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	52:a51c77007319	18	* by the user application to setup the SysTick
mbed_official	52:a51c77007319	19	* timer or configure other parameters.
mbed_official	52:a51c77007319	20	*
mbed_official	52:a51c77007319	21	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	52:a51c77007319	22	* be called whenever the core clock is changed
mbed_official	52:a51c77007319	23	* during program execution.
mbed_official	52:a51c77007319	24	*
mbed_official	52:a51c77007319	25	* 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official	52:a51c77007319	26	* Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
mbed_official	52:a51c77007319	27	* configure the system clock before to branch to main program.
mbed_official	52:a51c77007319	28	*
mbed_official	52:a51c77007319	29	* 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official	52:a51c77007319	30	* function will do nothing and HSI still used as system clock source. User can
mbed_official	52:a51c77007319	31	* add some code to deal with this issue inside the SetSysClock() function.
mbed_official	52:a51c77007319	32	*
mbed_official	52:a51c77007319	33	* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
mbed_official	52:a51c77007319	34	* the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
mbed_official	52:a51c77007319	35	* When HSE is used as system clock source, directly or through PLL, and you
mbed_official	52:a51c77007319	36	* are using different crystal you have to adapt the HSE value to your own
mbed_official	52:a51c77007319	37	* configuration.
mbed_official	52:a51c77007319	38	*
mbed_official	70:c1fbde68b492	39	*******************************************************************************
mbed_official	70:c1fbde68b492	40	* Copyright (c) 2014, STMicroelectronics
mbed_official	70:c1fbde68b492	41	* All rights reserved.
mbed_official	70:c1fbde68b492	42	*
mbed_official	70:c1fbde68b492	43	* Redistribution and use in source and binary forms, with or without
mbed_official	70:c1fbde68b492	44	* modification, are permitted provided that the following conditions are met:
mbed_official	70:c1fbde68b492	45	*
mbed_official	70:c1fbde68b492	46	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	70:c1fbde68b492	47	* this list of conditions and the following disclaimer.
mbed_official	70:c1fbde68b492	48	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	70:c1fbde68b492	49	* this list of conditions and the following disclaimer in the documentation
mbed_official	70:c1fbde68b492	50	* and/or other materials provided with the distribution.
mbed_official	70:c1fbde68b492	51	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	70:c1fbde68b492	52	* may be used to endorse or promote products derived from this software
mbed_official	70:c1fbde68b492	53	* without specific prior written permission.
mbed_official	70:c1fbde68b492	54	*
mbed_official	70:c1fbde68b492	55	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	70:c1fbde68b492	56	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	70:c1fbde68b492	57	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	70:c1fbde68b492	58	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	70:c1fbde68b492	59	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	70:c1fbde68b492	60	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	70:c1fbde68b492	61	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	70:c1fbde68b492	62	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	70:c1fbde68b492	63	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	70:c1fbde68b492	64	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	70:c1fbde68b492	65	*******************************************************************************
mbed_official	70:c1fbde68b492	66	*/
mbed_official	52:a51c77007319	67
mbed_official	52:a51c77007319	68	/** @addtogroup CMSIS
mbed_official	52:a51c77007319	69	* @{
mbed_official	52:a51c77007319	70	*/
mbed_official	52:a51c77007319	71
mbed_official	52:a51c77007319	72	/** @addtogroup stm32f10x_system
mbed_official	52:a51c77007319	73	* @{
mbed_official	52:a51c77007319	74	*/
mbed_official	52:a51c77007319	75
mbed_official	52:a51c77007319	76	/** @addtogroup STM32F10x_System_Private_Includes
mbed_official	52:a51c77007319	77	* @{
mbed_official	52:a51c77007319	78	*/
mbed_official	52:a51c77007319	79
mbed_official	52:a51c77007319	80	#include "stm32f10x.h"
mbed_official	52:a51c77007319	81
mbed_official	52:a51c77007319	82	/**
mbed_official	52:a51c77007319	83	* @}
mbed_official	52:a51c77007319	84	*/
mbed_official	52:a51c77007319	85
mbed_official	52:a51c77007319	86	/** @addtogroup STM32F10x_System_Private_TypesDefinitions
mbed_official	52:a51c77007319	87	* @{
mbed_official	52:a51c77007319	88	*/
mbed_official	52:a51c77007319	89
mbed_official	52:a51c77007319	90	/**
mbed_official	52:a51c77007319	91	* @}
mbed_official	52:a51c77007319	92	*/
mbed_official	52:a51c77007319	93
mbed_official	52:a51c77007319	94	/** @addtogroup STM32F10x_System_Private_Defines
mbed_official	52:a51c77007319	95	* @{
mbed_official	52:a51c77007319	96	*/
mbed_official	52:a51c77007319	97
mbed_official	52:a51c77007319	98	/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
mbed_official	52:a51c77007319	99	frequency (after reset the HSI is used as SYSCLK source)
mbed_official	52:a51c77007319	100
mbed_official	52:a51c77007319	101	IMPORTANT NOTE:
mbed_official	52:a51c77007319	102	==============
mbed_official	52:a51c77007319	103	1. After each device reset the HSI is used as System clock source.
mbed_official	52:a51c77007319	104
mbed_official	52:a51c77007319	105	2. Please make sure that the selected System clock doesn't exceed your device's
mbed_official	52:a51c77007319	106	maximum frequency.
mbed_official	52:a51c77007319	107
mbed_official	52:a51c77007319	108	3. If none of the define below is enabled, the HSI is used as System clock
mbed_official	52:a51c77007319	109	source.
mbed_official	52:a51c77007319	110
mbed_official	52:a51c77007319	111	4. The System clock configuration functions provided within this file assume that:
mbed_official	52:a51c77007319	112	- For Low, Medium and High density Value line devices an external 8MHz
mbed_official	52:a51c77007319	113	crystal is used to drive the System clock.
mbed_official	52:a51c77007319	114	- For Low, Medium and High density devices an external 8MHz crystal is
mbed_official	52:a51c77007319	115	used to drive the System clock.
mbed_official	52:a51c77007319	116	- For Connectivity line devices an external 25MHz crystal is used to drive
mbed_official	52:a51c77007319	117	the System clock.
mbed_official	52:a51c77007319	118	If you are using different crystal you have to adapt those functions accordingly.
mbed_official	52:a51c77007319	119	*/
mbed_official	52:a51c77007319	120
mbed_official	52:a51c77007319	121	#if defined (STM32F10X_LD_VL) \|\| (defined STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	122	/* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official	62:7731d679ae64	123	/* #define SYSCLK_FREQ_24MHz 24000000 */
mbed_official	52:a51c77007319	124	#else
mbed_official	52:a51c77007319	125	/* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official	52:a51c77007319	126	/* #define SYSCLK_FREQ_24MHz 24000000 */
mbed_official	52:a51c77007319	127	/* #define SYSCLK_FREQ_36MHz 36000000 */
mbed_official	52:a51c77007319	128	/* #define SYSCLK_FREQ_48MHz 48000000 */
mbed_official	52:a51c77007319	129	/* #define SYSCLK_FREQ_56MHz 56000000 */
mbed_official	62:7731d679ae64	130	/* #define SYSCLK_FREQ_72MHz 72000000 */
mbed_official	52:a51c77007319	131	#endif
mbed_official	52:a51c77007319	132
mbed_official	52:a51c77007319	133	/*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official	52:a51c77007319	134	on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
mbed_official	52:a51c77007319	135	STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
mbed_official	52:a51c77007319	136	#if defined (STM32F10X_HD) \|\| (defined STM32F10X_XL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	137	/* #define DATA_IN_ExtSRAM */
mbed_official	52:a51c77007319	138	#endif
mbed_official	52:a51c77007319	139
mbed_official	52:a51c77007319	140	/*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official	52:a51c77007319	141	Internal SRAM. */
mbed_official	52:a51c77007319	142	/* #define VECT_TAB_SRAM */
mbed_official	52:a51c77007319	143	#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official	52:a51c77007319	144	This value must be a multiple of 0x200. */
mbed_official	52:a51c77007319	145
mbed_official	52:a51c77007319	146
mbed_official	52:a51c77007319	147	/**
mbed_official	52:a51c77007319	148	* @}
mbed_official	52:a51c77007319	149	*/
mbed_official	52:a51c77007319	150
mbed_official	52:a51c77007319	151	/** @addtogroup STM32F10x_System_Private_Macros
mbed_official	52:a51c77007319	152	* @{
mbed_official	52:a51c77007319	153	*/
mbed_official	52:a51c77007319	154
mbed_official	52:a51c77007319	155	/**
mbed_official	52:a51c77007319	156	* @}
mbed_official	52:a51c77007319	157	*/
mbed_official	52:a51c77007319	158
mbed_official	52:a51c77007319	159	/** @addtogroup STM32F10x_System_Private_Variables
mbed_official	52:a51c77007319	160	* @{
mbed_official	52:a51c77007319	161	*/
mbed_official	52:a51c77007319	162
mbed_official	52:a51c77007319	163	/*******************************************************************************
mbed_official	52:a51c77007319	164	* Clock Definitions
mbed_official	52:a51c77007319	165	*******************************************************************************/
mbed_official	52:a51c77007319	166	#ifdef SYSCLK_FREQ_HSE
mbed_official	52:a51c77007319	167	uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	168	#elif defined SYSCLK_FREQ_24MHz
mbed_official	52:a51c77007319	169	uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	170	#elif defined SYSCLK_FREQ_36MHz
mbed_official	52:a51c77007319	171	uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	172	#elif defined SYSCLK_FREQ_48MHz
mbed_official	52:a51c77007319	173	uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	174	#elif defined SYSCLK_FREQ_56MHz
mbed_official	52:a51c77007319	175	uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	176	#elif defined SYSCLK_FREQ_72MHz
mbed_official	52:a51c77007319	177	uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	178	#else /!< HSI Selected as System Clock source /
mbed_official	52:a51c77007319	179	uint32_t SystemCoreClock = HSI_VALUE; /!< System Clock Frequency (Core Clock) /
mbed_official	52:a51c77007319	180	#endif
mbed_official	52:a51c77007319	181
mbed_official	52:a51c77007319	182	__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	52:a51c77007319	183	/**
mbed_official	52:a51c77007319	184	* @}
mbed_official	52:a51c77007319	185	*/
mbed_official	52:a51c77007319	186
mbed_official	52:a51c77007319	187	/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
mbed_official	52:a51c77007319	188	* @{
mbed_official	52:a51c77007319	189	*/
mbed_official	52:a51c77007319	190
mbed_official	52:a51c77007319	191	static void SetSysClock(void);
mbed_official	52:a51c77007319	192
mbed_official	52:a51c77007319	193	#ifdef SYSCLK_FREQ_HSE
mbed_official	52:a51c77007319	194	static void SetSysClockToHSE(void);
mbed_official	52:a51c77007319	195	#elif defined SYSCLK_FREQ_24MHz
mbed_official	52:a51c77007319	196	static void SetSysClockTo24(void);
mbed_official	52:a51c77007319	197	#elif defined SYSCLK_FREQ_36MHz
mbed_official	52:a51c77007319	198	static void SetSysClockTo36(void);
mbed_official	52:a51c77007319	199	#elif defined SYSCLK_FREQ_48MHz
mbed_official	52:a51c77007319	200	static void SetSysClockTo48(void);
mbed_official	52:a51c77007319	201	#elif defined SYSCLK_FREQ_56MHz
mbed_official	52:a51c77007319	202	static void SetSysClockTo56(void);
mbed_official	52:a51c77007319	203	#elif defined SYSCLK_FREQ_72MHz
mbed_official	52:a51c77007319	204	static void SetSysClockTo72(void);
mbed_official	52:a51c77007319	205	#endif
mbed_official	52:a51c77007319	206
mbed_official	52:a51c77007319	207	#ifdef DATA_IN_ExtSRAM
mbed_official	52:a51c77007319	208	static void SystemInit_ExtMemCtl(void);
mbed_official	52:a51c77007319	209	#endif /* DATA_IN_ExtSRAM */
mbed_official	52:a51c77007319	210
mbed_official	52:a51c77007319	211	/**
mbed_official	52:a51c77007319	212	* @}
mbed_official	52:a51c77007319	213	*/
mbed_official	52:a51c77007319	214
mbed_official	52:a51c77007319	215	/** @addtogroup STM32F10x_System_Private_Functions
mbed_official	52:a51c77007319	216	* @{
mbed_official	52:a51c77007319	217	*/
mbed_official	52:a51c77007319	218
mbed_official	52:a51c77007319	219	/**
mbed_official	52:a51c77007319	220	* @brief Setup the microcontroller system
mbed_official	52:a51c77007319	221	* Initialize the Embedded Flash Interface, the PLL and update the
mbed_official	52:a51c77007319	222	* SystemCoreClock variable.
mbed_official	52:a51c77007319	223	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	224	* @param None
mbed_official	52:a51c77007319	225	* @retval None
mbed_official	52:a51c77007319	226	*/
mbed_official	52:a51c77007319	227	void SystemInit (void)
mbed_official	52:a51c77007319	228	{
mbed_official	52:a51c77007319	229	/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
mbed_official	52:a51c77007319	230	/* Set HSION bit */
mbed_official	52:a51c77007319	231	RCC->CR \|= (uint32_t)0x00000001;
mbed_official	52:a51c77007319	232
mbed_official	52:a51c77007319	233	/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
mbed_official	52:a51c77007319	234	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	235	RCC->CFGR &= (uint32_t)0xF8FF0000;
mbed_official	52:a51c77007319	236	#else
mbed_official	52:a51c77007319	237	RCC->CFGR &= (uint32_t)0xF0FF0000;
mbed_official	52:a51c77007319	238	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	239
mbed_official	52:a51c77007319	240	/* Reset HSEON, CSSON and PLLON bits */
mbed_official	52:a51c77007319	241	RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official	52:a51c77007319	242
mbed_official	52:a51c77007319	243	/* Reset HSEBYP bit */
mbed_official	52:a51c77007319	244	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	52:a51c77007319	245
mbed_official	52:a51c77007319	246	/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
mbed_official	52:a51c77007319	247	RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official	52:a51c77007319	248
mbed_official	52:a51c77007319	249	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	250	/* Reset PLL2ON and PLL3ON bits */
mbed_official	52:a51c77007319	251	RCC->CR &= (uint32_t)0xEBFFFFFF;
mbed_official	52:a51c77007319	252
mbed_official	52:a51c77007319	253	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	254	RCC->CIR = 0x00FF0000;
mbed_official	52:a51c77007319	255
mbed_official	52:a51c77007319	256	/* Reset CFGR2 register */
mbed_official	52:a51c77007319	257	RCC->CFGR2 = 0x00000000;
mbed_official	52:a51c77007319	258	#elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	259	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	260	RCC->CIR = 0x009F0000;
mbed_official	52:a51c77007319	261
mbed_official	52:a51c77007319	262	/* Reset CFGR2 register */
mbed_official	52:a51c77007319	263	RCC->CFGR2 = 0x00000000;
mbed_official	52:a51c77007319	264	#else
mbed_official	52:a51c77007319	265	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	266	RCC->CIR = 0x009F0000;
mbed_official	52:a51c77007319	267	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	268
mbed_official	52:a51c77007319	269	#if defined (STM32F10X_HD) \|\| (defined STM32F10X_XL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	270	#ifdef DATA_IN_ExtSRAM
mbed_official	52:a51c77007319	271	SystemInit_ExtMemCtl();
mbed_official	52:a51c77007319	272	#endif /* DATA_IN_ExtSRAM */
mbed_official	52:a51c77007319	273	#endif
mbed_official	52:a51c77007319	274
mbed_official	52:a51c77007319	275	/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
mbed_official	52:a51c77007319	276	/* Configure the Flash Latency cycles and enable prefetch buffer */
mbed_official	52:a51c77007319	277	SetSysClock();
mbed_official	52:a51c77007319	278
mbed_official	52:a51c77007319	279	#ifdef VECT_TAB_SRAM
mbed_official	52:a51c77007319	280	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official	52:a51c77007319	281	#else
mbed_official	52:a51c77007319	282	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official	52:a51c77007319	283	#endif
mbed_official	52:a51c77007319	284	}
mbed_official	52:a51c77007319	285
mbed_official	52:a51c77007319	286	/**
mbed_official	52:a51c77007319	287	* @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official	52:a51c77007319	288	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	52:a51c77007319	289	* be used by the user application to setup the SysTick timer or configure
mbed_official	52:a51c77007319	290	* other parameters.
mbed_official	52:a51c77007319	291	*
mbed_official	52:a51c77007319	292	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	52:a51c77007319	293	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	52:a51c77007319	294	* based on this variable will be incorrect.
mbed_official	52:a51c77007319	295	*
mbed_official	52:a51c77007319	296	* @note - The system frequency computed by this function is not the real
mbed_official	52:a51c77007319	297	* frequency in the chip. It is calculated based on the predefined
mbed_official	52:a51c77007319	298	* constant and the selected clock source:
mbed_official	52:a51c77007319	299	*
mbed_official	52:a51c77007319	300	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	52:a51c77007319	301	*
mbed_official	52:a51c77007319	302	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	52:a51c77007319	303	*
mbed_official	52:a51c77007319	304	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	52:a51c77007319	305	* or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official	52:a51c77007319	306	*
mbed_official	52:a51c77007319	307	* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official	52:a51c77007319	308	* 8 MHz) but the real value may vary depending on the variations
mbed_official	52:a51c77007319	309	* in voltage and temperature.
mbed_official	52:a51c77007319	310	*
mbed_official	52:a51c77007319	311	* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official	52:a51c77007319	312	* 8 MHz or 25 MHz, depedning on the product used), user has to ensure
mbed_official	52:a51c77007319	313	* that HSE_VALUE is same as the real frequency of the crystal used.
mbed_official	52:a51c77007319	314	* Otherwise, this function may have wrong result.
mbed_official	52:a51c77007319	315	*
mbed_official	52:a51c77007319	316	* - The result of this function could be not correct when using fractional
mbed_official	52:a51c77007319	317	* value for HSE crystal.
mbed_official	52:a51c77007319	318	* @param None
mbed_official	52:a51c77007319	319	* @retval None
mbed_official	52:a51c77007319	320	*/
mbed_official	52:a51c77007319	321	void SystemCoreClockUpdate (void)
mbed_official	52:a51c77007319	322	{
mbed_official	52:a51c77007319	323	uint32_t tmp = 0, pllmull = 0, pllsource = 0;
mbed_official	52:a51c77007319	324
mbed_official	52:a51c77007319	325	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	326	uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
mbed_official	52:a51c77007319	327	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	328
mbed_official	52:a51c77007319	329	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	330	uint32_t prediv1factor = 0;
mbed_official	52:a51c77007319	331	#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
mbed_official	52:a51c77007319	332
mbed_official	52:a51c77007319	333	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	52:a51c77007319	334	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	52:a51c77007319	335
mbed_official	52:a51c77007319	336	switch (tmp)
mbed_official	52:a51c77007319	337	{
mbed_official	52:a51c77007319	338	case 0x00: /* HSI used as system clock */
mbed_official	52:a51c77007319	339	SystemCoreClock = HSI_VALUE;
mbed_official	52:a51c77007319	340	break;
mbed_official	52:a51c77007319	341	case 0x04: /* HSE used as system clock */
mbed_official	52:a51c77007319	342	SystemCoreClock = HSE_VALUE;
mbed_official	52:a51c77007319	343	break;
mbed_official	52:a51c77007319	344	case 0x08: /* PLL used as system clock */
mbed_official	52:a51c77007319	345
mbed_official	52:a51c77007319	346	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	52:a51c77007319	347	pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official	52:a51c77007319	348	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	52:a51c77007319	349
mbed_official	52:a51c77007319	350	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	351	pllmull = ( pllmull >> 18) + 2;
mbed_official	52:a51c77007319	352
mbed_official	52:a51c77007319	353	if (pllsource == 0x00)
mbed_official	52:a51c77007319	354	{
mbed_official	52:a51c77007319	355	/* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official	52:a51c77007319	356	SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	357	}
mbed_official	52:a51c77007319	358	else
mbed_official	52:a51c77007319	359	{
mbed_official	52:a51c77007319	360	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
mbed_official	52:a51c77007319	361	prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official	52:a51c77007319	362	/* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	363	SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	364	#else
mbed_official	52:a51c77007319	365	/* HSE selected as PLL clock entry */
mbed_official	52:a51c77007319	366	if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
mbed_official	52:a51c77007319	367	{/* HSE oscillator clock divided by 2 */
mbed_official	52:a51c77007319	368	SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	369	}
mbed_official	52:a51c77007319	370	else
mbed_official	52:a51c77007319	371	{
mbed_official	52:a51c77007319	372	SystemCoreClock = HSE_VALUE * pllmull;
mbed_official	52:a51c77007319	373	}
mbed_official	52:a51c77007319	374	#endif
mbed_official	52:a51c77007319	375	}
mbed_official	52:a51c77007319	376	#else
mbed_official	52:a51c77007319	377	pllmull = pllmull >> 18;
mbed_official	52:a51c77007319	378
mbed_official	52:a51c77007319	379	if (pllmull != 0x0D)
mbed_official	52:a51c77007319	380	{
mbed_official	52:a51c77007319	381	pllmull += 2;
mbed_official	52:a51c77007319	382	}
mbed_official	52:a51c77007319	383	else
mbed_official	52:a51c77007319	384	{ /* PLL multiplication factor = PLL input clock * 6.5 */
mbed_official	52:a51c77007319	385	pllmull = 13 / 2;
mbed_official	52:a51c77007319	386	}
mbed_official	52:a51c77007319	387
mbed_official	52:a51c77007319	388	if (pllsource == 0x00)
mbed_official	52:a51c77007319	389	{
mbed_official	52:a51c77007319	390	/* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official	52:a51c77007319	391	SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	392	}
mbed_official	52:a51c77007319	393	else
mbed_official	52:a51c77007319	394	{/* PREDIV1 selected as PLL clock entry */
mbed_official	52:a51c77007319	395
mbed_official	52:a51c77007319	396	/* Get PREDIV1 clock source and division factor */
mbed_official	52:a51c77007319	397	prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
mbed_official	52:a51c77007319	398	prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official	52:a51c77007319	399
mbed_official	52:a51c77007319	400	if (prediv1source == 0)
mbed_official	52:a51c77007319	401	{
mbed_official	52:a51c77007319	402	/* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	403	SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	404	}
mbed_official	52:a51c77007319	405	else
mbed_official	52:a51c77007319	406	{/* PLL2 clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	407
mbed_official	52:a51c77007319	408	/* Get PREDIV2 division factor and PLL2 multiplication factor */
mbed_official	52:a51c77007319	409	prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
mbed_official	52:a51c77007319	410	pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
mbed_official	52:a51c77007319	411	SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	412	}
mbed_official	52:a51c77007319	413	}
mbed_official	52:a51c77007319	414	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	415	break;
mbed_official	52:a51c77007319	416
mbed_official	52:a51c77007319	417	default:
mbed_official	52:a51c77007319	418	SystemCoreClock = HSI_VALUE;
mbed_official	52:a51c77007319	419	break;
mbed_official	52:a51c77007319	420	}
mbed_official	52:a51c77007319	421
mbed_official	52:a51c77007319	422	/* Compute HCLK clock frequency ----------------*/
mbed_official	52:a51c77007319	423	/* Get HCLK prescaler */
mbed_official	52:a51c77007319	424	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	52:a51c77007319	425	/* HCLK clock frequency */
mbed_official	52:a51c77007319	426	SystemCoreClock >>= tmp;
mbed_official	52:a51c77007319	427	}
mbed_official	52:a51c77007319	428
mbed_official	52:a51c77007319	429	/**
mbed_official	52:a51c77007319	430	* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
mbed_official	52:a51c77007319	431	* @param None
mbed_official	52:a51c77007319	432	* @retval None
mbed_official	52:a51c77007319	433	*/
mbed_official	52:a51c77007319	434	static void SetSysClock(void)
mbed_official	52:a51c77007319	435	{
mbed_official	52:a51c77007319	436	#ifdef SYSCLK_FREQ_HSE
mbed_official	52:a51c77007319	437	SetSysClockToHSE();
mbed_official	52:a51c77007319	438	#elif defined SYSCLK_FREQ_24MHz
mbed_official	52:a51c77007319	439	SetSysClockTo24();
mbed_official	52:a51c77007319	440	#elif defined SYSCLK_FREQ_36MHz
mbed_official	52:a51c77007319	441	SetSysClockTo36();
mbed_official	52:a51c77007319	442	#elif defined SYSCLK_FREQ_48MHz
mbed_official	52:a51c77007319	443	SetSysClockTo48();
mbed_official	52:a51c77007319	444	#elif defined SYSCLK_FREQ_56MHz
mbed_official	52:a51c77007319	445	SetSysClockTo56();
mbed_official	52:a51c77007319	446	#elif defined SYSCLK_FREQ_72MHz
mbed_official	52:a51c77007319	447	SetSysClockTo72();
mbed_official	52:a51c77007319	448	#endif
mbed_official	52:a51c77007319	449
mbed_official	52:a51c77007319	450	/* If none of the define above is enabled, the HSI is used as System clock
mbed_official	52:a51c77007319	451	source (default after reset) */
mbed_official	52:a51c77007319	452	}
mbed_official	52:a51c77007319	453
mbed_official	52:a51c77007319	454	/**
mbed_official	52:a51c77007319	455	* @brief Setup the external memory controller. Called in startup_stm32f10x.s
mbed_official	52:a51c77007319	456	* before jump to __main
mbed_official	52:a51c77007319	457	* @param None
mbed_official	52:a51c77007319	458	* @retval None
mbed_official	52:a51c77007319	459	*/
mbed_official	52:a51c77007319	460	#ifdef DATA_IN_ExtSRAM
mbed_official	52:a51c77007319	461	/**
mbed_official	52:a51c77007319	462	* @brief Setup the external memory controller.
mbed_official	52:a51c77007319	463	* Called in startup_stm32f10x_xx.s/.c before jump to main.
mbed_official	52:a51c77007319	464	* This function configures the external SRAM mounted on STM3210E-EVAL
mbed_official	52:a51c77007319	465	* board (STM32 High density devices). This SRAM will be used as program
mbed_official	52:a51c77007319	466	* data memory (including heap and stack).
mbed_official	52:a51c77007319	467	* @param None
mbed_official	52:a51c77007319	468	* @retval None
mbed_official	52:a51c77007319	469	*/
mbed_official	52:a51c77007319	470	void SystemInit_ExtMemCtl(void)
mbed_official	52:a51c77007319	471	{
mbed_official	52:a51c77007319	472	/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
mbed_official	52:a51c77007319	473	required, then adjust the Register Addresses */
mbed_official	52:a51c77007319	474
mbed_official	52:a51c77007319	475	/* Enable FSMC clock */
mbed_official	52:a51c77007319	476	RCC->AHBENR = 0x00000114;
mbed_official	52:a51c77007319	477
mbed_official	52:a51c77007319	478	/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
mbed_official	52:a51c77007319	479	RCC->APB2ENR = 0x000001E0;
mbed_official	52:a51c77007319	480
mbed_official	52:a51c77007319	481	/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
mbed_official	52:a51c77007319	482	/---------------- SRAM Address lines configuration -------------------------/
mbed_official	52:a51c77007319	483	/---------------- NOE and NWE configuration --------------------------------/
mbed_official	52:a51c77007319	484	/---------------- NE3 configuration ----------------------------------------/
mbed_official	52:a51c77007319	485	/---------------- NBL0, NBL1 configuration ---------------------------------/
mbed_official	52:a51c77007319	486
mbed_official	52:a51c77007319	487	GPIOD->CRL = 0x44BB44BB;
mbed_official	52:a51c77007319	488	GPIOD->CRH = 0xBBBBBBBB;
mbed_official	52:a51c77007319	489
mbed_official	52:a51c77007319	490	GPIOE->CRL = 0xB44444BB;
mbed_official	52:a51c77007319	491	GPIOE->CRH = 0xBBBBBBBB;
mbed_official	52:a51c77007319	492
mbed_official	52:a51c77007319	493	GPIOF->CRL = 0x44BBBBBB;
mbed_official	52:a51c77007319	494	GPIOF->CRH = 0xBBBB4444;
mbed_official	52:a51c77007319	495
mbed_official	52:a51c77007319	496	GPIOG->CRL = 0x44BBBBBB;
mbed_official	52:a51c77007319	497	GPIOG->CRH = 0x44444B44;
mbed_official	52:a51c77007319	498
mbed_official	52:a51c77007319	499	/---------------- FSMC Configuration ---------------------------------------/
mbed_official	52:a51c77007319	500	/---------------- Enable FSMC Bank1_SRAM Bank ------------------------------/
mbed_official	52:a51c77007319	501
mbed_official	52:a51c77007319	502	FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official	52:a51c77007319	503	FSMC_Bank1->BTCR[5] = 0x00000200;
mbed_official	52:a51c77007319	504	}
mbed_official	52:a51c77007319	505	#endif /* DATA_IN_ExtSRAM */
mbed_official	52:a51c77007319	506
mbed_official	52:a51c77007319	507	#ifdef SYSCLK_FREQ_HSE
mbed_official	52:a51c77007319	508	/**
mbed_official	52:a51c77007319	509	* @brief Selects HSE as System clock source and configure HCLK, PCLK2
mbed_official	52:a51c77007319	510	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	511	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	512	* @param None
mbed_official	52:a51c77007319	513	* @retval None
mbed_official	52:a51c77007319	514	*/
mbed_official	52:a51c77007319	515	static void SetSysClockToHSE(void)
mbed_official	52:a51c77007319	516	{
mbed_official	52:a51c77007319	517	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	518
mbed_official	52:a51c77007319	519	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	520	/* Enable HSE */
mbed_official	52:a51c77007319	521	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	522
mbed_official	52:a51c77007319	523	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	524	do
mbed_official	52:a51c77007319	525	{
mbed_official	52:a51c77007319	526	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	527	StartUpCounter++;
mbed_official	52:a51c77007319	528	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	529
mbed_official	52:a51c77007319	530	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	531	{
mbed_official	52:a51c77007319	532	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	533	}
mbed_official	52:a51c77007319	534	else
mbed_official	52:a51c77007319	535	{
mbed_official	52:a51c77007319	536	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	537	}
mbed_official	52:a51c77007319	538
mbed_official	52:a51c77007319	539	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	540	{
mbed_official	52:a51c77007319	541
mbed_official	52:a51c77007319	542	#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official	52:a51c77007319	543	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	544	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	545
mbed_official	52:a51c77007319	546	/* Flash 0 wait state */
mbed_official	52:a51c77007319	547	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	548
mbed_official	52:a51c77007319	549	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	550	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official	52:a51c77007319	551	#else
mbed_official	52:a51c77007319	552	if (HSE_VALUE <= 24000000)
mbed_official	52:a51c77007319	553	{
mbed_official	52:a51c77007319	554	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official	52:a51c77007319	555	}
mbed_official	52:a51c77007319	556	else
mbed_official	52:a51c77007319	557	{
mbed_official	52:a51c77007319	558	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official	52:a51c77007319	559	}
mbed_official	52:a51c77007319	560	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	561	#endif
mbed_official	52:a51c77007319	562
mbed_official	52:a51c77007319	563	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	564	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	565
mbed_official	52:a51c77007319	566	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	567	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	568
mbed_official	52:a51c77007319	569	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	570	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official	52:a51c77007319	571
mbed_official	52:a51c77007319	572	/* Select HSE as system clock source */
mbed_official	52:a51c77007319	573	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	574	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_HSE;
mbed_official	52:a51c77007319	575
mbed_official	52:a51c77007319	576	/* Wait till HSE is used as system clock source */
mbed_official	52:a51c77007319	577	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
mbed_official	52:a51c77007319	578	{
mbed_official	52:a51c77007319	579	}
mbed_official	52:a51c77007319	580	}
mbed_official	52:a51c77007319	581	else
mbed_official	52:a51c77007319	582	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	583	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	584	}
mbed_official	52:a51c77007319	585	}
mbed_official	52:a51c77007319	586	#elif defined SYSCLK_FREQ_24MHz
mbed_official	52:a51c77007319	587	/**
mbed_official	52:a51c77007319	588	* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
mbed_official	52:a51c77007319	589	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	590	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	591	* @param None
mbed_official	52:a51c77007319	592	* @retval None
mbed_official	52:a51c77007319	593	*/
mbed_official	52:a51c77007319	594	static void SetSysClockTo24(void)
mbed_official	52:a51c77007319	595	{
mbed_official	52:a51c77007319	596	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	597
mbed_official	52:a51c77007319	598	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	599	/* Enable HSE */
mbed_official	52:a51c77007319	600	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	601
mbed_official	52:a51c77007319	602	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	603	do
mbed_official	52:a51c77007319	604	{
mbed_official	52:a51c77007319	605	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	606	StartUpCounter++;
mbed_official	52:a51c77007319	607	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	608
mbed_official	52:a51c77007319	609	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	610	{
mbed_official	52:a51c77007319	611	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	612	}
mbed_official	52:a51c77007319	613	else
mbed_official	52:a51c77007319	614	{
mbed_official	52:a51c77007319	615	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	616	}
mbed_official	52:a51c77007319	617
mbed_official	52:a51c77007319	618	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	619	{
mbed_official	52:a51c77007319	620	#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official	52:a51c77007319	621	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	622	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	623
mbed_official	52:a51c77007319	624	/* Flash 0 wait state */
mbed_official	52:a51c77007319	625	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	626	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official	52:a51c77007319	627	#endif
mbed_official	52:a51c77007319	628
mbed_official	52:a51c77007319	629	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	630	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	631
mbed_official	52:a51c77007319	632	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	633	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	634
mbed_official	52:a51c77007319	635	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	636	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official	52:a51c77007319	637
mbed_official	52:a51c77007319	638	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	639	/* Configure PLLs ------------------------------------------------------*/
mbed_official	52:a51c77007319	640	/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
mbed_official	52:a51c77007319	641	RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
mbed_official	52:a51c77007319	642	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
mbed_official	52:a51c77007319	643	RCC_CFGR_PLLMULL6);
mbed_official	52:a51c77007319	644
mbed_official	52:a51c77007319	645	/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official	52:a51c77007319	646	/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official	52:a51c77007319	647	RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
mbed_official	52:a51c77007319	648	RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	649	RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
mbed_official	52:a51c77007319	650	RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV10);
mbed_official	52:a51c77007319	651
mbed_official	52:a51c77007319	652	/* Enable PLL2 */
mbed_official	52:a51c77007319	653	RCC->CR \|= RCC_CR_PLL2ON;
mbed_official	52:a51c77007319	654	/* Wait till PLL2 is ready */
mbed_official	52:a51c77007319	655	while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official	52:a51c77007319	656	{
mbed_official	52:a51c77007319	657	}
mbed_official	52:a51c77007319	658	#elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
mbed_official	52:a51c77007319	659	/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official	52:a51c77007319	660	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	661	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1_Div2 \| RCC_CFGR_PLLMULL6);
mbed_official	52:a51c77007319	662	#else
mbed_official	52:a51c77007319	663	/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official	52:a51c77007319	664	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	665	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLXTPRE_HSE_Div2 \| RCC_CFGR_PLLMULL6);
mbed_official	52:a51c77007319	666	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	667
mbed_official	52:a51c77007319	668	/* Enable PLL */
mbed_official	52:a51c77007319	669	RCC->CR \|= RCC_CR_PLLON;
mbed_official	52:a51c77007319	670
mbed_official	52:a51c77007319	671	/* Wait till PLL is ready */
mbed_official	52:a51c77007319	672	while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official	52:a51c77007319	673	{
mbed_official	52:a51c77007319	674	}
mbed_official	52:a51c77007319	675
mbed_official	52:a51c77007319	676	/* Select PLL as system clock source */
mbed_official	52:a51c77007319	677	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	678	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official	52:a51c77007319	679
mbed_official	52:a51c77007319	680	/* Wait till PLL is used as system clock source */
mbed_official	52:a51c77007319	681	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official	52:a51c77007319	682	{
mbed_official	52:a51c77007319	683	}
mbed_official	52:a51c77007319	684	}
mbed_official	52:a51c77007319	685	else
mbed_official	52:a51c77007319	686	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	687	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	688	}
mbed_official	52:a51c77007319	689	}
mbed_official	52:a51c77007319	690	#elif defined SYSCLK_FREQ_36MHz
mbed_official	52:a51c77007319	691	/**
mbed_official	52:a51c77007319	692	* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
mbed_official	52:a51c77007319	693	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	694	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	695	* @param None
mbed_official	52:a51c77007319	696	* @retval None
mbed_official	52:a51c77007319	697	*/
mbed_official	52:a51c77007319	698	static void SetSysClockTo36(void)
mbed_official	52:a51c77007319	699	{
mbed_official	52:a51c77007319	700	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	701
mbed_official	52:a51c77007319	702	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	703	/* Enable HSE */
mbed_official	52:a51c77007319	704	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	705
mbed_official	52:a51c77007319	706	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	707	do
mbed_official	52:a51c77007319	708	{
mbed_official	52:a51c77007319	709	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	710	StartUpCounter++;
mbed_official	52:a51c77007319	711	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	712
mbed_official	52:a51c77007319	713	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	714	{
mbed_official	52:a51c77007319	715	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	716	}
mbed_official	52:a51c77007319	717	else
mbed_official	52:a51c77007319	718	{
mbed_official	52:a51c77007319	719	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	720	}
mbed_official	52:a51c77007319	721
mbed_official	52:a51c77007319	722	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	723	{
mbed_official	52:a51c77007319	724	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	725	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	726
mbed_official	52:a51c77007319	727	/* Flash 1 wait state */
mbed_official	52:a51c77007319	728	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	729	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official	52:a51c77007319	730
mbed_official	52:a51c77007319	731	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	732	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	733
mbed_official	52:a51c77007319	734	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	735	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	736
mbed_official	52:a51c77007319	737	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	738	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official	52:a51c77007319	739
mbed_official	52:a51c77007319	740	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	741	/* Configure PLLs ------------------------------------------------------*/
mbed_official	52:a51c77007319	742
mbed_official	52:a51c77007319	743	/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
mbed_official	52:a51c77007319	744	RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
mbed_official	52:a51c77007319	745	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
mbed_official	52:a51c77007319	746	RCC_CFGR_PLLMULL9);
mbed_official	52:a51c77007319	747
mbed_official	52:a51c77007319	748	/!< PLL2 configuration: PLL2CLK = (HSE / 5) 8 = 40 MHz */
mbed_official	52:a51c77007319	749	/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official	52:a51c77007319	750
mbed_official	52:a51c77007319	751	RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
mbed_official	52:a51c77007319	752	RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	753	RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
mbed_official	52:a51c77007319	754	RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV10);
mbed_official	52:a51c77007319	755
mbed_official	52:a51c77007319	756	/* Enable PLL2 */
mbed_official	52:a51c77007319	757	RCC->CR \|= RCC_CR_PLL2ON;
mbed_official	52:a51c77007319	758	/* Wait till PLL2 is ready */
mbed_official	52:a51c77007319	759	while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official	52:a51c77007319	760	{
mbed_official	52:a51c77007319	761	}
mbed_official	52:a51c77007319	762
mbed_official	52:a51c77007319	763	#else
mbed_official	52:a51c77007319	764	/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
mbed_official	52:a51c77007319	765	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	766	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLXTPRE_HSE_Div2 \| RCC_CFGR_PLLMULL9);
mbed_official	52:a51c77007319	767	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	768
mbed_official	52:a51c77007319	769	/* Enable PLL */
mbed_official	52:a51c77007319	770	RCC->CR \|= RCC_CR_PLLON;
mbed_official	52:a51c77007319	771
mbed_official	52:a51c77007319	772	/* Wait till PLL is ready */
mbed_official	52:a51c77007319	773	while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official	52:a51c77007319	774	{
mbed_official	52:a51c77007319	775	}
mbed_official	52:a51c77007319	776
mbed_official	52:a51c77007319	777	/* Select PLL as system clock source */
mbed_official	52:a51c77007319	778	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	779	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official	52:a51c77007319	780
mbed_official	52:a51c77007319	781	/* Wait till PLL is used as system clock source */
mbed_official	52:a51c77007319	782	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official	52:a51c77007319	783	{
mbed_official	52:a51c77007319	784	}
mbed_official	52:a51c77007319	785	}
mbed_official	52:a51c77007319	786	else
mbed_official	52:a51c77007319	787	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	788	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	789	}
mbed_official	52:a51c77007319	790	}
mbed_official	52:a51c77007319	791	#elif defined SYSCLK_FREQ_48MHz
mbed_official	52:a51c77007319	792	/**
mbed_official	52:a51c77007319	793	* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
mbed_official	52:a51c77007319	794	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	795	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	796	* @param None
mbed_official	52:a51c77007319	797	* @retval None
mbed_official	52:a51c77007319	798	*/
mbed_official	52:a51c77007319	799	static void SetSysClockTo48(void)
mbed_official	52:a51c77007319	800	{
mbed_official	52:a51c77007319	801	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	802
mbed_official	52:a51c77007319	803	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	804	/* Enable HSE */
mbed_official	52:a51c77007319	805	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	806
mbed_official	52:a51c77007319	807	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	808	do
mbed_official	52:a51c77007319	809	{
mbed_official	52:a51c77007319	810	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	811	StartUpCounter++;
mbed_official	52:a51c77007319	812	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	813
mbed_official	52:a51c77007319	814	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	815	{
mbed_official	52:a51c77007319	816	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	817	}
mbed_official	52:a51c77007319	818	else
mbed_official	52:a51c77007319	819	{
mbed_official	52:a51c77007319	820	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	821	}
mbed_official	52:a51c77007319	822
mbed_official	52:a51c77007319	823	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	824	{
mbed_official	52:a51c77007319	825	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	826	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	827
mbed_official	52:a51c77007319	828	/* Flash 1 wait state */
mbed_official	52:a51c77007319	829	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	830	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official	52:a51c77007319	831
mbed_official	52:a51c77007319	832	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	833	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	834
mbed_official	52:a51c77007319	835	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	836	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	837
mbed_official	52:a51c77007319	838	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	839	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official	52:a51c77007319	840
mbed_official	52:a51c77007319	841	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	842	/* Configure PLLs ------------------------------------------------------*/
mbed_official	52:a51c77007319	843	/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official	52:a51c77007319	844	/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official	52:a51c77007319	845
mbed_official	52:a51c77007319	846	RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
mbed_official	52:a51c77007319	847	RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	848	RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
mbed_official	52:a51c77007319	849	RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
mbed_official	52:a51c77007319	850
mbed_official	52:a51c77007319	851	/* Enable PLL2 */
mbed_official	52:a51c77007319	852	RCC->CR \|= RCC_CR_PLL2ON;
mbed_official	52:a51c77007319	853	/* Wait till PLL2 is ready */
mbed_official	52:a51c77007319	854	while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official	52:a51c77007319	855	{
mbed_official	52:a51c77007319	856	}
mbed_official	52:a51c77007319	857
mbed_official	52:a51c77007319	858
mbed_official	52:a51c77007319	859	/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
mbed_official	52:a51c77007319	860	RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
mbed_official	52:a51c77007319	861	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
mbed_official	52:a51c77007319	862	RCC_CFGR_PLLMULL6);
mbed_official	52:a51c77007319	863	#else
mbed_official	52:a51c77007319	864	/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
mbed_official	52:a51c77007319	865	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	866	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL6);
mbed_official	52:a51c77007319	867	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	868
mbed_official	52:a51c77007319	869	/* Enable PLL */
mbed_official	52:a51c77007319	870	RCC->CR \|= RCC_CR_PLLON;
mbed_official	52:a51c77007319	871
mbed_official	52:a51c77007319	872	/* Wait till PLL is ready */
mbed_official	52:a51c77007319	873	while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official	52:a51c77007319	874	{
mbed_official	52:a51c77007319	875	}
mbed_official	52:a51c77007319	876
mbed_official	52:a51c77007319	877	/* Select PLL as system clock source */
mbed_official	52:a51c77007319	878	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	879	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official	52:a51c77007319	880
mbed_official	52:a51c77007319	881	/* Wait till PLL is used as system clock source */
mbed_official	52:a51c77007319	882	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official	52:a51c77007319	883	{
mbed_official	52:a51c77007319	884	}
mbed_official	52:a51c77007319	885	}
mbed_official	52:a51c77007319	886	else
mbed_official	52:a51c77007319	887	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	888	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	889	}
mbed_official	52:a51c77007319	890	}
mbed_official	52:a51c77007319	891
mbed_official	52:a51c77007319	892	#elif defined SYSCLK_FREQ_56MHz
mbed_official	52:a51c77007319	893	/**
mbed_official	52:a51c77007319	894	* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
mbed_official	52:a51c77007319	895	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	896	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	897	* @param None
mbed_official	52:a51c77007319	898	* @retval None
mbed_official	52:a51c77007319	899	*/
mbed_official	52:a51c77007319	900	static void SetSysClockTo56(void)
mbed_official	52:a51c77007319	901	{
mbed_official	52:a51c77007319	902	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	903
mbed_official	52:a51c77007319	904	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	905	/* Enable HSE */
mbed_official	52:a51c77007319	906	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	907
mbed_official	52:a51c77007319	908	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	909	do
mbed_official	52:a51c77007319	910	{
mbed_official	52:a51c77007319	911	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	912	StartUpCounter++;
mbed_official	52:a51c77007319	913	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	914
mbed_official	52:a51c77007319	915	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	916	{
mbed_official	52:a51c77007319	917	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	918	}
mbed_official	52:a51c77007319	919	else
mbed_official	52:a51c77007319	920	{
mbed_official	52:a51c77007319	921	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	922	}
mbed_official	52:a51c77007319	923
mbed_official	52:a51c77007319	924	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	925	{
mbed_official	52:a51c77007319	926	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	927	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	928
mbed_official	52:a51c77007319	929	/* Flash 2 wait state */
mbed_official	52:a51c77007319	930	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	931	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official	52:a51c77007319	932
mbed_official	52:a51c77007319	933	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	934	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	935
mbed_official	52:a51c77007319	936	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	937	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	938
mbed_official	52:a51c77007319	939	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	940	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official	52:a51c77007319	941
mbed_official	52:a51c77007319	942	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	943	/* Configure PLLs ------------------------------------------------------*/
mbed_official	52:a51c77007319	944	/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official	52:a51c77007319	945	/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official	52:a51c77007319	946
mbed_official	52:a51c77007319	947	RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
mbed_official	52:a51c77007319	948	RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	949	RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
mbed_official	52:a51c77007319	950	RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
mbed_official	52:a51c77007319	951
mbed_official	52:a51c77007319	952	/* Enable PLL2 */
mbed_official	52:a51c77007319	953	RCC->CR \|= RCC_CR_PLL2ON;
mbed_official	52:a51c77007319	954	/* Wait till PLL2 is ready */
mbed_official	52:a51c77007319	955	while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official	52:a51c77007319	956	{
mbed_official	52:a51c77007319	957	}
mbed_official	52:a51c77007319	958
mbed_official	52:a51c77007319	959
mbed_official	52:a51c77007319	960	/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
mbed_official	52:a51c77007319	961	RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
mbed_official	52:a51c77007319	962	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
mbed_official	52:a51c77007319	963	RCC_CFGR_PLLMULL7);
mbed_official	52:a51c77007319	964	#else
mbed_official	52:a51c77007319	965	/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
mbed_official	52:a51c77007319	966	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	967	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL7);
mbed_official	52:a51c77007319	968
mbed_official	52:a51c77007319	969	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	970
mbed_official	52:a51c77007319	971	/* Enable PLL */
mbed_official	52:a51c77007319	972	RCC->CR \|= RCC_CR_PLLON;
mbed_official	52:a51c77007319	973
mbed_official	52:a51c77007319	974	/* Wait till PLL is ready */
mbed_official	52:a51c77007319	975	while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official	52:a51c77007319	976	{
mbed_official	52:a51c77007319	977	}
mbed_official	52:a51c77007319	978
mbed_official	52:a51c77007319	979	/* Select PLL as system clock source */
mbed_official	52:a51c77007319	980	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	981	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official	52:a51c77007319	982
mbed_official	52:a51c77007319	983	/* Wait till PLL is used as system clock source */
mbed_official	52:a51c77007319	984	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official	52:a51c77007319	985	{
mbed_official	52:a51c77007319	986	}
mbed_official	52:a51c77007319	987	}
mbed_official	52:a51c77007319	988	else
mbed_official	52:a51c77007319	989	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	990	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	991	}
mbed_official	52:a51c77007319	992	}
mbed_official	52:a51c77007319	993
mbed_official	52:a51c77007319	994	#elif defined SYSCLK_FREQ_72MHz
mbed_official	52:a51c77007319	995	/**
mbed_official	52:a51c77007319	996	* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
mbed_official	52:a51c77007319	997	* and PCLK1 prescalers.
mbed_official	52:a51c77007319	998	* @note This function should be used only after reset.
mbed_official	52:a51c77007319	999	* @param None
mbed_official	52:a51c77007319	1000	* @retval None
mbed_official	52:a51c77007319	1001	*/
mbed_official	52:a51c77007319	1002	static void SetSysClockTo72(void)
mbed_official	52:a51c77007319	1003	{
mbed_official	52:a51c77007319	1004	__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official	52:a51c77007319	1005
mbed_official	52:a51c77007319	1006	/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official	52:a51c77007319	1007	/* Enable HSE */
mbed_official	52:a51c77007319	1008	RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
mbed_official	52:a51c77007319	1009
mbed_official	52:a51c77007319	1010	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	1011	do
mbed_official	52:a51c77007319	1012	{
mbed_official	52:a51c77007319	1013	HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official	52:a51c77007319	1014	StartUpCounter++;
mbed_official	52:a51c77007319	1015	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official	52:a51c77007319	1016
mbed_official	52:a51c77007319	1017	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official	52:a51c77007319	1018	{
mbed_official	52:a51c77007319	1019	HSEStatus = (uint32_t)0x01;
mbed_official	52:a51c77007319	1020	}
mbed_official	52:a51c77007319	1021	else
mbed_official	52:a51c77007319	1022	{
mbed_official	52:a51c77007319	1023	HSEStatus = (uint32_t)0x00;
mbed_official	52:a51c77007319	1024	}
mbed_official	52:a51c77007319	1025
mbed_official	52:a51c77007319	1026	if (HSEStatus == (uint32_t)0x01)
mbed_official	52:a51c77007319	1027	{
mbed_official	52:a51c77007319	1028	/* Enable Prefetch Buffer */
mbed_official	52:a51c77007319	1029	FLASH->ACR \|= FLASH_ACR_PRFTBE;
mbed_official	52:a51c77007319	1030
mbed_official	52:a51c77007319	1031	/* Flash 2 wait state */
mbed_official	52:a51c77007319	1032	FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official	52:a51c77007319	1033	FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official	52:a51c77007319	1034
mbed_official	52:a51c77007319	1035
mbed_official	52:a51c77007319	1036	/* HCLK = SYSCLK */
mbed_official	52:a51c77007319	1037	RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official	52:a51c77007319	1038
mbed_official	52:a51c77007319	1039	/* PCLK2 = HCLK */
mbed_official	52:a51c77007319	1040	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official	52:a51c77007319	1041
mbed_official	52:a51c77007319	1042	/* PCLK1 = HCLK */
mbed_official	52:a51c77007319	1043	RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official	52:a51c77007319	1044
mbed_official	52:a51c77007319	1045	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	1046	/* Configure PLLs ------------------------------------------------------*/
mbed_official	52:a51c77007319	1047	/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official	52:a51c77007319	1048	/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official	52:a51c77007319	1049
mbed_official	52:a51c77007319	1050	RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
mbed_official	52:a51c77007319	1051	RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	1052	RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
mbed_official	52:a51c77007319	1053	RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
mbed_official	52:a51c77007319	1054
mbed_official	52:a51c77007319	1055	/* Enable PLL2 */
mbed_official	52:a51c77007319	1056	RCC->CR \|= RCC_CR_PLL2ON;
mbed_official	52:a51c77007319	1057	/* Wait till PLL2 is ready */
mbed_official	52:a51c77007319	1058	while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official	52:a51c77007319	1059	{
mbed_official	52:a51c77007319	1060	}
mbed_official	52:a51c77007319	1061
mbed_official	52:a51c77007319	1062
mbed_official	52:a51c77007319	1063	/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
mbed_official	52:a51c77007319	1064	RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
mbed_official	52:a51c77007319	1065	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
mbed_official	52:a51c77007319	1066	RCC_CFGR_PLLMULL9);
mbed_official	52:a51c77007319	1067	#else
mbed_official	52:a51c77007319	1068	/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
mbed_official	52:a51c77007319	1069	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \|
mbed_official	52:a51c77007319	1070	RCC_CFGR_PLLMULL));
mbed_official	52:a51c77007319	1071	RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL9);
mbed_official	52:a51c77007319	1072	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	1073
mbed_official	52:a51c77007319	1074	/* Enable PLL */
mbed_official	52:a51c77007319	1075	RCC->CR \|= RCC_CR_PLLON;
mbed_official	52:a51c77007319	1076
mbed_official	52:a51c77007319	1077	/* Wait till PLL is ready */
mbed_official	52:a51c77007319	1078	while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official	52:a51c77007319	1079	{
mbed_official	52:a51c77007319	1080	}
mbed_official	52:a51c77007319	1081
mbed_official	52:a51c77007319	1082	/* Select PLL as system clock source */
mbed_official	52:a51c77007319	1083	RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official	52:a51c77007319	1084	RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official	52:a51c77007319	1085
mbed_official	52:a51c77007319	1086	/* Wait till PLL is used as system clock source */
mbed_official	52:a51c77007319	1087	while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official	52:a51c77007319	1088	{
mbed_official	52:a51c77007319	1089	}
mbed_official	52:a51c77007319	1090	}
mbed_official	52:a51c77007319	1091	else
mbed_official	52:a51c77007319	1092	{ /* If HSE fails to start-up, the application will have wrong clock
mbed_official	52:a51c77007319	1093	configuration. User can add here some code to deal with this error */
mbed_official	52:a51c77007319	1094	}
mbed_official	52:a51c77007319	1095	}
mbed_official	52:a51c77007319	1096	#endif
mbed_official	52:a51c77007319	1097
mbed_official	52:a51c77007319	1098	/**
mbed_official	52:a51c77007319	1099	* @}
mbed_official	52:a51c77007319	1100	*/
mbed_official	52:a51c77007319	1101
mbed_official	52:a51c77007319	1102	/**
mbed_official	52:a51c77007319	1103	* @}
mbed_official	52:a51c77007319	1104	*/
mbed_official	52:a51c77007319	1105
mbed_official	52:a51c77007319	1106	/**
mbed_official	52:a51c77007319	1107	* @}
mbed_official	52:a51c77007319	1108	*/
mbed_official	84:f54042cbc282	1109	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/