mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_WDOG_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_WDOG_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 WDOG
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Generation 2008 Watchdog Timer
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
mbed_official	324:406fd2029f23	93	* - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
mbed_official	324:406fd2029f23	94	* - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
mbed_official	324:406fd2029f23	95	* - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
mbed_official	324:406fd2029f23	96	* - HW_WDOG_WINH - Watchdog Window Register High
mbed_official	324:406fd2029f23	97	* - HW_WDOG_WINL - Watchdog Window Register Low
mbed_official	324:406fd2029f23	98	* - HW_WDOG_REFRESH - Watchdog Refresh register
mbed_official	324:406fd2029f23	99	* - HW_WDOG_UNLOCK - Watchdog Unlock register
mbed_official	324:406fd2029f23	100	* - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
mbed_official	324:406fd2029f23	101	* - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
mbed_official	324:406fd2029f23	102	* - HW_WDOG_RSTCNT - Watchdog Reset Count register
mbed_official	324:406fd2029f23	103	* - HW_WDOG_PRESC - Watchdog Prescaler register
mbed_official	324:406fd2029f23	104	*
mbed_official	324:406fd2029f23	105	* - hw_wdog_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	106	*/
mbed_official	324:406fd2029f23	107
mbed_official	324:406fd2029f23	108	#define HW_WDOG_INSTANCE_COUNT (1U) /!< Number of instances of the WDOG module. /
mbed_official	324:406fd2029f23	109
mbed_official	324:406fd2029f23	110	/*******************************************************************************
mbed_official	324:406fd2029f23	111	* HW_WDOG_STCTRLH - Watchdog Status and Control Register High
mbed_official	324:406fd2029f23	112	******************************************************************************/
mbed_official	324:406fd2029f23	113
mbed_official	324:406fd2029f23	114	/*!
mbed_official	324:406fd2029f23	115	* @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
mbed_official	324:406fd2029f23	116	*
mbed_official	324:406fd2029f23	117	* Reset value: 0x01D3U
mbed_official	324:406fd2029f23	118	*/
mbed_official	324:406fd2029f23	119	typedef union _hw_wdog_stctrlh
mbed_official	324:406fd2029f23	120	{
mbed_official	324:406fd2029f23	121	uint16_t U;
mbed_official	324:406fd2029f23	122	struct _hw_wdog_stctrlh_bitfields
mbed_official	324:406fd2029f23	123	{
mbed_official	324:406fd2029f23	124	uint16_t WDOGEN : 1; /!< [0] /
mbed_official	324:406fd2029f23	125	uint16_t CLKSRC : 1; /!< [1] /
mbed_official	324:406fd2029f23	126	uint16_t IRQRSTEN : 1; /!< [2] /
mbed_official	324:406fd2029f23	127	uint16_t WINEN : 1; /!< [3] /
mbed_official	324:406fd2029f23	128	uint16_t ALLOWUPDATE : 1; /!< [4] /
mbed_official	324:406fd2029f23	129	uint16_t DBGEN : 1; /!< [5] /
mbed_official	324:406fd2029f23	130	uint16_t STOPEN : 1; /!< [6] /
mbed_official	324:406fd2029f23	131	uint16_t WAITEN : 1; /!< [7] /
mbed_official	324:406fd2029f23	132	uint16_t RESERVED0 : 2; /!< [9:8] /
mbed_official	324:406fd2029f23	133	uint16_t TESTWDOG : 1; /!< [10] /
mbed_official	324:406fd2029f23	134	uint16_t TESTSEL : 1; /!< [11] /
mbed_official	324:406fd2029f23	135	uint16_t BYTESEL : 2; /!< [13:12] /
mbed_official	324:406fd2029f23	136	uint16_t DISTESTWDOG : 1; /!< [14] /
mbed_official	324:406fd2029f23	137	uint16_t RESERVED1 : 1; /!< [15] /
mbed_official	324:406fd2029f23	138	} B;
mbed_official	324:406fd2029f23	139	} hw_wdog_stctrlh_t;
mbed_official	324:406fd2029f23	140
mbed_official	324:406fd2029f23	141	/*!
mbed_official	324:406fd2029f23	142	* @name Constants and macros for entire WDOG_STCTRLH register
mbed_official	324:406fd2029f23	143	*/
mbed_official	324:406fd2029f23	144	/@{/
mbed_official	324:406fd2029f23	145	#define HW_WDOG_STCTRLH_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	146
mbed_official	324:406fd2029f23	147	#define HW_WDOG_STCTRLH(x) ((__IO hw_wdog_stctrlh_t ) HW_WDOG_STCTRLH_ADDR(x))
mbed_official	324:406fd2029f23	148	#define HW_WDOG_STCTRLH_RD(x) (HW_WDOG_STCTRLH(x).U)
mbed_official	324:406fd2029f23	149	#define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v))
mbed_official	324:406fd2029f23	150	#define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	151	#define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	152	#define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	153	/@}/
mbed_official	324:406fd2029f23	154
mbed_official	324:406fd2029f23	155	/*
mbed_official	324:406fd2029f23	156	* Constants & macros for individual WDOG_STCTRLH bitfields
mbed_official	324:406fd2029f23	157	*/
mbed_official	324:406fd2029f23	158
mbed_official	324:406fd2029f23	159	/*!
mbed_official	324:406fd2029f23	160	* @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
mbed_official	324:406fd2029f23	161	*
mbed_official	324:406fd2029f23	162	* Enables or disables the WDOG's operation. In the disabled state, the watchdog
mbed_official	324:406fd2029f23	163	* timer is kept in the reset state, but the other exception conditions can
mbed_official	324:406fd2029f23	164	* still trigger a reset/interrupt. A change in the value of this bit must be held
mbed_official	324:406fd2029f23	165	* for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
mbed_official	324:406fd2029f23	166	*
mbed_official	324:406fd2029f23	167	* Values:
mbed_official	324:406fd2029f23	168	* - 0 - WDOG is disabled.
mbed_official	324:406fd2029f23	169	* - 1 - WDOG is enabled.
mbed_official	324:406fd2029f23	170	*/
mbed_official	324:406fd2029f23	171	/@{/
mbed_official	324:406fd2029f23	172	#define BP_WDOG_STCTRLH_WDOGEN (0U) /!< Bit position for WDOG_STCTRLH_WDOGEN. /
mbed_official	324:406fd2029f23	173	#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) /!< Bit mask for WDOG_STCTRLH_WDOGEN. /
mbed_official	324:406fd2029f23	174	#define BS_WDOG_STCTRLH_WDOGEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. /
mbed_official	324:406fd2029f23	175
mbed_official	324:406fd2029f23	176	/! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. /
mbed_official	324:406fd2029f23	177	#define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN))
mbed_official	324:406fd2029f23	178
mbed_official	324:406fd2029f23	179	/! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. /
mbed_official	324:406fd2029f23	180	#define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN)
mbed_official	324:406fd2029f23	181
mbed_official	324:406fd2029f23	182	/! @brief Set the WDOGEN field to a new value. /
mbed_official	324:406fd2029f23	183	#define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v))
mbed_official	324:406fd2029f23	184	/@}/
mbed_official	324:406fd2029f23	185
mbed_official	324:406fd2029f23	186	/*!
mbed_official	324:406fd2029f23	187	* @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
mbed_official	324:406fd2029f23	188	*
mbed_official	324:406fd2029f23	189	* Selects clock source for the WDOG timer and other internal timing operations.
mbed_official	324:406fd2029f23	190	*
mbed_official	324:406fd2029f23	191	* Values:
mbed_official	324:406fd2029f23	192	* - 0 - WDOG clock sourced from LPO .
mbed_official	324:406fd2029f23	193	* - 1 - WDOG clock sourced from alternate clock source.
mbed_official	324:406fd2029f23	194	*/
mbed_official	324:406fd2029f23	195	/@{/
mbed_official	324:406fd2029f23	196	#define BP_WDOG_STCTRLH_CLKSRC (1U) /!< Bit position for WDOG_STCTRLH_CLKSRC. /
mbed_official	324:406fd2029f23	197	#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) /!< Bit mask for WDOG_STCTRLH_CLKSRC. /
mbed_official	324:406fd2029f23	198	#define BS_WDOG_STCTRLH_CLKSRC (1U) /!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. /
mbed_official	324:406fd2029f23	199
mbed_official	324:406fd2029f23	200	/! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. /
mbed_official	324:406fd2029f23	201	#define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC))
mbed_official	324:406fd2029f23	202
mbed_official	324:406fd2029f23	203	/! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. /
mbed_official	324:406fd2029f23	204	#define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC)
mbed_official	324:406fd2029f23	205
mbed_official	324:406fd2029f23	206	/! @brief Set the CLKSRC field to a new value. /
mbed_official	324:406fd2029f23	207	#define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v))
mbed_official	324:406fd2029f23	208	/@}/
mbed_official	324:406fd2029f23	209
mbed_official	324:406fd2029f23	210	/*!
mbed_official	324:406fd2029f23	211	* @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
mbed_official	324:406fd2029f23	212	*
mbed_official	324:406fd2029f23	213	* Used to enable the debug breadcrumbs feature. A change in this bit is updated
mbed_official	324:406fd2029f23	214	* immediately, as opposed to updating after WCT.
mbed_official	324:406fd2029f23	215	*
mbed_official	324:406fd2029f23	216	* Values:
mbed_official	324:406fd2029f23	217	* - 0 - WDOG time-out generates reset only.
mbed_official	324:406fd2029f23	218	* - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
mbed_official	324:406fd2029f23	219	* a reset.
mbed_official	324:406fd2029f23	220	*/
mbed_official	324:406fd2029f23	221	/@{/
mbed_official	324:406fd2029f23	222	#define BP_WDOG_STCTRLH_IRQRSTEN (2U) /!< Bit position for WDOG_STCTRLH_IRQRSTEN. /
mbed_official	324:406fd2029f23	223	#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /!< Bit mask for WDOG_STCTRLH_IRQRSTEN. /
mbed_official	324:406fd2029f23	224	#define BS_WDOG_STCTRLH_IRQRSTEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. /
mbed_official	324:406fd2029f23	225
mbed_official	324:406fd2029f23	226	/! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. /
mbed_official	324:406fd2029f23	227	#define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN))
mbed_official	324:406fd2029f23	228
mbed_official	324:406fd2029f23	229	/! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. /
mbed_official	324:406fd2029f23	230	#define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN)
mbed_official	324:406fd2029f23	231
mbed_official	324:406fd2029f23	232	/! @brief Set the IRQRSTEN field to a new value. /
mbed_official	324:406fd2029f23	233	#define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v))
mbed_official	324:406fd2029f23	234	/@}/
mbed_official	324:406fd2029f23	235
mbed_official	324:406fd2029f23	236	/*!
mbed_official	324:406fd2029f23	237	* @name Register WDOG_STCTRLH, field WINEN[3] (RW)
mbed_official	324:406fd2029f23	238	*
mbed_official	324:406fd2029f23	239	* Enables Windowing mode.
mbed_official	324:406fd2029f23	240	*
mbed_official	324:406fd2029f23	241	* Values:
mbed_official	324:406fd2029f23	242	* - 0 - Windowing mode is disabled.
mbed_official	324:406fd2029f23	243	* - 1 - Windowing mode is enabled.
mbed_official	324:406fd2029f23	244	*/
mbed_official	324:406fd2029f23	245	/@{/
mbed_official	324:406fd2029f23	246	#define BP_WDOG_STCTRLH_WINEN (3U) /!< Bit position for WDOG_STCTRLH_WINEN. /
mbed_official	324:406fd2029f23	247	#define BM_WDOG_STCTRLH_WINEN (0x0008U) /!< Bit mask for WDOG_STCTRLH_WINEN. /
mbed_official	324:406fd2029f23	248	#define BS_WDOG_STCTRLH_WINEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_WINEN. /
mbed_official	324:406fd2029f23	249
mbed_official	324:406fd2029f23	250	/! @brief Read current value of the WDOG_STCTRLH_WINEN field. /
mbed_official	324:406fd2029f23	251	#define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN))
mbed_official	324:406fd2029f23	252
mbed_official	324:406fd2029f23	253	/! @brief Format value for bitfield WDOG_STCTRLH_WINEN. /
mbed_official	324:406fd2029f23	254	#define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN)
mbed_official	324:406fd2029f23	255
mbed_official	324:406fd2029f23	256	/! @brief Set the WINEN field to a new value. /
mbed_official	324:406fd2029f23	257	#define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v))
mbed_official	324:406fd2029f23	258	/@}/
mbed_official	324:406fd2029f23	259
mbed_official	324:406fd2029f23	260	/*!
mbed_official	324:406fd2029f23	261	* @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
mbed_official	324:406fd2029f23	262	*
mbed_official	324:406fd2029f23	263	* Enables updates to watchdog write-once registers, after the reset-triggered
mbed_official	324:406fd2029f23	264	* initial configuration window (WCT) closes, through unlock sequence.
mbed_official	324:406fd2029f23	265	*
mbed_official	324:406fd2029f23	266	* Values:
mbed_official	324:406fd2029f23	267	* - 0 - No further updates allowed to WDOG write-once registers.
mbed_official	324:406fd2029f23	268	* - 1 - WDOG write-once registers can be unlocked for updating.
mbed_official	324:406fd2029f23	269	*/
mbed_official	324:406fd2029f23	270	/@{/
mbed_official	324:406fd2029f23	271	#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) /!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. /
mbed_official	324:406fd2029f23	272	#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. /
mbed_official	324:406fd2029f23	273	#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) /!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. /
mbed_official	324:406fd2029f23	274
mbed_official	324:406fd2029f23	275	/! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. /
mbed_official	324:406fd2029f23	276	#define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE))
mbed_official	324:406fd2029f23	277
mbed_official	324:406fd2029f23	278	/! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. /
mbed_official	324:406fd2029f23	279	#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE)
mbed_official	324:406fd2029f23	280
mbed_official	324:406fd2029f23	281	/! @brief Set the ALLOWUPDATE field to a new value. /
mbed_official	324:406fd2029f23	282	#define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
mbed_official	324:406fd2029f23	283	/@}/
mbed_official	324:406fd2029f23	284
mbed_official	324:406fd2029f23	285	/*!
mbed_official	324:406fd2029f23	286	* @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
mbed_official	324:406fd2029f23	287	*
mbed_official	324:406fd2029f23	288	* Enables or disables WDOG in Debug mode.
mbed_official	324:406fd2029f23	289	*
mbed_official	324:406fd2029f23	290	* Values:
mbed_official	324:406fd2029f23	291	* - 0 - WDOG is disabled in CPU Debug mode.
mbed_official	324:406fd2029f23	292	* - 1 - WDOG is enabled in CPU Debug mode.
mbed_official	324:406fd2029f23	293	*/
mbed_official	324:406fd2029f23	294	/@{/
mbed_official	324:406fd2029f23	295	#define BP_WDOG_STCTRLH_DBGEN (5U) /!< Bit position for WDOG_STCTRLH_DBGEN. /
mbed_official	324:406fd2029f23	296	#define BM_WDOG_STCTRLH_DBGEN (0x0020U) /!< Bit mask for WDOG_STCTRLH_DBGEN. /
mbed_official	324:406fd2029f23	297	#define BS_WDOG_STCTRLH_DBGEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_DBGEN. /
mbed_official	324:406fd2029f23	298
mbed_official	324:406fd2029f23	299	/! @brief Read current value of the WDOG_STCTRLH_DBGEN field. /
mbed_official	324:406fd2029f23	300	#define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN))
mbed_official	324:406fd2029f23	301
mbed_official	324:406fd2029f23	302	/! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. /
mbed_official	324:406fd2029f23	303	#define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN)
mbed_official	324:406fd2029f23	304
mbed_official	324:406fd2029f23	305	/! @brief Set the DBGEN field to a new value. /
mbed_official	324:406fd2029f23	306	#define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v))
mbed_official	324:406fd2029f23	307	/@}/
mbed_official	324:406fd2029f23	308
mbed_official	324:406fd2029f23	309	/*!
mbed_official	324:406fd2029f23	310	* @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
mbed_official	324:406fd2029f23	311	*
mbed_official	324:406fd2029f23	312	* Enables or disables WDOG in Stop mode.
mbed_official	324:406fd2029f23	313	*
mbed_official	324:406fd2029f23	314	* Values:
mbed_official	324:406fd2029f23	315	* - 0 - WDOG is disabled in CPU Stop mode.
mbed_official	324:406fd2029f23	316	* - 1 - WDOG is enabled in CPU Stop mode.
mbed_official	324:406fd2029f23	317	*/
mbed_official	324:406fd2029f23	318	/@{/
mbed_official	324:406fd2029f23	319	#define BP_WDOG_STCTRLH_STOPEN (6U) /!< Bit position for WDOG_STCTRLH_STOPEN. /
mbed_official	324:406fd2029f23	320	#define BM_WDOG_STCTRLH_STOPEN (0x0040U) /!< Bit mask for WDOG_STCTRLH_STOPEN. /
mbed_official	324:406fd2029f23	321	#define BS_WDOG_STCTRLH_STOPEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_STOPEN. /
mbed_official	324:406fd2029f23	322
mbed_official	324:406fd2029f23	323	/! @brief Read current value of the WDOG_STCTRLH_STOPEN field. /
mbed_official	324:406fd2029f23	324	#define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN))
mbed_official	324:406fd2029f23	325
mbed_official	324:406fd2029f23	326	/! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. /
mbed_official	324:406fd2029f23	327	#define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN)
mbed_official	324:406fd2029f23	328
mbed_official	324:406fd2029f23	329	/! @brief Set the STOPEN field to a new value. /
mbed_official	324:406fd2029f23	330	#define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v))
mbed_official	324:406fd2029f23	331	/@}/
mbed_official	324:406fd2029f23	332
mbed_official	324:406fd2029f23	333	/*!
mbed_official	324:406fd2029f23	334	* @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
mbed_official	324:406fd2029f23	335	*
mbed_official	324:406fd2029f23	336	* Enables or disables WDOG in Wait mode.
mbed_official	324:406fd2029f23	337	*
mbed_official	324:406fd2029f23	338	* Values:
mbed_official	324:406fd2029f23	339	* - 0 - WDOG is disabled in CPU Wait mode.
mbed_official	324:406fd2029f23	340	* - 1 - WDOG is enabled in CPU Wait mode.
mbed_official	324:406fd2029f23	341	*/
mbed_official	324:406fd2029f23	342	/@{/
mbed_official	324:406fd2029f23	343	#define BP_WDOG_STCTRLH_WAITEN (7U) /!< Bit position for WDOG_STCTRLH_WAITEN. /
mbed_official	324:406fd2029f23	344	#define BM_WDOG_STCTRLH_WAITEN (0x0080U) /!< Bit mask for WDOG_STCTRLH_WAITEN. /
mbed_official	324:406fd2029f23	345	#define BS_WDOG_STCTRLH_WAITEN (1U) /!< Bit field size in bits for WDOG_STCTRLH_WAITEN. /
mbed_official	324:406fd2029f23	346
mbed_official	324:406fd2029f23	347	/! @brief Read current value of the WDOG_STCTRLH_WAITEN field. /
mbed_official	324:406fd2029f23	348	#define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN))
mbed_official	324:406fd2029f23	349
mbed_official	324:406fd2029f23	350	/! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. /
mbed_official	324:406fd2029f23	351	#define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN)
mbed_official	324:406fd2029f23	352
mbed_official	324:406fd2029f23	353	/! @brief Set the WAITEN field to a new value. /
mbed_official	324:406fd2029f23	354	#define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v))
mbed_official	324:406fd2029f23	355	/@}/
mbed_official	324:406fd2029f23	356
mbed_official	324:406fd2029f23	357	/*!
mbed_official	324:406fd2029f23	358	* @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
mbed_official	324:406fd2029f23	359	*
mbed_official	324:406fd2029f23	360	* Puts the watchdog in the functional test mode. In this mode, the watchdog
mbed_official	324:406fd2029f23	361	* timer and the associated compare and reset generation logic is tested for correct
mbed_official	324:406fd2029f23	362	* operation. The clock for the timer is switched from the main watchdog clock
mbed_official	324:406fd2029f23	363	* to the fast clock input for watchdog functional test. The TESTSEL bit selects
mbed_official	324:406fd2029f23	364	* the test to be run.
mbed_official	324:406fd2029f23	365	*/
mbed_official	324:406fd2029f23	366	/@{/
mbed_official	324:406fd2029f23	367	#define BP_WDOG_STCTRLH_TESTWDOG (10U) /!< Bit position for WDOG_STCTRLH_TESTWDOG. /
mbed_official	324:406fd2029f23	368	#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /!< Bit mask for WDOG_STCTRLH_TESTWDOG. /
mbed_official	324:406fd2029f23	369	#define BS_WDOG_STCTRLH_TESTWDOG (1U) /!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. /
mbed_official	324:406fd2029f23	370
mbed_official	324:406fd2029f23	371	/! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. /
mbed_official	324:406fd2029f23	372	#define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG))
mbed_official	324:406fd2029f23	373
mbed_official	324:406fd2029f23	374	/! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. /
mbed_official	324:406fd2029f23	375	#define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG)
mbed_official	324:406fd2029f23	376
mbed_official	324:406fd2029f23	377	/! @brief Set the TESTWDOG field to a new value. /
mbed_official	324:406fd2029f23	378	#define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v))
mbed_official	324:406fd2029f23	379	/@}/
mbed_official	324:406fd2029f23	380
mbed_official	324:406fd2029f23	381	/*!
mbed_official	324:406fd2029f23	382	* @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
mbed_official	324:406fd2029f23	383	*
mbed_official	324:406fd2029f23	384	* Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
mbed_official	324:406fd2029f23	385	* timer.
mbed_official	324:406fd2029f23	386	*
mbed_official	324:406fd2029f23	387	* Values:
mbed_official	324:406fd2029f23	388	* - 0 - Quick test. The timer runs in normal operation. You can load a small
mbed_official	324:406fd2029f23	389	* time-out value to do a quick test.
mbed_official	324:406fd2029f23	390	* - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
mbed_official	324:406fd2029f23	391	* of the timer are enabled for operation and are compared for time-out
mbed_official	324:406fd2029f23	392	* against the corresponding byte of the programmed time-out value. Select the
mbed_official	324:406fd2029f23	393	* byte through BYTESEL[1:0] for testing.
mbed_official	324:406fd2029f23	394	*/
mbed_official	324:406fd2029f23	395	/@{/
mbed_official	324:406fd2029f23	396	#define BP_WDOG_STCTRLH_TESTSEL (11U) /!< Bit position for WDOG_STCTRLH_TESTSEL. /
mbed_official	324:406fd2029f23	397	#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) /!< Bit mask for WDOG_STCTRLH_TESTSEL. /
mbed_official	324:406fd2029f23	398	#define BS_WDOG_STCTRLH_TESTSEL (1U) /!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. /
mbed_official	324:406fd2029f23	399
mbed_official	324:406fd2029f23	400	/! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. /
mbed_official	324:406fd2029f23	401	#define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL))
mbed_official	324:406fd2029f23	402
mbed_official	324:406fd2029f23	403	/! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. /
mbed_official	324:406fd2029f23	404	#define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL)
mbed_official	324:406fd2029f23	405
mbed_official	324:406fd2029f23	406	/! @brief Set the TESTSEL field to a new value. /
mbed_official	324:406fd2029f23	407	#define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v))
mbed_official	324:406fd2029f23	408	/@}/
mbed_official	324:406fd2029f23	409
mbed_official	324:406fd2029f23	410	/*!
mbed_official	324:406fd2029f23	411	* @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
mbed_official	324:406fd2029f23	412	*
mbed_official	324:406fd2029f23	413	* This 2-bit field selects the byte to be tested when the watchdog is in the
mbed_official	324:406fd2029f23	414	* byte test mode.
mbed_official	324:406fd2029f23	415	*
mbed_official	324:406fd2029f23	416	* Values:
mbed_official	324:406fd2029f23	417	* - 00 - Byte 0 selected
mbed_official	324:406fd2029f23	418	* - 01 - Byte 1 selected
mbed_official	324:406fd2029f23	419	* - 10 - Byte 2 selected
mbed_official	324:406fd2029f23	420	* - 11 - Byte 3 selected
mbed_official	324:406fd2029f23	421	*/
mbed_official	324:406fd2029f23	422	/@{/
mbed_official	324:406fd2029f23	423	#define BP_WDOG_STCTRLH_BYTESEL (12U) /!< Bit position for WDOG_STCTRLH_BYTESEL. /
mbed_official	324:406fd2029f23	424	#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) /!< Bit mask for WDOG_STCTRLH_BYTESEL. /
mbed_official	324:406fd2029f23	425	#define BS_WDOG_STCTRLH_BYTESEL (2U) /!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. /
mbed_official	324:406fd2029f23	426
mbed_official	324:406fd2029f23	427	/! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. /
mbed_official	324:406fd2029f23	428	#define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL)
mbed_official	324:406fd2029f23	429
mbed_official	324:406fd2029f23	430	/! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. /
mbed_official	324:406fd2029f23	431	#define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL)
mbed_official	324:406fd2029f23	432
mbed_official	324:406fd2029f23	433	/! @brief Set the BYTESEL field to a new value. /
mbed_official	324:406fd2029f23	434	#define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) \| BF_WDOG_STCTRLH_BYTESEL(v)))
mbed_official	324:406fd2029f23	435	/@}/
mbed_official	324:406fd2029f23	436
mbed_official	324:406fd2029f23	437	/*!
mbed_official	324:406fd2029f23	438	* @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
mbed_official	324:406fd2029f23	439	*
mbed_official	324:406fd2029f23	440	* Allows the WDOG's functional test mode to be disabled permanently. After it
mbed_official	324:406fd2029f23	441	* is set, it can only be cleared by a reset. It cannot be unlocked for editing
mbed_official	324:406fd2029f23	442	* after it is set.
mbed_official	324:406fd2029f23	443	*
mbed_official	324:406fd2029f23	444	* Values:
mbed_official	324:406fd2029f23	445	* - 0 - WDOG functional test mode is not disabled.
mbed_official	324:406fd2029f23	446	* - 1 - WDOG functional test mode is disabled permanently until reset.
mbed_official	324:406fd2029f23	447	*/
mbed_official	324:406fd2029f23	448	/@{/
mbed_official	324:406fd2029f23	449	#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) /!< Bit position for WDOG_STCTRLH_DISTESTWDOG. /
mbed_official	324:406fd2029f23	450	#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. /
mbed_official	324:406fd2029f23	451	#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) /!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. /
mbed_official	324:406fd2029f23	452
mbed_official	324:406fd2029f23	453	/! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. /
mbed_official	324:406fd2029f23	454	#define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG))
mbed_official	324:406fd2029f23	455
mbed_official	324:406fd2029f23	456	/! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. /
mbed_official	324:406fd2029f23	457	#define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG)
mbed_official	324:406fd2029f23	458
mbed_official	324:406fd2029f23	459	/! @brief Set the DISTESTWDOG field to a new value. /
mbed_official	324:406fd2029f23	460	#define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
mbed_official	324:406fd2029f23	461	/@}/
mbed_official	324:406fd2029f23	462
mbed_official	324:406fd2029f23	463	/*******************************************************************************
mbed_official	324:406fd2029f23	464	* HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
mbed_official	324:406fd2029f23	465	******************************************************************************/
mbed_official	324:406fd2029f23	466
mbed_official	324:406fd2029f23	467	/*!
mbed_official	324:406fd2029f23	468	* @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
mbed_official	324:406fd2029f23	469	*
mbed_official	324:406fd2029f23	470	* Reset value: 0x0001U
mbed_official	324:406fd2029f23	471	*/
mbed_official	324:406fd2029f23	472	typedef union _hw_wdog_stctrll
mbed_official	324:406fd2029f23	473	{
mbed_official	324:406fd2029f23	474	uint16_t U;
mbed_official	324:406fd2029f23	475	struct _hw_wdog_stctrll_bitfields
mbed_official	324:406fd2029f23	476	{
mbed_official	324:406fd2029f23	477	uint16_t RESERVED0 : 15; /!< [14:0] /
mbed_official	324:406fd2029f23	478	uint16_t INTFLG : 1; /!< [15] /
mbed_official	324:406fd2029f23	479	} B;
mbed_official	324:406fd2029f23	480	} hw_wdog_stctrll_t;
mbed_official	324:406fd2029f23	481
mbed_official	324:406fd2029f23	482	/*!
mbed_official	324:406fd2029f23	483	* @name Constants and macros for entire WDOG_STCTRLL register
mbed_official	324:406fd2029f23	484	*/
mbed_official	324:406fd2029f23	485	/@{/
mbed_official	324:406fd2029f23	486	#define HW_WDOG_STCTRLL_ADDR(x) ((x) + 0x2U)
mbed_official	324:406fd2029f23	487
mbed_official	324:406fd2029f23	488	#define HW_WDOG_STCTRLL(x) ((__IO hw_wdog_stctrll_t ) HW_WDOG_STCTRLL_ADDR(x))
mbed_official	324:406fd2029f23	489	#define HW_WDOG_STCTRLL_RD(x) (HW_WDOG_STCTRLL(x).U)
mbed_official	324:406fd2029f23	490	#define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v))
mbed_official	324:406fd2029f23	491	#define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	492	#define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	493	#define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	494	/@}/
mbed_official	324:406fd2029f23	495
mbed_official	324:406fd2029f23	496	/*
mbed_official	324:406fd2029f23	497	* Constants & macros for individual WDOG_STCTRLL bitfields
mbed_official	324:406fd2029f23	498	*/
mbed_official	324:406fd2029f23	499
mbed_official	324:406fd2029f23	500	/*!
mbed_official	324:406fd2029f23	501	* @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
mbed_official	324:406fd2029f23	502	*
mbed_official	324:406fd2029f23	503	* Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
mbed_official	324:406fd2029f23	504	* precondition to set this flag. INTFLG = 1 results in an interrupt being issued
mbed_official	324:406fd2029f23	505	* followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
mbed_official	324:406fd2029f23	506	* bit. It also gets cleared on a system reset.
mbed_official	324:406fd2029f23	507	*/
mbed_official	324:406fd2029f23	508	/@{/
mbed_official	324:406fd2029f23	509	#define BP_WDOG_STCTRLL_INTFLG (15U) /!< Bit position for WDOG_STCTRLL_INTFLG. /
mbed_official	324:406fd2029f23	510	#define BM_WDOG_STCTRLL_INTFLG (0x8000U) /!< Bit mask for WDOG_STCTRLL_INTFLG. /
mbed_official	324:406fd2029f23	511	#define BS_WDOG_STCTRLL_INTFLG (1U) /!< Bit field size in bits for WDOG_STCTRLL_INTFLG. /
mbed_official	324:406fd2029f23	512
mbed_official	324:406fd2029f23	513	/! @brief Read current value of the WDOG_STCTRLL_INTFLG field. /
mbed_official	324:406fd2029f23	514	#define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG))
mbed_official	324:406fd2029f23	515
mbed_official	324:406fd2029f23	516	/! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. /
mbed_official	324:406fd2029f23	517	#define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG)
mbed_official	324:406fd2029f23	518
mbed_official	324:406fd2029f23	519	/! @brief Set the INTFLG field to a new value. /
mbed_official	324:406fd2029f23	520	#define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v))
mbed_official	324:406fd2029f23	521	/@}/
mbed_official	324:406fd2029f23	522
mbed_official	324:406fd2029f23	523	/*******************************************************************************
mbed_official	324:406fd2029f23	524	* HW_WDOG_TOVALH - Watchdog Time-out Value Register High
mbed_official	324:406fd2029f23	525	******************************************************************************/
mbed_official	324:406fd2029f23	526
mbed_official	324:406fd2029f23	527	/*!
mbed_official	324:406fd2029f23	528	* @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
mbed_official	324:406fd2029f23	529	*
mbed_official	324:406fd2029f23	530	* Reset value: 0x004CU
mbed_official	324:406fd2029f23	531	*/
mbed_official	324:406fd2029f23	532	typedef union _hw_wdog_tovalh
mbed_official	324:406fd2029f23	533	{
mbed_official	324:406fd2029f23	534	uint16_t U;
mbed_official	324:406fd2029f23	535	struct _hw_wdog_tovalh_bitfields
mbed_official	324:406fd2029f23	536	{
mbed_official	324:406fd2029f23	537	uint16_t TOVALHIGH : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	538	} B;
mbed_official	324:406fd2029f23	539	} hw_wdog_tovalh_t;
mbed_official	324:406fd2029f23	540
mbed_official	324:406fd2029f23	541	/*!
mbed_official	324:406fd2029f23	542	* @name Constants and macros for entire WDOG_TOVALH register
mbed_official	324:406fd2029f23	543	*/
mbed_official	324:406fd2029f23	544	/@{/
mbed_official	324:406fd2029f23	545	#define HW_WDOG_TOVALH_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	546
mbed_official	324:406fd2029f23	547	#define HW_WDOG_TOVALH(x) ((__IO hw_wdog_tovalh_t ) HW_WDOG_TOVALH_ADDR(x))
mbed_official	324:406fd2029f23	548	#define HW_WDOG_TOVALH_RD(x) (HW_WDOG_TOVALH(x).U)
mbed_official	324:406fd2029f23	549	#define HW_WDOG_TOVALH_WR(x, v) (HW_WDOG_TOVALH(x).U = (v))
mbed_official	324:406fd2029f23	550	#define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	551	#define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	552	#define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	553	/@}/
mbed_official	324:406fd2029f23	554
mbed_official	324:406fd2029f23	555	/*
mbed_official	324:406fd2029f23	556	* Constants & macros for individual WDOG_TOVALH bitfields
mbed_official	324:406fd2029f23	557	*/
mbed_official	324:406fd2029f23	558
mbed_official	324:406fd2029f23	559	/*!
mbed_official	324:406fd2029f23	560	* @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
mbed_official	324:406fd2029f23	561	*
mbed_official	324:406fd2029f23	562	* Defines the upper 16 bits of the 32-bit time-out value for the watchdog
mbed_official	324:406fd2029f23	563	* timer. It is defined in terms of cycles of the watchdog clock.
mbed_official	324:406fd2029f23	564	*/
mbed_official	324:406fd2029f23	565	/@{/
mbed_official	324:406fd2029f23	566	#define BP_WDOG_TOVALH_TOVALHIGH (0U) /!< Bit position for WDOG_TOVALH_TOVALHIGH. /
mbed_official	324:406fd2029f23	567	#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /!< Bit mask for WDOG_TOVALH_TOVALHIGH. /
mbed_official	324:406fd2029f23	568	#define BS_WDOG_TOVALH_TOVALHIGH (16U) /!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. /
mbed_official	324:406fd2029f23	569
mbed_official	324:406fd2029f23	570	/! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. /
mbed_official	324:406fd2029f23	571	#define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U)
mbed_official	324:406fd2029f23	572
mbed_official	324:406fd2029f23	573	/! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. /
mbed_official	324:406fd2029f23	574	#define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH)
mbed_official	324:406fd2029f23	575
mbed_official	324:406fd2029f23	576	/! @brief Set the TOVALHIGH field to a new value. /
mbed_official	324:406fd2029f23	577	#define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v))
mbed_official	324:406fd2029f23	578	/@}/
mbed_official	324:406fd2029f23	579
mbed_official	324:406fd2029f23	580	/*******************************************************************************
mbed_official	324:406fd2029f23	581	* HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
mbed_official	324:406fd2029f23	582	******************************************************************************/
mbed_official	324:406fd2029f23	583
mbed_official	324:406fd2029f23	584	/*!
mbed_official	324:406fd2029f23	585	* @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
mbed_official	324:406fd2029f23	586	*
mbed_official	324:406fd2029f23	587	* Reset value: 0x4B4CU
mbed_official	324:406fd2029f23	588	*
mbed_official	324:406fd2029f23	589	* The time-out value of the watchdog must be set to a minimum of four watchdog
mbed_official	324:406fd2029f23	590	* clock cycles. This is to take into account the delay in new settings taking
mbed_official	324:406fd2029f23	591	* effect in the watchdog clock domain.
mbed_official	324:406fd2029f23	592	*/
mbed_official	324:406fd2029f23	593	typedef union _hw_wdog_tovall
mbed_official	324:406fd2029f23	594	{
mbed_official	324:406fd2029f23	595	uint16_t U;
mbed_official	324:406fd2029f23	596	struct _hw_wdog_tovall_bitfields
mbed_official	324:406fd2029f23	597	{
mbed_official	324:406fd2029f23	598	uint16_t TOVALLOW : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	599	} B;
mbed_official	324:406fd2029f23	600	} hw_wdog_tovall_t;
mbed_official	324:406fd2029f23	601
mbed_official	324:406fd2029f23	602	/*!
mbed_official	324:406fd2029f23	603	* @name Constants and macros for entire WDOG_TOVALL register
mbed_official	324:406fd2029f23	604	*/
mbed_official	324:406fd2029f23	605	/@{/
mbed_official	324:406fd2029f23	606	#define HW_WDOG_TOVALL_ADDR(x) ((x) + 0x6U)
mbed_official	324:406fd2029f23	607
mbed_official	324:406fd2029f23	608	#define HW_WDOG_TOVALL(x) ((__IO hw_wdog_tovall_t ) HW_WDOG_TOVALL_ADDR(x))
mbed_official	324:406fd2029f23	609	#define HW_WDOG_TOVALL_RD(x) (HW_WDOG_TOVALL(x).U)
mbed_official	324:406fd2029f23	610	#define HW_WDOG_TOVALL_WR(x, v) (HW_WDOG_TOVALL(x).U = (v))
mbed_official	324:406fd2029f23	611	#define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	612	#define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	613	#define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	614	/@}/
mbed_official	324:406fd2029f23	615
mbed_official	324:406fd2029f23	616	/*
mbed_official	324:406fd2029f23	617	* Constants & macros for individual WDOG_TOVALL bitfields
mbed_official	324:406fd2029f23	618	*/
mbed_official	324:406fd2029f23	619
mbed_official	324:406fd2029f23	620	/*!
mbed_official	324:406fd2029f23	621	* @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
mbed_official	324:406fd2029f23	622	*
mbed_official	324:406fd2029f23	623	* Defines the lower 16 bits of the 32-bit time-out value for the watchdog
mbed_official	324:406fd2029f23	624	* timer. It is defined in terms of cycles of the watchdog clock.
mbed_official	324:406fd2029f23	625	*/
mbed_official	324:406fd2029f23	626	/@{/
mbed_official	324:406fd2029f23	627	#define BP_WDOG_TOVALL_TOVALLOW (0U) /!< Bit position for WDOG_TOVALL_TOVALLOW. /
mbed_official	324:406fd2029f23	628	#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) /!< Bit mask for WDOG_TOVALL_TOVALLOW. /
mbed_official	324:406fd2029f23	629	#define BS_WDOG_TOVALL_TOVALLOW (16U) /!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. /
mbed_official	324:406fd2029f23	630
mbed_official	324:406fd2029f23	631	/! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. /
mbed_official	324:406fd2029f23	632	#define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U)
mbed_official	324:406fd2029f23	633
mbed_official	324:406fd2029f23	634	/! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. /
mbed_official	324:406fd2029f23	635	#define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW)
mbed_official	324:406fd2029f23	636
mbed_official	324:406fd2029f23	637	/! @brief Set the TOVALLOW field to a new value. /
mbed_official	324:406fd2029f23	638	#define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v))
mbed_official	324:406fd2029f23	639	/@}/
mbed_official	324:406fd2029f23	640
mbed_official	324:406fd2029f23	641	/*******************************************************************************
mbed_official	324:406fd2029f23	642	* HW_WDOG_WINH - Watchdog Window Register High
mbed_official	324:406fd2029f23	643	******************************************************************************/
mbed_official	324:406fd2029f23	644
mbed_official	324:406fd2029f23	645	/*!
mbed_official	324:406fd2029f23	646	* @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
mbed_official	324:406fd2029f23	647	*
mbed_official	324:406fd2029f23	648	* Reset value: 0x0000U
mbed_official	324:406fd2029f23	649	*
mbed_official	324:406fd2029f23	650	* You must set the Window Register value lower than the Time-out Value Register.
mbed_official	324:406fd2029f23	651	*/
mbed_official	324:406fd2029f23	652	typedef union _hw_wdog_winh
mbed_official	324:406fd2029f23	653	{
mbed_official	324:406fd2029f23	654	uint16_t U;
mbed_official	324:406fd2029f23	655	struct _hw_wdog_winh_bitfields
mbed_official	324:406fd2029f23	656	{
mbed_official	324:406fd2029f23	657	uint16_t WINHIGH : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	658	} B;
mbed_official	324:406fd2029f23	659	} hw_wdog_winh_t;
mbed_official	324:406fd2029f23	660
mbed_official	324:406fd2029f23	661	/*!
mbed_official	324:406fd2029f23	662	* @name Constants and macros for entire WDOG_WINH register
mbed_official	324:406fd2029f23	663	*/
mbed_official	324:406fd2029f23	664	/@{/
mbed_official	324:406fd2029f23	665	#define HW_WDOG_WINH_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	666
mbed_official	324:406fd2029f23	667	#define HW_WDOG_WINH(x) ((__IO hw_wdog_winh_t ) HW_WDOG_WINH_ADDR(x))
mbed_official	324:406fd2029f23	668	#define HW_WDOG_WINH_RD(x) (HW_WDOG_WINH(x).U)
mbed_official	324:406fd2029f23	669	#define HW_WDOG_WINH_WR(x, v) (HW_WDOG_WINH(x).U = (v))
mbed_official	324:406fd2029f23	670	#define HW_WDOG_WINH_SET(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	671	#define HW_WDOG_WINH_CLR(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	672	#define HW_WDOG_WINH_TOG(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	673	/@}/
mbed_official	324:406fd2029f23	674
mbed_official	324:406fd2029f23	675	/*
mbed_official	324:406fd2029f23	676	* Constants & macros for individual WDOG_WINH bitfields
mbed_official	324:406fd2029f23	677	*/
mbed_official	324:406fd2029f23	678
mbed_official	324:406fd2029f23	679	/*!
mbed_official	324:406fd2029f23	680	* @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
mbed_official	324:406fd2029f23	681	*
mbed_official	324:406fd2029f23	682	* Defines the upper 16 bits of the 32-bit window for the windowed mode of
mbed_official	324:406fd2029f23	683	* operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
mbed_official	324:406fd2029f23	684	* In this mode, the watchdog can be refreshed only when the timer has reached a
mbed_official	324:406fd2029f23	685	* value greater than or equal to this window length. A refresh outside this
mbed_official	324:406fd2029f23	686	* window resets the system or if IRQRSTEN is set, it interrupts and then resets the
mbed_official	324:406fd2029f23	687	* system.
mbed_official	324:406fd2029f23	688	*/
mbed_official	324:406fd2029f23	689	/@{/
mbed_official	324:406fd2029f23	690	#define BP_WDOG_WINH_WINHIGH (0U) /!< Bit position for WDOG_WINH_WINHIGH. /
mbed_official	324:406fd2029f23	691	#define BM_WDOG_WINH_WINHIGH (0xFFFFU) /!< Bit mask for WDOG_WINH_WINHIGH. /
mbed_official	324:406fd2029f23	692	#define BS_WDOG_WINH_WINHIGH (16U) /!< Bit field size in bits for WDOG_WINH_WINHIGH. /
mbed_official	324:406fd2029f23	693
mbed_official	324:406fd2029f23	694	/! @brief Read current value of the WDOG_WINH_WINHIGH field. /
mbed_official	324:406fd2029f23	695	#define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U)
mbed_official	324:406fd2029f23	696
mbed_official	324:406fd2029f23	697	/! @brief Format value for bitfield WDOG_WINH_WINHIGH. /
mbed_official	324:406fd2029f23	698	#define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH)
mbed_official	324:406fd2029f23	699
mbed_official	324:406fd2029f23	700	/! @brief Set the WINHIGH field to a new value. /
mbed_official	324:406fd2029f23	701	#define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v))
mbed_official	324:406fd2029f23	702	/@}/
mbed_official	324:406fd2029f23	703
mbed_official	324:406fd2029f23	704	/*******************************************************************************
mbed_official	324:406fd2029f23	705	* HW_WDOG_WINL - Watchdog Window Register Low
mbed_official	324:406fd2029f23	706	******************************************************************************/
mbed_official	324:406fd2029f23	707
mbed_official	324:406fd2029f23	708	/*!
mbed_official	324:406fd2029f23	709	* @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
mbed_official	324:406fd2029f23	710	*
mbed_official	324:406fd2029f23	711	* Reset value: 0x0010U
mbed_official	324:406fd2029f23	712	*
mbed_official	324:406fd2029f23	713	* You must set the Window Register value lower than the Time-out Value Register.
mbed_official	324:406fd2029f23	714	*/
mbed_official	324:406fd2029f23	715	typedef union _hw_wdog_winl
mbed_official	324:406fd2029f23	716	{
mbed_official	324:406fd2029f23	717	uint16_t U;
mbed_official	324:406fd2029f23	718	struct _hw_wdog_winl_bitfields
mbed_official	324:406fd2029f23	719	{
mbed_official	324:406fd2029f23	720	uint16_t WINLOW : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	721	} B;
mbed_official	324:406fd2029f23	722	} hw_wdog_winl_t;
mbed_official	324:406fd2029f23	723
mbed_official	324:406fd2029f23	724	/*!
mbed_official	324:406fd2029f23	725	* @name Constants and macros for entire WDOG_WINL register
mbed_official	324:406fd2029f23	726	*/
mbed_official	324:406fd2029f23	727	/@{/
mbed_official	324:406fd2029f23	728	#define HW_WDOG_WINL_ADDR(x) ((x) + 0xAU)
mbed_official	324:406fd2029f23	729
mbed_official	324:406fd2029f23	730	#define HW_WDOG_WINL(x) ((__IO hw_wdog_winl_t ) HW_WDOG_WINL_ADDR(x))
mbed_official	324:406fd2029f23	731	#define HW_WDOG_WINL_RD(x) (HW_WDOG_WINL(x).U)
mbed_official	324:406fd2029f23	732	#define HW_WDOG_WINL_WR(x, v) (HW_WDOG_WINL(x).U = (v))
mbed_official	324:406fd2029f23	733	#define HW_WDOG_WINL_SET(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	734	#define HW_WDOG_WINL_CLR(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	735	#define HW_WDOG_WINL_TOG(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	736	/@}/
mbed_official	324:406fd2029f23	737
mbed_official	324:406fd2029f23	738	/*
mbed_official	324:406fd2029f23	739	* Constants & macros for individual WDOG_WINL bitfields
mbed_official	324:406fd2029f23	740	*/
mbed_official	324:406fd2029f23	741
mbed_official	324:406fd2029f23	742	/*!
mbed_official	324:406fd2029f23	743	* @name Register WDOG_WINL, field WINLOW[15:0] (RW)
mbed_official	324:406fd2029f23	744	*
mbed_official	324:406fd2029f23	745	* Defines the lower 16 bits of the 32-bit window for the windowed mode of
mbed_official	324:406fd2029f23	746	* operation of the watchdog. It is defined in terms of cycles of the pre-scaled
mbed_official	324:406fd2029f23	747	* watchdog clock. In this mode, the watchdog can be refreshed only when the timer
mbed_official	324:406fd2029f23	748	* reaches a value greater than or equal to this window length value. A refresh
mbed_official	324:406fd2029f23	749	* outside of this window resets the system or if IRQRSTEN is set, it interrupts and
mbed_official	324:406fd2029f23	750	* then resets the system.
mbed_official	324:406fd2029f23	751	*/
mbed_official	324:406fd2029f23	752	/@{/
mbed_official	324:406fd2029f23	753	#define BP_WDOG_WINL_WINLOW (0U) /!< Bit position for WDOG_WINL_WINLOW. /
mbed_official	324:406fd2029f23	754	#define BM_WDOG_WINL_WINLOW (0xFFFFU) /!< Bit mask for WDOG_WINL_WINLOW. /
mbed_official	324:406fd2029f23	755	#define BS_WDOG_WINL_WINLOW (16U) /!< Bit field size in bits for WDOG_WINL_WINLOW. /
mbed_official	324:406fd2029f23	756
mbed_official	324:406fd2029f23	757	/! @brief Read current value of the WDOG_WINL_WINLOW field. /
mbed_official	324:406fd2029f23	758	#define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U)
mbed_official	324:406fd2029f23	759
mbed_official	324:406fd2029f23	760	/! @brief Format value for bitfield WDOG_WINL_WINLOW. /
mbed_official	324:406fd2029f23	761	#define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW)
mbed_official	324:406fd2029f23	762
mbed_official	324:406fd2029f23	763	/! @brief Set the WINLOW field to a new value. /
mbed_official	324:406fd2029f23	764	#define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v))
mbed_official	324:406fd2029f23	765	/@}/
mbed_official	324:406fd2029f23	766
mbed_official	324:406fd2029f23	767	/*******************************************************************************
mbed_official	324:406fd2029f23	768	* HW_WDOG_REFRESH - Watchdog Refresh register
mbed_official	324:406fd2029f23	769	******************************************************************************/
mbed_official	324:406fd2029f23	770
mbed_official	324:406fd2029f23	771	/*!
mbed_official	324:406fd2029f23	772	* @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
mbed_official	324:406fd2029f23	773	*
mbed_official	324:406fd2029f23	774	* Reset value: 0xB480U
mbed_official	324:406fd2029f23	775	*/
mbed_official	324:406fd2029f23	776	typedef union _hw_wdog_refresh
mbed_official	324:406fd2029f23	777	{
mbed_official	324:406fd2029f23	778	uint16_t U;
mbed_official	324:406fd2029f23	779	struct _hw_wdog_refresh_bitfields
mbed_official	324:406fd2029f23	780	{
mbed_official	324:406fd2029f23	781	uint16_t WDOGREFRESH : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	782	} B;
mbed_official	324:406fd2029f23	783	} hw_wdog_refresh_t;
mbed_official	324:406fd2029f23	784
mbed_official	324:406fd2029f23	785	/*!
mbed_official	324:406fd2029f23	786	* @name Constants and macros for entire WDOG_REFRESH register
mbed_official	324:406fd2029f23	787	*/
mbed_official	324:406fd2029f23	788	/@{/
mbed_official	324:406fd2029f23	789	#define HW_WDOG_REFRESH_ADDR(x) ((x) + 0xCU)
mbed_official	324:406fd2029f23	790
mbed_official	324:406fd2029f23	791	#define HW_WDOG_REFRESH(x) ((__IO hw_wdog_refresh_t ) HW_WDOG_REFRESH_ADDR(x))
mbed_official	324:406fd2029f23	792	#define HW_WDOG_REFRESH_RD(x) (HW_WDOG_REFRESH(x).U)
mbed_official	324:406fd2029f23	793	#define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v))
mbed_official	324:406fd2029f23	794	#define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	795	#define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	796	#define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	797	/@}/
mbed_official	324:406fd2029f23	798
mbed_official	324:406fd2029f23	799	/*
mbed_official	324:406fd2029f23	800	* Constants & macros for individual WDOG_REFRESH bitfields
mbed_official	324:406fd2029f23	801	*/
mbed_official	324:406fd2029f23	802
mbed_official	324:406fd2029f23	803	/*!
mbed_official	324:406fd2029f23	804	* @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
mbed_official	324:406fd2029f23	805	*
mbed_official	324:406fd2029f23	806	* Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
mbed_official	324:406fd2029f23	807	* bus clock cycles written to this register refreshes the WDOG and prevents it
mbed_official	324:406fd2029f23	808	* from resetting the system. Writing a value other than the above mentioned
mbed_official	324:406fd2029f23	809	* sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
mbed_official	324:406fd2029f23	810	* IRQRSTEN is set, it interrupts and then resets the system.
mbed_official	324:406fd2029f23	811	*/
mbed_official	324:406fd2029f23	812	/@{/
mbed_official	324:406fd2029f23	813	#define BP_WDOG_REFRESH_WDOGREFRESH (0U) /!< Bit position for WDOG_REFRESH_WDOGREFRESH. /
mbed_official	324:406fd2029f23	814	#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /!< Bit mask for WDOG_REFRESH_WDOGREFRESH. /
mbed_official	324:406fd2029f23	815	#define BS_WDOG_REFRESH_WDOGREFRESH (16U) /!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. /
mbed_official	324:406fd2029f23	816
mbed_official	324:406fd2029f23	817	/! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. /
mbed_official	324:406fd2029f23	818	#define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U)
mbed_official	324:406fd2029f23	819
mbed_official	324:406fd2029f23	820	/! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. /
mbed_official	324:406fd2029f23	821	#define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH)
mbed_official	324:406fd2029f23	822
mbed_official	324:406fd2029f23	823	/! @brief Set the WDOGREFRESH field to a new value. /
mbed_official	324:406fd2029f23	824	#define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v))
mbed_official	324:406fd2029f23	825	/@}/
mbed_official	324:406fd2029f23	826
mbed_official	324:406fd2029f23	827	/*******************************************************************************
mbed_official	324:406fd2029f23	828	* HW_WDOG_UNLOCK - Watchdog Unlock register
mbed_official	324:406fd2029f23	829	******************************************************************************/
mbed_official	324:406fd2029f23	830
mbed_official	324:406fd2029f23	831	/*!
mbed_official	324:406fd2029f23	832	* @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
mbed_official	324:406fd2029f23	833	*
mbed_official	324:406fd2029f23	834	* Reset value: 0xD928U
mbed_official	324:406fd2029f23	835	*/
mbed_official	324:406fd2029f23	836	typedef union _hw_wdog_unlock
mbed_official	324:406fd2029f23	837	{
mbed_official	324:406fd2029f23	838	uint16_t U;
mbed_official	324:406fd2029f23	839	struct _hw_wdog_unlock_bitfields
mbed_official	324:406fd2029f23	840	{
mbed_official	324:406fd2029f23	841	uint16_t WDOGUNLOCK : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	842	} B;
mbed_official	324:406fd2029f23	843	} hw_wdog_unlock_t;
mbed_official	324:406fd2029f23	844
mbed_official	324:406fd2029f23	845	/*!
mbed_official	324:406fd2029f23	846	* @name Constants and macros for entire WDOG_UNLOCK register
mbed_official	324:406fd2029f23	847	*/
mbed_official	324:406fd2029f23	848	/@{/
mbed_official	324:406fd2029f23	849	#define HW_WDOG_UNLOCK_ADDR(x) ((x) + 0xEU)
mbed_official	324:406fd2029f23	850
mbed_official	324:406fd2029f23	851	#define HW_WDOG_UNLOCK(x) ((__IO hw_wdog_unlock_t ) HW_WDOG_UNLOCK_ADDR(x))
mbed_official	324:406fd2029f23	852	#define HW_WDOG_UNLOCK_RD(x) (HW_WDOG_UNLOCK(x).U)
mbed_official	324:406fd2029f23	853	#define HW_WDOG_UNLOCK_WR(x, v) (HW_WDOG_UNLOCK(x).U = (v))
mbed_official	324:406fd2029f23	854	#define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	855	#define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	856	#define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	857	/@}/
mbed_official	324:406fd2029f23	858
mbed_official	324:406fd2029f23	859	/*
mbed_official	324:406fd2029f23	860	* Constants & macros for individual WDOG_UNLOCK bitfields
mbed_official	324:406fd2029f23	861	*/
mbed_official	324:406fd2029f23	862
mbed_official	324:406fd2029f23	863	/*!
mbed_official	324:406fd2029f23	864	* @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
mbed_official	324:406fd2029f23	865	*
mbed_official	324:406fd2029f23	866	* Writing the unlock sequence values to this register to makes the watchdog
mbed_official	324:406fd2029f23	867	* write-once registers writable again. The required unlock sequence is 0xC520
mbed_official	324:406fd2029f23	868	* followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
mbed_official	324:406fd2029f23	869	* window equal in length to the WCT within which you can update the registers.
mbed_official	324:406fd2029f23	870	* Writing a value other than the above mentioned sequence or if the sequence is
mbed_official	324:406fd2029f23	871	* longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
mbed_official	324:406fd2029f23	872	* and then resets the system. The unlock sequence is effective only if
mbed_official	324:406fd2029f23	873	* ALLOWUPDATE is set.
mbed_official	324:406fd2029f23	874	*/
mbed_official	324:406fd2029f23	875	/@{/
mbed_official	324:406fd2029f23	876	#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) /!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. /
mbed_official	324:406fd2029f23	877	#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. /
mbed_official	324:406fd2029f23	878	#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) /!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. /
mbed_official	324:406fd2029f23	879
mbed_official	324:406fd2029f23	880	/! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. /
mbed_official	324:406fd2029f23	881	#define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U)
mbed_official	324:406fd2029f23	882
mbed_official	324:406fd2029f23	883	/! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. /
mbed_official	324:406fd2029f23	884	#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK)
mbed_official	324:406fd2029f23	885
mbed_official	324:406fd2029f23	886	/! @brief Set the WDOGUNLOCK field to a new value. /
mbed_official	324:406fd2029f23	887	#define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v))
mbed_official	324:406fd2029f23	888	/@}/
mbed_official	324:406fd2029f23	889
mbed_official	324:406fd2029f23	890	/*******************************************************************************
mbed_official	324:406fd2029f23	891	* HW_WDOG_TMROUTH - Watchdog Timer Output Register High
mbed_official	324:406fd2029f23	892	******************************************************************************/
mbed_official	324:406fd2029f23	893
mbed_official	324:406fd2029f23	894	/*!
mbed_official	324:406fd2029f23	895	* @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
mbed_official	324:406fd2029f23	896	*
mbed_official	324:406fd2029f23	897	* Reset value: 0x0000U
mbed_official	324:406fd2029f23	898	*/
mbed_official	324:406fd2029f23	899	typedef union _hw_wdog_tmrouth
mbed_official	324:406fd2029f23	900	{
mbed_official	324:406fd2029f23	901	uint16_t U;
mbed_official	324:406fd2029f23	902	struct _hw_wdog_tmrouth_bitfields
mbed_official	324:406fd2029f23	903	{
mbed_official	324:406fd2029f23	904	uint16_t TIMEROUTHIGH : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	905	} B;
mbed_official	324:406fd2029f23	906	} hw_wdog_tmrouth_t;
mbed_official	324:406fd2029f23	907
mbed_official	324:406fd2029f23	908	/*!
mbed_official	324:406fd2029f23	909	* @name Constants and macros for entire WDOG_TMROUTH register
mbed_official	324:406fd2029f23	910	*/
mbed_official	324:406fd2029f23	911	/@{/
mbed_official	324:406fd2029f23	912	#define HW_WDOG_TMROUTH_ADDR(x) ((x) + 0x10U)
mbed_official	324:406fd2029f23	913
mbed_official	324:406fd2029f23	914	#define HW_WDOG_TMROUTH(x) ((__IO hw_wdog_tmrouth_t ) HW_WDOG_TMROUTH_ADDR(x))
mbed_official	324:406fd2029f23	915	#define HW_WDOG_TMROUTH_RD(x) (HW_WDOG_TMROUTH(x).U)
mbed_official	324:406fd2029f23	916	#define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v))
mbed_official	324:406fd2029f23	917	#define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	918	#define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	919	#define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	920	/@}/
mbed_official	324:406fd2029f23	921
mbed_official	324:406fd2029f23	922	/*
mbed_official	324:406fd2029f23	923	* Constants & macros for individual WDOG_TMROUTH bitfields
mbed_official	324:406fd2029f23	924	*/
mbed_official	324:406fd2029f23	925
mbed_official	324:406fd2029f23	926	/*!
mbed_official	324:406fd2029f23	927	* @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
mbed_official	324:406fd2029f23	928	*
mbed_official	324:406fd2029f23	929	* Shows the value of the upper 16 bits of the watchdog timer.
mbed_official	324:406fd2029f23	930	*/
mbed_official	324:406fd2029f23	931	/@{/
mbed_official	324:406fd2029f23	932	#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) /!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. /
mbed_official	324:406fd2029f23	933	#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. /
mbed_official	324:406fd2029f23	934	#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. /
mbed_official	324:406fd2029f23	935
mbed_official	324:406fd2029f23	936	/! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. /
mbed_official	324:406fd2029f23	937	#define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U)
mbed_official	324:406fd2029f23	938
mbed_official	324:406fd2029f23	939	/! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. /
mbed_official	324:406fd2029f23	940	#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
mbed_official	324:406fd2029f23	941
mbed_official	324:406fd2029f23	942	/! @brief Set the TIMEROUTHIGH field to a new value. /
mbed_official	324:406fd2029f23	943	#define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v))
mbed_official	324:406fd2029f23	944	/@}/
mbed_official	324:406fd2029f23	945
mbed_official	324:406fd2029f23	946	/*******************************************************************************
mbed_official	324:406fd2029f23	947	* HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
mbed_official	324:406fd2029f23	948	******************************************************************************/
mbed_official	324:406fd2029f23	949
mbed_official	324:406fd2029f23	950	/*!
mbed_official	324:406fd2029f23	951	* @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
mbed_official	324:406fd2029f23	952	*
mbed_official	324:406fd2029f23	953	* Reset value: 0x0000U
mbed_official	324:406fd2029f23	954	*
mbed_official	324:406fd2029f23	955	* During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
mbed_official	324:406fd2029f23	956	* the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
mbed_official	324:406fd2029f23	957	* cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
mbed_official	324:406fd2029f23	958	* the watchdog timer.
mbed_official	324:406fd2029f23	959	*/
mbed_official	324:406fd2029f23	960	typedef union _hw_wdog_tmroutl
mbed_official	324:406fd2029f23	961	{
mbed_official	324:406fd2029f23	962	uint16_t U;
mbed_official	324:406fd2029f23	963	struct _hw_wdog_tmroutl_bitfields
mbed_official	324:406fd2029f23	964	{
mbed_official	324:406fd2029f23	965	uint16_t TIMEROUTLOW : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	966	} B;
mbed_official	324:406fd2029f23	967	} hw_wdog_tmroutl_t;
mbed_official	324:406fd2029f23	968
mbed_official	324:406fd2029f23	969	/*!
mbed_official	324:406fd2029f23	970	* @name Constants and macros for entire WDOG_TMROUTL register
mbed_official	324:406fd2029f23	971	*/
mbed_official	324:406fd2029f23	972	/@{/
mbed_official	324:406fd2029f23	973	#define HW_WDOG_TMROUTL_ADDR(x) ((x) + 0x12U)
mbed_official	324:406fd2029f23	974
mbed_official	324:406fd2029f23	975	#define HW_WDOG_TMROUTL(x) ((__IO hw_wdog_tmroutl_t ) HW_WDOG_TMROUTL_ADDR(x))
mbed_official	324:406fd2029f23	976	#define HW_WDOG_TMROUTL_RD(x) (HW_WDOG_TMROUTL(x).U)
mbed_official	324:406fd2029f23	977	#define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v))
mbed_official	324:406fd2029f23	978	#define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	979	#define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	980	#define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	981	/@}/
mbed_official	324:406fd2029f23	982
mbed_official	324:406fd2029f23	983	/*
mbed_official	324:406fd2029f23	984	* Constants & macros for individual WDOG_TMROUTL bitfields
mbed_official	324:406fd2029f23	985	*/
mbed_official	324:406fd2029f23	986
mbed_official	324:406fd2029f23	987	/*!
mbed_official	324:406fd2029f23	988	* @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
mbed_official	324:406fd2029f23	989	*
mbed_official	324:406fd2029f23	990	* Shows the value of the lower 16 bits of the watchdog timer.
mbed_official	324:406fd2029f23	991	*/
mbed_official	324:406fd2029f23	992	/@{/
mbed_official	324:406fd2029f23	993	#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) /!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. /
mbed_official	324:406fd2029f23	994	#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. /
mbed_official	324:406fd2029f23	995	#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) /!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. /
mbed_official	324:406fd2029f23	996
mbed_official	324:406fd2029f23	997	/! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. /
mbed_official	324:406fd2029f23	998	#define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U)
mbed_official	324:406fd2029f23	999
mbed_official	324:406fd2029f23	1000	/! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. /
mbed_official	324:406fd2029f23	1001	#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW)
mbed_official	324:406fd2029f23	1002
mbed_official	324:406fd2029f23	1003	/! @brief Set the TIMEROUTLOW field to a new value. /
mbed_official	324:406fd2029f23	1004	#define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v))
mbed_official	324:406fd2029f23	1005	/@}/
mbed_official	324:406fd2029f23	1006
mbed_official	324:406fd2029f23	1007	/*******************************************************************************
mbed_official	324:406fd2029f23	1008	* HW_WDOG_RSTCNT - Watchdog Reset Count register
mbed_official	324:406fd2029f23	1009	******************************************************************************/
mbed_official	324:406fd2029f23	1010
mbed_official	324:406fd2029f23	1011	/*!
mbed_official	324:406fd2029f23	1012	* @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
mbed_official	324:406fd2029f23	1013	*
mbed_official	324:406fd2029f23	1014	* Reset value: 0x0000U
mbed_official	324:406fd2029f23	1015	*/
mbed_official	324:406fd2029f23	1016	typedef union _hw_wdog_rstcnt
mbed_official	324:406fd2029f23	1017	{
mbed_official	324:406fd2029f23	1018	uint16_t U;
mbed_official	324:406fd2029f23	1019	struct _hw_wdog_rstcnt_bitfields
mbed_official	324:406fd2029f23	1020	{
mbed_official	324:406fd2029f23	1021	uint16_t RSTCNT : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	1022	} B;
mbed_official	324:406fd2029f23	1023	} hw_wdog_rstcnt_t;
mbed_official	324:406fd2029f23	1024
mbed_official	324:406fd2029f23	1025	/*!
mbed_official	324:406fd2029f23	1026	* @name Constants and macros for entire WDOG_RSTCNT register
mbed_official	324:406fd2029f23	1027	*/
mbed_official	324:406fd2029f23	1028	/@{/
mbed_official	324:406fd2029f23	1029	#define HW_WDOG_RSTCNT_ADDR(x) ((x) + 0x14U)
mbed_official	324:406fd2029f23	1030
mbed_official	324:406fd2029f23	1031	#define HW_WDOG_RSTCNT(x) ((__IO hw_wdog_rstcnt_t ) HW_WDOG_RSTCNT_ADDR(x))
mbed_official	324:406fd2029f23	1032	#define HW_WDOG_RSTCNT_RD(x) (HW_WDOG_RSTCNT(x).U)
mbed_official	324:406fd2029f23	1033	#define HW_WDOG_RSTCNT_WR(x, v) (HW_WDOG_RSTCNT(x).U = (v))
mbed_official	324:406fd2029f23	1034	#define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1035	#define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1036	#define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1037	/@}/
mbed_official	324:406fd2029f23	1038
mbed_official	324:406fd2029f23	1039	/*
mbed_official	324:406fd2029f23	1040	* Constants & macros for individual WDOG_RSTCNT bitfields
mbed_official	324:406fd2029f23	1041	*/
mbed_official	324:406fd2029f23	1042
mbed_official	324:406fd2029f23	1043	/*!
mbed_official	324:406fd2029f23	1044	* @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
mbed_official	324:406fd2029f23	1045	*
mbed_official	324:406fd2029f23	1046	* Counts the number of times the watchdog resets the system. This register is
mbed_official	324:406fd2029f23	1047	* reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
mbed_official	324:406fd2029f23	1048	* the contents of this register.
mbed_official	324:406fd2029f23	1049	*/
mbed_official	324:406fd2029f23	1050	/@{/
mbed_official	324:406fd2029f23	1051	#define BP_WDOG_RSTCNT_RSTCNT (0U) /!< Bit position for WDOG_RSTCNT_RSTCNT. /
mbed_official	324:406fd2029f23	1052	#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) /!< Bit mask for WDOG_RSTCNT_RSTCNT. /
mbed_official	324:406fd2029f23	1053	#define BS_WDOG_RSTCNT_RSTCNT (16U) /!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. /
mbed_official	324:406fd2029f23	1054
mbed_official	324:406fd2029f23	1055	/! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. /
mbed_official	324:406fd2029f23	1056	#define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U)
mbed_official	324:406fd2029f23	1057
mbed_official	324:406fd2029f23	1058	/! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. /
mbed_official	324:406fd2029f23	1059	#define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT)
mbed_official	324:406fd2029f23	1060
mbed_official	324:406fd2029f23	1061	/! @brief Set the RSTCNT field to a new value. /
mbed_official	324:406fd2029f23	1062	#define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v))
mbed_official	324:406fd2029f23	1063	/@}/
mbed_official	324:406fd2029f23	1064
mbed_official	324:406fd2029f23	1065	/*******************************************************************************
mbed_official	324:406fd2029f23	1066	* HW_WDOG_PRESC - Watchdog Prescaler register
mbed_official	324:406fd2029f23	1067	******************************************************************************/
mbed_official	324:406fd2029f23	1068
mbed_official	324:406fd2029f23	1069	/*!
mbed_official	324:406fd2029f23	1070	* @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
mbed_official	324:406fd2029f23	1071	*
mbed_official	324:406fd2029f23	1072	* Reset value: 0x0400U
mbed_official	324:406fd2029f23	1073	*/
mbed_official	324:406fd2029f23	1074	typedef union _hw_wdog_presc
mbed_official	324:406fd2029f23	1075	{
mbed_official	324:406fd2029f23	1076	uint16_t U;
mbed_official	324:406fd2029f23	1077	struct _hw_wdog_presc_bitfields
mbed_official	324:406fd2029f23	1078	{
mbed_official	324:406fd2029f23	1079	uint16_t RESERVED0 : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1080	uint16_t PRESCVAL : 3; /!< [10:8] /
mbed_official	324:406fd2029f23	1081	uint16_t RESERVED1 : 5; /!< [15:11] /
mbed_official	324:406fd2029f23	1082	} B;
mbed_official	324:406fd2029f23	1083	} hw_wdog_presc_t;
mbed_official	324:406fd2029f23	1084
mbed_official	324:406fd2029f23	1085	/*!
mbed_official	324:406fd2029f23	1086	* @name Constants and macros for entire WDOG_PRESC register
mbed_official	324:406fd2029f23	1087	*/
mbed_official	324:406fd2029f23	1088	/@{/
mbed_official	324:406fd2029f23	1089	#define HW_WDOG_PRESC_ADDR(x) ((x) + 0x16U)
mbed_official	324:406fd2029f23	1090
mbed_official	324:406fd2029f23	1091	#define HW_WDOG_PRESC(x) ((__IO hw_wdog_presc_t ) HW_WDOG_PRESC_ADDR(x))
mbed_official	324:406fd2029f23	1092	#define HW_WDOG_PRESC_RD(x) (HW_WDOG_PRESC(x).U)
mbed_official	324:406fd2029f23	1093	#define HW_WDOG_PRESC_WR(x, v) (HW_WDOG_PRESC(x).U = (v))
mbed_official	324:406fd2029f23	1094	#define HW_WDOG_PRESC_SET(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1095	#define HW_WDOG_PRESC_CLR(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1096	#define HW_WDOG_PRESC_TOG(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1097	/@}/
mbed_official	324:406fd2029f23	1098
mbed_official	324:406fd2029f23	1099	/*
mbed_official	324:406fd2029f23	1100	* Constants & macros for individual WDOG_PRESC bitfields
mbed_official	324:406fd2029f23	1101	*/
mbed_official	324:406fd2029f23	1102
mbed_official	324:406fd2029f23	1103	/*!
mbed_official	324:406fd2029f23	1104	* @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
mbed_official	324:406fd2029f23	1105	*
mbed_official	324:406fd2029f23	1106	* 3-bit prescaler for the watchdog clock source. A value of zero indicates no
mbed_official	324:406fd2029f23	1107	* division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
mbed_official	324:406fd2029f23	1108	* 1) to provide the prescaled WDOG_CLK.
mbed_official	324:406fd2029f23	1109	*/
mbed_official	324:406fd2029f23	1110	/@{/
mbed_official	324:406fd2029f23	1111	#define BP_WDOG_PRESC_PRESCVAL (8U) /!< Bit position for WDOG_PRESC_PRESCVAL. /
mbed_official	324:406fd2029f23	1112	#define BM_WDOG_PRESC_PRESCVAL (0x0700U) /!< Bit mask for WDOG_PRESC_PRESCVAL. /
mbed_official	324:406fd2029f23	1113	#define BS_WDOG_PRESC_PRESCVAL (3U) /!< Bit field size in bits for WDOG_PRESC_PRESCVAL. /
mbed_official	324:406fd2029f23	1114
mbed_official	324:406fd2029f23	1115	/! @brief Read current value of the WDOG_PRESC_PRESCVAL field. /
mbed_official	324:406fd2029f23	1116	#define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL)
mbed_official	324:406fd2029f23	1117
mbed_official	324:406fd2029f23	1118	/! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. /
mbed_official	324:406fd2029f23	1119	#define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL)
mbed_official	324:406fd2029f23	1120
mbed_official	324:406fd2029f23	1121	/! @brief Set the PRESCVAL field to a new value. /
mbed_official	324:406fd2029f23	1122	#define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) \| BF_WDOG_PRESC_PRESCVAL(v)))
mbed_official	324:406fd2029f23	1123	/@}/
mbed_official	324:406fd2029f23	1124
mbed_official	324:406fd2029f23	1125	/*******************************************************************************
mbed_official	324:406fd2029f23	1126	* hw_wdog_t - module struct
mbed_official	324:406fd2029f23	1127	******************************************************************************/
mbed_official	324:406fd2029f23	1128	/*!
mbed_official	324:406fd2029f23	1129	* @brief All WDOG module registers.
mbed_official	324:406fd2029f23	1130	*/
mbed_official	324:406fd2029f23	1131	#pragma pack(1)
mbed_official	324:406fd2029f23	1132	typedef struct _hw_wdog
mbed_official	324:406fd2029f23	1133	{
mbed_official	324:406fd2029f23	1134	__IO hw_wdog_stctrlh_t STCTRLH; /!< [0x0] Watchdog Status and Control Register High /
mbed_official	324:406fd2029f23	1135	__IO hw_wdog_stctrll_t STCTRLL; /!< [0x2] Watchdog Status and Control Register Low /
mbed_official	324:406fd2029f23	1136	__IO hw_wdog_tovalh_t TOVALH; /!< [0x4] Watchdog Time-out Value Register High /
mbed_official	324:406fd2029f23	1137	__IO hw_wdog_tovall_t TOVALL; /!< [0x6] Watchdog Time-out Value Register Low /
mbed_official	324:406fd2029f23	1138	__IO hw_wdog_winh_t WINH; /!< [0x8] Watchdog Window Register High /
mbed_official	324:406fd2029f23	1139	__IO hw_wdog_winl_t WINL; /!< [0xA] Watchdog Window Register Low /
mbed_official	324:406fd2029f23	1140	__IO hw_wdog_refresh_t REFRESH; /!< [0xC] Watchdog Refresh register /
mbed_official	324:406fd2029f23	1141	__IO hw_wdog_unlock_t UNLOCK; /!< [0xE] Watchdog Unlock register /
mbed_official	324:406fd2029f23	1142	__IO hw_wdog_tmrouth_t TMROUTH; /!< [0x10] Watchdog Timer Output Register High /
mbed_official	324:406fd2029f23	1143	__IO hw_wdog_tmroutl_t TMROUTL; /!< [0x12] Watchdog Timer Output Register Low /
mbed_official	324:406fd2029f23	1144	__IO hw_wdog_rstcnt_t RSTCNT; /!< [0x14] Watchdog Reset Count register /
mbed_official	324:406fd2029f23	1145	__IO hw_wdog_presc_t PRESC; /!< [0x16] Watchdog Prescaler register /
mbed_official	324:406fd2029f23	1146	} hw_wdog_t;
mbed_official	324:406fd2029f23	1147	#pragma pack()
mbed_official	324:406fd2029f23	1148
mbed_official	324:406fd2029f23	1149	/! @brief Macro to access all WDOG registers. /
mbed_official	324:406fd2029f23	1150	/! @param x WDOG module instance base address. /
mbed_official	324:406fd2029f23	1151	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	1152	* use the '&' operator, like <code>&HW_WDOG(WDOG_BASE)</code>. */
mbed_official	324:406fd2029f23	1153	#define HW_WDOG(x) ((hw_wdog_t )(x))
mbed_official	324:406fd2029f23	1154
mbed_official	324:406fd2029f23	1155	#endif /* __HW_WDOG_REGISTERS_H__ */
mbed_official	324:406fd2029f23	1156	/* EOF */