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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_VREF_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_VREF_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 VREF
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Voltage Reference
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_VREF_TRM - VREF Trim Register
mbed_official 324:406fd2029f23 93 * - HW_VREF_SC - VREF Status and Control Register
mbed_official 324:406fd2029f23 94 *
mbed_official 324:406fd2029f23 95 * - hw_vref_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 96 */
mbed_official 324:406fd2029f23 97
mbed_official 324:406fd2029f23 98 #define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 /*******************************************************************************
mbed_official 324:406fd2029f23 101 * HW_VREF_TRM - VREF Trim Register
mbed_official 324:406fd2029f23 102 ******************************************************************************/
mbed_official 324:406fd2029f23 103
mbed_official 324:406fd2029f23 104 /*!
mbed_official 324:406fd2029f23 105 * @brief HW_VREF_TRM - VREF Trim Register (RW)
mbed_official 324:406fd2029f23 106 *
mbed_official 324:406fd2029f23 107 * Reset value: 0x00U
mbed_official 324:406fd2029f23 108 *
mbed_official 324:406fd2029f23 109 * This register contains bits that contain the trim data for the Voltage
mbed_official 324:406fd2029f23 110 * Reference.
mbed_official 324:406fd2029f23 111 */
mbed_official 324:406fd2029f23 112 typedef union _hw_vref_trm
mbed_official 324:406fd2029f23 113 {
mbed_official 324:406fd2029f23 114 uint8_t U;
mbed_official 324:406fd2029f23 115 struct _hw_vref_trm_bitfields
mbed_official 324:406fd2029f23 116 {
mbed_official 324:406fd2029f23 117 uint8_t TRIM : 6; /*!< [5:0] Trim bits */
mbed_official 324:406fd2029f23 118 uint8_t CHOPEN : 1; /*!< [6] Chop oscillator enable. When set,
mbed_official 324:406fd2029f23 119 * internal chopping operation is enabled and the internal analog offset will be
mbed_official 324:406fd2029f23 120 * minimized. */
mbed_official 324:406fd2029f23 121 uint8_t RESERVED0 : 1; /*!< [7] */
mbed_official 324:406fd2029f23 122 } B;
mbed_official 324:406fd2029f23 123 } hw_vref_trm_t;
mbed_official 324:406fd2029f23 124
mbed_official 324:406fd2029f23 125 /*!
mbed_official 324:406fd2029f23 126 * @name Constants and macros for entire VREF_TRM register
mbed_official 324:406fd2029f23 127 */
mbed_official 324:406fd2029f23 128 /*@{*/
mbed_official 324:406fd2029f23 129 #define HW_VREF_TRM_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 #define HW_VREF_TRM(x) (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
mbed_official 324:406fd2029f23 132 #define HW_VREF_TRM_RD(x) (HW_VREF_TRM(x).U)
mbed_official 324:406fd2029f23 133 #define HW_VREF_TRM_WR(x, v) (HW_VREF_TRM(x).U = (v))
mbed_official 324:406fd2029f23 134 #define HW_VREF_TRM_SET(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) | (v)))
mbed_official 324:406fd2029f23 135 #define HW_VREF_TRM_CLR(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 136 #define HW_VREF_TRM_TOG(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 137 /*@}*/
mbed_official 324:406fd2029f23 138
mbed_official 324:406fd2029f23 139 /*
mbed_official 324:406fd2029f23 140 * Constants & macros for individual VREF_TRM bitfields
mbed_official 324:406fd2029f23 141 */
mbed_official 324:406fd2029f23 142
mbed_official 324:406fd2029f23 143 /*!
mbed_official 324:406fd2029f23 144 * @name Register VREF_TRM, field TRIM[5:0] (RW)
mbed_official 324:406fd2029f23 145 *
mbed_official 324:406fd2029f23 146 * These bits change the resulting VREF by approximately +/- 0.5 mV for each
mbed_official 324:406fd2029f23 147 * step. Min = minimum and max = maximum voltage reference output. For minimum and
mbed_official 324:406fd2029f23 148 * maximum voltage reference output values, refer to the Data Sheet for this chip.
mbed_official 324:406fd2029f23 149 *
mbed_official 324:406fd2029f23 150 * Values:
mbed_official 324:406fd2029f23 151 * - 000000 - Min
mbed_official 324:406fd2029f23 152 * - 111111 - Max
mbed_official 324:406fd2029f23 153 */
mbed_official 324:406fd2029f23 154 /*@{*/
mbed_official 324:406fd2029f23 155 #define BP_VREF_TRM_TRIM (0U) /*!< Bit position for VREF_TRM_TRIM. */
mbed_official 324:406fd2029f23 156 #define BM_VREF_TRM_TRIM (0x3FU) /*!< Bit mask for VREF_TRM_TRIM. */
mbed_official 324:406fd2029f23 157 #define BS_VREF_TRM_TRIM (6U) /*!< Bit field size in bits for VREF_TRM_TRIM. */
mbed_official 324:406fd2029f23 158
mbed_official 324:406fd2029f23 159 /*! @brief Read current value of the VREF_TRM_TRIM field. */
mbed_official 324:406fd2029f23 160 #define BR_VREF_TRM_TRIM(x) (HW_VREF_TRM(x).B.TRIM)
mbed_official 324:406fd2029f23 161
mbed_official 324:406fd2029f23 162 /*! @brief Format value for bitfield VREF_TRM_TRIM. */
mbed_official 324:406fd2029f23 163 #define BF_VREF_TRM_TRIM(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
mbed_official 324:406fd2029f23 164
mbed_official 324:406fd2029f23 165 /*! @brief Set the TRIM field to a new value. */
mbed_official 324:406fd2029f23 166 #define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
mbed_official 324:406fd2029f23 167 /*@}*/
mbed_official 324:406fd2029f23 168
mbed_official 324:406fd2029f23 169 /*!
mbed_official 324:406fd2029f23 170 * @name Register VREF_TRM, field CHOPEN[6] (RW)
mbed_official 324:406fd2029f23 171 *
mbed_official 324:406fd2029f23 172 * This bit is set during factory trimming of the VREF voltage. This bit should
mbed_official 324:406fd2029f23 173 * be written to 1 to achieve the performance stated in the data sheet.
mbed_official 324:406fd2029f23 174 *
mbed_official 324:406fd2029f23 175 * Values:
mbed_official 324:406fd2029f23 176 * - 0 - Chop oscillator is disabled.
mbed_official 324:406fd2029f23 177 * - 1 - Chop oscillator is enabled.
mbed_official 324:406fd2029f23 178 */
mbed_official 324:406fd2029f23 179 /*@{*/
mbed_official 324:406fd2029f23 180 #define BP_VREF_TRM_CHOPEN (6U) /*!< Bit position for VREF_TRM_CHOPEN. */
mbed_official 324:406fd2029f23 181 #define BM_VREF_TRM_CHOPEN (0x40U) /*!< Bit mask for VREF_TRM_CHOPEN. */
mbed_official 324:406fd2029f23 182 #define BS_VREF_TRM_CHOPEN (1U) /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
mbed_official 324:406fd2029f23 183
mbed_official 324:406fd2029f23 184 /*! @brief Read current value of the VREF_TRM_CHOPEN field. */
mbed_official 324:406fd2029f23 185 #define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
mbed_official 324:406fd2029f23 186
mbed_official 324:406fd2029f23 187 /*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
mbed_official 324:406fd2029f23 188 #define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
mbed_official 324:406fd2029f23 189
mbed_official 324:406fd2029f23 190 /*! @brief Set the CHOPEN field to a new value. */
mbed_official 324:406fd2029f23 191 #define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
mbed_official 324:406fd2029f23 192 /*@}*/
mbed_official 324:406fd2029f23 193
mbed_official 324:406fd2029f23 194 /*******************************************************************************
mbed_official 324:406fd2029f23 195 * HW_VREF_SC - VREF Status and Control Register
mbed_official 324:406fd2029f23 196 ******************************************************************************/
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*!
mbed_official 324:406fd2029f23 199 * @brief HW_VREF_SC - VREF Status and Control Register (RW)
mbed_official 324:406fd2029f23 200 *
mbed_official 324:406fd2029f23 201 * Reset value: 0x00U
mbed_official 324:406fd2029f23 202 *
mbed_official 324:406fd2029f23 203 * This register contains the control bits used to enable the internal voltage
mbed_official 324:406fd2029f23 204 * reference and to select the buffer mode to be used.
mbed_official 324:406fd2029f23 205 */
mbed_official 324:406fd2029f23 206 typedef union _hw_vref_sc
mbed_official 324:406fd2029f23 207 {
mbed_official 324:406fd2029f23 208 uint8_t U;
mbed_official 324:406fd2029f23 209 struct _hw_vref_sc_bitfields
mbed_official 324:406fd2029f23 210 {
mbed_official 324:406fd2029f23 211 uint8_t MODE_LV : 2; /*!< [1:0] Buffer Mode selection */
mbed_official 324:406fd2029f23 212 uint8_t VREFST : 1; /*!< [2] Internal Voltage Reference stable */
mbed_official 324:406fd2029f23 213 uint8_t RESERVED0 : 2; /*!< [4:3] */
mbed_official 324:406fd2029f23 214 uint8_t ICOMPEN : 1; /*!< [5] Second order curvature compensation
mbed_official 324:406fd2029f23 215 * enable */
mbed_official 324:406fd2029f23 216 uint8_t REGEN : 1; /*!< [6] Regulator enable */
mbed_official 324:406fd2029f23 217 uint8_t VREFEN : 1; /*!< [7] Internal Voltage Reference enable */
mbed_official 324:406fd2029f23 218 } B;
mbed_official 324:406fd2029f23 219 } hw_vref_sc_t;
mbed_official 324:406fd2029f23 220
mbed_official 324:406fd2029f23 221 /*!
mbed_official 324:406fd2029f23 222 * @name Constants and macros for entire VREF_SC register
mbed_official 324:406fd2029f23 223 */
mbed_official 324:406fd2029f23 224 /*@{*/
mbed_official 324:406fd2029f23 225 #define HW_VREF_SC_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 226
mbed_official 324:406fd2029f23 227 #define HW_VREF_SC(x) (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
mbed_official 324:406fd2029f23 228 #define HW_VREF_SC_RD(x) (HW_VREF_SC(x).U)
mbed_official 324:406fd2029f23 229 #define HW_VREF_SC_WR(x, v) (HW_VREF_SC(x).U = (v))
mbed_official 324:406fd2029f23 230 #define HW_VREF_SC_SET(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) | (v)))
mbed_official 324:406fd2029f23 231 #define HW_VREF_SC_CLR(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 232 #define HW_VREF_SC_TOG(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 233 /*@}*/
mbed_official 324:406fd2029f23 234
mbed_official 324:406fd2029f23 235 /*
mbed_official 324:406fd2029f23 236 * Constants & macros for individual VREF_SC bitfields
mbed_official 324:406fd2029f23 237 */
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*!
mbed_official 324:406fd2029f23 240 * @name Register VREF_SC, field MODE_LV[1:0] (RW)
mbed_official 324:406fd2029f23 241 *
mbed_official 324:406fd2029f23 242 * These bits select the buffer modes for the Voltage Reference module.
mbed_official 324:406fd2029f23 243 *
mbed_official 324:406fd2029f23 244 * Values:
mbed_official 324:406fd2029f23 245 * - 00 - Bandgap on only, for stabilization and startup
mbed_official 324:406fd2029f23 246 * - 01 - High power buffer mode enabled
mbed_official 324:406fd2029f23 247 * - 10 - Low-power buffer mode enabled
mbed_official 324:406fd2029f23 248 * - 11 - Reserved
mbed_official 324:406fd2029f23 249 */
mbed_official 324:406fd2029f23 250 /*@{*/
mbed_official 324:406fd2029f23 251 #define BP_VREF_SC_MODE_LV (0U) /*!< Bit position for VREF_SC_MODE_LV. */
mbed_official 324:406fd2029f23 252 #define BM_VREF_SC_MODE_LV (0x03U) /*!< Bit mask for VREF_SC_MODE_LV. */
mbed_official 324:406fd2029f23 253 #define BS_VREF_SC_MODE_LV (2U) /*!< Bit field size in bits for VREF_SC_MODE_LV. */
mbed_official 324:406fd2029f23 254
mbed_official 324:406fd2029f23 255 /*! @brief Read current value of the VREF_SC_MODE_LV field. */
mbed_official 324:406fd2029f23 256 #define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 /*! @brief Format value for bitfield VREF_SC_MODE_LV. */
mbed_official 324:406fd2029f23 259 #define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*! @brief Set the MODE_LV field to a new value. */
mbed_official 324:406fd2029f23 262 #define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
mbed_official 324:406fd2029f23 263 /*@}*/
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*!
mbed_official 324:406fd2029f23 266 * @name Register VREF_SC, field VREFST[2] (RO)
mbed_official 324:406fd2029f23 267 *
mbed_official 324:406fd2029f23 268 * This bit indicates that the bandgap reference within the Voltage Reference
mbed_official 324:406fd2029f23 269 * module has completed its startup and stabilization.
mbed_official 324:406fd2029f23 270 *
mbed_official 324:406fd2029f23 271 * Values:
mbed_official 324:406fd2029f23 272 * - 0 - The module is disabled or not stable.
mbed_official 324:406fd2029f23 273 * - 1 - The module is stable.
mbed_official 324:406fd2029f23 274 */
mbed_official 324:406fd2029f23 275 /*@{*/
mbed_official 324:406fd2029f23 276 #define BP_VREF_SC_VREFST (2U) /*!< Bit position for VREF_SC_VREFST. */
mbed_official 324:406fd2029f23 277 #define BM_VREF_SC_VREFST (0x04U) /*!< Bit mask for VREF_SC_VREFST. */
mbed_official 324:406fd2029f23 278 #define BS_VREF_SC_VREFST (1U) /*!< Bit field size in bits for VREF_SC_VREFST. */
mbed_official 324:406fd2029f23 279
mbed_official 324:406fd2029f23 280 /*! @brief Read current value of the VREF_SC_VREFST field. */
mbed_official 324:406fd2029f23 281 #define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
mbed_official 324:406fd2029f23 282 /*@}*/
mbed_official 324:406fd2029f23 283
mbed_official 324:406fd2029f23 284 /*!
mbed_official 324:406fd2029f23 285 * @name Register VREF_SC, field ICOMPEN[5] (RW)
mbed_official 324:406fd2029f23 286 *
mbed_official 324:406fd2029f23 287 * This bit is set during factory trimming of the VREF voltage. This bit should
mbed_official 324:406fd2029f23 288 * be written to 1 to achieve the performance stated in the data sheet.
mbed_official 324:406fd2029f23 289 *
mbed_official 324:406fd2029f23 290 * Values:
mbed_official 324:406fd2029f23 291 * - 0 - Disabled
mbed_official 324:406fd2029f23 292 * - 1 - Enabled
mbed_official 324:406fd2029f23 293 */
mbed_official 324:406fd2029f23 294 /*@{*/
mbed_official 324:406fd2029f23 295 #define BP_VREF_SC_ICOMPEN (5U) /*!< Bit position for VREF_SC_ICOMPEN. */
mbed_official 324:406fd2029f23 296 #define BM_VREF_SC_ICOMPEN (0x20U) /*!< Bit mask for VREF_SC_ICOMPEN. */
mbed_official 324:406fd2029f23 297 #define BS_VREF_SC_ICOMPEN (1U) /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
mbed_official 324:406fd2029f23 298
mbed_official 324:406fd2029f23 299 /*! @brief Read current value of the VREF_SC_ICOMPEN field. */
mbed_official 324:406fd2029f23 300 #define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
mbed_official 324:406fd2029f23 301
mbed_official 324:406fd2029f23 302 /*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
mbed_official 324:406fd2029f23 303 #define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
mbed_official 324:406fd2029f23 304
mbed_official 324:406fd2029f23 305 /*! @brief Set the ICOMPEN field to a new value. */
mbed_official 324:406fd2029f23 306 #define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
mbed_official 324:406fd2029f23 307 /*@}*/
mbed_official 324:406fd2029f23 308
mbed_official 324:406fd2029f23 309 /*!
mbed_official 324:406fd2029f23 310 * @name Register VREF_SC, field REGEN[6] (RW)
mbed_official 324:406fd2029f23 311 *
mbed_official 324:406fd2029f23 312 * This bit is used to enable the internal 1.75 V regulator to produce a
mbed_official 324:406fd2029f23 313 * constant internal voltage supply in order to reduce the sensitivity to external
mbed_official 324:406fd2029f23 314 * supply noise and variation. If it is desired to keep the regulator enabled in very
mbed_official 324:406fd2029f23 315 * low power modes, refer to the Chip Configuration details for a description on
mbed_official 324:406fd2029f23 316 * how this can be achieved. This bit is set during factory trimming of the VREF
mbed_official 324:406fd2029f23 317 * voltage. This bit should be written to 1 to achieve the performance stated in
mbed_official 324:406fd2029f23 318 * the data sheet.
mbed_official 324:406fd2029f23 319 *
mbed_official 324:406fd2029f23 320 * Values:
mbed_official 324:406fd2029f23 321 * - 0 - Internal 1.75 V regulator is disabled.
mbed_official 324:406fd2029f23 322 * - 1 - Internal 1.75 V regulator is enabled.
mbed_official 324:406fd2029f23 323 */
mbed_official 324:406fd2029f23 324 /*@{*/
mbed_official 324:406fd2029f23 325 #define BP_VREF_SC_REGEN (6U) /*!< Bit position for VREF_SC_REGEN. */
mbed_official 324:406fd2029f23 326 #define BM_VREF_SC_REGEN (0x40U) /*!< Bit mask for VREF_SC_REGEN. */
mbed_official 324:406fd2029f23 327 #define BS_VREF_SC_REGEN (1U) /*!< Bit field size in bits for VREF_SC_REGEN. */
mbed_official 324:406fd2029f23 328
mbed_official 324:406fd2029f23 329 /*! @brief Read current value of the VREF_SC_REGEN field. */
mbed_official 324:406fd2029f23 330 #define BR_VREF_SC_REGEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
mbed_official 324:406fd2029f23 331
mbed_official 324:406fd2029f23 332 /*! @brief Format value for bitfield VREF_SC_REGEN. */
mbed_official 324:406fd2029f23 333 #define BF_VREF_SC_REGEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
mbed_official 324:406fd2029f23 334
mbed_official 324:406fd2029f23 335 /*! @brief Set the REGEN field to a new value. */
mbed_official 324:406fd2029f23 336 #define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
mbed_official 324:406fd2029f23 337 /*@}*/
mbed_official 324:406fd2029f23 338
mbed_official 324:406fd2029f23 339 /*!
mbed_official 324:406fd2029f23 340 * @name Register VREF_SC, field VREFEN[7] (RW)
mbed_official 324:406fd2029f23 341 *
mbed_official 324:406fd2029f23 342 * This bit is used to enable the bandgap reference within the Voltage Reference
mbed_official 324:406fd2029f23 343 * module. After the VREF is enabled, turning off the clock to the VREF module
mbed_official 324:406fd2029f23 344 * via the corresponding clock gate register will not disable the VREF. VREF must
mbed_official 324:406fd2029f23 345 * be disabled via this VREFEN bit.
mbed_official 324:406fd2029f23 346 *
mbed_official 324:406fd2029f23 347 * Values:
mbed_official 324:406fd2029f23 348 * - 0 - The module is disabled.
mbed_official 324:406fd2029f23 349 * - 1 - The module is enabled.
mbed_official 324:406fd2029f23 350 */
mbed_official 324:406fd2029f23 351 /*@{*/
mbed_official 324:406fd2029f23 352 #define BP_VREF_SC_VREFEN (7U) /*!< Bit position for VREF_SC_VREFEN. */
mbed_official 324:406fd2029f23 353 #define BM_VREF_SC_VREFEN (0x80U) /*!< Bit mask for VREF_SC_VREFEN. */
mbed_official 324:406fd2029f23 354 #define BS_VREF_SC_VREFEN (1U) /*!< Bit field size in bits for VREF_SC_VREFEN. */
mbed_official 324:406fd2029f23 355
mbed_official 324:406fd2029f23 356 /*! @brief Read current value of the VREF_SC_VREFEN field. */
mbed_official 324:406fd2029f23 357 #define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*! @brief Format value for bitfield VREF_SC_VREFEN. */
mbed_official 324:406fd2029f23 360 #define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
mbed_official 324:406fd2029f23 361
mbed_official 324:406fd2029f23 362 /*! @brief Set the VREFEN field to a new value. */
mbed_official 324:406fd2029f23 363 #define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
mbed_official 324:406fd2029f23 364 /*@}*/
mbed_official 324:406fd2029f23 365
mbed_official 324:406fd2029f23 366 /*******************************************************************************
mbed_official 324:406fd2029f23 367 * hw_vref_t - module struct
mbed_official 324:406fd2029f23 368 ******************************************************************************/
mbed_official 324:406fd2029f23 369 /*!
mbed_official 324:406fd2029f23 370 * @brief All VREF module registers.
mbed_official 324:406fd2029f23 371 */
mbed_official 324:406fd2029f23 372 #pragma pack(1)
mbed_official 324:406fd2029f23 373 typedef struct _hw_vref
mbed_official 324:406fd2029f23 374 {
mbed_official 324:406fd2029f23 375 __IO hw_vref_trm_t TRM; /*!< [0x0] VREF Trim Register */
mbed_official 324:406fd2029f23 376 __IO hw_vref_sc_t SC; /*!< [0x1] VREF Status and Control Register */
mbed_official 324:406fd2029f23 377 } hw_vref_t;
mbed_official 324:406fd2029f23 378 #pragma pack()
mbed_official 324:406fd2029f23 379
mbed_official 324:406fd2029f23 380 /*! @brief Macro to access all VREF registers. */
mbed_official 324:406fd2029f23 381 /*! @param x VREF module instance base address. */
mbed_official 324:406fd2029f23 382 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 383 * use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
mbed_official 324:406fd2029f23 384 #define HW_VREF(x) (*(hw_vref_t *)(x))
mbed_official 324:406fd2029f23 385
mbed_official 324:406fd2029f23 386 #endif /* __HW_VREF_REGISTERS_H__ */
mbed_official 324:406fd2029f23 387 /* EOF */