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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_uart.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_UART_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_UART_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 UART
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Serial Communication Interface
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_UART_BDH - UART Baud Rate Registers: High
mbed_official	324:406fd2029f23	93	* - HW_UART_BDL - UART Baud Rate Registers: Low
mbed_official	324:406fd2029f23	94	* - HW_UART_C1 - UART Control Register 1
mbed_official	324:406fd2029f23	95	* - HW_UART_C2 - UART Control Register 2
mbed_official	324:406fd2029f23	96	* - HW_UART_S1 - UART Status Register 1
mbed_official	324:406fd2029f23	97	* - HW_UART_S2 - UART Status Register 2
mbed_official	324:406fd2029f23	98	* - HW_UART_C3 - UART Control Register 3
mbed_official	324:406fd2029f23	99	* - HW_UART_D - UART Data Register
mbed_official	324:406fd2029f23	100	* - HW_UART_MA1 - UART Match Address Registers 1
mbed_official	324:406fd2029f23	101	* - HW_UART_MA2 - UART Match Address Registers 2
mbed_official	324:406fd2029f23	102	* - HW_UART_C4 - UART Control Register 4
mbed_official	324:406fd2029f23	103	* - HW_UART_C5 - UART Control Register 5
mbed_official	324:406fd2029f23	104	* - HW_UART_ED - UART Extended Data Register
mbed_official	324:406fd2029f23	105	* - HW_UART_MODEM - UART Modem Register
mbed_official	324:406fd2029f23	106	* - HW_UART_IR - UART Infrared Register
mbed_official	324:406fd2029f23	107	* - HW_UART_PFIFO - UART FIFO Parameters
mbed_official	324:406fd2029f23	108	* - HW_UART_CFIFO - UART FIFO Control Register
mbed_official	324:406fd2029f23	109	* - HW_UART_SFIFO - UART FIFO Status Register
mbed_official	324:406fd2029f23	110	* - HW_UART_TWFIFO - UART FIFO Transmit Watermark
mbed_official	324:406fd2029f23	111	* - HW_UART_TCFIFO - UART FIFO Transmit Count
mbed_official	324:406fd2029f23	112	* - HW_UART_RWFIFO - UART FIFO Receive Watermark
mbed_official	324:406fd2029f23	113	* - HW_UART_RCFIFO - UART FIFO Receive Count
mbed_official	324:406fd2029f23	114	* - HW_UART_C7816 - UART 7816 Control Register
mbed_official	324:406fd2029f23	115	* - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
mbed_official	324:406fd2029f23	116	* - HW_UART_IS7816 - UART 7816 Interrupt Status Register
mbed_official	324:406fd2029f23	117	* - HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
mbed_official	324:406fd2029f23	118	* - HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
mbed_official	324:406fd2029f23	119	* - HW_UART_WN7816 - UART 7816 Wait N Register
mbed_official	324:406fd2029f23	120	* - HW_UART_WF7816 - UART 7816 Wait FD Register
mbed_official	324:406fd2029f23	121	* - HW_UART_ET7816 - UART 7816 Error Threshold Register
mbed_official	324:406fd2029f23	122	* - HW_UART_TL7816 - UART 7816 Transmit Length Register
mbed_official	324:406fd2029f23	123	*
mbed_official	324:406fd2029f23	124	* - hw_uart_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	125	*/
mbed_official	324:406fd2029f23	126
mbed_official	324:406fd2029f23	127	#define HW_UART_INSTANCE_COUNT (6U) /!< Number of instances of the UART module. /
mbed_official	324:406fd2029f23	128	#define HW_UART0 (0U) /!< Instance number for UART0. /
mbed_official	324:406fd2029f23	129	#define HW_UART1 (1U) /!< Instance number for UART1. /
mbed_official	324:406fd2029f23	130	#define HW_UART2 (2U) /!< Instance number for UART2. /
mbed_official	324:406fd2029f23	131	#define HW_UART3 (3U) /!< Instance number for UART3. /
mbed_official	324:406fd2029f23	132	#define HW_UART4 (4U) /!< Instance number for UART4. /
mbed_official	324:406fd2029f23	133	#define HW_UART5 (5U) /!< Instance number for UART5. /
mbed_official	324:406fd2029f23	134
mbed_official	324:406fd2029f23	135	/*******************************************************************************
mbed_official	324:406fd2029f23	136	* HW_UART_BDH - UART Baud Rate Registers: High
mbed_official	324:406fd2029f23	137	******************************************************************************/
mbed_official	324:406fd2029f23	138
mbed_official	324:406fd2029f23	139	/*!
mbed_official	324:406fd2029f23	140	* @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
mbed_official	324:406fd2029f23	141	*
mbed_official	324:406fd2029f23	142	* Reset value: 0x00U
mbed_official	324:406fd2029f23	143	*
mbed_official	324:406fd2029f23	144	* This register, along with the BDL register, controls the prescale divisor for
mbed_official	324:406fd2029f23	145	* UART baud rate generation. To update the 13-bit baud rate setting
mbed_official	324:406fd2029f23	146	* (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
mbed_official	324:406fd2029f23	147	* to BDL. The working value in BDH does not change until BDL is written. BDL is
mbed_official	324:406fd2029f23	148	* reset to a nonzero value, but after reset, the baud rate generator remains
mbed_official	324:406fd2029f23	149	* disabled until the first time the receiver or transmitter is enabled, that is,
mbed_official	324:406fd2029f23	150	* when C2[RE] or C2[TE] is set.
mbed_official	324:406fd2029f23	151	*/
mbed_official	324:406fd2029f23	152	typedef union _hw_uart_bdh
mbed_official	324:406fd2029f23	153	{
mbed_official	324:406fd2029f23	154	uint8_t U;
mbed_official	324:406fd2029f23	155	struct _hw_uart_bdh_bitfields
mbed_official	324:406fd2029f23	156	{
mbed_official	324:406fd2029f23	157	uint8_t SBR : 5; /!< [4:0] UART Baud Rate Bits /
mbed_official	324:406fd2029f23	158	uint8_t SBNS : 1; /!< [5] Stop Bit Number Select /
mbed_official	324:406fd2029f23	159	uint8_t RXEDGIE : 1; /*!< [6] RxD Input Active Edge Interrupt Enable
mbed_official	324:406fd2029f23	160	* */
mbed_official	324:406fd2029f23	161	uint8_t LBKDIE : 1; /*!< [7] LIN Break Detect Interrupt or DMA
mbed_official	324:406fd2029f23	162	* Request Enable */
mbed_official	324:406fd2029f23	163	} B;
mbed_official	324:406fd2029f23	164	} hw_uart_bdh_t;
mbed_official	324:406fd2029f23	165
mbed_official	324:406fd2029f23	166	/*!
mbed_official	324:406fd2029f23	167	* @name Constants and macros for entire UART_BDH register
mbed_official	324:406fd2029f23	168	*/
mbed_official	324:406fd2029f23	169	/@{/
mbed_official	324:406fd2029f23	170	#define HW_UART_BDH_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	171
mbed_official	324:406fd2029f23	172	#define HW_UART_BDH(x) ((__IO hw_uart_bdh_t ) HW_UART_BDH_ADDR(x))
mbed_official	324:406fd2029f23	173	#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
mbed_official	324:406fd2029f23	174	#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
mbed_official	324:406fd2029f23	175	#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	176	#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	177	#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	178	/@}/
mbed_official	324:406fd2029f23	179
mbed_official	324:406fd2029f23	180	/*
mbed_official	324:406fd2029f23	181	* Constants & macros for individual UART_BDH bitfields
mbed_official	324:406fd2029f23	182	*/
mbed_official	324:406fd2029f23	183
mbed_official	324:406fd2029f23	184	/*!
mbed_official	324:406fd2029f23	185	* @name Register UART_BDH, field SBR[4:0] (RW)
mbed_official	324:406fd2029f23	186	*
mbed_official	324:406fd2029f23	187	* The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
mbed_official	324:406fd2029f23	188	* generation for details. The baud rate generator is disabled until C2[TE] or
mbed_official	324:406fd2029f23	189	* C2[RE] is set for the first time after reset.The baud rate generator is disabled
mbed_official	324:406fd2029f23	190	* when SBR = 0. Writing to BDH has no effect without writing to BDL, because
mbed_official	324:406fd2029f23	191	* writing to BDH puts the data in a temporary location until BDL is written.
mbed_official	324:406fd2029f23	192	*/
mbed_official	324:406fd2029f23	193	/@{/
mbed_official	324:406fd2029f23	194	#define BP_UART_BDH_SBR (0U) /!< Bit position for UART_BDH_SBR. /
mbed_official	324:406fd2029f23	195	#define BM_UART_BDH_SBR (0x1FU) /!< Bit mask for UART_BDH_SBR. /
mbed_official	324:406fd2029f23	196	#define BS_UART_BDH_SBR (5U) /!< Bit field size in bits for UART_BDH_SBR. /
mbed_official	324:406fd2029f23	197
mbed_official	324:406fd2029f23	198	/! @brief Read current value of the UART_BDH_SBR field. /
mbed_official	324:406fd2029f23	199	#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
mbed_official	324:406fd2029f23	200
mbed_official	324:406fd2029f23	201	/! @brief Format value for bitfield UART_BDH_SBR. /
mbed_official	324:406fd2029f23	202	#define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR)
mbed_official	324:406fd2029f23	203
mbed_official	324:406fd2029f23	204	/! @brief Set the SBR field to a new value. /
mbed_official	324:406fd2029f23	205	#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) \| BF_UART_BDH_SBR(v)))
mbed_official	324:406fd2029f23	206	/@}/
mbed_official	324:406fd2029f23	207
mbed_official	324:406fd2029f23	208	/*!
mbed_official	324:406fd2029f23	209	* @name Register UART_BDH, field SBNS[5] (RW)
mbed_official	324:406fd2029f23	210	*
mbed_official	324:406fd2029f23	211	* SBNS selects the number of stop bits present in a data frame. This field
mbed_official	324:406fd2029f23	212	* valid for all 8, 9 and 10 bit data formats available. This field is not valid when
mbed_official	324:406fd2029f23	213	* C7816[ISO7816E] is enabled.
mbed_official	324:406fd2029f23	214	*
mbed_official	324:406fd2029f23	215	* Values:
mbed_official	324:406fd2029f23	216	* - 0 - Data frame consists of a single stop bit.
mbed_official	324:406fd2029f23	217	* - 1 - Data frame consists of two stop bits.
mbed_official	324:406fd2029f23	218	*/
mbed_official	324:406fd2029f23	219	/@{/
mbed_official	324:406fd2029f23	220	#define BP_UART_BDH_SBNS (5U) /!< Bit position for UART_BDH_SBNS. /
mbed_official	324:406fd2029f23	221	#define BM_UART_BDH_SBNS (0x20U) /!< Bit mask for UART_BDH_SBNS. /
mbed_official	324:406fd2029f23	222	#define BS_UART_BDH_SBNS (1U) /!< Bit field size in bits for UART_BDH_SBNS. /
mbed_official	324:406fd2029f23	223
mbed_official	324:406fd2029f23	224	/! @brief Read current value of the UART_BDH_SBNS field. /
mbed_official	324:406fd2029f23	225	#define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
mbed_official	324:406fd2029f23	226
mbed_official	324:406fd2029f23	227	/! @brief Format value for bitfield UART_BDH_SBNS. /
mbed_official	324:406fd2029f23	228	#define BF_UART_BDH_SBNS(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBNS) & BM_UART_BDH_SBNS)
mbed_official	324:406fd2029f23	229
mbed_official	324:406fd2029f23	230	/! @brief Set the SBNS field to a new value. /
mbed_official	324:406fd2029f23	231	#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
mbed_official	324:406fd2029f23	232	/@}/
mbed_official	324:406fd2029f23	233
mbed_official	324:406fd2029f23	234	/*!
mbed_official	324:406fd2029f23	235	* @name Register UART_BDH, field RXEDGIE[6] (RW)
mbed_official	324:406fd2029f23	236	*
mbed_official	324:406fd2029f23	237	* Enables the receive input active edge, RXEDGIF, to generate interrupt
mbed_official	324:406fd2029f23	238	* requests.
mbed_official	324:406fd2029f23	239	*
mbed_official	324:406fd2029f23	240	* Values:
mbed_official	324:406fd2029f23	241	* - 0 - Hardware interrupts from RXEDGIF disabled using polling.
mbed_official	324:406fd2029f23	242	* - 1 - RXEDGIF interrupt request enabled.
mbed_official	324:406fd2029f23	243	*/
mbed_official	324:406fd2029f23	244	/@{/
mbed_official	324:406fd2029f23	245	#define BP_UART_BDH_RXEDGIE (6U) /!< Bit position for UART_BDH_RXEDGIE. /
mbed_official	324:406fd2029f23	246	#define BM_UART_BDH_RXEDGIE (0x40U) /!< Bit mask for UART_BDH_RXEDGIE. /
mbed_official	324:406fd2029f23	247	#define BS_UART_BDH_RXEDGIE (1U) /!< Bit field size in bits for UART_BDH_RXEDGIE. /
mbed_official	324:406fd2029f23	248
mbed_official	324:406fd2029f23	249	/! @brief Read current value of the UART_BDH_RXEDGIE field. /
mbed_official	324:406fd2029f23	250	#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
mbed_official	324:406fd2029f23	251
mbed_official	324:406fd2029f23	252	/! @brief Format value for bitfield UART_BDH_RXEDGIE. /
mbed_official	324:406fd2029f23	253	#define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE)
mbed_official	324:406fd2029f23	254
mbed_official	324:406fd2029f23	255	/! @brief Set the RXEDGIE field to a new value. /
mbed_official	324:406fd2029f23	256	#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
mbed_official	324:406fd2029f23	257	/@}/
mbed_official	324:406fd2029f23	258
mbed_official	324:406fd2029f23	259	/*!
mbed_official	324:406fd2029f23	260	* @name Register UART_BDH, field LBKDIE[7] (RW)
mbed_official	324:406fd2029f23	261	*
mbed_official	324:406fd2029f23	262	* Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
mbed_official	324:406fd2029f23	263	* based on the state of LBKDDMAS. or DMA transfer requests,
mbed_official	324:406fd2029f23	264	*
mbed_official	324:406fd2029f23	265	* Values:
mbed_official	324:406fd2029f23	266	* - 0 - LBKDIF interrupt and DMA transfer requests disabled.
mbed_official	324:406fd2029f23	267	* - 1 - LBKDIF interrupt or DMA transfer requests enabled.
mbed_official	324:406fd2029f23	268	*/
mbed_official	324:406fd2029f23	269	/@{/
mbed_official	324:406fd2029f23	270	#define BP_UART_BDH_LBKDIE (7U) /!< Bit position for UART_BDH_LBKDIE. /
mbed_official	324:406fd2029f23	271	#define BM_UART_BDH_LBKDIE (0x80U) /!< Bit mask for UART_BDH_LBKDIE. /
mbed_official	324:406fd2029f23	272	#define BS_UART_BDH_LBKDIE (1U) /!< Bit field size in bits for UART_BDH_LBKDIE. /
mbed_official	324:406fd2029f23	273
mbed_official	324:406fd2029f23	274	/! @brief Read current value of the UART_BDH_LBKDIE field. /
mbed_official	324:406fd2029f23	275	#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
mbed_official	324:406fd2029f23	276
mbed_official	324:406fd2029f23	277	/! @brief Format value for bitfield UART_BDH_LBKDIE. /
mbed_official	324:406fd2029f23	278	#define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE)
mbed_official	324:406fd2029f23	279
mbed_official	324:406fd2029f23	280	/! @brief Set the LBKDIE field to a new value. /
mbed_official	324:406fd2029f23	281	#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
mbed_official	324:406fd2029f23	282	/@}/
mbed_official	324:406fd2029f23	283
mbed_official	324:406fd2029f23	284	/*******************************************************************************
mbed_official	324:406fd2029f23	285	* HW_UART_BDL - UART Baud Rate Registers: Low
mbed_official	324:406fd2029f23	286	******************************************************************************/
mbed_official	324:406fd2029f23	287
mbed_official	324:406fd2029f23	288	/*!
mbed_official	324:406fd2029f23	289	* @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
mbed_official	324:406fd2029f23	290	*
mbed_official	324:406fd2029f23	291	* Reset value: 0x04U
mbed_official	324:406fd2029f23	292	*
mbed_official	324:406fd2029f23	293	* This register, along with the BDH register, controls the prescale divisor for
mbed_official	324:406fd2029f23	294	* UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
mbed_official	324:406fd2029f23	295	* first write to BDH to buffer the high half of the new value and then write to
mbed_official	324:406fd2029f23	296	* BDL. The working value in BDH does not change until BDL is written. BDL is
mbed_official	324:406fd2029f23	297	* reset to a nonzero value, but after reset, the baud rate generator remains
mbed_official	324:406fd2029f23	298	* disabled until the first time the receiver or transmitter is enabled, that is, when
mbed_official	324:406fd2029f23	299	* C2[RE] or C2[TE] is set.
mbed_official	324:406fd2029f23	300	*/
mbed_official	324:406fd2029f23	301	typedef union _hw_uart_bdl
mbed_official	324:406fd2029f23	302	{
mbed_official	324:406fd2029f23	303	uint8_t U;
mbed_official	324:406fd2029f23	304	struct _hw_uart_bdl_bitfields
mbed_official	324:406fd2029f23	305	{
mbed_official	324:406fd2029f23	306	uint8_t SBR : 8; /!< [7:0] UART Baud Rate Bits /
mbed_official	324:406fd2029f23	307	} B;
mbed_official	324:406fd2029f23	308	} hw_uart_bdl_t;
mbed_official	324:406fd2029f23	309
mbed_official	324:406fd2029f23	310	/*!
mbed_official	324:406fd2029f23	311	* @name Constants and macros for entire UART_BDL register
mbed_official	324:406fd2029f23	312	*/
mbed_official	324:406fd2029f23	313	/@{/
mbed_official	324:406fd2029f23	314	#define HW_UART_BDL_ADDR(x) ((x) + 0x1U)
mbed_official	324:406fd2029f23	315
mbed_official	324:406fd2029f23	316	#define HW_UART_BDL(x) ((__IO hw_uart_bdl_t ) HW_UART_BDL_ADDR(x))
mbed_official	324:406fd2029f23	317	#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
mbed_official	324:406fd2029f23	318	#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
mbed_official	324:406fd2029f23	319	#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	320	#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	321	#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	322	/@}/
mbed_official	324:406fd2029f23	323
mbed_official	324:406fd2029f23	324	/*
mbed_official	324:406fd2029f23	325	* Constants & macros for individual UART_BDL bitfields
mbed_official	324:406fd2029f23	326	*/
mbed_official	324:406fd2029f23	327
mbed_official	324:406fd2029f23	328	/*!
mbed_official	324:406fd2029f23	329	* @name Register UART_BDL, field SBR[7:0] (RW)
mbed_official	324:406fd2029f23	330	*
mbed_official	324:406fd2029f23	331	* The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
mbed_official	324:406fd2029f23	332	* generation for details. The baud rate generator is disabled until C2[TE] or
mbed_official	324:406fd2029f23	333	* C2[RE] is set for the first time after reset.The baud rate generator is disabled
mbed_official	324:406fd2029f23	334	* when SBR = 0. Writing to BDH has no effect without writing to BDL, because
mbed_official	324:406fd2029f23	335	* writing to BDH puts the data in a temporary location until BDL is written. When
mbed_official	324:406fd2029f23	336	* the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
mbed_official	324:406fd2029f23	337	* fields must be even, the least significant bit is 0. See MODEM register for more
mbed_official	324:406fd2029f23	338	* details.
mbed_official	324:406fd2029f23	339	*/
mbed_official	324:406fd2029f23	340	/@{/
mbed_official	324:406fd2029f23	341	#define BP_UART_BDL_SBR (0U) /!< Bit position for UART_BDL_SBR. /
mbed_official	324:406fd2029f23	342	#define BM_UART_BDL_SBR (0xFFU) /!< Bit mask for UART_BDL_SBR. /
mbed_official	324:406fd2029f23	343	#define BS_UART_BDL_SBR (8U) /!< Bit field size in bits for UART_BDL_SBR. /
mbed_official	324:406fd2029f23	344
mbed_official	324:406fd2029f23	345	/! @brief Read current value of the UART_BDL_SBR field. /
mbed_official	324:406fd2029f23	346	#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
mbed_official	324:406fd2029f23	347
mbed_official	324:406fd2029f23	348	/! @brief Format value for bitfield UART_BDL_SBR. /
mbed_official	324:406fd2029f23	349	#define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR)
mbed_official	324:406fd2029f23	350
mbed_official	324:406fd2029f23	351	/! @brief Set the SBR field to a new value. /
mbed_official	324:406fd2029f23	352	#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
mbed_official	324:406fd2029f23	353	/@}/
mbed_official	324:406fd2029f23	354
mbed_official	324:406fd2029f23	355	/*******************************************************************************
mbed_official	324:406fd2029f23	356	* HW_UART_C1 - UART Control Register 1
mbed_official	324:406fd2029f23	357	******************************************************************************/
mbed_official	324:406fd2029f23	358
mbed_official	324:406fd2029f23	359	/*!
mbed_official	324:406fd2029f23	360	* @brief HW_UART_C1 - UART Control Register 1 (RW)
mbed_official	324:406fd2029f23	361	*
mbed_official	324:406fd2029f23	362	* Reset value: 0x00U
mbed_official	324:406fd2029f23	363	*
mbed_official	324:406fd2029f23	364	* This read/write register controls various optional features of the UART
mbed_official	324:406fd2029f23	365	* system.
mbed_official	324:406fd2029f23	366	*/
mbed_official	324:406fd2029f23	367	typedef union _hw_uart_c1
mbed_official	324:406fd2029f23	368	{
mbed_official	324:406fd2029f23	369	uint8_t U;
mbed_official	324:406fd2029f23	370	struct _hw_uart_c1_bitfields
mbed_official	324:406fd2029f23	371	{
mbed_official	324:406fd2029f23	372	uint8_t PT : 1; /!< [0] Parity Type /
mbed_official	324:406fd2029f23	373	uint8_t PE : 1; /!< [1] Parity Enable /
mbed_official	324:406fd2029f23	374	uint8_t ILT : 1; /!< [2] Idle Line Type Select /
mbed_official	324:406fd2029f23	375	uint8_t WAKE : 1; /!< [3] Receiver Wakeup Method Select /
mbed_official	324:406fd2029f23	376	uint8_t M : 1; /!< [4] 9-bit or 8-bit Mode Select /
mbed_official	324:406fd2029f23	377	uint8_t RSRC : 1; /!< [5] Receiver Source Select /
mbed_official	324:406fd2029f23	378	uint8_t UARTSWAI : 1; /!< [6] UART Stops in Wait Mode /
mbed_official	324:406fd2029f23	379	uint8_t LOOPS : 1; /!< [7] Loop Mode Select /
mbed_official	324:406fd2029f23	380	} B;
mbed_official	324:406fd2029f23	381	} hw_uart_c1_t;
mbed_official	324:406fd2029f23	382
mbed_official	324:406fd2029f23	383	/*!
mbed_official	324:406fd2029f23	384	* @name Constants and macros for entire UART_C1 register
mbed_official	324:406fd2029f23	385	*/
mbed_official	324:406fd2029f23	386	/@{/
mbed_official	324:406fd2029f23	387	#define HW_UART_C1_ADDR(x) ((x) + 0x2U)
mbed_official	324:406fd2029f23	388
mbed_official	324:406fd2029f23	389	#define HW_UART_C1(x) ((__IO hw_uart_c1_t ) HW_UART_C1_ADDR(x))
mbed_official	324:406fd2029f23	390	#define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
mbed_official	324:406fd2029f23	391	#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
mbed_official	324:406fd2029f23	392	#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	393	#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	394	#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	395	/@}/
mbed_official	324:406fd2029f23	396
mbed_official	324:406fd2029f23	397	/*
mbed_official	324:406fd2029f23	398	* Constants & macros for individual UART_C1 bitfields
mbed_official	324:406fd2029f23	399	*/
mbed_official	324:406fd2029f23	400
mbed_official	324:406fd2029f23	401	/*!
mbed_official	324:406fd2029f23	402	* @name Register UART_C1, field PT[0] (RW)
mbed_official	324:406fd2029f23	403	*
mbed_official	324:406fd2029f23	404	* Determines whether the UART generates and checks for even parity or odd
mbed_official	324:406fd2029f23	405	* parity. With even parity, an even number of 1s clears the parity bit and an odd
mbed_official	324:406fd2029f23	406	* number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
mbed_official	324:406fd2029f23	407	* parity bit and an even number of 1s sets the parity bit. This field must be
mbed_official	324:406fd2029f23	408	* cleared when C7816[ISO_7816E] is set/enabled.
mbed_official	324:406fd2029f23	409	*
mbed_official	324:406fd2029f23	410	* Values:
mbed_official	324:406fd2029f23	411	* - 0 - Even parity.
mbed_official	324:406fd2029f23	412	* - 1 - Odd parity.
mbed_official	324:406fd2029f23	413	*/
mbed_official	324:406fd2029f23	414	/@{/
mbed_official	324:406fd2029f23	415	#define BP_UART_C1_PT (0U) /!< Bit position for UART_C1_PT. /
mbed_official	324:406fd2029f23	416	#define BM_UART_C1_PT (0x01U) /!< Bit mask for UART_C1_PT. /
mbed_official	324:406fd2029f23	417	#define BS_UART_C1_PT (1U) /!< Bit field size in bits for UART_C1_PT. /
mbed_official	324:406fd2029f23	418
mbed_official	324:406fd2029f23	419	/! @brief Read current value of the UART_C1_PT field. /
mbed_official	324:406fd2029f23	420	#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
mbed_official	324:406fd2029f23	421
mbed_official	324:406fd2029f23	422	/! @brief Format value for bitfield UART_C1_PT. /
mbed_official	324:406fd2029f23	423	#define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT)
mbed_official	324:406fd2029f23	424
mbed_official	324:406fd2029f23	425	/! @brief Set the PT field to a new value. /
mbed_official	324:406fd2029f23	426	#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
mbed_official	324:406fd2029f23	427	/@}/
mbed_official	324:406fd2029f23	428
mbed_official	324:406fd2029f23	429	/*!
mbed_official	324:406fd2029f23	430	* @name Register UART_C1, field PE[1] (RW)
mbed_official	324:406fd2029f23	431	*
mbed_official	324:406fd2029f23	432	* Enables the parity function. When parity is enabled, parity function inserts
mbed_official	324:406fd2029f23	433	* a parity bit in the bit position immediately preceding the stop bit. This
mbed_official	324:406fd2029f23	434	* field must be set when C7816[ISO_7816E] is set/enabled.
mbed_official	324:406fd2029f23	435	*
mbed_official	324:406fd2029f23	436	* Values:
mbed_official	324:406fd2029f23	437	* - 0 - Parity function disabled.
mbed_official	324:406fd2029f23	438	* - 1 - Parity function enabled.
mbed_official	324:406fd2029f23	439	*/
mbed_official	324:406fd2029f23	440	/@{/
mbed_official	324:406fd2029f23	441	#define BP_UART_C1_PE (1U) /!< Bit position for UART_C1_PE. /
mbed_official	324:406fd2029f23	442	#define BM_UART_C1_PE (0x02U) /!< Bit mask for UART_C1_PE. /
mbed_official	324:406fd2029f23	443	#define BS_UART_C1_PE (1U) /!< Bit field size in bits for UART_C1_PE. /
mbed_official	324:406fd2029f23	444
mbed_official	324:406fd2029f23	445	/! @brief Read current value of the UART_C1_PE field. /
mbed_official	324:406fd2029f23	446	#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
mbed_official	324:406fd2029f23	447
mbed_official	324:406fd2029f23	448	/! @brief Format value for bitfield UART_C1_PE. /
mbed_official	324:406fd2029f23	449	#define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE)
mbed_official	324:406fd2029f23	450
mbed_official	324:406fd2029f23	451	/! @brief Set the PE field to a new value. /
mbed_official	324:406fd2029f23	452	#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
mbed_official	324:406fd2029f23	453	/@}/
mbed_official	324:406fd2029f23	454
mbed_official	324:406fd2029f23	455	/*!
mbed_official	324:406fd2029f23	456	* @name Register UART_C1, field ILT[2] (RW)
mbed_official	324:406fd2029f23	457	*
mbed_official	324:406fd2029f23	458	* Determines when the receiver starts counting logic 1s as idle character bits.
mbed_official	324:406fd2029f23	459	* The count begins either after a valid start bit or after the stop bit. If the
mbed_official	324:406fd2029f23	460	* count begins after the start bit, then a string of logic 1s preceding the
mbed_official	324:406fd2029f23	461	* stop bit can cause false recognition of an idle character. Beginning the count
mbed_official	324:406fd2029f23	462	* after the stop bit avoids false idle character recognition, but requires
mbed_official	324:406fd2029f23	463	* properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
mbed_official	324:406fd2029f23	464	* logic of 1'b0 is automatically shifted after a received stop bit, therefore
mbed_official	324:406fd2029f23	465	* resetting the idle count. In case the UART is programmed for IDLE line wakeup
mbed_official	324:406fd2029f23	466	* (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
mbed_official	324:406fd2029f23	467	* logic 1s as idle character bits. In idle line wakeup, an idle character is
mbed_official	324:406fd2029f23	468	* recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
mbed_official	324:406fd2029f23	469	* and C4[M10] fields.
mbed_official	324:406fd2029f23	470	*
mbed_official	324:406fd2029f23	471	* Values:
mbed_official	324:406fd2029f23	472	* - 0 - Idle character bit count starts after start bit.
mbed_official	324:406fd2029f23	473	* - 1 - Idle character bit count starts after stop bit.
mbed_official	324:406fd2029f23	474	*/
mbed_official	324:406fd2029f23	475	/@{/
mbed_official	324:406fd2029f23	476	#define BP_UART_C1_ILT (2U) /!< Bit position for UART_C1_ILT. /
mbed_official	324:406fd2029f23	477	#define BM_UART_C1_ILT (0x04U) /!< Bit mask for UART_C1_ILT. /
mbed_official	324:406fd2029f23	478	#define BS_UART_C1_ILT (1U) /!< Bit field size in bits for UART_C1_ILT. /
mbed_official	324:406fd2029f23	479
mbed_official	324:406fd2029f23	480	/! @brief Read current value of the UART_C1_ILT field. /
mbed_official	324:406fd2029f23	481	#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
mbed_official	324:406fd2029f23	482
mbed_official	324:406fd2029f23	483	/! @brief Format value for bitfield UART_C1_ILT. /
mbed_official	324:406fd2029f23	484	#define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT)
mbed_official	324:406fd2029f23	485
mbed_official	324:406fd2029f23	486	/! @brief Set the ILT field to a new value. /
mbed_official	324:406fd2029f23	487	#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
mbed_official	324:406fd2029f23	488	/@}/
mbed_official	324:406fd2029f23	489
mbed_official	324:406fd2029f23	490	/*!
mbed_official	324:406fd2029f23	491	* @name Register UART_C1, field WAKE[3] (RW)
mbed_official	324:406fd2029f23	492	*
mbed_official	324:406fd2029f23	493	* Determines which condition wakes the UART: Address mark in the most
mbed_official	324:406fd2029f23	494	* significant bit position of a received data character, or An idle condition on the
mbed_official	324:406fd2029f23	495	* receive pin input signal.
mbed_official	324:406fd2029f23	496	*
mbed_official	324:406fd2029f23	497	* Values:
mbed_official	324:406fd2029f23	498	* - 0 - Idle line wakeup.
mbed_official	324:406fd2029f23	499	* - 1 - Address mark wakeup.
mbed_official	324:406fd2029f23	500	*/
mbed_official	324:406fd2029f23	501	/@{/
mbed_official	324:406fd2029f23	502	#define BP_UART_C1_WAKE (3U) /!< Bit position for UART_C1_WAKE. /
mbed_official	324:406fd2029f23	503	#define BM_UART_C1_WAKE (0x08U) /!< Bit mask for UART_C1_WAKE. /
mbed_official	324:406fd2029f23	504	#define BS_UART_C1_WAKE (1U) /!< Bit field size in bits for UART_C1_WAKE. /
mbed_official	324:406fd2029f23	505
mbed_official	324:406fd2029f23	506	/! @brief Read current value of the UART_C1_WAKE field. /
mbed_official	324:406fd2029f23	507	#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
mbed_official	324:406fd2029f23	508
mbed_official	324:406fd2029f23	509	/! @brief Format value for bitfield UART_C1_WAKE. /
mbed_official	324:406fd2029f23	510	#define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE)
mbed_official	324:406fd2029f23	511
mbed_official	324:406fd2029f23	512	/! @brief Set the WAKE field to a new value. /
mbed_official	324:406fd2029f23	513	#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
mbed_official	324:406fd2029f23	514	/@}/
mbed_official	324:406fd2029f23	515
mbed_official	324:406fd2029f23	516	/*!
mbed_official	324:406fd2029f23	517	* @name Register UART_C1, field M[4] (RW)
mbed_official	324:406fd2029f23	518	*
mbed_official	324:406fd2029f23	519	* This field must be set when C7816[ISO_7816E] is set/enabled.
mbed_official	324:406fd2029f23	520	*
mbed_official	324:406fd2029f23	521	* Values:
mbed_official	324:406fd2029f23	522	* - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
mbed_official	324:406fd2029f23	523	* - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
mbed_official	324:406fd2029f23	524	*/
mbed_official	324:406fd2029f23	525	/@{/
mbed_official	324:406fd2029f23	526	#define BP_UART_C1_M (4U) /!< Bit position for UART_C1_M. /
mbed_official	324:406fd2029f23	527	#define BM_UART_C1_M (0x10U) /!< Bit mask for UART_C1_M. /
mbed_official	324:406fd2029f23	528	#define BS_UART_C1_M (1U) /!< Bit field size in bits for UART_C1_M. /
mbed_official	324:406fd2029f23	529
mbed_official	324:406fd2029f23	530	/! @brief Read current value of the UART_C1_M field. /
mbed_official	324:406fd2029f23	531	#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
mbed_official	324:406fd2029f23	532
mbed_official	324:406fd2029f23	533	/! @brief Format value for bitfield UART_C1_M. /
mbed_official	324:406fd2029f23	534	#define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M)
mbed_official	324:406fd2029f23	535
mbed_official	324:406fd2029f23	536	/! @brief Set the M field to a new value. /
mbed_official	324:406fd2029f23	537	#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
mbed_official	324:406fd2029f23	538	/@}/
mbed_official	324:406fd2029f23	539
mbed_official	324:406fd2029f23	540	/*!
mbed_official	324:406fd2029f23	541	* @name Register UART_C1, field RSRC[5] (RW)
mbed_official	324:406fd2029f23	542	*
mbed_official	324:406fd2029f23	543	* This field has no meaning or effect unless the LOOPS field is set. When LOOPS
mbed_official	324:406fd2029f23	544	* is set, the RSRC field determines the source for the receiver shift register
mbed_official	324:406fd2029f23	545	* input.
mbed_official	324:406fd2029f23	546	*
mbed_official	324:406fd2029f23	547	* Values:
mbed_official	324:406fd2029f23	548	* - 0 - Selects internal loop back mode. The receiver input is internally
mbed_official	324:406fd2029f23	549	* connected to transmitter output.
mbed_official	324:406fd2029f23	550	* - 1 - Single wire UART mode where the receiver input is connected to the
mbed_official	324:406fd2029f23	551	* transmit pin input signal.
mbed_official	324:406fd2029f23	552	*/
mbed_official	324:406fd2029f23	553	/@{/
mbed_official	324:406fd2029f23	554	#define BP_UART_C1_RSRC (5U) /!< Bit position for UART_C1_RSRC. /
mbed_official	324:406fd2029f23	555	#define BM_UART_C1_RSRC (0x20U) /!< Bit mask for UART_C1_RSRC. /
mbed_official	324:406fd2029f23	556	#define BS_UART_C1_RSRC (1U) /!< Bit field size in bits for UART_C1_RSRC. /
mbed_official	324:406fd2029f23	557
mbed_official	324:406fd2029f23	558	/! @brief Read current value of the UART_C1_RSRC field. /
mbed_official	324:406fd2029f23	559	#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
mbed_official	324:406fd2029f23	560
mbed_official	324:406fd2029f23	561	/! @brief Format value for bitfield UART_C1_RSRC. /
mbed_official	324:406fd2029f23	562	#define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC)
mbed_official	324:406fd2029f23	563
mbed_official	324:406fd2029f23	564	/! @brief Set the RSRC field to a new value. /
mbed_official	324:406fd2029f23	565	#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
mbed_official	324:406fd2029f23	566	/@}/
mbed_official	324:406fd2029f23	567
mbed_official	324:406fd2029f23	568	/*!
mbed_official	324:406fd2029f23	569	* @name Register UART_C1, field UARTSWAI[6] (RW)
mbed_official	324:406fd2029f23	570	*
mbed_official	324:406fd2029f23	571	* Values:
mbed_official	324:406fd2029f23	572	* - 0 - UART clock continues to run in Wait mode.
mbed_official	324:406fd2029f23	573	* - 1 - UART clock freezes while CPU is in Wait mode.
mbed_official	324:406fd2029f23	574	*/
mbed_official	324:406fd2029f23	575	/@{/
mbed_official	324:406fd2029f23	576	#define BP_UART_C1_UARTSWAI (6U) /!< Bit position for UART_C1_UARTSWAI. /
mbed_official	324:406fd2029f23	577	#define BM_UART_C1_UARTSWAI (0x40U) /!< Bit mask for UART_C1_UARTSWAI. /
mbed_official	324:406fd2029f23	578	#define BS_UART_C1_UARTSWAI (1U) /!< Bit field size in bits for UART_C1_UARTSWAI. /
mbed_official	324:406fd2029f23	579
mbed_official	324:406fd2029f23	580	/! @brief Read current value of the UART_C1_UARTSWAI field. /
mbed_official	324:406fd2029f23	581	#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
mbed_official	324:406fd2029f23	582
mbed_official	324:406fd2029f23	583	/! @brief Format value for bitfield UART_C1_UARTSWAI. /
mbed_official	324:406fd2029f23	584	#define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI)
mbed_official	324:406fd2029f23	585
mbed_official	324:406fd2029f23	586	/! @brief Set the UARTSWAI field to a new value. /
mbed_official	324:406fd2029f23	587	#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
mbed_official	324:406fd2029f23	588	/@}/
mbed_official	324:406fd2029f23	589
mbed_official	324:406fd2029f23	590	/*!
mbed_official	324:406fd2029f23	591	* @name Register UART_C1, field LOOPS[7] (RW)
mbed_official	324:406fd2029f23	592	*
mbed_official	324:406fd2029f23	593	* When LOOPS is set, the RxD pin is disconnected from the UART and the
mbed_official	324:406fd2029f23	594	* transmitter output is internally connected to the receiver input. The transmitter and
mbed_official	324:406fd2029f23	595	* the receiver must be enabled to use the loop function.
mbed_official	324:406fd2029f23	596	*
mbed_official	324:406fd2029f23	597	* Values:
mbed_official	324:406fd2029f23	598	* - 0 - Normal operation.
mbed_official	324:406fd2029f23	599	* - 1 - Loop mode where transmitter output is internally connected to receiver
mbed_official	324:406fd2029f23	600	* input. The receiver input is determined by RSRC.
mbed_official	324:406fd2029f23	601	*/
mbed_official	324:406fd2029f23	602	/@{/
mbed_official	324:406fd2029f23	603	#define BP_UART_C1_LOOPS (7U) /!< Bit position for UART_C1_LOOPS. /
mbed_official	324:406fd2029f23	604	#define BM_UART_C1_LOOPS (0x80U) /!< Bit mask for UART_C1_LOOPS. /
mbed_official	324:406fd2029f23	605	#define BS_UART_C1_LOOPS (1U) /!< Bit field size in bits for UART_C1_LOOPS. /
mbed_official	324:406fd2029f23	606
mbed_official	324:406fd2029f23	607	/! @brief Read current value of the UART_C1_LOOPS field. /
mbed_official	324:406fd2029f23	608	#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
mbed_official	324:406fd2029f23	609
mbed_official	324:406fd2029f23	610	/! @brief Format value for bitfield UART_C1_LOOPS. /
mbed_official	324:406fd2029f23	611	#define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS)
mbed_official	324:406fd2029f23	612
mbed_official	324:406fd2029f23	613	/! @brief Set the LOOPS field to a new value. /
mbed_official	324:406fd2029f23	614	#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
mbed_official	324:406fd2029f23	615	/@}/
mbed_official	324:406fd2029f23	616
mbed_official	324:406fd2029f23	617	/*******************************************************************************
mbed_official	324:406fd2029f23	618	* HW_UART_C2 - UART Control Register 2
mbed_official	324:406fd2029f23	619	******************************************************************************/
mbed_official	324:406fd2029f23	620
mbed_official	324:406fd2029f23	621	/*!
mbed_official	324:406fd2029f23	622	* @brief HW_UART_C2 - UART Control Register 2 (RW)
mbed_official	324:406fd2029f23	623	*
mbed_official	324:406fd2029f23	624	* Reset value: 0x00U
mbed_official	324:406fd2029f23	625	*
mbed_official	324:406fd2029f23	626	* This register can be read or written at any time.
mbed_official	324:406fd2029f23	627	*/
mbed_official	324:406fd2029f23	628	typedef union _hw_uart_c2
mbed_official	324:406fd2029f23	629	{
mbed_official	324:406fd2029f23	630	uint8_t U;
mbed_official	324:406fd2029f23	631	struct _hw_uart_c2_bitfields
mbed_official	324:406fd2029f23	632	{
mbed_official	324:406fd2029f23	633	uint8_t SBK : 1; /!< [0] Send Break /
mbed_official	324:406fd2029f23	634	uint8_t RWU : 1; /!< [1] Receiver Wakeup Control /
mbed_official	324:406fd2029f23	635	uint8_t RE : 1; /!< [2] Receiver Enable /
mbed_official	324:406fd2029f23	636	uint8_t TE : 1; /!< [3] Transmitter Enable /
mbed_official	324:406fd2029f23	637	uint8_t ILIE : 1; /!< [4] Idle Line Interrupt DMA Transfer Enable /
mbed_official	324:406fd2029f23	638	uint8_t RIE : 1; /*!< [5] Receiver Full Interrupt or DMA Transfer
mbed_official	324:406fd2029f23	639	* Enable */
mbed_official	324:406fd2029f23	640	uint8_t TCIE : 1; /*!< [6] Transmission Complete Interrupt or DMA
mbed_official	324:406fd2029f23	641	* Transfer Enable */
mbed_official	324:406fd2029f23	642	uint8_t TIE : 1; /*!< [7] Transmitter Interrupt or DMA Transfer
mbed_official	324:406fd2029f23	643	* Enable. */
mbed_official	324:406fd2029f23	644	} B;
mbed_official	324:406fd2029f23	645	} hw_uart_c2_t;
mbed_official	324:406fd2029f23	646
mbed_official	324:406fd2029f23	647	/*!
mbed_official	324:406fd2029f23	648	* @name Constants and macros for entire UART_C2 register
mbed_official	324:406fd2029f23	649	*/
mbed_official	324:406fd2029f23	650	/@{/
mbed_official	324:406fd2029f23	651	#define HW_UART_C2_ADDR(x) ((x) + 0x3U)
mbed_official	324:406fd2029f23	652
mbed_official	324:406fd2029f23	653	#define HW_UART_C2(x) ((__IO hw_uart_c2_t ) HW_UART_C2_ADDR(x))
mbed_official	324:406fd2029f23	654	#define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
mbed_official	324:406fd2029f23	655	#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
mbed_official	324:406fd2029f23	656	#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	657	#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	658	#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	659	/@}/
mbed_official	324:406fd2029f23	660
mbed_official	324:406fd2029f23	661	/*
mbed_official	324:406fd2029f23	662	* Constants & macros for individual UART_C2 bitfields
mbed_official	324:406fd2029f23	663	*/
mbed_official	324:406fd2029f23	664
mbed_official	324:406fd2029f23	665	/*!
mbed_official	324:406fd2029f23	666	* @name Register UART_C2, field SBK[0] (RW)
mbed_official	324:406fd2029f23	667	*
mbed_official	324:406fd2029f23	668	* Toggling SBK sends one break character from the following: See Transmitting
mbed_official	324:406fd2029f23	669	* break characters for the number of logic 0s for the different configurations.
mbed_official	324:406fd2029f23	670	* Toggling implies clearing the SBK field before the break character has finished
mbed_official	324:406fd2029f23	671	* transmitting. As long as SBK is set, the transmitter continues to send
mbed_official	324:406fd2029f23	672	* complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
mbed_official	324:406fd2029f23	673	* Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
mbed_official	324:406fd2029f23	674	* 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
mbed_official	324:406fd2029f23	675	* is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
mbed_official	324:406fd2029f23	676	* C7816[ISO_7816E] is set.
mbed_official	324:406fd2029f23	677	*
mbed_official	324:406fd2029f23	678	* Values:
mbed_official	324:406fd2029f23	679	* - 0 - Normal transmitter operation.
mbed_official	324:406fd2029f23	680	* - 1 - Queue break characters to be sent.
mbed_official	324:406fd2029f23	681	*/
mbed_official	324:406fd2029f23	682	/@{/
mbed_official	324:406fd2029f23	683	#define BP_UART_C2_SBK (0U) /!< Bit position for UART_C2_SBK. /
mbed_official	324:406fd2029f23	684	#define BM_UART_C2_SBK (0x01U) /!< Bit mask for UART_C2_SBK. /
mbed_official	324:406fd2029f23	685	#define BS_UART_C2_SBK (1U) /!< Bit field size in bits for UART_C2_SBK. /
mbed_official	324:406fd2029f23	686
mbed_official	324:406fd2029f23	687	/! @brief Read current value of the UART_C2_SBK field. /
mbed_official	324:406fd2029f23	688	#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
mbed_official	324:406fd2029f23	689
mbed_official	324:406fd2029f23	690	/! @brief Format value for bitfield UART_C2_SBK. /
mbed_official	324:406fd2029f23	691	#define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK)
mbed_official	324:406fd2029f23	692
mbed_official	324:406fd2029f23	693	/! @brief Set the SBK field to a new value. /
mbed_official	324:406fd2029f23	694	#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
mbed_official	324:406fd2029f23	695	/@}/
mbed_official	324:406fd2029f23	696
mbed_official	324:406fd2029f23	697	/*!
mbed_official	324:406fd2029f23	698	* @name Register UART_C2, field RWU[1] (RW)
mbed_official	324:406fd2029f23	699	*
mbed_official	324:406fd2029f23	700	* This field can be set to place the UART receiver in a standby state. RWU
mbed_official	324:406fd2029f23	701	* automatically clears when an RWU event occurs, that is, an IDLE event when
mbed_official	324:406fd2029f23	702	* C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
mbed_official	324:406fd2029f23	703	* cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
mbed_official	324:406fd2029f23	704	* on idle) if the channel is currently not idle. This can be determined by
mbed_official	324:406fd2029f23	705	* S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
mbed_official	324:406fd2029f23	706	* idle, it is possible that the UART will discard data. This is because the data
mbed_official	324:406fd2029f23	707	* must be received or a LIN break detected after an IDLE is detected before IDLE
mbed_official	324:406fd2029f23	708	* is allowed to reasserted.
mbed_official	324:406fd2029f23	709	*
mbed_official	324:406fd2029f23	710	* Values:
mbed_official	324:406fd2029f23	711	* - 0 - Normal operation.
mbed_official	324:406fd2029f23	712	* - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
mbed_official	324:406fd2029f23	713	* requests. Normally, hardware wakes the receiver by automatically clearing
mbed_official	324:406fd2029f23	714	* RWU.
mbed_official	324:406fd2029f23	715	*/
mbed_official	324:406fd2029f23	716	/@{/
mbed_official	324:406fd2029f23	717	#define BP_UART_C2_RWU (1U) /!< Bit position for UART_C2_RWU. /
mbed_official	324:406fd2029f23	718	#define BM_UART_C2_RWU (0x02U) /!< Bit mask for UART_C2_RWU. /
mbed_official	324:406fd2029f23	719	#define BS_UART_C2_RWU (1U) /!< Bit field size in bits for UART_C2_RWU. /
mbed_official	324:406fd2029f23	720
mbed_official	324:406fd2029f23	721	/! @brief Read current value of the UART_C2_RWU field. /
mbed_official	324:406fd2029f23	722	#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
mbed_official	324:406fd2029f23	723
mbed_official	324:406fd2029f23	724	/! @brief Format value for bitfield UART_C2_RWU. /
mbed_official	324:406fd2029f23	725	#define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU)
mbed_official	324:406fd2029f23	726
mbed_official	324:406fd2029f23	727	/! @brief Set the RWU field to a new value. /
mbed_official	324:406fd2029f23	728	#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
mbed_official	324:406fd2029f23	729	/@}/
mbed_official	324:406fd2029f23	730
mbed_official	324:406fd2029f23	731	/*!
mbed_official	324:406fd2029f23	732	* @name Register UART_C2, field RE[2] (RW)
mbed_official	324:406fd2029f23	733	*
mbed_official	324:406fd2029f23	734	* Enables the UART receiver.
mbed_official	324:406fd2029f23	735	*
mbed_official	324:406fd2029f23	736	* Values:
mbed_official	324:406fd2029f23	737	* - 0 - Receiver off.
mbed_official	324:406fd2029f23	738	* - 1 - Receiver on.
mbed_official	324:406fd2029f23	739	*/
mbed_official	324:406fd2029f23	740	/@{/
mbed_official	324:406fd2029f23	741	#define BP_UART_C2_RE (2U) /!< Bit position for UART_C2_RE. /
mbed_official	324:406fd2029f23	742	#define BM_UART_C2_RE (0x04U) /!< Bit mask for UART_C2_RE. /
mbed_official	324:406fd2029f23	743	#define BS_UART_C2_RE (1U) /!< Bit field size in bits for UART_C2_RE. /
mbed_official	324:406fd2029f23	744
mbed_official	324:406fd2029f23	745	/! @brief Read current value of the UART_C2_RE field. /
mbed_official	324:406fd2029f23	746	#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
mbed_official	324:406fd2029f23	747
mbed_official	324:406fd2029f23	748	/! @brief Format value for bitfield UART_C2_RE. /
mbed_official	324:406fd2029f23	749	#define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE)
mbed_official	324:406fd2029f23	750
mbed_official	324:406fd2029f23	751	/! @brief Set the RE field to a new value. /
mbed_official	324:406fd2029f23	752	#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
mbed_official	324:406fd2029f23	753	/@}/
mbed_official	324:406fd2029f23	754
mbed_official	324:406fd2029f23	755	/*!
mbed_official	324:406fd2029f23	756	* @name Register UART_C2, field TE[3] (RW)
mbed_official	324:406fd2029f23	757	*
mbed_official	324:406fd2029f23	758	* Enables the UART transmitter. TE can be used to queue an idle preamble by
mbed_official	324:406fd2029f23	759	* clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
mbed_official	324:406fd2029f23	760	* C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
mbed_official	324:406fd2029f23	761	* transmitted. This condition is detected when TL7816[TLEN] = 0 and four
mbed_official	324:406fd2029f23	762	* additional characters are transmitted.
mbed_official	324:406fd2029f23	763	*
mbed_official	324:406fd2029f23	764	* Values:
mbed_official	324:406fd2029f23	765	* - 0 - Transmitter off.
mbed_official	324:406fd2029f23	766	* - 1 - Transmitter on.
mbed_official	324:406fd2029f23	767	*/
mbed_official	324:406fd2029f23	768	/@{/
mbed_official	324:406fd2029f23	769	#define BP_UART_C2_TE (3U) /!< Bit position for UART_C2_TE. /
mbed_official	324:406fd2029f23	770	#define BM_UART_C2_TE (0x08U) /!< Bit mask for UART_C2_TE. /
mbed_official	324:406fd2029f23	771	#define BS_UART_C2_TE (1U) /!< Bit field size in bits for UART_C2_TE. /
mbed_official	324:406fd2029f23	772
mbed_official	324:406fd2029f23	773	/! @brief Read current value of the UART_C2_TE field. /
mbed_official	324:406fd2029f23	774	#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
mbed_official	324:406fd2029f23	775
mbed_official	324:406fd2029f23	776	/! @brief Format value for bitfield UART_C2_TE. /
mbed_official	324:406fd2029f23	777	#define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE)
mbed_official	324:406fd2029f23	778
mbed_official	324:406fd2029f23	779	/! @brief Set the TE field to a new value. /
mbed_official	324:406fd2029f23	780	#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
mbed_official	324:406fd2029f23	781	/@}/
mbed_official	324:406fd2029f23	782
mbed_official	324:406fd2029f23	783	/*!
mbed_official	324:406fd2029f23	784	* @name Register UART_C2, field ILIE[4] (RW)
mbed_official	324:406fd2029f23	785	*
mbed_official	324:406fd2029f23	786	* Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
mbed_official	324:406fd2029f23	787	* transfer requests based on the state of C5[ILDMAS].
mbed_official	324:406fd2029f23	788	*
mbed_official	324:406fd2029f23	789	* Values:
mbed_official	324:406fd2029f23	790	* - 0 - IDLE interrupt requests disabled. and DMA transfer
mbed_official	324:406fd2029f23	791	* - 1 - IDLE interrupt requests enabled. or DMA transfer
mbed_official	324:406fd2029f23	792	*/
mbed_official	324:406fd2029f23	793	/@{/
mbed_official	324:406fd2029f23	794	#define BP_UART_C2_ILIE (4U) /!< Bit position for UART_C2_ILIE. /
mbed_official	324:406fd2029f23	795	#define BM_UART_C2_ILIE (0x10U) /!< Bit mask for UART_C2_ILIE. /
mbed_official	324:406fd2029f23	796	#define BS_UART_C2_ILIE (1U) /!< Bit field size in bits for UART_C2_ILIE. /
mbed_official	324:406fd2029f23	797
mbed_official	324:406fd2029f23	798	/! @brief Read current value of the UART_C2_ILIE field. /
mbed_official	324:406fd2029f23	799	#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
mbed_official	324:406fd2029f23	800
mbed_official	324:406fd2029f23	801	/! @brief Format value for bitfield UART_C2_ILIE. /
mbed_official	324:406fd2029f23	802	#define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE)
mbed_official	324:406fd2029f23	803
mbed_official	324:406fd2029f23	804	/! @brief Set the ILIE field to a new value. /
mbed_official	324:406fd2029f23	805	#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
mbed_official	324:406fd2029f23	806	/@}/
mbed_official	324:406fd2029f23	807
mbed_official	324:406fd2029f23	808	/*!
mbed_official	324:406fd2029f23	809	* @name Register UART_C2, field RIE[5] (RW)
mbed_official	324:406fd2029f23	810	*
mbed_official	324:406fd2029f23	811	* Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
mbed_official	324:406fd2029f23	812	* based on the state of C5[RDMAS].
mbed_official	324:406fd2029f23	813	*
mbed_official	324:406fd2029f23	814	* Values:
mbed_official	324:406fd2029f23	815	* - 0 - RDRF interrupt and DMA transfer requests disabled.
mbed_official	324:406fd2029f23	816	* - 1 - RDRF interrupt or DMA transfer requests enabled.
mbed_official	324:406fd2029f23	817	*/
mbed_official	324:406fd2029f23	818	/@{/
mbed_official	324:406fd2029f23	819	#define BP_UART_C2_RIE (5U) /!< Bit position for UART_C2_RIE. /
mbed_official	324:406fd2029f23	820	#define BM_UART_C2_RIE (0x20U) /!< Bit mask for UART_C2_RIE. /
mbed_official	324:406fd2029f23	821	#define BS_UART_C2_RIE (1U) /!< Bit field size in bits for UART_C2_RIE. /
mbed_official	324:406fd2029f23	822
mbed_official	324:406fd2029f23	823	/! @brief Read current value of the UART_C2_RIE field. /
mbed_official	324:406fd2029f23	824	#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
mbed_official	324:406fd2029f23	825
mbed_official	324:406fd2029f23	826	/! @brief Format value for bitfield UART_C2_RIE. /
mbed_official	324:406fd2029f23	827	#define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE)
mbed_official	324:406fd2029f23	828
mbed_official	324:406fd2029f23	829	/! @brief Set the RIE field to a new value. /
mbed_official	324:406fd2029f23	830	#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
mbed_official	324:406fd2029f23	831	/@}/
mbed_official	324:406fd2029f23	832
mbed_official	324:406fd2029f23	833	/*!
mbed_official	324:406fd2029f23	834	* @name Register UART_C2, field TCIE[6] (RW)
mbed_official	324:406fd2029f23	835	*
mbed_official	324:406fd2029f23	836	* Enables the transmission complete flag, S1[TC], to generate interrupt
mbed_official	324:406fd2029f23	837	* requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
mbed_official	324:406fd2029f23	838	* C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
mbed_official	324:406fd2029f23	839	* written unless servicing a DMA request.
mbed_official	324:406fd2029f23	840	*
mbed_official	324:406fd2029f23	841	* Values:
mbed_official	324:406fd2029f23	842	* - 0 - TC interrupt and DMA transfer requests disabled.
mbed_official	324:406fd2029f23	843	* - 1 - TC interrupt or DMA transfer requests enabled.
mbed_official	324:406fd2029f23	844	*/
mbed_official	324:406fd2029f23	845	/@{/
mbed_official	324:406fd2029f23	846	#define BP_UART_C2_TCIE (6U) /!< Bit position for UART_C2_TCIE. /
mbed_official	324:406fd2029f23	847	#define BM_UART_C2_TCIE (0x40U) /!< Bit mask for UART_C2_TCIE. /
mbed_official	324:406fd2029f23	848	#define BS_UART_C2_TCIE (1U) /!< Bit field size in bits for UART_C2_TCIE. /
mbed_official	324:406fd2029f23	849
mbed_official	324:406fd2029f23	850	/! @brief Read current value of the UART_C2_TCIE field. /
mbed_official	324:406fd2029f23	851	#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
mbed_official	324:406fd2029f23	852
mbed_official	324:406fd2029f23	853	/! @brief Format value for bitfield UART_C2_TCIE. /
mbed_official	324:406fd2029f23	854	#define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE)
mbed_official	324:406fd2029f23	855
mbed_official	324:406fd2029f23	856	/! @brief Set the TCIE field to a new value. /
mbed_official	324:406fd2029f23	857	#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
mbed_official	324:406fd2029f23	858	/@}/
mbed_official	324:406fd2029f23	859
mbed_official	324:406fd2029f23	860	/*!
mbed_official	324:406fd2029f23	861	* @name Register UART_C2, field TIE[7] (RW)
mbed_official	324:406fd2029f23	862	*
mbed_official	324:406fd2029f23	863	* Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
mbed_official	324:406fd2029f23	864	* based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
mbed_official	324:406fd2029f23	865	* must be cleared, and D[D] must not be written unless servicing a DMA request.
mbed_official	324:406fd2029f23	866	*
mbed_official	324:406fd2029f23	867	* Values:
mbed_official	324:406fd2029f23	868	* - 0 - TDRE interrupt and DMA transfer requests disabled.
mbed_official	324:406fd2029f23	869	* - 1 - TDRE interrupt or DMA transfer requests enabled.
mbed_official	324:406fd2029f23	870	*/
mbed_official	324:406fd2029f23	871	/@{/
mbed_official	324:406fd2029f23	872	#define BP_UART_C2_TIE (7U) /!< Bit position for UART_C2_TIE. /
mbed_official	324:406fd2029f23	873	#define BM_UART_C2_TIE (0x80U) /!< Bit mask for UART_C2_TIE. /
mbed_official	324:406fd2029f23	874	#define BS_UART_C2_TIE (1U) /!< Bit field size in bits for UART_C2_TIE. /
mbed_official	324:406fd2029f23	875
mbed_official	324:406fd2029f23	876	/! @brief Read current value of the UART_C2_TIE field. /
mbed_official	324:406fd2029f23	877	#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
mbed_official	324:406fd2029f23	878
mbed_official	324:406fd2029f23	879	/! @brief Format value for bitfield UART_C2_TIE. /
mbed_official	324:406fd2029f23	880	#define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE)
mbed_official	324:406fd2029f23	881
mbed_official	324:406fd2029f23	882	/! @brief Set the TIE field to a new value. /
mbed_official	324:406fd2029f23	883	#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
mbed_official	324:406fd2029f23	884	/@}/
mbed_official	324:406fd2029f23	885
mbed_official	324:406fd2029f23	886	/*******************************************************************************
mbed_official	324:406fd2029f23	887	* HW_UART_S1 - UART Status Register 1
mbed_official	324:406fd2029f23	888	******************************************************************************/
mbed_official	324:406fd2029f23	889
mbed_official	324:406fd2029f23	890	/*!
mbed_official	324:406fd2029f23	891	* @brief HW_UART_S1 - UART Status Register 1 (RO)
mbed_official	324:406fd2029f23	892	*
mbed_official	324:406fd2029f23	893	* Reset value: 0xC0U
mbed_official	324:406fd2029f23	894	*
mbed_official	324:406fd2029f23	895	* The S1 register provides inputs to the MCU for generation of UART interrupts
mbed_official	324:406fd2029f23	896	* or DMA requests. This register can also be polled by the MCU to check the
mbed_official	324:406fd2029f23	897	* status of its fields. To clear a flag, the status register should be read followed
mbed_official	324:406fd2029f23	898	* by a read or write to D register, depending on the interrupt flag type. Other
mbed_official	324:406fd2029f23	899	* instructions can be executed between the two steps as long the handling of
mbed_official	324:406fd2029f23	900	* I/O is not compromised, but the order of operations is important for flag
mbed_official	324:406fd2029f23	901	* clearing. When a flag is configured to trigger a DMA request, assertion of the
mbed_official	324:406fd2029f23	902	* associated DMA done signal from the DMA controller clears the flag. If the
mbed_official	324:406fd2029f23	903	* condition that results in the assertion of the flag, interrupt, or DMA request is not
mbed_official	324:406fd2029f23	904	* resolved prior to clearing the flag, the flag, and interrupt/DMA request,
mbed_official	324:406fd2029f23	905	* reasserts. For example, if the DMA or interrupt service routine fails to write
mbed_official	324:406fd2029f23	906	* sufficient data to the transmit buffer to raise it above the watermark level, the
mbed_official	324:406fd2029f23	907	* flag reasserts and generates another interrupt or DMA request. Reading an
mbed_official	324:406fd2029f23	908	* empty data register to clear one of the flags of the S1 register causes the FIFO
mbed_official	324:406fd2029f23	909	* pointers to become misaligned. A receive FIFO flush reinitializes the
mbed_official	324:406fd2029f23	910	* pointers. A better way to prevent this situation is to always leave one byte in FIFO
mbed_official	324:406fd2029f23	911	* and this byte will be read eventually in clearing the flag bit.
mbed_official	324:406fd2029f23	912	*/
mbed_official	324:406fd2029f23	913	typedef union _hw_uart_s1
mbed_official	324:406fd2029f23	914	{
mbed_official	324:406fd2029f23	915	uint8_t U;
mbed_official	324:406fd2029f23	916	struct _hw_uart_s1_bitfields
mbed_official	324:406fd2029f23	917	{
mbed_official	324:406fd2029f23	918	uint8_t PF : 1; /!< [0] Parity Error Flag /
mbed_official	324:406fd2029f23	919	uint8_t FE : 1; /!< [1] Framing Error Flag /
mbed_official	324:406fd2029f23	920	uint8_t NF : 1; /!< [2] Noise Flag /
mbed_official	324:406fd2029f23	921	uint8_t OR : 1; /!< [3] Receiver Overrun Flag /
mbed_official	324:406fd2029f23	922	uint8_t IDLE : 1; /!< [4] Idle Line Flag /
mbed_official	324:406fd2029f23	923	uint8_t RDRF : 1; /!< [5] Receive Data Register Full Flag /
mbed_official	324:406fd2029f23	924	uint8_t TC : 1; /!< [6] Transmit Complete Flag /
mbed_official	324:406fd2029f23	925	uint8_t TDRE : 1; /!< [7] Transmit Data Register Empty Flag /
mbed_official	324:406fd2029f23	926	} B;
mbed_official	324:406fd2029f23	927	} hw_uart_s1_t;
mbed_official	324:406fd2029f23	928
mbed_official	324:406fd2029f23	929	/*!
mbed_official	324:406fd2029f23	930	* @name Constants and macros for entire UART_S1 register
mbed_official	324:406fd2029f23	931	*/
mbed_official	324:406fd2029f23	932	/@{/
mbed_official	324:406fd2029f23	933	#define HW_UART_S1_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	934
mbed_official	324:406fd2029f23	935	#define HW_UART_S1(x) ((__I hw_uart_s1_t ) HW_UART_S1_ADDR(x))
mbed_official	324:406fd2029f23	936	#define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
mbed_official	324:406fd2029f23	937	/@}/
mbed_official	324:406fd2029f23	938
mbed_official	324:406fd2029f23	939	/*
mbed_official	324:406fd2029f23	940	* Constants & macros for individual UART_S1 bitfields
mbed_official	324:406fd2029f23	941	*/
mbed_official	324:406fd2029f23	942
mbed_official	324:406fd2029f23	943	/*!
mbed_official	324:406fd2029f23	944	* @name Register UART_S1, field PF[0] (RO)
mbed_official	324:406fd2029f23	945	*
mbed_official	324:406fd2029f23	946	* PF is set when PE is set and the parity of the received data does not match
mbed_official	324:406fd2029f23	947	* its parity bit. The PF is not set in the case of an overrun condition. When PF
mbed_official	324:406fd2029f23	948	* is set, it indicates only that a dataword was received with parity error since
mbed_official	324:406fd2029f23	949	* the last time it was cleared. There is no guarantee that the first dataword
mbed_official	324:406fd2029f23	950	* read from the receive buffer has a parity error or that there is only one
mbed_official	324:406fd2029f23	951	* dataword in the buffer that was received with a parity error, unless the receive
mbed_official	324:406fd2029f23	952	* buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
mbed_official	324:406fd2029f23	953	* disabled, Within the receive buffer structure the received dataword is tagged
mbed_official	324:406fd2029f23	954	* if it is received with a parity error. This information is available by reading
mbed_official	324:406fd2029f23	955	* the ED register prior to reading the D register.
mbed_official	324:406fd2029f23	956	*
mbed_official	324:406fd2029f23	957	* Values:
mbed_official	324:406fd2029f23	958	* - 0 - No parity error detected since the last time this flag was cleared. If
mbed_official	324:406fd2029f23	959	* the receive buffer has a depth greater than 1, then there may be data in
mbed_official	324:406fd2029f23	960	* the receive buffer what was received with a parity error.
mbed_official	324:406fd2029f23	961	* - 1 - At least one dataword was received with a parity error since the last
mbed_official	324:406fd2029f23	962	* time this flag was cleared.
mbed_official	324:406fd2029f23	963	*/
mbed_official	324:406fd2029f23	964	/@{/
mbed_official	324:406fd2029f23	965	#define BP_UART_S1_PF (0U) /!< Bit position for UART_S1_PF. /
mbed_official	324:406fd2029f23	966	#define BM_UART_S1_PF (0x01U) /!< Bit mask for UART_S1_PF. /
mbed_official	324:406fd2029f23	967	#define BS_UART_S1_PF (1U) /!< Bit field size in bits for UART_S1_PF. /
mbed_official	324:406fd2029f23	968
mbed_official	324:406fd2029f23	969	/! @brief Read current value of the UART_S1_PF field. /
mbed_official	324:406fd2029f23	970	#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
mbed_official	324:406fd2029f23	971	/@}/
mbed_official	324:406fd2029f23	972
mbed_official	324:406fd2029f23	973	/*!
mbed_official	324:406fd2029f23	974	* @name Register UART_S1, field FE[1] (RO)
mbed_official	324:406fd2029f23	975	*
mbed_official	324:406fd2029f23	976	* FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
mbed_official	324:406fd2029f23	977	* then FE will set when a logic 0 is accepted for either of the two stop bits.
mbed_official	324:406fd2029f23	978	* FE does not set in the case of an overrun or while the LIN break detect feature
mbed_official	324:406fd2029f23	979	* is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
mbed_official	324:406fd2029f23	980	* cleared. To clear FE, read S1 with FE set and then read D. The last data in the
mbed_official	324:406fd2029f23	981	* receive buffer represents the data that was received with the frame error
mbed_official	324:406fd2029f23	982	* enabled. Framing errors are not supported when 7816E is set/enabled. However, if
mbed_official	324:406fd2029f23	983	* this flag is set, data is still not received in 7816 mode.
mbed_official	324:406fd2029f23	984	*
mbed_official	324:406fd2029f23	985	* Values:
mbed_official	324:406fd2029f23	986	* - 0 - No framing error detected.
mbed_official	324:406fd2029f23	987	* - 1 - Framing error.
mbed_official	324:406fd2029f23	988	*/
mbed_official	324:406fd2029f23	989	/@{/
mbed_official	324:406fd2029f23	990	#define BP_UART_S1_FE (1U) /!< Bit position for UART_S1_FE. /
mbed_official	324:406fd2029f23	991	#define BM_UART_S1_FE (0x02U) /!< Bit mask for UART_S1_FE. /
mbed_official	324:406fd2029f23	992	#define BS_UART_S1_FE (1U) /!< Bit field size in bits for UART_S1_FE. /
mbed_official	324:406fd2029f23	993
mbed_official	324:406fd2029f23	994	/! @brief Read current value of the UART_S1_FE field. /
mbed_official	324:406fd2029f23	995	#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
mbed_official	324:406fd2029f23	996	/@}/
mbed_official	324:406fd2029f23	997
mbed_official	324:406fd2029f23	998	/*!
mbed_official	324:406fd2029f23	999	* @name Register UART_S1, field NF[2] (RO)
mbed_official	324:406fd2029f23	1000	*
mbed_official	324:406fd2029f23	1001	* NF is set when the UART detects noise on the receiver input. NF does not
mbed_official	324:406fd2029f23	1002	* become set in the case of an overrun or while the LIN break detect feature is
mbed_official	324:406fd2029f23	1003	* enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
mbed_official	324:406fd2029f23	1004	* been received with noise since the last time it was cleared. There is no
mbed_official	324:406fd2029f23	1005	* guarantee that the first dataword read from the receive buffer has noise or that there
mbed_official	324:406fd2029f23	1006	* is only one dataword in the buffer that was received with noise unless the
mbed_official	324:406fd2029f23	1007	* receive buffer has a depth of one. To clear NF, read S1 and then read D.
mbed_official	324:406fd2029f23	1008	*
mbed_official	324:406fd2029f23	1009	* Values:
mbed_official	324:406fd2029f23	1010	* - 0 - No noise detected since the last time this flag was cleared. If the
mbed_official	324:406fd2029f23	1011	* receive buffer has a depth greater than 1 then there may be data in the
mbed_official	324:406fd2029f23	1012	* receiver buffer that was received with noise.
mbed_official	324:406fd2029f23	1013	* - 1 - At least one dataword was received with noise detected since the last
mbed_official	324:406fd2029f23	1014	* time the flag was cleared.
mbed_official	324:406fd2029f23	1015	*/
mbed_official	324:406fd2029f23	1016	/@{/
mbed_official	324:406fd2029f23	1017	#define BP_UART_S1_NF (2U) /!< Bit position for UART_S1_NF. /
mbed_official	324:406fd2029f23	1018	#define BM_UART_S1_NF (0x04U) /!< Bit mask for UART_S1_NF. /
mbed_official	324:406fd2029f23	1019	#define BS_UART_S1_NF (1U) /!< Bit field size in bits for UART_S1_NF. /
mbed_official	324:406fd2029f23	1020
mbed_official	324:406fd2029f23	1021	/! @brief Read current value of the UART_S1_NF field. /
mbed_official	324:406fd2029f23	1022	#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
mbed_official	324:406fd2029f23	1023	/@}/
mbed_official	324:406fd2029f23	1024
mbed_official	324:406fd2029f23	1025	/*!
mbed_official	324:406fd2029f23	1026	* @name Register UART_S1, field OR[3] (RO)
mbed_official	324:406fd2029f23	1027	*
mbed_official	324:406fd2029f23	1028	* OR is set when software fails to prevent the receive data register from
mbed_official	324:406fd2029f23	1029	* overflowing with data. The OR bit is set immediately after the stop bit has been
mbed_official	324:406fd2029f23	1030	* completely received for the dataword that overflows the buffer and all the other
mbed_official	324:406fd2029f23	1031	* error flags (FE, NF, and PF) are prevented from setting. The data in the
mbed_official	324:406fd2029f23	1032	* shift register is lost, but the data already in the UART data registers is not
mbed_official	324:406fd2029f23	1033	* affected. If the OR flag is set, no data is stored in the data buffer even if
mbed_official	324:406fd2029f23	1034	* sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
mbed_official	324:406fd2029f23	1035	* flags are blocked from asserting, that is, transition from an inactive to an
mbed_official	324:406fd2029f23	1036	* active state. To clear OR, read S1 when OR is set and then read D. See
mbed_official	324:406fd2029f23	1037	* functional description for more details regarding the operation of the OR bit.If
mbed_official	324:406fd2029f23	1038	* LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
mbed_official	324:406fd2029f23	1039	* is not cleared before the next data character is received. In 7816 mode, it is
mbed_official	324:406fd2029f23	1040	* possible to configure a NACK to be returned by programing C7816[ONACK].
mbed_official	324:406fd2029f23	1041	*
mbed_official	324:406fd2029f23	1042	* Values:
mbed_official	324:406fd2029f23	1043	* - 0 - No overrun has occurred since the last time the flag was cleared.
mbed_official	324:406fd2029f23	1044	* - 1 - Overrun has occurred or the overrun flag has not been cleared since the
mbed_official	324:406fd2029f23	1045	* last overrun occured.
mbed_official	324:406fd2029f23	1046	*/
mbed_official	324:406fd2029f23	1047	/@{/
mbed_official	324:406fd2029f23	1048	#define BP_UART_S1_OR (3U) /!< Bit position for UART_S1_OR. /
mbed_official	324:406fd2029f23	1049	#define BM_UART_S1_OR (0x08U) /!< Bit mask for UART_S1_OR. /
mbed_official	324:406fd2029f23	1050	#define BS_UART_S1_OR (1U) /!< Bit field size in bits for UART_S1_OR. /
mbed_official	324:406fd2029f23	1051
mbed_official	324:406fd2029f23	1052	/! @brief Read current value of the UART_S1_OR field. /
mbed_official	324:406fd2029f23	1053	#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
mbed_official	324:406fd2029f23	1054	/@}/
mbed_official	324:406fd2029f23	1055
mbed_official	324:406fd2029f23	1056	/*!
mbed_official	324:406fd2029f23	1057	* @name Register UART_S1, field IDLE[4] (RO)
mbed_official	324:406fd2029f23	1058	*
mbed_official	324:406fd2029f23	1059	* After the IDLE flag is cleared, a frame must be received (although not
mbed_official	324:406fd2029f23	1060	* necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
mbed_official	324:406fd2029f23	1061	* break character must set the S2[LBKDIF] flag before an idle condition can set the
mbed_official	324:406fd2029f23	1062	* IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
mbed_official	324:406fd2029f23	1063	* IDLE is set when either of the following appear on the receiver input: 10
mbed_official	324:406fd2029f23	1064	* consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
mbed_official	324:406fd2029f23	1065	* = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
mbed_official	324:406fd2029f23	1066	* detection is not supported when 7816E is set/enabled and hence this flag is
mbed_official	324:406fd2029f23	1067	* ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
mbed_official	324:406fd2029f23	1068	* flag if RWUID is set, else the IDLE flag does not become set.
mbed_official	324:406fd2029f23	1069	*
mbed_official	324:406fd2029f23	1070	* Values:
mbed_official	324:406fd2029f23	1071	* - 0 - Receiver input is either active now or has never become active since
mbed_official	324:406fd2029f23	1072	* the IDLE flag was last cleared.
mbed_official	324:406fd2029f23	1073	* - 1 - Receiver input has become idle or the flag has not been cleared since
mbed_official	324:406fd2029f23	1074	* it last asserted.
mbed_official	324:406fd2029f23	1075	*/
mbed_official	324:406fd2029f23	1076	/@{/
mbed_official	324:406fd2029f23	1077	#define BP_UART_S1_IDLE (4U) /!< Bit position for UART_S1_IDLE. /
mbed_official	324:406fd2029f23	1078	#define BM_UART_S1_IDLE (0x10U) /!< Bit mask for UART_S1_IDLE. /
mbed_official	324:406fd2029f23	1079	#define BS_UART_S1_IDLE (1U) /!< Bit field size in bits for UART_S1_IDLE. /
mbed_official	324:406fd2029f23	1080
mbed_official	324:406fd2029f23	1081	/! @brief Read current value of the UART_S1_IDLE field. /
mbed_official	324:406fd2029f23	1082	#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
mbed_official	324:406fd2029f23	1083	/@}/
mbed_official	324:406fd2029f23	1084
mbed_official	324:406fd2029f23	1085	/*!
mbed_official	324:406fd2029f23	1086	* @name Register UART_S1, field RDRF[5] (RO)
mbed_official	324:406fd2029f23	1087	*
mbed_official	324:406fd2029f23	1088	* RDRF is set when the number of datawords in the receive buffer is equal to or
mbed_official	324:406fd2029f23	1089	* more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
mbed_official	324:406fd2029f23	1090	* process of being received is not included in the count. To clear RDRF, read S1
mbed_official	324:406fd2029f23	1091	* when RDRF is set and then read D. For more efficient interrupt and DMA
mbed_official	324:406fd2029f23	1092	* operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
mbed_official	324:406fd2029f23	1093	* Then read S1 and the final data value, resulting in the clearing of the RDRF
mbed_official	324:406fd2029f23	1094	* flag. Even if RDRF is set, data will continue to be received until an overrun
mbed_official	324:406fd2029f23	1095	* condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
mbed_official	324:406fd2029f23	1096	* Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
mbed_official	324:406fd2029f23	1097	* buffer but over-write each other.
mbed_official	324:406fd2029f23	1098	*
mbed_official	324:406fd2029f23	1099	* Values:
mbed_official	324:406fd2029f23	1100	* - 0 - The number of datawords in the receive buffer is less than the number
mbed_official	324:406fd2029f23	1101	* indicated by RXWATER.
mbed_official	324:406fd2029f23	1102	* - 1 - The number of datawords in the receive buffer is equal to or greater
mbed_official	324:406fd2029f23	1103	* than the number indicated by RXWATER at some point in time since this flag
mbed_official	324:406fd2029f23	1104	* was last cleared.
mbed_official	324:406fd2029f23	1105	*/
mbed_official	324:406fd2029f23	1106	/@{/
mbed_official	324:406fd2029f23	1107	#define BP_UART_S1_RDRF (5U) /!< Bit position for UART_S1_RDRF. /
mbed_official	324:406fd2029f23	1108	#define BM_UART_S1_RDRF (0x20U) /!< Bit mask for UART_S1_RDRF. /
mbed_official	324:406fd2029f23	1109	#define BS_UART_S1_RDRF (1U) /!< Bit field size in bits for UART_S1_RDRF. /
mbed_official	324:406fd2029f23	1110
mbed_official	324:406fd2029f23	1111	/! @brief Read current value of the UART_S1_RDRF field. /
mbed_official	324:406fd2029f23	1112	#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
mbed_official	324:406fd2029f23	1113	/@}/
mbed_official	324:406fd2029f23	1114
mbed_official	324:406fd2029f23	1115	/*!
mbed_official	324:406fd2029f23	1116	* @name Register UART_S1, field TC[6] (RO)
mbed_official	324:406fd2029f23	1117	*
mbed_official	324:406fd2029f23	1118	* TC is set when the transmit buffer is empty and no data, preamble, or break
mbed_official	324:406fd2029f23	1119	* character is being transmitted. When TC is set, the transmit data output signal
mbed_official	324:406fd2029f23	1120	* becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
mbed_official	324:406fd2029f23	1121	* doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
mbed_official	324:406fd2029f23	1122	* set after any NACK signal has been received, but prior to any corresponding
mbed_official	324:406fd2029f23	1123	* guard times expiring. Writing to D to transmit new data. Queuing a preamble by
mbed_official	324:406fd2029f23	1124	* clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
mbed_official	324:406fd2029f23	1125	* in C2.
mbed_official	324:406fd2029f23	1126	*
mbed_official	324:406fd2029f23	1127	* Values:
mbed_official	324:406fd2029f23	1128	* - 0 - Transmitter active (sending data, a preamble, or a break).
mbed_official	324:406fd2029f23	1129	* - 1 - Transmitter idle (transmission activity complete).
mbed_official	324:406fd2029f23	1130	*/
mbed_official	324:406fd2029f23	1131	/@{/
mbed_official	324:406fd2029f23	1132	#define BP_UART_S1_TC (6U) /!< Bit position for UART_S1_TC. /
mbed_official	324:406fd2029f23	1133	#define BM_UART_S1_TC (0x40U) /!< Bit mask for UART_S1_TC. /
mbed_official	324:406fd2029f23	1134	#define BS_UART_S1_TC (1U) /!< Bit field size in bits for UART_S1_TC. /
mbed_official	324:406fd2029f23	1135
mbed_official	324:406fd2029f23	1136	/! @brief Read current value of the UART_S1_TC field. /
mbed_official	324:406fd2029f23	1137	#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
mbed_official	324:406fd2029f23	1138	/@}/
mbed_official	324:406fd2029f23	1139
mbed_official	324:406fd2029f23	1140	/*!
mbed_official	324:406fd2029f23	1141	* @name Register UART_S1, field TDRE[7] (RO)
mbed_official	324:406fd2029f23	1142	*
mbed_official	324:406fd2029f23	1143	* TDRE will set when the number of datawords in the transmit buffer (D and
mbed_official	324:406fd2029f23	1144	* C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
mbed_official	324:406fd2029f23	1145	* character that is in the process of being transmitted is not included in the count.
mbed_official	324:406fd2029f23	1146	* To clear TDRE, read S1 when TDRE is set and then write to the UART data
mbed_official	324:406fd2029f23	1147	* register (D). For more efficient interrupt servicing, all data except the final value
mbed_official	324:406fd2029f23	1148	* to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
mbed_official	324:406fd2029f23	1149	* before writing the final data value, resulting in the clearing of the TRDE
mbed_official	324:406fd2029f23	1150	* flag. This is more efficient because the TDRE reasserts until the watermark has
mbed_official	324:406fd2029f23	1151	* been exceeded. So, attempting to clear the TDRE with every write will be
mbed_official	324:406fd2029f23	1152	* ineffective until sufficient data has been written.
mbed_official	324:406fd2029f23	1153	*
mbed_official	324:406fd2029f23	1154	* Values:
mbed_official	324:406fd2029f23	1155	* - 0 - The amount of data in the transmit buffer is greater than the value
mbed_official	324:406fd2029f23	1156	* indicated by TWFIFO[TXWATER].
mbed_official	324:406fd2029f23	1157	* - 1 - The amount of data in the transmit buffer is less than or equal to the
mbed_official	324:406fd2029f23	1158	* value indicated by TWFIFO[TXWATER] at some point in time since the flag
mbed_official	324:406fd2029f23	1159	* has been cleared.
mbed_official	324:406fd2029f23	1160	*/
mbed_official	324:406fd2029f23	1161	/@{/
mbed_official	324:406fd2029f23	1162	#define BP_UART_S1_TDRE (7U) /!< Bit position for UART_S1_TDRE. /
mbed_official	324:406fd2029f23	1163	#define BM_UART_S1_TDRE (0x80U) /!< Bit mask for UART_S1_TDRE. /
mbed_official	324:406fd2029f23	1164	#define BS_UART_S1_TDRE (1U) /!< Bit field size in bits for UART_S1_TDRE. /
mbed_official	324:406fd2029f23	1165
mbed_official	324:406fd2029f23	1166	/! @brief Read current value of the UART_S1_TDRE field. /
mbed_official	324:406fd2029f23	1167	#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
mbed_official	324:406fd2029f23	1168	/@}/
mbed_official	324:406fd2029f23	1169
mbed_official	324:406fd2029f23	1170	/*******************************************************************************
mbed_official	324:406fd2029f23	1171	* HW_UART_S2 - UART Status Register 2
mbed_official	324:406fd2029f23	1172	******************************************************************************/
mbed_official	324:406fd2029f23	1173
mbed_official	324:406fd2029f23	1174	/*!
mbed_official	324:406fd2029f23	1175	* @brief HW_UART_S2 - UART Status Register 2 (RW)
mbed_official	324:406fd2029f23	1176	*
mbed_official	324:406fd2029f23	1177	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1178	*
mbed_official	324:406fd2029f23	1179	* The S2 register provides inputs to the MCU for generation of UART interrupts
mbed_official	324:406fd2029f23	1180	* or DMA requests. Also, this register can be polled by the MCU to check the
mbed_official	324:406fd2029f23	1181	* status of these bits. This register can be read or written at any time, with the
mbed_official	324:406fd2029f23	1182	* exception of the MSBF and RXINV bits, which should be changed by the user only
mbed_official	324:406fd2029f23	1183	* between transmit and receive packets.
mbed_official	324:406fd2029f23	1184	*/
mbed_official	324:406fd2029f23	1185	typedef union _hw_uart_s2
mbed_official	324:406fd2029f23	1186	{
mbed_official	324:406fd2029f23	1187	uint8_t U;
mbed_official	324:406fd2029f23	1188	struct _hw_uart_s2_bitfields
mbed_official	324:406fd2029f23	1189	{
mbed_official	324:406fd2029f23	1190	uint8_t RAF : 1; /!< [0] Receiver Active Flag /
mbed_official	324:406fd2029f23	1191	uint8_t LBKDE : 1; /!< [1] LIN Break Detection Enable /
mbed_official	324:406fd2029f23	1192	uint8_t BRK13 : 1; /!< [2] Break Transmit Character Length /
mbed_official	324:406fd2029f23	1193	uint8_t RWUID : 1; /!< [3] Receive Wakeup Idle Detect /
mbed_official	324:406fd2029f23	1194	uint8_t RXINV : 1; /!< [4] Receive Data Inversion /
mbed_official	324:406fd2029f23	1195	uint8_t MSBF : 1; /!< [5] Most Significant Bit First /
mbed_official	324:406fd2029f23	1196	uint8_t RXEDGIF : 1; /!< [6] RxD Pin Active Edge Interrupt Flag /
mbed_official	324:406fd2029f23	1197	uint8_t LBKDIF : 1; /!< [7] LIN Break Detect Interrupt Flag /
mbed_official	324:406fd2029f23	1198	} B;
mbed_official	324:406fd2029f23	1199	} hw_uart_s2_t;
mbed_official	324:406fd2029f23	1200
mbed_official	324:406fd2029f23	1201	/*!
mbed_official	324:406fd2029f23	1202	* @name Constants and macros for entire UART_S2 register
mbed_official	324:406fd2029f23	1203	*/
mbed_official	324:406fd2029f23	1204	/@{/
mbed_official	324:406fd2029f23	1205	#define HW_UART_S2_ADDR(x) ((x) + 0x5U)
mbed_official	324:406fd2029f23	1206
mbed_official	324:406fd2029f23	1207	#define HW_UART_S2(x) ((__IO hw_uart_s2_t ) HW_UART_S2_ADDR(x))
mbed_official	324:406fd2029f23	1208	#define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
mbed_official	324:406fd2029f23	1209	#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
mbed_official	324:406fd2029f23	1210	#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1211	#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1212	#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1213	/@}/
mbed_official	324:406fd2029f23	1214
mbed_official	324:406fd2029f23	1215	/*
mbed_official	324:406fd2029f23	1216	* Constants & macros for individual UART_S2 bitfields
mbed_official	324:406fd2029f23	1217	*/
mbed_official	324:406fd2029f23	1218
mbed_official	324:406fd2029f23	1219	/*!
mbed_official	324:406fd2029f23	1220	* @name Register UART_S2, field RAF[0] (RO)
mbed_official	324:406fd2029f23	1221	*
mbed_official	324:406fd2029f23	1222	* RAF is set when the UART receiver detects a logic 0 during the RT1 time
mbed_official	324:406fd2029f23	1223	* period of the start bit search. RAF is cleared when the receiver detects an idle
mbed_official	324:406fd2029f23	1224	* character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
mbed_official	324:406fd2029f23	1225	* enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
mbed_official	324:406fd2029f23	1226	* 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
mbed_official	324:406fd2029f23	1227	* to configure the guard time to 12. However, if a NACK is required to be
mbed_official	324:406fd2029f23	1228	* transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
mbed_official	324:406fd2029f23	1229	* inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
mbed_official	324:406fd2029f23	1230	* prior to actually being inactive.
mbed_official	324:406fd2029f23	1231	*
mbed_official	324:406fd2029f23	1232	* Values:
mbed_official	324:406fd2029f23	1233	* - 0 - UART receiver idle/inactive waiting for a start bit.
mbed_official	324:406fd2029f23	1234	* - 1 - UART receiver active, RxD input not idle.
mbed_official	324:406fd2029f23	1235	*/
mbed_official	324:406fd2029f23	1236	/@{/
mbed_official	324:406fd2029f23	1237	#define BP_UART_S2_RAF (0U) /!< Bit position for UART_S2_RAF. /
mbed_official	324:406fd2029f23	1238	#define BM_UART_S2_RAF (0x01U) /!< Bit mask for UART_S2_RAF. /
mbed_official	324:406fd2029f23	1239	#define BS_UART_S2_RAF (1U) /!< Bit field size in bits for UART_S2_RAF. /
mbed_official	324:406fd2029f23	1240
mbed_official	324:406fd2029f23	1241	/! @brief Read current value of the UART_S2_RAF field. /
mbed_official	324:406fd2029f23	1242	#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
mbed_official	324:406fd2029f23	1243	/@}/
mbed_official	324:406fd2029f23	1244
mbed_official	324:406fd2029f23	1245	/*!
mbed_official	324:406fd2029f23	1246	* @name Register UART_S2, field LBKDE[1] (RW)
mbed_official	324:406fd2029f23	1247	*
mbed_official	324:406fd2029f23	1248	* Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
mbed_official	324:406fd2029f23	1249	* S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
mbed_official	324:406fd2029f23	1250	* Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
mbed_official	324:406fd2029f23	1251	*
mbed_official	324:406fd2029f23	1252	* Values:
mbed_official	324:406fd2029f23	1253	* - 0 - Break character detection is disabled.
mbed_official	324:406fd2029f23	1254	* - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
mbed_official	324:406fd2029f23	1255	* 12 bits time if C1[M] = 1.
mbed_official	324:406fd2029f23	1256	*/
mbed_official	324:406fd2029f23	1257	/@{/
mbed_official	324:406fd2029f23	1258	#define BP_UART_S2_LBKDE (1U) /!< Bit position for UART_S2_LBKDE. /
mbed_official	324:406fd2029f23	1259	#define BM_UART_S2_LBKDE (0x02U) /!< Bit mask for UART_S2_LBKDE. /
mbed_official	324:406fd2029f23	1260	#define BS_UART_S2_LBKDE (1U) /!< Bit field size in bits for UART_S2_LBKDE. /
mbed_official	324:406fd2029f23	1261
mbed_official	324:406fd2029f23	1262	/! @brief Read current value of the UART_S2_LBKDE field. /
mbed_official	324:406fd2029f23	1263	#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
mbed_official	324:406fd2029f23	1264
mbed_official	324:406fd2029f23	1265	/! @brief Format value for bitfield UART_S2_LBKDE. /
mbed_official	324:406fd2029f23	1266	#define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE)
mbed_official	324:406fd2029f23	1267
mbed_official	324:406fd2029f23	1268	/! @brief Set the LBKDE field to a new value. /
mbed_official	324:406fd2029f23	1269	#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
mbed_official	324:406fd2029f23	1270	/@}/
mbed_official	324:406fd2029f23	1271
mbed_official	324:406fd2029f23	1272	/*!
mbed_official	324:406fd2029f23	1273	* @name Register UART_S2, field BRK13[2] (RW)
mbed_official	324:406fd2029f23	1274	*
mbed_official	324:406fd2029f23	1275	* Determines whether the transmit break character is 10, 11, or 12 bits long,
mbed_official	324:406fd2029f23	1276	* or 13 or 14 bits long. See for the length of the break character for the
mbed_official	324:406fd2029f23	1277	* different configurations. The detection of a framing error is not affected by this
mbed_official	324:406fd2029f23	1278	* field. Transmitting break characters
mbed_official	324:406fd2029f23	1279	*
mbed_official	324:406fd2029f23	1280	* Values:
mbed_official	324:406fd2029f23	1281	* - 0 - Break character is 10, 11, or 12 bits long.
mbed_official	324:406fd2029f23	1282	* - 1 - Break character is 13 or 14 bits long.
mbed_official	324:406fd2029f23	1283	*/
mbed_official	324:406fd2029f23	1284	/@{/
mbed_official	324:406fd2029f23	1285	#define BP_UART_S2_BRK13 (2U) /!< Bit position for UART_S2_BRK13. /
mbed_official	324:406fd2029f23	1286	#define BM_UART_S2_BRK13 (0x04U) /!< Bit mask for UART_S2_BRK13. /
mbed_official	324:406fd2029f23	1287	#define BS_UART_S2_BRK13 (1U) /!< Bit field size in bits for UART_S2_BRK13. /
mbed_official	324:406fd2029f23	1288
mbed_official	324:406fd2029f23	1289	/! @brief Read current value of the UART_S2_BRK13 field. /
mbed_official	324:406fd2029f23	1290	#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
mbed_official	324:406fd2029f23	1291
mbed_official	324:406fd2029f23	1292	/! @brief Format value for bitfield UART_S2_BRK13. /
mbed_official	324:406fd2029f23	1293	#define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13)
mbed_official	324:406fd2029f23	1294
mbed_official	324:406fd2029f23	1295	/! @brief Set the BRK13 field to a new value. /
mbed_official	324:406fd2029f23	1296	#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
mbed_official	324:406fd2029f23	1297	/@}/
mbed_official	324:406fd2029f23	1298
mbed_official	324:406fd2029f23	1299	/*!
mbed_official	324:406fd2029f23	1300	* @name Register UART_S2, field RWUID[3] (RW)
mbed_official	324:406fd2029f23	1301	*
mbed_official	324:406fd2029f23	1302	* When RWU is set and WAKE is cleared, this field controls whether the idle
mbed_official	324:406fd2029f23	1303	* character that wakes the receiver sets S1[IDLE]. This field must be cleared when
mbed_official	324:406fd2029f23	1304	* C7816[ISO7816E] is set/enabled.
mbed_official	324:406fd2029f23	1305	*
mbed_official	324:406fd2029f23	1306	* Values:
mbed_official	324:406fd2029f23	1307	* - 0 - S1[IDLE] is not set upon detection of an idle character.
mbed_official	324:406fd2029f23	1308	* - 1 - S1[IDLE] is set upon detection of an idle character.
mbed_official	324:406fd2029f23	1309	*/
mbed_official	324:406fd2029f23	1310	/@{/
mbed_official	324:406fd2029f23	1311	#define BP_UART_S2_RWUID (3U) /!< Bit position for UART_S2_RWUID. /
mbed_official	324:406fd2029f23	1312	#define BM_UART_S2_RWUID (0x08U) /!< Bit mask for UART_S2_RWUID. /
mbed_official	324:406fd2029f23	1313	#define BS_UART_S2_RWUID (1U) /!< Bit field size in bits for UART_S2_RWUID. /
mbed_official	324:406fd2029f23	1314
mbed_official	324:406fd2029f23	1315	/! @brief Read current value of the UART_S2_RWUID field. /
mbed_official	324:406fd2029f23	1316	#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
mbed_official	324:406fd2029f23	1317
mbed_official	324:406fd2029f23	1318	/! @brief Format value for bitfield UART_S2_RWUID. /
mbed_official	324:406fd2029f23	1319	#define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID)
mbed_official	324:406fd2029f23	1320
mbed_official	324:406fd2029f23	1321	/! @brief Set the RWUID field to a new value. /
mbed_official	324:406fd2029f23	1322	#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
mbed_official	324:406fd2029f23	1323	/@}/
mbed_official	324:406fd2029f23	1324
mbed_official	324:406fd2029f23	1325	/*!
mbed_official	324:406fd2029f23	1326	* @name Register UART_S2, field RXINV[4] (RW)
mbed_official	324:406fd2029f23	1327	*
mbed_official	324:406fd2029f23	1328	* Setting this field reverses the polarity of the received data input. In NRZ
mbed_official	324:406fd2029f23	1329	* format, a one is represented by a mark and a zero is represented by a space for
mbed_official	324:406fd2029f23	1330	* normal polarity, and the opposite for inverted polarity. In IrDA format, a
mbed_official	324:406fd2029f23	1331	* zero is represented by short high pulse in the middle of a bit time remaining
mbed_official	324:406fd2029f23	1332	* idle low for a one for normal polarity. A zero is represented by a short low
mbed_official	324:406fd2029f23	1333	* pulse in the middle of a bit time remaining idle high for a one for inverted
mbed_official	324:406fd2029f23	1334	* polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
mbed_official	324:406fd2029f23	1335	* enabled and an initial character is detected in T = 0 protocol mode. Setting
mbed_official	324:406fd2029f23	1336	* RXINV inverts the RxD input for data bits, start and stop bits, break, and
mbed_official	324:406fd2029f23	1337	* idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
mbed_official	324:406fd2029f23	1338	* are inverted.
mbed_official	324:406fd2029f23	1339	*
mbed_official	324:406fd2029f23	1340	* Values:
mbed_official	324:406fd2029f23	1341	* - 0 - Receive data is not inverted.
mbed_official	324:406fd2029f23	1342	* - 1 - Receive data is inverted.
mbed_official	324:406fd2029f23	1343	*/
mbed_official	324:406fd2029f23	1344	/@{/
mbed_official	324:406fd2029f23	1345	#define BP_UART_S2_RXINV (4U) /!< Bit position for UART_S2_RXINV. /
mbed_official	324:406fd2029f23	1346	#define BM_UART_S2_RXINV (0x10U) /!< Bit mask for UART_S2_RXINV. /
mbed_official	324:406fd2029f23	1347	#define BS_UART_S2_RXINV (1U) /!< Bit field size in bits for UART_S2_RXINV. /
mbed_official	324:406fd2029f23	1348
mbed_official	324:406fd2029f23	1349	/! @brief Read current value of the UART_S2_RXINV field. /
mbed_official	324:406fd2029f23	1350	#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
mbed_official	324:406fd2029f23	1351
mbed_official	324:406fd2029f23	1352	/! @brief Format value for bitfield UART_S2_RXINV. /
mbed_official	324:406fd2029f23	1353	#define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV)
mbed_official	324:406fd2029f23	1354
mbed_official	324:406fd2029f23	1355	/! @brief Set the RXINV field to a new value. /
mbed_official	324:406fd2029f23	1356	#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
mbed_official	324:406fd2029f23	1357	/@}/
mbed_official	324:406fd2029f23	1358
mbed_official	324:406fd2029f23	1359	/*!
mbed_official	324:406fd2029f23	1360	* @name Register UART_S2, field MSBF[5] (RW)
mbed_official	324:406fd2029f23	1361	*
mbed_official	324:406fd2029f23	1362	* Setting this field reverses the order of the bits that are transmitted and
mbed_official	324:406fd2029f23	1363	* received on the wire. This field does not affect the polarity of the bits, the
mbed_official	324:406fd2029f23	1364	* location of the parity bit, or the location of the start or stop bits. This
mbed_official	324:406fd2029f23	1365	* field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
mbed_official	324:406fd2029f23	1366	* an initial character is detected in T = 0 protocol mode.
mbed_official	324:406fd2029f23	1367	*
mbed_official	324:406fd2029f23	1368	* Values:
mbed_official	324:406fd2029f23	1369	* - 0 - LSB (bit0) is the first bit that is transmitted following the start
mbed_official	324:406fd2029f23	1370	* bit. Further, the first bit received after the start bit is identified as
mbed_official	324:406fd2029f23	1371	* bit0.
mbed_official	324:406fd2029f23	1372	* - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
mbed_official	324:406fd2029f23	1373	* the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
mbed_official	324:406fd2029f23	1374	* first bit received after the start bit is identified as bit8, bit7, or
mbed_official	324:406fd2029f23	1375	* bit6, depending on the setting of C1[M] and C1[PE].
mbed_official	324:406fd2029f23	1376	*/
mbed_official	324:406fd2029f23	1377	/@{/
mbed_official	324:406fd2029f23	1378	#define BP_UART_S2_MSBF (5U) /!< Bit position for UART_S2_MSBF. /
mbed_official	324:406fd2029f23	1379	#define BM_UART_S2_MSBF (0x20U) /!< Bit mask for UART_S2_MSBF. /
mbed_official	324:406fd2029f23	1380	#define BS_UART_S2_MSBF (1U) /!< Bit field size in bits for UART_S2_MSBF. /
mbed_official	324:406fd2029f23	1381
mbed_official	324:406fd2029f23	1382	/! @brief Read current value of the UART_S2_MSBF field. /
mbed_official	324:406fd2029f23	1383	#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
mbed_official	324:406fd2029f23	1384
mbed_official	324:406fd2029f23	1385	/! @brief Format value for bitfield UART_S2_MSBF. /
mbed_official	324:406fd2029f23	1386	#define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF)
mbed_official	324:406fd2029f23	1387
mbed_official	324:406fd2029f23	1388	/! @brief Set the MSBF field to a new value. /
mbed_official	324:406fd2029f23	1389	#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
mbed_official	324:406fd2029f23	1390	/@}/
mbed_official	324:406fd2029f23	1391
mbed_official	324:406fd2029f23	1392	/*!
mbed_official	324:406fd2029f23	1393	* @name Register UART_S2, field RXEDGIF[6] (W1C)
mbed_official	324:406fd2029f23	1394	*
mbed_official	324:406fd2029f23	1395	* RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
mbed_official	324:406fd2029f23	1396	* falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
mbed_official	324:406fd2029f23	1397	* to it. See for additional details. RXEDGIF description The active edge is
mbed_official	324:406fd2029f23	1398	* detected only in two wire mode and on receiving data coming from the RxD pin.
mbed_official	324:406fd2029f23	1399	*
mbed_official	324:406fd2029f23	1400	* Values:
mbed_official	324:406fd2029f23	1401	* - 0 - No active edge on the receive pin has occurred.
mbed_official	324:406fd2029f23	1402	* - 1 - An active edge on the receive pin has occurred.
mbed_official	324:406fd2029f23	1403	*/
mbed_official	324:406fd2029f23	1404	/@{/
mbed_official	324:406fd2029f23	1405	#define BP_UART_S2_RXEDGIF (6U) /!< Bit position for UART_S2_RXEDGIF. /
mbed_official	324:406fd2029f23	1406	#define BM_UART_S2_RXEDGIF (0x40U) /!< Bit mask for UART_S2_RXEDGIF. /
mbed_official	324:406fd2029f23	1407	#define BS_UART_S2_RXEDGIF (1U) /!< Bit field size in bits for UART_S2_RXEDGIF. /
mbed_official	324:406fd2029f23	1408
mbed_official	324:406fd2029f23	1409	/! @brief Read current value of the UART_S2_RXEDGIF field. /
mbed_official	324:406fd2029f23	1410	#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
mbed_official	324:406fd2029f23	1411
mbed_official	324:406fd2029f23	1412	/! @brief Format value for bitfield UART_S2_RXEDGIF. /
mbed_official	324:406fd2029f23	1413	#define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF)
mbed_official	324:406fd2029f23	1414
mbed_official	324:406fd2029f23	1415	/! @brief Set the RXEDGIF field to a new value. /
mbed_official	324:406fd2029f23	1416	#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
mbed_official	324:406fd2029f23	1417	/@}/
mbed_official	324:406fd2029f23	1418
mbed_official	324:406fd2029f23	1419	/*!
mbed_official	324:406fd2029f23	1420	* @name Register UART_S2, field LBKDIF[7] (W1C)
mbed_official	324:406fd2029f23	1421	*
mbed_official	324:406fd2029f23	1422	* LBKDIF is set when LBKDE is set and a LIN break character is detected on the
mbed_official	324:406fd2029f23	1423	* receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
mbed_official	324:406fd2029f23	1424	* = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
mbed_official	324:406fd2029f23	1425	* last LIN break character. LBKDIF is cleared by writing a 1 to it.
mbed_official	324:406fd2029f23	1426	*
mbed_official	324:406fd2029f23	1427	* Values:
mbed_official	324:406fd2029f23	1428	* - 0 - No LIN break character detected.
mbed_official	324:406fd2029f23	1429	* - 1 - LIN break character detected.
mbed_official	324:406fd2029f23	1430	*/
mbed_official	324:406fd2029f23	1431	/@{/
mbed_official	324:406fd2029f23	1432	#define BP_UART_S2_LBKDIF (7U) /!< Bit position for UART_S2_LBKDIF. /
mbed_official	324:406fd2029f23	1433	#define BM_UART_S2_LBKDIF (0x80U) /!< Bit mask for UART_S2_LBKDIF. /
mbed_official	324:406fd2029f23	1434	#define BS_UART_S2_LBKDIF (1U) /!< Bit field size in bits for UART_S2_LBKDIF. /
mbed_official	324:406fd2029f23	1435
mbed_official	324:406fd2029f23	1436	/! @brief Read current value of the UART_S2_LBKDIF field. /
mbed_official	324:406fd2029f23	1437	#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
mbed_official	324:406fd2029f23	1438
mbed_official	324:406fd2029f23	1439	/! @brief Format value for bitfield UART_S2_LBKDIF. /
mbed_official	324:406fd2029f23	1440	#define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF)
mbed_official	324:406fd2029f23	1441
mbed_official	324:406fd2029f23	1442	/! @brief Set the LBKDIF field to a new value. /
mbed_official	324:406fd2029f23	1443	#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
mbed_official	324:406fd2029f23	1444	/@}/
mbed_official	324:406fd2029f23	1445
mbed_official	324:406fd2029f23	1446	/*******************************************************************************
mbed_official	324:406fd2029f23	1447	* HW_UART_C3 - UART Control Register 3
mbed_official	324:406fd2029f23	1448	******************************************************************************/
mbed_official	324:406fd2029f23	1449
mbed_official	324:406fd2029f23	1450	/*!
mbed_official	324:406fd2029f23	1451	* @brief HW_UART_C3 - UART Control Register 3 (RW)
mbed_official	324:406fd2029f23	1452	*
mbed_official	324:406fd2029f23	1453	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1454	*
mbed_official	324:406fd2029f23	1455	* Writing R8 does not have any effect. TXDIR and TXINV can be changed only
mbed_official	324:406fd2029f23	1456	* between transmit and receive packets.
mbed_official	324:406fd2029f23	1457	*/
mbed_official	324:406fd2029f23	1458	typedef union _hw_uart_c3
mbed_official	324:406fd2029f23	1459	{
mbed_official	324:406fd2029f23	1460	uint8_t U;
mbed_official	324:406fd2029f23	1461	struct _hw_uart_c3_bitfields
mbed_official	324:406fd2029f23	1462	{
mbed_official	324:406fd2029f23	1463	uint8_t PEIE : 1; /!< [0] Parity Error Interrupt Enable /
mbed_official	324:406fd2029f23	1464	uint8_t FEIE : 1; /!< [1] Framing Error Interrupt Enable /
mbed_official	324:406fd2029f23	1465	uint8_t NEIE : 1; /!< [2] Noise Error Interrupt Enable /
mbed_official	324:406fd2029f23	1466	uint8_t ORIE : 1; /!< [3] Overrun Error Interrupt Enable /
mbed_official	324:406fd2029f23	1467	uint8_t TXINV : 1; /!< [4] Transmit Data Inversion. /
mbed_official	324:406fd2029f23	1468	uint8_t TXDIR : 1; /*!< [5] Transmitter Pin Data Direction in
mbed_official	324:406fd2029f23	1469	* Single-Wire mode */
mbed_official	324:406fd2029f23	1470	uint8_t T8 : 1; /!< [6] Transmit Bit 8 /
mbed_official	324:406fd2029f23	1471	uint8_t R8 : 1; /!< [7] Received Bit 8 /
mbed_official	324:406fd2029f23	1472	} B;
mbed_official	324:406fd2029f23	1473	} hw_uart_c3_t;
mbed_official	324:406fd2029f23	1474
mbed_official	324:406fd2029f23	1475	/*!
mbed_official	324:406fd2029f23	1476	* @name Constants and macros for entire UART_C3 register
mbed_official	324:406fd2029f23	1477	*/
mbed_official	324:406fd2029f23	1478	/@{/
mbed_official	324:406fd2029f23	1479	#define HW_UART_C3_ADDR(x) ((x) + 0x6U)
mbed_official	324:406fd2029f23	1480
mbed_official	324:406fd2029f23	1481	#define HW_UART_C3(x) ((__IO hw_uart_c3_t ) HW_UART_C3_ADDR(x))
mbed_official	324:406fd2029f23	1482	#define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
mbed_official	324:406fd2029f23	1483	#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
mbed_official	324:406fd2029f23	1484	#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1485	#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1486	#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1487	/@}/
mbed_official	324:406fd2029f23	1488
mbed_official	324:406fd2029f23	1489	/*
mbed_official	324:406fd2029f23	1490	* Constants & macros for individual UART_C3 bitfields
mbed_official	324:406fd2029f23	1491	*/
mbed_official	324:406fd2029f23	1492
mbed_official	324:406fd2029f23	1493	/*!
mbed_official	324:406fd2029f23	1494	* @name Register UART_C3, field PEIE[0] (RW)
mbed_official	324:406fd2029f23	1495	*
mbed_official	324:406fd2029f23	1496	* Enables the parity error flag, S1[PF], to generate interrupt requests.
mbed_official	324:406fd2029f23	1497	*
mbed_official	324:406fd2029f23	1498	* Values:
mbed_official	324:406fd2029f23	1499	* - 0 - PF interrupt requests are disabled.
mbed_official	324:406fd2029f23	1500	* - 1 - PF interrupt requests are enabled.
mbed_official	324:406fd2029f23	1501	*/
mbed_official	324:406fd2029f23	1502	/@{/
mbed_official	324:406fd2029f23	1503	#define BP_UART_C3_PEIE (0U) /!< Bit position for UART_C3_PEIE. /
mbed_official	324:406fd2029f23	1504	#define BM_UART_C3_PEIE (0x01U) /!< Bit mask for UART_C3_PEIE. /
mbed_official	324:406fd2029f23	1505	#define BS_UART_C3_PEIE (1U) /!< Bit field size in bits for UART_C3_PEIE. /
mbed_official	324:406fd2029f23	1506
mbed_official	324:406fd2029f23	1507	/! @brief Read current value of the UART_C3_PEIE field. /
mbed_official	324:406fd2029f23	1508	#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
mbed_official	324:406fd2029f23	1509
mbed_official	324:406fd2029f23	1510	/! @brief Format value for bitfield UART_C3_PEIE. /
mbed_official	324:406fd2029f23	1511	#define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE)
mbed_official	324:406fd2029f23	1512
mbed_official	324:406fd2029f23	1513	/! @brief Set the PEIE field to a new value. /
mbed_official	324:406fd2029f23	1514	#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
mbed_official	324:406fd2029f23	1515	/@}/
mbed_official	324:406fd2029f23	1516
mbed_official	324:406fd2029f23	1517	/*!
mbed_official	324:406fd2029f23	1518	* @name Register UART_C3, field FEIE[1] (RW)
mbed_official	324:406fd2029f23	1519	*
mbed_official	324:406fd2029f23	1520	* Enables the framing error flag, S1[FE], to generate interrupt requests.
mbed_official	324:406fd2029f23	1521	*
mbed_official	324:406fd2029f23	1522	* Values:
mbed_official	324:406fd2029f23	1523	* - 0 - FE interrupt requests are disabled.
mbed_official	324:406fd2029f23	1524	* - 1 - FE interrupt requests are enabled.
mbed_official	324:406fd2029f23	1525	*/
mbed_official	324:406fd2029f23	1526	/@{/
mbed_official	324:406fd2029f23	1527	#define BP_UART_C3_FEIE (1U) /!< Bit position for UART_C3_FEIE. /
mbed_official	324:406fd2029f23	1528	#define BM_UART_C3_FEIE (0x02U) /!< Bit mask for UART_C3_FEIE. /
mbed_official	324:406fd2029f23	1529	#define BS_UART_C3_FEIE (1U) /!< Bit field size in bits for UART_C3_FEIE. /
mbed_official	324:406fd2029f23	1530
mbed_official	324:406fd2029f23	1531	/! @brief Read current value of the UART_C3_FEIE field. /
mbed_official	324:406fd2029f23	1532	#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
mbed_official	324:406fd2029f23	1533
mbed_official	324:406fd2029f23	1534	/! @brief Format value for bitfield UART_C3_FEIE. /
mbed_official	324:406fd2029f23	1535	#define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE)
mbed_official	324:406fd2029f23	1536
mbed_official	324:406fd2029f23	1537	/! @brief Set the FEIE field to a new value. /
mbed_official	324:406fd2029f23	1538	#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
mbed_official	324:406fd2029f23	1539	/@}/
mbed_official	324:406fd2029f23	1540
mbed_official	324:406fd2029f23	1541	/*!
mbed_official	324:406fd2029f23	1542	* @name Register UART_C3, field NEIE[2] (RW)
mbed_official	324:406fd2029f23	1543	*
mbed_official	324:406fd2029f23	1544	* Enables the noise flag, S1[NF], to generate interrupt requests.
mbed_official	324:406fd2029f23	1545	*
mbed_official	324:406fd2029f23	1546	* Values:
mbed_official	324:406fd2029f23	1547	* - 0 - NF interrupt requests are disabled.
mbed_official	324:406fd2029f23	1548	* - 1 - NF interrupt requests are enabled.
mbed_official	324:406fd2029f23	1549	*/
mbed_official	324:406fd2029f23	1550	/@{/
mbed_official	324:406fd2029f23	1551	#define BP_UART_C3_NEIE (2U) /!< Bit position for UART_C3_NEIE. /
mbed_official	324:406fd2029f23	1552	#define BM_UART_C3_NEIE (0x04U) /!< Bit mask for UART_C3_NEIE. /
mbed_official	324:406fd2029f23	1553	#define BS_UART_C3_NEIE (1U) /!< Bit field size in bits for UART_C3_NEIE. /
mbed_official	324:406fd2029f23	1554
mbed_official	324:406fd2029f23	1555	/! @brief Read current value of the UART_C3_NEIE field. /
mbed_official	324:406fd2029f23	1556	#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
mbed_official	324:406fd2029f23	1557
mbed_official	324:406fd2029f23	1558	/! @brief Format value for bitfield UART_C3_NEIE. /
mbed_official	324:406fd2029f23	1559	#define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE)
mbed_official	324:406fd2029f23	1560
mbed_official	324:406fd2029f23	1561	/! @brief Set the NEIE field to a new value. /
mbed_official	324:406fd2029f23	1562	#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
mbed_official	324:406fd2029f23	1563	/@}/
mbed_official	324:406fd2029f23	1564
mbed_official	324:406fd2029f23	1565	/*!
mbed_official	324:406fd2029f23	1566	* @name Register UART_C3, field ORIE[3] (RW)
mbed_official	324:406fd2029f23	1567	*
mbed_official	324:406fd2029f23	1568	* Enables the overrun error flag, S1[OR], to generate interrupt requests.
mbed_official	324:406fd2029f23	1569	*
mbed_official	324:406fd2029f23	1570	* Values:
mbed_official	324:406fd2029f23	1571	* - 0 - OR interrupts are disabled.
mbed_official	324:406fd2029f23	1572	* - 1 - OR interrupt requests are enabled.
mbed_official	324:406fd2029f23	1573	*/
mbed_official	324:406fd2029f23	1574	/@{/
mbed_official	324:406fd2029f23	1575	#define BP_UART_C3_ORIE (3U) /!< Bit position for UART_C3_ORIE. /
mbed_official	324:406fd2029f23	1576	#define BM_UART_C3_ORIE (0x08U) /!< Bit mask for UART_C3_ORIE. /
mbed_official	324:406fd2029f23	1577	#define BS_UART_C3_ORIE (1U) /!< Bit field size in bits for UART_C3_ORIE. /
mbed_official	324:406fd2029f23	1578
mbed_official	324:406fd2029f23	1579	/! @brief Read current value of the UART_C3_ORIE field. /
mbed_official	324:406fd2029f23	1580	#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
mbed_official	324:406fd2029f23	1581
mbed_official	324:406fd2029f23	1582	/! @brief Format value for bitfield UART_C3_ORIE. /
mbed_official	324:406fd2029f23	1583	#define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE)
mbed_official	324:406fd2029f23	1584
mbed_official	324:406fd2029f23	1585	/! @brief Set the ORIE field to a new value. /
mbed_official	324:406fd2029f23	1586	#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
mbed_official	324:406fd2029f23	1587	/@}/
mbed_official	324:406fd2029f23	1588
mbed_official	324:406fd2029f23	1589	/*!
mbed_official	324:406fd2029f23	1590	* @name Register UART_C3, field TXINV[4] (RW)
mbed_official	324:406fd2029f23	1591	*
mbed_official	324:406fd2029f23	1592	* Setting this field reverses the polarity of the transmitted data output. In
mbed_official	324:406fd2029f23	1593	* NRZ format, a one is represented by a mark and a zero is represented by a space
mbed_official	324:406fd2029f23	1594	* for normal polarity, and the opposite for inverted polarity. In IrDA format,
mbed_official	324:406fd2029f23	1595	* a zero is represented by short high pulse in the middle of a bit time
mbed_official	324:406fd2029f23	1596	* remaining idle low for a one for normal polarity, and a zero is represented by short
mbed_official	324:406fd2029f23	1597	* low pulse in the middle of a bit time remaining idle high for a one for
mbed_official	324:406fd2029f23	1598	* inverted polarity. This field is automatically set when C7816[INIT] and
mbed_official	324:406fd2029f23	1599	* C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
mbed_official	324:406fd2029f23	1600	* Setting TXINV inverts all transmitted values, including idle, break, start, and
mbed_official	324:406fd2029f23	1601	* stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
mbed_official	324:406fd2029f23	1602	* inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
mbed_official	324:406fd2029f23	1603	* the transmitted data bits and parity bit are inverted.
mbed_official	324:406fd2029f23	1604	*
mbed_official	324:406fd2029f23	1605	* Values:
mbed_official	324:406fd2029f23	1606	* - 0 - Transmit data is not inverted.
mbed_official	324:406fd2029f23	1607	* - 1 - Transmit data is inverted.
mbed_official	324:406fd2029f23	1608	*/
mbed_official	324:406fd2029f23	1609	/@{/
mbed_official	324:406fd2029f23	1610	#define BP_UART_C3_TXINV (4U) /!< Bit position for UART_C3_TXINV. /
mbed_official	324:406fd2029f23	1611	#define BM_UART_C3_TXINV (0x10U) /!< Bit mask for UART_C3_TXINV. /
mbed_official	324:406fd2029f23	1612	#define BS_UART_C3_TXINV (1U) /!< Bit field size in bits for UART_C3_TXINV. /
mbed_official	324:406fd2029f23	1613
mbed_official	324:406fd2029f23	1614	/! @brief Read current value of the UART_C3_TXINV field. /
mbed_official	324:406fd2029f23	1615	#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
mbed_official	324:406fd2029f23	1616
mbed_official	324:406fd2029f23	1617	/! @brief Format value for bitfield UART_C3_TXINV. /
mbed_official	324:406fd2029f23	1618	#define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV)
mbed_official	324:406fd2029f23	1619
mbed_official	324:406fd2029f23	1620	/! @brief Set the TXINV field to a new value. /
mbed_official	324:406fd2029f23	1621	#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
mbed_official	324:406fd2029f23	1622	/@}/
mbed_official	324:406fd2029f23	1623
mbed_official	324:406fd2029f23	1624	/*!
mbed_official	324:406fd2029f23	1625	* @name Register UART_C3, field TXDIR[5] (RW)
mbed_official	324:406fd2029f23	1626	*
mbed_official	324:406fd2029f23	1627	* Determines whether the TXD pin is used as an input or output in the
mbed_official	324:406fd2029f23	1628	* single-wire mode of operation. This field is relevant only to the single wire mode.
mbed_official	324:406fd2029f23	1629	* When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
mbed_official	324:406fd2029f23	1630	* automatically cleared after the requested block is transmitted. This condition is
mbed_official	324:406fd2029f23	1631	* detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
mbed_official	324:406fd2029f23	1632	* Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
mbed_official	324:406fd2029f23	1633	* being transmitted, the hardware automatically overrides this field as needed. In
mbed_official	324:406fd2029f23	1634	* this situation, TXDIR does not reflect the temporary state associated with
mbed_official	324:406fd2029f23	1635	* the NACK.
mbed_official	324:406fd2029f23	1636	*
mbed_official	324:406fd2029f23	1637	* Values:
mbed_official	324:406fd2029f23	1638	* - 0 - TXD pin is an input in single wire mode.
mbed_official	324:406fd2029f23	1639	* - 1 - TXD pin is an output in single wire mode.
mbed_official	324:406fd2029f23	1640	*/
mbed_official	324:406fd2029f23	1641	/@{/
mbed_official	324:406fd2029f23	1642	#define BP_UART_C3_TXDIR (5U) /!< Bit position for UART_C3_TXDIR. /
mbed_official	324:406fd2029f23	1643	#define BM_UART_C3_TXDIR (0x20U) /!< Bit mask for UART_C3_TXDIR. /
mbed_official	324:406fd2029f23	1644	#define BS_UART_C3_TXDIR (1U) /!< Bit field size in bits for UART_C3_TXDIR. /
mbed_official	324:406fd2029f23	1645
mbed_official	324:406fd2029f23	1646	/! @brief Read current value of the UART_C3_TXDIR field. /
mbed_official	324:406fd2029f23	1647	#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
mbed_official	324:406fd2029f23	1648
mbed_official	324:406fd2029f23	1649	/! @brief Format value for bitfield UART_C3_TXDIR. /
mbed_official	324:406fd2029f23	1650	#define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR)
mbed_official	324:406fd2029f23	1651
mbed_official	324:406fd2029f23	1652	/! @brief Set the TXDIR field to a new value. /
mbed_official	324:406fd2029f23	1653	#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
mbed_official	324:406fd2029f23	1654	/@}/
mbed_official	324:406fd2029f23	1655
mbed_official	324:406fd2029f23	1656	/*!
mbed_official	324:406fd2029f23	1657	* @name Register UART_C3, field T8[6] (RW)
mbed_official	324:406fd2029f23	1658	*
mbed_official	324:406fd2029f23	1659	* T8 is the ninth data bit transmitted when the UART is configured for 9-bit
mbed_official	324:406fd2029f23	1660	* data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
mbed_official	324:406fd2029f23	1661	* same as in the previous transmission, T8 does not have to be rewritten. The same
mbed_official	324:406fd2029f23	1662	* value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
mbed_official	324:406fd2029f23	1663	* write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
mbed_official	324:406fd2029f23	1664	* the remaining data.
mbed_official	324:406fd2029f23	1665	*/
mbed_official	324:406fd2029f23	1666	/@{/
mbed_official	324:406fd2029f23	1667	#define BP_UART_C3_T8 (6U) /!< Bit position for UART_C3_T8. /
mbed_official	324:406fd2029f23	1668	#define BM_UART_C3_T8 (0x40U) /!< Bit mask for UART_C3_T8. /
mbed_official	324:406fd2029f23	1669	#define BS_UART_C3_T8 (1U) /!< Bit field size in bits for UART_C3_T8. /
mbed_official	324:406fd2029f23	1670
mbed_official	324:406fd2029f23	1671	/! @brief Read current value of the UART_C3_T8 field. /
mbed_official	324:406fd2029f23	1672	#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
mbed_official	324:406fd2029f23	1673
mbed_official	324:406fd2029f23	1674	/! @brief Format value for bitfield UART_C3_T8. /
mbed_official	324:406fd2029f23	1675	#define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8)
mbed_official	324:406fd2029f23	1676
mbed_official	324:406fd2029f23	1677	/! @brief Set the T8 field to a new value. /
mbed_official	324:406fd2029f23	1678	#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
mbed_official	324:406fd2029f23	1679	/@}/
mbed_official	324:406fd2029f23	1680
mbed_official	324:406fd2029f23	1681	/*!
mbed_official	324:406fd2029f23	1682	* @name Register UART_C3, field R8[7] (RO)
mbed_official	324:406fd2029f23	1683	*
mbed_official	324:406fd2029f23	1684	* R8 is the ninth data bit received when the UART is configured for 9-bit data
mbed_official	324:406fd2029f23	1685	* format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
mbed_official	324:406fd2029f23	1686	* current data value in the UARTx_D register. To read the 9th bit, read the
mbed_official	324:406fd2029f23	1687	* value of UARTx_C3[R8], then read the UARTx_D register.
mbed_official	324:406fd2029f23	1688	*/
mbed_official	324:406fd2029f23	1689	/@{/
mbed_official	324:406fd2029f23	1690	#define BP_UART_C3_R8 (7U) /!< Bit position for UART_C3_R8. /
mbed_official	324:406fd2029f23	1691	#define BM_UART_C3_R8 (0x80U) /!< Bit mask for UART_C3_R8. /
mbed_official	324:406fd2029f23	1692	#define BS_UART_C3_R8 (1U) /!< Bit field size in bits for UART_C3_R8. /
mbed_official	324:406fd2029f23	1693
mbed_official	324:406fd2029f23	1694	/! @brief Read current value of the UART_C3_R8 field. /
mbed_official	324:406fd2029f23	1695	#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
mbed_official	324:406fd2029f23	1696	/@}/
mbed_official	324:406fd2029f23	1697
mbed_official	324:406fd2029f23	1698	/*******************************************************************************
mbed_official	324:406fd2029f23	1699	* HW_UART_D - UART Data Register
mbed_official	324:406fd2029f23	1700	******************************************************************************/
mbed_official	324:406fd2029f23	1701
mbed_official	324:406fd2029f23	1702	/*!
mbed_official	324:406fd2029f23	1703	* @brief HW_UART_D - UART Data Register (RW)
mbed_official	324:406fd2029f23	1704	*
mbed_official	324:406fd2029f23	1705	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1706	*
mbed_official	324:406fd2029f23	1707	* This register is actually two separate registers. Reads return the contents
mbed_official	324:406fd2029f23	1708	* of the read-only receive data register and writes go to the write-only transmit
mbed_official	324:406fd2029f23	1709	* data register. In 8-bit or 9-bit data format, only UART data register (D)
mbed_official	324:406fd2029f23	1710	* needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
mbed_official	324:406fd2029f23	1711	* less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
mbed_official	324:406fd2029f23	1712	* register, only if the ninth bit of data needs to be captured. Similarly, the
mbed_official	324:406fd2029f23	1713	* ED register needs to be read, prior to the D register, only if the additional
mbed_official	324:406fd2029f23	1714	* flag data for the dataword needs to be captured. In the normal 8-bit mode (M
mbed_official	324:406fd2029f23	1715	* bit cleared) if the parity is enabled, you get seven data bits and one parity
mbed_official	324:406fd2029f23	1716	* bit. That one parity bit is loaded into the D register. So, for the data bits,
mbed_official	324:406fd2029f23	1717	* mask off the parity bit from the value you read out of this register. When
mbed_official	324:406fd2029f23	1718	* transmitting in 9-bit data format and using 8-bit write instructions, write first
mbed_official	324:406fd2029f23	1719	* to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
mbed_official	324:406fd2029f23	1720	* C3[T8] stores the data in a temporary register. If D register is written first,
mbed_official	324:406fd2029f23	1721	* and then the new data on data bus is stored in D, the temporary value written by
mbed_official	324:406fd2029f23	1722	* the last write to C3[T8] gets stored in the C3[T8] register.
mbed_official	324:406fd2029f23	1723	*/
mbed_official	324:406fd2029f23	1724	typedef union _hw_uart_d
mbed_official	324:406fd2029f23	1725	{
mbed_official	324:406fd2029f23	1726	uint8_t U;
mbed_official	324:406fd2029f23	1727	struct _hw_uart_d_bitfields
mbed_official	324:406fd2029f23	1728	{
mbed_official	324:406fd2029f23	1729	uint8_t RT : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1730	} B;
mbed_official	324:406fd2029f23	1731	} hw_uart_d_t;
mbed_official	324:406fd2029f23	1732
mbed_official	324:406fd2029f23	1733	/*!
mbed_official	324:406fd2029f23	1734	* @name Constants and macros for entire UART_D register
mbed_official	324:406fd2029f23	1735	*/
mbed_official	324:406fd2029f23	1736	/@{/
mbed_official	324:406fd2029f23	1737	#define HW_UART_D_ADDR(x) ((x) + 0x7U)
mbed_official	324:406fd2029f23	1738
mbed_official	324:406fd2029f23	1739	#define HW_UART_D(x) ((__IO hw_uart_d_t ) HW_UART_D_ADDR(x))
mbed_official	324:406fd2029f23	1740	#define HW_UART_D_RD(x) (HW_UART_D(x).U)
mbed_official	324:406fd2029f23	1741	#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
mbed_official	324:406fd2029f23	1742	#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1743	#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1744	#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1745	/@}/
mbed_official	324:406fd2029f23	1746
mbed_official	324:406fd2029f23	1747	/*
mbed_official	324:406fd2029f23	1748	* Constants & macros for individual UART_D bitfields
mbed_official	324:406fd2029f23	1749	*/
mbed_official	324:406fd2029f23	1750
mbed_official	324:406fd2029f23	1751	/*!
mbed_official	324:406fd2029f23	1752	* @name Register UART_D, field RT[7:0] (RW)
mbed_official	324:406fd2029f23	1753	*
mbed_official	324:406fd2029f23	1754	* Reads return the contents of the read-only receive data register and writes
mbed_official	324:406fd2029f23	1755	* go to the write-only transmit data register.
mbed_official	324:406fd2029f23	1756	*/
mbed_official	324:406fd2029f23	1757	/@{/
mbed_official	324:406fd2029f23	1758	#define BP_UART_D_RT (0U) /!< Bit position for UART_D_RT. /
mbed_official	324:406fd2029f23	1759	#define BM_UART_D_RT (0xFFU) /!< Bit mask for UART_D_RT. /
mbed_official	324:406fd2029f23	1760	#define BS_UART_D_RT (8U) /!< Bit field size in bits for UART_D_RT. /
mbed_official	324:406fd2029f23	1761
mbed_official	324:406fd2029f23	1762	/! @brief Read current value of the UART_D_RT field. /
mbed_official	324:406fd2029f23	1763	#define BR_UART_D_RT(x) (HW_UART_D(x).U)
mbed_official	324:406fd2029f23	1764
mbed_official	324:406fd2029f23	1765	/! @brief Format value for bitfield UART_D_RT. /
mbed_official	324:406fd2029f23	1766	#define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT)
mbed_official	324:406fd2029f23	1767
mbed_official	324:406fd2029f23	1768	/! @brief Set the RT field to a new value. /
mbed_official	324:406fd2029f23	1769	#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
mbed_official	324:406fd2029f23	1770	/@}/
mbed_official	324:406fd2029f23	1771
mbed_official	324:406fd2029f23	1772	/*******************************************************************************
mbed_official	324:406fd2029f23	1773	* HW_UART_MA1 - UART Match Address Registers 1
mbed_official	324:406fd2029f23	1774	******************************************************************************/
mbed_official	324:406fd2029f23	1775
mbed_official	324:406fd2029f23	1776	/*!
mbed_official	324:406fd2029f23	1777	* @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
mbed_official	324:406fd2029f23	1778	*
mbed_official	324:406fd2029f23	1779	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1780	*
mbed_official	324:406fd2029f23	1781	* The MA1 and MA2 registers are compared to input data addresses when the most
mbed_official	324:406fd2029f23	1782	* significant bit is set and the associated C4[MAEN] field is set. If a match
mbed_official	324:406fd2029f23	1783	* occurs, the following data is transferred to the data register. If a match
mbed_official	324:406fd2029f23	1784	* fails, the following data is discarded. These registers can be read and written at
mbed_official	324:406fd2029f23	1785	* anytime.
mbed_official	324:406fd2029f23	1786	*/
mbed_official	324:406fd2029f23	1787	typedef union _hw_uart_ma1
mbed_official	324:406fd2029f23	1788	{
mbed_official	324:406fd2029f23	1789	uint8_t U;
mbed_official	324:406fd2029f23	1790	struct _hw_uart_ma1_bitfields
mbed_official	324:406fd2029f23	1791	{
mbed_official	324:406fd2029f23	1792	uint8_t MA : 8; /!< [7:0] Match Address /
mbed_official	324:406fd2029f23	1793	} B;
mbed_official	324:406fd2029f23	1794	} hw_uart_ma1_t;
mbed_official	324:406fd2029f23	1795
mbed_official	324:406fd2029f23	1796	/*!
mbed_official	324:406fd2029f23	1797	* @name Constants and macros for entire UART_MA1 register
mbed_official	324:406fd2029f23	1798	*/
mbed_official	324:406fd2029f23	1799	/@{/
mbed_official	324:406fd2029f23	1800	#define HW_UART_MA1_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	1801
mbed_official	324:406fd2029f23	1802	#define HW_UART_MA1(x) ((__IO hw_uart_ma1_t ) HW_UART_MA1_ADDR(x))
mbed_official	324:406fd2029f23	1803	#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
mbed_official	324:406fd2029f23	1804	#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
mbed_official	324:406fd2029f23	1805	#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1806	#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1807	#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1808	/@}/
mbed_official	324:406fd2029f23	1809
mbed_official	324:406fd2029f23	1810	/*
mbed_official	324:406fd2029f23	1811	* Constants & macros for individual UART_MA1 bitfields
mbed_official	324:406fd2029f23	1812	*/
mbed_official	324:406fd2029f23	1813
mbed_official	324:406fd2029f23	1814	/*!
mbed_official	324:406fd2029f23	1815	* @name Register UART_MA1, field MA[7:0] (RW)
mbed_official	324:406fd2029f23	1816	*/
mbed_official	324:406fd2029f23	1817	/@{/
mbed_official	324:406fd2029f23	1818	#define BP_UART_MA1_MA (0U) /!< Bit position for UART_MA1_MA. /
mbed_official	324:406fd2029f23	1819	#define BM_UART_MA1_MA (0xFFU) /!< Bit mask for UART_MA1_MA. /
mbed_official	324:406fd2029f23	1820	#define BS_UART_MA1_MA (8U) /!< Bit field size in bits for UART_MA1_MA. /
mbed_official	324:406fd2029f23	1821
mbed_official	324:406fd2029f23	1822	/! @brief Read current value of the UART_MA1_MA field. /
mbed_official	324:406fd2029f23	1823	#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
mbed_official	324:406fd2029f23	1824
mbed_official	324:406fd2029f23	1825	/! @brief Format value for bitfield UART_MA1_MA. /
mbed_official	324:406fd2029f23	1826	#define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA)
mbed_official	324:406fd2029f23	1827
mbed_official	324:406fd2029f23	1828	/! @brief Set the MA field to a new value. /
mbed_official	324:406fd2029f23	1829	#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
mbed_official	324:406fd2029f23	1830	/@}/
mbed_official	324:406fd2029f23	1831
mbed_official	324:406fd2029f23	1832	/*******************************************************************************
mbed_official	324:406fd2029f23	1833	* HW_UART_MA2 - UART Match Address Registers 2
mbed_official	324:406fd2029f23	1834	******************************************************************************/
mbed_official	324:406fd2029f23	1835
mbed_official	324:406fd2029f23	1836	/*!
mbed_official	324:406fd2029f23	1837	* @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
mbed_official	324:406fd2029f23	1838	*
mbed_official	324:406fd2029f23	1839	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1840	*
mbed_official	324:406fd2029f23	1841	* These registers can be read and written at anytime. The MA1 and MA2 registers
mbed_official	324:406fd2029f23	1842	* are compared to input data addresses when the most significant bit is set and
mbed_official	324:406fd2029f23	1843	* the associated C4[MAEN] field is set. If a match occurs, the following data
mbed_official	324:406fd2029f23	1844	* is transferred to the data register. If a match fails, the following data is
mbed_official	324:406fd2029f23	1845	* discarded.
mbed_official	324:406fd2029f23	1846	*/
mbed_official	324:406fd2029f23	1847	typedef union _hw_uart_ma2
mbed_official	324:406fd2029f23	1848	{
mbed_official	324:406fd2029f23	1849	uint8_t U;
mbed_official	324:406fd2029f23	1850	struct _hw_uart_ma2_bitfields
mbed_official	324:406fd2029f23	1851	{
mbed_official	324:406fd2029f23	1852	uint8_t MA : 8; /!< [7:0] Match Address /
mbed_official	324:406fd2029f23	1853	} B;
mbed_official	324:406fd2029f23	1854	} hw_uart_ma2_t;
mbed_official	324:406fd2029f23	1855
mbed_official	324:406fd2029f23	1856	/*!
mbed_official	324:406fd2029f23	1857	* @name Constants and macros for entire UART_MA2 register
mbed_official	324:406fd2029f23	1858	*/
mbed_official	324:406fd2029f23	1859	/@{/
mbed_official	324:406fd2029f23	1860	#define HW_UART_MA2_ADDR(x) ((x) + 0x9U)
mbed_official	324:406fd2029f23	1861
mbed_official	324:406fd2029f23	1862	#define HW_UART_MA2(x) ((__IO hw_uart_ma2_t ) HW_UART_MA2_ADDR(x))
mbed_official	324:406fd2029f23	1863	#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
mbed_official	324:406fd2029f23	1864	#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
mbed_official	324:406fd2029f23	1865	#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1866	#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1867	#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1868	/@}/
mbed_official	324:406fd2029f23	1869
mbed_official	324:406fd2029f23	1870	/*
mbed_official	324:406fd2029f23	1871	* Constants & macros for individual UART_MA2 bitfields
mbed_official	324:406fd2029f23	1872	*/
mbed_official	324:406fd2029f23	1873
mbed_official	324:406fd2029f23	1874	/*!
mbed_official	324:406fd2029f23	1875	* @name Register UART_MA2, field MA[7:0] (RW)
mbed_official	324:406fd2029f23	1876	*/
mbed_official	324:406fd2029f23	1877	/@{/
mbed_official	324:406fd2029f23	1878	#define BP_UART_MA2_MA (0U) /!< Bit position for UART_MA2_MA. /
mbed_official	324:406fd2029f23	1879	#define BM_UART_MA2_MA (0xFFU) /!< Bit mask for UART_MA2_MA. /
mbed_official	324:406fd2029f23	1880	#define BS_UART_MA2_MA (8U) /!< Bit field size in bits for UART_MA2_MA. /
mbed_official	324:406fd2029f23	1881
mbed_official	324:406fd2029f23	1882	/! @brief Read current value of the UART_MA2_MA field. /
mbed_official	324:406fd2029f23	1883	#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
mbed_official	324:406fd2029f23	1884
mbed_official	324:406fd2029f23	1885	/! @brief Format value for bitfield UART_MA2_MA. /
mbed_official	324:406fd2029f23	1886	#define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA)
mbed_official	324:406fd2029f23	1887
mbed_official	324:406fd2029f23	1888	/! @brief Set the MA field to a new value. /
mbed_official	324:406fd2029f23	1889	#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
mbed_official	324:406fd2029f23	1890	/@}/
mbed_official	324:406fd2029f23	1891
mbed_official	324:406fd2029f23	1892	/*******************************************************************************
mbed_official	324:406fd2029f23	1893	* HW_UART_C4 - UART Control Register 4
mbed_official	324:406fd2029f23	1894	******************************************************************************/
mbed_official	324:406fd2029f23	1895
mbed_official	324:406fd2029f23	1896	/*!
mbed_official	324:406fd2029f23	1897	* @brief HW_UART_C4 - UART Control Register 4 (RW)
mbed_official	324:406fd2029f23	1898	*
mbed_official	324:406fd2029f23	1899	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1900	*/
mbed_official	324:406fd2029f23	1901	typedef union _hw_uart_c4
mbed_official	324:406fd2029f23	1902	{
mbed_official	324:406fd2029f23	1903	uint8_t U;
mbed_official	324:406fd2029f23	1904	struct _hw_uart_c4_bitfields
mbed_official	324:406fd2029f23	1905	{
mbed_official	324:406fd2029f23	1906	uint8_t BRFA : 5; /!< [4:0] Baud Rate Fine Adjust /
mbed_official	324:406fd2029f23	1907	uint8_t M10 : 1; /!< [5] 10-bit Mode select /
mbed_official	324:406fd2029f23	1908	uint8_t MAEN2 : 1; /!< [6] Match Address Mode Enable 2 /
mbed_official	324:406fd2029f23	1909	uint8_t MAEN1 : 1; /!< [7] Match Address Mode Enable 1 /
mbed_official	324:406fd2029f23	1910	} B;
mbed_official	324:406fd2029f23	1911	} hw_uart_c4_t;
mbed_official	324:406fd2029f23	1912
mbed_official	324:406fd2029f23	1913	/*!
mbed_official	324:406fd2029f23	1914	* @name Constants and macros for entire UART_C4 register
mbed_official	324:406fd2029f23	1915	*/
mbed_official	324:406fd2029f23	1916	/@{/
mbed_official	324:406fd2029f23	1917	#define HW_UART_C4_ADDR(x) ((x) + 0xAU)
mbed_official	324:406fd2029f23	1918
mbed_official	324:406fd2029f23	1919	#define HW_UART_C4(x) ((__IO hw_uart_c4_t ) HW_UART_C4_ADDR(x))
mbed_official	324:406fd2029f23	1920	#define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
mbed_official	324:406fd2029f23	1921	#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
mbed_official	324:406fd2029f23	1922	#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1923	#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1924	#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1925	/@}/
mbed_official	324:406fd2029f23	1926
mbed_official	324:406fd2029f23	1927	/*
mbed_official	324:406fd2029f23	1928	* Constants & macros for individual UART_C4 bitfields
mbed_official	324:406fd2029f23	1929	*/
mbed_official	324:406fd2029f23	1930
mbed_official	324:406fd2029f23	1931	/*!
mbed_official	324:406fd2029f23	1932	* @name Register UART_C4, field BRFA[4:0] (RW)
mbed_official	324:406fd2029f23	1933	*
mbed_official	324:406fd2029f23	1934	* This bit field is used to add more timing resolution to the average baud
mbed_official	324:406fd2029f23	1935	* frequency, in increments of 1/32. See Baud rate generation for more information.
mbed_official	324:406fd2029f23	1936	*/
mbed_official	324:406fd2029f23	1937	/@{/
mbed_official	324:406fd2029f23	1938	#define BP_UART_C4_BRFA (0U) /!< Bit position for UART_C4_BRFA. /
mbed_official	324:406fd2029f23	1939	#define BM_UART_C4_BRFA (0x1FU) /!< Bit mask for UART_C4_BRFA. /
mbed_official	324:406fd2029f23	1940	#define BS_UART_C4_BRFA (5U) /!< Bit field size in bits for UART_C4_BRFA. /
mbed_official	324:406fd2029f23	1941
mbed_official	324:406fd2029f23	1942	/! @brief Read current value of the UART_C4_BRFA field. /
mbed_official	324:406fd2029f23	1943	#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
mbed_official	324:406fd2029f23	1944
mbed_official	324:406fd2029f23	1945	/! @brief Format value for bitfield UART_C4_BRFA. /
mbed_official	324:406fd2029f23	1946	#define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA)
mbed_official	324:406fd2029f23	1947
mbed_official	324:406fd2029f23	1948	/! @brief Set the BRFA field to a new value. /
mbed_official	324:406fd2029f23	1949	#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) \| BF_UART_C4_BRFA(v)))
mbed_official	324:406fd2029f23	1950	/@}/
mbed_official	324:406fd2029f23	1951
mbed_official	324:406fd2029f23	1952	/*!
mbed_official	324:406fd2029f23	1953	* @name Register UART_C4, field M10[5] (RW)
mbed_official	324:406fd2029f23	1954	*
mbed_official	324:406fd2029f23	1955	* Causes a tenth, non-memory mapped bit to be part of the serial transmission.
mbed_official	324:406fd2029f23	1956	* This tenth bit is generated and interpreted as a parity bit. The M10 field
mbed_official	324:406fd2029f23	1957	* does not affect the LIN send or detect break behavior. If M10 is set, then both
mbed_official	324:406fd2029f23	1958	* C1[M] and C1[PE] must also be set. This field must be cleared when
mbed_official	324:406fd2029f23	1959	* C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
mbed_official	324:406fd2029f23	1960	*
mbed_official	324:406fd2029f23	1961	* Values:
mbed_official	324:406fd2029f23	1962	* - 0 - The parity bit is the ninth bit in the serial transmission.
mbed_official	324:406fd2029f23	1963	* - 1 - The parity bit is the tenth bit in the serial transmission.
mbed_official	324:406fd2029f23	1964	*/
mbed_official	324:406fd2029f23	1965	/@{/
mbed_official	324:406fd2029f23	1966	#define BP_UART_C4_M10 (5U) /!< Bit position for UART_C4_M10. /
mbed_official	324:406fd2029f23	1967	#define BM_UART_C4_M10 (0x20U) /!< Bit mask for UART_C4_M10. /
mbed_official	324:406fd2029f23	1968	#define BS_UART_C4_M10 (1U) /!< Bit field size in bits for UART_C4_M10. /
mbed_official	324:406fd2029f23	1969
mbed_official	324:406fd2029f23	1970	/! @brief Read current value of the UART_C4_M10 field. /
mbed_official	324:406fd2029f23	1971	#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
mbed_official	324:406fd2029f23	1972
mbed_official	324:406fd2029f23	1973	/! @brief Format value for bitfield UART_C4_M10. /
mbed_official	324:406fd2029f23	1974	#define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10)
mbed_official	324:406fd2029f23	1975
mbed_official	324:406fd2029f23	1976	/! @brief Set the M10 field to a new value. /
mbed_official	324:406fd2029f23	1977	#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
mbed_official	324:406fd2029f23	1978	/@}/
mbed_official	324:406fd2029f23	1979
mbed_official	324:406fd2029f23	1980	/*!
mbed_official	324:406fd2029f23	1981	* @name Register UART_C4, field MAEN2[6] (RW)
mbed_official	324:406fd2029f23	1982	*
mbed_official	324:406fd2029f23	1983	* See Match address operation for more information.
mbed_official	324:406fd2029f23	1984	*
mbed_official	324:406fd2029f23	1985	* Values:
mbed_official	324:406fd2029f23	1986	* - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
mbed_official	324:406fd2029f23	1987	* - 1 - All data received with the most significant bit cleared, is discarded.
mbed_official	324:406fd2029f23	1988	* All data received with the most significant bit set, is compared with
mbed_official	324:406fd2029f23	1989	* contents of MA2 register. If no match occurs, the data is discarded. If a
mbed_official	324:406fd2029f23	1990	* match occurs, data is transferred to the data buffer. This field must be
mbed_official	324:406fd2029f23	1991	* cleared when C7816[ISO7816E] is set/enabled.
mbed_official	324:406fd2029f23	1992	*/
mbed_official	324:406fd2029f23	1993	/@{/
mbed_official	324:406fd2029f23	1994	#define BP_UART_C4_MAEN2 (6U) /!< Bit position for UART_C4_MAEN2. /
mbed_official	324:406fd2029f23	1995	#define BM_UART_C4_MAEN2 (0x40U) /!< Bit mask for UART_C4_MAEN2. /
mbed_official	324:406fd2029f23	1996	#define BS_UART_C4_MAEN2 (1U) /!< Bit field size in bits for UART_C4_MAEN2. /
mbed_official	324:406fd2029f23	1997
mbed_official	324:406fd2029f23	1998	/! @brief Read current value of the UART_C4_MAEN2 field. /
mbed_official	324:406fd2029f23	1999	#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
mbed_official	324:406fd2029f23	2000
mbed_official	324:406fd2029f23	2001	/! @brief Format value for bitfield UART_C4_MAEN2. /
mbed_official	324:406fd2029f23	2002	#define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2)
mbed_official	324:406fd2029f23	2003
mbed_official	324:406fd2029f23	2004	/! @brief Set the MAEN2 field to a new value. /
mbed_official	324:406fd2029f23	2005	#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
mbed_official	324:406fd2029f23	2006	/@}/
mbed_official	324:406fd2029f23	2007
mbed_official	324:406fd2029f23	2008	/*!
mbed_official	324:406fd2029f23	2009	* @name Register UART_C4, field MAEN1[7] (RW)
mbed_official	324:406fd2029f23	2010	*
mbed_official	324:406fd2029f23	2011	* See Match address operation for more information.
mbed_official	324:406fd2029f23	2012	*
mbed_official	324:406fd2029f23	2013	* Values:
mbed_official	324:406fd2029f23	2014	* - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
mbed_official	324:406fd2029f23	2015	* - 1 - All data received with the most significant bit cleared, is discarded.
mbed_official	324:406fd2029f23	2016	* All data received with the most significant bit set, is compared with
mbed_official	324:406fd2029f23	2017	* contents of MA1 register. If no match occurs, the data is discarded. If match
mbed_official	324:406fd2029f23	2018	* occurs, data is transferred to the data buffer. This field must be cleared
mbed_official	324:406fd2029f23	2019	* when C7816[ISO7816E] is set/enabled.
mbed_official	324:406fd2029f23	2020	*/
mbed_official	324:406fd2029f23	2021	/@{/
mbed_official	324:406fd2029f23	2022	#define BP_UART_C4_MAEN1 (7U) /!< Bit position for UART_C4_MAEN1. /
mbed_official	324:406fd2029f23	2023	#define BM_UART_C4_MAEN1 (0x80U) /!< Bit mask for UART_C4_MAEN1. /
mbed_official	324:406fd2029f23	2024	#define BS_UART_C4_MAEN1 (1U) /!< Bit field size in bits for UART_C4_MAEN1. /
mbed_official	324:406fd2029f23	2025
mbed_official	324:406fd2029f23	2026	/! @brief Read current value of the UART_C4_MAEN1 field. /
mbed_official	324:406fd2029f23	2027	#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
mbed_official	324:406fd2029f23	2028
mbed_official	324:406fd2029f23	2029	/! @brief Format value for bitfield UART_C4_MAEN1. /
mbed_official	324:406fd2029f23	2030	#define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1)
mbed_official	324:406fd2029f23	2031
mbed_official	324:406fd2029f23	2032	/! @brief Set the MAEN1 field to a new value. /
mbed_official	324:406fd2029f23	2033	#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
mbed_official	324:406fd2029f23	2034	/@}/
mbed_official	324:406fd2029f23	2035
mbed_official	324:406fd2029f23	2036	/*******************************************************************************
mbed_official	324:406fd2029f23	2037	* HW_UART_C5 - UART Control Register 5
mbed_official	324:406fd2029f23	2038	******************************************************************************/
mbed_official	324:406fd2029f23	2039
mbed_official	324:406fd2029f23	2040	/*!
mbed_official	324:406fd2029f23	2041	* @brief HW_UART_C5 - UART Control Register 5 (RW)
mbed_official	324:406fd2029f23	2042	*
mbed_official	324:406fd2029f23	2043	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2044	*/
mbed_official	324:406fd2029f23	2045	typedef union _hw_uart_c5
mbed_official	324:406fd2029f23	2046	{
mbed_official	324:406fd2029f23	2047	uint8_t U;
mbed_official	324:406fd2029f23	2048	struct _hw_uart_c5_bitfields
mbed_official	324:406fd2029f23	2049	{
mbed_official	324:406fd2029f23	2050	uint8_t RESERVED0 : 3; /!< [2:0] /
mbed_official	324:406fd2029f23	2051	uint8_t LBKDDMAS : 1; /!< [3] LIN Break Detect DMA Select Bit /
mbed_official	324:406fd2029f23	2052	uint8_t ILDMAS : 1; /!< [4] Idle Line DMA Select /
mbed_official	324:406fd2029f23	2053	uint8_t RDMAS : 1; /!< [5] Receiver Full DMA Select /
mbed_official	324:406fd2029f23	2054	uint8_t TCDMAS : 1; /!< [6] Transmission Complete DMA Select /
mbed_official	324:406fd2029f23	2055	uint8_t TDMAS : 1; /!< [7] Transmitter DMA Select /
mbed_official	324:406fd2029f23	2056	} B;
mbed_official	324:406fd2029f23	2057	} hw_uart_c5_t;
mbed_official	324:406fd2029f23	2058
mbed_official	324:406fd2029f23	2059	/*!
mbed_official	324:406fd2029f23	2060	* @name Constants and macros for entire UART_C5 register
mbed_official	324:406fd2029f23	2061	*/
mbed_official	324:406fd2029f23	2062	/@{/
mbed_official	324:406fd2029f23	2063	#define HW_UART_C5_ADDR(x) ((x) + 0xBU)
mbed_official	324:406fd2029f23	2064
mbed_official	324:406fd2029f23	2065	#define HW_UART_C5(x) ((__IO hw_uart_c5_t ) HW_UART_C5_ADDR(x))
mbed_official	324:406fd2029f23	2066	#define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
mbed_official	324:406fd2029f23	2067	#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
mbed_official	324:406fd2029f23	2068	#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2069	#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2070	#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2071	/@}/
mbed_official	324:406fd2029f23	2072
mbed_official	324:406fd2029f23	2073	/*
mbed_official	324:406fd2029f23	2074	* Constants & macros for individual UART_C5 bitfields
mbed_official	324:406fd2029f23	2075	*/
mbed_official	324:406fd2029f23	2076
mbed_official	324:406fd2029f23	2077	/*!
mbed_official	324:406fd2029f23	2078	* @name Register UART_C5, field LBKDDMAS[3] (RW)
mbed_official	324:406fd2029f23	2079	*
mbed_official	324:406fd2029f23	2080	* Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
mbed_official	324:406fd2029f23	2081	* DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
mbed_official	324:406fd2029f23	2082	* set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
mbed_official	324:406fd2029f23	2083	* of the state of LBKDDMAS.
mbed_official	324:406fd2029f23	2084	*
mbed_official	324:406fd2029f23	2085	* Values:
mbed_official	324:406fd2029f23	2086	* - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
mbed_official	324:406fd2029f23	2087	* asserted to request an interrupt service.
mbed_official	324:406fd2029f23	2088	* - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
mbed_official	324:406fd2029f23	2089	* asserted to request a DMA transfer.
mbed_official	324:406fd2029f23	2090	*/
mbed_official	324:406fd2029f23	2091	/@{/
mbed_official	324:406fd2029f23	2092	#define BP_UART_C5_LBKDDMAS (3U) /!< Bit position for UART_C5_LBKDDMAS. /
mbed_official	324:406fd2029f23	2093	#define BM_UART_C5_LBKDDMAS (0x08U) /!< Bit mask for UART_C5_LBKDDMAS. /
mbed_official	324:406fd2029f23	2094	#define BS_UART_C5_LBKDDMAS (1U) /!< Bit field size in bits for UART_C5_LBKDDMAS. /
mbed_official	324:406fd2029f23	2095
mbed_official	324:406fd2029f23	2096	/! @brief Read current value of the UART_C5_LBKDDMAS field. /
mbed_official	324:406fd2029f23	2097	#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
mbed_official	324:406fd2029f23	2098
mbed_official	324:406fd2029f23	2099	/! @brief Format value for bitfield UART_C5_LBKDDMAS. /
mbed_official	324:406fd2029f23	2100	#define BF_UART_C5_LBKDDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_LBKDDMAS) & BM_UART_C5_LBKDDMAS)
mbed_official	324:406fd2029f23	2101
mbed_official	324:406fd2029f23	2102	/! @brief Set the LBKDDMAS field to a new value. /
mbed_official	324:406fd2029f23	2103	#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
mbed_official	324:406fd2029f23	2104	/@}/
mbed_official	324:406fd2029f23	2105
mbed_official	324:406fd2029f23	2106	/*!
mbed_official	324:406fd2029f23	2107	* @name Register UART_C5, field ILDMAS[4] (RW)
mbed_official	324:406fd2029f23	2108	*
mbed_official	324:406fd2029f23	2109	* Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
mbed_official	324:406fd2029f23	2110	* requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
mbed_official	324:406fd2029f23	2111	* DMA and IDLE interrupt request signals are not asserted, regardless of the state
mbed_official	324:406fd2029f23	2112	* of ILDMAS.
mbed_official	324:406fd2029f23	2113	*
mbed_official	324:406fd2029f23	2114	* Values:
mbed_official	324:406fd2029f23	2115	* - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
mbed_official	324:406fd2029f23	2116	* asserted to request an interrupt service.
mbed_official	324:406fd2029f23	2117	* - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
mbed_official	324:406fd2029f23	2118	* asserted to request a DMA transfer.
mbed_official	324:406fd2029f23	2119	*/
mbed_official	324:406fd2029f23	2120	/@{/
mbed_official	324:406fd2029f23	2121	#define BP_UART_C5_ILDMAS (4U) /!< Bit position for UART_C5_ILDMAS. /
mbed_official	324:406fd2029f23	2122	#define BM_UART_C5_ILDMAS (0x10U) /!< Bit mask for UART_C5_ILDMAS. /
mbed_official	324:406fd2029f23	2123	#define BS_UART_C5_ILDMAS (1U) /!< Bit field size in bits for UART_C5_ILDMAS. /
mbed_official	324:406fd2029f23	2124
mbed_official	324:406fd2029f23	2125	/! @brief Read current value of the UART_C5_ILDMAS field. /
mbed_official	324:406fd2029f23	2126	#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
mbed_official	324:406fd2029f23	2127
mbed_official	324:406fd2029f23	2128	/! @brief Format value for bitfield UART_C5_ILDMAS. /
mbed_official	324:406fd2029f23	2129	#define BF_UART_C5_ILDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_ILDMAS) & BM_UART_C5_ILDMAS)
mbed_official	324:406fd2029f23	2130
mbed_official	324:406fd2029f23	2131	/! @brief Set the ILDMAS field to a new value. /
mbed_official	324:406fd2029f23	2132	#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
mbed_official	324:406fd2029f23	2133	/@}/
mbed_official	324:406fd2029f23	2134
mbed_official	324:406fd2029f23	2135	/*!
mbed_official	324:406fd2029f23	2136	* @name Register UART_C5, field RDMAS[5] (RW)
mbed_official	324:406fd2029f23	2137	*
mbed_official	324:406fd2029f23	2138	* Configures the receiver data register full flag, S1[RDRF], to generate
mbed_official	324:406fd2029f23	2139	* interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
mbed_official	324:406fd2029f23	2140	* set, the RDRF DMA and RDFR interrupt request signals are not asserted,
mbed_official	324:406fd2029f23	2141	* regardless of the state of RDMAS.
mbed_official	324:406fd2029f23	2142	*
mbed_official	324:406fd2029f23	2143	* Values:
mbed_official	324:406fd2029f23	2144	* - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
mbed_official	324:406fd2029f23	2145	* asserted to request an interrupt service.
mbed_official	324:406fd2029f23	2146	* - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
mbed_official	324:406fd2029f23	2147	* asserted to request a DMA transfer.
mbed_official	324:406fd2029f23	2148	*/
mbed_official	324:406fd2029f23	2149	/@{/
mbed_official	324:406fd2029f23	2150	#define BP_UART_C5_RDMAS (5U) /!< Bit position for UART_C5_RDMAS. /
mbed_official	324:406fd2029f23	2151	#define BM_UART_C5_RDMAS (0x20U) /!< Bit mask for UART_C5_RDMAS. /
mbed_official	324:406fd2029f23	2152	#define BS_UART_C5_RDMAS (1U) /!< Bit field size in bits for UART_C5_RDMAS. /
mbed_official	324:406fd2029f23	2153
mbed_official	324:406fd2029f23	2154	/! @brief Read current value of the UART_C5_RDMAS field. /
mbed_official	324:406fd2029f23	2155	#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
mbed_official	324:406fd2029f23	2156
mbed_official	324:406fd2029f23	2157	/! @brief Format value for bitfield UART_C5_RDMAS. /
mbed_official	324:406fd2029f23	2158	#define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS)
mbed_official	324:406fd2029f23	2159
mbed_official	324:406fd2029f23	2160	/! @brief Set the RDMAS field to a new value. /
mbed_official	324:406fd2029f23	2161	#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
mbed_official	324:406fd2029f23	2162	/@}/
mbed_official	324:406fd2029f23	2163
mbed_official	324:406fd2029f23	2164	/*!
mbed_official	324:406fd2029f23	2165	* @name Register UART_C5, field TCDMAS[6] (RW)
mbed_official	324:406fd2029f23	2166	*
mbed_official	324:406fd2029f23	2167	* Configures the transmission complete flag, S1[TC], to generate interrupt or
mbed_official	324:406fd2029f23	2168	* DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
mbed_official	324:406fd2029f23	2169	* interrupt request signals are not asserted when the S1[TC] flag is set, regardless
mbed_official	324:406fd2029f23	2170	* of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
mbed_official	324:406fd2029f23	2171	* must be cleared, and D must not be written unless a DMA request is being serviced.
mbed_official	324:406fd2029f23	2172	*
mbed_official	324:406fd2029f23	2173	* Values:
mbed_official	324:406fd2029f23	2174	* - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
mbed_official	324:406fd2029f23	2175	* signal is asserted to request an interrupt service.
mbed_official	324:406fd2029f23	2176	* - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
mbed_official	324:406fd2029f23	2177	* signal is asserted to request a DMA transfer.
mbed_official	324:406fd2029f23	2178	*/
mbed_official	324:406fd2029f23	2179	/@{/
mbed_official	324:406fd2029f23	2180	#define BP_UART_C5_TCDMAS (6U) /!< Bit position for UART_C5_TCDMAS. /
mbed_official	324:406fd2029f23	2181	#define BM_UART_C5_TCDMAS (0x40U) /!< Bit mask for UART_C5_TCDMAS. /
mbed_official	324:406fd2029f23	2182	#define BS_UART_C5_TCDMAS (1U) /!< Bit field size in bits for UART_C5_TCDMAS. /
mbed_official	324:406fd2029f23	2183
mbed_official	324:406fd2029f23	2184	/! @brief Read current value of the UART_C5_TCDMAS field. /
mbed_official	324:406fd2029f23	2185	#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
mbed_official	324:406fd2029f23	2186
mbed_official	324:406fd2029f23	2187	/! @brief Format value for bitfield UART_C5_TCDMAS. /
mbed_official	324:406fd2029f23	2188	#define BF_UART_C5_TCDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TCDMAS) & BM_UART_C5_TCDMAS)
mbed_official	324:406fd2029f23	2189
mbed_official	324:406fd2029f23	2190	/! @brief Set the TCDMAS field to a new value. /
mbed_official	324:406fd2029f23	2191	#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
mbed_official	324:406fd2029f23	2192	/@}/
mbed_official	324:406fd2029f23	2193
mbed_official	324:406fd2029f23	2194	/*!
mbed_official	324:406fd2029f23	2195	* @name Register UART_C5, field TDMAS[7] (RW)
mbed_official	324:406fd2029f23	2196	*
mbed_official	324:406fd2029f23	2197	* Configures the transmit data register empty flag, S1[TDRE], to generate
mbed_official	324:406fd2029f23	2198	* interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
mbed_official	324:406fd2029f23	2199	* TDRE interrupt request signals are not asserted when the TDRE flag is set,
mbed_official	324:406fd2029f23	2200	* regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
mbed_official	324:406fd2029f23	2201	* must be cleared, and D must not be written unless a DMA request is being
mbed_official	324:406fd2029f23	2202	* serviced.
mbed_official	324:406fd2029f23	2203	*
mbed_official	324:406fd2029f23	2204	* Values:
mbed_official	324:406fd2029f23	2205	* - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
mbed_official	324:406fd2029f23	2206	* request signal is asserted to request interrupt service.
mbed_official	324:406fd2029f23	2207	* - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
mbed_official	324:406fd2029f23	2208	* signal is asserted to request a DMA transfer.
mbed_official	324:406fd2029f23	2209	*/
mbed_official	324:406fd2029f23	2210	/@{/
mbed_official	324:406fd2029f23	2211	#define BP_UART_C5_TDMAS (7U) /!< Bit position for UART_C5_TDMAS. /
mbed_official	324:406fd2029f23	2212	#define BM_UART_C5_TDMAS (0x80U) /!< Bit mask for UART_C5_TDMAS. /
mbed_official	324:406fd2029f23	2213	#define BS_UART_C5_TDMAS (1U) /!< Bit field size in bits for UART_C5_TDMAS. /
mbed_official	324:406fd2029f23	2214
mbed_official	324:406fd2029f23	2215	/! @brief Read current value of the UART_C5_TDMAS field. /
mbed_official	324:406fd2029f23	2216	#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
mbed_official	324:406fd2029f23	2217
mbed_official	324:406fd2029f23	2218	/! @brief Format value for bitfield UART_C5_TDMAS. /
mbed_official	324:406fd2029f23	2219	#define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS)
mbed_official	324:406fd2029f23	2220
mbed_official	324:406fd2029f23	2221	/! @brief Set the TDMAS field to a new value. /
mbed_official	324:406fd2029f23	2222	#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
mbed_official	324:406fd2029f23	2223	/@}/
mbed_official	324:406fd2029f23	2224
mbed_official	324:406fd2029f23	2225	/*******************************************************************************
mbed_official	324:406fd2029f23	2226	* HW_UART_ED - UART Extended Data Register
mbed_official	324:406fd2029f23	2227	******************************************************************************/
mbed_official	324:406fd2029f23	2228
mbed_official	324:406fd2029f23	2229	/*!
mbed_official	324:406fd2029f23	2230	* @brief HW_UART_ED - UART Extended Data Register (RO)
mbed_official	324:406fd2029f23	2231	*
mbed_official	324:406fd2029f23	2232	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2233	*
mbed_official	324:406fd2029f23	2234	* This register contains additional information flags that are stored with a
mbed_official	324:406fd2029f23	2235	* received dataword. This register may be read at any time but contains valid data
mbed_official	324:406fd2029f23	2236	* only if there is a dataword in the receive FIFO. The data contained in this
mbed_official	324:406fd2029f23	2237	* register represents additional information regarding the conditions on which a
mbed_official	324:406fd2029f23	2238	* dataword was received. The importance of this data varies with the
mbed_official	324:406fd2029f23	2239	* application, and in some cases maybe completely optional. These fields automatically
mbed_official	324:406fd2029f23	2240	* update to reflect the conditions of the next dataword whenever D is read. If
mbed_official	324:406fd2029f23	2241	* S1[NF] and S1[PF] have not been set since the last time the receive buffer was
mbed_official	324:406fd2029f23	2242	* empty, the NOISY and PARITYE fields will be zero.
mbed_official	324:406fd2029f23	2243	*/
mbed_official	324:406fd2029f23	2244	typedef union _hw_uart_ed
mbed_official	324:406fd2029f23	2245	{
mbed_official	324:406fd2029f23	2246	uint8_t U;
mbed_official	324:406fd2029f23	2247	struct _hw_uart_ed_bitfields
mbed_official	324:406fd2029f23	2248	{
mbed_official	324:406fd2029f23	2249	uint8_t RESERVED0 : 6; /!< [5:0] /
mbed_official	324:406fd2029f23	2250	uint8_t PARITYE : 1; /!< [6] /
mbed_official	324:406fd2029f23	2251	uint8_t NOISY : 1; /!< [7] /
mbed_official	324:406fd2029f23	2252	} B;
mbed_official	324:406fd2029f23	2253	} hw_uart_ed_t;
mbed_official	324:406fd2029f23	2254
mbed_official	324:406fd2029f23	2255	/*!
mbed_official	324:406fd2029f23	2256	* @name Constants and macros for entire UART_ED register
mbed_official	324:406fd2029f23	2257	*/
mbed_official	324:406fd2029f23	2258	/@{/
mbed_official	324:406fd2029f23	2259	#define HW_UART_ED_ADDR(x) ((x) + 0xCU)
mbed_official	324:406fd2029f23	2260
mbed_official	324:406fd2029f23	2261	#define HW_UART_ED(x) ((__I hw_uart_ed_t ) HW_UART_ED_ADDR(x))
mbed_official	324:406fd2029f23	2262	#define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
mbed_official	324:406fd2029f23	2263	/@}/
mbed_official	324:406fd2029f23	2264
mbed_official	324:406fd2029f23	2265	/*
mbed_official	324:406fd2029f23	2266	* Constants & macros for individual UART_ED bitfields
mbed_official	324:406fd2029f23	2267	*/
mbed_official	324:406fd2029f23	2268
mbed_official	324:406fd2029f23	2269	/*!
mbed_official	324:406fd2029f23	2270	* @name Register UART_ED, field PARITYE[6] (RO)
mbed_official	324:406fd2029f23	2271	*
mbed_official	324:406fd2029f23	2272	* The current received dataword contained in D and C3[R8] was received with a
mbed_official	324:406fd2029f23	2273	* parity error.
mbed_official	324:406fd2029f23	2274	*
mbed_official	324:406fd2029f23	2275	* Values:
mbed_official	324:406fd2029f23	2276	* - 0 - The dataword was received without a parity error.
mbed_official	324:406fd2029f23	2277	* - 1 - The dataword was received with a parity error.
mbed_official	324:406fd2029f23	2278	*/
mbed_official	324:406fd2029f23	2279	/@{/
mbed_official	324:406fd2029f23	2280	#define BP_UART_ED_PARITYE (6U) /!< Bit position for UART_ED_PARITYE. /
mbed_official	324:406fd2029f23	2281	#define BM_UART_ED_PARITYE (0x40U) /!< Bit mask for UART_ED_PARITYE. /
mbed_official	324:406fd2029f23	2282	#define BS_UART_ED_PARITYE (1U) /!< Bit field size in bits for UART_ED_PARITYE. /
mbed_official	324:406fd2029f23	2283
mbed_official	324:406fd2029f23	2284	/! @brief Read current value of the UART_ED_PARITYE field. /
mbed_official	324:406fd2029f23	2285	#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
mbed_official	324:406fd2029f23	2286	/@}/
mbed_official	324:406fd2029f23	2287
mbed_official	324:406fd2029f23	2288	/*!
mbed_official	324:406fd2029f23	2289	* @name Register UART_ED, field NOISY[7] (RO)
mbed_official	324:406fd2029f23	2290	*
mbed_official	324:406fd2029f23	2291	* The current received dataword contained in D and C3[R8] was received with
mbed_official	324:406fd2029f23	2292	* noise.
mbed_official	324:406fd2029f23	2293	*
mbed_official	324:406fd2029f23	2294	* Values:
mbed_official	324:406fd2029f23	2295	* - 0 - The dataword was received without noise.
mbed_official	324:406fd2029f23	2296	* - 1 - The data was received with noise.
mbed_official	324:406fd2029f23	2297	*/
mbed_official	324:406fd2029f23	2298	/@{/
mbed_official	324:406fd2029f23	2299	#define BP_UART_ED_NOISY (7U) /!< Bit position for UART_ED_NOISY. /
mbed_official	324:406fd2029f23	2300	#define BM_UART_ED_NOISY (0x80U) /!< Bit mask for UART_ED_NOISY. /
mbed_official	324:406fd2029f23	2301	#define BS_UART_ED_NOISY (1U) /!< Bit field size in bits for UART_ED_NOISY. /
mbed_official	324:406fd2029f23	2302
mbed_official	324:406fd2029f23	2303	/! @brief Read current value of the UART_ED_NOISY field. /
mbed_official	324:406fd2029f23	2304	#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
mbed_official	324:406fd2029f23	2305	/@}/
mbed_official	324:406fd2029f23	2306
mbed_official	324:406fd2029f23	2307	/*******************************************************************************
mbed_official	324:406fd2029f23	2308	* HW_UART_MODEM - UART Modem Register
mbed_official	324:406fd2029f23	2309	******************************************************************************/
mbed_official	324:406fd2029f23	2310
mbed_official	324:406fd2029f23	2311	/*!
mbed_official	324:406fd2029f23	2312	* @brief HW_UART_MODEM - UART Modem Register (RW)
mbed_official	324:406fd2029f23	2313	*
mbed_official	324:406fd2029f23	2314	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2315	*
mbed_official	324:406fd2029f23	2316	* The MODEM register controls options for setting the modem configuration.
mbed_official	324:406fd2029f23	2317	* RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
mbed_official	324:406fd2029f23	2318	* enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
mbed_official	324:406fd2029f23	2319	* ISO-7816 protocol does not use the RTS and CTS signals.
mbed_official	324:406fd2029f23	2320	*/
mbed_official	324:406fd2029f23	2321	typedef union _hw_uart_modem
mbed_official	324:406fd2029f23	2322	{
mbed_official	324:406fd2029f23	2323	uint8_t U;
mbed_official	324:406fd2029f23	2324	struct _hw_uart_modem_bitfields
mbed_official	324:406fd2029f23	2325	{
mbed_official	324:406fd2029f23	2326	uint8_t TXCTSE : 1; /!< [0] Transmitter clear-to-send enable /
mbed_official	324:406fd2029f23	2327	uint8_t TXRTSE : 1; /!< [1] Transmitter request-to-send enable /
mbed_official	324:406fd2029f23	2328	uint8_t TXRTSPOL : 1; /!< [2] Transmitter request-to-send polarity /
mbed_official	324:406fd2029f23	2329	uint8_t RXRTSE : 1; /!< [3] Receiver request-to-send enable /
mbed_official	324:406fd2029f23	2330	uint8_t RESERVED0 : 4; /!< [7:4] /
mbed_official	324:406fd2029f23	2331	} B;
mbed_official	324:406fd2029f23	2332	} hw_uart_modem_t;
mbed_official	324:406fd2029f23	2333
mbed_official	324:406fd2029f23	2334	/*!
mbed_official	324:406fd2029f23	2335	* @name Constants and macros for entire UART_MODEM register
mbed_official	324:406fd2029f23	2336	*/
mbed_official	324:406fd2029f23	2337	/@{/
mbed_official	324:406fd2029f23	2338	#define HW_UART_MODEM_ADDR(x) ((x) + 0xDU)
mbed_official	324:406fd2029f23	2339
mbed_official	324:406fd2029f23	2340	#define HW_UART_MODEM(x) ((__IO hw_uart_modem_t ) HW_UART_MODEM_ADDR(x))
mbed_official	324:406fd2029f23	2341	#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
mbed_official	324:406fd2029f23	2342	#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
mbed_official	324:406fd2029f23	2343	#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2344	#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2345	#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2346	/@}/
mbed_official	324:406fd2029f23	2347
mbed_official	324:406fd2029f23	2348	/*
mbed_official	324:406fd2029f23	2349	* Constants & macros for individual UART_MODEM bitfields
mbed_official	324:406fd2029f23	2350	*/
mbed_official	324:406fd2029f23	2351
mbed_official	324:406fd2029f23	2352	/*!
mbed_official	324:406fd2029f23	2353	* @name Register UART_MODEM, field TXCTSE[0] (RW)
mbed_official	324:406fd2029f23	2354	*
mbed_official	324:406fd2029f23	2355	* TXCTSE controls the operation of the transmitter. TXCTSE can be set
mbed_official	324:406fd2029f23	2356	* independently from the state of TXRTSE and RXRTSE.
mbed_official	324:406fd2029f23	2357	*
mbed_official	324:406fd2029f23	2358	* Values:
mbed_official	324:406fd2029f23	2359	* - 0 - CTS has no effect on the transmitter.
mbed_official	324:406fd2029f23	2360	* - 1 - Enables clear-to-send operation. The transmitter checks the state of
mbed_official	324:406fd2029f23	2361	* CTS each time it is ready to send a character. If CTS is asserted, the
mbed_official	324:406fd2029f23	2362	* character is sent. If CTS is deasserted, the signal TXD remains in the mark
mbed_official	324:406fd2029f23	2363	* state and transmission is delayed until CTS is asserted. Changes in CTS as a
mbed_official	324:406fd2029f23	2364	* character is being sent do not affect its transmission.
mbed_official	324:406fd2029f23	2365	*/
mbed_official	324:406fd2029f23	2366	/@{/
mbed_official	324:406fd2029f23	2367	#define BP_UART_MODEM_TXCTSE (0U) /!< Bit position for UART_MODEM_TXCTSE. /
mbed_official	324:406fd2029f23	2368	#define BM_UART_MODEM_TXCTSE (0x01U) /!< Bit mask for UART_MODEM_TXCTSE. /
mbed_official	324:406fd2029f23	2369	#define BS_UART_MODEM_TXCTSE (1U) /!< Bit field size in bits for UART_MODEM_TXCTSE. /
mbed_official	324:406fd2029f23	2370
mbed_official	324:406fd2029f23	2371	/! @brief Read current value of the UART_MODEM_TXCTSE field. /
mbed_official	324:406fd2029f23	2372	#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
mbed_official	324:406fd2029f23	2373
mbed_official	324:406fd2029f23	2374	/! @brief Format value for bitfield UART_MODEM_TXCTSE. /
mbed_official	324:406fd2029f23	2375	#define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE)
mbed_official	324:406fd2029f23	2376
mbed_official	324:406fd2029f23	2377	/! @brief Set the TXCTSE field to a new value. /
mbed_official	324:406fd2029f23	2378	#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
mbed_official	324:406fd2029f23	2379	/@}/
mbed_official	324:406fd2029f23	2380
mbed_official	324:406fd2029f23	2381	/*!
mbed_official	324:406fd2029f23	2382	* @name Register UART_MODEM, field TXRTSE[1] (RW)
mbed_official	324:406fd2029f23	2383	*
mbed_official	324:406fd2029f23	2384	* Controls RTS before and after a transmission.
mbed_official	324:406fd2029f23	2385	*
mbed_official	324:406fd2029f23	2386	* Values:
mbed_official	324:406fd2029f23	2387	* - 0 - The transmitter has no effect on RTS.
mbed_official	324:406fd2029f23	2388	* - 1 - When a character is placed into an empty transmitter data buffer , RTS
mbed_official	324:406fd2029f23	2389	* asserts one bit time before the start bit is transmitted. RTS deasserts
mbed_official	324:406fd2029f23	2390	* one bit time after all characters in the transmitter data buffer and shift
mbed_official	324:406fd2029f23	2391	* register are completely sent, including the last stop bit. (FIFO) (FIFO)
mbed_official	324:406fd2029f23	2392	*/
mbed_official	324:406fd2029f23	2393	/@{/
mbed_official	324:406fd2029f23	2394	#define BP_UART_MODEM_TXRTSE (1U) /!< Bit position for UART_MODEM_TXRTSE. /
mbed_official	324:406fd2029f23	2395	#define BM_UART_MODEM_TXRTSE (0x02U) /!< Bit mask for UART_MODEM_TXRTSE. /
mbed_official	324:406fd2029f23	2396	#define BS_UART_MODEM_TXRTSE (1U) /!< Bit field size in bits for UART_MODEM_TXRTSE. /
mbed_official	324:406fd2029f23	2397
mbed_official	324:406fd2029f23	2398	/! @brief Read current value of the UART_MODEM_TXRTSE field. /
mbed_official	324:406fd2029f23	2399	#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
mbed_official	324:406fd2029f23	2400
mbed_official	324:406fd2029f23	2401	/! @brief Format value for bitfield UART_MODEM_TXRTSE. /
mbed_official	324:406fd2029f23	2402	#define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE)
mbed_official	324:406fd2029f23	2403
mbed_official	324:406fd2029f23	2404	/! @brief Set the TXRTSE field to a new value. /
mbed_official	324:406fd2029f23	2405	#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
mbed_official	324:406fd2029f23	2406	/@}/
mbed_official	324:406fd2029f23	2407
mbed_official	324:406fd2029f23	2408	/*!
mbed_official	324:406fd2029f23	2409	* @name Register UART_MODEM, field TXRTSPOL[2] (RW)
mbed_official	324:406fd2029f23	2410	*
mbed_official	324:406fd2029f23	2411	* Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
mbed_official	324:406fd2029f23	2412	* polarity of the receiver RTS. RTS will remain negated in the active low state
mbed_official	324:406fd2029f23	2413	* unless TXRTSE is set.
mbed_official	324:406fd2029f23	2414	*
mbed_official	324:406fd2029f23	2415	* Values:
mbed_official	324:406fd2029f23	2416	* - 0 - Transmitter RTS is active low.
mbed_official	324:406fd2029f23	2417	* - 1 - Transmitter RTS is active high.
mbed_official	324:406fd2029f23	2418	*/
mbed_official	324:406fd2029f23	2419	/@{/
mbed_official	324:406fd2029f23	2420	#define BP_UART_MODEM_TXRTSPOL (2U) /!< Bit position for UART_MODEM_TXRTSPOL. /
mbed_official	324:406fd2029f23	2421	#define BM_UART_MODEM_TXRTSPOL (0x04U) /!< Bit mask for UART_MODEM_TXRTSPOL. /
mbed_official	324:406fd2029f23	2422	#define BS_UART_MODEM_TXRTSPOL (1U) /!< Bit field size in bits for UART_MODEM_TXRTSPOL. /
mbed_official	324:406fd2029f23	2423
mbed_official	324:406fd2029f23	2424	/! @brief Read current value of the UART_MODEM_TXRTSPOL field. /
mbed_official	324:406fd2029f23	2425	#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
mbed_official	324:406fd2029f23	2426
mbed_official	324:406fd2029f23	2427	/! @brief Format value for bitfield UART_MODEM_TXRTSPOL. /
mbed_official	324:406fd2029f23	2428	#define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL)
mbed_official	324:406fd2029f23	2429
mbed_official	324:406fd2029f23	2430	/! @brief Set the TXRTSPOL field to a new value. /
mbed_official	324:406fd2029f23	2431	#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
mbed_official	324:406fd2029f23	2432	/@}/
mbed_official	324:406fd2029f23	2433
mbed_official	324:406fd2029f23	2434	/*!
mbed_official	324:406fd2029f23	2435	* @name Register UART_MODEM, field RXRTSE[3] (RW)
mbed_official	324:406fd2029f23	2436	*
mbed_official	324:406fd2029f23	2437	* Allows the RTS output to control the CTS input of the transmitting device to
mbed_official	324:406fd2029f23	2438	* prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
mbed_official	324:406fd2029f23	2439	*
mbed_official	324:406fd2029f23	2440	* Values:
mbed_official	324:406fd2029f23	2441	* - 0 - The receiver has no effect on RTS.
mbed_official	324:406fd2029f23	2442	* - 1 - RTS is deasserted if the number of characters in the receiver data
mbed_official	324:406fd2029f23	2443	* register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
mbed_official	324:406fd2029f23	2444	* when the number of characters in the receiver data register (FIFO) is less
mbed_official	324:406fd2029f23	2445	* than RWFIFO[RXWATER].
mbed_official	324:406fd2029f23	2446	*/
mbed_official	324:406fd2029f23	2447	/@{/
mbed_official	324:406fd2029f23	2448	#define BP_UART_MODEM_RXRTSE (3U) /!< Bit position for UART_MODEM_RXRTSE. /
mbed_official	324:406fd2029f23	2449	#define BM_UART_MODEM_RXRTSE (0x08U) /!< Bit mask for UART_MODEM_RXRTSE. /
mbed_official	324:406fd2029f23	2450	#define BS_UART_MODEM_RXRTSE (1U) /!< Bit field size in bits for UART_MODEM_RXRTSE. /
mbed_official	324:406fd2029f23	2451
mbed_official	324:406fd2029f23	2452	/! @brief Read current value of the UART_MODEM_RXRTSE field. /
mbed_official	324:406fd2029f23	2453	#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
mbed_official	324:406fd2029f23	2454
mbed_official	324:406fd2029f23	2455	/! @brief Format value for bitfield UART_MODEM_RXRTSE. /
mbed_official	324:406fd2029f23	2456	#define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE)
mbed_official	324:406fd2029f23	2457
mbed_official	324:406fd2029f23	2458	/! @brief Set the RXRTSE field to a new value. /
mbed_official	324:406fd2029f23	2459	#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
mbed_official	324:406fd2029f23	2460	/@}/
mbed_official	324:406fd2029f23	2461
mbed_official	324:406fd2029f23	2462	/*******************************************************************************
mbed_official	324:406fd2029f23	2463	* HW_UART_IR - UART Infrared Register
mbed_official	324:406fd2029f23	2464	******************************************************************************/
mbed_official	324:406fd2029f23	2465
mbed_official	324:406fd2029f23	2466	/*!
mbed_official	324:406fd2029f23	2467	* @brief HW_UART_IR - UART Infrared Register (RW)
mbed_official	324:406fd2029f23	2468	*
mbed_official	324:406fd2029f23	2469	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2470	*
mbed_official	324:406fd2029f23	2471	* The IR register controls options for setting the infrared configuration.
mbed_official	324:406fd2029f23	2472	*/
mbed_official	324:406fd2029f23	2473	typedef union _hw_uart_ir
mbed_official	324:406fd2029f23	2474	{
mbed_official	324:406fd2029f23	2475	uint8_t U;
mbed_official	324:406fd2029f23	2476	struct _hw_uart_ir_bitfields
mbed_official	324:406fd2029f23	2477	{
mbed_official	324:406fd2029f23	2478	uint8_t TNP : 2; /!< [1:0] Transmitter narrow pulse /
mbed_official	324:406fd2029f23	2479	uint8_t IREN : 1; /!< [2] Infrared enable /
mbed_official	324:406fd2029f23	2480	uint8_t RESERVED0 : 5; /!< [7:3] /
mbed_official	324:406fd2029f23	2481	} B;
mbed_official	324:406fd2029f23	2482	} hw_uart_ir_t;
mbed_official	324:406fd2029f23	2483
mbed_official	324:406fd2029f23	2484	/*!
mbed_official	324:406fd2029f23	2485	* @name Constants and macros for entire UART_IR register
mbed_official	324:406fd2029f23	2486	*/
mbed_official	324:406fd2029f23	2487	/@{/
mbed_official	324:406fd2029f23	2488	#define HW_UART_IR_ADDR(x) ((x) + 0xEU)
mbed_official	324:406fd2029f23	2489
mbed_official	324:406fd2029f23	2490	#define HW_UART_IR(x) ((__IO hw_uart_ir_t ) HW_UART_IR_ADDR(x))
mbed_official	324:406fd2029f23	2491	#define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
mbed_official	324:406fd2029f23	2492	#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
mbed_official	324:406fd2029f23	2493	#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2494	#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2495	#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2496	/@}/
mbed_official	324:406fd2029f23	2497
mbed_official	324:406fd2029f23	2498	/*
mbed_official	324:406fd2029f23	2499	* Constants & macros for individual UART_IR bitfields
mbed_official	324:406fd2029f23	2500	*/
mbed_official	324:406fd2029f23	2501
mbed_official	324:406fd2029f23	2502	/*!
mbed_official	324:406fd2029f23	2503	* @name Register UART_IR, field TNP[1:0] (RW)
mbed_official	324:406fd2029f23	2504	*
mbed_official	324:406fd2029f23	2505	* Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
mbed_official	324:406fd2029f23	2506	*
mbed_official	324:406fd2029f23	2507	* Values:
mbed_official	324:406fd2029f23	2508	* - 00 - 3/16.
mbed_official	324:406fd2029f23	2509	* - 01 - 1/16.
mbed_official	324:406fd2029f23	2510	* - 10 - 1/32.
mbed_official	324:406fd2029f23	2511	* - 11 - 1/4.
mbed_official	324:406fd2029f23	2512	*/
mbed_official	324:406fd2029f23	2513	/@{/
mbed_official	324:406fd2029f23	2514	#define BP_UART_IR_TNP (0U) /!< Bit position for UART_IR_TNP. /
mbed_official	324:406fd2029f23	2515	#define BM_UART_IR_TNP (0x03U) /!< Bit mask for UART_IR_TNP. /
mbed_official	324:406fd2029f23	2516	#define BS_UART_IR_TNP (2U) /!< Bit field size in bits for UART_IR_TNP. /
mbed_official	324:406fd2029f23	2517
mbed_official	324:406fd2029f23	2518	/! @brief Read current value of the UART_IR_TNP field. /
mbed_official	324:406fd2029f23	2519	#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
mbed_official	324:406fd2029f23	2520
mbed_official	324:406fd2029f23	2521	/! @brief Format value for bitfield UART_IR_TNP. /
mbed_official	324:406fd2029f23	2522	#define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP)
mbed_official	324:406fd2029f23	2523
mbed_official	324:406fd2029f23	2524	/! @brief Set the TNP field to a new value. /
mbed_official	324:406fd2029f23	2525	#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) \| BF_UART_IR_TNP(v)))
mbed_official	324:406fd2029f23	2526	/@}/
mbed_official	324:406fd2029f23	2527
mbed_official	324:406fd2029f23	2528	/*!
mbed_official	324:406fd2029f23	2529	* @name Register UART_IR, field IREN[2] (RW)
mbed_official	324:406fd2029f23	2530	*
mbed_official	324:406fd2029f23	2531	* Enables/disables the infrared modulation/demodulation.
mbed_official	324:406fd2029f23	2532	*
mbed_official	324:406fd2029f23	2533	* Values:
mbed_official	324:406fd2029f23	2534	* - 0 - IR disabled.
mbed_official	324:406fd2029f23	2535	* - 1 - IR enabled.
mbed_official	324:406fd2029f23	2536	*/
mbed_official	324:406fd2029f23	2537	/@{/
mbed_official	324:406fd2029f23	2538	#define BP_UART_IR_IREN (2U) /!< Bit position for UART_IR_IREN. /
mbed_official	324:406fd2029f23	2539	#define BM_UART_IR_IREN (0x04U) /!< Bit mask for UART_IR_IREN. /
mbed_official	324:406fd2029f23	2540	#define BS_UART_IR_IREN (1U) /!< Bit field size in bits for UART_IR_IREN. /
mbed_official	324:406fd2029f23	2541
mbed_official	324:406fd2029f23	2542	/! @brief Read current value of the UART_IR_IREN field. /
mbed_official	324:406fd2029f23	2543	#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
mbed_official	324:406fd2029f23	2544
mbed_official	324:406fd2029f23	2545	/! @brief Format value for bitfield UART_IR_IREN. /
mbed_official	324:406fd2029f23	2546	#define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN)
mbed_official	324:406fd2029f23	2547
mbed_official	324:406fd2029f23	2548	/! @brief Set the IREN field to a new value. /
mbed_official	324:406fd2029f23	2549	#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
mbed_official	324:406fd2029f23	2550	/@}/
mbed_official	324:406fd2029f23	2551
mbed_official	324:406fd2029f23	2552	/*******************************************************************************
mbed_official	324:406fd2029f23	2553	* HW_UART_PFIFO - UART FIFO Parameters
mbed_official	324:406fd2029f23	2554	******************************************************************************/
mbed_official	324:406fd2029f23	2555
mbed_official	324:406fd2029f23	2556	/*!
mbed_official	324:406fd2029f23	2557	* @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
mbed_official	324:406fd2029f23	2558	*
mbed_official	324:406fd2029f23	2559	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2560	*
mbed_official	324:406fd2029f23	2561	* This register provides the ability for the programmer to turn on and off FIFO
mbed_official	324:406fd2029f23	2562	* functionality. It also provides the size of the FIFO that has been
mbed_official	324:406fd2029f23	2563	* implemented. This register may be read at any time. This register must be written only
mbed_official	324:406fd2029f23	2564	* when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
mbed_official	324:406fd2029f23	2565	* empty.
mbed_official	324:406fd2029f23	2566	*/
mbed_official	324:406fd2029f23	2567	typedef union _hw_uart_pfifo
mbed_official	324:406fd2029f23	2568	{
mbed_official	324:406fd2029f23	2569	uint8_t U;
mbed_official	324:406fd2029f23	2570	struct _hw_uart_pfifo_bitfields
mbed_official	324:406fd2029f23	2571	{
mbed_official	324:406fd2029f23	2572	uint8_t RXFIFOSIZE : 3; /!< [2:0] Receive FIFO. Buffer Depth /
mbed_official	324:406fd2029f23	2573	uint8_t RXFE : 1; /!< [3] Receive FIFO Enable /
mbed_official	324:406fd2029f23	2574	uint8_t TXFIFOSIZE : 3; /!< [6:4] Transmit FIFO. Buffer Depth /
mbed_official	324:406fd2029f23	2575	uint8_t TXFE : 1; /!< [7] Transmit FIFO Enable /
mbed_official	324:406fd2029f23	2576	} B;
mbed_official	324:406fd2029f23	2577	} hw_uart_pfifo_t;
mbed_official	324:406fd2029f23	2578
mbed_official	324:406fd2029f23	2579	/*!
mbed_official	324:406fd2029f23	2580	* @name Constants and macros for entire UART_PFIFO register
mbed_official	324:406fd2029f23	2581	*/
mbed_official	324:406fd2029f23	2582	/@{/
mbed_official	324:406fd2029f23	2583	#define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U)
mbed_official	324:406fd2029f23	2584
mbed_official	324:406fd2029f23	2585	#define HW_UART_PFIFO(x) ((__IO hw_uart_pfifo_t ) HW_UART_PFIFO_ADDR(x))
mbed_official	324:406fd2029f23	2586	#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
mbed_official	324:406fd2029f23	2587	#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
mbed_official	324:406fd2029f23	2588	#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2589	#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2590	#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2591	/@}/
mbed_official	324:406fd2029f23	2592
mbed_official	324:406fd2029f23	2593	/*
mbed_official	324:406fd2029f23	2594	* Constants & macros for individual UART_PFIFO bitfields
mbed_official	324:406fd2029f23	2595	*/
mbed_official	324:406fd2029f23	2596
mbed_official	324:406fd2029f23	2597	/*!
mbed_official	324:406fd2029f23	2598	* @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
mbed_official	324:406fd2029f23	2599	*
mbed_official	324:406fd2029f23	2600	* The maximum number of receive datawords that can be stored in the receive
mbed_official	324:406fd2029f23	2601	* buffer before an overrun occurs. This field is read only.
mbed_official	324:406fd2029f23	2602	*
mbed_official	324:406fd2029f23	2603	* Values:
mbed_official	324:406fd2029f23	2604	* - 000 - Receive FIFO/Buffer depth = 1 dataword.
mbed_official	324:406fd2029f23	2605	* - 001 - Receive FIFO/Buffer depth = 4 datawords.
mbed_official	324:406fd2029f23	2606	* - 010 - Receive FIFO/Buffer depth = 8 datawords.
mbed_official	324:406fd2029f23	2607	* - 011 - Receive FIFO/Buffer depth = 16 datawords.
mbed_official	324:406fd2029f23	2608	* - 100 - Receive FIFO/Buffer depth = 32 datawords.
mbed_official	324:406fd2029f23	2609	* - 101 - Receive FIFO/Buffer depth = 64 datawords.
mbed_official	324:406fd2029f23	2610	* - 110 - Receive FIFO/Buffer depth = 128 datawords.
mbed_official	324:406fd2029f23	2611	* - 111 - Reserved.
mbed_official	324:406fd2029f23	2612	*/
mbed_official	324:406fd2029f23	2613	/@{/
mbed_official	324:406fd2029f23	2614	#define BP_UART_PFIFO_RXFIFOSIZE (0U) /!< Bit position for UART_PFIFO_RXFIFOSIZE. /
mbed_official	324:406fd2029f23	2615	#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /!< Bit mask for UART_PFIFO_RXFIFOSIZE. /
mbed_official	324:406fd2029f23	2616	#define BS_UART_PFIFO_RXFIFOSIZE (3U) /!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. /
mbed_official	324:406fd2029f23	2617
mbed_official	324:406fd2029f23	2618	/! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. /
mbed_official	324:406fd2029f23	2619	#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
mbed_official	324:406fd2029f23	2620	/@}/
mbed_official	324:406fd2029f23	2621
mbed_official	324:406fd2029f23	2622	/*!
mbed_official	324:406fd2029f23	2623	* @name Register UART_PFIFO, field RXFE[3] (RW)
mbed_official	324:406fd2029f23	2624	*
mbed_official	324:406fd2029f23	2625	* When this field is set, the built in FIFO structure for the receive buffer is
mbed_official	324:406fd2029f23	2626	* enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
mbed_official	324:406fd2029f23	2627	* If this field is not set, the receive buffer operates as a FIFO of depth one
mbed_official	324:406fd2029f23	2628	* dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
mbed_official	324:406fd2029f23	2629	* cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
mbed_official	324:406fd2029f23	2630	* commands must be issued immediately after changing this field.
mbed_official	324:406fd2029f23	2631	*
mbed_official	324:406fd2029f23	2632	* Values:
mbed_official	324:406fd2029f23	2633	* - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
mbed_official	324:406fd2029f23	2634	* - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
mbed_official	324:406fd2029f23	2635	*/
mbed_official	324:406fd2029f23	2636	/@{/
mbed_official	324:406fd2029f23	2637	#define BP_UART_PFIFO_RXFE (3U) /!< Bit position for UART_PFIFO_RXFE. /
mbed_official	324:406fd2029f23	2638	#define BM_UART_PFIFO_RXFE (0x08U) /!< Bit mask for UART_PFIFO_RXFE. /
mbed_official	324:406fd2029f23	2639	#define BS_UART_PFIFO_RXFE (1U) /!< Bit field size in bits for UART_PFIFO_RXFE. /
mbed_official	324:406fd2029f23	2640
mbed_official	324:406fd2029f23	2641	/! @brief Read current value of the UART_PFIFO_RXFE field. /
mbed_official	324:406fd2029f23	2642	#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
mbed_official	324:406fd2029f23	2643
mbed_official	324:406fd2029f23	2644	/! @brief Format value for bitfield UART_PFIFO_RXFE. /
mbed_official	324:406fd2029f23	2645	#define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE)
mbed_official	324:406fd2029f23	2646
mbed_official	324:406fd2029f23	2647	/! @brief Set the RXFE field to a new value. /
mbed_official	324:406fd2029f23	2648	#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
mbed_official	324:406fd2029f23	2649	/@}/
mbed_official	324:406fd2029f23	2650
mbed_official	324:406fd2029f23	2651	/*!
mbed_official	324:406fd2029f23	2652	* @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
mbed_official	324:406fd2029f23	2653	*
mbed_official	324:406fd2029f23	2654	* The maximum number of transmit datawords that can be stored in the transmit
mbed_official	324:406fd2029f23	2655	* buffer. This field is read only.
mbed_official	324:406fd2029f23	2656	*
mbed_official	324:406fd2029f23	2657	* Values:
mbed_official	324:406fd2029f23	2658	* - 000 - Transmit FIFO/Buffer depth = 1 dataword.
mbed_official	324:406fd2029f23	2659	* - 001 - Transmit FIFO/Buffer depth = 4 datawords.
mbed_official	324:406fd2029f23	2660	* - 010 - Transmit FIFO/Buffer depth = 8 datawords.
mbed_official	324:406fd2029f23	2661	* - 011 - Transmit FIFO/Buffer depth = 16 datawords.
mbed_official	324:406fd2029f23	2662	* - 100 - Transmit FIFO/Buffer depth = 32 datawords.
mbed_official	324:406fd2029f23	2663	* - 101 - Transmit FIFO/Buffer depth = 64 datawords.
mbed_official	324:406fd2029f23	2664	* - 110 - Transmit FIFO/Buffer depth = 128 datawords.
mbed_official	324:406fd2029f23	2665	* - 111 - Reserved.
mbed_official	324:406fd2029f23	2666	*/
mbed_official	324:406fd2029f23	2667	/@{/
mbed_official	324:406fd2029f23	2668	#define BP_UART_PFIFO_TXFIFOSIZE (4U) /!< Bit position for UART_PFIFO_TXFIFOSIZE. /
mbed_official	324:406fd2029f23	2669	#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /!< Bit mask for UART_PFIFO_TXFIFOSIZE. /
mbed_official	324:406fd2029f23	2670	#define BS_UART_PFIFO_TXFIFOSIZE (3U) /!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. /
mbed_official	324:406fd2029f23	2671
mbed_official	324:406fd2029f23	2672	/! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. /
mbed_official	324:406fd2029f23	2673	#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
mbed_official	324:406fd2029f23	2674	/@}/
mbed_official	324:406fd2029f23	2675
mbed_official	324:406fd2029f23	2676	/*!
mbed_official	324:406fd2029f23	2677	* @name Register UART_PFIFO, field TXFE[7] (RW)
mbed_official	324:406fd2029f23	2678	*
mbed_official	324:406fd2029f23	2679	* When this field is set, the built in FIFO structure for the transmit buffer
mbed_official	324:406fd2029f23	2680	* is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
mbed_official	324:406fd2029f23	2681	* field is not set, the transmit buffer operates as a FIFO of depth one dataword
mbed_official	324:406fd2029f23	2682	* regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
mbed_official	324:406fd2029f23	2683	* prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
mbed_official	324:406fd2029f23	2684	* be issued immediately after changing this field.
mbed_official	324:406fd2029f23	2685	*
mbed_official	324:406fd2029f23	2686	* Values:
mbed_official	324:406fd2029f23	2687	* - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
mbed_official	324:406fd2029f23	2688	* - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
mbed_official	324:406fd2029f23	2689	*/
mbed_official	324:406fd2029f23	2690	/@{/
mbed_official	324:406fd2029f23	2691	#define BP_UART_PFIFO_TXFE (7U) /!< Bit position for UART_PFIFO_TXFE. /
mbed_official	324:406fd2029f23	2692	#define BM_UART_PFIFO_TXFE (0x80U) /!< Bit mask for UART_PFIFO_TXFE. /
mbed_official	324:406fd2029f23	2693	#define BS_UART_PFIFO_TXFE (1U) /!< Bit field size in bits for UART_PFIFO_TXFE. /
mbed_official	324:406fd2029f23	2694
mbed_official	324:406fd2029f23	2695	/! @brief Read current value of the UART_PFIFO_TXFE field. /
mbed_official	324:406fd2029f23	2696	#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
mbed_official	324:406fd2029f23	2697
mbed_official	324:406fd2029f23	2698	/! @brief Format value for bitfield UART_PFIFO_TXFE. /
mbed_official	324:406fd2029f23	2699	#define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE)
mbed_official	324:406fd2029f23	2700
mbed_official	324:406fd2029f23	2701	/! @brief Set the TXFE field to a new value. /
mbed_official	324:406fd2029f23	2702	#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
mbed_official	324:406fd2029f23	2703	/@}/
mbed_official	324:406fd2029f23	2704
mbed_official	324:406fd2029f23	2705	/*******************************************************************************
mbed_official	324:406fd2029f23	2706	* HW_UART_CFIFO - UART FIFO Control Register
mbed_official	324:406fd2029f23	2707	******************************************************************************/
mbed_official	324:406fd2029f23	2708
mbed_official	324:406fd2029f23	2709	/*!
mbed_official	324:406fd2029f23	2710	* @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
mbed_official	324:406fd2029f23	2711	*
mbed_official	324:406fd2029f23	2712	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2713	*
mbed_official	324:406fd2029f23	2714	* This register provides the ability to program various control fields for FIFO
mbed_official	324:406fd2029f23	2715	* operation. This register may be read or written at any time. Note that
mbed_official	324:406fd2029f23	2716	* writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
mbed_official	324:406fd2029f23	2717	* to prevent unintended/unpredictable behavior. Therefore, it is recommended that
mbed_official	324:406fd2029f23	2718	* TE and RE be cleared prior to flushing the corresponding FIFO.
mbed_official	324:406fd2029f23	2719	*/
mbed_official	324:406fd2029f23	2720	typedef union _hw_uart_cfifo
mbed_official	324:406fd2029f23	2721	{
mbed_official	324:406fd2029f23	2722	uint8_t U;
mbed_official	324:406fd2029f23	2723	struct _hw_uart_cfifo_bitfields
mbed_official	324:406fd2029f23	2724	{
mbed_official	324:406fd2029f23	2725	uint8_t RXUFE : 1; /!< [0] Receive FIFO Underflow Interrupt Enable /
mbed_official	324:406fd2029f23	2726	uint8_t TXOFE : 1; /!< [1] Transmit FIFO Overflow Interrupt Enable /
mbed_official	324:406fd2029f23	2727	uint8_t RXOFE : 1; /!< [2] Receive FIFO Overflow Interrupt Enable /
mbed_official	324:406fd2029f23	2728	uint8_t RESERVED0 : 3; /!< [5:3] /
mbed_official	324:406fd2029f23	2729	uint8_t RXFLUSH : 1; /!< [6] Receive FIFO/Buffer Flush /
mbed_official	324:406fd2029f23	2730	uint8_t TXFLUSH : 1; /!< [7] Transmit FIFO/Buffer Flush /
mbed_official	324:406fd2029f23	2731	} B;
mbed_official	324:406fd2029f23	2732	} hw_uart_cfifo_t;
mbed_official	324:406fd2029f23	2733
mbed_official	324:406fd2029f23	2734	/*!
mbed_official	324:406fd2029f23	2735	* @name Constants and macros for entire UART_CFIFO register
mbed_official	324:406fd2029f23	2736	*/
mbed_official	324:406fd2029f23	2737	/@{/
mbed_official	324:406fd2029f23	2738	#define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U)
mbed_official	324:406fd2029f23	2739
mbed_official	324:406fd2029f23	2740	#define HW_UART_CFIFO(x) ((__IO hw_uart_cfifo_t ) HW_UART_CFIFO_ADDR(x))
mbed_official	324:406fd2029f23	2741	#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
mbed_official	324:406fd2029f23	2742	#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
mbed_official	324:406fd2029f23	2743	#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2744	#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2745	#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2746	/@}/
mbed_official	324:406fd2029f23	2747
mbed_official	324:406fd2029f23	2748	/*
mbed_official	324:406fd2029f23	2749	* Constants & macros for individual UART_CFIFO bitfields
mbed_official	324:406fd2029f23	2750	*/
mbed_official	324:406fd2029f23	2751
mbed_official	324:406fd2029f23	2752	/*!
mbed_official	324:406fd2029f23	2753	* @name Register UART_CFIFO, field RXUFE[0] (RW)
mbed_official	324:406fd2029f23	2754	*
mbed_official	324:406fd2029f23	2755	* When this field is set, the RXUF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2756	*
mbed_official	324:406fd2029f23	2757	* Values:
mbed_official	324:406fd2029f23	2758	* - 0 - RXUF flag does not generate an interrupt to the host.
mbed_official	324:406fd2029f23	2759	* - 1 - RXUF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2760	*/
mbed_official	324:406fd2029f23	2761	/@{/
mbed_official	324:406fd2029f23	2762	#define BP_UART_CFIFO_RXUFE (0U) /!< Bit position for UART_CFIFO_RXUFE. /
mbed_official	324:406fd2029f23	2763	#define BM_UART_CFIFO_RXUFE (0x01U) /!< Bit mask for UART_CFIFO_RXUFE. /
mbed_official	324:406fd2029f23	2764	#define BS_UART_CFIFO_RXUFE (1U) /!< Bit field size in bits for UART_CFIFO_RXUFE. /
mbed_official	324:406fd2029f23	2765
mbed_official	324:406fd2029f23	2766	/! @brief Read current value of the UART_CFIFO_RXUFE field. /
mbed_official	324:406fd2029f23	2767	#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
mbed_official	324:406fd2029f23	2768
mbed_official	324:406fd2029f23	2769	/! @brief Format value for bitfield UART_CFIFO_RXUFE. /
mbed_official	324:406fd2029f23	2770	#define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE)
mbed_official	324:406fd2029f23	2771
mbed_official	324:406fd2029f23	2772	/! @brief Set the RXUFE field to a new value. /
mbed_official	324:406fd2029f23	2773	#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
mbed_official	324:406fd2029f23	2774	/@}/
mbed_official	324:406fd2029f23	2775
mbed_official	324:406fd2029f23	2776	/*!
mbed_official	324:406fd2029f23	2777	* @name Register UART_CFIFO, field TXOFE[1] (RW)
mbed_official	324:406fd2029f23	2778	*
mbed_official	324:406fd2029f23	2779	* When this field is set, the TXOF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2780	*
mbed_official	324:406fd2029f23	2781	* Values:
mbed_official	324:406fd2029f23	2782	* - 0 - TXOF flag does not generate an interrupt to the host.
mbed_official	324:406fd2029f23	2783	* - 1 - TXOF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2784	*/
mbed_official	324:406fd2029f23	2785	/@{/
mbed_official	324:406fd2029f23	2786	#define BP_UART_CFIFO_TXOFE (1U) /!< Bit position for UART_CFIFO_TXOFE. /
mbed_official	324:406fd2029f23	2787	#define BM_UART_CFIFO_TXOFE (0x02U) /!< Bit mask for UART_CFIFO_TXOFE. /
mbed_official	324:406fd2029f23	2788	#define BS_UART_CFIFO_TXOFE (1U) /!< Bit field size in bits for UART_CFIFO_TXOFE. /
mbed_official	324:406fd2029f23	2789
mbed_official	324:406fd2029f23	2790	/! @brief Read current value of the UART_CFIFO_TXOFE field. /
mbed_official	324:406fd2029f23	2791	#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
mbed_official	324:406fd2029f23	2792
mbed_official	324:406fd2029f23	2793	/! @brief Format value for bitfield UART_CFIFO_TXOFE. /
mbed_official	324:406fd2029f23	2794	#define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE)
mbed_official	324:406fd2029f23	2795
mbed_official	324:406fd2029f23	2796	/! @brief Set the TXOFE field to a new value. /
mbed_official	324:406fd2029f23	2797	#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
mbed_official	324:406fd2029f23	2798	/@}/
mbed_official	324:406fd2029f23	2799
mbed_official	324:406fd2029f23	2800	/*!
mbed_official	324:406fd2029f23	2801	* @name Register UART_CFIFO, field RXOFE[2] (RW)
mbed_official	324:406fd2029f23	2802	*
mbed_official	324:406fd2029f23	2803	* When this field is set, the RXOF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2804	*
mbed_official	324:406fd2029f23	2805	* Values:
mbed_official	324:406fd2029f23	2806	* - 0 - RXOF flag does not generate an interrupt to the host.
mbed_official	324:406fd2029f23	2807	* - 1 - RXOF flag generates an interrupt to the host.
mbed_official	324:406fd2029f23	2808	*/
mbed_official	324:406fd2029f23	2809	/@{/
mbed_official	324:406fd2029f23	2810	#define BP_UART_CFIFO_RXOFE (2U) /!< Bit position for UART_CFIFO_RXOFE. /
mbed_official	324:406fd2029f23	2811	#define BM_UART_CFIFO_RXOFE (0x04U) /!< Bit mask for UART_CFIFO_RXOFE. /
mbed_official	324:406fd2029f23	2812	#define BS_UART_CFIFO_RXOFE (1U) /!< Bit field size in bits for UART_CFIFO_RXOFE. /
mbed_official	324:406fd2029f23	2813
mbed_official	324:406fd2029f23	2814	/! @brief Read current value of the UART_CFIFO_RXOFE field. /
mbed_official	324:406fd2029f23	2815	#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
mbed_official	324:406fd2029f23	2816
mbed_official	324:406fd2029f23	2817	/! @brief Format value for bitfield UART_CFIFO_RXOFE. /
mbed_official	324:406fd2029f23	2818	#define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE)
mbed_official	324:406fd2029f23	2819
mbed_official	324:406fd2029f23	2820	/! @brief Set the RXOFE field to a new value. /
mbed_official	324:406fd2029f23	2821	#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
mbed_official	324:406fd2029f23	2822	/@}/
mbed_official	324:406fd2029f23	2823
mbed_official	324:406fd2029f23	2824	/*!
mbed_official	324:406fd2029f23	2825	* @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
mbed_official	324:406fd2029f23	2826	*
mbed_official	324:406fd2029f23	2827	* Writing to this field causes all data that is stored in the receive
mbed_official	324:406fd2029f23	2828	* FIFO/buffer to be flushed. This does not affect data that is in the receive shift
mbed_official	324:406fd2029f23	2829	* register.
mbed_official	324:406fd2029f23	2830	*
mbed_official	324:406fd2029f23	2831	* Values:
mbed_official	324:406fd2029f23	2832	* - 0 - No flush operation occurs.
mbed_official	324:406fd2029f23	2833	* - 1 - All data in the receive FIFO/buffer is cleared out.
mbed_official	324:406fd2029f23	2834	*/
mbed_official	324:406fd2029f23	2835	/@{/
mbed_official	324:406fd2029f23	2836	#define BP_UART_CFIFO_RXFLUSH (6U) /!< Bit position for UART_CFIFO_RXFLUSH. /
mbed_official	324:406fd2029f23	2837	#define BM_UART_CFIFO_RXFLUSH (0x40U) /!< Bit mask for UART_CFIFO_RXFLUSH. /
mbed_official	324:406fd2029f23	2838	#define BS_UART_CFIFO_RXFLUSH (1U) /!< Bit field size in bits for UART_CFIFO_RXFLUSH. /
mbed_official	324:406fd2029f23	2839
mbed_official	324:406fd2029f23	2840	/! @brief Format value for bitfield UART_CFIFO_RXFLUSH. /
mbed_official	324:406fd2029f23	2841	#define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH)
mbed_official	324:406fd2029f23	2842
mbed_official	324:406fd2029f23	2843	/! @brief Set the RXFLUSH field to a new value. /
mbed_official	324:406fd2029f23	2844	#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
mbed_official	324:406fd2029f23	2845	/@}/
mbed_official	324:406fd2029f23	2846
mbed_official	324:406fd2029f23	2847	/*!
mbed_official	324:406fd2029f23	2848	* @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
mbed_official	324:406fd2029f23	2849	*
mbed_official	324:406fd2029f23	2850	* Writing to this field causes all data that is stored in the transmit
mbed_official	324:406fd2029f23	2851	* FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
mbed_official	324:406fd2029f23	2852	* register.
mbed_official	324:406fd2029f23	2853	*
mbed_official	324:406fd2029f23	2854	* Values:
mbed_official	324:406fd2029f23	2855	* - 0 - No flush operation occurs.
mbed_official	324:406fd2029f23	2856	* - 1 - All data in the transmit FIFO/Buffer is cleared out.
mbed_official	324:406fd2029f23	2857	*/
mbed_official	324:406fd2029f23	2858	/@{/
mbed_official	324:406fd2029f23	2859	#define BP_UART_CFIFO_TXFLUSH (7U) /!< Bit position for UART_CFIFO_TXFLUSH. /
mbed_official	324:406fd2029f23	2860	#define BM_UART_CFIFO_TXFLUSH (0x80U) /!< Bit mask for UART_CFIFO_TXFLUSH. /
mbed_official	324:406fd2029f23	2861	#define BS_UART_CFIFO_TXFLUSH (1U) /!< Bit field size in bits for UART_CFIFO_TXFLUSH. /
mbed_official	324:406fd2029f23	2862
mbed_official	324:406fd2029f23	2863	/! @brief Format value for bitfield UART_CFIFO_TXFLUSH. /
mbed_official	324:406fd2029f23	2864	#define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH)
mbed_official	324:406fd2029f23	2865
mbed_official	324:406fd2029f23	2866	/! @brief Set the TXFLUSH field to a new value. /
mbed_official	324:406fd2029f23	2867	#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
mbed_official	324:406fd2029f23	2868	/@}/
mbed_official	324:406fd2029f23	2869
mbed_official	324:406fd2029f23	2870	/*******************************************************************************
mbed_official	324:406fd2029f23	2871	* HW_UART_SFIFO - UART FIFO Status Register
mbed_official	324:406fd2029f23	2872	******************************************************************************/
mbed_official	324:406fd2029f23	2873
mbed_official	324:406fd2029f23	2874	/*!
mbed_official	324:406fd2029f23	2875	* @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
mbed_official	324:406fd2029f23	2876	*
mbed_official	324:406fd2029f23	2877	* Reset value: 0xC0U
mbed_official	324:406fd2029f23	2878	*
mbed_official	324:406fd2029f23	2879	* This register provides status information regarding the transmit and receiver
mbed_official	324:406fd2029f23	2880	* buffers/FIFOs, including interrupt information. This register may be written
mbed_official	324:406fd2029f23	2881	* to or read at any time.
mbed_official	324:406fd2029f23	2882	*/
mbed_official	324:406fd2029f23	2883	typedef union _hw_uart_sfifo
mbed_official	324:406fd2029f23	2884	{
mbed_official	324:406fd2029f23	2885	uint8_t U;
mbed_official	324:406fd2029f23	2886	struct _hw_uart_sfifo_bitfields
mbed_official	324:406fd2029f23	2887	{
mbed_official	324:406fd2029f23	2888	uint8_t RXUF : 1; /!< [0] Receiver Buffer Underflow Flag /
mbed_official	324:406fd2029f23	2889	uint8_t TXOF : 1; /!< [1] Transmitter Buffer Overflow Flag /
mbed_official	324:406fd2029f23	2890	uint8_t RXOF : 1; /!< [2] Receiver Buffer Overflow Flag /
mbed_official	324:406fd2029f23	2891	uint8_t RESERVED0 : 3; /!< [5:3] /
mbed_official	324:406fd2029f23	2892	uint8_t RXEMPT : 1; /!< [6] Receive Buffer/FIFO Empty /
mbed_official	324:406fd2029f23	2893	uint8_t TXEMPT : 1; /!< [7] Transmit Buffer/FIFO Empty /
mbed_official	324:406fd2029f23	2894	} B;
mbed_official	324:406fd2029f23	2895	} hw_uart_sfifo_t;
mbed_official	324:406fd2029f23	2896
mbed_official	324:406fd2029f23	2897	/*!
mbed_official	324:406fd2029f23	2898	* @name Constants and macros for entire UART_SFIFO register
mbed_official	324:406fd2029f23	2899	*/
mbed_official	324:406fd2029f23	2900	/@{/
mbed_official	324:406fd2029f23	2901	#define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U)
mbed_official	324:406fd2029f23	2902
mbed_official	324:406fd2029f23	2903	#define HW_UART_SFIFO(x) ((__IO hw_uart_sfifo_t ) HW_UART_SFIFO_ADDR(x))
mbed_official	324:406fd2029f23	2904	#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
mbed_official	324:406fd2029f23	2905	#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
mbed_official	324:406fd2029f23	2906	#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2907	#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2908	#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2909	/@}/
mbed_official	324:406fd2029f23	2910
mbed_official	324:406fd2029f23	2911	/*
mbed_official	324:406fd2029f23	2912	* Constants & macros for individual UART_SFIFO bitfields
mbed_official	324:406fd2029f23	2913	*/
mbed_official	324:406fd2029f23	2914
mbed_official	324:406fd2029f23	2915	/*!
mbed_official	324:406fd2029f23	2916	* @name Register UART_SFIFO, field RXUF[0] (W1C)
mbed_official	324:406fd2029f23	2917	*
mbed_official	324:406fd2029f23	2918	* Indicates that more data has been read from the receive buffer than was
mbed_official	324:406fd2029f23	2919	* present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
mbed_official	324:406fd2029f23	2920	* an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
mbed_official	324:406fd2029f23	2921	* is cleared by writing a 1.
mbed_official	324:406fd2029f23	2922	*
mbed_official	324:406fd2029f23	2923	* Values:
mbed_official	324:406fd2029f23	2924	* - 0 - No receive buffer underflow has occurred since the last time the flag
mbed_official	324:406fd2029f23	2925	* was cleared.
mbed_official	324:406fd2029f23	2926	* - 1 - At least one receive buffer underflow has occurred since the last time
mbed_official	324:406fd2029f23	2927	* the flag was cleared.
mbed_official	324:406fd2029f23	2928	*/
mbed_official	324:406fd2029f23	2929	/@{/
mbed_official	324:406fd2029f23	2930	#define BP_UART_SFIFO_RXUF (0U) /!< Bit position for UART_SFIFO_RXUF. /
mbed_official	324:406fd2029f23	2931	#define BM_UART_SFIFO_RXUF (0x01U) /!< Bit mask for UART_SFIFO_RXUF. /
mbed_official	324:406fd2029f23	2932	#define BS_UART_SFIFO_RXUF (1U) /!< Bit field size in bits for UART_SFIFO_RXUF. /
mbed_official	324:406fd2029f23	2933
mbed_official	324:406fd2029f23	2934	/! @brief Read current value of the UART_SFIFO_RXUF field. /
mbed_official	324:406fd2029f23	2935	#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
mbed_official	324:406fd2029f23	2936
mbed_official	324:406fd2029f23	2937	/! @brief Format value for bitfield UART_SFIFO_RXUF. /
mbed_official	324:406fd2029f23	2938	#define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF)
mbed_official	324:406fd2029f23	2939
mbed_official	324:406fd2029f23	2940	/! @brief Set the RXUF field to a new value. /
mbed_official	324:406fd2029f23	2941	#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
mbed_official	324:406fd2029f23	2942	/@}/
mbed_official	324:406fd2029f23	2943
mbed_official	324:406fd2029f23	2944	/*!
mbed_official	324:406fd2029f23	2945	* @name Register UART_SFIFO, field TXOF[1] (W1C)
mbed_official	324:406fd2029f23	2946	*
mbed_official	324:406fd2029f23	2947	* Indicates that more data has been written to the transmit buffer than it can
mbed_official	324:406fd2029f23	2948	* hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
mbed_official	324:406fd2029f23	2949	* an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
mbed_official	324:406fd2029f23	2950	* flag is cleared by writing a 1.
mbed_official	324:406fd2029f23	2951	*
mbed_official	324:406fd2029f23	2952	* Values:
mbed_official	324:406fd2029f23	2953	* - 0 - No transmit buffer overflow has occurred since the last time the flag
mbed_official	324:406fd2029f23	2954	* was cleared.
mbed_official	324:406fd2029f23	2955	* - 1 - At least one transmit buffer overflow has occurred since the last time
mbed_official	324:406fd2029f23	2956	* the flag was cleared.
mbed_official	324:406fd2029f23	2957	*/
mbed_official	324:406fd2029f23	2958	/@{/
mbed_official	324:406fd2029f23	2959	#define BP_UART_SFIFO_TXOF (1U) /!< Bit position for UART_SFIFO_TXOF. /
mbed_official	324:406fd2029f23	2960	#define BM_UART_SFIFO_TXOF (0x02U) /!< Bit mask for UART_SFIFO_TXOF. /
mbed_official	324:406fd2029f23	2961	#define BS_UART_SFIFO_TXOF (1U) /!< Bit field size in bits for UART_SFIFO_TXOF. /
mbed_official	324:406fd2029f23	2962
mbed_official	324:406fd2029f23	2963	/! @brief Read current value of the UART_SFIFO_TXOF field. /
mbed_official	324:406fd2029f23	2964	#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
mbed_official	324:406fd2029f23	2965
mbed_official	324:406fd2029f23	2966	/! @brief Format value for bitfield UART_SFIFO_TXOF. /
mbed_official	324:406fd2029f23	2967	#define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF)
mbed_official	324:406fd2029f23	2968
mbed_official	324:406fd2029f23	2969	/! @brief Set the TXOF field to a new value. /
mbed_official	324:406fd2029f23	2970	#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
mbed_official	324:406fd2029f23	2971	/@}/
mbed_official	324:406fd2029f23	2972
mbed_official	324:406fd2029f23	2973	/*!
mbed_official	324:406fd2029f23	2974	* @name Register UART_SFIFO, field RXOF[2] (W1C)
mbed_official	324:406fd2029f23	2975	*
mbed_official	324:406fd2029f23	2976	* Indicates that more data has been written to the receive buffer than it can
mbed_official	324:406fd2029f23	2977	* hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
mbed_official	324:406fd2029f23	2978	* an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
mbed_official	324:406fd2029f23	2979	* is cleared by writing a 1.
mbed_official	324:406fd2029f23	2980	*
mbed_official	324:406fd2029f23	2981	* Values:
mbed_official	324:406fd2029f23	2982	* - 0 - No receive buffer overflow has occurred since the last time the flag
mbed_official	324:406fd2029f23	2983	* was cleared.
mbed_official	324:406fd2029f23	2984	* - 1 - At least one receive buffer overflow has occurred since the last time
mbed_official	324:406fd2029f23	2985	* the flag was cleared.
mbed_official	324:406fd2029f23	2986	*/
mbed_official	324:406fd2029f23	2987	/@{/
mbed_official	324:406fd2029f23	2988	#define BP_UART_SFIFO_RXOF (2U) /!< Bit position for UART_SFIFO_RXOF. /
mbed_official	324:406fd2029f23	2989	#define BM_UART_SFIFO_RXOF (0x04U) /!< Bit mask for UART_SFIFO_RXOF. /
mbed_official	324:406fd2029f23	2990	#define BS_UART_SFIFO_RXOF (1U) /!< Bit field size in bits for UART_SFIFO_RXOF. /
mbed_official	324:406fd2029f23	2991
mbed_official	324:406fd2029f23	2992	/! @brief Read current value of the UART_SFIFO_RXOF field. /
mbed_official	324:406fd2029f23	2993	#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
mbed_official	324:406fd2029f23	2994
mbed_official	324:406fd2029f23	2995	/! @brief Format value for bitfield UART_SFIFO_RXOF. /
mbed_official	324:406fd2029f23	2996	#define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF)
mbed_official	324:406fd2029f23	2997
mbed_official	324:406fd2029f23	2998	/! @brief Set the RXOF field to a new value. /
mbed_official	324:406fd2029f23	2999	#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
mbed_official	324:406fd2029f23	3000	/@}/
mbed_official	324:406fd2029f23	3001
mbed_official	324:406fd2029f23	3002	/*!
mbed_official	324:406fd2029f23	3003	* @name Register UART_SFIFO, field RXEMPT[6] (RO)
mbed_official	324:406fd2029f23	3004	*
mbed_official	324:406fd2029f23	3005	* Asserts when there is no data in the receive FIFO/Buffer. This field does not
mbed_official	324:406fd2029f23	3006	* take into account data that is in the receive shift register.
mbed_official	324:406fd2029f23	3007	*
mbed_official	324:406fd2029f23	3008	* Values:
mbed_official	324:406fd2029f23	3009	* - 0 - Receive buffer is not empty.
mbed_official	324:406fd2029f23	3010	* - 1 - Receive buffer is empty.
mbed_official	324:406fd2029f23	3011	*/
mbed_official	324:406fd2029f23	3012	/@{/
mbed_official	324:406fd2029f23	3013	#define BP_UART_SFIFO_RXEMPT (6U) /!< Bit position for UART_SFIFO_RXEMPT. /
mbed_official	324:406fd2029f23	3014	#define BM_UART_SFIFO_RXEMPT (0x40U) /!< Bit mask for UART_SFIFO_RXEMPT. /
mbed_official	324:406fd2029f23	3015	#define BS_UART_SFIFO_RXEMPT (1U) /!< Bit field size in bits for UART_SFIFO_RXEMPT. /
mbed_official	324:406fd2029f23	3016
mbed_official	324:406fd2029f23	3017	/! @brief Read current value of the UART_SFIFO_RXEMPT field. /
mbed_official	324:406fd2029f23	3018	#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
mbed_official	324:406fd2029f23	3019	/@}/
mbed_official	324:406fd2029f23	3020
mbed_official	324:406fd2029f23	3021	/*!
mbed_official	324:406fd2029f23	3022	* @name Register UART_SFIFO, field TXEMPT[7] (RO)
mbed_official	324:406fd2029f23	3023	*
mbed_official	324:406fd2029f23	3024	* Asserts when there is no data in the Transmit FIFO/buffer. This field does
mbed_official	324:406fd2029f23	3025	* not take into account data that is in the transmit shift register.
mbed_official	324:406fd2029f23	3026	*
mbed_official	324:406fd2029f23	3027	* Values:
mbed_official	324:406fd2029f23	3028	* - 0 - Transmit buffer is not empty.
mbed_official	324:406fd2029f23	3029	* - 1 - Transmit buffer is empty.
mbed_official	324:406fd2029f23	3030	*/
mbed_official	324:406fd2029f23	3031	/@{/
mbed_official	324:406fd2029f23	3032	#define BP_UART_SFIFO_TXEMPT (7U) /!< Bit position for UART_SFIFO_TXEMPT. /
mbed_official	324:406fd2029f23	3033	#define BM_UART_SFIFO_TXEMPT (0x80U) /!< Bit mask for UART_SFIFO_TXEMPT. /
mbed_official	324:406fd2029f23	3034	#define BS_UART_SFIFO_TXEMPT (1U) /!< Bit field size in bits for UART_SFIFO_TXEMPT. /
mbed_official	324:406fd2029f23	3035
mbed_official	324:406fd2029f23	3036	/! @brief Read current value of the UART_SFIFO_TXEMPT field. /
mbed_official	324:406fd2029f23	3037	#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
mbed_official	324:406fd2029f23	3038	/@}/
mbed_official	324:406fd2029f23	3039
mbed_official	324:406fd2029f23	3040	/*******************************************************************************
mbed_official	324:406fd2029f23	3041	* HW_UART_TWFIFO - UART FIFO Transmit Watermark
mbed_official	324:406fd2029f23	3042	******************************************************************************/
mbed_official	324:406fd2029f23	3043
mbed_official	324:406fd2029f23	3044	/*!
mbed_official	324:406fd2029f23	3045	* @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
mbed_official	324:406fd2029f23	3046	*
mbed_official	324:406fd2029f23	3047	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3048	*
mbed_official	324:406fd2029f23	3049	* This register provides the ability to set a programmable threshold for
mbed_official	324:406fd2029f23	3050	* notification of needing additional transmit data. This register may be read at any
mbed_official	324:406fd2029f23	3051	* time but must be written only when C2[TE] is not set. Changing the value of the
mbed_official	324:406fd2029f23	3052	* watermark will not clear the S1[TDRE] flag.
mbed_official	324:406fd2029f23	3053	*/
mbed_official	324:406fd2029f23	3054	typedef union _hw_uart_twfifo
mbed_official	324:406fd2029f23	3055	{
mbed_official	324:406fd2029f23	3056	uint8_t U;
mbed_official	324:406fd2029f23	3057	struct _hw_uart_twfifo_bitfields
mbed_official	324:406fd2029f23	3058	{
mbed_official	324:406fd2029f23	3059	uint8_t TXWATER : 8; /!< [7:0] Transmit Watermark /
mbed_official	324:406fd2029f23	3060	} B;
mbed_official	324:406fd2029f23	3061	} hw_uart_twfifo_t;
mbed_official	324:406fd2029f23	3062
mbed_official	324:406fd2029f23	3063	/*!
mbed_official	324:406fd2029f23	3064	* @name Constants and macros for entire UART_TWFIFO register
mbed_official	324:406fd2029f23	3065	*/
mbed_official	324:406fd2029f23	3066	/@{/
mbed_official	324:406fd2029f23	3067	#define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U)
mbed_official	324:406fd2029f23	3068
mbed_official	324:406fd2029f23	3069	#define HW_UART_TWFIFO(x) ((__IO hw_uart_twfifo_t ) HW_UART_TWFIFO_ADDR(x))
mbed_official	324:406fd2029f23	3070	#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
mbed_official	324:406fd2029f23	3071	#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
mbed_official	324:406fd2029f23	3072	#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3073	#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3074	#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3075	/@}/
mbed_official	324:406fd2029f23	3076
mbed_official	324:406fd2029f23	3077	/*
mbed_official	324:406fd2029f23	3078	* Constants & macros for individual UART_TWFIFO bitfields
mbed_official	324:406fd2029f23	3079	*/
mbed_official	324:406fd2029f23	3080
mbed_official	324:406fd2029f23	3081	/*!
mbed_official	324:406fd2029f23	3082	* @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
mbed_official	324:406fd2029f23	3083	*
mbed_official	324:406fd2029f23	3084	* When the number of datawords in the transmit FIFO/buffer is equal to or less
mbed_official	324:406fd2029f23	3085	* than the value in this register field, an interrupt via S1[TDRE] or a DMA
mbed_official	324:406fd2029f23	3086	* request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
mbed_official	324:406fd2029f23	3087	* proper operation, the value in TXWATER must be set to be less than the size of
mbed_official	324:406fd2029f23	3088	* the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
mbed_official	324:406fd2029f23	3089	*/
mbed_official	324:406fd2029f23	3090	/@{/
mbed_official	324:406fd2029f23	3091	#define BP_UART_TWFIFO_TXWATER (0U) /!< Bit position for UART_TWFIFO_TXWATER. /
mbed_official	324:406fd2029f23	3092	#define BM_UART_TWFIFO_TXWATER (0xFFU) /!< Bit mask for UART_TWFIFO_TXWATER. /
mbed_official	324:406fd2029f23	3093	#define BS_UART_TWFIFO_TXWATER (8U) /!< Bit field size in bits for UART_TWFIFO_TXWATER. /
mbed_official	324:406fd2029f23	3094
mbed_official	324:406fd2029f23	3095	/! @brief Read current value of the UART_TWFIFO_TXWATER field. /
mbed_official	324:406fd2029f23	3096	#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
mbed_official	324:406fd2029f23	3097
mbed_official	324:406fd2029f23	3098	/! @brief Format value for bitfield UART_TWFIFO_TXWATER. /
mbed_official	324:406fd2029f23	3099	#define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER)
mbed_official	324:406fd2029f23	3100
mbed_official	324:406fd2029f23	3101	/! @brief Set the TXWATER field to a new value. /
mbed_official	324:406fd2029f23	3102	#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
mbed_official	324:406fd2029f23	3103	/@}/
mbed_official	324:406fd2029f23	3104
mbed_official	324:406fd2029f23	3105	/*******************************************************************************
mbed_official	324:406fd2029f23	3106	* HW_UART_TCFIFO - UART FIFO Transmit Count
mbed_official	324:406fd2029f23	3107	******************************************************************************/
mbed_official	324:406fd2029f23	3108
mbed_official	324:406fd2029f23	3109	/*!
mbed_official	324:406fd2029f23	3110	* @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
mbed_official	324:406fd2029f23	3111	*
mbed_official	324:406fd2029f23	3112	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3113	*
mbed_official	324:406fd2029f23	3114	* This is a read only register that indicates how many datawords are currently
mbed_official	324:406fd2029f23	3115	* in the transmit buffer/FIFO. It may be read at any time.
mbed_official	324:406fd2029f23	3116	*/
mbed_official	324:406fd2029f23	3117	typedef union _hw_uart_tcfifo
mbed_official	324:406fd2029f23	3118	{
mbed_official	324:406fd2029f23	3119	uint8_t U;
mbed_official	324:406fd2029f23	3120	struct _hw_uart_tcfifo_bitfields
mbed_official	324:406fd2029f23	3121	{
mbed_official	324:406fd2029f23	3122	uint8_t TXCOUNT : 8; /!< [7:0] Transmit Counter /
mbed_official	324:406fd2029f23	3123	} B;
mbed_official	324:406fd2029f23	3124	} hw_uart_tcfifo_t;
mbed_official	324:406fd2029f23	3125
mbed_official	324:406fd2029f23	3126	/*!
mbed_official	324:406fd2029f23	3127	* @name Constants and macros for entire UART_TCFIFO register
mbed_official	324:406fd2029f23	3128	*/
mbed_official	324:406fd2029f23	3129	/@{/
mbed_official	324:406fd2029f23	3130	#define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U)
mbed_official	324:406fd2029f23	3131
mbed_official	324:406fd2029f23	3132	#define HW_UART_TCFIFO(x) ((__I hw_uart_tcfifo_t ) HW_UART_TCFIFO_ADDR(x))
mbed_official	324:406fd2029f23	3133	#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
mbed_official	324:406fd2029f23	3134	/@}/
mbed_official	324:406fd2029f23	3135
mbed_official	324:406fd2029f23	3136	/*
mbed_official	324:406fd2029f23	3137	* Constants & macros for individual UART_TCFIFO bitfields
mbed_official	324:406fd2029f23	3138	*/
mbed_official	324:406fd2029f23	3139
mbed_official	324:406fd2029f23	3140	/*!
mbed_official	324:406fd2029f23	3141	* @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
mbed_official	324:406fd2029f23	3142	*
mbed_official	324:406fd2029f23	3143	* The value in this register indicates the number of datawords that are in the
mbed_official	324:406fd2029f23	3144	* transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
mbed_official	324:406fd2029f23	3145	* transmit shift register, it is not included in the count. This value may be used
mbed_official	324:406fd2029f23	3146	* in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
mbed_official	324:406fd2029f23	3147	* transmit FIFO/buffer.
mbed_official	324:406fd2029f23	3148	*/
mbed_official	324:406fd2029f23	3149	/@{/
mbed_official	324:406fd2029f23	3150	#define BP_UART_TCFIFO_TXCOUNT (0U) /!< Bit position for UART_TCFIFO_TXCOUNT. /
mbed_official	324:406fd2029f23	3151	#define BM_UART_TCFIFO_TXCOUNT (0xFFU) /!< Bit mask for UART_TCFIFO_TXCOUNT. /
mbed_official	324:406fd2029f23	3152	#define BS_UART_TCFIFO_TXCOUNT (8U) /!< Bit field size in bits for UART_TCFIFO_TXCOUNT. /
mbed_official	324:406fd2029f23	3153
mbed_official	324:406fd2029f23	3154	/! @brief Read current value of the UART_TCFIFO_TXCOUNT field. /
mbed_official	324:406fd2029f23	3155	#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
mbed_official	324:406fd2029f23	3156	/@}/
mbed_official	324:406fd2029f23	3157
mbed_official	324:406fd2029f23	3158	/*******************************************************************************
mbed_official	324:406fd2029f23	3159	* HW_UART_RWFIFO - UART FIFO Receive Watermark
mbed_official	324:406fd2029f23	3160	******************************************************************************/
mbed_official	324:406fd2029f23	3161
mbed_official	324:406fd2029f23	3162	/*!
mbed_official	324:406fd2029f23	3163	* @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
mbed_official	324:406fd2029f23	3164	*
mbed_official	324:406fd2029f23	3165	* Reset value: 0x01U
mbed_official	324:406fd2029f23	3166	*
mbed_official	324:406fd2029f23	3167	* This register provides the ability to set a programmable threshold for
mbed_official	324:406fd2029f23	3168	* notification of the need to remove data from the receiver FIFO/buffer. This register
mbed_official	324:406fd2029f23	3169	* may be read at any time but must be written only when C2[RE] is not asserted.
mbed_official	324:406fd2029f23	3170	* Changing the value in this register will not clear S1[RDRF].
mbed_official	324:406fd2029f23	3171	*/
mbed_official	324:406fd2029f23	3172	typedef union _hw_uart_rwfifo
mbed_official	324:406fd2029f23	3173	{
mbed_official	324:406fd2029f23	3174	uint8_t U;
mbed_official	324:406fd2029f23	3175	struct _hw_uart_rwfifo_bitfields
mbed_official	324:406fd2029f23	3176	{
mbed_official	324:406fd2029f23	3177	uint8_t RXWATER : 8; /!< [7:0] Receive Watermark /
mbed_official	324:406fd2029f23	3178	} B;
mbed_official	324:406fd2029f23	3179	} hw_uart_rwfifo_t;
mbed_official	324:406fd2029f23	3180
mbed_official	324:406fd2029f23	3181	/*!
mbed_official	324:406fd2029f23	3182	* @name Constants and macros for entire UART_RWFIFO register
mbed_official	324:406fd2029f23	3183	*/
mbed_official	324:406fd2029f23	3184	/@{/
mbed_official	324:406fd2029f23	3185	#define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U)
mbed_official	324:406fd2029f23	3186
mbed_official	324:406fd2029f23	3187	#define HW_UART_RWFIFO(x) ((__IO hw_uart_rwfifo_t ) HW_UART_RWFIFO_ADDR(x))
mbed_official	324:406fd2029f23	3188	#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
mbed_official	324:406fd2029f23	3189	#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
mbed_official	324:406fd2029f23	3190	#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3191	#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3192	#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3193	/@}/
mbed_official	324:406fd2029f23	3194
mbed_official	324:406fd2029f23	3195	/*
mbed_official	324:406fd2029f23	3196	* Constants & macros for individual UART_RWFIFO bitfields
mbed_official	324:406fd2029f23	3197	*/
mbed_official	324:406fd2029f23	3198
mbed_official	324:406fd2029f23	3199	/*!
mbed_official	324:406fd2029f23	3200	* @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
mbed_official	324:406fd2029f23	3201	*
mbed_official	324:406fd2029f23	3202	* When the number of datawords in the receive FIFO/buffer is equal to or
mbed_official	324:406fd2029f23	3203	* greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
mbed_official	324:406fd2029f23	3204	* request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
mbed_official	324:406fd2029f23	3205	* proper operation, the value in RXWATER must be set to be less than the receive
mbed_official	324:406fd2029f23	3206	* FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
mbed_official	324:406fd2029f23	3207	* greater than 0.
mbed_official	324:406fd2029f23	3208	*/
mbed_official	324:406fd2029f23	3209	/@{/
mbed_official	324:406fd2029f23	3210	#define BP_UART_RWFIFO_RXWATER (0U) /!< Bit position for UART_RWFIFO_RXWATER. /
mbed_official	324:406fd2029f23	3211	#define BM_UART_RWFIFO_RXWATER (0xFFU) /!< Bit mask for UART_RWFIFO_RXWATER. /
mbed_official	324:406fd2029f23	3212	#define BS_UART_RWFIFO_RXWATER (8U) /!< Bit field size in bits for UART_RWFIFO_RXWATER. /
mbed_official	324:406fd2029f23	3213
mbed_official	324:406fd2029f23	3214	/! @brief Read current value of the UART_RWFIFO_RXWATER field. /
mbed_official	324:406fd2029f23	3215	#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
mbed_official	324:406fd2029f23	3216
mbed_official	324:406fd2029f23	3217	/! @brief Format value for bitfield UART_RWFIFO_RXWATER. /
mbed_official	324:406fd2029f23	3218	#define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER)
mbed_official	324:406fd2029f23	3219
mbed_official	324:406fd2029f23	3220	/! @brief Set the RXWATER field to a new value. /
mbed_official	324:406fd2029f23	3221	#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
mbed_official	324:406fd2029f23	3222	/@}/
mbed_official	324:406fd2029f23	3223
mbed_official	324:406fd2029f23	3224	/*******************************************************************************
mbed_official	324:406fd2029f23	3225	* HW_UART_RCFIFO - UART FIFO Receive Count
mbed_official	324:406fd2029f23	3226	******************************************************************************/
mbed_official	324:406fd2029f23	3227
mbed_official	324:406fd2029f23	3228	/*!
mbed_official	324:406fd2029f23	3229	* @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
mbed_official	324:406fd2029f23	3230	*
mbed_official	324:406fd2029f23	3231	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3232	*
mbed_official	324:406fd2029f23	3233	* This is a read only register that indicates how many datawords are currently
mbed_official	324:406fd2029f23	3234	* in the receive FIFO/buffer. It may be read at any time.
mbed_official	324:406fd2029f23	3235	*/
mbed_official	324:406fd2029f23	3236	typedef union _hw_uart_rcfifo
mbed_official	324:406fd2029f23	3237	{
mbed_official	324:406fd2029f23	3238	uint8_t U;
mbed_official	324:406fd2029f23	3239	struct _hw_uart_rcfifo_bitfields
mbed_official	324:406fd2029f23	3240	{
mbed_official	324:406fd2029f23	3241	uint8_t RXCOUNT : 8; /!< [7:0] Receive Counter /
mbed_official	324:406fd2029f23	3242	} B;
mbed_official	324:406fd2029f23	3243	} hw_uart_rcfifo_t;
mbed_official	324:406fd2029f23	3244
mbed_official	324:406fd2029f23	3245	/*!
mbed_official	324:406fd2029f23	3246	* @name Constants and macros for entire UART_RCFIFO register
mbed_official	324:406fd2029f23	3247	*/
mbed_official	324:406fd2029f23	3248	/@{/
mbed_official	324:406fd2029f23	3249	#define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U)
mbed_official	324:406fd2029f23	3250
mbed_official	324:406fd2029f23	3251	#define HW_UART_RCFIFO(x) ((__I hw_uart_rcfifo_t ) HW_UART_RCFIFO_ADDR(x))
mbed_official	324:406fd2029f23	3252	#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
mbed_official	324:406fd2029f23	3253	/@}/
mbed_official	324:406fd2029f23	3254
mbed_official	324:406fd2029f23	3255	/*
mbed_official	324:406fd2029f23	3256	* Constants & macros for individual UART_RCFIFO bitfields
mbed_official	324:406fd2029f23	3257	*/
mbed_official	324:406fd2029f23	3258
mbed_official	324:406fd2029f23	3259	/*!
mbed_official	324:406fd2029f23	3260	* @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
mbed_official	324:406fd2029f23	3261	*
mbed_official	324:406fd2029f23	3262	* The value in this register indicates the number of datawords that are in the
mbed_official	324:406fd2029f23	3263	* receive FIFO/buffer. If a dataword is being received, that is, in the receive
mbed_official	324:406fd2029f23	3264	* shift register, it is not included in the count. This value may be used in
mbed_official	324:406fd2029f23	3265	* conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
mbed_official	324:406fd2029f23	3266	* receive FIFO/buffer.
mbed_official	324:406fd2029f23	3267	*/
mbed_official	324:406fd2029f23	3268	/@{/
mbed_official	324:406fd2029f23	3269	#define BP_UART_RCFIFO_RXCOUNT (0U) /!< Bit position for UART_RCFIFO_RXCOUNT. /
mbed_official	324:406fd2029f23	3270	#define BM_UART_RCFIFO_RXCOUNT (0xFFU) /!< Bit mask for UART_RCFIFO_RXCOUNT. /
mbed_official	324:406fd2029f23	3271	#define BS_UART_RCFIFO_RXCOUNT (8U) /!< Bit field size in bits for UART_RCFIFO_RXCOUNT. /
mbed_official	324:406fd2029f23	3272
mbed_official	324:406fd2029f23	3273	/! @brief Read current value of the UART_RCFIFO_RXCOUNT field. /
mbed_official	324:406fd2029f23	3274	#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
mbed_official	324:406fd2029f23	3275	/@}/
mbed_official	324:406fd2029f23	3276
mbed_official	324:406fd2029f23	3277	/*******************************************************************************
mbed_official	324:406fd2029f23	3278	* HW_UART_C7816 - UART 7816 Control Register
mbed_official	324:406fd2029f23	3279	******************************************************************************/
mbed_official	324:406fd2029f23	3280
mbed_official	324:406fd2029f23	3281	/*!
mbed_official	324:406fd2029f23	3282	* @brief HW_UART_C7816 - UART 7816 Control Register (RW)
mbed_official	324:406fd2029f23	3283	*
mbed_official	324:406fd2029f23	3284	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3285	*
mbed_official	324:406fd2029f23	3286	* The C7816 register is the primary control register for ISO-7816 specific
mbed_official	324:406fd2029f23	3287	* functionality. This register is specific to 7816 functionality and the values in
mbed_official	324:406fd2029f23	3288	* this register have no effect on UART operation and should be ignored if
mbed_official	324:406fd2029f23	3289	* ISO_7816E is not set/enabled. This register may be read at any time but values must
mbed_official	324:406fd2029f23	3290	* be changed only when ISO_7816E is not set.
mbed_official	324:406fd2029f23	3291	*/
mbed_official	324:406fd2029f23	3292	typedef union _hw_uart_c7816
mbed_official	324:406fd2029f23	3293	{
mbed_official	324:406fd2029f23	3294	uint8_t U;
mbed_official	324:406fd2029f23	3295	struct _hw_uart_c7816_bitfields
mbed_official	324:406fd2029f23	3296	{
mbed_official	324:406fd2029f23	3297	uint8_t ISO_7816E : 1; /!< [0] ISO-7816 Functionality Enabled /
mbed_official	324:406fd2029f23	3298	uint8_t TTYPE : 1; /!< [1] Transfer Type /
mbed_official	324:406fd2029f23	3299	uint8_t INIT : 1; /!< [2] Detect Initial Character /
mbed_official	324:406fd2029f23	3300	uint8_t ANACK : 1; /!< [3] Generate NACK on Error /
mbed_official	324:406fd2029f23	3301	uint8_t ONACK : 1; /!< [4] Generate NACK on Overflow /
mbed_official	324:406fd2029f23	3302	uint8_t RESERVED0 : 3; /!< [7:5] /
mbed_official	324:406fd2029f23	3303	} B;
mbed_official	324:406fd2029f23	3304	} hw_uart_c7816_t;
mbed_official	324:406fd2029f23	3305
mbed_official	324:406fd2029f23	3306	/*!
mbed_official	324:406fd2029f23	3307	* @name Constants and macros for entire UART_C7816 register
mbed_official	324:406fd2029f23	3308	*/
mbed_official	324:406fd2029f23	3309	/@{/
mbed_official	324:406fd2029f23	3310	#define HW_UART_C7816_ADDR(x) ((x) + 0x18U)
mbed_official	324:406fd2029f23	3311
mbed_official	324:406fd2029f23	3312	#define HW_UART_C7816(x) ((__IO hw_uart_c7816_t ) HW_UART_C7816_ADDR(x))
mbed_official	324:406fd2029f23	3313	#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
mbed_official	324:406fd2029f23	3314	#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
mbed_official	324:406fd2029f23	3315	#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3316	#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3317	#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3318	/@}/
mbed_official	324:406fd2029f23	3319
mbed_official	324:406fd2029f23	3320	/*
mbed_official	324:406fd2029f23	3321	* Constants & macros for individual UART_C7816 bitfields
mbed_official	324:406fd2029f23	3322	*/
mbed_official	324:406fd2029f23	3323
mbed_official	324:406fd2029f23	3324	/*!
mbed_official	324:406fd2029f23	3325	* @name Register UART_C7816, field ISO_7816E[0] (RW)
mbed_official	324:406fd2029f23	3326	*
mbed_official	324:406fd2029f23	3327	* Indicates that the UART is operating according to the ISO-7816 protocol. This
mbed_official	324:406fd2029f23	3328	* field must be modified only when no transmit or receive is occurring. If this
mbed_official	324:406fd2029f23	3329	* field is changed during a data transfer, the data being transmitted or
mbed_official	324:406fd2029f23	3330	* received may be transferred incorrectly.
mbed_official	324:406fd2029f23	3331	*
mbed_official	324:406fd2029f23	3332	* Values:
mbed_official	324:406fd2029f23	3333	* - 0 - ISO-7816 functionality is turned off/not enabled.
mbed_official	324:406fd2029f23	3334	* - 1 - ISO-7816 functionality is turned on/enabled.
mbed_official	324:406fd2029f23	3335	*/
mbed_official	324:406fd2029f23	3336	/@{/
mbed_official	324:406fd2029f23	3337	#define BP_UART_C7816_ISO_7816E (0U) /!< Bit position for UART_C7816_ISO_7816E. /
mbed_official	324:406fd2029f23	3338	#define BM_UART_C7816_ISO_7816E (0x01U) /!< Bit mask for UART_C7816_ISO_7816E. /
mbed_official	324:406fd2029f23	3339	#define BS_UART_C7816_ISO_7816E (1U) /!< Bit field size in bits for UART_C7816_ISO_7816E. /
mbed_official	324:406fd2029f23	3340
mbed_official	324:406fd2029f23	3341	/! @brief Read current value of the UART_C7816_ISO_7816E field. /
mbed_official	324:406fd2029f23	3342	#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
mbed_official	324:406fd2029f23	3343
mbed_official	324:406fd2029f23	3344	/! @brief Format value for bitfield UART_C7816_ISO_7816E. /
mbed_official	324:406fd2029f23	3345	#define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E)
mbed_official	324:406fd2029f23	3346
mbed_official	324:406fd2029f23	3347	/! @brief Set the ISO_7816E field to a new value. /
mbed_official	324:406fd2029f23	3348	#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
mbed_official	324:406fd2029f23	3349	/@}/
mbed_official	324:406fd2029f23	3350
mbed_official	324:406fd2029f23	3351	/*!
mbed_official	324:406fd2029f23	3352	* @name Register UART_C7816, field TTYPE[1] (RW)
mbed_official	324:406fd2029f23	3353	*
mbed_official	324:406fd2029f23	3354	* Indicates the transfer protocol being used. See ISO-7816 / smartcard support
mbed_official	324:406fd2029f23	3355	* for more details.
mbed_official	324:406fd2029f23	3356	*
mbed_official	324:406fd2029f23	3357	* Values:
mbed_official	324:406fd2029f23	3358	* - 0 - T = 0 per the ISO-7816 specification.
mbed_official	324:406fd2029f23	3359	* - 1 - T = 1 per the ISO-7816 specification.
mbed_official	324:406fd2029f23	3360	*/
mbed_official	324:406fd2029f23	3361	/@{/
mbed_official	324:406fd2029f23	3362	#define BP_UART_C7816_TTYPE (1U) /!< Bit position for UART_C7816_TTYPE. /
mbed_official	324:406fd2029f23	3363	#define BM_UART_C7816_TTYPE (0x02U) /!< Bit mask for UART_C7816_TTYPE. /
mbed_official	324:406fd2029f23	3364	#define BS_UART_C7816_TTYPE (1U) /!< Bit field size in bits for UART_C7816_TTYPE. /
mbed_official	324:406fd2029f23	3365
mbed_official	324:406fd2029f23	3366	/! @brief Read current value of the UART_C7816_TTYPE field. /
mbed_official	324:406fd2029f23	3367	#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
mbed_official	324:406fd2029f23	3368
mbed_official	324:406fd2029f23	3369	/! @brief Format value for bitfield UART_C7816_TTYPE. /
mbed_official	324:406fd2029f23	3370	#define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE)
mbed_official	324:406fd2029f23	3371
mbed_official	324:406fd2029f23	3372	/! @brief Set the TTYPE field to a new value. /
mbed_official	324:406fd2029f23	3373	#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
mbed_official	324:406fd2029f23	3374	/@}/
mbed_official	324:406fd2029f23	3375
mbed_official	324:406fd2029f23	3376	/*!
mbed_official	324:406fd2029f23	3377	* @name Register UART_C7816, field INIT[2] (RW)
mbed_official	324:406fd2029f23	3378	*
mbed_official	324:406fd2029f23	3379	* When this field is set, all received characters are searched for a valid
mbed_official	324:406fd2029f23	3380	* initial character. If an invalid initial character is identified, and ANACK is
mbed_official	324:406fd2029f23	3381	* set, a NACK is sent. All received data is discarded and error flags blocked
mbed_official	324:406fd2029f23	3382	* (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
mbed_official	324:406fd2029f23	3383	* until a valid initial character is detected. Upon detecting a valid initial
mbed_official	324:406fd2029f23	3384	* character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
mbed_official	324:406fd2029f23	3385	* automatically updated to reflect the initial character that was received. The
mbed_official	324:406fd2029f23	3386	* actual INIT data value is not stored in the receive buffer. Additionally, upon
mbed_official	324:406fd2029f23	3387	* detection of a valid initial character, IS7816[INITD] is set and an interrupt
mbed_official	324:406fd2029f23	3388	* issued as programmed by IE7816[INITDE]. When a valid initial character is
mbed_official	324:406fd2029f23	3389	* detected, INIT is automatically cleared. This Initial Character Detect feature is
mbed_official	324:406fd2029f23	3390	* supported only in T = 0 protocol mode.
mbed_official	324:406fd2029f23	3391	*
mbed_official	324:406fd2029f23	3392	* Values:
mbed_official	324:406fd2029f23	3393	* - 0 - Normal operating mode. Receiver does not seek to identify initial
mbed_official	324:406fd2029f23	3394	* character.
mbed_official	324:406fd2029f23	3395	* - 1 - Receiver searches for initial character.
mbed_official	324:406fd2029f23	3396	*/
mbed_official	324:406fd2029f23	3397	/@{/
mbed_official	324:406fd2029f23	3398	#define BP_UART_C7816_INIT (2U) /!< Bit position for UART_C7816_INIT. /
mbed_official	324:406fd2029f23	3399	#define BM_UART_C7816_INIT (0x04U) /!< Bit mask for UART_C7816_INIT. /
mbed_official	324:406fd2029f23	3400	#define BS_UART_C7816_INIT (1U) /!< Bit field size in bits for UART_C7816_INIT. /
mbed_official	324:406fd2029f23	3401
mbed_official	324:406fd2029f23	3402	/! @brief Read current value of the UART_C7816_INIT field. /
mbed_official	324:406fd2029f23	3403	#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
mbed_official	324:406fd2029f23	3404
mbed_official	324:406fd2029f23	3405	/! @brief Format value for bitfield UART_C7816_INIT. /
mbed_official	324:406fd2029f23	3406	#define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT)
mbed_official	324:406fd2029f23	3407
mbed_official	324:406fd2029f23	3408	/! @brief Set the INIT field to a new value. /
mbed_official	324:406fd2029f23	3409	#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
mbed_official	324:406fd2029f23	3410	/@}/
mbed_official	324:406fd2029f23	3411
mbed_official	324:406fd2029f23	3412	/*!
mbed_official	324:406fd2029f23	3413	* @name Register UART_C7816, field ANACK[3] (RW)
mbed_official	324:406fd2029f23	3414	*
mbed_official	324:406fd2029f23	3415	* When this field is set, the receiver automatically generates a NACK response
mbed_official	324:406fd2029f23	3416	* if a parity error occurs or if INIT is set and an invalid initial character is
mbed_official	324:406fd2029f23	3417	* detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
mbed_official	324:406fd2029f23	3418	* attempts to retransmit the data indefinitely. To stop retransmission attempts,
mbed_official	324:406fd2029f23	3419	* clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
mbed_official	324:406fd2029f23	3420	*
mbed_official	324:406fd2029f23	3421	* Values:
mbed_official	324:406fd2029f23	3422	* - 0 - No NACK is automatically generated.
mbed_official	324:406fd2029f23	3423	* - 1 - A NACK is automatically generated if a parity error is detected or if
mbed_official	324:406fd2029f23	3424	* an invalid initial character is detected.
mbed_official	324:406fd2029f23	3425	*/
mbed_official	324:406fd2029f23	3426	/@{/
mbed_official	324:406fd2029f23	3427	#define BP_UART_C7816_ANACK (3U) /!< Bit position for UART_C7816_ANACK. /
mbed_official	324:406fd2029f23	3428	#define BM_UART_C7816_ANACK (0x08U) /!< Bit mask for UART_C7816_ANACK. /
mbed_official	324:406fd2029f23	3429	#define BS_UART_C7816_ANACK (1U) /!< Bit field size in bits for UART_C7816_ANACK. /
mbed_official	324:406fd2029f23	3430
mbed_official	324:406fd2029f23	3431	/! @brief Read current value of the UART_C7816_ANACK field. /
mbed_official	324:406fd2029f23	3432	#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
mbed_official	324:406fd2029f23	3433
mbed_official	324:406fd2029f23	3434	/! @brief Format value for bitfield UART_C7816_ANACK. /
mbed_official	324:406fd2029f23	3435	#define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK)
mbed_official	324:406fd2029f23	3436
mbed_official	324:406fd2029f23	3437	/! @brief Set the ANACK field to a new value. /
mbed_official	324:406fd2029f23	3438	#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
mbed_official	324:406fd2029f23	3439	/@}/
mbed_official	324:406fd2029f23	3440
mbed_official	324:406fd2029f23	3441	/*!
mbed_official	324:406fd2029f23	3442	* @name Register UART_C7816, field ONACK[4] (RW)
mbed_official	324:406fd2029f23	3443	*
mbed_official	324:406fd2029f23	3444	* When this field is set, the receiver automatically generates a NACK response
mbed_official	324:406fd2029f23	3445	* if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
mbed_official	324:406fd2029f23	3446	* this results in the transmitter resending the packet that overflowed until the
mbed_official	324:406fd2029f23	3447	* retransmit threshold for that transmitter is reached. A NACK is generated only
mbed_official	324:406fd2029f23	3448	* if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
mbed_official	324:406fd2029f23	3449	* considerations
mbed_official	324:406fd2029f23	3450	*
mbed_official	324:406fd2029f23	3451	* Values:
mbed_official	324:406fd2029f23	3452	* - 0 - The received data does not generate a NACK when the receipt of the data
mbed_official	324:406fd2029f23	3453	* results in an overflow event.
mbed_official	324:406fd2029f23	3454	* - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
mbed_official	324:406fd2029f23	3455	* received character.
mbed_official	324:406fd2029f23	3456	*/
mbed_official	324:406fd2029f23	3457	/@{/
mbed_official	324:406fd2029f23	3458	#define BP_UART_C7816_ONACK (4U) /!< Bit position for UART_C7816_ONACK. /
mbed_official	324:406fd2029f23	3459	#define BM_UART_C7816_ONACK (0x10U) /!< Bit mask for UART_C7816_ONACK. /
mbed_official	324:406fd2029f23	3460	#define BS_UART_C7816_ONACK (1U) /!< Bit field size in bits for UART_C7816_ONACK. /
mbed_official	324:406fd2029f23	3461
mbed_official	324:406fd2029f23	3462	/! @brief Read current value of the UART_C7816_ONACK field. /
mbed_official	324:406fd2029f23	3463	#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
mbed_official	324:406fd2029f23	3464
mbed_official	324:406fd2029f23	3465	/! @brief Format value for bitfield UART_C7816_ONACK. /
mbed_official	324:406fd2029f23	3466	#define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK)
mbed_official	324:406fd2029f23	3467
mbed_official	324:406fd2029f23	3468	/! @brief Set the ONACK field to a new value. /
mbed_official	324:406fd2029f23	3469	#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
mbed_official	324:406fd2029f23	3470	/@}/
mbed_official	324:406fd2029f23	3471
mbed_official	324:406fd2029f23	3472	/*******************************************************************************
mbed_official	324:406fd2029f23	3473	* HW_UART_IE7816 - UART 7816 Interrupt Enable Register
mbed_official	324:406fd2029f23	3474	******************************************************************************/
mbed_official	324:406fd2029f23	3475
mbed_official	324:406fd2029f23	3476	/*!
mbed_official	324:406fd2029f23	3477	* @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
mbed_official	324:406fd2029f23	3478	*
mbed_official	324:406fd2029f23	3479	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3480	*
mbed_official	324:406fd2029f23	3481	* The IE7816 register controls which flags result in an interrupt being issued.
mbed_official	324:406fd2029f23	3482	* This register is specific to 7816 functionality, the corresponding flags that
mbed_official	324:406fd2029f23	3483	* drive the interrupts are not asserted when 7816E is not set/enabled. However,
mbed_official	324:406fd2029f23	3484	* these flags may remain set if they are asserted while 7816E was set and not
mbed_official	324:406fd2029f23	3485	* subsequently cleared. This register may be read or written to at any time.
mbed_official	324:406fd2029f23	3486	*/
mbed_official	324:406fd2029f23	3487	typedef union _hw_uart_ie7816
mbed_official	324:406fd2029f23	3488	{
mbed_official	324:406fd2029f23	3489	uint8_t U;
mbed_official	324:406fd2029f23	3490	struct _hw_uart_ie7816_bitfields
mbed_official	324:406fd2029f23	3491	{
mbed_official	324:406fd2029f23	3492	uint8_t RXTE : 1; /*!< [0] Receive Threshold Exceeded Interrupt
mbed_official	324:406fd2029f23	3493	* Enable */
mbed_official	324:406fd2029f23	3494	uint8_t TXTE : 1; /*!< [1] Transmit Threshold Exceeded Interrupt
mbed_official	324:406fd2029f23	3495	* Enable */
mbed_official	324:406fd2029f23	3496	uint8_t GTVE : 1; /!< [2] Guard Timer Violated Interrupt Enable /
mbed_official	324:406fd2029f23	3497	uint8_t RESERVED0 : 1; /!< [3] /
mbed_official	324:406fd2029f23	3498	uint8_t INITDE : 1; /*!< [4] Initial Character Detected Interrupt
mbed_official	324:406fd2029f23	3499	* Enable */
mbed_official	324:406fd2029f23	3500	uint8_t BWTE : 1; /!< [5] Block Wait Timer Interrupt Enable /
mbed_official	324:406fd2029f23	3501	uint8_t CWTE : 1; /!< [6] Character Wait Timer Interrupt Enable /
mbed_official	324:406fd2029f23	3502	uint8_t WTE : 1; /!< [7] Wait Timer Interrupt Enable /
mbed_official	324:406fd2029f23	3503	} B;
mbed_official	324:406fd2029f23	3504	} hw_uart_ie7816_t;
mbed_official	324:406fd2029f23	3505
mbed_official	324:406fd2029f23	3506	/*!
mbed_official	324:406fd2029f23	3507	* @name Constants and macros for entire UART_IE7816 register
mbed_official	324:406fd2029f23	3508	*/
mbed_official	324:406fd2029f23	3509	/@{/
mbed_official	324:406fd2029f23	3510	#define HW_UART_IE7816_ADDR(x) ((x) + 0x19U)
mbed_official	324:406fd2029f23	3511
mbed_official	324:406fd2029f23	3512	#define HW_UART_IE7816(x) ((__IO hw_uart_ie7816_t ) HW_UART_IE7816_ADDR(x))
mbed_official	324:406fd2029f23	3513	#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
mbed_official	324:406fd2029f23	3514	#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
mbed_official	324:406fd2029f23	3515	#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3516	#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3517	#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3518	/@}/
mbed_official	324:406fd2029f23	3519
mbed_official	324:406fd2029f23	3520	/*
mbed_official	324:406fd2029f23	3521	* Constants & macros for individual UART_IE7816 bitfields
mbed_official	324:406fd2029f23	3522	*/
mbed_official	324:406fd2029f23	3523
mbed_official	324:406fd2029f23	3524	/*!
mbed_official	324:406fd2029f23	3525	* @name Register UART_IE7816, field RXTE[0] (RW)
mbed_official	324:406fd2029f23	3526	*
mbed_official	324:406fd2029f23	3527	* Values:
mbed_official	324:406fd2029f23	3528	* - 0 - The assertion of IS7816[RXT] does not result in the generation of an
mbed_official	324:406fd2029f23	3529	* interrupt.
mbed_official	324:406fd2029f23	3530	* - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3531	*/
mbed_official	324:406fd2029f23	3532	/@{/
mbed_official	324:406fd2029f23	3533	#define BP_UART_IE7816_RXTE (0U) /!< Bit position for UART_IE7816_RXTE. /
mbed_official	324:406fd2029f23	3534	#define BM_UART_IE7816_RXTE (0x01U) /!< Bit mask for UART_IE7816_RXTE. /
mbed_official	324:406fd2029f23	3535	#define BS_UART_IE7816_RXTE (1U) /!< Bit field size in bits for UART_IE7816_RXTE. /
mbed_official	324:406fd2029f23	3536
mbed_official	324:406fd2029f23	3537	/! @brief Read current value of the UART_IE7816_RXTE field. /
mbed_official	324:406fd2029f23	3538	#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
mbed_official	324:406fd2029f23	3539
mbed_official	324:406fd2029f23	3540	/! @brief Format value for bitfield UART_IE7816_RXTE. /
mbed_official	324:406fd2029f23	3541	#define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE)
mbed_official	324:406fd2029f23	3542
mbed_official	324:406fd2029f23	3543	/! @brief Set the RXTE field to a new value. /
mbed_official	324:406fd2029f23	3544	#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
mbed_official	324:406fd2029f23	3545	/@}/
mbed_official	324:406fd2029f23	3546
mbed_official	324:406fd2029f23	3547	/*!
mbed_official	324:406fd2029f23	3548	* @name Register UART_IE7816, field TXTE[1] (RW)
mbed_official	324:406fd2029f23	3549	*
mbed_official	324:406fd2029f23	3550	* Values:
mbed_official	324:406fd2029f23	3551	* - 0 - The assertion of IS7816[TXT] does not result in the generation of an
mbed_official	324:406fd2029f23	3552	* interrupt.
mbed_official	324:406fd2029f23	3553	* - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3554	*/
mbed_official	324:406fd2029f23	3555	/@{/
mbed_official	324:406fd2029f23	3556	#define BP_UART_IE7816_TXTE (1U) /!< Bit position for UART_IE7816_TXTE. /
mbed_official	324:406fd2029f23	3557	#define BM_UART_IE7816_TXTE (0x02U) /!< Bit mask for UART_IE7816_TXTE. /
mbed_official	324:406fd2029f23	3558	#define BS_UART_IE7816_TXTE (1U) /!< Bit field size in bits for UART_IE7816_TXTE. /
mbed_official	324:406fd2029f23	3559
mbed_official	324:406fd2029f23	3560	/! @brief Read current value of the UART_IE7816_TXTE field. /
mbed_official	324:406fd2029f23	3561	#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
mbed_official	324:406fd2029f23	3562
mbed_official	324:406fd2029f23	3563	/! @brief Format value for bitfield UART_IE7816_TXTE. /
mbed_official	324:406fd2029f23	3564	#define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE)
mbed_official	324:406fd2029f23	3565
mbed_official	324:406fd2029f23	3566	/! @brief Set the TXTE field to a new value. /
mbed_official	324:406fd2029f23	3567	#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
mbed_official	324:406fd2029f23	3568	/@}/
mbed_official	324:406fd2029f23	3569
mbed_official	324:406fd2029f23	3570	/*!
mbed_official	324:406fd2029f23	3571	* @name Register UART_IE7816, field GTVE[2] (RW)
mbed_official	324:406fd2029f23	3572	*
mbed_official	324:406fd2029f23	3573	* Values:
mbed_official	324:406fd2029f23	3574	* - 0 - The assertion of IS7816[GTV] does not result in the generation of an
mbed_official	324:406fd2029f23	3575	* interrupt.
mbed_official	324:406fd2029f23	3576	* - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3577	*/
mbed_official	324:406fd2029f23	3578	/@{/
mbed_official	324:406fd2029f23	3579	#define BP_UART_IE7816_GTVE (2U) /!< Bit position for UART_IE7816_GTVE. /
mbed_official	324:406fd2029f23	3580	#define BM_UART_IE7816_GTVE (0x04U) /!< Bit mask for UART_IE7816_GTVE. /
mbed_official	324:406fd2029f23	3581	#define BS_UART_IE7816_GTVE (1U) /!< Bit field size in bits for UART_IE7816_GTVE. /
mbed_official	324:406fd2029f23	3582
mbed_official	324:406fd2029f23	3583	/! @brief Read current value of the UART_IE7816_GTVE field. /
mbed_official	324:406fd2029f23	3584	#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
mbed_official	324:406fd2029f23	3585
mbed_official	324:406fd2029f23	3586	/! @brief Format value for bitfield UART_IE7816_GTVE. /
mbed_official	324:406fd2029f23	3587	#define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE)
mbed_official	324:406fd2029f23	3588
mbed_official	324:406fd2029f23	3589	/! @brief Set the GTVE field to a new value. /
mbed_official	324:406fd2029f23	3590	#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
mbed_official	324:406fd2029f23	3591	/@}/
mbed_official	324:406fd2029f23	3592
mbed_official	324:406fd2029f23	3593	/*!
mbed_official	324:406fd2029f23	3594	* @name Register UART_IE7816, field INITDE[4] (RW)
mbed_official	324:406fd2029f23	3595	*
mbed_official	324:406fd2029f23	3596	* Values:
mbed_official	324:406fd2029f23	3597	* - 0 - The assertion of IS7816[INITD] does not result in the generation of an
mbed_official	324:406fd2029f23	3598	* interrupt.
mbed_official	324:406fd2029f23	3599	* - 1 - The assertion of IS7816[INITD] results in the generation of an
mbed_official	324:406fd2029f23	3600	* interrupt.
mbed_official	324:406fd2029f23	3601	*/
mbed_official	324:406fd2029f23	3602	/@{/
mbed_official	324:406fd2029f23	3603	#define BP_UART_IE7816_INITDE (4U) /!< Bit position for UART_IE7816_INITDE. /
mbed_official	324:406fd2029f23	3604	#define BM_UART_IE7816_INITDE (0x10U) /!< Bit mask for UART_IE7816_INITDE. /
mbed_official	324:406fd2029f23	3605	#define BS_UART_IE7816_INITDE (1U) /!< Bit field size in bits for UART_IE7816_INITDE. /
mbed_official	324:406fd2029f23	3606
mbed_official	324:406fd2029f23	3607	/! @brief Read current value of the UART_IE7816_INITDE field. /
mbed_official	324:406fd2029f23	3608	#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
mbed_official	324:406fd2029f23	3609
mbed_official	324:406fd2029f23	3610	/! @brief Format value for bitfield UART_IE7816_INITDE. /
mbed_official	324:406fd2029f23	3611	#define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE)
mbed_official	324:406fd2029f23	3612
mbed_official	324:406fd2029f23	3613	/! @brief Set the INITDE field to a new value. /
mbed_official	324:406fd2029f23	3614	#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
mbed_official	324:406fd2029f23	3615	/@}/
mbed_official	324:406fd2029f23	3616
mbed_official	324:406fd2029f23	3617	/*!
mbed_official	324:406fd2029f23	3618	* @name Register UART_IE7816, field BWTE[5] (RW)
mbed_official	324:406fd2029f23	3619	*
mbed_official	324:406fd2029f23	3620	* Values:
mbed_official	324:406fd2029f23	3621	* - 0 - The assertion of IS7816[BWT] does not result in the generation of an
mbed_official	324:406fd2029f23	3622	* interrupt.
mbed_official	324:406fd2029f23	3623	* - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3624	*/
mbed_official	324:406fd2029f23	3625	/@{/
mbed_official	324:406fd2029f23	3626	#define BP_UART_IE7816_BWTE (5U) /!< Bit position for UART_IE7816_BWTE. /
mbed_official	324:406fd2029f23	3627	#define BM_UART_IE7816_BWTE (0x20U) /!< Bit mask for UART_IE7816_BWTE. /
mbed_official	324:406fd2029f23	3628	#define BS_UART_IE7816_BWTE (1U) /!< Bit field size in bits for UART_IE7816_BWTE. /
mbed_official	324:406fd2029f23	3629
mbed_official	324:406fd2029f23	3630	/! @brief Read current value of the UART_IE7816_BWTE field. /
mbed_official	324:406fd2029f23	3631	#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
mbed_official	324:406fd2029f23	3632
mbed_official	324:406fd2029f23	3633	/! @brief Format value for bitfield UART_IE7816_BWTE. /
mbed_official	324:406fd2029f23	3634	#define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE)
mbed_official	324:406fd2029f23	3635
mbed_official	324:406fd2029f23	3636	/! @brief Set the BWTE field to a new value. /
mbed_official	324:406fd2029f23	3637	#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
mbed_official	324:406fd2029f23	3638	/@}/
mbed_official	324:406fd2029f23	3639
mbed_official	324:406fd2029f23	3640	/*!
mbed_official	324:406fd2029f23	3641	* @name Register UART_IE7816, field CWTE[6] (RW)
mbed_official	324:406fd2029f23	3642	*
mbed_official	324:406fd2029f23	3643	* Values:
mbed_official	324:406fd2029f23	3644	* - 0 - The assertion of IS7816[CWT] does not result in the generation of an
mbed_official	324:406fd2029f23	3645	* interrupt.
mbed_official	324:406fd2029f23	3646	* - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3647	*/
mbed_official	324:406fd2029f23	3648	/@{/
mbed_official	324:406fd2029f23	3649	#define BP_UART_IE7816_CWTE (6U) /!< Bit position for UART_IE7816_CWTE. /
mbed_official	324:406fd2029f23	3650	#define BM_UART_IE7816_CWTE (0x40U) /!< Bit mask for UART_IE7816_CWTE. /
mbed_official	324:406fd2029f23	3651	#define BS_UART_IE7816_CWTE (1U) /!< Bit field size in bits for UART_IE7816_CWTE. /
mbed_official	324:406fd2029f23	3652
mbed_official	324:406fd2029f23	3653	/! @brief Read current value of the UART_IE7816_CWTE field. /
mbed_official	324:406fd2029f23	3654	#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
mbed_official	324:406fd2029f23	3655
mbed_official	324:406fd2029f23	3656	/! @brief Format value for bitfield UART_IE7816_CWTE. /
mbed_official	324:406fd2029f23	3657	#define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE)
mbed_official	324:406fd2029f23	3658
mbed_official	324:406fd2029f23	3659	/! @brief Set the CWTE field to a new value. /
mbed_official	324:406fd2029f23	3660	#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
mbed_official	324:406fd2029f23	3661	/@}/
mbed_official	324:406fd2029f23	3662
mbed_official	324:406fd2029f23	3663	/*!
mbed_official	324:406fd2029f23	3664	* @name Register UART_IE7816, field WTE[7] (RW)
mbed_official	324:406fd2029f23	3665	*
mbed_official	324:406fd2029f23	3666	* Values:
mbed_official	324:406fd2029f23	3667	* - 0 - The assertion of IS7816[WT] does not result in the generation of an
mbed_official	324:406fd2029f23	3668	* interrupt.
mbed_official	324:406fd2029f23	3669	* - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
mbed_official	324:406fd2029f23	3670	*/
mbed_official	324:406fd2029f23	3671	/@{/
mbed_official	324:406fd2029f23	3672	#define BP_UART_IE7816_WTE (7U) /!< Bit position for UART_IE7816_WTE. /
mbed_official	324:406fd2029f23	3673	#define BM_UART_IE7816_WTE (0x80U) /!< Bit mask for UART_IE7816_WTE. /
mbed_official	324:406fd2029f23	3674	#define BS_UART_IE7816_WTE (1U) /!< Bit field size in bits for UART_IE7816_WTE. /
mbed_official	324:406fd2029f23	3675
mbed_official	324:406fd2029f23	3676	/! @brief Read current value of the UART_IE7816_WTE field. /
mbed_official	324:406fd2029f23	3677	#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
mbed_official	324:406fd2029f23	3678
mbed_official	324:406fd2029f23	3679	/! @brief Format value for bitfield UART_IE7816_WTE. /
mbed_official	324:406fd2029f23	3680	#define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE)
mbed_official	324:406fd2029f23	3681
mbed_official	324:406fd2029f23	3682	/! @brief Set the WTE field to a new value. /
mbed_official	324:406fd2029f23	3683	#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
mbed_official	324:406fd2029f23	3684	/@}/
mbed_official	324:406fd2029f23	3685
mbed_official	324:406fd2029f23	3686	/*******************************************************************************
mbed_official	324:406fd2029f23	3687	* HW_UART_IS7816 - UART 7816 Interrupt Status Register
mbed_official	324:406fd2029f23	3688	******************************************************************************/
mbed_official	324:406fd2029f23	3689
mbed_official	324:406fd2029f23	3690	/*!
mbed_official	324:406fd2029f23	3691	* @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
mbed_official	324:406fd2029f23	3692	*
mbed_official	324:406fd2029f23	3693	* Reset value: 0x00U
mbed_official	324:406fd2029f23	3694	*
mbed_official	324:406fd2029f23	3695	* The IS7816 register provides a mechanism to read and clear the interrupt
mbed_official	324:406fd2029f23	3696	* flags. All flags/interrupts are cleared by writing a 1 to the field location.
mbed_official	324:406fd2029f23	3697	* Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
mbed_official	324:406fd2029f23	3698	* the flag condition that occurred since the last time the bit was cleared, not
mbed_official	324:406fd2029f23	3699	* that the condition currently exists. The status flags are set regardless of
mbed_official	324:406fd2029f23	3700	* whether the corresponding field in the IE7816 is set or cleared. The IE7816
mbed_official	324:406fd2029f23	3701	* controls only if an interrupt is issued to the host processor. This register is
mbed_official	324:406fd2029f23	3702	* specific to 7816 functionality and the values in this register have no affect on
mbed_official	324:406fd2029f23	3703	* UART operation and should be ignored if 7816E is not set/enabled. This
mbed_official	324:406fd2029f23	3704	* register may be read or written at anytime.
mbed_official	324:406fd2029f23	3705	*/
mbed_official	324:406fd2029f23	3706	typedef union _hw_uart_is7816
mbed_official	324:406fd2029f23	3707	{
mbed_official	324:406fd2029f23	3708	uint8_t U;
mbed_official	324:406fd2029f23	3709	struct _hw_uart_is7816_bitfields
mbed_official	324:406fd2029f23	3710	{
mbed_official	324:406fd2029f23	3711	uint8_t RXT : 1; /!< [0] Receive Threshold Exceeded Interrupt /
mbed_official	324:406fd2029f23	3712	uint8_t TXT : 1; /!< [1] Transmit Threshold Exceeded Interrupt /
mbed_official	324:406fd2029f23	3713	uint8_t GTV : 1; /!< [2] Guard Timer Violated Interrupt /
mbed_official	324:406fd2029f23	3714	uint8_t RESERVED0 : 1; /!< [3] /
mbed_official	324:406fd2029f23	3715	uint8_t INITD : 1; /!< [4] Initial Character Detected Interrupt /
mbed_official	324:406fd2029f23	3716	uint8_t BWT : 1; /!< [5] Block Wait Timer Interrupt /
mbed_official	324:406fd2029f23	3717	uint8_t CWT : 1; /!< [6] Character Wait Timer Interrupt /
mbed_official	324:406fd2029f23	3718	uint8_t WT : 1; /!< [7] Wait Timer Interrupt /
mbed_official	324:406fd2029f23	3719	} B;
mbed_official	324:406fd2029f23	3720	} hw_uart_is7816_t;
mbed_official	324:406fd2029f23	3721
mbed_official	324:406fd2029f23	3722	/*!
mbed_official	324:406fd2029f23	3723	* @name Constants and macros for entire UART_IS7816 register
mbed_official	324:406fd2029f23	3724	*/
mbed_official	324:406fd2029f23	3725	/@{/
mbed_official	324:406fd2029f23	3726	#define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU)
mbed_official	324:406fd2029f23	3727
mbed_official	324:406fd2029f23	3728	#define HW_UART_IS7816(x) ((__IO hw_uart_is7816_t ) HW_UART_IS7816_ADDR(x))
mbed_official	324:406fd2029f23	3729	#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
mbed_official	324:406fd2029f23	3730	#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
mbed_official	324:406fd2029f23	3731	#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3732	#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3733	#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3734	/@}/
mbed_official	324:406fd2029f23	3735
mbed_official	324:406fd2029f23	3736	/*
mbed_official	324:406fd2029f23	3737	* Constants & macros for individual UART_IS7816 bitfields
mbed_official	324:406fd2029f23	3738	*/
mbed_official	324:406fd2029f23	3739
mbed_official	324:406fd2029f23	3740	/*!
mbed_official	324:406fd2029f23	3741	* @name Register UART_IS7816, field RXT[0] (W1C)
mbed_official	324:406fd2029f23	3742	*
mbed_official	324:406fd2029f23	3743	* Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
mbed_official	324:406fd2029f23	3744	* generated in response to parity errors on received data. This flag requires ANACK
mbed_official	324:406fd2029f23	3745	* to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
mbed_official	324:406fd2029f23	3746	* Clearing this field also resets the counter keeping track of consecutive NACKS. The
mbed_official	324:406fd2029f23	3747	* UART will continue to attempt to receive data regardless of whether this flag
mbed_official	324:406fd2029f23	3748	* is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
mbed_official	324:406fd2029f23	3749	* or packet is received without needing to issue a NACK, the internal NACK
mbed_official	324:406fd2029f23	3750	* detection counter is cleared and the count restarts from zero on the next
mbed_official	324:406fd2029f23	3751	* transmitted NACK. This interrupt is cleared by writing 1.
mbed_official	324:406fd2029f23	3752	*
mbed_official	324:406fd2029f23	3753	* Values:
mbed_official	324:406fd2029f23	3754	* - 0 - The number of consecutive NACKS generated as a result of parity errors
mbed_official	324:406fd2029f23	3755	* and buffer overruns is less than or equal to the value in
mbed_official	324:406fd2029f23	3756	* ET7816[RXTHRESHOLD].
mbed_official	324:406fd2029f23	3757	* - 1 - The number of consecutive NACKS generated as a result of parity errors
mbed_official	324:406fd2029f23	3758	* and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
mbed_official	324:406fd2029f23	3759	*/
mbed_official	324:406fd2029f23	3760	/@{/
mbed_official	324:406fd2029f23	3761	#define BP_UART_IS7816_RXT (0U) /!< Bit position for UART_IS7816_RXT. /
mbed_official	324:406fd2029f23	3762	#define BM_UART_IS7816_RXT (0x01U) /!< Bit mask for UART_IS7816_RXT. /
mbed_official	324:406fd2029f23	3763	#define BS_UART_IS7816_RXT (1U) /!< Bit field size in bits for UART_IS7816_RXT. /
mbed_official	324:406fd2029f23	3764
mbed_official	324:406fd2029f23	3765	/! @brief Read current value of the UART_IS7816_RXT field. /
mbed_official	324:406fd2029f23	3766	#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
mbed_official	324:406fd2029f23	3767
mbed_official	324:406fd2029f23	3768	/! @brief Format value for bitfield UART_IS7816_RXT. /
mbed_official	324:406fd2029f23	3769	#define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT)
mbed_official	324:406fd2029f23	3770
mbed_official	324:406fd2029f23	3771	/! @brief Set the RXT field to a new value. /
mbed_official	324:406fd2029f23	3772	#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
mbed_official	324:406fd2029f23	3773	/@}/
mbed_official	324:406fd2029f23	3774
mbed_official	324:406fd2029f23	3775	/*!
mbed_official	324:406fd2029f23	3776	* @name Register UART_IS7816, field TXT[1] (W1C)
mbed_official	324:406fd2029f23	3777	*
mbed_official	324:406fd2029f23	3778	* Indicates that the transmit NACK threshold has been exceeded as indicated by
mbed_official	324:406fd2029f23	3779	* ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
mbed_official	324:406fd2029f23	3780	* continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
mbed_official	324:406fd2029f23	3781	* 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
mbed_official	324:406fd2029f23	3782	* cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
mbed_official	324:406fd2029f23	3783	* internal NACK detection counter is cleared and the count restarts from zero on
mbed_official	324:406fd2029f23	3784	* the next received NACK. This interrupt is cleared by writing 1.
mbed_official	324:406fd2029f23	3785	*
mbed_official	324:406fd2029f23	3786	* Values:
mbed_official	324:406fd2029f23	3787	* - 0 - The number of retries and corresponding NACKS does not exceed the value
mbed_official	324:406fd2029f23	3788	* in ET7816[TXTHRESHOLD].
mbed_official	324:406fd2029f23	3789	* - 1 - The number of retries and corresponding NACKS exceeds the value in
mbed_official	324:406fd2029f23	3790	* ET7816[TXTHRESHOLD].
mbed_official	324:406fd2029f23	3791	*/
mbed_official	324:406fd2029f23	3792	/@{/
mbed_official	324:406fd2029f23	3793	#define BP_UART_IS7816_TXT (1U) /!< Bit position for UART_IS7816_TXT. /
mbed_official	324:406fd2029f23	3794	#define BM_UART_IS7816_TXT (0x02U) /!< Bit mask for UART_IS7816_TXT. /
mbed_official	324:406fd2029f23	3795	#define BS_UART_IS7816_TXT (1U) /!< Bit field size in bits for UART_IS7816_TXT. /
mbed_official	324:406fd2029f23	3796
mbed_official	324:406fd2029f23	3797	/! @brief Read current value of the UART_IS7816_TXT field. /
mbed_official	324:406fd2029f23	3798	#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
mbed_official	324:406fd2029f23	3799
mbed_official	324:406fd2029f23	3800	/! @brief Format value for bitfield UART_IS7816_TXT. /
mbed_official	324:406fd2029f23	3801	#define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT)
mbed_official	324:406fd2029f23	3802
mbed_official	324:406fd2029f23	3803	/! @brief Set the TXT field to a new value. /
mbed_official	324:406fd2029f23	3804	#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
mbed_official	324:406fd2029f23	3805	/@}/
mbed_official	324:406fd2029f23	3806
mbed_official	324:406fd2029f23	3807	/*!
mbed_official	324:406fd2029f23	3808	* @name Register UART_IS7816, field GTV[2] (W1C)
mbed_official	324:406fd2029f23	3809	*
mbed_official	324:406fd2029f23	3810	* Indicates that one or more of the character guard time, block guard time, or
mbed_official	324:406fd2029f23	3811	* guard time are violated. This interrupt is cleared by writing 1.
mbed_official	324:406fd2029f23	3812	*
mbed_official	324:406fd2029f23	3813	* Values:
mbed_official	324:406fd2029f23	3814	* - 0 - A guard time (GT, CGT, or BGT) has not been violated.
mbed_official	324:406fd2029f23	3815	* - 1 - A guard time (GT, CGT, or BGT) has been violated.
mbed_official	324:406fd2029f23	3816	*/
mbed_official	324:406fd2029f23	3817	/@{/
mbed_official	324:406fd2029f23	3818	#define BP_UART_IS7816_GTV (2U) /!< Bit position for UART_IS7816_GTV. /
mbed_official	324:406fd2029f23	3819	#define BM_UART_IS7816_GTV (0x04U) /!< Bit mask for UART_IS7816_GTV. /
mbed_official	324:406fd2029f23	3820	#define BS_UART_IS7816_GTV (1U) /!< Bit field size in bits for UART_IS7816_GTV. /
mbed_official	324:406fd2029f23	3821
mbed_official	324:406fd2029f23	3822	/! @brief Read current value of the UART_IS7816_GTV field. /
mbed_official	324:406fd2029f23	3823	#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
mbed_official	324:406fd2029f23	3824
mbed_official	324:406fd2029f23	3825	/! @brief Format value for bitfield UART_IS7816_GTV. /
mbed_official	324:406fd2029f23	3826	#define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV)
mbed_official	324:406fd2029f23	3827
mbed_official	324:406fd2029f23	3828	/! @brief Set the GTV field to a new value. /
mbed_official	324:406fd2029f23	3829	#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
mbed_official	324:406fd2029f23	3830	/@}/
mbed_official	324:406fd2029f23	3831
mbed_official	324:406fd2029f23	3832	/*!
mbed_official	324:406fd2029f23	3833	* @name Register UART_IS7816, field INITD[4] (W1C)
mbed_official	324:406fd2029f23	3834	*
mbed_official	324:406fd2029f23	3835	* Indicates that a valid initial character is received. This interrupt is
mbed_official	324:406fd2029f23	3836	* cleared by writing 1.
mbed_official	324:406fd2029f23	3837	*
mbed_official	324:406fd2029f23	3838	* Values:
mbed_official	324:406fd2029f23	3839	* - 0 - A valid initial character has not been received.
mbed_official	324:406fd2029f23	3840	* - 1 - A valid initial character has been received.
mbed_official	324:406fd2029f23	3841	*/
mbed_official	324:406fd2029f23	3842	/@{/
mbed_official	324:406fd2029f23	3843	#define BP_UART_IS7816_INITD (4U) /!< Bit position for UART_IS7816_INITD. /
mbed_official	324:406fd2029f23	3844	#define BM_UART_IS7816_INITD (0x10U) /!< Bit mask for UART_IS7816_INITD. /
mbed_official	324:406fd2029f23	3845	#define BS_UART_IS7816_INITD (1U) /!< Bit field size in bits for UART_IS7816_INITD. /
mbed_official	324:406fd2029f23	3846
mbed_official	324:406fd2029f23	3847	/! @brief Read current value of the UART_IS7816_INITD field. /
mbed_official	324:406fd2029f23	3848	#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
mbed_official	324:406fd2029f23	3849
mbed_official	324:406fd2029f23	3850	/! @brief Format value for bitfield UART_IS7816_INITD. /
mbed_official	324:406fd2029f23	3851	#define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD)
mbed_official	324:406fd2029f23	3852
mbed_official	324:406fd2029f23	3853	/! @brief Set the INITD field to a new value. /
mbed_official	324:406fd2029f23	3854	#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
mbed_official	324:406fd2029f23	3855	/@}/
mbed_official	324:406fd2029f23	3856
mbed_official	324:406fd2029f23	3857	/*!
mbed_official	324:406fd2029f23	3858	* @name Register UART_IS7816, field BWT[5] (W1C)
mbed_official	324:406fd2029f23	3859	*
mbed_official	324:406fd2029f23	3860	* Indicates that the block wait time, the time between the leading edge of
mbed_official	324:406fd2029f23	3861	* first received character of a block and the leading edge of the last character the
mbed_official	324:406fd2029f23	3862	* previously transmitted block, has exceeded the programmed value. This flag
mbed_official	324:406fd2029f23	3863	* asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
mbed_official	324:406fd2029f23	3864	*
mbed_official	324:406fd2029f23	3865	* Values:
mbed_official	324:406fd2029f23	3866	* - 0 - Block wait time (BWT) has not been violated.
mbed_official	324:406fd2029f23	3867	* - 1 - Block wait time (BWT) has been violated.
mbed_official	324:406fd2029f23	3868	*/
mbed_official	324:406fd2029f23	3869	/@{/
mbed_official	324:406fd2029f23	3870	#define BP_UART_IS7816_BWT (5U) /!< Bit position for UART_IS7816_BWT. /
mbed_official	324:406fd2029f23	3871	#define BM_UART_IS7816_BWT (0x20U) /!< Bit mask for UART_IS7816_BWT. /
mbed_official	324:406fd2029f23	3872	#define BS_UART_IS7816_BWT (1U) /!< Bit field size in bits for UART_IS7816_BWT. /
mbed_official	324:406fd2029f23	3873
mbed_official	324:406fd2029f23	3874	/! @brief Read current value of the UART_IS7816_BWT field. /
mbed_official	324:406fd2029f23	3875	#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
mbed_official	324:406fd2029f23	3876
mbed_official	324:406fd2029f23	3877	/! @brief Format value for bitfield UART_IS7816_BWT. /
mbed_official	324:406fd2029f23	3878	#define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT)
mbed_official	324:406fd2029f23	3879
mbed_official	324:406fd2029f23	3880	/! @brief Set the BWT field to a new value. /
mbed_official	324:406fd2029f23	3881	#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
mbed_official	324:406fd2029f23	3882	/@}/
mbed_official	324:406fd2029f23	3883
mbed_official	324:406fd2029f23	3884	/*!
mbed_official	324:406fd2029f23	3885	* @name Register UART_IS7816, field CWT[6] (W1C)
mbed_official	324:406fd2029f23	3886	*
mbed_official	324:406fd2029f23	3887	* Indicates that the character wait time, the time between the leading edges of
mbed_official	324:406fd2029f23	3888	* two consecutive characters in a block, has exceeded the programmed value.
mbed_official	324:406fd2029f23	3889	* This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
mbed_official	324:406fd2029f23	3890	* writing 1.
mbed_official	324:406fd2029f23	3891	*
mbed_official	324:406fd2029f23	3892	* Values:
mbed_official	324:406fd2029f23	3893	* - 0 - Character wait time (CWT) has not been violated.
mbed_official	324:406fd2029f23	3894	* - 1 - Character wait time (CWT) has been violated.
mbed_official	324:406fd2029f23	3895	*/
mbed_official	324:406fd2029f23	3896	/@{/
mbed_official	324:406fd2029f23	3897	#define BP_UART_IS7816_CWT (6U) /!< Bit position for UART_IS7816_CWT. /
mbed_official	324:406fd2029f23	3898	#define BM_UART_IS7816_CWT (0x40U) /!< Bit mask for UART_IS7816_CWT. /
mbed_official	324:406fd2029f23	3899	#define BS_UART_IS7816_CWT (1U) /!< Bit field size in bits for UART_IS7816_CWT. /
mbed_official	324:406fd2029f23	3900
mbed_official	324:406fd2029f23	3901	/! @brief Read current value of the UART_IS7816_CWT field. /
mbed_official	324:406fd2029f23	3902	#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
mbed_official	324:406fd2029f23	3903
mbed_official	324:406fd2029f23	3904	/! @brief Format value for bitfield UART_IS7816_CWT. /
mbed_official	324:406fd2029f23	3905	#define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT)
mbed_official	324:406fd2029f23	3906
mbed_official	324:406fd2029f23	3907	/! @brief Set the CWT field to a new value. /
mbed_official	324:406fd2029f23	3908	#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
mbed_official	324:406fd2029f23	3909	/@}/
mbed_official	324:406fd2029f23	3910
mbed_official	324:406fd2029f23	3911	/*!
mbed_official	324:406fd2029f23	3912	* @name Register UART_IS7816, field WT[7] (W1C)
mbed_official	324:406fd2029f23	3913	*
mbed_official	324:406fd2029f23	3914	* Indicates that the wait time, the time between the leading edge of a
mbed_official	324:406fd2029f23	3915	* character being transmitted and the leading edge of the next response character, has
mbed_official	324:406fd2029f23	3916	* exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
mbed_official	324:406fd2029f23	3917	* This interrupt is cleared by writing 1.
mbed_official	324:406fd2029f23	3918	*
mbed_official	324:406fd2029f23	3919	* Values:
mbed_official	324:406fd2029f23	3920	* - 0 - Wait time (WT) has not been violated.
mbed_official	324:406fd2029f23	3921	* - 1 - Wait time (WT) has been violated.
mbed_official	324:406fd2029f23	3922	*/
mbed_official	324:406fd2029f23	3923	/@{/
mbed_official	324:406fd2029f23	3924	#define BP_UART_IS7816_WT (7U) /!< Bit position for UART_IS7816_WT. /
mbed_official	324:406fd2029f23	3925	#define BM_UART_IS7816_WT (0x80U) /!< Bit mask for UART_IS7816_WT. /
mbed_official	324:406fd2029f23	3926	#define BS_UART_IS7816_WT (1U) /!< Bit field size in bits for UART_IS7816_WT. /
mbed_official	324:406fd2029f23	3927
mbed_official	324:406fd2029f23	3928	/! @brief Read current value of the UART_IS7816_WT field. /
mbed_official	324:406fd2029f23	3929	#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
mbed_official	324:406fd2029f23	3930
mbed_official	324:406fd2029f23	3931	/! @brief Format value for bitfield UART_IS7816_WT. /
mbed_official	324:406fd2029f23	3932	#define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT)
mbed_official	324:406fd2029f23	3933
mbed_official	324:406fd2029f23	3934	/! @brief Set the WT field to a new value. /
mbed_official	324:406fd2029f23	3935	#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
mbed_official	324:406fd2029f23	3936	/@}/
mbed_official	324:406fd2029f23	3937
mbed_official	324:406fd2029f23	3938	/*******************************************************************************
mbed_official	324:406fd2029f23	3939	* HW_UART_WP7816T0 - UART 7816 Wait Parameter Register
mbed_official	324:406fd2029f23	3940	******************************************************************************/
mbed_official	324:406fd2029f23	3941
mbed_official	324:406fd2029f23	3942	/*!
mbed_official	324:406fd2029f23	3943	* @brief HW_UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
mbed_official	324:406fd2029f23	3944	*
mbed_official	324:406fd2029f23	3945	* Reset value: 0x0AU
mbed_official	324:406fd2029f23	3946	*
mbed_official	324:406fd2029f23	3947	* The WP7816 register contains constants used in the generation of various wait
mbed_official	324:406fd2029f23	3948	* timer counters. To save register space, this register is used differently
mbed_official	324:406fd2029f23	3949	* when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
mbed_official	324:406fd2029f23	3950	* time. This register must be written to only when C7816[ISO_7816E] is not set.
mbed_official	324:406fd2029f23	3951	*/
mbed_official	324:406fd2029f23	3952	typedef union _hw_uart_wp7816t0
mbed_official	324:406fd2029f23	3953	{
mbed_official	324:406fd2029f23	3954	uint8_t U;
mbed_official	324:406fd2029f23	3955	struct _hw_uart_wp7816t0_bitfields
mbed_official	324:406fd2029f23	3956	{
mbed_official	324:406fd2029f23	3957	uint8_t WI : 8; /!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) /
mbed_official	324:406fd2029f23	3958	} B;
mbed_official	324:406fd2029f23	3959	} hw_uart_wp7816t0_t;
mbed_official	324:406fd2029f23	3960
mbed_official	324:406fd2029f23	3961	/*!
mbed_official	324:406fd2029f23	3962	* @name Constants and macros for entire UART_WP7816T0 register
mbed_official	324:406fd2029f23	3963	*/
mbed_official	324:406fd2029f23	3964	/@{/
mbed_official	324:406fd2029f23	3965	#define HW_UART_WP7816T0_ADDR(x) ((x) + 0x1BU)
mbed_official	324:406fd2029f23	3966
mbed_official	324:406fd2029f23	3967	#define HW_UART_WP7816T0(x) ((__IO hw_uart_wp7816t0_t ) HW_UART_WP7816T0_ADDR(x))
mbed_official	324:406fd2029f23	3968	#define HW_UART_WP7816T0_RD(x) (HW_UART_WP7816T0(x).U)
mbed_official	324:406fd2029f23	3969	#define HW_UART_WP7816T0_WR(x, v) (HW_UART_WP7816T0(x).U = (v))
mbed_official	324:406fd2029f23	3970	#define HW_UART_WP7816T0_SET(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3971	#define HW_UART_WP7816T0_CLR(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3972	#define HW_UART_WP7816T0_TOG(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3973	/@}/
mbed_official	324:406fd2029f23	3974
mbed_official	324:406fd2029f23	3975	/*
mbed_official	324:406fd2029f23	3976	* Constants & macros for individual UART_WP7816T0 bitfields
mbed_official	324:406fd2029f23	3977	*/
mbed_official	324:406fd2029f23	3978
mbed_official	324:406fd2029f23	3979	/*!
mbed_official	324:406fd2029f23	3980	* @name Register UART_WP7816T0, field WI[7:0] (RW)
mbed_official	324:406fd2029f23	3981	*
mbed_official	324:406fd2029f23	3982	* Used to calculate the value used for the WT counter. It represents a value
mbed_official	324:406fd2029f23	3983	* between 1 and 255. The value of zero is not valid. This value is used only when
mbed_official	324:406fd2029f23	3984	* C7816[TTYPE] = 0. See Wait time and guard time parameters.
mbed_official	324:406fd2029f23	3985	*/
mbed_official	324:406fd2029f23	3986	/@{/
mbed_official	324:406fd2029f23	3987	#define BP_UART_WP7816T0_WI (0U) /!< Bit position for UART_WP7816T0_WI. /
mbed_official	324:406fd2029f23	3988	#define BM_UART_WP7816T0_WI (0xFFU) /!< Bit mask for UART_WP7816T0_WI. /
mbed_official	324:406fd2029f23	3989	#define BS_UART_WP7816T0_WI (8U) /!< Bit field size in bits for UART_WP7816T0_WI. /
mbed_official	324:406fd2029f23	3990
mbed_official	324:406fd2029f23	3991	/! @brief Read current value of the UART_WP7816T0_WI field. /
mbed_official	324:406fd2029f23	3992	#define BR_UART_WP7816T0_WI(x) (HW_UART_WP7816T0(x).U)
mbed_official	324:406fd2029f23	3993
mbed_official	324:406fd2029f23	3994	/! @brief Format value for bitfield UART_WP7816T0_WI. /
mbed_official	324:406fd2029f23	3995	#define BF_UART_WP7816T0_WI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T0_WI) & BM_UART_WP7816T0_WI)
mbed_official	324:406fd2029f23	3996
mbed_official	324:406fd2029f23	3997	/! @brief Set the WI field to a new value. /
mbed_official	324:406fd2029f23	3998	#define BW_UART_WP7816T0_WI(x, v) (HW_UART_WP7816T0_WR(x, v))
mbed_official	324:406fd2029f23	3999	/@}/
mbed_official	324:406fd2029f23	4000	/*******************************************************************************
mbed_official	324:406fd2029f23	4001	* HW_UART_WP7816T1 - UART 7816 Wait Parameter Register
mbed_official	324:406fd2029f23	4002	******************************************************************************/
mbed_official	324:406fd2029f23	4003
mbed_official	324:406fd2029f23	4004	/*!
mbed_official	324:406fd2029f23	4005	* @brief HW_UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
mbed_official	324:406fd2029f23	4006	*
mbed_official	324:406fd2029f23	4007	* Reset value: 0x0AU
mbed_official	324:406fd2029f23	4008	*
mbed_official	324:406fd2029f23	4009	* The WP7816 register contains constants used in the generation of various wait
mbed_official	324:406fd2029f23	4010	* timer counters. To save register space, this register is used differently
mbed_official	324:406fd2029f23	4011	* when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
mbed_official	324:406fd2029f23	4012	* time. This register must be written to only when C7816[ISO_7816E] is not set.
mbed_official	324:406fd2029f23	4013	*/
mbed_official	324:406fd2029f23	4014	typedef union _hw_uart_wp7816t1
mbed_official	324:406fd2029f23	4015	{
mbed_official	324:406fd2029f23	4016	uint8_t U;
mbed_official	324:406fd2029f23	4017	struct _hw_uart_wp7816t1_bitfields
mbed_official	324:406fd2029f23	4018	{
mbed_official	324:406fd2029f23	4019	uint8_t BWI : 4; /*!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
mbed_official	324:406fd2029f23	4020	* */
mbed_official	324:406fd2029f23	4021	uint8_t CWI : 4; /*!< [7:4] Character Wait Time Integer (C7816[TTYPE]
mbed_official	324:406fd2029f23	4022	* = 1) */
mbed_official	324:406fd2029f23	4023	} B;
mbed_official	324:406fd2029f23	4024	} hw_uart_wp7816t1_t;
mbed_official	324:406fd2029f23	4025
mbed_official	324:406fd2029f23	4026	/*!
mbed_official	324:406fd2029f23	4027	* @name Constants and macros for entire UART_WP7816T1 register
mbed_official	324:406fd2029f23	4028	*/
mbed_official	324:406fd2029f23	4029	/@{/
mbed_official	324:406fd2029f23	4030	#define HW_UART_WP7816T1_ADDR(x) ((x) + 0x1BU)
mbed_official	324:406fd2029f23	4031
mbed_official	324:406fd2029f23	4032	#define HW_UART_WP7816T1(x) ((__IO hw_uart_wp7816t1_t ) HW_UART_WP7816T1_ADDR(x))
mbed_official	324:406fd2029f23	4033	#define HW_UART_WP7816T1_RD(x) (HW_UART_WP7816T1(x).U)
mbed_official	324:406fd2029f23	4034	#define HW_UART_WP7816T1_WR(x, v) (HW_UART_WP7816T1(x).U = (v))
mbed_official	324:406fd2029f23	4035	#define HW_UART_WP7816T1_SET(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4036	#define HW_UART_WP7816T1_CLR(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4037	#define HW_UART_WP7816T1_TOG(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4038	/@}/
mbed_official	324:406fd2029f23	4039
mbed_official	324:406fd2029f23	4040	/*
mbed_official	324:406fd2029f23	4041	* Constants & macros for individual UART_WP7816T1 bitfields
mbed_official	324:406fd2029f23	4042	*/
mbed_official	324:406fd2029f23	4043
mbed_official	324:406fd2029f23	4044	/*!
mbed_official	324:406fd2029f23	4045	* @name Register UART_WP7816T1, field BWI[3:0] (RW)
mbed_official	324:406fd2029f23	4046	*
mbed_official	324:406fd2029f23	4047	* Used to calculate the value used for the BWT counter. It represent a value
mbed_official	324:406fd2029f23	4048	* between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
mbed_official	324:406fd2029f23	4049	* and guard time parameters .
mbed_official	324:406fd2029f23	4050	*/
mbed_official	324:406fd2029f23	4051	/@{/
mbed_official	324:406fd2029f23	4052	#define BP_UART_WP7816T1_BWI (0U) /!< Bit position for UART_WP7816T1_BWI. /
mbed_official	324:406fd2029f23	4053	#define BM_UART_WP7816T1_BWI (0x0FU) /!< Bit mask for UART_WP7816T1_BWI. /
mbed_official	324:406fd2029f23	4054	#define BS_UART_WP7816T1_BWI (4U) /!< Bit field size in bits for UART_WP7816T1_BWI. /
mbed_official	324:406fd2029f23	4055
mbed_official	324:406fd2029f23	4056	/! @brief Read current value of the UART_WP7816T1_BWI field. /
mbed_official	324:406fd2029f23	4057	#define BR_UART_WP7816T1_BWI(x) (HW_UART_WP7816T1(x).B.BWI)
mbed_official	324:406fd2029f23	4058
mbed_official	324:406fd2029f23	4059	/! @brief Format value for bitfield UART_WP7816T1_BWI. /
mbed_official	324:406fd2029f23	4060	#define BF_UART_WP7816T1_BWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_BWI) & BM_UART_WP7816T1_BWI)
mbed_official	324:406fd2029f23	4061
mbed_official	324:406fd2029f23	4062	/! @brief Set the BWI field to a new value. /
mbed_official	324:406fd2029f23	4063	#define BW_UART_WP7816T1_BWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_BWI) \| BF_UART_WP7816T1_BWI(v)))
mbed_official	324:406fd2029f23	4064	/@}/
mbed_official	324:406fd2029f23	4065
mbed_official	324:406fd2029f23	4066	/*!
mbed_official	324:406fd2029f23	4067	* @name Register UART_WP7816T1, field CWI[7:4] (RW)
mbed_official	324:406fd2029f23	4068	*
mbed_official	324:406fd2029f23	4069	* Used to calculate the value used for the CWT counter. It represents a value
mbed_official	324:406fd2029f23	4070	* between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
mbed_official	324:406fd2029f23	4071	* and guard time parameters .
mbed_official	324:406fd2029f23	4072	*/
mbed_official	324:406fd2029f23	4073	/@{/
mbed_official	324:406fd2029f23	4074	#define BP_UART_WP7816T1_CWI (4U) /!< Bit position for UART_WP7816T1_CWI. /
mbed_official	324:406fd2029f23	4075	#define BM_UART_WP7816T1_CWI (0xF0U) /!< Bit mask for UART_WP7816T1_CWI. /
mbed_official	324:406fd2029f23	4076	#define BS_UART_WP7816T1_CWI (4U) /!< Bit field size in bits for UART_WP7816T1_CWI. /
mbed_official	324:406fd2029f23	4077
mbed_official	324:406fd2029f23	4078	/! @brief Read current value of the UART_WP7816T1_CWI field. /
mbed_official	324:406fd2029f23	4079	#define BR_UART_WP7816T1_CWI(x) (HW_UART_WP7816T1(x).B.CWI)
mbed_official	324:406fd2029f23	4080
mbed_official	324:406fd2029f23	4081	/! @brief Format value for bitfield UART_WP7816T1_CWI. /
mbed_official	324:406fd2029f23	4082	#define BF_UART_WP7816T1_CWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_CWI) & BM_UART_WP7816T1_CWI)
mbed_official	324:406fd2029f23	4083
mbed_official	324:406fd2029f23	4084	/! @brief Set the CWI field to a new value. /
mbed_official	324:406fd2029f23	4085	#define BW_UART_WP7816T1_CWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_CWI) \| BF_UART_WP7816T1_CWI(v)))
mbed_official	324:406fd2029f23	4086	/@}/
mbed_official	324:406fd2029f23	4087
mbed_official	324:406fd2029f23	4088	/*******************************************************************************
mbed_official	324:406fd2029f23	4089	* HW_UART_WN7816 - UART 7816 Wait N Register
mbed_official	324:406fd2029f23	4090	******************************************************************************/
mbed_official	324:406fd2029f23	4091
mbed_official	324:406fd2029f23	4092	/*!
mbed_official	324:406fd2029f23	4093	* @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
mbed_official	324:406fd2029f23	4094	*
mbed_official	324:406fd2029f23	4095	* Reset value: 0x00U
mbed_official	324:406fd2029f23	4096	*
mbed_official	324:406fd2029f23	4097	* The WN7816 register contains a parameter that is used in the calculation of
mbed_official	324:406fd2029f23	4098	* the guard time counter. This register may be read at any time. This register
mbed_official	324:406fd2029f23	4099	* must be written to only when C7816[ISO_7816E] is not set.
mbed_official	324:406fd2029f23	4100	*/
mbed_official	324:406fd2029f23	4101	typedef union _hw_uart_wn7816
mbed_official	324:406fd2029f23	4102	{
mbed_official	324:406fd2029f23	4103	uint8_t U;
mbed_official	324:406fd2029f23	4104	struct _hw_uart_wn7816_bitfields
mbed_official	324:406fd2029f23	4105	{
mbed_official	324:406fd2029f23	4106	uint8_t GTN : 8; /!< [7:0] Guard Band N /
mbed_official	324:406fd2029f23	4107	} B;
mbed_official	324:406fd2029f23	4108	} hw_uart_wn7816_t;
mbed_official	324:406fd2029f23	4109
mbed_official	324:406fd2029f23	4110	/*!
mbed_official	324:406fd2029f23	4111	* @name Constants and macros for entire UART_WN7816 register
mbed_official	324:406fd2029f23	4112	*/
mbed_official	324:406fd2029f23	4113	/@{/
mbed_official	324:406fd2029f23	4114	#define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU)
mbed_official	324:406fd2029f23	4115
mbed_official	324:406fd2029f23	4116	#define HW_UART_WN7816(x) ((__IO hw_uart_wn7816_t ) HW_UART_WN7816_ADDR(x))
mbed_official	324:406fd2029f23	4117	#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
mbed_official	324:406fd2029f23	4118	#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
mbed_official	324:406fd2029f23	4119	#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4120	#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4121	#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4122	/@}/
mbed_official	324:406fd2029f23	4123
mbed_official	324:406fd2029f23	4124	/*
mbed_official	324:406fd2029f23	4125	* Constants & macros for individual UART_WN7816 bitfields
mbed_official	324:406fd2029f23	4126	*/
mbed_official	324:406fd2029f23	4127
mbed_official	324:406fd2029f23	4128	/*!
mbed_official	324:406fd2029f23	4129	* @name Register UART_WN7816, field GTN[7:0] (RW)
mbed_official	324:406fd2029f23	4130	*
mbed_official	324:406fd2029f23	4131	* Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
mbed_official	324:406fd2029f23	4132	* value represents an integer number between 0 and 255. See Wait time and guard
mbed_official	324:406fd2029f23	4133	* time parameters .
mbed_official	324:406fd2029f23	4134	*/
mbed_official	324:406fd2029f23	4135	/@{/
mbed_official	324:406fd2029f23	4136	#define BP_UART_WN7816_GTN (0U) /!< Bit position for UART_WN7816_GTN. /
mbed_official	324:406fd2029f23	4137	#define BM_UART_WN7816_GTN (0xFFU) /!< Bit mask for UART_WN7816_GTN. /
mbed_official	324:406fd2029f23	4138	#define BS_UART_WN7816_GTN (8U) /!< Bit field size in bits for UART_WN7816_GTN. /
mbed_official	324:406fd2029f23	4139
mbed_official	324:406fd2029f23	4140	/! @brief Read current value of the UART_WN7816_GTN field. /
mbed_official	324:406fd2029f23	4141	#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
mbed_official	324:406fd2029f23	4142
mbed_official	324:406fd2029f23	4143	/! @brief Format value for bitfield UART_WN7816_GTN. /
mbed_official	324:406fd2029f23	4144	#define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN)
mbed_official	324:406fd2029f23	4145
mbed_official	324:406fd2029f23	4146	/! @brief Set the GTN field to a new value. /
mbed_official	324:406fd2029f23	4147	#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
mbed_official	324:406fd2029f23	4148	/@}/
mbed_official	324:406fd2029f23	4149
mbed_official	324:406fd2029f23	4150	/*******************************************************************************
mbed_official	324:406fd2029f23	4151	* HW_UART_WF7816 - UART 7816 Wait FD Register
mbed_official	324:406fd2029f23	4152	******************************************************************************/
mbed_official	324:406fd2029f23	4153
mbed_official	324:406fd2029f23	4154	/*!
mbed_official	324:406fd2029f23	4155	* @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
mbed_official	324:406fd2029f23	4156	*
mbed_official	324:406fd2029f23	4157	* Reset value: 0x01U
mbed_official	324:406fd2029f23	4158	*
mbed_official	324:406fd2029f23	4159	* The WF7816 contains parameters that are used in the generation of various
mbed_official	324:406fd2029f23	4160	* counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
mbed_official	324:406fd2029f23	4161	* time. This register must be written to only when C7816[ISO_7816E] is not set.
mbed_official	324:406fd2029f23	4162	*/
mbed_official	324:406fd2029f23	4163	typedef union _hw_uart_wf7816
mbed_official	324:406fd2029f23	4164	{
mbed_official	324:406fd2029f23	4165	uint8_t U;
mbed_official	324:406fd2029f23	4166	struct _hw_uart_wf7816_bitfields
mbed_official	324:406fd2029f23	4167	{
mbed_official	324:406fd2029f23	4168	uint8_t GTFD : 8; /!< [7:0] FD Multiplier /
mbed_official	324:406fd2029f23	4169	} B;
mbed_official	324:406fd2029f23	4170	} hw_uart_wf7816_t;
mbed_official	324:406fd2029f23	4171
mbed_official	324:406fd2029f23	4172	/*!
mbed_official	324:406fd2029f23	4173	* @name Constants and macros for entire UART_WF7816 register
mbed_official	324:406fd2029f23	4174	*/
mbed_official	324:406fd2029f23	4175	/@{/
mbed_official	324:406fd2029f23	4176	#define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU)
mbed_official	324:406fd2029f23	4177
mbed_official	324:406fd2029f23	4178	#define HW_UART_WF7816(x) ((__IO hw_uart_wf7816_t ) HW_UART_WF7816_ADDR(x))
mbed_official	324:406fd2029f23	4179	#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
mbed_official	324:406fd2029f23	4180	#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
mbed_official	324:406fd2029f23	4181	#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4182	#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4183	#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4184	/@}/
mbed_official	324:406fd2029f23	4185
mbed_official	324:406fd2029f23	4186	/*
mbed_official	324:406fd2029f23	4187	* Constants & macros for individual UART_WF7816 bitfields
mbed_official	324:406fd2029f23	4188	*/
mbed_official	324:406fd2029f23	4189
mbed_official	324:406fd2029f23	4190	/*!
mbed_official	324:406fd2029f23	4191	* @name Register UART_WF7816, field GTFD[7:0] (RW)
mbed_official	324:406fd2029f23	4192	*
mbed_official	324:406fd2029f23	4193	* Used as another multiplier in the calculation of WT and BWT. This value
mbed_official	324:406fd2029f23	4194	* represents a number between 1 and 255. The value of 0 is invalid. This value is not
mbed_official	324:406fd2029f23	4195	* used in baud rate generation. See Wait time and guard time parameters and
mbed_official	324:406fd2029f23	4196	* Baud rate generation .
mbed_official	324:406fd2029f23	4197	*/
mbed_official	324:406fd2029f23	4198	/@{/
mbed_official	324:406fd2029f23	4199	#define BP_UART_WF7816_GTFD (0U) /!< Bit position for UART_WF7816_GTFD. /
mbed_official	324:406fd2029f23	4200	#define BM_UART_WF7816_GTFD (0xFFU) /!< Bit mask for UART_WF7816_GTFD. /
mbed_official	324:406fd2029f23	4201	#define BS_UART_WF7816_GTFD (8U) /!< Bit field size in bits for UART_WF7816_GTFD. /
mbed_official	324:406fd2029f23	4202
mbed_official	324:406fd2029f23	4203	/! @brief Read current value of the UART_WF7816_GTFD field. /
mbed_official	324:406fd2029f23	4204	#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
mbed_official	324:406fd2029f23	4205
mbed_official	324:406fd2029f23	4206	/! @brief Format value for bitfield UART_WF7816_GTFD. /
mbed_official	324:406fd2029f23	4207	#define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD)
mbed_official	324:406fd2029f23	4208
mbed_official	324:406fd2029f23	4209	/! @brief Set the GTFD field to a new value. /
mbed_official	324:406fd2029f23	4210	#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
mbed_official	324:406fd2029f23	4211	/@}/
mbed_official	324:406fd2029f23	4212
mbed_official	324:406fd2029f23	4213	/*******************************************************************************
mbed_official	324:406fd2029f23	4214	* HW_UART_ET7816 - UART 7816 Error Threshold Register
mbed_official	324:406fd2029f23	4215	******************************************************************************/
mbed_official	324:406fd2029f23	4216
mbed_official	324:406fd2029f23	4217	/*!
mbed_official	324:406fd2029f23	4218	* @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
mbed_official	324:406fd2029f23	4219	*
mbed_official	324:406fd2029f23	4220	* Reset value: 0x00U
mbed_official	324:406fd2029f23	4221	*
mbed_official	324:406fd2029f23	4222	* The ET7816 register contains fields that determine the number of NACKs that
mbed_official	324:406fd2029f23	4223	* must be received or transmitted before the host processor is notified. This
mbed_official	324:406fd2029f23	4224	* register may be read at anytime. This register must be written to only when
mbed_official	324:406fd2029f23	4225	* C7816[ISO_7816E] is not set.
mbed_official	324:406fd2029f23	4226	*/
mbed_official	324:406fd2029f23	4227	typedef union _hw_uart_et7816
mbed_official	324:406fd2029f23	4228	{
mbed_official	324:406fd2029f23	4229	uint8_t U;
mbed_official	324:406fd2029f23	4230	struct _hw_uart_et7816_bitfields
mbed_official	324:406fd2029f23	4231	{
mbed_official	324:406fd2029f23	4232	uint8_t RXTHRESHOLD : 4; /!< [3:0] Receive NACK Threshold /
mbed_official	324:406fd2029f23	4233	uint8_t TXTHRESHOLD : 4; /!< [7:4] Transmit NACK Threshold /
mbed_official	324:406fd2029f23	4234	} B;
mbed_official	324:406fd2029f23	4235	} hw_uart_et7816_t;
mbed_official	324:406fd2029f23	4236
mbed_official	324:406fd2029f23	4237	/*!
mbed_official	324:406fd2029f23	4238	* @name Constants and macros for entire UART_ET7816 register
mbed_official	324:406fd2029f23	4239	*/
mbed_official	324:406fd2029f23	4240	/@{/
mbed_official	324:406fd2029f23	4241	#define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU)
mbed_official	324:406fd2029f23	4242
mbed_official	324:406fd2029f23	4243	#define HW_UART_ET7816(x) ((__IO hw_uart_et7816_t ) HW_UART_ET7816_ADDR(x))
mbed_official	324:406fd2029f23	4244	#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
mbed_official	324:406fd2029f23	4245	#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
mbed_official	324:406fd2029f23	4246	#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4247	#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4248	#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4249	/@}/
mbed_official	324:406fd2029f23	4250
mbed_official	324:406fd2029f23	4251	/*
mbed_official	324:406fd2029f23	4252	* Constants & macros for individual UART_ET7816 bitfields
mbed_official	324:406fd2029f23	4253	*/
mbed_official	324:406fd2029f23	4254
mbed_official	324:406fd2029f23	4255	/*!
mbed_official	324:406fd2029f23	4256	* @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
mbed_official	324:406fd2029f23	4257	*
mbed_official	324:406fd2029f23	4258	* The value written to this field indicates the maximum number of consecutive
mbed_official	324:406fd2029f23	4259	* NACKs generated as a result of a parity error or receiver buffer overruns
mbed_official	324:406fd2029f23	4260	* before the host processor is notified. After the counter exceeds that value in the
mbed_official	324:406fd2029f23	4261	* field, the IS7816[RXT] is asserted. This field is meaningful only when
mbed_official	324:406fd2029f23	4262	* C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
mbed_official	324:406fd2029f23	4263	* NACKs that have been transmitted since the last successful reception. This
mbed_official	324:406fd2029f23	4264	* counter saturates at 4'hF and does not wrap around. Regardless of the number of
mbed_official	324:406fd2029f23	4265	* NACKs sent, the UART continues to receive valid packets indefinitely. For
mbed_official	324:406fd2029f23	4266	* additional information, see IS7816[RXT] field description.
mbed_official	324:406fd2029f23	4267	*/
mbed_official	324:406fd2029f23	4268	/@{/
mbed_official	324:406fd2029f23	4269	#define BP_UART_ET7816_RXTHRESHOLD (0U) /!< Bit position for UART_ET7816_RXTHRESHOLD. /
mbed_official	324:406fd2029f23	4270	#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /!< Bit mask for UART_ET7816_RXTHRESHOLD. /
mbed_official	324:406fd2029f23	4271	#define BS_UART_ET7816_RXTHRESHOLD (4U) /!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. /
mbed_official	324:406fd2029f23	4272
mbed_official	324:406fd2029f23	4273	/! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. /
mbed_official	324:406fd2029f23	4274	#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
mbed_official	324:406fd2029f23	4275
mbed_official	324:406fd2029f23	4276	/! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. /
mbed_official	324:406fd2029f23	4277	#define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD)
mbed_official	324:406fd2029f23	4278
mbed_official	324:406fd2029f23	4279	/! @brief Set the RXTHRESHOLD field to a new value. /
mbed_official	324:406fd2029f23	4280	#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) \| BF_UART_ET7816_RXTHRESHOLD(v)))
mbed_official	324:406fd2029f23	4281	/@}/
mbed_official	324:406fd2029f23	4282
mbed_official	324:406fd2029f23	4283	/*!
mbed_official	324:406fd2029f23	4284	* @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
mbed_official	324:406fd2029f23	4285	*
mbed_official	324:406fd2029f23	4286	* The value written to this field indicates the maximum number of failed
mbed_official	324:406fd2029f23	4287	* attempts (NACKs) a transmitted character can have before the host processor is
mbed_official	324:406fd2029f23	4288	* notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
mbed_official	324:406fd2029f23	4289	* The value read from this field represents the number of consecutive NACKs
mbed_official	324:406fd2029f23	4290	* that have been received since the last successful transmission. This counter
mbed_official	324:406fd2029f23	4291	* saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
mbed_official	324:406fd2029f23	4292	* received, the UART continues to retransmit indefinitely. This flag only
mbed_official	324:406fd2029f23	4293	* asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
mbed_official	324:406fd2029f23	4294	* description.
mbed_official	324:406fd2029f23	4295	*
mbed_official	324:406fd2029f23	4296	* Values:
mbed_official	324:406fd2029f23	4297	* - 0 - TXT asserts on the first NACK that is received.
mbed_official	324:406fd2029f23	4298	* - 1 - TXT asserts on the second NACK that is received.
mbed_official	324:406fd2029f23	4299	*/
mbed_official	324:406fd2029f23	4300	/@{/
mbed_official	324:406fd2029f23	4301	#define BP_UART_ET7816_TXTHRESHOLD (4U) /!< Bit position for UART_ET7816_TXTHRESHOLD. /
mbed_official	324:406fd2029f23	4302	#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /!< Bit mask for UART_ET7816_TXTHRESHOLD. /
mbed_official	324:406fd2029f23	4303	#define BS_UART_ET7816_TXTHRESHOLD (4U) /!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. /
mbed_official	324:406fd2029f23	4304
mbed_official	324:406fd2029f23	4305	/! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. /
mbed_official	324:406fd2029f23	4306	#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
mbed_official	324:406fd2029f23	4307
mbed_official	324:406fd2029f23	4308	/! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. /
mbed_official	324:406fd2029f23	4309	#define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD)
mbed_official	324:406fd2029f23	4310
mbed_official	324:406fd2029f23	4311	/! @brief Set the TXTHRESHOLD field to a new value. /
mbed_official	324:406fd2029f23	4312	#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) \| BF_UART_ET7816_TXTHRESHOLD(v)))
mbed_official	324:406fd2029f23	4313	/@}/
mbed_official	324:406fd2029f23	4314
mbed_official	324:406fd2029f23	4315	/*******************************************************************************
mbed_official	324:406fd2029f23	4316	* HW_UART_TL7816 - UART 7816 Transmit Length Register
mbed_official	324:406fd2029f23	4317	******************************************************************************/
mbed_official	324:406fd2029f23	4318
mbed_official	324:406fd2029f23	4319	/*!
mbed_official	324:406fd2029f23	4320	* @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
mbed_official	324:406fd2029f23	4321	*
mbed_official	324:406fd2029f23	4322	* Reset value: 0x00U
mbed_official	324:406fd2029f23	4323	*
mbed_official	324:406fd2029f23	4324	* The TL7816 register is used to indicate the number of characters contained in
mbed_official	324:406fd2029f23	4325	* the block being transmitted. This register is used only when C7816[TTYPE] =
mbed_official	324:406fd2029f23	4326	* 1. This register may be read at anytime. This register must be written only
mbed_official	324:406fd2029f23	4327	* when C2[TE] is not enabled.
mbed_official	324:406fd2029f23	4328	*/
mbed_official	324:406fd2029f23	4329	typedef union _hw_uart_tl7816
mbed_official	324:406fd2029f23	4330	{
mbed_official	324:406fd2029f23	4331	uint8_t U;
mbed_official	324:406fd2029f23	4332	struct _hw_uart_tl7816_bitfields
mbed_official	324:406fd2029f23	4333	{
mbed_official	324:406fd2029f23	4334	uint8_t TLEN : 8; /!< [7:0] Transmit Length /
mbed_official	324:406fd2029f23	4335	} B;
mbed_official	324:406fd2029f23	4336	} hw_uart_tl7816_t;
mbed_official	324:406fd2029f23	4337
mbed_official	324:406fd2029f23	4338	/*!
mbed_official	324:406fd2029f23	4339	* @name Constants and macros for entire UART_TL7816 register
mbed_official	324:406fd2029f23	4340	*/
mbed_official	324:406fd2029f23	4341	/@{/
mbed_official	324:406fd2029f23	4342	#define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU)
mbed_official	324:406fd2029f23	4343
mbed_official	324:406fd2029f23	4344	#define HW_UART_TL7816(x) ((__IO hw_uart_tl7816_t ) HW_UART_TL7816_ADDR(x))
mbed_official	324:406fd2029f23	4345	#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
mbed_official	324:406fd2029f23	4346	#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
mbed_official	324:406fd2029f23	4347	#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4348	#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4349	#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4350	/@}/
mbed_official	324:406fd2029f23	4351
mbed_official	324:406fd2029f23	4352	/*
mbed_official	324:406fd2029f23	4353	* Constants & macros for individual UART_TL7816 bitfields
mbed_official	324:406fd2029f23	4354	*/
mbed_official	324:406fd2029f23	4355
mbed_official	324:406fd2029f23	4356	/*!
mbed_official	324:406fd2029f23	4357	* @name Register UART_TL7816, field TLEN[7:0] (RW)
mbed_official	324:406fd2029f23	4358	*
mbed_official	324:406fd2029f23	4359	* This value plus four indicates the number of characters contained in the
mbed_official	324:406fd2029f23	4360	* block being transmitted. This register is automatically decremented by 1 for each
mbed_official	324:406fd2029f23	4361	* character in the information field portion of the block. Additionally, this
mbed_official	324:406fd2029f23	4362	* register is automatically decremented by 1 for the first character of a CRC in
mbed_official	324:406fd2029f23	4363	* the epilogue field. Therefore, this register must be programmed with the number
mbed_official	324:406fd2029f23	4364	* of bytes in the data packet if an LRC is being transmitted, and the number of
mbed_official	324:406fd2029f23	4365	* bytes + 1 if a CRC is being transmitted. This register is not decremented for
mbed_official	324:406fd2029f23	4366	* characters that are assumed to be part of the Prologue field, that is, the
mbed_official	324:406fd2029f23	4367	* first three characters transmitted in a block, or the LRC or last CRC character
mbed_official	324:406fd2029f23	4368	* in the Epilogue field, that is, the last character transmitted. This field
mbed_official	324:406fd2029f23	4369	* must be programed or adjusted only when C2[TE] is cleared.
mbed_official	324:406fd2029f23	4370	*/
mbed_official	324:406fd2029f23	4371	/@{/
mbed_official	324:406fd2029f23	4372	#define BP_UART_TL7816_TLEN (0U) /!< Bit position for UART_TL7816_TLEN. /
mbed_official	324:406fd2029f23	4373	#define BM_UART_TL7816_TLEN (0xFFU) /!< Bit mask for UART_TL7816_TLEN. /
mbed_official	324:406fd2029f23	4374	#define BS_UART_TL7816_TLEN (8U) /!< Bit field size in bits for UART_TL7816_TLEN. /
mbed_official	324:406fd2029f23	4375
mbed_official	324:406fd2029f23	4376	/! @brief Read current value of the UART_TL7816_TLEN field. /
mbed_official	324:406fd2029f23	4377	#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
mbed_official	324:406fd2029f23	4378
mbed_official	324:406fd2029f23	4379	/! @brief Format value for bitfield UART_TL7816_TLEN. /
mbed_official	324:406fd2029f23	4380	#define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN)
mbed_official	324:406fd2029f23	4381
mbed_official	324:406fd2029f23	4382	/! @brief Set the TLEN field to a new value. /
mbed_official	324:406fd2029f23	4383	#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
mbed_official	324:406fd2029f23	4384	/@}/
mbed_official	324:406fd2029f23	4385
mbed_official	324:406fd2029f23	4386	/*
mbed_official	324:406fd2029f23	4387	** Start of section using anonymous unions
mbed_official	324:406fd2029f23	4388	*/
mbed_official	324:406fd2029f23	4389
mbed_official	324:406fd2029f23	4390	#if defined(__ARMCC_VERSION)
mbed_official	324:406fd2029f23	4391	#pragma push
mbed_official	324:406fd2029f23	4392	#pragma anon_unions
mbed_official	324:406fd2029f23	4393	#elif defined(__CWCC__)
mbed_official	324:406fd2029f23	4394	#pragma push
mbed_official	324:406fd2029f23	4395	#pragma cpp_extensions on
mbed_official	324:406fd2029f23	4396	#elif defined(__GNUC__)
mbed_official	324:406fd2029f23	4397	/* anonymous unions are enabled by default */
mbed_official	324:406fd2029f23	4398	#elif defined(__IAR_SYSTEMS_ICC__)
mbed_official	324:406fd2029f23	4399	#pragma language=extended
mbed_official	324:406fd2029f23	4400	#else
mbed_official	324:406fd2029f23	4401	#error Not supported compiler type
mbed_official	324:406fd2029f23	4402	#endif
mbed_official	324:406fd2029f23	4403
mbed_official	324:406fd2029f23	4404	/*******************************************************************************
mbed_official	324:406fd2029f23	4405	* hw_uart_t - module struct
mbed_official	324:406fd2029f23	4406	******************************************************************************/
mbed_official	324:406fd2029f23	4407	/*!
mbed_official	324:406fd2029f23	4408	* @brief All UART module registers.
mbed_official	324:406fd2029f23	4409	*/
mbed_official	324:406fd2029f23	4410	#pragma pack(1)
mbed_official	324:406fd2029f23	4411	typedef struct _hw_uart
mbed_official	324:406fd2029f23	4412	{
mbed_official	324:406fd2029f23	4413	__IO hw_uart_bdh_t BDH; /!< [0x0] UART Baud Rate Registers: High /
mbed_official	324:406fd2029f23	4414	__IO hw_uart_bdl_t BDL; /!< [0x1] UART Baud Rate Registers: Low /
mbed_official	324:406fd2029f23	4415	__IO hw_uart_c1_t C1; /!< [0x2] UART Control Register 1 /
mbed_official	324:406fd2029f23	4416	__IO hw_uart_c2_t C2; /!< [0x3] UART Control Register 2 /
mbed_official	324:406fd2029f23	4417	__I hw_uart_s1_t S1; /!< [0x4] UART Status Register 1 /
mbed_official	324:406fd2029f23	4418	__IO hw_uart_s2_t S2; /!< [0x5] UART Status Register 2 /
mbed_official	324:406fd2029f23	4419	__IO hw_uart_c3_t C3; /!< [0x6] UART Control Register 3 /
mbed_official	324:406fd2029f23	4420	__IO hw_uart_d_t D; /!< [0x7] UART Data Register /
mbed_official	324:406fd2029f23	4421	__IO hw_uart_ma1_t MA1; /!< [0x8] UART Match Address Registers 1 /
mbed_official	324:406fd2029f23	4422	__IO hw_uart_ma2_t MA2; /!< [0x9] UART Match Address Registers 2 /
mbed_official	324:406fd2029f23	4423	__IO hw_uart_c4_t C4; /!< [0xA] UART Control Register 4 /
mbed_official	324:406fd2029f23	4424	__IO hw_uart_c5_t C5; /!< [0xB] UART Control Register 5 /
mbed_official	324:406fd2029f23	4425	__I hw_uart_ed_t ED; /!< [0xC] UART Extended Data Register /
mbed_official	324:406fd2029f23	4426	__IO hw_uart_modem_t MODEM; /!< [0xD] UART Modem Register /
mbed_official	324:406fd2029f23	4427	__IO hw_uart_ir_t IR; /!< [0xE] UART Infrared Register /
mbed_official	324:406fd2029f23	4428	uint8_t _reserved0[1];
mbed_official	324:406fd2029f23	4429	__IO hw_uart_pfifo_t PFIFO; /!< [0x10] UART FIFO Parameters /
mbed_official	324:406fd2029f23	4430	__IO hw_uart_cfifo_t CFIFO; /!< [0x11] UART FIFO Control Register /
mbed_official	324:406fd2029f23	4431	__IO hw_uart_sfifo_t SFIFO; /!< [0x12] UART FIFO Status Register /
mbed_official	324:406fd2029f23	4432	__IO hw_uart_twfifo_t TWFIFO; /!< [0x13] UART FIFO Transmit Watermark /
mbed_official	324:406fd2029f23	4433	__I hw_uart_tcfifo_t TCFIFO; /!< [0x14] UART FIFO Transmit Count /
mbed_official	324:406fd2029f23	4434	__IO hw_uart_rwfifo_t RWFIFO; /!< [0x15] UART FIFO Receive Watermark /
mbed_official	324:406fd2029f23	4435	__I hw_uart_rcfifo_t RCFIFO; /!< [0x16] UART FIFO Receive Count /
mbed_official	324:406fd2029f23	4436	uint8_t _reserved1[1];
mbed_official	324:406fd2029f23	4437	__IO hw_uart_c7816_t C7816; /!< [0x18] UART 7816 Control Register /
mbed_official	324:406fd2029f23	4438	__IO hw_uart_ie7816_t IE7816; /!< [0x19] UART 7816 Interrupt Enable Register /
mbed_official	324:406fd2029f23	4439	__IO hw_uart_is7816_t IS7816; /!< [0x1A] UART 7816 Interrupt Status Register /
mbed_official	324:406fd2029f23	4440	union {
mbed_official	324:406fd2029f23	4441	__IO hw_uart_wp7816t0_t WP7816T0; /!< [0x1B] UART 7816 Wait Parameter Register /
mbed_official	324:406fd2029f23	4442	__IO hw_uart_wp7816t1_t WP7816T1; /!< [0x1B] UART 7816 Wait Parameter Register /
mbed_official	324:406fd2029f23	4443	};
mbed_official	324:406fd2029f23	4444	__IO hw_uart_wn7816_t WN7816; /!< [0x1C] UART 7816 Wait N Register /
mbed_official	324:406fd2029f23	4445	__IO hw_uart_wf7816_t WF7816; /!< [0x1D] UART 7816 Wait FD Register /
mbed_official	324:406fd2029f23	4446	__IO hw_uart_et7816_t ET7816; /!< [0x1E] UART 7816 Error Threshold Register /
mbed_official	324:406fd2029f23	4447	__IO hw_uart_tl7816_t TL7816; /!< [0x1F] UART 7816 Transmit Length Register /
mbed_official	324:406fd2029f23	4448	} hw_uart_t;
mbed_official	324:406fd2029f23	4449	#pragma pack()
mbed_official	324:406fd2029f23	4450
mbed_official	324:406fd2029f23	4451	/! @brief Macro to access all UART registers. /
mbed_official	324:406fd2029f23	4452	/! @param x UART module instance base address. /
mbed_official	324:406fd2029f23	4453	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	4454	* use the '&' operator, like <code>&HW_UART(UART0_BASE)</code>. */
mbed_official	324:406fd2029f23	4455	#define HW_UART(x) ((hw_uart_t )(x))
mbed_official	324:406fd2029f23	4456
mbed_official	324:406fd2029f23	4457	/*
mbed_official	324:406fd2029f23	4458	** End of section using anonymous unions
mbed_official	324:406fd2029f23	4459	*/
mbed_official	324:406fd2029f23	4460
mbed_official	324:406fd2029f23	4461	#if defined(__ARMCC_VERSION)
mbed_official	324:406fd2029f23	4462	#pragma pop
mbed_official	324:406fd2029f23	4463	#elif defined(__CWCC__)
mbed_official	324:406fd2029f23	4464	#pragma pop
mbed_official	324:406fd2029f23	4465	#elif defined(__GNUC__)
mbed_official	324:406fd2029f23	4466	/* leave anonymous unions enabled */
mbed_official	324:406fd2029f23	4467	#elif defined(__IAR_SYSTEMS_ICC__)
mbed_official	324:406fd2029f23	4468	#pragma language=default
mbed_official	324:406fd2029f23	4469	#else
mbed_official	324:406fd2029f23	4470	#error Not supported compiler type
mbed_official	324:406fd2029f23	4471	#endif
mbed_official	324:406fd2029f23	4472
mbed_official	324:406fd2029f23	4473	#endif /* __HW_UART_REGISTERS_H__ */
mbed_official	324:406fd2029f23	4474	/* EOF */