mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_SIM_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_SIM_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 SIM
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* System Integration Module
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_SIM_SOPT1 - System Options Register 1
mbed_official	324:406fd2029f23	93	* - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
mbed_official	324:406fd2029f23	94	* - HW_SIM_SOPT2 - System Options Register 2
mbed_official	324:406fd2029f23	95	* - HW_SIM_SOPT4 - System Options Register 4
mbed_official	324:406fd2029f23	96	* - HW_SIM_SOPT5 - System Options Register 5
mbed_official	324:406fd2029f23	97	* - HW_SIM_SOPT7 - System Options Register 7
mbed_official	324:406fd2029f23	98	* - HW_SIM_SDID - System Device Identification Register
mbed_official	324:406fd2029f23	99	* - HW_SIM_SCGC1 - System Clock Gating Control Register 1
mbed_official	324:406fd2029f23	100	* - HW_SIM_SCGC2 - System Clock Gating Control Register 2
mbed_official	324:406fd2029f23	101	* - HW_SIM_SCGC3 - System Clock Gating Control Register 3
mbed_official	324:406fd2029f23	102	* - HW_SIM_SCGC4 - System Clock Gating Control Register 4
mbed_official	324:406fd2029f23	103	* - HW_SIM_SCGC5 - System Clock Gating Control Register 5
mbed_official	324:406fd2029f23	104	* - HW_SIM_SCGC6 - System Clock Gating Control Register 6
mbed_official	324:406fd2029f23	105	* - HW_SIM_SCGC7 - System Clock Gating Control Register 7
mbed_official	324:406fd2029f23	106	* - HW_SIM_CLKDIV1 - System Clock Divider Register 1
mbed_official	324:406fd2029f23	107	* - HW_SIM_CLKDIV2 - System Clock Divider Register 2
mbed_official	324:406fd2029f23	108	* - HW_SIM_FCFG1 - Flash Configuration Register 1
mbed_official	324:406fd2029f23	109	* - HW_SIM_FCFG2 - Flash Configuration Register 2
mbed_official	324:406fd2029f23	110	* - HW_SIM_UIDH - Unique Identification Register High
mbed_official	324:406fd2029f23	111	* - HW_SIM_UIDMH - Unique Identification Register Mid-High
mbed_official	324:406fd2029f23	112	* - HW_SIM_UIDML - Unique Identification Register Mid Low
mbed_official	324:406fd2029f23	113	* - HW_SIM_UIDL - Unique Identification Register Low
mbed_official	324:406fd2029f23	114	*
mbed_official	324:406fd2029f23	115	* - hw_sim_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	116	*/
mbed_official	324:406fd2029f23	117
mbed_official	324:406fd2029f23	118	#define HW_SIM_INSTANCE_COUNT (1U) /!< Number of instances of the SIM module. /
mbed_official	324:406fd2029f23	119
mbed_official	324:406fd2029f23	120	/*******************************************************************************
mbed_official	324:406fd2029f23	121	* HW_SIM_SOPT1 - System Options Register 1
mbed_official	324:406fd2029f23	122	******************************************************************************/
mbed_official	324:406fd2029f23	123
mbed_official	324:406fd2029f23	124	/*!
mbed_official	324:406fd2029f23	125	* @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
mbed_official	324:406fd2029f23	126	*
mbed_official	324:406fd2029f23	127	* Reset value: 0x80000000U
mbed_official	324:406fd2029f23	128	*
mbed_official	324:406fd2029f23	129	* The SOPT1 register is only reset on POR or LVD.
mbed_official	324:406fd2029f23	130	*/
mbed_official	324:406fd2029f23	131	typedef union _hw_sim_sopt1
mbed_official	324:406fd2029f23	132	{
mbed_official	324:406fd2029f23	133	uint32_t U;
mbed_official	324:406fd2029f23	134	struct _hw_sim_sopt1_bitfields
mbed_official	324:406fd2029f23	135	{
mbed_official	324:406fd2029f23	136	uint32_t RESERVED0 : 12; /!< [11:0] /
mbed_official	324:406fd2029f23	137	uint32_t RAMSIZE : 4; /!< [15:12] RAM size /
mbed_official	324:406fd2029f23	138	uint32_t RESERVED1 : 2; /!< [17:16] /
mbed_official	324:406fd2029f23	139	uint32_t OSC32KSEL : 2; /!< [19:18] 32K oscillator clock select /
mbed_official	324:406fd2029f23	140	uint32_t RESERVED2 : 9; /!< [28:20] /
mbed_official	324:406fd2029f23	141	uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby
mbed_official	324:406fd2029f23	142	* mode during VLPR and VLPW modes */
mbed_official	324:406fd2029f23	143	uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby
mbed_official	324:406fd2029f23	144	* mode during Stop, VLPS, LLS and VLLS modes. */
mbed_official	324:406fd2029f23	145	uint32_t USBREGEN : 1; /!< [31] USB voltage regulator enable /
mbed_official	324:406fd2029f23	146	} B;
mbed_official	324:406fd2029f23	147	} hw_sim_sopt1_t;
mbed_official	324:406fd2029f23	148
mbed_official	324:406fd2029f23	149	/*!
mbed_official	324:406fd2029f23	150	* @name Constants and macros for entire SIM_SOPT1 register
mbed_official	324:406fd2029f23	151	*/
mbed_official	324:406fd2029f23	152	/@{/
mbed_official	324:406fd2029f23	153	#define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	154
mbed_official	324:406fd2029f23	155	#define HW_SIM_SOPT1(x) ((__IO hw_sim_sopt1_t ) HW_SIM_SOPT1_ADDR(x))
mbed_official	324:406fd2029f23	156	#define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U)
mbed_official	324:406fd2029f23	157	#define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v))
mbed_official	324:406fd2029f23	158	#define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	159	#define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	160	#define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	161	/@}/
mbed_official	324:406fd2029f23	162
mbed_official	324:406fd2029f23	163	/*
mbed_official	324:406fd2029f23	164	* Constants & macros for individual SIM_SOPT1 bitfields
mbed_official	324:406fd2029f23	165	*/
mbed_official	324:406fd2029f23	166
mbed_official	324:406fd2029f23	167	/*!
mbed_official	324:406fd2029f23	168	* @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
mbed_official	324:406fd2029f23	169	*
mbed_official	324:406fd2029f23	170	* This field specifies the amount of system RAM available on the device.
mbed_official	324:406fd2029f23	171	*
mbed_official	324:406fd2029f23	172	* Values:
mbed_official	324:406fd2029f23	173	* - 0001 - 8 KB
mbed_official	324:406fd2029f23	174	* - 0011 - 16 KB
mbed_official	324:406fd2029f23	175	* - 0100 - 24 KB
mbed_official	324:406fd2029f23	176	* - 0101 - 32 KB
mbed_official	324:406fd2029f23	177	* - 0110 - 48 KB
mbed_official	324:406fd2029f23	178	* - 0111 - 64 KB
mbed_official	324:406fd2029f23	179	* - 1000 - 96 KB
mbed_official	324:406fd2029f23	180	* - 1001 - 128 KB
mbed_official	324:406fd2029f23	181	* - 1011 - 256 KB
mbed_official	324:406fd2029f23	182	*/
mbed_official	324:406fd2029f23	183	/@{/
mbed_official	324:406fd2029f23	184	#define BP_SIM_SOPT1_RAMSIZE (12U) /!< Bit position for SIM_SOPT1_RAMSIZE. /
mbed_official	324:406fd2029f23	185	#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /!< Bit mask for SIM_SOPT1_RAMSIZE. /
mbed_official	324:406fd2029f23	186	#define BS_SIM_SOPT1_RAMSIZE (4U) /!< Bit field size in bits for SIM_SOPT1_RAMSIZE. /
mbed_official	324:406fd2029f23	187
mbed_official	324:406fd2029f23	188	/! @brief Read current value of the SIM_SOPT1_RAMSIZE field. /
mbed_official	324:406fd2029f23	189	#define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE)
mbed_official	324:406fd2029f23	190	/@}/
mbed_official	324:406fd2029f23	191
mbed_official	324:406fd2029f23	192	/*!
mbed_official	324:406fd2029f23	193	* @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
mbed_official	324:406fd2029f23	194	*
mbed_official	324:406fd2029f23	195	* Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
mbed_official	324:406fd2029f23	196	* only on POR/LVD.
mbed_official	324:406fd2029f23	197	*
mbed_official	324:406fd2029f23	198	* Values:
mbed_official	324:406fd2029f23	199	* - 00 - System oscillator (OSC32KCLK)
mbed_official	324:406fd2029f23	200	* - 01 - Reserved
mbed_official	324:406fd2029f23	201	* - 10 - RTC 32.768kHz oscillator
mbed_official	324:406fd2029f23	202	* - 11 - LPO 1 kHz
mbed_official	324:406fd2029f23	203	*/
mbed_official	324:406fd2029f23	204	/@{/
mbed_official	324:406fd2029f23	205	#define BP_SIM_SOPT1_OSC32KSEL (18U) /!< Bit position for SIM_SOPT1_OSC32KSEL. /
mbed_official	324:406fd2029f23	206	#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /!< Bit mask for SIM_SOPT1_OSC32KSEL. /
mbed_official	324:406fd2029f23	207	#define BS_SIM_SOPT1_OSC32KSEL (2U) /!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. /
mbed_official	324:406fd2029f23	208
mbed_official	324:406fd2029f23	209	/! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. /
mbed_official	324:406fd2029f23	210	#define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL)
mbed_official	324:406fd2029f23	211
mbed_official	324:406fd2029f23	212	/! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. /
mbed_official	324:406fd2029f23	213	#define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL)
mbed_official	324:406fd2029f23	214
mbed_official	324:406fd2029f23	215	/! @brief Set the OSC32KSEL field to a new value. /
mbed_official	324:406fd2029f23	216	#define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) \| BF_SIM_SOPT1_OSC32KSEL(v)))
mbed_official	324:406fd2029f23	217	/@}/
mbed_official	324:406fd2029f23	218
mbed_official	324:406fd2029f23	219	/*!
mbed_official	324:406fd2029f23	220	* @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
mbed_official	324:406fd2029f23	221	*
mbed_official	324:406fd2029f23	222	* Controls whether the USB voltage regulator is placed in standby mode during
mbed_official	324:406fd2029f23	223	* VLPR and VLPW modes.
mbed_official	324:406fd2029f23	224	*
mbed_official	324:406fd2029f23	225	* Values:
mbed_official	324:406fd2029f23	226	* - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
mbed_official	324:406fd2029f23	227	* - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
mbed_official	324:406fd2029f23	228	*/
mbed_official	324:406fd2029f23	229	/@{/
mbed_official	324:406fd2029f23	230	#define BP_SIM_SOPT1_USBVSTBY (29U) /!< Bit position for SIM_SOPT1_USBVSTBY. /
mbed_official	324:406fd2029f23	231	#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /!< Bit mask for SIM_SOPT1_USBVSTBY. /
mbed_official	324:406fd2029f23	232	#define BS_SIM_SOPT1_USBVSTBY (1U) /!< Bit field size in bits for SIM_SOPT1_USBVSTBY. /
mbed_official	324:406fd2029f23	233
mbed_official	324:406fd2029f23	234	/! @brief Read current value of the SIM_SOPT1_USBVSTBY field. /
mbed_official	324:406fd2029f23	235	#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))
mbed_official	324:406fd2029f23	236
mbed_official	324:406fd2029f23	237	/! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. /
mbed_official	324:406fd2029f23	238	#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY)
mbed_official	324:406fd2029f23	239
mbed_official	324:406fd2029f23	240	/! @brief Set the USBVSTBY field to a new value. /
mbed_official	324:406fd2029f23	241	#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v))
mbed_official	324:406fd2029f23	242	/@}/
mbed_official	324:406fd2029f23	243
mbed_official	324:406fd2029f23	244	/*!
mbed_official	324:406fd2029f23	245	* @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
mbed_official	324:406fd2029f23	246	*
mbed_official	324:406fd2029f23	247	* Controls whether the USB voltage regulator is placed in standby mode during
mbed_official	324:406fd2029f23	248	* Stop, VLPS, LLS and VLLS modes.
mbed_official	324:406fd2029f23	249	*
mbed_official	324:406fd2029f23	250	* Values:
mbed_official	324:406fd2029f23	251	* - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
mbed_official	324:406fd2029f23	252	* modes.
mbed_official	324:406fd2029f23	253	* - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
mbed_official	324:406fd2029f23	254	*/
mbed_official	324:406fd2029f23	255	/@{/
mbed_official	324:406fd2029f23	256	#define BP_SIM_SOPT1_USBSSTBY (30U) /!< Bit position for SIM_SOPT1_USBSSTBY. /
mbed_official	324:406fd2029f23	257	#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /!< Bit mask for SIM_SOPT1_USBSSTBY. /
mbed_official	324:406fd2029f23	258	#define BS_SIM_SOPT1_USBSSTBY (1U) /!< Bit field size in bits for SIM_SOPT1_USBSSTBY. /
mbed_official	324:406fd2029f23	259
mbed_official	324:406fd2029f23	260	/! @brief Read current value of the SIM_SOPT1_USBSSTBY field. /
mbed_official	324:406fd2029f23	261	#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))
mbed_official	324:406fd2029f23	262
mbed_official	324:406fd2029f23	263	/! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. /
mbed_official	324:406fd2029f23	264	#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY)
mbed_official	324:406fd2029f23	265
mbed_official	324:406fd2029f23	266	/! @brief Set the USBSSTBY field to a new value. /
mbed_official	324:406fd2029f23	267	#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v))
mbed_official	324:406fd2029f23	268	/@}/
mbed_official	324:406fd2029f23	269
mbed_official	324:406fd2029f23	270	/*!
mbed_official	324:406fd2029f23	271	* @name Register SIM_SOPT1, field USBREGEN[31] (RW)
mbed_official	324:406fd2029f23	272	*
mbed_official	324:406fd2029f23	273	* Controls whether the USB voltage regulator is enabled.
mbed_official	324:406fd2029f23	274	*
mbed_official	324:406fd2029f23	275	* Values:
mbed_official	324:406fd2029f23	276	* - 0 - USB voltage regulator is disabled.
mbed_official	324:406fd2029f23	277	* - 1 - USB voltage regulator is enabled.
mbed_official	324:406fd2029f23	278	*/
mbed_official	324:406fd2029f23	279	/@{/
mbed_official	324:406fd2029f23	280	#define BP_SIM_SOPT1_USBREGEN (31U) /!< Bit position for SIM_SOPT1_USBREGEN. /
mbed_official	324:406fd2029f23	281	#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /!< Bit mask for SIM_SOPT1_USBREGEN. /
mbed_official	324:406fd2029f23	282	#define BS_SIM_SOPT1_USBREGEN (1U) /!< Bit field size in bits for SIM_SOPT1_USBREGEN. /
mbed_official	324:406fd2029f23	283
mbed_official	324:406fd2029f23	284	/! @brief Read current value of the SIM_SOPT1_USBREGEN field. /
mbed_official	324:406fd2029f23	285	#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))
mbed_official	324:406fd2029f23	286
mbed_official	324:406fd2029f23	287	/! @brief Format value for bitfield SIM_SOPT1_USBREGEN. /
mbed_official	324:406fd2029f23	288	#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN)
mbed_official	324:406fd2029f23	289
mbed_official	324:406fd2029f23	290	/! @brief Set the USBREGEN field to a new value. /
mbed_official	324:406fd2029f23	291	#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v))
mbed_official	324:406fd2029f23	292	/@}/
mbed_official	324:406fd2029f23	293
mbed_official	324:406fd2029f23	294	/*******************************************************************************
mbed_official	324:406fd2029f23	295	* HW_SIM_SOPT1CFG - SOPT1 Configuration Register
mbed_official	324:406fd2029f23	296	******************************************************************************/
mbed_official	324:406fd2029f23	297
mbed_official	324:406fd2029f23	298	/*!
mbed_official	324:406fd2029f23	299	* @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
mbed_official	324:406fd2029f23	300	*
mbed_official	324:406fd2029f23	301	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	302	*
mbed_official	324:406fd2029f23	303	* The SOPT1CFG register is reset on System Reset not VLLS.
mbed_official	324:406fd2029f23	304	*/
mbed_official	324:406fd2029f23	305	typedef union _hw_sim_sopt1cfg
mbed_official	324:406fd2029f23	306	{
mbed_official	324:406fd2029f23	307	uint32_t U;
mbed_official	324:406fd2029f23	308	struct _hw_sim_sopt1cfg_bitfields
mbed_official	324:406fd2029f23	309	{
mbed_official	324:406fd2029f23	310	uint32_t RESERVED0 : 24; /!< [23:0] /
mbed_official	324:406fd2029f23	311	uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write
mbed_official	324:406fd2029f23	312	* enable */
mbed_official	324:406fd2029f23	313	uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write
mbed_official	324:406fd2029f23	314	* enable */
mbed_official	324:406fd2029f23	315	uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby
mbed_official	324:406fd2029f23	316	* write enable */
mbed_official	324:406fd2029f23	317	uint32_t RESERVED1 : 5; /!< [31:27] /
mbed_official	324:406fd2029f23	318	} B;
mbed_official	324:406fd2029f23	319	} hw_sim_sopt1cfg_t;
mbed_official	324:406fd2029f23	320
mbed_official	324:406fd2029f23	321	/*!
mbed_official	324:406fd2029f23	322	* @name Constants and macros for entire SIM_SOPT1CFG register
mbed_official	324:406fd2029f23	323	*/
mbed_official	324:406fd2029f23	324	/@{/
mbed_official	324:406fd2029f23	325	#define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	326
mbed_official	324:406fd2029f23	327	#define HW_SIM_SOPT1CFG(x) ((__IO hw_sim_sopt1cfg_t ) HW_SIM_SOPT1CFG_ADDR(x))
mbed_official	324:406fd2029f23	328	#define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U)
mbed_official	324:406fd2029f23	329	#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v))
mbed_official	324:406fd2029f23	330	#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) \| (v)))
mbed_official	324:406fd2029f23	331	#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	332	#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	333	/@}/
mbed_official	324:406fd2029f23	334
mbed_official	324:406fd2029f23	335	/*
mbed_official	324:406fd2029f23	336	* Constants & macros for individual SIM_SOPT1CFG bitfields
mbed_official	324:406fd2029f23	337	*/
mbed_official	324:406fd2029f23	338
mbed_official	324:406fd2029f23	339	/*!
mbed_official	324:406fd2029f23	340	* @name Register SIM_SOPT1CFG, field URWE[24] (RW)
mbed_official	324:406fd2029f23	341	*
mbed_official	324:406fd2029f23	342	* Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
mbed_official	324:406fd2029f23	343	* register bit clears after a write to USBREGEN.
mbed_official	324:406fd2029f23	344	*
mbed_official	324:406fd2029f23	345	* Values:
mbed_official	324:406fd2029f23	346	* - 0 - SOPT1 USBREGEN cannot be written.
mbed_official	324:406fd2029f23	347	* - 1 - SOPT1 USBREGEN can be written.
mbed_official	324:406fd2029f23	348	*/
mbed_official	324:406fd2029f23	349	/@{/
mbed_official	324:406fd2029f23	350	#define BP_SIM_SOPT1CFG_URWE (24U) /!< Bit position for SIM_SOPT1CFG_URWE. /
mbed_official	324:406fd2029f23	351	#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /!< Bit mask for SIM_SOPT1CFG_URWE. /
mbed_official	324:406fd2029f23	352	#define BS_SIM_SOPT1CFG_URWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_URWE. /
mbed_official	324:406fd2029f23	353
mbed_official	324:406fd2029f23	354	/! @brief Read current value of the SIM_SOPT1CFG_URWE field. /
mbed_official	324:406fd2029f23	355	#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))
mbed_official	324:406fd2029f23	356
mbed_official	324:406fd2029f23	357	/! @brief Format value for bitfield SIM_SOPT1CFG_URWE. /
mbed_official	324:406fd2029f23	358	#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE)
mbed_official	324:406fd2029f23	359
mbed_official	324:406fd2029f23	360	/! @brief Set the URWE field to a new value. /
mbed_official	324:406fd2029f23	361	#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v))
mbed_official	324:406fd2029f23	362	/@}/
mbed_official	324:406fd2029f23	363
mbed_official	324:406fd2029f23	364	/*!
mbed_official	324:406fd2029f23	365	* @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
mbed_official	324:406fd2029f23	366	*
mbed_official	324:406fd2029f23	367	* Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
mbed_official	324:406fd2029f23	368	* This register bit clears after a write to USBVSTBY.
mbed_official	324:406fd2029f23	369	*
mbed_official	324:406fd2029f23	370	* Values:
mbed_official	324:406fd2029f23	371	* - 0 - SOPT1 USBVSTBY cannot be written.
mbed_official	324:406fd2029f23	372	* - 1 - SOPT1 USBVSTBY can be written.
mbed_official	324:406fd2029f23	373	*/
mbed_official	324:406fd2029f23	374	/@{/
mbed_official	324:406fd2029f23	375	#define BP_SIM_SOPT1CFG_UVSWE (25U) /!< Bit position for SIM_SOPT1CFG_UVSWE. /
mbed_official	324:406fd2029f23	376	#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /!< Bit mask for SIM_SOPT1CFG_UVSWE. /
mbed_official	324:406fd2029f23	377	#define BS_SIM_SOPT1CFG_UVSWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. /
mbed_official	324:406fd2029f23	378
mbed_official	324:406fd2029f23	379	/! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. /
mbed_official	324:406fd2029f23	380	#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))
mbed_official	324:406fd2029f23	381
mbed_official	324:406fd2029f23	382	/! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. /
mbed_official	324:406fd2029f23	383	#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE)
mbed_official	324:406fd2029f23	384
mbed_official	324:406fd2029f23	385	/! @brief Set the UVSWE field to a new value. /
mbed_official	324:406fd2029f23	386	#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v))
mbed_official	324:406fd2029f23	387	/@}/
mbed_official	324:406fd2029f23	388
mbed_official	324:406fd2029f23	389	/*!
mbed_official	324:406fd2029f23	390	* @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
mbed_official	324:406fd2029f23	391	*
mbed_official	324:406fd2029f23	392	* Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
mbed_official	324:406fd2029f23	393	* This register bit clears after a write to USBSSTBY.
mbed_official	324:406fd2029f23	394	*
mbed_official	324:406fd2029f23	395	* Values:
mbed_official	324:406fd2029f23	396	* - 0 - SOPT1 USBSSTBY cannot be written.
mbed_official	324:406fd2029f23	397	* - 1 - SOPT1 USBSSTBY can be written.
mbed_official	324:406fd2029f23	398	*/
mbed_official	324:406fd2029f23	399	/@{/
mbed_official	324:406fd2029f23	400	#define BP_SIM_SOPT1CFG_USSWE (26U) /!< Bit position for SIM_SOPT1CFG_USSWE. /
mbed_official	324:406fd2029f23	401	#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /!< Bit mask for SIM_SOPT1CFG_USSWE. /
mbed_official	324:406fd2029f23	402	#define BS_SIM_SOPT1CFG_USSWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_USSWE. /
mbed_official	324:406fd2029f23	403
mbed_official	324:406fd2029f23	404	/! @brief Read current value of the SIM_SOPT1CFG_USSWE field. /
mbed_official	324:406fd2029f23	405	#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))
mbed_official	324:406fd2029f23	406
mbed_official	324:406fd2029f23	407	/! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. /
mbed_official	324:406fd2029f23	408	#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE)
mbed_official	324:406fd2029f23	409
mbed_official	324:406fd2029f23	410	/! @brief Set the USSWE field to a new value. /
mbed_official	324:406fd2029f23	411	#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v))
mbed_official	324:406fd2029f23	412	/@}/
mbed_official	324:406fd2029f23	413
mbed_official	324:406fd2029f23	414	/*******************************************************************************
mbed_official	324:406fd2029f23	415	* HW_SIM_SOPT2 - System Options Register 2
mbed_official	324:406fd2029f23	416	******************************************************************************/
mbed_official	324:406fd2029f23	417
mbed_official	324:406fd2029f23	418	/*!
mbed_official	324:406fd2029f23	419	* @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
mbed_official	324:406fd2029f23	420	*
mbed_official	324:406fd2029f23	421	* Reset value: 0x00001000U
mbed_official	324:406fd2029f23	422	*
mbed_official	324:406fd2029f23	423	* SOPT2 contains the controls for selecting many of the module clock source
mbed_official	324:406fd2029f23	424	* options on this device. See the Clock Distribution chapter for more information
mbed_official	324:406fd2029f23	425	* including clocking diagrams and definitions of device clocks.
mbed_official	324:406fd2029f23	426	*/
mbed_official	324:406fd2029f23	427	typedef union _hw_sim_sopt2
mbed_official	324:406fd2029f23	428	{
mbed_official	324:406fd2029f23	429	uint32_t U;
mbed_official	324:406fd2029f23	430	struct _hw_sim_sopt2_bitfields
mbed_official	324:406fd2029f23	431	{
mbed_official	324:406fd2029f23	432	uint32_t RESERVED0 : 4; /!< [3:0] /
mbed_official	324:406fd2029f23	433	uint32_t RTCCLKOUTSEL : 1; /!< [4] RTC clock out select /
mbed_official	324:406fd2029f23	434	uint32_t CLKOUTSEL : 3; /!< [7:5] CLKOUT select /
mbed_official	324:406fd2029f23	435	uint32_t FBSL : 2; /!< [9:8] FlexBus security level /
mbed_official	324:406fd2029f23	436	uint32_t RESERVED1 : 1; /!< [10] /
mbed_official	324:406fd2029f23	437	uint32_t PTD7PAD : 1; /!< [11] PTD7 pad drive strength /
mbed_official	324:406fd2029f23	438	uint32_t TRACECLKSEL : 1; /!< [12] Debug trace clock select /
mbed_official	324:406fd2029f23	439	uint32_t RESERVED2 : 3; /!< [15:13] /
mbed_official	324:406fd2029f23	440	uint32_t PLLFLLSEL : 2; /!< [17:16] PLL/FLL clock select /
mbed_official	324:406fd2029f23	441	uint32_t USBSRC : 1; /!< [18] USB clock source select /
mbed_official	324:406fd2029f23	442	uint32_t RMIISRC : 1; /!< [19] RMII clock source select /
mbed_official	324:406fd2029f23	443	uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source
mbed_official	324:406fd2029f23	444	* select */
mbed_official	324:406fd2029f23	445	uint32_t RESERVED3 : 6; /!< [27:22] /
mbed_official	324:406fd2029f23	446	uint32_t SDHCSRC : 2; /!< [29:28] SDHC clock source select /
mbed_official	324:406fd2029f23	447	uint32_t RESERVED4 : 2; /!< [31:30] /
mbed_official	324:406fd2029f23	448	} B;
mbed_official	324:406fd2029f23	449	} hw_sim_sopt2_t;
mbed_official	324:406fd2029f23	450
mbed_official	324:406fd2029f23	451	/*!
mbed_official	324:406fd2029f23	452	* @name Constants and macros for entire SIM_SOPT2 register
mbed_official	324:406fd2029f23	453	*/
mbed_official	324:406fd2029f23	454	/@{/
mbed_official	324:406fd2029f23	455	#define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U)
mbed_official	324:406fd2029f23	456
mbed_official	324:406fd2029f23	457	#define HW_SIM_SOPT2(x) ((__IO hw_sim_sopt2_t ) HW_SIM_SOPT2_ADDR(x))
mbed_official	324:406fd2029f23	458	#define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U)
mbed_official	324:406fd2029f23	459	#define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v))
mbed_official	324:406fd2029f23	460	#define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	461	#define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	462	#define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	463	/@}/
mbed_official	324:406fd2029f23	464
mbed_official	324:406fd2029f23	465	/*
mbed_official	324:406fd2029f23	466	* Constants & macros for individual SIM_SOPT2 bitfields
mbed_official	324:406fd2029f23	467	*/
mbed_official	324:406fd2029f23	468
mbed_official	324:406fd2029f23	469	/*!
mbed_official	324:406fd2029f23	470	* @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
mbed_official	324:406fd2029f23	471	*
mbed_official	324:406fd2029f23	472	* Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
mbed_official	324:406fd2029f23	473	* RTC_CLKOUT pin.
mbed_official	324:406fd2029f23	474	*
mbed_official	324:406fd2029f23	475	* Values:
mbed_official	324:406fd2029f23	476	* - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
mbed_official	324:406fd2029f23	477	* - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
mbed_official	324:406fd2029f23	478	*/
mbed_official	324:406fd2029f23	479	/@{/
mbed_official	324:406fd2029f23	480	#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. /
mbed_official	324:406fd2029f23	481	#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. /
mbed_official	324:406fd2029f23	482	#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. /
mbed_official	324:406fd2029f23	483
mbed_official	324:406fd2029f23	484	/! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. /
mbed_official	324:406fd2029f23	485	#define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))
mbed_official	324:406fd2029f23	486
mbed_official	324:406fd2029f23	487	/! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. /
mbed_official	324:406fd2029f23	488	#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL)
mbed_official	324:406fd2029f23	489
mbed_official	324:406fd2029f23	490	/! @brief Set the RTCCLKOUTSEL field to a new value. /
mbed_official	324:406fd2029f23	491	#define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
mbed_official	324:406fd2029f23	492	/@}/
mbed_official	324:406fd2029f23	493
mbed_official	324:406fd2029f23	494	/*!
mbed_official	324:406fd2029f23	495	* @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
mbed_official	324:406fd2029f23	496	*
mbed_official	324:406fd2029f23	497	* Selects the clock to output on the CLKOUT pin.
mbed_official	324:406fd2029f23	498	*
mbed_official	324:406fd2029f23	499	* Values:
mbed_official	324:406fd2029f23	500	* - 000 - FlexBus CLKOUT
mbed_official	324:406fd2029f23	501	* - 001 - Reserved
mbed_official	324:406fd2029f23	502	* - 010 - Flash clock
mbed_official	324:406fd2029f23	503	* - 011 - LPO clock (1 kHz)
mbed_official	324:406fd2029f23	504	* - 100 - MCGIRCLK
mbed_official	324:406fd2029f23	505	* - 101 - RTC 32.768kHz clock
mbed_official	324:406fd2029f23	506	* - 110 - OSCERCLK0
mbed_official	324:406fd2029f23	507	* - 111 - IRC 48 MHz clock
mbed_official	324:406fd2029f23	508	*/
mbed_official	324:406fd2029f23	509	/@{/
mbed_official	324:406fd2029f23	510	#define BP_SIM_SOPT2_CLKOUTSEL (5U) /!< Bit position for SIM_SOPT2_CLKOUTSEL. /
mbed_official	324:406fd2029f23	511	#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /!< Bit mask for SIM_SOPT2_CLKOUTSEL. /
mbed_official	324:406fd2029f23	512	#define BS_SIM_SOPT2_CLKOUTSEL (3U) /!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. /
mbed_official	324:406fd2029f23	513
mbed_official	324:406fd2029f23	514	/! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. /
mbed_official	324:406fd2029f23	515	#define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL)
mbed_official	324:406fd2029f23	516
mbed_official	324:406fd2029f23	517	/! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. /
mbed_official	324:406fd2029f23	518	#define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL)
mbed_official	324:406fd2029f23	519
mbed_official	324:406fd2029f23	520	/! @brief Set the CLKOUTSEL field to a new value. /
mbed_official	324:406fd2029f23	521	#define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) \| BF_SIM_SOPT2_CLKOUTSEL(v)))
mbed_official	324:406fd2029f23	522	/@}/
mbed_official	324:406fd2029f23	523
mbed_official	324:406fd2029f23	524	/*!
mbed_official	324:406fd2029f23	525	* @name Register SIM_SOPT2, field FBSL[9:8] (RW)
mbed_official	324:406fd2029f23	526	*
mbed_official	324:406fd2029f23	527	* If flash security is enabled, then this field affects what CPU operations can
mbed_official	324:406fd2029f23	528	* access off-chip via the FlexBus interface. This field has no effect if flash
mbed_official	324:406fd2029f23	529	* security is not enabled.
mbed_official	324:406fd2029f23	530	*
mbed_official	324:406fd2029f23	531	* Values:
mbed_official	324:406fd2029f23	532	* - 00 - All off-chip accesses (instruction and data) via the FlexBus are
mbed_official	324:406fd2029f23	533	* disallowed.
mbed_official	324:406fd2029f23	534	* - 01 - All off-chip accesses (instruction and data) via the FlexBus are
mbed_official	324:406fd2029f23	535	* disallowed.
mbed_official	324:406fd2029f23	536	* - 10 - Off-chip instruction accesses are disallowed. Data accesses are
mbed_official	324:406fd2029f23	537	* allowed.
mbed_official	324:406fd2029f23	538	* - 11 - Off-chip instruction accesses and data accesses are allowed.
mbed_official	324:406fd2029f23	539	*/
mbed_official	324:406fd2029f23	540	/@{/
mbed_official	324:406fd2029f23	541	#define BP_SIM_SOPT2_FBSL (8U) /!< Bit position for SIM_SOPT2_FBSL. /
mbed_official	324:406fd2029f23	542	#define BM_SIM_SOPT2_FBSL (0x00000300U) /!< Bit mask for SIM_SOPT2_FBSL. /
mbed_official	324:406fd2029f23	543	#define BS_SIM_SOPT2_FBSL (2U) /!< Bit field size in bits for SIM_SOPT2_FBSL. /
mbed_official	324:406fd2029f23	544
mbed_official	324:406fd2029f23	545	/! @brief Read current value of the SIM_SOPT2_FBSL field. /
mbed_official	324:406fd2029f23	546	#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL)
mbed_official	324:406fd2029f23	547
mbed_official	324:406fd2029f23	548	/! @brief Format value for bitfield SIM_SOPT2_FBSL. /
mbed_official	324:406fd2029f23	549	#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL)
mbed_official	324:406fd2029f23	550
mbed_official	324:406fd2029f23	551	/! @brief Set the FBSL field to a new value. /
mbed_official	324:406fd2029f23	552	#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) \| BF_SIM_SOPT2_FBSL(v)))
mbed_official	324:406fd2029f23	553	/@}/
mbed_official	324:406fd2029f23	554
mbed_official	324:406fd2029f23	555	/*!
mbed_official	324:406fd2029f23	556	* @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
mbed_official	324:406fd2029f23	557	*
mbed_official	324:406fd2029f23	558	* Controls the output drive strength of the PTD7 pin by selecting either one or
mbed_official	324:406fd2029f23	559	* two pads to drive it.
mbed_official	324:406fd2029f23	560	*
mbed_official	324:406fd2029f23	561	* Values:
mbed_official	324:406fd2029f23	562	* - 0 - Single-pad drive strength for PTD7.
mbed_official	324:406fd2029f23	563	* - 1 - Double pad drive strength for PTD7.
mbed_official	324:406fd2029f23	564	*/
mbed_official	324:406fd2029f23	565	/@{/
mbed_official	324:406fd2029f23	566	#define BP_SIM_SOPT2_PTD7PAD (11U) /!< Bit position for SIM_SOPT2_PTD7PAD. /
mbed_official	324:406fd2029f23	567	#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /!< Bit mask for SIM_SOPT2_PTD7PAD. /
mbed_official	324:406fd2029f23	568	#define BS_SIM_SOPT2_PTD7PAD (1U) /!< Bit field size in bits for SIM_SOPT2_PTD7PAD. /
mbed_official	324:406fd2029f23	569
mbed_official	324:406fd2029f23	570	/! @brief Read current value of the SIM_SOPT2_PTD7PAD field. /
mbed_official	324:406fd2029f23	571	#define BR_SIM_SOPT2_PTD7PAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD))
mbed_official	324:406fd2029f23	572
mbed_official	324:406fd2029f23	573	/! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. /
mbed_official	324:406fd2029f23	574	#define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD)
mbed_official	324:406fd2029f23	575
mbed_official	324:406fd2029f23	576	/! @brief Set the PTD7PAD field to a new value. /
mbed_official	324:406fd2029f23	577	#define BW_SIM_SOPT2_PTD7PAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD) = (v))
mbed_official	324:406fd2029f23	578	/@}/
mbed_official	324:406fd2029f23	579
mbed_official	324:406fd2029f23	580	/*!
mbed_official	324:406fd2029f23	581	* @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
mbed_official	324:406fd2029f23	582	*
mbed_official	324:406fd2029f23	583	* Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
mbed_official	324:406fd2029f23	584	* clock source.
mbed_official	324:406fd2029f23	585	*
mbed_official	324:406fd2029f23	586	* Values:
mbed_official	324:406fd2029f23	587	* - 0 - MCGOUTCLK
mbed_official	324:406fd2029f23	588	* - 1 - Core/system clock
mbed_official	324:406fd2029f23	589	*/
mbed_official	324:406fd2029f23	590	/@{/
mbed_official	324:406fd2029f23	591	#define BP_SIM_SOPT2_TRACECLKSEL (12U) /!< Bit position for SIM_SOPT2_TRACECLKSEL. /
mbed_official	324:406fd2029f23	592	#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /!< Bit mask for SIM_SOPT2_TRACECLKSEL. /
mbed_official	324:406fd2029f23	593	#define BS_SIM_SOPT2_TRACECLKSEL (1U) /!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. /
mbed_official	324:406fd2029f23	594
mbed_official	324:406fd2029f23	595	/! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. /
mbed_official	324:406fd2029f23	596	#define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))
mbed_official	324:406fd2029f23	597
mbed_official	324:406fd2029f23	598	/! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. /
mbed_official	324:406fd2029f23	599	#define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL)
mbed_official	324:406fd2029f23	600
mbed_official	324:406fd2029f23	601	/! @brief Set the TRACECLKSEL field to a new value. /
mbed_official	324:406fd2029f23	602	#define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v))
mbed_official	324:406fd2029f23	603	/@}/
mbed_official	324:406fd2029f23	604
mbed_official	324:406fd2029f23	605	/*!
mbed_official	324:406fd2029f23	606	* @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
mbed_official	324:406fd2029f23	607	*
mbed_official	324:406fd2029f23	608	* Selects the high frequency clock for various peripheral clocking options.
mbed_official	324:406fd2029f23	609	*
mbed_official	324:406fd2029f23	610	* Values:
mbed_official	324:406fd2029f23	611	* - 00 - MCGFLLCLK clock
mbed_official	324:406fd2029f23	612	* - 01 - MCGPLLCLK clock
mbed_official	324:406fd2029f23	613	* - 10 - Reserved
mbed_official	324:406fd2029f23	614	* - 11 - IRC48 MHz clock
mbed_official	324:406fd2029f23	615	*/
mbed_official	324:406fd2029f23	616	/@{/
mbed_official	324:406fd2029f23	617	#define BP_SIM_SOPT2_PLLFLLSEL (16U) /!< Bit position for SIM_SOPT2_PLLFLLSEL. /
mbed_official	324:406fd2029f23	618	#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /!< Bit mask for SIM_SOPT2_PLLFLLSEL. /
mbed_official	324:406fd2029f23	619	#define BS_SIM_SOPT2_PLLFLLSEL (2U) /!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. /
mbed_official	324:406fd2029f23	620
mbed_official	324:406fd2029f23	621	/! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. /
mbed_official	324:406fd2029f23	622	#define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL)
mbed_official	324:406fd2029f23	623
mbed_official	324:406fd2029f23	624	/! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. /
mbed_official	324:406fd2029f23	625	#define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL)
mbed_official	324:406fd2029f23	626
mbed_official	324:406fd2029f23	627	/! @brief Set the PLLFLLSEL field to a new value. /
mbed_official	324:406fd2029f23	628	#define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) \| BF_SIM_SOPT2_PLLFLLSEL(v)))
mbed_official	324:406fd2029f23	629	/@}/
mbed_official	324:406fd2029f23	630
mbed_official	324:406fd2029f23	631	/*!
mbed_official	324:406fd2029f23	632	* @name Register SIM_SOPT2, field USBSRC[18] (RW)
mbed_official	324:406fd2029f23	633	*
mbed_official	324:406fd2029f23	634	* Selects the clock source for the USB 48 MHz clock.
mbed_official	324:406fd2029f23	635	*
mbed_official	324:406fd2029f23	636	* Values:
mbed_official	324:406fd2029f23	637	* - 0 - External bypass clock (USB_CLKIN).
mbed_official	324:406fd2029f23	638	* - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
mbed_official	324:406fd2029f23	639	* SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
mbed_official	324:406fd2029f23	640	* SIM_CLKDIV2[USBFRAC, USBDIV].
mbed_official	324:406fd2029f23	641	*/
mbed_official	324:406fd2029f23	642	/@{/
mbed_official	324:406fd2029f23	643	#define BP_SIM_SOPT2_USBSRC (18U) /!< Bit position for SIM_SOPT2_USBSRC. /
mbed_official	324:406fd2029f23	644	#define BM_SIM_SOPT2_USBSRC (0x00040000U) /!< Bit mask for SIM_SOPT2_USBSRC. /
mbed_official	324:406fd2029f23	645	#define BS_SIM_SOPT2_USBSRC (1U) /!< Bit field size in bits for SIM_SOPT2_USBSRC. /
mbed_official	324:406fd2029f23	646
mbed_official	324:406fd2029f23	647	/! @brief Read current value of the SIM_SOPT2_USBSRC field. /
mbed_official	324:406fd2029f23	648	#define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC))
mbed_official	324:406fd2029f23	649
mbed_official	324:406fd2029f23	650	/! @brief Format value for bitfield SIM_SOPT2_USBSRC. /
mbed_official	324:406fd2029f23	651	#define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC)
mbed_official	324:406fd2029f23	652
mbed_official	324:406fd2029f23	653	/! @brief Set the USBSRC field to a new value. /
mbed_official	324:406fd2029f23	654	#define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v))
mbed_official	324:406fd2029f23	655	/@}/
mbed_official	324:406fd2029f23	656
mbed_official	324:406fd2029f23	657	/*!
mbed_official	324:406fd2029f23	658	* @name Register SIM_SOPT2, field RMIISRC[19] (RW)
mbed_official	324:406fd2029f23	659	*
mbed_official	324:406fd2029f23	660	* Selects the clock source for the Ethernet RMII interface
mbed_official	324:406fd2029f23	661	*
mbed_official	324:406fd2029f23	662	* Values:
mbed_official	324:406fd2029f23	663	* - 0 - EXTAL clock
mbed_official	324:406fd2029f23	664	* - 1 - External bypass clock (ENET_1588_CLKIN).
mbed_official	324:406fd2029f23	665	*/
mbed_official	324:406fd2029f23	666	/@{/
mbed_official	324:406fd2029f23	667	#define BP_SIM_SOPT2_RMIISRC (19U) /!< Bit position for SIM_SOPT2_RMIISRC. /
mbed_official	324:406fd2029f23	668	#define BM_SIM_SOPT2_RMIISRC (0x00080000U) /!< Bit mask for SIM_SOPT2_RMIISRC. /
mbed_official	324:406fd2029f23	669	#define BS_SIM_SOPT2_RMIISRC (1U) /!< Bit field size in bits for SIM_SOPT2_RMIISRC. /
mbed_official	324:406fd2029f23	670
mbed_official	324:406fd2029f23	671	/! @brief Read current value of the SIM_SOPT2_RMIISRC field. /
mbed_official	324:406fd2029f23	672	#define BR_SIM_SOPT2_RMIISRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC))
mbed_official	324:406fd2029f23	673
mbed_official	324:406fd2029f23	674	/! @brief Format value for bitfield SIM_SOPT2_RMIISRC. /
mbed_official	324:406fd2029f23	675	#define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC)
mbed_official	324:406fd2029f23	676
mbed_official	324:406fd2029f23	677	/! @brief Set the RMIISRC field to a new value. /
mbed_official	324:406fd2029f23	678	#define BW_SIM_SOPT2_RMIISRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC) = (v))
mbed_official	324:406fd2029f23	679	/@}/
mbed_official	324:406fd2029f23	680
mbed_official	324:406fd2029f23	681	/*!
mbed_official	324:406fd2029f23	682	* @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
mbed_official	324:406fd2029f23	683	*
mbed_official	324:406fd2029f23	684	* Selects the clock source for the Ethernet timestamp clock.
mbed_official	324:406fd2029f23	685	*
mbed_official	324:406fd2029f23	686	* Values:
mbed_official	324:406fd2029f23	687	* - 00 - Core/system clock.
mbed_official	324:406fd2029f23	688	* - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
mbed_official	324:406fd2029f23	689	* SOPT2[PLLFLLSEL].
mbed_official	324:406fd2029f23	690	* - 10 - OSCERCLK clock
mbed_official	324:406fd2029f23	691	* - 11 - External bypass clock (ENET_1588_CLKIN).
mbed_official	324:406fd2029f23	692	*/
mbed_official	324:406fd2029f23	693	/@{/
mbed_official	324:406fd2029f23	694	#define BP_SIM_SOPT2_TIMESRC (20U) /!< Bit position for SIM_SOPT2_TIMESRC. /
mbed_official	324:406fd2029f23	695	#define BM_SIM_SOPT2_TIMESRC (0x00300000U) /!< Bit mask for SIM_SOPT2_TIMESRC. /
mbed_official	324:406fd2029f23	696	#define BS_SIM_SOPT2_TIMESRC (2U) /!< Bit field size in bits for SIM_SOPT2_TIMESRC. /
mbed_official	324:406fd2029f23	697
mbed_official	324:406fd2029f23	698	/! @brief Read current value of the SIM_SOPT2_TIMESRC field. /
mbed_official	324:406fd2029f23	699	#define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC)
mbed_official	324:406fd2029f23	700
mbed_official	324:406fd2029f23	701	/! @brief Format value for bitfield SIM_SOPT2_TIMESRC. /
mbed_official	324:406fd2029f23	702	#define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC)
mbed_official	324:406fd2029f23	703
mbed_official	324:406fd2029f23	704	/! @brief Set the TIMESRC field to a new value. /
mbed_official	324:406fd2029f23	705	#define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) \| BF_SIM_SOPT2_TIMESRC(v)))
mbed_official	324:406fd2029f23	706	/@}/
mbed_official	324:406fd2029f23	707
mbed_official	324:406fd2029f23	708	/*!
mbed_official	324:406fd2029f23	709	* @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
mbed_official	324:406fd2029f23	710	*
mbed_official	324:406fd2029f23	711	* Selects the clock source for the SDHC clock .
mbed_official	324:406fd2029f23	712	*
mbed_official	324:406fd2029f23	713	* Values:
mbed_official	324:406fd2029f23	714	* - 00 - Core/system clock.
mbed_official	324:406fd2029f23	715	* - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
mbed_official	324:406fd2029f23	716	* SOPT2[PLLFLLSEL].
mbed_official	324:406fd2029f23	717	* - 10 - OSCERCLK clock
mbed_official	324:406fd2029f23	718	* - 11 - External bypass clock (SDHC0_CLKIN)
mbed_official	324:406fd2029f23	719	*/
mbed_official	324:406fd2029f23	720	/@{/
mbed_official	324:406fd2029f23	721	#define BP_SIM_SOPT2_SDHCSRC (28U) /!< Bit position for SIM_SOPT2_SDHCSRC. /
mbed_official	324:406fd2029f23	722	#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /!< Bit mask for SIM_SOPT2_SDHCSRC. /
mbed_official	324:406fd2029f23	723	#define BS_SIM_SOPT2_SDHCSRC (2U) /!< Bit field size in bits for SIM_SOPT2_SDHCSRC. /
mbed_official	324:406fd2029f23	724
mbed_official	324:406fd2029f23	725	/! @brief Read current value of the SIM_SOPT2_SDHCSRC field. /
mbed_official	324:406fd2029f23	726	#define BR_SIM_SOPT2_SDHCSRC(x) (HW_SIM_SOPT2(x).B.SDHCSRC)
mbed_official	324:406fd2029f23	727
mbed_official	324:406fd2029f23	728	/! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. /
mbed_official	324:406fd2029f23	729	#define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC)
mbed_official	324:406fd2029f23	730
mbed_official	324:406fd2029f23	731	/! @brief Set the SDHCSRC field to a new value. /
mbed_official	324:406fd2029f23	732	#define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) \| BF_SIM_SOPT2_SDHCSRC(v)))
mbed_official	324:406fd2029f23	733	/@}/
mbed_official	324:406fd2029f23	734
mbed_official	324:406fd2029f23	735	/*******************************************************************************
mbed_official	324:406fd2029f23	736	* HW_SIM_SOPT4 - System Options Register 4
mbed_official	324:406fd2029f23	737	******************************************************************************/
mbed_official	324:406fd2029f23	738
mbed_official	324:406fd2029f23	739	/*!
mbed_official	324:406fd2029f23	740	* @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
mbed_official	324:406fd2029f23	741	*
mbed_official	324:406fd2029f23	742	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	743	*/
mbed_official	324:406fd2029f23	744	typedef union _hw_sim_sopt4
mbed_official	324:406fd2029f23	745	{
mbed_official	324:406fd2029f23	746	uint32_t U;
mbed_official	324:406fd2029f23	747	struct _hw_sim_sopt4_bitfields
mbed_official	324:406fd2029f23	748	{
mbed_official	324:406fd2029f23	749	uint32_t FTM0FLT0 : 1; /!< [0] FTM0 Fault 0 Select /
mbed_official	324:406fd2029f23	750	uint32_t FTM0FLT1 : 1; /!< [1] FTM0 Fault 1 Select /
mbed_official	324:406fd2029f23	751	uint32_t FTM0FLT2 : 1; /!< [2] FTM0 Fault 2 Select /
mbed_official	324:406fd2029f23	752	uint32_t RESERVED0 : 1; /!< [3] /
mbed_official	324:406fd2029f23	753	uint32_t FTM1FLT0 : 1; /!< [4] FTM1 Fault 0 Select /
mbed_official	324:406fd2029f23	754	uint32_t RESERVED1 : 3; /!< [7:5] /
mbed_official	324:406fd2029f23	755	uint32_t FTM2FLT0 : 1; /!< [8] FTM2 Fault 0 Select /
mbed_official	324:406fd2029f23	756	uint32_t RESERVED2 : 3; /!< [11:9] /
mbed_official	324:406fd2029f23	757	uint32_t FTM3FLT0 : 1; /!< [12] FTM3 Fault 0 Select /
mbed_official	324:406fd2029f23	758	uint32_t RESERVED3 : 5; /!< [17:13] /
mbed_official	324:406fd2029f23	759	uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture
mbed_official	324:406fd2029f23	760	* source select */
mbed_official	324:406fd2029f23	761	uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture
mbed_official	324:406fd2029f23	762	* source select */
mbed_official	324:406fd2029f23	763	uint32_t RESERVED4 : 2; /!< [23:22] /
mbed_official	324:406fd2029f23	764	uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin
mbed_official	324:406fd2029f23	765	* Select */
mbed_official	324:406fd2029f23	766	uint32_t FTM1CLKSEL : 1; /!< [25] FTM1 External Clock Pin Select /
mbed_official	324:406fd2029f23	767	uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin
mbed_official	324:406fd2029f23	768	* Select */
mbed_official	324:406fd2029f23	769	uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin
mbed_official	324:406fd2029f23	770	* Select */
mbed_official	324:406fd2029f23	771	uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0
mbed_official	324:406fd2029f23	772	* Source Select */
mbed_official	324:406fd2029f23	773	uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1
mbed_official	324:406fd2029f23	774	* Source Select */
mbed_official	324:406fd2029f23	775	uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0
mbed_official	324:406fd2029f23	776	* Source Select */
mbed_official	324:406fd2029f23	777	uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1
mbed_official	324:406fd2029f23	778	* Source Select */
mbed_official	324:406fd2029f23	779	} B;
mbed_official	324:406fd2029f23	780	} hw_sim_sopt4_t;
mbed_official	324:406fd2029f23	781
mbed_official	324:406fd2029f23	782	/*!
mbed_official	324:406fd2029f23	783	* @name Constants and macros for entire SIM_SOPT4 register
mbed_official	324:406fd2029f23	784	*/
mbed_official	324:406fd2029f23	785	/@{/
mbed_official	324:406fd2029f23	786	#define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU)
mbed_official	324:406fd2029f23	787
mbed_official	324:406fd2029f23	788	#define HW_SIM_SOPT4(x) ((__IO hw_sim_sopt4_t ) HW_SIM_SOPT4_ADDR(x))
mbed_official	324:406fd2029f23	789	#define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U)
mbed_official	324:406fd2029f23	790	#define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v))
mbed_official	324:406fd2029f23	791	#define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) \| (v)))
mbed_official	324:406fd2029f23	792	#define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	793	#define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	794	/@}/
mbed_official	324:406fd2029f23	795
mbed_official	324:406fd2029f23	796	/*
mbed_official	324:406fd2029f23	797	* Constants & macros for individual SIM_SOPT4 bitfields
mbed_official	324:406fd2029f23	798	*/
mbed_official	324:406fd2029f23	799
mbed_official	324:406fd2029f23	800	/*!
mbed_official	324:406fd2029f23	801	* @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
mbed_official	324:406fd2029f23	802	*
mbed_official	324:406fd2029f23	803	* Selects the source of FTM0 fault 0. The pin source for fault 0 must be
mbed_official	324:406fd2029f23	804	* configured for the FTM module fault function through the appropriate pin control
mbed_official	324:406fd2029f23	805	* register in the port control module.
mbed_official	324:406fd2029f23	806	*
mbed_official	324:406fd2029f23	807	* Values:
mbed_official	324:406fd2029f23	808	* - 0 - FTM0_FLT0 pin
mbed_official	324:406fd2029f23	809	* - 1 - CMP0 out
mbed_official	324:406fd2029f23	810	*/
mbed_official	324:406fd2029f23	811	/@{/
mbed_official	324:406fd2029f23	812	#define BP_SIM_SOPT4_FTM0FLT0 (0U) /!< Bit position for SIM_SOPT4_FTM0FLT0. /
mbed_official	324:406fd2029f23	813	#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /!< Bit mask for SIM_SOPT4_FTM0FLT0. /
mbed_official	324:406fd2029f23	814	#define BS_SIM_SOPT4_FTM0FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. /
mbed_official	324:406fd2029f23	815
mbed_official	324:406fd2029f23	816	/! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. /
mbed_official	324:406fd2029f23	817	#define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))
mbed_official	324:406fd2029f23	818
mbed_official	324:406fd2029f23	819	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. /
mbed_official	324:406fd2029f23	820	#define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0)
mbed_official	324:406fd2029f23	821
mbed_official	324:406fd2029f23	822	/! @brief Set the FTM0FLT0 field to a new value. /
mbed_official	324:406fd2029f23	823	#define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v))
mbed_official	324:406fd2029f23	824	/@}/
mbed_official	324:406fd2029f23	825
mbed_official	324:406fd2029f23	826	/*!
mbed_official	324:406fd2029f23	827	* @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
mbed_official	324:406fd2029f23	828	*
mbed_official	324:406fd2029f23	829	* Selects the source of FTM0 fault 1. The pin source for fault 1 must be
mbed_official	324:406fd2029f23	830	* configured for the FTM module fault function through the appropriate pin control
mbed_official	324:406fd2029f23	831	* register in the port control module.
mbed_official	324:406fd2029f23	832	*
mbed_official	324:406fd2029f23	833	* Values:
mbed_official	324:406fd2029f23	834	* - 0 - FTM0_FLT1 pin
mbed_official	324:406fd2029f23	835	* - 1 - CMP1 out
mbed_official	324:406fd2029f23	836	*/
mbed_official	324:406fd2029f23	837	/@{/
mbed_official	324:406fd2029f23	838	#define BP_SIM_SOPT4_FTM0FLT1 (1U) /!< Bit position for SIM_SOPT4_FTM0FLT1. /
mbed_official	324:406fd2029f23	839	#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /!< Bit mask for SIM_SOPT4_FTM0FLT1. /
mbed_official	324:406fd2029f23	840	#define BS_SIM_SOPT4_FTM0FLT1 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. /
mbed_official	324:406fd2029f23	841
mbed_official	324:406fd2029f23	842	/! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. /
mbed_official	324:406fd2029f23	843	#define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))
mbed_official	324:406fd2029f23	844
mbed_official	324:406fd2029f23	845	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. /
mbed_official	324:406fd2029f23	846	#define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1)
mbed_official	324:406fd2029f23	847
mbed_official	324:406fd2029f23	848	/! @brief Set the FTM0FLT1 field to a new value. /
mbed_official	324:406fd2029f23	849	#define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v))
mbed_official	324:406fd2029f23	850	/@}/
mbed_official	324:406fd2029f23	851
mbed_official	324:406fd2029f23	852	/*!
mbed_official	324:406fd2029f23	853	* @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
mbed_official	324:406fd2029f23	854	*
mbed_official	324:406fd2029f23	855	* Selects the source of FTM0 fault 2. The pin source for fault 2 must be
mbed_official	324:406fd2029f23	856	* configured for the FTM module fault function through the appropriate pin control
mbed_official	324:406fd2029f23	857	* register in the port control module.
mbed_official	324:406fd2029f23	858	*
mbed_official	324:406fd2029f23	859	* Values:
mbed_official	324:406fd2029f23	860	* - 0 - FTM0_FLT2 pin
mbed_official	324:406fd2029f23	861	* - 1 - CMP2 out
mbed_official	324:406fd2029f23	862	*/
mbed_official	324:406fd2029f23	863	/@{/
mbed_official	324:406fd2029f23	864	#define BP_SIM_SOPT4_FTM0FLT2 (2U) /!< Bit position for SIM_SOPT4_FTM0FLT2. /
mbed_official	324:406fd2029f23	865	#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /!< Bit mask for SIM_SOPT4_FTM0FLT2. /
mbed_official	324:406fd2029f23	866	#define BS_SIM_SOPT4_FTM0FLT2 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. /
mbed_official	324:406fd2029f23	867
mbed_official	324:406fd2029f23	868	/! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. /
mbed_official	324:406fd2029f23	869	#define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2))
mbed_official	324:406fd2029f23	870
mbed_official	324:406fd2029f23	871	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. /
mbed_official	324:406fd2029f23	872	#define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2)
mbed_official	324:406fd2029f23	873
mbed_official	324:406fd2029f23	874	/! @brief Set the FTM0FLT2 field to a new value. /
mbed_official	324:406fd2029f23	875	#define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v))
mbed_official	324:406fd2029f23	876	/@}/
mbed_official	324:406fd2029f23	877
mbed_official	324:406fd2029f23	878	/*!
mbed_official	324:406fd2029f23	879	* @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
mbed_official	324:406fd2029f23	880	*
mbed_official	324:406fd2029f23	881	* Selects the source of FTM1 fault 0. The pin source for fault 0 must be
mbed_official	324:406fd2029f23	882	* configured for the FTM module fault function through the appropriate pin control
mbed_official	324:406fd2029f23	883	* register in the port control module.
mbed_official	324:406fd2029f23	884	*
mbed_official	324:406fd2029f23	885	* Values:
mbed_official	324:406fd2029f23	886	* - 0 - FTM1_FLT0 pin
mbed_official	324:406fd2029f23	887	* - 1 - CMP0 out
mbed_official	324:406fd2029f23	888	*/
mbed_official	324:406fd2029f23	889	/@{/
mbed_official	324:406fd2029f23	890	#define BP_SIM_SOPT4_FTM1FLT0 (4U) /!< Bit position for SIM_SOPT4_FTM1FLT0. /
mbed_official	324:406fd2029f23	891	#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /!< Bit mask for SIM_SOPT4_FTM1FLT0. /
mbed_official	324:406fd2029f23	892	#define BS_SIM_SOPT4_FTM1FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. /
mbed_official	324:406fd2029f23	893
mbed_official	324:406fd2029f23	894	/! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. /
mbed_official	324:406fd2029f23	895	#define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))
mbed_official	324:406fd2029f23	896
mbed_official	324:406fd2029f23	897	/! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. /
mbed_official	324:406fd2029f23	898	#define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0)
mbed_official	324:406fd2029f23	899
mbed_official	324:406fd2029f23	900	/! @brief Set the FTM1FLT0 field to a new value. /
mbed_official	324:406fd2029f23	901	#define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v))
mbed_official	324:406fd2029f23	902	/@}/
mbed_official	324:406fd2029f23	903
mbed_official	324:406fd2029f23	904	/*!
mbed_official	324:406fd2029f23	905	* @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
mbed_official	324:406fd2029f23	906	*
mbed_official	324:406fd2029f23	907	* Selects the source of FTM2 fault 0. The pin source for fault 0 must be
mbed_official	324:406fd2029f23	908	* configured for the FTM module fault function through the appropriate PORTx pin
mbed_official	324:406fd2029f23	909	* control register.
mbed_official	324:406fd2029f23	910	*
mbed_official	324:406fd2029f23	911	* Values:
mbed_official	324:406fd2029f23	912	* - 0 - FTM2_FLT0 pin
mbed_official	324:406fd2029f23	913	* - 1 - CMP0 out
mbed_official	324:406fd2029f23	914	*/
mbed_official	324:406fd2029f23	915	/@{/
mbed_official	324:406fd2029f23	916	#define BP_SIM_SOPT4_FTM2FLT0 (8U) /!< Bit position for SIM_SOPT4_FTM2FLT0. /
mbed_official	324:406fd2029f23	917	#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /!< Bit mask for SIM_SOPT4_FTM2FLT0. /
mbed_official	324:406fd2029f23	918	#define BS_SIM_SOPT4_FTM2FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. /
mbed_official	324:406fd2029f23	919
mbed_official	324:406fd2029f23	920	/! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. /
mbed_official	324:406fd2029f23	921	#define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))
mbed_official	324:406fd2029f23	922
mbed_official	324:406fd2029f23	923	/! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. /
mbed_official	324:406fd2029f23	924	#define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0)
mbed_official	324:406fd2029f23	925
mbed_official	324:406fd2029f23	926	/! @brief Set the FTM2FLT0 field to a new value. /
mbed_official	324:406fd2029f23	927	#define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v))
mbed_official	324:406fd2029f23	928	/@}/
mbed_official	324:406fd2029f23	929
mbed_official	324:406fd2029f23	930	/*!
mbed_official	324:406fd2029f23	931	* @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
mbed_official	324:406fd2029f23	932	*
mbed_official	324:406fd2029f23	933	* Selects the source of FTM3 fault 0. The pin source for fault 0 must be
mbed_official	324:406fd2029f23	934	* configured for the FTM module fault function through the appropriate PORTx pin
mbed_official	324:406fd2029f23	935	* control register.
mbed_official	324:406fd2029f23	936	*
mbed_official	324:406fd2029f23	937	* Values:
mbed_official	324:406fd2029f23	938	* - 0 - FTM3_FLT0 pin
mbed_official	324:406fd2029f23	939	* - 1 - CMP0 out
mbed_official	324:406fd2029f23	940	*/
mbed_official	324:406fd2029f23	941	/@{/
mbed_official	324:406fd2029f23	942	#define BP_SIM_SOPT4_FTM3FLT0 (12U) /!< Bit position for SIM_SOPT4_FTM3FLT0. /
mbed_official	324:406fd2029f23	943	#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /!< Bit mask for SIM_SOPT4_FTM3FLT0. /
mbed_official	324:406fd2029f23	944	#define BS_SIM_SOPT4_FTM3FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. /
mbed_official	324:406fd2029f23	945
mbed_official	324:406fd2029f23	946	/! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. /
mbed_official	324:406fd2029f23	947	#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))
mbed_official	324:406fd2029f23	948
mbed_official	324:406fd2029f23	949	/! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. /
mbed_official	324:406fd2029f23	950	#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0)
mbed_official	324:406fd2029f23	951
mbed_official	324:406fd2029f23	952	/! @brief Set the FTM3FLT0 field to a new value. /
mbed_official	324:406fd2029f23	953	#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v))
mbed_official	324:406fd2029f23	954	/@}/
mbed_official	324:406fd2029f23	955
mbed_official	324:406fd2029f23	956	/*!
mbed_official	324:406fd2029f23	957	* @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
mbed_official	324:406fd2029f23	958	*
mbed_official	324:406fd2029f23	959	* Selects the source for FTM1 channel 0 input capture. When the FTM is not in
mbed_official	324:406fd2029f23	960	* input capture mode, clear this field.
mbed_official	324:406fd2029f23	961	*
mbed_official	324:406fd2029f23	962	* Values:
mbed_official	324:406fd2029f23	963	* - 00 - FTM1_CH0 signal
mbed_official	324:406fd2029f23	964	* - 01 - CMP0 output
mbed_official	324:406fd2029f23	965	* - 10 - CMP1 output
mbed_official	324:406fd2029f23	966	* - 11 - USB start of frame pulse
mbed_official	324:406fd2029f23	967	*/
mbed_official	324:406fd2029f23	968	/@{/
mbed_official	324:406fd2029f23	969	#define BP_SIM_SOPT4_FTM1CH0SRC (18U) /!< Bit position for SIM_SOPT4_FTM1CH0SRC. /
mbed_official	324:406fd2029f23	970	#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /!< Bit mask for SIM_SOPT4_FTM1CH0SRC. /
mbed_official	324:406fd2029f23	971	#define BS_SIM_SOPT4_FTM1CH0SRC (2U) /!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. /
mbed_official	324:406fd2029f23	972
mbed_official	324:406fd2029f23	973	/! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. /
mbed_official	324:406fd2029f23	974	#define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC)
mbed_official	324:406fd2029f23	975
mbed_official	324:406fd2029f23	976	/! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. /
mbed_official	324:406fd2029f23	977	#define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC)
mbed_official	324:406fd2029f23	978
mbed_official	324:406fd2029f23	979	/! @brief Set the FTM1CH0SRC field to a new value. /
mbed_official	324:406fd2029f23	980	#define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) \| BF_SIM_SOPT4_FTM1CH0SRC(v)))
mbed_official	324:406fd2029f23	981	/@}/
mbed_official	324:406fd2029f23	982
mbed_official	324:406fd2029f23	983	/*!
mbed_official	324:406fd2029f23	984	* @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
mbed_official	324:406fd2029f23	985	*
mbed_official	324:406fd2029f23	986	* Selects the source for FTM2 channel 0 input capture. When the FTM is not in
mbed_official	324:406fd2029f23	987	* input capture mode, clear this field.
mbed_official	324:406fd2029f23	988	*
mbed_official	324:406fd2029f23	989	* Values:
mbed_official	324:406fd2029f23	990	* - 00 - FTM2_CH0 signal
mbed_official	324:406fd2029f23	991	* - 01 - CMP0 output
mbed_official	324:406fd2029f23	992	* - 10 - CMP1 output
mbed_official	324:406fd2029f23	993	* - 11 - Reserved
mbed_official	324:406fd2029f23	994	*/
mbed_official	324:406fd2029f23	995	/@{/
mbed_official	324:406fd2029f23	996	#define BP_SIM_SOPT4_FTM2CH0SRC (20U) /!< Bit position for SIM_SOPT4_FTM2CH0SRC. /
mbed_official	324:406fd2029f23	997	#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /!< Bit mask for SIM_SOPT4_FTM2CH0SRC. /
mbed_official	324:406fd2029f23	998	#define BS_SIM_SOPT4_FTM2CH0SRC (2U) /!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. /
mbed_official	324:406fd2029f23	999
mbed_official	324:406fd2029f23	1000	/! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. /
mbed_official	324:406fd2029f23	1001	#define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC)
mbed_official	324:406fd2029f23	1002
mbed_official	324:406fd2029f23	1003	/! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. /
mbed_official	324:406fd2029f23	1004	#define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC)
mbed_official	324:406fd2029f23	1005
mbed_official	324:406fd2029f23	1006	/! @brief Set the FTM2CH0SRC field to a new value. /
mbed_official	324:406fd2029f23	1007	#define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) \| BF_SIM_SOPT4_FTM2CH0SRC(v)))
mbed_official	324:406fd2029f23	1008	/@}/
mbed_official	324:406fd2029f23	1009
mbed_official	324:406fd2029f23	1010	/*!
mbed_official	324:406fd2029f23	1011	* @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
mbed_official	324:406fd2029f23	1012	*
mbed_official	324:406fd2029f23	1013	* Selects the external pin used to drive the clock to the FTM0 module. The
mbed_official	324:406fd2029f23	1014	* selected pin must also be configured for the FTM external clock function through
mbed_official	324:406fd2029f23	1015	* the appropriate pin control register in the port control module.
mbed_official	324:406fd2029f23	1016	*
mbed_official	324:406fd2029f23	1017	* Values:
mbed_official	324:406fd2029f23	1018	* - 0 - FTM_CLK0 pin
mbed_official	324:406fd2029f23	1019	* - 1 - FTM_CLK1 pin
mbed_official	324:406fd2029f23	1020	*/
mbed_official	324:406fd2029f23	1021	/@{/
mbed_official	324:406fd2029f23	1022	#define BP_SIM_SOPT4_FTM0CLKSEL (24U) /!< Bit position for SIM_SOPT4_FTM0CLKSEL. /
mbed_official	324:406fd2029f23	1023	#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /!< Bit mask for SIM_SOPT4_FTM0CLKSEL. /
mbed_official	324:406fd2029f23	1024	#define BS_SIM_SOPT4_FTM0CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. /
mbed_official	324:406fd2029f23	1025
mbed_official	324:406fd2029f23	1026	/! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. /
mbed_official	324:406fd2029f23	1027	#define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))
mbed_official	324:406fd2029f23	1028
mbed_official	324:406fd2029f23	1029	/! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. /
mbed_official	324:406fd2029f23	1030	#define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL)
mbed_official	324:406fd2029f23	1031
mbed_official	324:406fd2029f23	1032	/! @brief Set the FTM0CLKSEL field to a new value. /
mbed_official	324:406fd2029f23	1033	#define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v))
mbed_official	324:406fd2029f23	1034	/@}/
mbed_official	324:406fd2029f23	1035
mbed_official	324:406fd2029f23	1036	/*!
mbed_official	324:406fd2029f23	1037	* @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
mbed_official	324:406fd2029f23	1038	*
mbed_official	324:406fd2029f23	1039	* Selects the external pin used to drive the clock to the FTM1 module. The
mbed_official	324:406fd2029f23	1040	* selected pin must also be configured for the FTM external clock function through
mbed_official	324:406fd2029f23	1041	* the appropriate pin control register in the port control module.
mbed_official	324:406fd2029f23	1042	*
mbed_official	324:406fd2029f23	1043	* Values:
mbed_official	324:406fd2029f23	1044	* - 0 - FTM_CLK0 pin
mbed_official	324:406fd2029f23	1045	* - 1 - FTM_CLK1 pin
mbed_official	324:406fd2029f23	1046	*/
mbed_official	324:406fd2029f23	1047	/@{/
mbed_official	324:406fd2029f23	1048	#define BP_SIM_SOPT4_FTM1CLKSEL (25U) /!< Bit position for SIM_SOPT4_FTM1CLKSEL. /
mbed_official	324:406fd2029f23	1049	#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /!< Bit mask for SIM_SOPT4_FTM1CLKSEL. /
mbed_official	324:406fd2029f23	1050	#define BS_SIM_SOPT4_FTM1CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. /
mbed_official	324:406fd2029f23	1051
mbed_official	324:406fd2029f23	1052	/! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. /
mbed_official	324:406fd2029f23	1053	#define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))
mbed_official	324:406fd2029f23	1054
mbed_official	324:406fd2029f23	1055	/! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. /
mbed_official	324:406fd2029f23	1056	#define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL)
mbed_official	324:406fd2029f23	1057
mbed_official	324:406fd2029f23	1058	/! @brief Set the FTM1CLKSEL field to a new value. /
mbed_official	324:406fd2029f23	1059	#define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v))
mbed_official	324:406fd2029f23	1060	/@}/
mbed_official	324:406fd2029f23	1061
mbed_official	324:406fd2029f23	1062	/*!
mbed_official	324:406fd2029f23	1063	* @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
mbed_official	324:406fd2029f23	1064	*
mbed_official	324:406fd2029f23	1065	* Selects the external pin used to drive the clock to the FTM2 module. The
mbed_official	324:406fd2029f23	1066	* selected pin must also be configured for the FTM2 module external clock function
mbed_official	324:406fd2029f23	1067	* through the appropriate pin control register in the port control module.
mbed_official	324:406fd2029f23	1068	*
mbed_official	324:406fd2029f23	1069	* Values:
mbed_official	324:406fd2029f23	1070	* - 0 - FTM2 external clock driven by FTM_CLK0 pin.
mbed_official	324:406fd2029f23	1071	* - 1 - FTM2 external clock driven by FTM_CLK1 pin.
mbed_official	324:406fd2029f23	1072	*/
mbed_official	324:406fd2029f23	1073	/@{/
mbed_official	324:406fd2029f23	1074	#define BP_SIM_SOPT4_FTM2CLKSEL (26U) /!< Bit position for SIM_SOPT4_FTM2CLKSEL. /
mbed_official	324:406fd2029f23	1075	#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /!< Bit mask for SIM_SOPT4_FTM2CLKSEL. /
mbed_official	324:406fd2029f23	1076	#define BS_SIM_SOPT4_FTM2CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. /
mbed_official	324:406fd2029f23	1077
mbed_official	324:406fd2029f23	1078	/! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. /
mbed_official	324:406fd2029f23	1079	#define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))
mbed_official	324:406fd2029f23	1080
mbed_official	324:406fd2029f23	1081	/! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. /
mbed_official	324:406fd2029f23	1082	#define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL)
mbed_official	324:406fd2029f23	1083
mbed_official	324:406fd2029f23	1084	/! @brief Set the FTM2CLKSEL field to a new value. /
mbed_official	324:406fd2029f23	1085	#define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v))
mbed_official	324:406fd2029f23	1086	/@}/
mbed_official	324:406fd2029f23	1087
mbed_official	324:406fd2029f23	1088	/*!
mbed_official	324:406fd2029f23	1089	* @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
mbed_official	324:406fd2029f23	1090	*
mbed_official	324:406fd2029f23	1091	* Selects the external pin used to drive the clock to the FTM3 module. The
mbed_official	324:406fd2029f23	1092	* selected pin must also be configured for the FTM3 module external clock function
mbed_official	324:406fd2029f23	1093	* through the appropriate pin control register in the port control module.
mbed_official	324:406fd2029f23	1094	*
mbed_official	324:406fd2029f23	1095	* Values:
mbed_official	324:406fd2029f23	1096	* - 0 - FTM3 external clock driven by FTM_CLK0 pin.
mbed_official	324:406fd2029f23	1097	* - 1 - FTM3 external clock driven by FTM_CLK1 pin.
mbed_official	324:406fd2029f23	1098	*/
mbed_official	324:406fd2029f23	1099	/@{/
mbed_official	324:406fd2029f23	1100	#define BP_SIM_SOPT4_FTM3CLKSEL (27U) /!< Bit position for SIM_SOPT4_FTM3CLKSEL. /
mbed_official	324:406fd2029f23	1101	#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /!< Bit mask for SIM_SOPT4_FTM3CLKSEL. /
mbed_official	324:406fd2029f23	1102	#define BS_SIM_SOPT4_FTM3CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. /
mbed_official	324:406fd2029f23	1103
mbed_official	324:406fd2029f23	1104	/! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. /
mbed_official	324:406fd2029f23	1105	#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))
mbed_official	324:406fd2029f23	1106
mbed_official	324:406fd2029f23	1107	/! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. /
mbed_official	324:406fd2029f23	1108	#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL)
mbed_official	324:406fd2029f23	1109
mbed_official	324:406fd2029f23	1110	/! @brief Set the FTM3CLKSEL field to a new value. /
mbed_official	324:406fd2029f23	1111	#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v))
mbed_official	324:406fd2029f23	1112	/@}/
mbed_official	324:406fd2029f23	1113
mbed_official	324:406fd2029f23	1114	/*!
mbed_official	324:406fd2029f23	1115	* @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
mbed_official	324:406fd2029f23	1116	*
mbed_official	324:406fd2029f23	1117	* Selects the source of FTM0 hardware trigger 0.
mbed_official	324:406fd2029f23	1118	*
mbed_official	324:406fd2029f23	1119	* Values:
mbed_official	324:406fd2029f23	1120	* - 0 - HSCMP0 output drives FTM0 hardware trigger 0
mbed_official	324:406fd2029f23	1121	* - 1 - FTM1 channel match drives FTM0 hardware trigger 0
mbed_official	324:406fd2029f23	1122	*/
mbed_official	324:406fd2029f23	1123	/@{/
mbed_official	324:406fd2029f23	1124	#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /!< Bit position for SIM_SOPT4_FTM0TRG0SRC. /
mbed_official	324:406fd2029f23	1125	#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. /
mbed_official	324:406fd2029f23	1126	#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. /
mbed_official	324:406fd2029f23	1127
mbed_official	324:406fd2029f23	1128	/! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. /
mbed_official	324:406fd2029f23	1129	#define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))
mbed_official	324:406fd2029f23	1130
mbed_official	324:406fd2029f23	1131	/! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. /
mbed_official	324:406fd2029f23	1132	#define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC)
mbed_official	324:406fd2029f23	1133
mbed_official	324:406fd2029f23	1134	/! @brief Set the FTM0TRG0SRC field to a new value. /
mbed_official	324:406fd2029f23	1135	#define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
mbed_official	324:406fd2029f23	1136	/@}/
mbed_official	324:406fd2029f23	1137
mbed_official	324:406fd2029f23	1138	/*!
mbed_official	324:406fd2029f23	1139	* @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
mbed_official	324:406fd2029f23	1140	*
mbed_official	324:406fd2029f23	1141	* Selects the source of FTM0 hardware trigger 1.
mbed_official	324:406fd2029f23	1142	*
mbed_official	324:406fd2029f23	1143	* Values:
mbed_official	324:406fd2029f23	1144	* - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
mbed_official	324:406fd2029f23	1145	* - 1 - FTM2 channel match drives FTM0 hardware trigger 1
mbed_official	324:406fd2029f23	1146	*/
mbed_official	324:406fd2029f23	1147	/@{/
mbed_official	324:406fd2029f23	1148	#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /!< Bit position for SIM_SOPT4_FTM0TRG1SRC. /
mbed_official	324:406fd2029f23	1149	#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. /
mbed_official	324:406fd2029f23	1150	#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. /
mbed_official	324:406fd2029f23	1151
mbed_official	324:406fd2029f23	1152	/! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. /
mbed_official	324:406fd2029f23	1153	#define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))
mbed_official	324:406fd2029f23	1154
mbed_official	324:406fd2029f23	1155	/! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. /
mbed_official	324:406fd2029f23	1156	#define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC)
mbed_official	324:406fd2029f23	1157
mbed_official	324:406fd2029f23	1158	/! @brief Set the FTM0TRG1SRC field to a new value. /
mbed_official	324:406fd2029f23	1159	#define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
mbed_official	324:406fd2029f23	1160	/@}/
mbed_official	324:406fd2029f23	1161
mbed_official	324:406fd2029f23	1162	/*!
mbed_official	324:406fd2029f23	1163	* @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
mbed_official	324:406fd2029f23	1164	*
mbed_official	324:406fd2029f23	1165	* Selects the source of FTM3 hardware trigger 0.
mbed_official	324:406fd2029f23	1166	*
mbed_official	324:406fd2029f23	1167	* Values:
mbed_official	324:406fd2029f23	1168	* - 0 - Reserved
mbed_official	324:406fd2029f23	1169	* - 1 - FTM1 channel match drives FTM3 hardware trigger 0
mbed_official	324:406fd2029f23	1170	*/
mbed_official	324:406fd2029f23	1171	/@{/
mbed_official	324:406fd2029f23	1172	#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /!< Bit position for SIM_SOPT4_FTM3TRG0SRC. /
mbed_official	324:406fd2029f23	1173	#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. /
mbed_official	324:406fd2029f23	1174	#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. /
mbed_official	324:406fd2029f23	1175
mbed_official	324:406fd2029f23	1176	/! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. /
mbed_official	324:406fd2029f23	1177	#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))
mbed_official	324:406fd2029f23	1178
mbed_official	324:406fd2029f23	1179	/! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. /
mbed_official	324:406fd2029f23	1180	#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC)
mbed_official	324:406fd2029f23	1181
mbed_official	324:406fd2029f23	1182	/! @brief Set the FTM3TRG0SRC field to a new value. /
mbed_official	324:406fd2029f23	1183	#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
mbed_official	324:406fd2029f23	1184	/@}/
mbed_official	324:406fd2029f23	1185
mbed_official	324:406fd2029f23	1186	/*!
mbed_official	324:406fd2029f23	1187	* @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
mbed_official	324:406fd2029f23	1188	*
mbed_official	324:406fd2029f23	1189	* Selects the source of FTM3 hardware trigger 1.
mbed_official	324:406fd2029f23	1190	*
mbed_official	324:406fd2029f23	1191	* Values:
mbed_official	324:406fd2029f23	1192	* - 0 - Reserved
mbed_official	324:406fd2029f23	1193	* - 1 - FTM2 channel match drives FTM3 hardware trigger 1
mbed_official	324:406fd2029f23	1194	*/
mbed_official	324:406fd2029f23	1195	/@{/
mbed_official	324:406fd2029f23	1196	#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /!< Bit position for SIM_SOPT4_FTM3TRG1SRC. /
mbed_official	324:406fd2029f23	1197	#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. /
mbed_official	324:406fd2029f23	1198	#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. /
mbed_official	324:406fd2029f23	1199
mbed_official	324:406fd2029f23	1200	/! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. /
mbed_official	324:406fd2029f23	1201	#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))
mbed_official	324:406fd2029f23	1202
mbed_official	324:406fd2029f23	1203	/! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. /
mbed_official	324:406fd2029f23	1204	#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC)
mbed_official	324:406fd2029f23	1205
mbed_official	324:406fd2029f23	1206	/! @brief Set the FTM3TRG1SRC field to a new value. /
mbed_official	324:406fd2029f23	1207	#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
mbed_official	324:406fd2029f23	1208	/@}/
mbed_official	324:406fd2029f23	1209
mbed_official	324:406fd2029f23	1210	/*******************************************************************************
mbed_official	324:406fd2029f23	1211	* HW_SIM_SOPT5 - System Options Register 5
mbed_official	324:406fd2029f23	1212	******************************************************************************/
mbed_official	324:406fd2029f23	1213
mbed_official	324:406fd2029f23	1214	/*!
mbed_official	324:406fd2029f23	1215	* @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
mbed_official	324:406fd2029f23	1216	*
mbed_official	324:406fd2029f23	1217	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1218	*/
mbed_official	324:406fd2029f23	1219	typedef union _hw_sim_sopt5
mbed_official	324:406fd2029f23	1220	{
mbed_official	324:406fd2029f23	1221	uint32_t U;
mbed_official	324:406fd2029f23	1222	struct _hw_sim_sopt5_bitfields
mbed_official	324:406fd2029f23	1223	{
mbed_official	324:406fd2029f23	1224	uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source
mbed_official	324:406fd2029f23	1225	* select */
mbed_official	324:406fd2029f23	1226	uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select
mbed_official	324:406fd2029f23	1227	* */
mbed_official	324:406fd2029f23	1228	uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source
mbed_official	324:406fd2029f23	1229	* select */
mbed_official	324:406fd2029f23	1230	uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select
mbed_official	324:406fd2029f23	1231	* */
mbed_official	324:406fd2029f23	1232	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1233	} B;
mbed_official	324:406fd2029f23	1234	} hw_sim_sopt5_t;
mbed_official	324:406fd2029f23	1235
mbed_official	324:406fd2029f23	1236	/*!
mbed_official	324:406fd2029f23	1237	* @name Constants and macros for entire SIM_SOPT5 register
mbed_official	324:406fd2029f23	1238	*/
mbed_official	324:406fd2029f23	1239	/@{/
mbed_official	324:406fd2029f23	1240	#define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U)
mbed_official	324:406fd2029f23	1241
mbed_official	324:406fd2029f23	1242	#define HW_SIM_SOPT5(x) ((__IO hw_sim_sopt5_t ) HW_SIM_SOPT5_ADDR(x))
mbed_official	324:406fd2029f23	1243	#define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U)
mbed_official	324:406fd2029f23	1244	#define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v))
mbed_official	324:406fd2029f23	1245	#define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1246	#define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1247	#define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1248	/@}/
mbed_official	324:406fd2029f23	1249
mbed_official	324:406fd2029f23	1250	/*
mbed_official	324:406fd2029f23	1251	* Constants & macros for individual SIM_SOPT5 bitfields
mbed_official	324:406fd2029f23	1252	*/
mbed_official	324:406fd2029f23	1253
mbed_official	324:406fd2029f23	1254	/*!
mbed_official	324:406fd2029f23	1255	* @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
mbed_official	324:406fd2029f23	1256	*
mbed_official	324:406fd2029f23	1257	* Selects the source for the UART 0 transmit data.
mbed_official	324:406fd2029f23	1258	*
mbed_official	324:406fd2029f23	1259	* Values:
mbed_official	324:406fd2029f23	1260	* - 00 - UART0_TX pin
mbed_official	324:406fd2029f23	1261	* - 01 - UART0_TX pin modulated with FTM1 channel 0 output
mbed_official	324:406fd2029f23	1262	* - 10 - UART0_TX pin modulated with FTM2 channel 0 output
mbed_official	324:406fd2029f23	1263	* - 11 - Reserved
mbed_official	324:406fd2029f23	1264	*/
mbed_official	324:406fd2029f23	1265	/@{/
mbed_official	324:406fd2029f23	1266	#define BP_SIM_SOPT5_UART0TXSRC (0U) /!< Bit position for SIM_SOPT5_UART0TXSRC. /
mbed_official	324:406fd2029f23	1267	#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /!< Bit mask for SIM_SOPT5_UART0TXSRC. /
mbed_official	324:406fd2029f23	1268	#define BS_SIM_SOPT5_UART0TXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. /
mbed_official	324:406fd2029f23	1269
mbed_official	324:406fd2029f23	1270	/! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. /
mbed_official	324:406fd2029f23	1271	#define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC)
mbed_official	324:406fd2029f23	1272
mbed_official	324:406fd2029f23	1273	/! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. /
mbed_official	324:406fd2029f23	1274	#define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC)
mbed_official	324:406fd2029f23	1275
mbed_official	324:406fd2029f23	1276	/! @brief Set the UART0TXSRC field to a new value. /
mbed_official	324:406fd2029f23	1277	#define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) \| BF_SIM_SOPT5_UART0TXSRC(v)))
mbed_official	324:406fd2029f23	1278	/@}/
mbed_official	324:406fd2029f23	1279
mbed_official	324:406fd2029f23	1280	/*!
mbed_official	324:406fd2029f23	1281	* @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
mbed_official	324:406fd2029f23	1282	*
mbed_official	324:406fd2029f23	1283	* Selects the source for the UART 0 receive data.
mbed_official	324:406fd2029f23	1284	*
mbed_official	324:406fd2029f23	1285	* Values:
mbed_official	324:406fd2029f23	1286	* - 00 - UART0_RX pin
mbed_official	324:406fd2029f23	1287	* - 01 - CMP0
mbed_official	324:406fd2029f23	1288	* - 10 - CMP1
mbed_official	324:406fd2029f23	1289	* - 11 - Reserved
mbed_official	324:406fd2029f23	1290	*/
mbed_official	324:406fd2029f23	1291	/@{/
mbed_official	324:406fd2029f23	1292	#define BP_SIM_SOPT5_UART0RXSRC (2U) /!< Bit position for SIM_SOPT5_UART0RXSRC. /
mbed_official	324:406fd2029f23	1293	#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /!< Bit mask for SIM_SOPT5_UART0RXSRC. /
mbed_official	324:406fd2029f23	1294	#define BS_SIM_SOPT5_UART0RXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. /
mbed_official	324:406fd2029f23	1295
mbed_official	324:406fd2029f23	1296	/! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. /
mbed_official	324:406fd2029f23	1297	#define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC)
mbed_official	324:406fd2029f23	1298
mbed_official	324:406fd2029f23	1299	/! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. /
mbed_official	324:406fd2029f23	1300	#define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC)
mbed_official	324:406fd2029f23	1301
mbed_official	324:406fd2029f23	1302	/! @brief Set the UART0RXSRC field to a new value. /
mbed_official	324:406fd2029f23	1303	#define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) \| BF_SIM_SOPT5_UART0RXSRC(v)))
mbed_official	324:406fd2029f23	1304	/@}/
mbed_official	324:406fd2029f23	1305
mbed_official	324:406fd2029f23	1306	/*!
mbed_official	324:406fd2029f23	1307	* @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
mbed_official	324:406fd2029f23	1308	*
mbed_official	324:406fd2029f23	1309	* Selects the source for the UART 1 transmit data.
mbed_official	324:406fd2029f23	1310	*
mbed_official	324:406fd2029f23	1311	* Values:
mbed_official	324:406fd2029f23	1312	* - 00 - UART1_TX pin
mbed_official	324:406fd2029f23	1313	* - 01 - UART1_TX pin modulated with FTM1 channel 0 output
mbed_official	324:406fd2029f23	1314	* - 10 - UART1_TX pin modulated with FTM2 channel 0 output
mbed_official	324:406fd2029f23	1315	* - 11 - Reserved
mbed_official	324:406fd2029f23	1316	*/
mbed_official	324:406fd2029f23	1317	/@{/
mbed_official	324:406fd2029f23	1318	#define BP_SIM_SOPT5_UART1TXSRC (4U) /!< Bit position for SIM_SOPT5_UART1TXSRC. /
mbed_official	324:406fd2029f23	1319	#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /!< Bit mask for SIM_SOPT5_UART1TXSRC. /
mbed_official	324:406fd2029f23	1320	#define BS_SIM_SOPT5_UART1TXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. /
mbed_official	324:406fd2029f23	1321
mbed_official	324:406fd2029f23	1322	/! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. /
mbed_official	324:406fd2029f23	1323	#define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC)
mbed_official	324:406fd2029f23	1324
mbed_official	324:406fd2029f23	1325	/! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. /
mbed_official	324:406fd2029f23	1326	#define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC)
mbed_official	324:406fd2029f23	1327
mbed_official	324:406fd2029f23	1328	/! @brief Set the UART1TXSRC field to a new value. /
mbed_official	324:406fd2029f23	1329	#define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) \| BF_SIM_SOPT5_UART1TXSRC(v)))
mbed_official	324:406fd2029f23	1330	/@}/
mbed_official	324:406fd2029f23	1331
mbed_official	324:406fd2029f23	1332	/*!
mbed_official	324:406fd2029f23	1333	* @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
mbed_official	324:406fd2029f23	1334	*
mbed_official	324:406fd2029f23	1335	* Selects the source for the UART 1 receive data.
mbed_official	324:406fd2029f23	1336	*
mbed_official	324:406fd2029f23	1337	* Values:
mbed_official	324:406fd2029f23	1338	* - 00 - UART1_RX pin
mbed_official	324:406fd2029f23	1339	* - 01 - CMP0
mbed_official	324:406fd2029f23	1340	* - 10 - CMP1
mbed_official	324:406fd2029f23	1341	* - 11 - Reserved
mbed_official	324:406fd2029f23	1342	*/
mbed_official	324:406fd2029f23	1343	/@{/
mbed_official	324:406fd2029f23	1344	#define BP_SIM_SOPT5_UART1RXSRC (6U) /!< Bit position for SIM_SOPT5_UART1RXSRC. /
mbed_official	324:406fd2029f23	1345	#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /!< Bit mask for SIM_SOPT5_UART1RXSRC. /
mbed_official	324:406fd2029f23	1346	#define BS_SIM_SOPT5_UART1RXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. /
mbed_official	324:406fd2029f23	1347
mbed_official	324:406fd2029f23	1348	/! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. /
mbed_official	324:406fd2029f23	1349	#define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC)
mbed_official	324:406fd2029f23	1350
mbed_official	324:406fd2029f23	1351	/! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. /
mbed_official	324:406fd2029f23	1352	#define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC)
mbed_official	324:406fd2029f23	1353
mbed_official	324:406fd2029f23	1354	/! @brief Set the UART1RXSRC field to a new value. /
mbed_official	324:406fd2029f23	1355	#define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) \| BF_SIM_SOPT5_UART1RXSRC(v)))
mbed_official	324:406fd2029f23	1356	/@}/
mbed_official	324:406fd2029f23	1357
mbed_official	324:406fd2029f23	1358	/*******************************************************************************
mbed_official	324:406fd2029f23	1359	* HW_SIM_SOPT7 - System Options Register 7
mbed_official	324:406fd2029f23	1360	******************************************************************************/
mbed_official	324:406fd2029f23	1361
mbed_official	324:406fd2029f23	1362	/*!
mbed_official	324:406fd2029f23	1363	* @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
mbed_official	324:406fd2029f23	1364	*
mbed_official	324:406fd2029f23	1365	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1366	*/
mbed_official	324:406fd2029f23	1367	typedef union _hw_sim_sopt7
mbed_official	324:406fd2029f23	1368	{
mbed_official	324:406fd2029f23	1369	uint32_t U;
mbed_official	324:406fd2029f23	1370	struct _hw_sim_sopt7_bitfields
mbed_official	324:406fd2029f23	1371	{
mbed_official	324:406fd2029f23	1372	uint32_t ADC0TRGSEL : 4; /!< [3:0] ADC0 trigger select /
mbed_official	324:406fd2029f23	1373	uint32_t ADC0PRETRGSEL : 1; /!< [4] ADC0 pretrigger select /
mbed_official	324:406fd2029f23	1374	uint32_t RESERVED0 : 2; /!< [6:5] /
mbed_official	324:406fd2029f23	1375	uint32_t ADC0ALTTRGEN : 1; /!< [7] ADC0 alternate trigger enable /
mbed_official	324:406fd2029f23	1376	uint32_t ADC1TRGSEL : 4; /!< [11:8] ADC1 trigger select /
mbed_official	324:406fd2029f23	1377	uint32_t ADC1PRETRGSEL : 1; /!< [12] ADC1 pre-trigger select /
mbed_official	324:406fd2029f23	1378	uint32_t RESERVED1 : 2; /!< [14:13] /
mbed_official	324:406fd2029f23	1379	uint32_t ADC1ALTTRGEN : 1; /!< [15] ADC1 alternate trigger enable /
mbed_official	324:406fd2029f23	1380	uint32_t RESERVED2 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	1381	} B;
mbed_official	324:406fd2029f23	1382	} hw_sim_sopt7_t;
mbed_official	324:406fd2029f23	1383
mbed_official	324:406fd2029f23	1384	/*!
mbed_official	324:406fd2029f23	1385	* @name Constants and macros for entire SIM_SOPT7 register
mbed_official	324:406fd2029f23	1386	*/
mbed_official	324:406fd2029f23	1387	/@{/
mbed_official	324:406fd2029f23	1388	#define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U)
mbed_official	324:406fd2029f23	1389
mbed_official	324:406fd2029f23	1390	#define HW_SIM_SOPT7(x) ((__IO hw_sim_sopt7_t ) HW_SIM_SOPT7_ADDR(x))
mbed_official	324:406fd2029f23	1391	#define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U)
mbed_official	324:406fd2029f23	1392	#define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v))
mbed_official	324:406fd2029f23	1393	#define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1394	#define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1395	#define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1396	/@}/
mbed_official	324:406fd2029f23	1397
mbed_official	324:406fd2029f23	1398	/*
mbed_official	324:406fd2029f23	1399	* Constants & macros for individual SIM_SOPT7 bitfields
mbed_official	324:406fd2029f23	1400	*/
mbed_official	324:406fd2029f23	1401
mbed_official	324:406fd2029f23	1402	/*!
mbed_official	324:406fd2029f23	1403	* @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
mbed_official	324:406fd2029f23	1404	*
mbed_official	324:406fd2029f23	1405	* Selects the ADC0 trigger source when alternative triggers are functional in
mbed_official	324:406fd2029f23	1406	* stop and VLPS modes. .
mbed_official	324:406fd2029f23	1407	*
mbed_official	324:406fd2029f23	1408	* Values:
mbed_official	324:406fd2029f23	1409	* - 0000 - PDB external trigger pin input (PDB0_EXTRG)
mbed_official	324:406fd2029f23	1410	* - 0001 - High speed comparator 0 output
mbed_official	324:406fd2029f23	1411	* - 0010 - High speed comparator 1 output
mbed_official	324:406fd2029f23	1412	* - 0011 - High speed comparator 2 output
mbed_official	324:406fd2029f23	1413	* - 0100 - PIT trigger 0
mbed_official	324:406fd2029f23	1414	* - 0101 - PIT trigger 1
mbed_official	324:406fd2029f23	1415	* - 0110 - PIT trigger 2
mbed_official	324:406fd2029f23	1416	* - 0111 - PIT trigger 3
mbed_official	324:406fd2029f23	1417	* - 1000 - FTM0 trigger
mbed_official	324:406fd2029f23	1418	* - 1001 - FTM1 trigger
mbed_official	324:406fd2029f23	1419	* - 1010 - FTM2 trigger
mbed_official	324:406fd2029f23	1420	* - 1011 - FTM3 trigger
mbed_official	324:406fd2029f23	1421	* - 1100 - RTC alarm
mbed_official	324:406fd2029f23	1422	* - 1101 - RTC seconds
mbed_official	324:406fd2029f23	1423	* - 1110 - Low-power timer (LPTMR) trigger
mbed_official	324:406fd2029f23	1424	* - 1111 - Reserved
mbed_official	324:406fd2029f23	1425	*/
mbed_official	324:406fd2029f23	1426	/@{/
mbed_official	324:406fd2029f23	1427	#define BP_SIM_SOPT7_ADC0TRGSEL (0U) /!< Bit position for SIM_SOPT7_ADC0TRGSEL. /
mbed_official	324:406fd2029f23	1428	#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /!< Bit mask for SIM_SOPT7_ADC0TRGSEL. /
mbed_official	324:406fd2029f23	1429	#define BS_SIM_SOPT7_ADC0TRGSEL (4U) /!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. /
mbed_official	324:406fd2029f23	1430
mbed_official	324:406fd2029f23	1431	/! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. /
mbed_official	324:406fd2029f23	1432	#define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL)
mbed_official	324:406fd2029f23	1433
mbed_official	324:406fd2029f23	1434	/! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. /
mbed_official	324:406fd2029f23	1435	#define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL)
mbed_official	324:406fd2029f23	1436
mbed_official	324:406fd2029f23	1437	/! @brief Set the ADC0TRGSEL field to a new value. /
mbed_official	324:406fd2029f23	1438	#define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) \| BF_SIM_SOPT7_ADC0TRGSEL(v)))
mbed_official	324:406fd2029f23	1439	/@}/
mbed_official	324:406fd2029f23	1440
mbed_official	324:406fd2029f23	1441	/*!
mbed_official	324:406fd2029f23	1442	* @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
mbed_official	324:406fd2029f23	1443	*
mbed_official	324:406fd2029f23	1444	* Selects the ADC0 pre-trigger source when alternative triggers are enabled
mbed_official	324:406fd2029f23	1445	* through ADC0ALTTRGEN.
mbed_official	324:406fd2029f23	1446	*
mbed_official	324:406fd2029f23	1447	* Values:
mbed_official	324:406fd2029f23	1448	* - 0 - Pre-trigger A
mbed_official	324:406fd2029f23	1449	* - 1 - Pre-trigger B
mbed_official	324:406fd2029f23	1450	*/
mbed_official	324:406fd2029f23	1451	/@{/
mbed_official	324:406fd2029f23	1452	#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. /
mbed_official	324:406fd2029f23	1453	#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. /
mbed_official	324:406fd2029f23	1454	#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. /
mbed_official	324:406fd2029f23	1455
mbed_official	324:406fd2029f23	1456	/! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. /
mbed_official	324:406fd2029f23	1457	#define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))
mbed_official	324:406fd2029f23	1458
mbed_official	324:406fd2029f23	1459	/! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. /
mbed_official	324:406fd2029f23	1460	#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL)
mbed_official	324:406fd2029f23	1461
mbed_official	324:406fd2029f23	1462	/! @brief Set the ADC0PRETRGSEL field to a new value. /
mbed_official	324:406fd2029f23	1463	#define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
mbed_official	324:406fd2029f23	1464	/@}/
mbed_official	324:406fd2029f23	1465
mbed_official	324:406fd2029f23	1466	/*!
mbed_official	324:406fd2029f23	1467	* @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
mbed_official	324:406fd2029f23	1468	*
mbed_official	324:406fd2029f23	1469	* Enable alternative conversion triggers for ADC0.
mbed_official	324:406fd2029f23	1470	*
mbed_official	324:406fd2029f23	1471	* Values:
mbed_official	324:406fd2029f23	1472	* - 0 - PDB trigger selected for ADC0.
mbed_official	324:406fd2029f23	1473	* - 1 - Alternate trigger selected for ADC0.
mbed_official	324:406fd2029f23	1474	*/
mbed_official	324:406fd2029f23	1475	/@{/
mbed_official	324:406fd2029f23	1476	#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. /
mbed_official	324:406fd2029f23	1477	#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. /
mbed_official	324:406fd2029f23	1478	#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. /
mbed_official	324:406fd2029f23	1479
mbed_official	324:406fd2029f23	1480	/! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. /
mbed_official	324:406fd2029f23	1481	#define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))
mbed_official	324:406fd2029f23	1482
mbed_official	324:406fd2029f23	1483	/! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. /
mbed_official	324:406fd2029f23	1484	#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN)
mbed_official	324:406fd2029f23	1485
mbed_official	324:406fd2029f23	1486	/! @brief Set the ADC0ALTTRGEN field to a new value. /
mbed_official	324:406fd2029f23	1487	#define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
mbed_official	324:406fd2029f23	1488	/@}/
mbed_official	324:406fd2029f23	1489
mbed_official	324:406fd2029f23	1490	/*!
mbed_official	324:406fd2029f23	1491	* @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
mbed_official	324:406fd2029f23	1492	*
mbed_official	324:406fd2029f23	1493	* Selects the ADC1 trigger source when alternative triggers are functional in
mbed_official	324:406fd2029f23	1494	* stop and VLPS modes.
mbed_official	324:406fd2029f23	1495	*
mbed_official	324:406fd2029f23	1496	* Values:
mbed_official	324:406fd2029f23	1497	* - 0000 - PDB external trigger pin input (PDB0_EXTRG)
mbed_official	324:406fd2029f23	1498	* - 0001 - High speed comparator 0 output
mbed_official	324:406fd2029f23	1499	* - 0010 - High speed comparator 1 output
mbed_official	324:406fd2029f23	1500	* - 0011 - High speed comparator 2 output
mbed_official	324:406fd2029f23	1501	* - 0100 - PIT trigger 0
mbed_official	324:406fd2029f23	1502	* - 0101 - PIT trigger 1
mbed_official	324:406fd2029f23	1503	* - 0110 - PIT trigger 2
mbed_official	324:406fd2029f23	1504	* - 0111 - PIT trigger 3
mbed_official	324:406fd2029f23	1505	* - 1000 - FTM0 trigger
mbed_official	324:406fd2029f23	1506	* - 1001 - FTM1 trigger
mbed_official	324:406fd2029f23	1507	* - 1010 - FTM2 trigger
mbed_official	324:406fd2029f23	1508	* - 1011 - FTM3 trigger
mbed_official	324:406fd2029f23	1509	* - 1100 - RTC alarm
mbed_official	324:406fd2029f23	1510	* - 1101 - RTC seconds
mbed_official	324:406fd2029f23	1511	* - 1110 - Low-power timer (LPTMR) trigger
mbed_official	324:406fd2029f23	1512	* - 1111 - Reserved
mbed_official	324:406fd2029f23	1513	*/
mbed_official	324:406fd2029f23	1514	/@{/
mbed_official	324:406fd2029f23	1515	#define BP_SIM_SOPT7_ADC1TRGSEL (8U) /!< Bit position for SIM_SOPT7_ADC1TRGSEL. /
mbed_official	324:406fd2029f23	1516	#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /!< Bit mask for SIM_SOPT7_ADC1TRGSEL. /
mbed_official	324:406fd2029f23	1517	#define BS_SIM_SOPT7_ADC1TRGSEL (4U) /!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. /
mbed_official	324:406fd2029f23	1518
mbed_official	324:406fd2029f23	1519	/! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. /
mbed_official	324:406fd2029f23	1520	#define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL)
mbed_official	324:406fd2029f23	1521
mbed_official	324:406fd2029f23	1522	/! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. /
mbed_official	324:406fd2029f23	1523	#define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL)
mbed_official	324:406fd2029f23	1524
mbed_official	324:406fd2029f23	1525	/! @brief Set the ADC1TRGSEL field to a new value. /
mbed_official	324:406fd2029f23	1526	#define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) \| BF_SIM_SOPT7_ADC1TRGSEL(v)))
mbed_official	324:406fd2029f23	1527	/@}/
mbed_official	324:406fd2029f23	1528
mbed_official	324:406fd2029f23	1529	/*!
mbed_official	324:406fd2029f23	1530	* @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
mbed_official	324:406fd2029f23	1531	*
mbed_official	324:406fd2029f23	1532	* Selects the ADC1 pre-trigger source when alternative triggers are enabled
mbed_official	324:406fd2029f23	1533	* through ADC1ALTTRGEN.
mbed_official	324:406fd2029f23	1534	*
mbed_official	324:406fd2029f23	1535	* Values:
mbed_official	324:406fd2029f23	1536	* - 0 - Pre-trigger A selected for ADC1.
mbed_official	324:406fd2029f23	1537	* - 1 - Pre-trigger B selected for ADC1.
mbed_official	324:406fd2029f23	1538	*/
mbed_official	324:406fd2029f23	1539	/@{/
mbed_official	324:406fd2029f23	1540	#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. /
mbed_official	324:406fd2029f23	1541	#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. /
mbed_official	324:406fd2029f23	1542	#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. /
mbed_official	324:406fd2029f23	1543
mbed_official	324:406fd2029f23	1544	/! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. /
mbed_official	324:406fd2029f23	1545	#define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))
mbed_official	324:406fd2029f23	1546
mbed_official	324:406fd2029f23	1547	/! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. /
mbed_official	324:406fd2029f23	1548	#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL)
mbed_official	324:406fd2029f23	1549
mbed_official	324:406fd2029f23	1550	/! @brief Set the ADC1PRETRGSEL field to a new value. /
mbed_official	324:406fd2029f23	1551	#define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
mbed_official	324:406fd2029f23	1552	/@}/
mbed_official	324:406fd2029f23	1553
mbed_official	324:406fd2029f23	1554	/*!
mbed_official	324:406fd2029f23	1555	* @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
mbed_official	324:406fd2029f23	1556	*
mbed_official	324:406fd2029f23	1557	* Enable alternative conversion triggers for ADC1.
mbed_official	324:406fd2029f23	1558	*
mbed_official	324:406fd2029f23	1559	* Values:
mbed_official	324:406fd2029f23	1560	* - 0 - PDB trigger selected for ADC1
mbed_official	324:406fd2029f23	1561	* - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
mbed_official	324:406fd2029f23	1562	*/
mbed_official	324:406fd2029f23	1563	/@{/
mbed_official	324:406fd2029f23	1564	#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. /
mbed_official	324:406fd2029f23	1565	#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. /
mbed_official	324:406fd2029f23	1566	#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. /
mbed_official	324:406fd2029f23	1567
mbed_official	324:406fd2029f23	1568	/! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. /
mbed_official	324:406fd2029f23	1569	#define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))
mbed_official	324:406fd2029f23	1570
mbed_official	324:406fd2029f23	1571	/! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. /
mbed_official	324:406fd2029f23	1572	#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN)
mbed_official	324:406fd2029f23	1573
mbed_official	324:406fd2029f23	1574	/! @brief Set the ADC1ALTTRGEN field to a new value. /
mbed_official	324:406fd2029f23	1575	#define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
mbed_official	324:406fd2029f23	1576	/@}/
mbed_official	324:406fd2029f23	1577
mbed_official	324:406fd2029f23	1578	/*******************************************************************************
mbed_official	324:406fd2029f23	1579	* HW_SIM_SDID - System Device Identification Register
mbed_official	324:406fd2029f23	1580	******************************************************************************/
mbed_official	324:406fd2029f23	1581
mbed_official	324:406fd2029f23	1582	/*!
mbed_official	324:406fd2029f23	1583	* @brief HW_SIM_SDID - System Device Identification Register (RO)
mbed_official	324:406fd2029f23	1584	*
mbed_official	324:406fd2029f23	1585	* Reset value: 0x00000380U
mbed_official	324:406fd2029f23	1586	*/
mbed_official	324:406fd2029f23	1587	typedef union _hw_sim_sdid
mbed_official	324:406fd2029f23	1588	{
mbed_official	324:406fd2029f23	1589	uint32_t U;
mbed_official	324:406fd2029f23	1590	struct _hw_sim_sdid_bitfields
mbed_official	324:406fd2029f23	1591	{
mbed_official	324:406fd2029f23	1592	uint32_t PINID : 4; /!< [3:0] Pincount identification /
mbed_official	324:406fd2029f23	1593	uint32_t FAMID : 3; /!< [6:4] Kinetis family identification /
mbed_official	324:406fd2029f23	1594	uint32_t DIEID : 5; /!< [11:7] Device Die ID /
mbed_official	324:406fd2029f23	1595	uint32_t REVID : 4; /!< [15:12] Device revision number /
mbed_official	324:406fd2029f23	1596	uint32_t RESERVED0 : 4; /!< [19:16] /
mbed_official	324:406fd2029f23	1597	uint32_t SERIESID : 4; /!< [23:20] Kinetis Series ID /
mbed_official	324:406fd2029f23	1598	uint32_t SUBFAMID : 4; /!< [27:24] Kinetis Sub-Family ID /
mbed_official	324:406fd2029f23	1599	uint32_t FAMILYID : 4; /!< [31:28] Kinetis Family ID /
mbed_official	324:406fd2029f23	1600	} B;
mbed_official	324:406fd2029f23	1601	} hw_sim_sdid_t;
mbed_official	324:406fd2029f23	1602
mbed_official	324:406fd2029f23	1603	/*!
mbed_official	324:406fd2029f23	1604	* @name Constants and macros for entire SIM_SDID register
mbed_official	324:406fd2029f23	1605	*/
mbed_official	324:406fd2029f23	1606	/@{/
mbed_official	324:406fd2029f23	1607	#define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U)
mbed_official	324:406fd2029f23	1608
mbed_official	324:406fd2029f23	1609	#define HW_SIM_SDID(x) ((__I hw_sim_sdid_t ) HW_SIM_SDID_ADDR(x))
mbed_official	324:406fd2029f23	1610	#define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U)
mbed_official	324:406fd2029f23	1611	/@}/
mbed_official	324:406fd2029f23	1612
mbed_official	324:406fd2029f23	1613	/*
mbed_official	324:406fd2029f23	1614	* Constants & macros for individual SIM_SDID bitfields
mbed_official	324:406fd2029f23	1615	*/
mbed_official	324:406fd2029f23	1616
mbed_official	324:406fd2029f23	1617	/*!
mbed_official	324:406fd2029f23	1618	* @name Register SIM_SDID, field PINID[3:0] (RO)
mbed_official	324:406fd2029f23	1619	*
mbed_official	324:406fd2029f23	1620	* Specifies the pincount of the device.
mbed_official	324:406fd2029f23	1621	*
mbed_official	324:406fd2029f23	1622	* Values:
mbed_official	324:406fd2029f23	1623	* - 0000 - Reserved
mbed_official	324:406fd2029f23	1624	* - 0001 - Reserved
mbed_official	324:406fd2029f23	1625	* - 0010 - 32-pin
mbed_official	324:406fd2029f23	1626	* - 0011 - Reserved
mbed_official	324:406fd2029f23	1627	* - 0100 - 48-pin
mbed_official	324:406fd2029f23	1628	* - 0101 - 64-pin
mbed_official	324:406fd2029f23	1629	* - 0110 - 80-pin
mbed_official	324:406fd2029f23	1630	* - 0111 - 81-pin or 121-pin
mbed_official	324:406fd2029f23	1631	* - 1000 - 100-pin
mbed_official	324:406fd2029f23	1632	* - 1001 - 121-pin
mbed_official	324:406fd2029f23	1633	* - 1010 - 144-pin
mbed_official	324:406fd2029f23	1634	* - 1011 - Custom pinout (WLCSP)
mbed_official	324:406fd2029f23	1635	* - 1100 - 169-pin
mbed_official	324:406fd2029f23	1636	* - 1101 - Reserved
mbed_official	324:406fd2029f23	1637	* - 1110 - 256-pin
mbed_official	324:406fd2029f23	1638	* - 1111 - Reserved
mbed_official	324:406fd2029f23	1639	*/
mbed_official	324:406fd2029f23	1640	/@{/
mbed_official	324:406fd2029f23	1641	#define BP_SIM_SDID_PINID (0U) /!< Bit position for SIM_SDID_PINID. /
mbed_official	324:406fd2029f23	1642	#define BM_SIM_SDID_PINID (0x0000000FU) /!< Bit mask for SIM_SDID_PINID. /
mbed_official	324:406fd2029f23	1643	#define BS_SIM_SDID_PINID (4U) /!< Bit field size in bits for SIM_SDID_PINID. /
mbed_official	324:406fd2029f23	1644
mbed_official	324:406fd2029f23	1645	/! @brief Read current value of the SIM_SDID_PINID field. /
mbed_official	324:406fd2029f23	1646	#define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID)
mbed_official	324:406fd2029f23	1647	/@}/
mbed_official	324:406fd2029f23	1648
mbed_official	324:406fd2029f23	1649	/*!
mbed_official	324:406fd2029f23	1650	* @name Register SIM_SDID, field FAMID[6:4] (RO)
mbed_official	324:406fd2029f23	1651	*
mbed_official	324:406fd2029f23	1652	* This field is maintained for compatibility only, but has been superceded by
mbed_official	324:406fd2029f23	1653	* the SERIESID, FAMILYID and SUBFAMID fields in this register.
mbed_official	324:406fd2029f23	1654	*
mbed_official	324:406fd2029f23	1655	* Values:
mbed_official	324:406fd2029f23	1656	* - 000 - K1x Family (without tamper)
mbed_official	324:406fd2029f23	1657	* - 001 - K2x Family (without tamper)
mbed_official	324:406fd2029f23	1658	* - 010 - K3x Family or K1x/K6x Family (with tamper)
mbed_official	324:406fd2029f23	1659	* - 011 - K4x Family or K2x Family (with tamper)
mbed_official	324:406fd2029f23	1660	* - 100 - K6x Family (without tamper)
mbed_official	324:406fd2029f23	1661	* - 101 - K7x Family
mbed_official	324:406fd2029f23	1662	* - 110 - Reserved
mbed_official	324:406fd2029f23	1663	* - 111 - Reserved
mbed_official	324:406fd2029f23	1664	*/
mbed_official	324:406fd2029f23	1665	/@{/
mbed_official	324:406fd2029f23	1666	#define BP_SIM_SDID_FAMID (4U) /!< Bit position for SIM_SDID_FAMID. /
mbed_official	324:406fd2029f23	1667	#define BM_SIM_SDID_FAMID (0x00000070U) /!< Bit mask for SIM_SDID_FAMID. /
mbed_official	324:406fd2029f23	1668	#define BS_SIM_SDID_FAMID (3U) /!< Bit field size in bits for SIM_SDID_FAMID. /
mbed_official	324:406fd2029f23	1669
mbed_official	324:406fd2029f23	1670	/! @brief Read current value of the SIM_SDID_FAMID field. /
mbed_official	324:406fd2029f23	1671	#define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID)
mbed_official	324:406fd2029f23	1672	/@}/
mbed_official	324:406fd2029f23	1673
mbed_official	324:406fd2029f23	1674	/*!
mbed_official	324:406fd2029f23	1675	* @name Register SIM_SDID, field DIEID[11:7] (RO)
mbed_official	324:406fd2029f23	1676	*
mbed_official	324:406fd2029f23	1677	* Specifies the silicon feature set identication number for the device.
mbed_official	324:406fd2029f23	1678	*/
mbed_official	324:406fd2029f23	1679	/@{/
mbed_official	324:406fd2029f23	1680	#define BP_SIM_SDID_DIEID (7U) /!< Bit position for SIM_SDID_DIEID. /
mbed_official	324:406fd2029f23	1681	#define BM_SIM_SDID_DIEID (0x00000F80U) /!< Bit mask for SIM_SDID_DIEID. /
mbed_official	324:406fd2029f23	1682	#define BS_SIM_SDID_DIEID (5U) /!< Bit field size in bits for SIM_SDID_DIEID. /
mbed_official	324:406fd2029f23	1683
mbed_official	324:406fd2029f23	1684	/! @brief Read current value of the SIM_SDID_DIEID field. /
mbed_official	324:406fd2029f23	1685	#define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID)
mbed_official	324:406fd2029f23	1686	/@}/
mbed_official	324:406fd2029f23	1687
mbed_official	324:406fd2029f23	1688	/*!
mbed_official	324:406fd2029f23	1689	* @name Register SIM_SDID, field REVID[15:12] (RO)
mbed_official	324:406fd2029f23	1690	*
mbed_official	324:406fd2029f23	1691	* Specifies the silicon implementation number for the device.
mbed_official	324:406fd2029f23	1692	*/
mbed_official	324:406fd2029f23	1693	/@{/
mbed_official	324:406fd2029f23	1694	#define BP_SIM_SDID_REVID (12U) /!< Bit position for SIM_SDID_REVID. /
mbed_official	324:406fd2029f23	1695	#define BM_SIM_SDID_REVID (0x0000F000U) /!< Bit mask for SIM_SDID_REVID. /
mbed_official	324:406fd2029f23	1696	#define BS_SIM_SDID_REVID (4U) /!< Bit field size in bits for SIM_SDID_REVID. /
mbed_official	324:406fd2029f23	1697
mbed_official	324:406fd2029f23	1698	/! @brief Read current value of the SIM_SDID_REVID field. /
mbed_official	324:406fd2029f23	1699	#define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID)
mbed_official	324:406fd2029f23	1700	/@}/
mbed_official	324:406fd2029f23	1701
mbed_official	324:406fd2029f23	1702	/*!
mbed_official	324:406fd2029f23	1703	* @name Register SIM_SDID, field SERIESID[23:20] (RO)
mbed_official	324:406fd2029f23	1704	*
mbed_official	324:406fd2029f23	1705	* Specifies the Kinetis series of the device.
mbed_official	324:406fd2029f23	1706	*
mbed_official	324:406fd2029f23	1707	* Values:
mbed_official	324:406fd2029f23	1708	* - 0000 - Kinetis K series
mbed_official	324:406fd2029f23	1709	* - 0001 - Kinetis L series
mbed_official	324:406fd2029f23	1710	* - 0101 - Kinetis W series
mbed_official	324:406fd2029f23	1711	* - 0110 - Kinetis V series
mbed_official	324:406fd2029f23	1712	*/
mbed_official	324:406fd2029f23	1713	/@{/
mbed_official	324:406fd2029f23	1714	#define BP_SIM_SDID_SERIESID (20U) /!< Bit position for SIM_SDID_SERIESID. /
mbed_official	324:406fd2029f23	1715	#define BM_SIM_SDID_SERIESID (0x00F00000U) /!< Bit mask for SIM_SDID_SERIESID. /
mbed_official	324:406fd2029f23	1716	#define BS_SIM_SDID_SERIESID (4U) /!< Bit field size in bits for SIM_SDID_SERIESID. /
mbed_official	324:406fd2029f23	1717
mbed_official	324:406fd2029f23	1718	/! @brief Read current value of the SIM_SDID_SERIESID field. /
mbed_official	324:406fd2029f23	1719	#define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID)
mbed_official	324:406fd2029f23	1720	/@}/
mbed_official	324:406fd2029f23	1721
mbed_official	324:406fd2029f23	1722	/*!
mbed_official	324:406fd2029f23	1723	* @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
mbed_official	324:406fd2029f23	1724	*
mbed_official	324:406fd2029f23	1725	* Specifies the Kinetis sub-family of the device.
mbed_official	324:406fd2029f23	1726	*
mbed_official	324:406fd2029f23	1727	* Values:
mbed_official	324:406fd2029f23	1728	* - 0000 - Kx0 Subfamily
mbed_official	324:406fd2029f23	1729	* - 0001 - Kx1 Subfamily (tamper detect)
mbed_official	324:406fd2029f23	1730	* - 0010 - Kx2 Subfamily
mbed_official	324:406fd2029f23	1731	* - 0011 - Kx3 Subfamily (tamper detect)
mbed_official	324:406fd2029f23	1732	* - 0100 - Kx4 Subfamily
mbed_official	324:406fd2029f23	1733	* - 0101 - Kx5 Subfamily (tamper detect)
mbed_official	324:406fd2029f23	1734	* - 0110 - Kx6 Subfamily
mbed_official	324:406fd2029f23	1735	*/
mbed_official	324:406fd2029f23	1736	/@{/
mbed_official	324:406fd2029f23	1737	#define BP_SIM_SDID_SUBFAMID (24U) /!< Bit position for SIM_SDID_SUBFAMID. /
mbed_official	324:406fd2029f23	1738	#define BM_SIM_SDID_SUBFAMID (0x0F000000U) /!< Bit mask for SIM_SDID_SUBFAMID. /
mbed_official	324:406fd2029f23	1739	#define BS_SIM_SDID_SUBFAMID (4U) /!< Bit field size in bits for SIM_SDID_SUBFAMID. /
mbed_official	324:406fd2029f23	1740
mbed_official	324:406fd2029f23	1741	/! @brief Read current value of the SIM_SDID_SUBFAMID field. /
mbed_official	324:406fd2029f23	1742	#define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID)
mbed_official	324:406fd2029f23	1743	/@}/
mbed_official	324:406fd2029f23	1744
mbed_official	324:406fd2029f23	1745	/*!
mbed_official	324:406fd2029f23	1746	* @name Register SIM_SDID, field FAMILYID[31:28] (RO)
mbed_official	324:406fd2029f23	1747	*
mbed_official	324:406fd2029f23	1748	* Specifies the Kinetis family of the device.
mbed_official	324:406fd2029f23	1749	*
mbed_official	324:406fd2029f23	1750	* Values:
mbed_official	324:406fd2029f23	1751	* - 0001 - K1x Family
mbed_official	324:406fd2029f23	1752	* - 0010 - K2x Family
mbed_official	324:406fd2029f23	1753	* - 0011 - K3x Family
mbed_official	324:406fd2029f23	1754	* - 0100 - K4x Family
mbed_official	324:406fd2029f23	1755	* - 0110 - K6x Family
mbed_official	324:406fd2029f23	1756	* - 0111 - K7x Family
mbed_official	324:406fd2029f23	1757	*/
mbed_official	324:406fd2029f23	1758	/@{/
mbed_official	324:406fd2029f23	1759	#define BP_SIM_SDID_FAMILYID (28U) /!< Bit position for SIM_SDID_FAMILYID. /
mbed_official	324:406fd2029f23	1760	#define BM_SIM_SDID_FAMILYID (0xF0000000U) /!< Bit mask for SIM_SDID_FAMILYID. /
mbed_official	324:406fd2029f23	1761	#define BS_SIM_SDID_FAMILYID (4U) /!< Bit field size in bits for SIM_SDID_FAMILYID. /
mbed_official	324:406fd2029f23	1762
mbed_official	324:406fd2029f23	1763	/! @brief Read current value of the SIM_SDID_FAMILYID field. /
mbed_official	324:406fd2029f23	1764	#define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID)
mbed_official	324:406fd2029f23	1765	/@}/
mbed_official	324:406fd2029f23	1766
mbed_official	324:406fd2029f23	1767	/*******************************************************************************
mbed_official	324:406fd2029f23	1768	* HW_SIM_SCGC1 - System Clock Gating Control Register 1
mbed_official	324:406fd2029f23	1769	******************************************************************************/
mbed_official	324:406fd2029f23	1770
mbed_official	324:406fd2029f23	1771	/*!
mbed_official	324:406fd2029f23	1772	* @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
mbed_official	324:406fd2029f23	1773	*
mbed_official	324:406fd2029f23	1774	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1775	*/
mbed_official	324:406fd2029f23	1776	typedef union _hw_sim_scgc1
mbed_official	324:406fd2029f23	1777	{
mbed_official	324:406fd2029f23	1778	uint32_t U;
mbed_official	324:406fd2029f23	1779	struct _hw_sim_scgc1_bitfields
mbed_official	324:406fd2029f23	1780	{
mbed_official	324:406fd2029f23	1781	uint32_t RESERVED0 : 6; /!< [5:0] /
mbed_official	324:406fd2029f23	1782	uint32_t I2C2b : 1; /!< [6] I2C2 Clock Gate Control /
mbed_official	324:406fd2029f23	1783	uint32_t RESERVED1 : 3; /!< [9:7] /
mbed_official	324:406fd2029f23	1784	uint32_t UART4b : 1; /!< [10] UART4 Clock Gate Control /
mbed_official	324:406fd2029f23	1785	uint32_t UART5b : 1; /!< [11] UART5 Clock Gate Control /
mbed_official	324:406fd2029f23	1786	uint32_t RESERVED2 : 20; /!< [31:12] /
mbed_official	324:406fd2029f23	1787	} B;
mbed_official	324:406fd2029f23	1788	} hw_sim_scgc1_t;
mbed_official	324:406fd2029f23	1789
mbed_official	324:406fd2029f23	1790	/*!
mbed_official	324:406fd2029f23	1791	* @name Constants and macros for entire SIM_SCGC1 register
mbed_official	324:406fd2029f23	1792	*/
mbed_official	324:406fd2029f23	1793	/@{/
mbed_official	324:406fd2029f23	1794	#define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U)
mbed_official	324:406fd2029f23	1795
mbed_official	324:406fd2029f23	1796	#define HW_SIM_SCGC1(x) ((__IO hw_sim_scgc1_t ) HW_SIM_SCGC1_ADDR(x))
mbed_official	324:406fd2029f23	1797	#define HW_SIM_SCGC1_RD(x) (HW_SIM_SCGC1(x).U)
mbed_official	324:406fd2029f23	1798	#define HW_SIM_SCGC1_WR(x, v) (HW_SIM_SCGC1(x).U = (v))
mbed_official	324:406fd2029f23	1799	#define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1800	#define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1801	#define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1802	/@}/
mbed_official	324:406fd2029f23	1803
mbed_official	324:406fd2029f23	1804	/*
mbed_official	324:406fd2029f23	1805	* Constants & macros for individual SIM_SCGC1 bitfields
mbed_official	324:406fd2029f23	1806	*/
mbed_official	324:406fd2029f23	1807
mbed_official	324:406fd2029f23	1808	/*!
mbed_official	324:406fd2029f23	1809	* @name Register SIM_SCGC1, field I2C2[6] (RW)
mbed_official	324:406fd2029f23	1810	*
mbed_official	324:406fd2029f23	1811	* This bit controls the clock gate to the I2C2 module.
mbed_official	324:406fd2029f23	1812	*
mbed_official	324:406fd2029f23	1813	* Values:
mbed_official	324:406fd2029f23	1814	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1815	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1816	*/
mbed_official	324:406fd2029f23	1817	/@{/
mbed_official	324:406fd2029f23	1818	#define BP_SIM_SCGC1_I2C2 (6U) /!< Bit position for SIM_SCGC1_I2C2. /
mbed_official	324:406fd2029f23	1819	#define BM_SIM_SCGC1_I2C2 (0x00000040U) /!< Bit mask for SIM_SCGC1_I2C2. /
mbed_official	324:406fd2029f23	1820	#define BS_SIM_SCGC1_I2C2 (1U) /!< Bit field size in bits for SIM_SCGC1_I2C2. /
mbed_official	324:406fd2029f23	1821
mbed_official	324:406fd2029f23	1822	/! @brief Read current value of the SIM_SCGC1_I2C2 field. /
mbed_official	324:406fd2029f23	1823	#define BR_SIM_SCGC1_I2C2(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2))
mbed_official	324:406fd2029f23	1824
mbed_official	324:406fd2029f23	1825	/! @brief Format value for bitfield SIM_SCGC1_I2C2. /
mbed_official	324:406fd2029f23	1826	#define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2)
mbed_official	324:406fd2029f23	1827
mbed_official	324:406fd2029f23	1828	/! @brief Set the I2C2 field to a new value. /
mbed_official	324:406fd2029f23	1829	#define BW_SIM_SCGC1_I2C2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2) = (v))
mbed_official	324:406fd2029f23	1830	/@}/
mbed_official	324:406fd2029f23	1831
mbed_official	324:406fd2029f23	1832	/*!
mbed_official	324:406fd2029f23	1833	* @name Register SIM_SCGC1, field UART4[10] (RW)
mbed_official	324:406fd2029f23	1834	*
mbed_official	324:406fd2029f23	1835	* This bit controls the clock gate to the UART4 module.
mbed_official	324:406fd2029f23	1836	*
mbed_official	324:406fd2029f23	1837	* Values:
mbed_official	324:406fd2029f23	1838	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1839	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1840	*/
mbed_official	324:406fd2029f23	1841	/@{/
mbed_official	324:406fd2029f23	1842	#define BP_SIM_SCGC1_UART4 (10U) /!< Bit position for SIM_SCGC1_UART4. /
mbed_official	324:406fd2029f23	1843	#define BM_SIM_SCGC1_UART4 (0x00000400U) /!< Bit mask for SIM_SCGC1_UART4. /
mbed_official	324:406fd2029f23	1844	#define BS_SIM_SCGC1_UART4 (1U) /!< Bit field size in bits for SIM_SCGC1_UART4. /
mbed_official	324:406fd2029f23	1845
mbed_official	324:406fd2029f23	1846	/! @brief Read current value of the SIM_SCGC1_UART4 field. /
mbed_official	324:406fd2029f23	1847	#define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4))
mbed_official	324:406fd2029f23	1848
mbed_official	324:406fd2029f23	1849	/! @brief Format value for bitfield SIM_SCGC1_UART4. /
mbed_official	324:406fd2029f23	1850	#define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4)
mbed_official	324:406fd2029f23	1851
mbed_official	324:406fd2029f23	1852	/! @brief Set the UART4 field to a new value. /
mbed_official	324:406fd2029f23	1853	#define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v))
mbed_official	324:406fd2029f23	1854	/@}/
mbed_official	324:406fd2029f23	1855
mbed_official	324:406fd2029f23	1856	/*!
mbed_official	324:406fd2029f23	1857	* @name Register SIM_SCGC1, field UART5[11] (RW)
mbed_official	324:406fd2029f23	1858	*
mbed_official	324:406fd2029f23	1859	* This bit controls the clock gate to the UART5 module.
mbed_official	324:406fd2029f23	1860	*
mbed_official	324:406fd2029f23	1861	* Values:
mbed_official	324:406fd2029f23	1862	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1863	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1864	*/
mbed_official	324:406fd2029f23	1865	/@{/
mbed_official	324:406fd2029f23	1866	#define BP_SIM_SCGC1_UART5 (11U) /!< Bit position for SIM_SCGC1_UART5. /
mbed_official	324:406fd2029f23	1867	#define BM_SIM_SCGC1_UART5 (0x00000800U) /!< Bit mask for SIM_SCGC1_UART5. /
mbed_official	324:406fd2029f23	1868	#define BS_SIM_SCGC1_UART5 (1U) /!< Bit field size in bits for SIM_SCGC1_UART5. /
mbed_official	324:406fd2029f23	1869
mbed_official	324:406fd2029f23	1870	/! @brief Read current value of the SIM_SCGC1_UART5 field. /
mbed_official	324:406fd2029f23	1871	#define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5))
mbed_official	324:406fd2029f23	1872
mbed_official	324:406fd2029f23	1873	/! @brief Format value for bitfield SIM_SCGC1_UART5. /
mbed_official	324:406fd2029f23	1874	#define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5)
mbed_official	324:406fd2029f23	1875
mbed_official	324:406fd2029f23	1876	/! @brief Set the UART5 field to a new value. /
mbed_official	324:406fd2029f23	1877	#define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v))
mbed_official	324:406fd2029f23	1878	/@}/
mbed_official	324:406fd2029f23	1879
mbed_official	324:406fd2029f23	1880	/*******************************************************************************
mbed_official	324:406fd2029f23	1881	* HW_SIM_SCGC2 - System Clock Gating Control Register 2
mbed_official	324:406fd2029f23	1882	******************************************************************************/
mbed_official	324:406fd2029f23	1883
mbed_official	324:406fd2029f23	1884	/*!
mbed_official	324:406fd2029f23	1885	* @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
mbed_official	324:406fd2029f23	1886	*
mbed_official	324:406fd2029f23	1887	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1888	*
mbed_official	324:406fd2029f23	1889	* DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
mbed_official	324:406fd2029f23	1890	* AIPS1, define the clock gate control bits in the SCGC2. When accessing through
mbed_official	324:406fd2029f23	1891	* AIPS0, define the clock gate control bits in SCGC6.
mbed_official	324:406fd2029f23	1892	*/
mbed_official	324:406fd2029f23	1893	typedef union _hw_sim_scgc2
mbed_official	324:406fd2029f23	1894	{
mbed_official	324:406fd2029f23	1895	uint32_t U;
mbed_official	324:406fd2029f23	1896	struct _hw_sim_scgc2_bitfields
mbed_official	324:406fd2029f23	1897	{
mbed_official	324:406fd2029f23	1898	uint32_t ENETb : 1; /!< [0] ENET Clock Gate Control /
mbed_official	324:406fd2029f23	1899	uint32_t RESERVED0 : 11; /!< [11:1] /
mbed_official	324:406fd2029f23	1900	uint32_t DAC0b : 1; /!< [12] DAC0 Clock Gate Control /
mbed_official	324:406fd2029f23	1901	uint32_t DAC1b : 1; /!< [13] DAC1 Clock Gate Control /
mbed_official	324:406fd2029f23	1902	uint32_t RESERVED1 : 18; /!< [31:14] /
mbed_official	324:406fd2029f23	1903	} B;
mbed_official	324:406fd2029f23	1904	} hw_sim_scgc2_t;
mbed_official	324:406fd2029f23	1905
mbed_official	324:406fd2029f23	1906	/*!
mbed_official	324:406fd2029f23	1907	* @name Constants and macros for entire SIM_SCGC2 register
mbed_official	324:406fd2029f23	1908	*/
mbed_official	324:406fd2029f23	1909	/@{/
mbed_official	324:406fd2029f23	1910	#define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU)
mbed_official	324:406fd2029f23	1911
mbed_official	324:406fd2029f23	1912	#define HW_SIM_SCGC2(x) ((__IO hw_sim_scgc2_t ) HW_SIM_SCGC2_ADDR(x))
mbed_official	324:406fd2029f23	1913	#define HW_SIM_SCGC2_RD(x) (HW_SIM_SCGC2(x).U)
mbed_official	324:406fd2029f23	1914	#define HW_SIM_SCGC2_WR(x, v) (HW_SIM_SCGC2(x).U = (v))
mbed_official	324:406fd2029f23	1915	#define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1916	#define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1917	#define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1918	/@}/
mbed_official	324:406fd2029f23	1919
mbed_official	324:406fd2029f23	1920	/*
mbed_official	324:406fd2029f23	1921	* Constants & macros for individual SIM_SCGC2 bitfields
mbed_official	324:406fd2029f23	1922	*/
mbed_official	324:406fd2029f23	1923
mbed_official	324:406fd2029f23	1924	/*!
mbed_official	324:406fd2029f23	1925	* @name Register SIM_SCGC2, field ENET[0] (RW)
mbed_official	324:406fd2029f23	1926	*
mbed_official	324:406fd2029f23	1927	* This bit controls the clock gate to the ENET module.
mbed_official	324:406fd2029f23	1928	*
mbed_official	324:406fd2029f23	1929	* Values:
mbed_official	324:406fd2029f23	1930	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1931	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1932	*/
mbed_official	324:406fd2029f23	1933	/@{/
mbed_official	324:406fd2029f23	1934	#define BP_SIM_SCGC2_ENET (0U) /!< Bit position for SIM_SCGC2_ENET. /
mbed_official	324:406fd2029f23	1935	#define BM_SIM_SCGC2_ENET (0x00000001U) /!< Bit mask for SIM_SCGC2_ENET. /
mbed_official	324:406fd2029f23	1936	#define BS_SIM_SCGC2_ENET (1U) /!< Bit field size in bits for SIM_SCGC2_ENET. /
mbed_official	324:406fd2029f23	1937
mbed_official	324:406fd2029f23	1938	/! @brief Read current value of the SIM_SCGC2_ENET field. /
mbed_official	324:406fd2029f23	1939	#define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET))
mbed_official	324:406fd2029f23	1940
mbed_official	324:406fd2029f23	1941	/! @brief Format value for bitfield SIM_SCGC2_ENET. /
mbed_official	324:406fd2029f23	1942	#define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET)
mbed_official	324:406fd2029f23	1943
mbed_official	324:406fd2029f23	1944	/! @brief Set the ENET field to a new value. /
mbed_official	324:406fd2029f23	1945	#define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v))
mbed_official	324:406fd2029f23	1946	/@}/
mbed_official	324:406fd2029f23	1947
mbed_official	324:406fd2029f23	1948	/*!
mbed_official	324:406fd2029f23	1949	* @name Register SIM_SCGC2, field DAC0[12] (RW)
mbed_official	324:406fd2029f23	1950	*
mbed_official	324:406fd2029f23	1951	* This bit controls the clock gate to the DAC0 module.
mbed_official	324:406fd2029f23	1952	*
mbed_official	324:406fd2029f23	1953	* Values:
mbed_official	324:406fd2029f23	1954	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1955	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1956	*/
mbed_official	324:406fd2029f23	1957	/@{/
mbed_official	324:406fd2029f23	1958	#define BP_SIM_SCGC2_DAC0 (12U) /!< Bit position for SIM_SCGC2_DAC0. /
mbed_official	324:406fd2029f23	1959	#define BM_SIM_SCGC2_DAC0 (0x00001000U) /!< Bit mask for SIM_SCGC2_DAC0. /
mbed_official	324:406fd2029f23	1960	#define BS_SIM_SCGC2_DAC0 (1U) /!< Bit field size in bits for SIM_SCGC2_DAC0. /
mbed_official	324:406fd2029f23	1961
mbed_official	324:406fd2029f23	1962	/! @brief Read current value of the SIM_SCGC2_DAC0 field. /
mbed_official	324:406fd2029f23	1963	#define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0))
mbed_official	324:406fd2029f23	1964
mbed_official	324:406fd2029f23	1965	/! @brief Format value for bitfield SIM_SCGC2_DAC0. /
mbed_official	324:406fd2029f23	1966	#define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0)
mbed_official	324:406fd2029f23	1967
mbed_official	324:406fd2029f23	1968	/! @brief Set the DAC0 field to a new value. /
mbed_official	324:406fd2029f23	1969	#define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v))
mbed_official	324:406fd2029f23	1970	/@}/
mbed_official	324:406fd2029f23	1971
mbed_official	324:406fd2029f23	1972	/*!
mbed_official	324:406fd2029f23	1973	* @name Register SIM_SCGC2, field DAC1[13] (RW)
mbed_official	324:406fd2029f23	1974	*
mbed_official	324:406fd2029f23	1975	* This bit controls the clock gate to the DAC1 module.
mbed_official	324:406fd2029f23	1976	*
mbed_official	324:406fd2029f23	1977	* Values:
mbed_official	324:406fd2029f23	1978	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	1979	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	1980	*/
mbed_official	324:406fd2029f23	1981	/@{/
mbed_official	324:406fd2029f23	1982	#define BP_SIM_SCGC2_DAC1 (13U) /!< Bit position for SIM_SCGC2_DAC1. /
mbed_official	324:406fd2029f23	1983	#define BM_SIM_SCGC2_DAC1 (0x00002000U) /!< Bit mask for SIM_SCGC2_DAC1. /
mbed_official	324:406fd2029f23	1984	#define BS_SIM_SCGC2_DAC1 (1U) /!< Bit field size in bits for SIM_SCGC2_DAC1. /
mbed_official	324:406fd2029f23	1985
mbed_official	324:406fd2029f23	1986	/! @brief Read current value of the SIM_SCGC2_DAC1 field. /
mbed_official	324:406fd2029f23	1987	#define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1))
mbed_official	324:406fd2029f23	1988
mbed_official	324:406fd2029f23	1989	/! @brief Format value for bitfield SIM_SCGC2_DAC1. /
mbed_official	324:406fd2029f23	1990	#define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1)
mbed_official	324:406fd2029f23	1991
mbed_official	324:406fd2029f23	1992	/! @brief Set the DAC1 field to a new value. /
mbed_official	324:406fd2029f23	1993	#define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v))
mbed_official	324:406fd2029f23	1994	/@}/
mbed_official	324:406fd2029f23	1995
mbed_official	324:406fd2029f23	1996	/*******************************************************************************
mbed_official	324:406fd2029f23	1997	* HW_SIM_SCGC3 - System Clock Gating Control Register 3
mbed_official	324:406fd2029f23	1998	******************************************************************************/
mbed_official	324:406fd2029f23	1999
mbed_official	324:406fd2029f23	2000	/*!
mbed_official	324:406fd2029f23	2001	* @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
mbed_official	324:406fd2029f23	2002	*
mbed_official	324:406fd2029f23	2003	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2004	*
mbed_official	324:406fd2029f23	2005	* FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
mbed_official	324:406fd2029f23	2006	* through AIPS1, define the clock gate control bits in the SCGC3. When accessing
mbed_official	324:406fd2029f23	2007	* through AIPS0, define the clock gate control bits in SCGC6.
mbed_official	324:406fd2029f23	2008	*/
mbed_official	324:406fd2029f23	2009	typedef union _hw_sim_scgc3
mbed_official	324:406fd2029f23	2010	{
mbed_official	324:406fd2029f23	2011	uint32_t U;
mbed_official	324:406fd2029f23	2012	struct _hw_sim_scgc3_bitfields
mbed_official	324:406fd2029f23	2013	{
mbed_official	324:406fd2029f23	2014	uint32_t RNGA : 1; /!< [0] RNGA Clock Gate Control /
mbed_official	324:406fd2029f23	2015	uint32_t RESERVED0 : 11; /!< [11:1] /
mbed_official	324:406fd2029f23	2016	uint32_t SPI2b : 1; /!< [12] SPI2 Clock Gate Control /
mbed_official	324:406fd2029f23	2017	uint32_t RESERVED1 : 4; /!< [16:13] /
mbed_official	324:406fd2029f23	2018	uint32_t SDHCb : 1; /!< [17] SDHC Clock Gate Control /
mbed_official	324:406fd2029f23	2019	uint32_t RESERVED2 : 6; /!< [23:18] /
mbed_official	324:406fd2029f23	2020	uint32_t FTM2b : 1; /!< [24] FTM2 Clock Gate Control /
mbed_official	324:406fd2029f23	2021	uint32_t FTM3b : 1; /!< [25] FTM3 Clock Gate Control /
mbed_official	324:406fd2029f23	2022	uint32_t RESERVED3 : 1; /!< [26] /
mbed_official	324:406fd2029f23	2023	uint32_t ADC1b : 1; /!< [27] ADC1 Clock Gate Control /
mbed_official	324:406fd2029f23	2024	uint32_t RESERVED4 : 4; /!< [31:28] /
mbed_official	324:406fd2029f23	2025	} B;
mbed_official	324:406fd2029f23	2026	} hw_sim_scgc3_t;
mbed_official	324:406fd2029f23	2027
mbed_official	324:406fd2029f23	2028	/*!
mbed_official	324:406fd2029f23	2029	* @name Constants and macros for entire SIM_SCGC3 register
mbed_official	324:406fd2029f23	2030	*/
mbed_official	324:406fd2029f23	2031	/@{/
mbed_official	324:406fd2029f23	2032	#define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U)
mbed_official	324:406fd2029f23	2033
mbed_official	324:406fd2029f23	2034	#define HW_SIM_SCGC3(x) ((__IO hw_sim_scgc3_t ) HW_SIM_SCGC3_ADDR(x))
mbed_official	324:406fd2029f23	2035	#define HW_SIM_SCGC3_RD(x) (HW_SIM_SCGC3(x).U)
mbed_official	324:406fd2029f23	2036	#define HW_SIM_SCGC3_WR(x, v) (HW_SIM_SCGC3(x).U = (v))
mbed_official	324:406fd2029f23	2037	#define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2038	#define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2039	#define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2040	/@}/
mbed_official	324:406fd2029f23	2041
mbed_official	324:406fd2029f23	2042	/*
mbed_official	324:406fd2029f23	2043	* Constants & macros for individual SIM_SCGC3 bitfields
mbed_official	324:406fd2029f23	2044	*/
mbed_official	324:406fd2029f23	2045
mbed_official	324:406fd2029f23	2046	/*!
mbed_official	324:406fd2029f23	2047	* @name Register SIM_SCGC3, field RNGA[0] (RW)
mbed_official	324:406fd2029f23	2048	*
mbed_official	324:406fd2029f23	2049	* This bit controls the clock gate to the RNGA module.
mbed_official	324:406fd2029f23	2050	*
mbed_official	324:406fd2029f23	2051	* Values:
mbed_official	324:406fd2029f23	2052	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2053	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2054	*/
mbed_official	324:406fd2029f23	2055	/@{/
mbed_official	324:406fd2029f23	2056	#define BP_SIM_SCGC3_RNGA (0U) /!< Bit position for SIM_SCGC3_RNGA. /
mbed_official	324:406fd2029f23	2057	#define BM_SIM_SCGC3_RNGA (0x00000001U) /!< Bit mask for SIM_SCGC3_RNGA. /
mbed_official	324:406fd2029f23	2058	#define BS_SIM_SCGC3_RNGA (1U) /!< Bit field size in bits for SIM_SCGC3_RNGA. /
mbed_official	324:406fd2029f23	2059
mbed_official	324:406fd2029f23	2060	/! @brief Read current value of the SIM_SCGC3_RNGA field. /
mbed_official	324:406fd2029f23	2061	#define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA))
mbed_official	324:406fd2029f23	2062
mbed_official	324:406fd2029f23	2063	/! @brief Format value for bitfield SIM_SCGC3_RNGA. /
mbed_official	324:406fd2029f23	2064	#define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA)
mbed_official	324:406fd2029f23	2065
mbed_official	324:406fd2029f23	2066	/! @brief Set the RNGA field to a new value. /
mbed_official	324:406fd2029f23	2067	#define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v))
mbed_official	324:406fd2029f23	2068	/@}/
mbed_official	324:406fd2029f23	2069
mbed_official	324:406fd2029f23	2070	/*!
mbed_official	324:406fd2029f23	2071	* @name Register SIM_SCGC3, field SPI2[12] (RW)
mbed_official	324:406fd2029f23	2072	*
mbed_official	324:406fd2029f23	2073	* This bit controls the clock gate to the SPI2 module.
mbed_official	324:406fd2029f23	2074	*
mbed_official	324:406fd2029f23	2075	* Values:
mbed_official	324:406fd2029f23	2076	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2077	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2078	*/
mbed_official	324:406fd2029f23	2079	/@{/
mbed_official	324:406fd2029f23	2080	#define BP_SIM_SCGC3_SPI2 (12U) /!< Bit position for SIM_SCGC3_SPI2. /
mbed_official	324:406fd2029f23	2081	#define BM_SIM_SCGC3_SPI2 (0x00001000U) /!< Bit mask for SIM_SCGC3_SPI2. /
mbed_official	324:406fd2029f23	2082	#define BS_SIM_SCGC3_SPI2 (1U) /!< Bit field size in bits for SIM_SCGC3_SPI2. /
mbed_official	324:406fd2029f23	2083
mbed_official	324:406fd2029f23	2084	/! @brief Read current value of the SIM_SCGC3_SPI2 field. /
mbed_official	324:406fd2029f23	2085	#define BR_SIM_SCGC3_SPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2))
mbed_official	324:406fd2029f23	2086
mbed_official	324:406fd2029f23	2087	/! @brief Format value for bitfield SIM_SCGC3_SPI2. /
mbed_official	324:406fd2029f23	2088	#define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2)
mbed_official	324:406fd2029f23	2089
mbed_official	324:406fd2029f23	2090	/! @brief Set the SPI2 field to a new value. /
mbed_official	324:406fd2029f23	2091	#define BW_SIM_SCGC3_SPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2) = (v))
mbed_official	324:406fd2029f23	2092	/@}/
mbed_official	324:406fd2029f23	2093
mbed_official	324:406fd2029f23	2094	/*!
mbed_official	324:406fd2029f23	2095	* @name Register SIM_SCGC3, field SDHC[17] (RW)
mbed_official	324:406fd2029f23	2096	*
mbed_official	324:406fd2029f23	2097	* This bit controls the clock gate to the SDHC module.
mbed_official	324:406fd2029f23	2098	*
mbed_official	324:406fd2029f23	2099	* Values:
mbed_official	324:406fd2029f23	2100	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2101	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2102	*/
mbed_official	324:406fd2029f23	2103	/@{/
mbed_official	324:406fd2029f23	2104	#define BP_SIM_SCGC3_SDHC (17U) /!< Bit position for SIM_SCGC3_SDHC. /
mbed_official	324:406fd2029f23	2105	#define BM_SIM_SCGC3_SDHC (0x00020000U) /!< Bit mask for SIM_SCGC3_SDHC. /
mbed_official	324:406fd2029f23	2106	#define BS_SIM_SCGC3_SDHC (1U) /!< Bit field size in bits for SIM_SCGC3_SDHC. /
mbed_official	324:406fd2029f23	2107
mbed_official	324:406fd2029f23	2108	/! @brief Read current value of the SIM_SCGC3_SDHC field. /
mbed_official	324:406fd2029f23	2109	#define BR_SIM_SCGC3_SDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC))
mbed_official	324:406fd2029f23	2110
mbed_official	324:406fd2029f23	2111	/! @brief Format value for bitfield SIM_SCGC3_SDHC. /
mbed_official	324:406fd2029f23	2112	#define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC)
mbed_official	324:406fd2029f23	2113
mbed_official	324:406fd2029f23	2114	/! @brief Set the SDHC field to a new value. /
mbed_official	324:406fd2029f23	2115	#define BW_SIM_SCGC3_SDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC) = (v))
mbed_official	324:406fd2029f23	2116	/@}/
mbed_official	324:406fd2029f23	2117
mbed_official	324:406fd2029f23	2118	/*!
mbed_official	324:406fd2029f23	2119	* @name Register SIM_SCGC3, field FTM2[24] (RW)
mbed_official	324:406fd2029f23	2120	*
mbed_official	324:406fd2029f23	2121	* This bit controls the clock gate to the FTM2 module.
mbed_official	324:406fd2029f23	2122	*
mbed_official	324:406fd2029f23	2123	* Values:
mbed_official	324:406fd2029f23	2124	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2125	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2126	*/
mbed_official	324:406fd2029f23	2127	/@{/
mbed_official	324:406fd2029f23	2128	#define BP_SIM_SCGC3_FTM2 (24U) /!< Bit position for SIM_SCGC3_FTM2. /
mbed_official	324:406fd2029f23	2129	#define BM_SIM_SCGC3_FTM2 (0x01000000U) /!< Bit mask for SIM_SCGC3_FTM2. /
mbed_official	324:406fd2029f23	2130	#define BS_SIM_SCGC3_FTM2 (1U) /!< Bit field size in bits for SIM_SCGC3_FTM2. /
mbed_official	324:406fd2029f23	2131
mbed_official	324:406fd2029f23	2132	/! @brief Read current value of the SIM_SCGC3_FTM2 field. /
mbed_official	324:406fd2029f23	2133	#define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2))
mbed_official	324:406fd2029f23	2134
mbed_official	324:406fd2029f23	2135	/! @brief Format value for bitfield SIM_SCGC3_FTM2. /
mbed_official	324:406fd2029f23	2136	#define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2)
mbed_official	324:406fd2029f23	2137
mbed_official	324:406fd2029f23	2138	/! @brief Set the FTM2 field to a new value. /
mbed_official	324:406fd2029f23	2139	#define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v))
mbed_official	324:406fd2029f23	2140	/@}/
mbed_official	324:406fd2029f23	2141
mbed_official	324:406fd2029f23	2142	/*!
mbed_official	324:406fd2029f23	2143	* @name Register SIM_SCGC3, field FTM3[25] (RW)
mbed_official	324:406fd2029f23	2144	*
mbed_official	324:406fd2029f23	2145	* This bit controls the clock gate to the FTM3 module.
mbed_official	324:406fd2029f23	2146	*
mbed_official	324:406fd2029f23	2147	* Values:
mbed_official	324:406fd2029f23	2148	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2149	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2150	*/
mbed_official	324:406fd2029f23	2151	/@{/
mbed_official	324:406fd2029f23	2152	#define BP_SIM_SCGC3_FTM3 (25U) /!< Bit position for SIM_SCGC3_FTM3. /
mbed_official	324:406fd2029f23	2153	#define BM_SIM_SCGC3_FTM3 (0x02000000U) /!< Bit mask for SIM_SCGC3_FTM3. /
mbed_official	324:406fd2029f23	2154	#define BS_SIM_SCGC3_FTM3 (1U) /!< Bit field size in bits for SIM_SCGC3_FTM3. /
mbed_official	324:406fd2029f23	2155
mbed_official	324:406fd2029f23	2156	/! @brief Read current value of the SIM_SCGC3_FTM3 field. /
mbed_official	324:406fd2029f23	2157	#define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3))
mbed_official	324:406fd2029f23	2158
mbed_official	324:406fd2029f23	2159	/! @brief Format value for bitfield SIM_SCGC3_FTM3. /
mbed_official	324:406fd2029f23	2160	#define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3)
mbed_official	324:406fd2029f23	2161
mbed_official	324:406fd2029f23	2162	/! @brief Set the FTM3 field to a new value. /
mbed_official	324:406fd2029f23	2163	#define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v))
mbed_official	324:406fd2029f23	2164	/@}/
mbed_official	324:406fd2029f23	2165
mbed_official	324:406fd2029f23	2166	/*!
mbed_official	324:406fd2029f23	2167	* @name Register SIM_SCGC3, field ADC1[27] (RW)
mbed_official	324:406fd2029f23	2168	*
mbed_official	324:406fd2029f23	2169	* This bit controls the clock gate to the ADC1 module.
mbed_official	324:406fd2029f23	2170	*
mbed_official	324:406fd2029f23	2171	* Values:
mbed_official	324:406fd2029f23	2172	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2173	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2174	*/
mbed_official	324:406fd2029f23	2175	/@{/
mbed_official	324:406fd2029f23	2176	#define BP_SIM_SCGC3_ADC1 (27U) /!< Bit position for SIM_SCGC3_ADC1. /
mbed_official	324:406fd2029f23	2177	#define BM_SIM_SCGC3_ADC1 (0x08000000U) /!< Bit mask for SIM_SCGC3_ADC1. /
mbed_official	324:406fd2029f23	2178	#define BS_SIM_SCGC3_ADC1 (1U) /!< Bit field size in bits for SIM_SCGC3_ADC1. /
mbed_official	324:406fd2029f23	2179
mbed_official	324:406fd2029f23	2180	/! @brief Read current value of the SIM_SCGC3_ADC1 field. /
mbed_official	324:406fd2029f23	2181	#define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1))
mbed_official	324:406fd2029f23	2182
mbed_official	324:406fd2029f23	2183	/! @brief Format value for bitfield SIM_SCGC3_ADC1. /
mbed_official	324:406fd2029f23	2184	#define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1)
mbed_official	324:406fd2029f23	2185
mbed_official	324:406fd2029f23	2186	/! @brief Set the ADC1 field to a new value. /
mbed_official	324:406fd2029f23	2187	#define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v))
mbed_official	324:406fd2029f23	2188	/@}/
mbed_official	324:406fd2029f23	2189
mbed_official	324:406fd2029f23	2190	/*******************************************************************************
mbed_official	324:406fd2029f23	2191	* HW_SIM_SCGC4 - System Clock Gating Control Register 4
mbed_official	324:406fd2029f23	2192	******************************************************************************/
mbed_official	324:406fd2029f23	2193
mbed_official	324:406fd2029f23	2194	/*!
mbed_official	324:406fd2029f23	2195	* @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
mbed_official	324:406fd2029f23	2196	*
mbed_official	324:406fd2029f23	2197	* Reset value: 0xF0100030U
mbed_official	324:406fd2029f23	2198	*/
mbed_official	324:406fd2029f23	2199	typedef union _hw_sim_scgc4
mbed_official	324:406fd2029f23	2200	{
mbed_official	324:406fd2029f23	2201	uint32_t U;
mbed_official	324:406fd2029f23	2202	struct _hw_sim_scgc4_bitfields
mbed_official	324:406fd2029f23	2203	{
mbed_official	324:406fd2029f23	2204	uint32_t RESERVED0 : 1; /!< [0] /
mbed_official	324:406fd2029f23	2205	uint32_t EWMb : 1; /!< [1] EWM Clock Gate Control /
mbed_official	324:406fd2029f23	2206	uint32_t CMTb : 1; /!< [2] CMT Clock Gate Control /
mbed_official	324:406fd2029f23	2207	uint32_t RESERVED1 : 3; /!< [5:3] /
mbed_official	324:406fd2029f23	2208	uint32_t I2C0b : 1; /!< [6] I2C0 Clock Gate Control /
mbed_official	324:406fd2029f23	2209	uint32_t I2C1b : 1; /!< [7] I2C1 Clock Gate Control /
mbed_official	324:406fd2029f23	2210	uint32_t RESERVED2 : 2; /!< [9:8] /
mbed_official	324:406fd2029f23	2211	uint32_t UART0b : 1; /!< [10] UART0 Clock Gate Control /
mbed_official	324:406fd2029f23	2212	uint32_t UART1b : 1; /!< [11] UART1 Clock Gate Control /
mbed_official	324:406fd2029f23	2213	uint32_t UART2b : 1; /!< [12] UART2 Clock Gate Control /
mbed_official	324:406fd2029f23	2214	uint32_t UART3b : 1; /!< [13] UART3 Clock Gate Control /
mbed_official	324:406fd2029f23	2215	uint32_t RESERVED3 : 4; /!< [17:14] /
mbed_official	324:406fd2029f23	2216	uint32_t USBOTG : 1; /!< [18] USB Clock Gate Control /
mbed_official	324:406fd2029f23	2217	uint32_t CMP : 1; /!< [19] Comparator Clock Gate Control /
mbed_official	324:406fd2029f23	2218	uint32_t VREFb : 1; /!< [20] VREF Clock Gate Control /
mbed_official	324:406fd2029f23	2219	uint32_t RESERVED4 : 11; /!< [31:21] /
mbed_official	324:406fd2029f23	2220	} B;
mbed_official	324:406fd2029f23	2221	} hw_sim_scgc4_t;
mbed_official	324:406fd2029f23	2222
mbed_official	324:406fd2029f23	2223	/*!
mbed_official	324:406fd2029f23	2224	* @name Constants and macros for entire SIM_SCGC4 register
mbed_official	324:406fd2029f23	2225	*/
mbed_official	324:406fd2029f23	2226	/@{/
mbed_official	324:406fd2029f23	2227	#define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U)
mbed_official	324:406fd2029f23	2228
mbed_official	324:406fd2029f23	2229	#define HW_SIM_SCGC4(x) ((__IO hw_sim_scgc4_t ) HW_SIM_SCGC4_ADDR(x))
mbed_official	324:406fd2029f23	2230	#define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U)
mbed_official	324:406fd2029f23	2231	#define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v))
mbed_official	324:406fd2029f23	2232	#define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2233	#define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2234	#define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2235	/@}/
mbed_official	324:406fd2029f23	2236
mbed_official	324:406fd2029f23	2237	/*
mbed_official	324:406fd2029f23	2238	* Constants & macros for individual SIM_SCGC4 bitfields
mbed_official	324:406fd2029f23	2239	*/
mbed_official	324:406fd2029f23	2240
mbed_official	324:406fd2029f23	2241	/*!
mbed_official	324:406fd2029f23	2242	* @name Register SIM_SCGC4, field EWM[1] (RW)
mbed_official	324:406fd2029f23	2243	*
mbed_official	324:406fd2029f23	2244	* This bit controls the clock gate to the EWM module.
mbed_official	324:406fd2029f23	2245	*
mbed_official	324:406fd2029f23	2246	* Values:
mbed_official	324:406fd2029f23	2247	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2248	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2249	*/
mbed_official	324:406fd2029f23	2250	/@{/
mbed_official	324:406fd2029f23	2251	#define BP_SIM_SCGC4_EWM (1U) /!< Bit position for SIM_SCGC4_EWM. /
mbed_official	324:406fd2029f23	2252	#define BM_SIM_SCGC4_EWM (0x00000002U) /!< Bit mask for SIM_SCGC4_EWM. /
mbed_official	324:406fd2029f23	2253	#define BS_SIM_SCGC4_EWM (1U) /!< Bit field size in bits for SIM_SCGC4_EWM. /
mbed_official	324:406fd2029f23	2254
mbed_official	324:406fd2029f23	2255	/! @brief Read current value of the SIM_SCGC4_EWM field. /
mbed_official	324:406fd2029f23	2256	#define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))
mbed_official	324:406fd2029f23	2257
mbed_official	324:406fd2029f23	2258	/! @brief Format value for bitfield SIM_SCGC4_EWM. /
mbed_official	324:406fd2029f23	2259	#define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM)
mbed_official	324:406fd2029f23	2260
mbed_official	324:406fd2029f23	2261	/! @brief Set the EWM field to a new value. /
mbed_official	324:406fd2029f23	2262	#define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v))
mbed_official	324:406fd2029f23	2263	/@}/
mbed_official	324:406fd2029f23	2264
mbed_official	324:406fd2029f23	2265	/*!
mbed_official	324:406fd2029f23	2266	* @name Register SIM_SCGC4, field CMT[2] (RW)
mbed_official	324:406fd2029f23	2267	*
mbed_official	324:406fd2029f23	2268	* This bit controls the clock gate to the CMT module.
mbed_official	324:406fd2029f23	2269	*
mbed_official	324:406fd2029f23	2270	* Values:
mbed_official	324:406fd2029f23	2271	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2272	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2273	*/
mbed_official	324:406fd2029f23	2274	/@{/
mbed_official	324:406fd2029f23	2275	#define BP_SIM_SCGC4_CMT (2U) /!< Bit position for SIM_SCGC4_CMT. /
mbed_official	324:406fd2029f23	2276	#define BM_SIM_SCGC4_CMT (0x00000004U) /!< Bit mask for SIM_SCGC4_CMT. /
mbed_official	324:406fd2029f23	2277	#define BS_SIM_SCGC4_CMT (1U) /!< Bit field size in bits for SIM_SCGC4_CMT. /
mbed_official	324:406fd2029f23	2278
mbed_official	324:406fd2029f23	2279	/! @brief Read current value of the SIM_SCGC4_CMT field. /
mbed_official	324:406fd2029f23	2280	#define BR_SIM_SCGC4_CMT(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT))
mbed_official	324:406fd2029f23	2281
mbed_official	324:406fd2029f23	2282	/! @brief Format value for bitfield SIM_SCGC4_CMT. /
mbed_official	324:406fd2029f23	2283	#define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT)
mbed_official	324:406fd2029f23	2284
mbed_official	324:406fd2029f23	2285	/! @brief Set the CMT field to a new value. /
mbed_official	324:406fd2029f23	2286	#define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v))
mbed_official	324:406fd2029f23	2287	/@}/
mbed_official	324:406fd2029f23	2288
mbed_official	324:406fd2029f23	2289	/*!
mbed_official	324:406fd2029f23	2290	* @name Register SIM_SCGC4, field I2C0[6] (RW)
mbed_official	324:406fd2029f23	2291	*
mbed_official	324:406fd2029f23	2292	* This bit controls the clock gate to the I 2 C0 module.
mbed_official	324:406fd2029f23	2293	*
mbed_official	324:406fd2029f23	2294	* Values:
mbed_official	324:406fd2029f23	2295	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2296	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2297	*/
mbed_official	324:406fd2029f23	2298	/@{/
mbed_official	324:406fd2029f23	2299	#define BP_SIM_SCGC4_I2C0 (6U) /!< Bit position for SIM_SCGC4_I2C0. /
mbed_official	324:406fd2029f23	2300	#define BM_SIM_SCGC4_I2C0 (0x00000040U) /!< Bit mask for SIM_SCGC4_I2C0. /
mbed_official	324:406fd2029f23	2301	#define BS_SIM_SCGC4_I2C0 (1U) /!< Bit field size in bits for SIM_SCGC4_I2C0. /
mbed_official	324:406fd2029f23	2302
mbed_official	324:406fd2029f23	2303	/! @brief Read current value of the SIM_SCGC4_I2C0 field. /
mbed_official	324:406fd2029f23	2304	#define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0))
mbed_official	324:406fd2029f23	2305
mbed_official	324:406fd2029f23	2306	/! @brief Format value for bitfield SIM_SCGC4_I2C0. /
mbed_official	324:406fd2029f23	2307	#define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0)
mbed_official	324:406fd2029f23	2308
mbed_official	324:406fd2029f23	2309	/! @brief Set the I2C0 field to a new value. /
mbed_official	324:406fd2029f23	2310	#define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v))
mbed_official	324:406fd2029f23	2311	/@}/
mbed_official	324:406fd2029f23	2312
mbed_official	324:406fd2029f23	2313	/*!
mbed_official	324:406fd2029f23	2314	* @name Register SIM_SCGC4, field I2C1[7] (RW)
mbed_official	324:406fd2029f23	2315	*
mbed_official	324:406fd2029f23	2316	* This bit controls the clock gate to the I 2 C1 module.
mbed_official	324:406fd2029f23	2317	*
mbed_official	324:406fd2029f23	2318	* Values:
mbed_official	324:406fd2029f23	2319	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2320	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2321	*/
mbed_official	324:406fd2029f23	2322	/@{/
mbed_official	324:406fd2029f23	2323	#define BP_SIM_SCGC4_I2C1 (7U) /!< Bit position for SIM_SCGC4_I2C1. /
mbed_official	324:406fd2029f23	2324	#define BM_SIM_SCGC4_I2C1 (0x00000080U) /!< Bit mask for SIM_SCGC4_I2C1. /
mbed_official	324:406fd2029f23	2325	#define BS_SIM_SCGC4_I2C1 (1U) /!< Bit field size in bits for SIM_SCGC4_I2C1. /
mbed_official	324:406fd2029f23	2326
mbed_official	324:406fd2029f23	2327	/! @brief Read current value of the SIM_SCGC4_I2C1 field. /
mbed_official	324:406fd2029f23	2328	#define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1))
mbed_official	324:406fd2029f23	2329
mbed_official	324:406fd2029f23	2330	/! @brief Format value for bitfield SIM_SCGC4_I2C1. /
mbed_official	324:406fd2029f23	2331	#define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1)
mbed_official	324:406fd2029f23	2332
mbed_official	324:406fd2029f23	2333	/! @brief Set the I2C1 field to a new value. /
mbed_official	324:406fd2029f23	2334	#define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v))
mbed_official	324:406fd2029f23	2335	/@}/
mbed_official	324:406fd2029f23	2336
mbed_official	324:406fd2029f23	2337	/*!
mbed_official	324:406fd2029f23	2338	* @name Register SIM_SCGC4, field UART0[10] (RW)
mbed_official	324:406fd2029f23	2339	*
mbed_official	324:406fd2029f23	2340	* This bit controls the clock gate to the UART0 module.
mbed_official	324:406fd2029f23	2341	*
mbed_official	324:406fd2029f23	2342	* Values:
mbed_official	324:406fd2029f23	2343	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2344	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2345	*/
mbed_official	324:406fd2029f23	2346	/@{/
mbed_official	324:406fd2029f23	2347	#define BP_SIM_SCGC4_UART0 (10U) /!< Bit position for SIM_SCGC4_UART0. /
mbed_official	324:406fd2029f23	2348	#define BM_SIM_SCGC4_UART0 (0x00000400U) /!< Bit mask for SIM_SCGC4_UART0. /
mbed_official	324:406fd2029f23	2349	#define BS_SIM_SCGC4_UART0 (1U) /!< Bit field size in bits for SIM_SCGC4_UART0. /
mbed_official	324:406fd2029f23	2350
mbed_official	324:406fd2029f23	2351	/! @brief Read current value of the SIM_SCGC4_UART0 field. /
mbed_official	324:406fd2029f23	2352	#define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))
mbed_official	324:406fd2029f23	2353
mbed_official	324:406fd2029f23	2354	/! @brief Format value for bitfield SIM_SCGC4_UART0. /
mbed_official	324:406fd2029f23	2355	#define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0)
mbed_official	324:406fd2029f23	2356
mbed_official	324:406fd2029f23	2357	/! @brief Set the UART0 field to a new value. /
mbed_official	324:406fd2029f23	2358	#define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v))
mbed_official	324:406fd2029f23	2359	/@}/
mbed_official	324:406fd2029f23	2360
mbed_official	324:406fd2029f23	2361	/*!
mbed_official	324:406fd2029f23	2362	* @name Register SIM_SCGC4, field UART1[11] (RW)
mbed_official	324:406fd2029f23	2363	*
mbed_official	324:406fd2029f23	2364	* This bit controls the clock gate to the UART1 module.
mbed_official	324:406fd2029f23	2365	*
mbed_official	324:406fd2029f23	2366	* Values:
mbed_official	324:406fd2029f23	2367	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2368	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2369	*/
mbed_official	324:406fd2029f23	2370	/@{/
mbed_official	324:406fd2029f23	2371	#define BP_SIM_SCGC4_UART1 (11U) /!< Bit position for SIM_SCGC4_UART1. /
mbed_official	324:406fd2029f23	2372	#define BM_SIM_SCGC4_UART1 (0x00000800U) /!< Bit mask for SIM_SCGC4_UART1. /
mbed_official	324:406fd2029f23	2373	#define BS_SIM_SCGC4_UART1 (1U) /!< Bit field size in bits for SIM_SCGC4_UART1. /
mbed_official	324:406fd2029f23	2374
mbed_official	324:406fd2029f23	2375	/! @brief Read current value of the SIM_SCGC4_UART1 field. /
mbed_official	324:406fd2029f23	2376	#define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))
mbed_official	324:406fd2029f23	2377
mbed_official	324:406fd2029f23	2378	/! @brief Format value for bitfield SIM_SCGC4_UART1. /
mbed_official	324:406fd2029f23	2379	#define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1)
mbed_official	324:406fd2029f23	2380
mbed_official	324:406fd2029f23	2381	/! @brief Set the UART1 field to a new value. /
mbed_official	324:406fd2029f23	2382	#define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v))
mbed_official	324:406fd2029f23	2383	/@}/
mbed_official	324:406fd2029f23	2384
mbed_official	324:406fd2029f23	2385	/*!
mbed_official	324:406fd2029f23	2386	* @name Register SIM_SCGC4, field UART2[12] (RW)
mbed_official	324:406fd2029f23	2387	*
mbed_official	324:406fd2029f23	2388	* This bit controls the clock gate to the UART2 module.
mbed_official	324:406fd2029f23	2389	*
mbed_official	324:406fd2029f23	2390	* Values:
mbed_official	324:406fd2029f23	2391	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2392	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2393	*/
mbed_official	324:406fd2029f23	2394	/@{/
mbed_official	324:406fd2029f23	2395	#define BP_SIM_SCGC4_UART2 (12U) /!< Bit position for SIM_SCGC4_UART2. /
mbed_official	324:406fd2029f23	2396	#define BM_SIM_SCGC4_UART2 (0x00001000U) /!< Bit mask for SIM_SCGC4_UART2. /
mbed_official	324:406fd2029f23	2397	#define BS_SIM_SCGC4_UART2 (1U) /!< Bit field size in bits for SIM_SCGC4_UART2. /
mbed_official	324:406fd2029f23	2398
mbed_official	324:406fd2029f23	2399	/! @brief Read current value of the SIM_SCGC4_UART2 field. /
mbed_official	324:406fd2029f23	2400	#define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))
mbed_official	324:406fd2029f23	2401
mbed_official	324:406fd2029f23	2402	/! @brief Format value for bitfield SIM_SCGC4_UART2. /
mbed_official	324:406fd2029f23	2403	#define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2)
mbed_official	324:406fd2029f23	2404
mbed_official	324:406fd2029f23	2405	/! @brief Set the UART2 field to a new value. /
mbed_official	324:406fd2029f23	2406	#define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v))
mbed_official	324:406fd2029f23	2407	/@}/
mbed_official	324:406fd2029f23	2408
mbed_official	324:406fd2029f23	2409	/*!
mbed_official	324:406fd2029f23	2410	* @name Register SIM_SCGC4, field UART3[13] (RW)
mbed_official	324:406fd2029f23	2411	*
mbed_official	324:406fd2029f23	2412	* This bit controls the clock gate to the UART3 module.
mbed_official	324:406fd2029f23	2413	*
mbed_official	324:406fd2029f23	2414	* Values:
mbed_official	324:406fd2029f23	2415	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2416	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2417	*/
mbed_official	324:406fd2029f23	2418	/@{/
mbed_official	324:406fd2029f23	2419	#define BP_SIM_SCGC4_UART3 (13U) /!< Bit position for SIM_SCGC4_UART3. /
mbed_official	324:406fd2029f23	2420	#define BM_SIM_SCGC4_UART3 (0x00002000U) /!< Bit mask for SIM_SCGC4_UART3. /
mbed_official	324:406fd2029f23	2421	#define BS_SIM_SCGC4_UART3 (1U) /!< Bit field size in bits for SIM_SCGC4_UART3. /
mbed_official	324:406fd2029f23	2422
mbed_official	324:406fd2029f23	2423	/! @brief Read current value of the SIM_SCGC4_UART3 field. /
mbed_official	324:406fd2029f23	2424	#define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3))
mbed_official	324:406fd2029f23	2425
mbed_official	324:406fd2029f23	2426	/! @brief Format value for bitfield SIM_SCGC4_UART3. /
mbed_official	324:406fd2029f23	2427	#define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3)
mbed_official	324:406fd2029f23	2428
mbed_official	324:406fd2029f23	2429	/! @brief Set the UART3 field to a new value. /
mbed_official	324:406fd2029f23	2430	#define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v))
mbed_official	324:406fd2029f23	2431	/@}/
mbed_official	324:406fd2029f23	2432
mbed_official	324:406fd2029f23	2433	/*!
mbed_official	324:406fd2029f23	2434	* @name Register SIM_SCGC4, field USBOTG[18] (RW)
mbed_official	324:406fd2029f23	2435	*
mbed_official	324:406fd2029f23	2436	* This bit controls the clock gate to the USB module.
mbed_official	324:406fd2029f23	2437	*
mbed_official	324:406fd2029f23	2438	* Values:
mbed_official	324:406fd2029f23	2439	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2440	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2441	*/
mbed_official	324:406fd2029f23	2442	/@{/
mbed_official	324:406fd2029f23	2443	#define BP_SIM_SCGC4_USBOTG (18U) /!< Bit position for SIM_SCGC4_USBOTG. /
mbed_official	324:406fd2029f23	2444	#define BM_SIM_SCGC4_USBOTG (0x00040000U) /!< Bit mask for SIM_SCGC4_USBOTG. /
mbed_official	324:406fd2029f23	2445	#define BS_SIM_SCGC4_USBOTG (1U) /!< Bit field size in bits for SIM_SCGC4_USBOTG. /
mbed_official	324:406fd2029f23	2446
mbed_official	324:406fd2029f23	2447	/! @brief Read current value of the SIM_SCGC4_USBOTG field. /
mbed_official	324:406fd2029f23	2448	#define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG))
mbed_official	324:406fd2029f23	2449
mbed_official	324:406fd2029f23	2450	/! @brief Format value for bitfield SIM_SCGC4_USBOTG. /
mbed_official	324:406fd2029f23	2451	#define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG)
mbed_official	324:406fd2029f23	2452
mbed_official	324:406fd2029f23	2453	/! @brief Set the USBOTG field to a new value. /
mbed_official	324:406fd2029f23	2454	#define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v))
mbed_official	324:406fd2029f23	2455	/@}/
mbed_official	324:406fd2029f23	2456
mbed_official	324:406fd2029f23	2457	/*!
mbed_official	324:406fd2029f23	2458	* @name Register SIM_SCGC4, field CMP[19] (RW)
mbed_official	324:406fd2029f23	2459	*
mbed_official	324:406fd2029f23	2460	* This bit controls the clock gate to the comparator module.
mbed_official	324:406fd2029f23	2461	*
mbed_official	324:406fd2029f23	2462	* Values:
mbed_official	324:406fd2029f23	2463	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2464	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2465	*/
mbed_official	324:406fd2029f23	2466	/@{/
mbed_official	324:406fd2029f23	2467	#define BP_SIM_SCGC4_CMP (19U) /!< Bit position for SIM_SCGC4_CMP. /
mbed_official	324:406fd2029f23	2468	#define BM_SIM_SCGC4_CMP (0x00080000U) /!< Bit mask for SIM_SCGC4_CMP. /
mbed_official	324:406fd2029f23	2469	#define BS_SIM_SCGC4_CMP (1U) /!< Bit field size in bits for SIM_SCGC4_CMP. /
mbed_official	324:406fd2029f23	2470
mbed_official	324:406fd2029f23	2471	/! @brief Read current value of the SIM_SCGC4_CMP field. /
mbed_official	324:406fd2029f23	2472	#define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))
mbed_official	324:406fd2029f23	2473
mbed_official	324:406fd2029f23	2474	/! @brief Format value for bitfield SIM_SCGC4_CMP. /
mbed_official	324:406fd2029f23	2475	#define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP)
mbed_official	324:406fd2029f23	2476
mbed_official	324:406fd2029f23	2477	/! @brief Set the CMP field to a new value. /
mbed_official	324:406fd2029f23	2478	#define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v))
mbed_official	324:406fd2029f23	2479	/@}/
mbed_official	324:406fd2029f23	2480
mbed_official	324:406fd2029f23	2481	/*!
mbed_official	324:406fd2029f23	2482	* @name Register SIM_SCGC4, field VREF[20] (RW)
mbed_official	324:406fd2029f23	2483	*
mbed_official	324:406fd2029f23	2484	* This bit controls the clock gate to the VREF module.
mbed_official	324:406fd2029f23	2485	*
mbed_official	324:406fd2029f23	2486	* Values:
mbed_official	324:406fd2029f23	2487	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2488	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2489	*/
mbed_official	324:406fd2029f23	2490	/@{/
mbed_official	324:406fd2029f23	2491	#define BP_SIM_SCGC4_VREF (20U) /!< Bit position for SIM_SCGC4_VREF. /
mbed_official	324:406fd2029f23	2492	#define BM_SIM_SCGC4_VREF (0x00100000U) /!< Bit mask for SIM_SCGC4_VREF. /
mbed_official	324:406fd2029f23	2493	#define BS_SIM_SCGC4_VREF (1U) /!< Bit field size in bits for SIM_SCGC4_VREF. /
mbed_official	324:406fd2029f23	2494
mbed_official	324:406fd2029f23	2495	/! @brief Read current value of the SIM_SCGC4_VREF field. /
mbed_official	324:406fd2029f23	2496	#define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))
mbed_official	324:406fd2029f23	2497
mbed_official	324:406fd2029f23	2498	/! @brief Format value for bitfield SIM_SCGC4_VREF. /
mbed_official	324:406fd2029f23	2499	#define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF)
mbed_official	324:406fd2029f23	2500
mbed_official	324:406fd2029f23	2501	/! @brief Set the VREF field to a new value. /
mbed_official	324:406fd2029f23	2502	#define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v))
mbed_official	324:406fd2029f23	2503	/@}/
mbed_official	324:406fd2029f23	2504
mbed_official	324:406fd2029f23	2505	/*******************************************************************************
mbed_official	324:406fd2029f23	2506	* HW_SIM_SCGC5 - System Clock Gating Control Register 5
mbed_official	324:406fd2029f23	2507	******************************************************************************/
mbed_official	324:406fd2029f23	2508
mbed_official	324:406fd2029f23	2509	/*!
mbed_official	324:406fd2029f23	2510	* @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
mbed_official	324:406fd2029f23	2511	*
mbed_official	324:406fd2029f23	2512	* Reset value: 0x00040182U
mbed_official	324:406fd2029f23	2513	*/
mbed_official	324:406fd2029f23	2514	typedef union _hw_sim_scgc5
mbed_official	324:406fd2029f23	2515	{
mbed_official	324:406fd2029f23	2516	uint32_t U;
mbed_official	324:406fd2029f23	2517	struct _hw_sim_scgc5_bitfields
mbed_official	324:406fd2029f23	2518	{
mbed_official	324:406fd2029f23	2519	uint32_t LPTMR : 1; /!< [0] Low Power Timer Access Control /
mbed_official	324:406fd2029f23	2520	uint32_t RESERVED0 : 8; /!< [8:1] /
mbed_official	324:406fd2029f23	2521	uint32_t PORTAb : 1; /!< [9] Port A Clock Gate Control /
mbed_official	324:406fd2029f23	2522	uint32_t PORTBb : 1; /!< [10] Port B Clock Gate Control /
mbed_official	324:406fd2029f23	2523	uint32_t PORTCb : 1; /!< [11] Port C Clock Gate Control /
mbed_official	324:406fd2029f23	2524	uint32_t PORTDb : 1; /!< [12] Port D Clock Gate Control /
mbed_official	324:406fd2029f23	2525	uint32_t PORTEb : 1; /!< [13] Port E Clock Gate Control /
mbed_official	324:406fd2029f23	2526	uint32_t RESERVED1 : 18; /!< [31:14] /
mbed_official	324:406fd2029f23	2527	} B;
mbed_official	324:406fd2029f23	2528	} hw_sim_scgc5_t;
mbed_official	324:406fd2029f23	2529
mbed_official	324:406fd2029f23	2530	/*!
mbed_official	324:406fd2029f23	2531	* @name Constants and macros for entire SIM_SCGC5 register
mbed_official	324:406fd2029f23	2532	*/
mbed_official	324:406fd2029f23	2533	/@{/
mbed_official	324:406fd2029f23	2534	#define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U)
mbed_official	324:406fd2029f23	2535
mbed_official	324:406fd2029f23	2536	#define HW_SIM_SCGC5(x) ((__IO hw_sim_scgc5_t ) HW_SIM_SCGC5_ADDR(x))
mbed_official	324:406fd2029f23	2537	#define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U)
mbed_official	324:406fd2029f23	2538	#define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v))
mbed_official	324:406fd2029f23	2539	#define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2540	#define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2541	#define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2542	/@}/
mbed_official	324:406fd2029f23	2543
mbed_official	324:406fd2029f23	2544	/*
mbed_official	324:406fd2029f23	2545	* Constants & macros for individual SIM_SCGC5 bitfields
mbed_official	324:406fd2029f23	2546	*/
mbed_official	324:406fd2029f23	2547
mbed_official	324:406fd2029f23	2548	/*!
mbed_official	324:406fd2029f23	2549	* @name Register SIM_SCGC5, field LPTMR[0] (RW)
mbed_official	324:406fd2029f23	2550	*
mbed_official	324:406fd2029f23	2551	* This bit controls software access to the Low Power Timer module.
mbed_official	324:406fd2029f23	2552	*
mbed_official	324:406fd2029f23	2553	* Values:
mbed_official	324:406fd2029f23	2554	* - 0 - Access disabled
mbed_official	324:406fd2029f23	2555	* - 1 - Access enabled
mbed_official	324:406fd2029f23	2556	*/
mbed_official	324:406fd2029f23	2557	/@{/
mbed_official	324:406fd2029f23	2558	#define BP_SIM_SCGC5_LPTMR (0U) /!< Bit position for SIM_SCGC5_LPTMR. /
mbed_official	324:406fd2029f23	2559	#define BM_SIM_SCGC5_LPTMR (0x00000001U) /!< Bit mask for SIM_SCGC5_LPTMR. /
mbed_official	324:406fd2029f23	2560	#define BS_SIM_SCGC5_LPTMR (1U) /!< Bit field size in bits for SIM_SCGC5_LPTMR. /
mbed_official	324:406fd2029f23	2561
mbed_official	324:406fd2029f23	2562	/! @brief Read current value of the SIM_SCGC5_LPTMR field. /
mbed_official	324:406fd2029f23	2563	#define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR))
mbed_official	324:406fd2029f23	2564
mbed_official	324:406fd2029f23	2565	/! @brief Format value for bitfield SIM_SCGC5_LPTMR. /
mbed_official	324:406fd2029f23	2566	#define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR)
mbed_official	324:406fd2029f23	2567
mbed_official	324:406fd2029f23	2568	/! @brief Set the LPTMR field to a new value. /
mbed_official	324:406fd2029f23	2569	#define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v))
mbed_official	324:406fd2029f23	2570	/@}/
mbed_official	324:406fd2029f23	2571
mbed_official	324:406fd2029f23	2572	/*!
mbed_official	324:406fd2029f23	2573	* @name Register SIM_SCGC5, field PORTA[9] (RW)
mbed_official	324:406fd2029f23	2574	*
mbed_official	324:406fd2029f23	2575	* This bit controls the clock gate to the Port A module.
mbed_official	324:406fd2029f23	2576	*
mbed_official	324:406fd2029f23	2577	* Values:
mbed_official	324:406fd2029f23	2578	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2579	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2580	*/
mbed_official	324:406fd2029f23	2581	/@{/
mbed_official	324:406fd2029f23	2582	#define BP_SIM_SCGC5_PORTA (9U) /!< Bit position for SIM_SCGC5_PORTA. /
mbed_official	324:406fd2029f23	2583	#define BM_SIM_SCGC5_PORTA (0x00000200U) /!< Bit mask for SIM_SCGC5_PORTA. /
mbed_official	324:406fd2029f23	2584	#define BS_SIM_SCGC5_PORTA (1U) /!< Bit field size in bits for SIM_SCGC5_PORTA. /
mbed_official	324:406fd2029f23	2585
mbed_official	324:406fd2029f23	2586	/! @brief Read current value of the SIM_SCGC5_PORTA field. /
mbed_official	324:406fd2029f23	2587	#define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))
mbed_official	324:406fd2029f23	2588
mbed_official	324:406fd2029f23	2589	/! @brief Format value for bitfield SIM_SCGC5_PORTA. /
mbed_official	324:406fd2029f23	2590	#define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA)
mbed_official	324:406fd2029f23	2591
mbed_official	324:406fd2029f23	2592	/! @brief Set the PORTA field to a new value. /
mbed_official	324:406fd2029f23	2593	#define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v))
mbed_official	324:406fd2029f23	2594	/@}/
mbed_official	324:406fd2029f23	2595
mbed_official	324:406fd2029f23	2596	/*!
mbed_official	324:406fd2029f23	2597	* @name Register SIM_SCGC5, field PORTB[10] (RW)
mbed_official	324:406fd2029f23	2598	*
mbed_official	324:406fd2029f23	2599	* This bit controls the clock gate to the Port B module.
mbed_official	324:406fd2029f23	2600	*
mbed_official	324:406fd2029f23	2601	* Values:
mbed_official	324:406fd2029f23	2602	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2603	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2604	*/
mbed_official	324:406fd2029f23	2605	/@{/
mbed_official	324:406fd2029f23	2606	#define BP_SIM_SCGC5_PORTB (10U) /!< Bit position for SIM_SCGC5_PORTB. /
mbed_official	324:406fd2029f23	2607	#define BM_SIM_SCGC5_PORTB (0x00000400U) /!< Bit mask for SIM_SCGC5_PORTB. /
mbed_official	324:406fd2029f23	2608	#define BS_SIM_SCGC5_PORTB (1U) /!< Bit field size in bits for SIM_SCGC5_PORTB. /
mbed_official	324:406fd2029f23	2609
mbed_official	324:406fd2029f23	2610	/! @brief Read current value of the SIM_SCGC5_PORTB field. /
mbed_official	324:406fd2029f23	2611	#define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))
mbed_official	324:406fd2029f23	2612
mbed_official	324:406fd2029f23	2613	/! @brief Format value for bitfield SIM_SCGC5_PORTB. /
mbed_official	324:406fd2029f23	2614	#define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB)
mbed_official	324:406fd2029f23	2615
mbed_official	324:406fd2029f23	2616	/! @brief Set the PORTB field to a new value. /
mbed_official	324:406fd2029f23	2617	#define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v))
mbed_official	324:406fd2029f23	2618	/@}/
mbed_official	324:406fd2029f23	2619
mbed_official	324:406fd2029f23	2620	/*!
mbed_official	324:406fd2029f23	2621	* @name Register SIM_SCGC5, field PORTC[11] (RW)
mbed_official	324:406fd2029f23	2622	*
mbed_official	324:406fd2029f23	2623	* This bit controls the clock gate to the Port C module.
mbed_official	324:406fd2029f23	2624	*
mbed_official	324:406fd2029f23	2625	* Values:
mbed_official	324:406fd2029f23	2626	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2627	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2628	*/
mbed_official	324:406fd2029f23	2629	/@{/
mbed_official	324:406fd2029f23	2630	#define BP_SIM_SCGC5_PORTC (11U) /!< Bit position for SIM_SCGC5_PORTC. /
mbed_official	324:406fd2029f23	2631	#define BM_SIM_SCGC5_PORTC (0x00000800U) /!< Bit mask for SIM_SCGC5_PORTC. /
mbed_official	324:406fd2029f23	2632	#define BS_SIM_SCGC5_PORTC (1U) /!< Bit field size in bits for SIM_SCGC5_PORTC. /
mbed_official	324:406fd2029f23	2633
mbed_official	324:406fd2029f23	2634	/! @brief Read current value of the SIM_SCGC5_PORTC field. /
mbed_official	324:406fd2029f23	2635	#define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))
mbed_official	324:406fd2029f23	2636
mbed_official	324:406fd2029f23	2637	/! @brief Format value for bitfield SIM_SCGC5_PORTC. /
mbed_official	324:406fd2029f23	2638	#define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC)
mbed_official	324:406fd2029f23	2639
mbed_official	324:406fd2029f23	2640	/! @brief Set the PORTC field to a new value. /
mbed_official	324:406fd2029f23	2641	#define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v))
mbed_official	324:406fd2029f23	2642	/@}/
mbed_official	324:406fd2029f23	2643
mbed_official	324:406fd2029f23	2644	/*!
mbed_official	324:406fd2029f23	2645	* @name Register SIM_SCGC5, field PORTD[12] (RW)
mbed_official	324:406fd2029f23	2646	*
mbed_official	324:406fd2029f23	2647	* This bit controls the clock gate to the Port D module.
mbed_official	324:406fd2029f23	2648	*
mbed_official	324:406fd2029f23	2649	* Values:
mbed_official	324:406fd2029f23	2650	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2651	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2652	*/
mbed_official	324:406fd2029f23	2653	/@{/
mbed_official	324:406fd2029f23	2654	#define BP_SIM_SCGC5_PORTD (12U) /!< Bit position for SIM_SCGC5_PORTD. /
mbed_official	324:406fd2029f23	2655	#define BM_SIM_SCGC5_PORTD (0x00001000U) /!< Bit mask for SIM_SCGC5_PORTD. /
mbed_official	324:406fd2029f23	2656	#define BS_SIM_SCGC5_PORTD (1U) /!< Bit field size in bits for SIM_SCGC5_PORTD. /
mbed_official	324:406fd2029f23	2657
mbed_official	324:406fd2029f23	2658	/! @brief Read current value of the SIM_SCGC5_PORTD field. /
mbed_official	324:406fd2029f23	2659	#define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))
mbed_official	324:406fd2029f23	2660
mbed_official	324:406fd2029f23	2661	/! @brief Format value for bitfield SIM_SCGC5_PORTD. /
mbed_official	324:406fd2029f23	2662	#define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD)
mbed_official	324:406fd2029f23	2663
mbed_official	324:406fd2029f23	2664	/! @brief Set the PORTD field to a new value. /
mbed_official	324:406fd2029f23	2665	#define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v))
mbed_official	324:406fd2029f23	2666	/@}/
mbed_official	324:406fd2029f23	2667
mbed_official	324:406fd2029f23	2668	/*!
mbed_official	324:406fd2029f23	2669	* @name Register SIM_SCGC5, field PORTE[13] (RW)
mbed_official	324:406fd2029f23	2670	*
mbed_official	324:406fd2029f23	2671	* This bit controls the clock gate to the Port E module.
mbed_official	324:406fd2029f23	2672	*
mbed_official	324:406fd2029f23	2673	* Values:
mbed_official	324:406fd2029f23	2674	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2675	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2676	*/
mbed_official	324:406fd2029f23	2677	/@{/
mbed_official	324:406fd2029f23	2678	#define BP_SIM_SCGC5_PORTE (13U) /!< Bit position for SIM_SCGC5_PORTE. /
mbed_official	324:406fd2029f23	2679	#define BM_SIM_SCGC5_PORTE (0x00002000U) /!< Bit mask for SIM_SCGC5_PORTE. /
mbed_official	324:406fd2029f23	2680	#define BS_SIM_SCGC5_PORTE (1U) /!< Bit field size in bits for SIM_SCGC5_PORTE. /
mbed_official	324:406fd2029f23	2681
mbed_official	324:406fd2029f23	2682	/! @brief Read current value of the SIM_SCGC5_PORTE field. /
mbed_official	324:406fd2029f23	2683	#define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))
mbed_official	324:406fd2029f23	2684
mbed_official	324:406fd2029f23	2685	/! @brief Format value for bitfield SIM_SCGC5_PORTE. /
mbed_official	324:406fd2029f23	2686	#define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE)
mbed_official	324:406fd2029f23	2687
mbed_official	324:406fd2029f23	2688	/! @brief Set the PORTE field to a new value. /
mbed_official	324:406fd2029f23	2689	#define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v))
mbed_official	324:406fd2029f23	2690	/@}/
mbed_official	324:406fd2029f23	2691
mbed_official	324:406fd2029f23	2692	/*******************************************************************************
mbed_official	324:406fd2029f23	2693	* HW_SIM_SCGC6 - System Clock Gating Control Register 6
mbed_official	324:406fd2029f23	2694	******************************************************************************/
mbed_official	324:406fd2029f23	2695
mbed_official	324:406fd2029f23	2696	/*!
mbed_official	324:406fd2029f23	2697	* @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
mbed_official	324:406fd2029f23	2698	*
mbed_official	324:406fd2029f23	2699	* Reset value: 0x40000001U
mbed_official	324:406fd2029f23	2700	*
mbed_official	324:406fd2029f23	2701	* DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
mbed_official	324:406fd2029f23	2702	* accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
mbed_official	324:406fd2029f23	2703	* When accessing through AIPS0, define the clock gate control bits in SCGC6.
mbed_official	324:406fd2029f23	2704	*/
mbed_official	324:406fd2029f23	2705	typedef union _hw_sim_scgc6
mbed_official	324:406fd2029f23	2706	{
mbed_official	324:406fd2029f23	2707	uint32_t U;
mbed_official	324:406fd2029f23	2708	struct _hw_sim_scgc6_bitfields
mbed_official	324:406fd2029f23	2709	{
mbed_official	324:406fd2029f23	2710	uint32_t FTF : 1; /!< [0] Flash Memory Clock Gate Control /
mbed_official	324:406fd2029f23	2711	uint32_t DMAMUXb : 1; /!< [1] DMA Mux Clock Gate Control /
mbed_official	324:406fd2029f23	2712	uint32_t RESERVED0 : 2; /!< [3:2] /
mbed_official	324:406fd2029f23	2713	uint32_t FLEXCAN0 : 1; /!< [4] FlexCAN0 Clock Gate Control /
mbed_official	324:406fd2029f23	2714	uint32_t RESERVED1 : 4; /!< [8:5] /
mbed_official	324:406fd2029f23	2715	uint32_t RNGA : 1; /!< [9] RNGA Clock Gate Control /
mbed_official	324:406fd2029f23	2716	uint32_t RESERVED2 : 2; /!< [11:10] /
mbed_official	324:406fd2029f23	2717	uint32_t SPI0b : 1; /!< [12] SPI0 Clock Gate Control /
mbed_official	324:406fd2029f23	2718	uint32_t SPI1b : 1; /!< [13] SPI1 Clock Gate Control /
mbed_official	324:406fd2029f23	2719	uint32_t RESERVED3 : 1; /!< [14] /
mbed_official	324:406fd2029f23	2720	uint32_t I2S : 1; /!< [15] I2S Clock Gate Control /
mbed_official	324:406fd2029f23	2721	uint32_t RESERVED4 : 2; /!< [17:16] /
mbed_official	324:406fd2029f23	2722	uint32_t CRC : 1; /!< [18] CRC Clock Gate Control /
mbed_official	324:406fd2029f23	2723	uint32_t RESERVED5 : 2; /!< [20:19] /
mbed_official	324:406fd2029f23	2724	uint32_t USBDCDb : 1; /!< [21] USB DCD Clock Gate Control /
mbed_official	324:406fd2029f23	2725	uint32_t PDB : 1; /!< [22] PDB Clock Gate Control /
mbed_official	324:406fd2029f23	2726	uint32_t PITb : 1; /!< [23] PIT Clock Gate Control /
mbed_official	324:406fd2029f23	2727	uint32_t FTM0b : 1; /!< [24] FTM0 Clock Gate Control /
mbed_official	324:406fd2029f23	2728	uint32_t FTM1b : 1; /!< [25] FTM1 Clock Gate Control /
mbed_official	324:406fd2029f23	2729	uint32_t FTM2b : 1; /!< [26] FTM2 Clock Gate Control /
mbed_official	324:406fd2029f23	2730	uint32_t ADC0b : 1; /!< [27] ADC0 Clock Gate Control /
mbed_official	324:406fd2029f23	2731	uint32_t RESERVED6 : 1; /!< [28] /
mbed_official	324:406fd2029f23	2732	uint32_t RTCb : 1; /!< [29] RTC Access Control /
mbed_official	324:406fd2029f23	2733	uint32_t RESERVED7 : 1; /!< [30] /
mbed_official	324:406fd2029f23	2734	uint32_t DAC0b : 1; /!< [31] DAC0 Clock Gate Control /
mbed_official	324:406fd2029f23	2735	} B;
mbed_official	324:406fd2029f23	2736	} hw_sim_scgc6_t;
mbed_official	324:406fd2029f23	2737
mbed_official	324:406fd2029f23	2738	/*!
mbed_official	324:406fd2029f23	2739	* @name Constants and macros for entire SIM_SCGC6 register
mbed_official	324:406fd2029f23	2740	*/
mbed_official	324:406fd2029f23	2741	/@{/
mbed_official	324:406fd2029f23	2742	#define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU)
mbed_official	324:406fd2029f23	2743
mbed_official	324:406fd2029f23	2744	#define HW_SIM_SCGC6(x) ((__IO hw_sim_scgc6_t ) HW_SIM_SCGC6_ADDR(x))
mbed_official	324:406fd2029f23	2745	#define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U)
mbed_official	324:406fd2029f23	2746	#define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v))
mbed_official	324:406fd2029f23	2747	#define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2748	#define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2749	#define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2750	/@}/
mbed_official	324:406fd2029f23	2751
mbed_official	324:406fd2029f23	2752	/*
mbed_official	324:406fd2029f23	2753	* Constants & macros for individual SIM_SCGC6 bitfields
mbed_official	324:406fd2029f23	2754	*/
mbed_official	324:406fd2029f23	2755
mbed_official	324:406fd2029f23	2756	/*!
mbed_official	324:406fd2029f23	2757	* @name Register SIM_SCGC6, field FTF[0] (RW)
mbed_official	324:406fd2029f23	2758	*
mbed_official	324:406fd2029f23	2759	* This bit controls the clock gate to the flash memory. Flash reads are still
mbed_official	324:406fd2029f23	2760	* supported while the flash memory is clock gated, but entry into low power modes
mbed_official	324:406fd2029f23	2761	* is blocked.
mbed_official	324:406fd2029f23	2762	*
mbed_official	324:406fd2029f23	2763	* Values:
mbed_official	324:406fd2029f23	2764	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2765	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2766	*/
mbed_official	324:406fd2029f23	2767	/@{/
mbed_official	324:406fd2029f23	2768	#define BP_SIM_SCGC6_FTF (0U) /!< Bit position for SIM_SCGC6_FTF. /
mbed_official	324:406fd2029f23	2769	#define BM_SIM_SCGC6_FTF (0x00000001U) /!< Bit mask for SIM_SCGC6_FTF. /
mbed_official	324:406fd2029f23	2770	#define BS_SIM_SCGC6_FTF (1U) /!< Bit field size in bits for SIM_SCGC6_FTF. /
mbed_official	324:406fd2029f23	2771
mbed_official	324:406fd2029f23	2772	/! @brief Read current value of the SIM_SCGC6_FTF field. /
mbed_official	324:406fd2029f23	2773	#define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF))
mbed_official	324:406fd2029f23	2774
mbed_official	324:406fd2029f23	2775	/! @brief Format value for bitfield SIM_SCGC6_FTF. /
mbed_official	324:406fd2029f23	2776	#define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF)
mbed_official	324:406fd2029f23	2777
mbed_official	324:406fd2029f23	2778	/! @brief Set the FTF field to a new value. /
mbed_official	324:406fd2029f23	2779	#define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v))
mbed_official	324:406fd2029f23	2780	/@}/
mbed_official	324:406fd2029f23	2781
mbed_official	324:406fd2029f23	2782	/*!
mbed_official	324:406fd2029f23	2783	* @name Register SIM_SCGC6, field DMAMUX[1] (RW)
mbed_official	324:406fd2029f23	2784	*
mbed_official	324:406fd2029f23	2785	* This bit controls the clock gate to the DMA Mux module.
mbed_official	324:406fd2029f23	2786	*
mbed_official	324:406fd2029f23	2787	* Values:
mbed_official	324:406fd2029f23	2788	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2789	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2790	*/
mbed_official	324:406fd2029f23	2791	/@{/
mbed_official	324:406fd2029f23	2792	#define BP_SIM_SCGC6_DMAMUX (1U) /!< Bit position for SIM_SCGC6_DMAMUX. /
mbed_official	324:406fd2029f23	2793	#define BM_SIM_SCGC6_DMAMUX (0x00000002U) /!< Bit mask for SIM_SCGC6_DMAMUX. /
mbed_official	324:406fd2029f23	2794	#define BS_SIM_SCGC6_DMAMUX (1U) /!< Bit field size in bits for SIM_SCGC6_DMAMUX. /
mbed_official	324:406fd2029f23	2795
mbed_official	324:406fd2029f23	2796	/! @brief Read current value of the SIM_SCGC6_DMAMUX field. /
mbed_official	324:406fd2029f23	2797	#define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX))
mbed_official	324:406fd2029f23	2798
mbed_official	324:406fd2029f23	2799	/! @brief Format value for bitfield SIM_SCGC6_DMAMUX. /
mbed_official	324:406fd2029f23	2800	#define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX)
mbed_official	324:406fd2029f23	2801
mbed_official	324:406fd2029f23	2802	/! @brief Set the DMAMUX field to a new value. /
mbed_official	324:406fd2029f23	2803	#define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v))
mbed_official	324:406fd2029f23	2804	/@}/
mbed_official	324:406fd2029f23	2805
mbed_official	324:406fd2029f23	2806	/*!
mbed_official	324:406fd2029f23	2807	* @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
mbed_official	324:406fd2029f23	2808	*
mbed_official	324:406fd2029f23	2809	* This bit controls the clock gate to the FlexCAN0 module.
mbed_official	324:406fd2029f23	2810	*
mbed_official	324:406fd2029f23	2811	* Values:
mbed_official	324:406fd2029f23	2812	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2813	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2814	*/
mbed_official	324:406fd2029f23	2815	/@{/
mbed_official	324:406fd2029f23	2816	#define BP_SIM_SCGC6_FLEXCAN0 (4U) /!< Bit position for SIM_SCGC6_FLEXCAN0. /
mbed_official	324:406fd2029f23	2817	#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /!< Bit mask for SIM_SCGC6_FLEXCAN0. /
mbed_official	324:406fd2029f23	2818	#define BS_SIM_SCGC6_FLEXCAN0 (1U) /!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. /
mbed_official	324:406fd2029f23	2819
mbed_official	324:406fd2029f23	2820	/! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. /
mbed_official	324:406fd2029f23	2821	#define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0))
mbed_official	324:406fd2029f23	2822
mbed_official	324:406fd2029f23	2823	/! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. /
mbed_official	324:406fd2029f23	2824	#define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0)
mbed_official	324:406fd2029f23	2825
mbed_official	324:406fd2029f23	2826	/! @brief Set the FLEXCAN0 field to a new value. /
mbed_official	324:406fd2029f23	2827	#define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v))
mbed_official	324:406fd2029f23	2828	/@}/
mbed_official	324:406fd2029f23	2829
mbed_official	324:406fd2029f23	2830	/*!
mbed_official	324:406fd2029f23	2831	* @name Register SIM_SCGC6, field RNGA[9] (RW)
mbed_official	324:406fd2029f23	2832	*
mbed_official	324:406fd2029f23	2833	* This bit controls the clock gate to the RNGA module.
mbed_official	324:406fd2029f23	2834	*/
mbed_official	324:406fd2029f23	2835	/@{/
mbed_official	324:406fd2029f23	2836	#define BP_SIM_SCGC6_RNGA (9U) /!< Bit position for SIM_SCGC6_RNGA. /
mbed_official	324:406fd2029f23	2837	#define BM_SIM_SCGC6_RNGA (0x00000200U) /!< Bit mask for SIM_SCGC6_RNGA. /
mbed_official	324:406fd2029f23	2838	#define BS_SIM_SCGC6_RNGA (1U) /!< Bit field size in bits for SIM_SCGC6_RNGA. /
mbed_official	324:406fd2029f23	2839
mbed_official	324:406fd2029f23	2840	/! @brief Read current value of the SIM_SCGC6_RNGA field. /
mbed_official	324:406fd2029f23	2841	#define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA))
mbed_official	324:406fd2029f23	2842
mbed_official	324:406fd2029f23	2843	/! @brief Format value for bitfield SIM_SCGC6_RNGA. /
mbed_official	324:406fd2029f23	2844	#define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA)
mbed_official	324:406fd2029f23	2845
mbed_official	324:406fd2029f23	2846	/! @brief Set the RNGA field to a new value. /
mbed_official	324:406fd2029f23	2847	#define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v))
mbed_official	324:406fd2029f23	2848	/@}/
mbed_official	324:406fd2029f23	2849
mbed_official	324:406fd2029f23	2850	/*!
mbed_official	324:406fd2029f23	2851	* @name Register SIM_SCGC6, field SPI0[12] (RW)
mbed_official	324:406fd2029f23	2852	*
mbed_official	324:406fd2029f23	2853	* This bit controls the clock gate to the SPI0 module.
mbed_official	324:406fd2029f23	2854	*
mbed_official	324:406fd2029f23	2855	* Values:
mbed_official	324:406fd2029f23	2856	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2857	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2858	*/
mbed_official	324:406fd2029f23	2859	/@{/
mbed_official	324:406fd2029f23	2860	#define BP_SIM_SCGC6_SPI0 (12U) /!< Bit position for SIM_SCGC6_SPI0. /
mbed_official	324:406fd2029f23	2861	#define BM_SIM_SCGC6_SPI0 (0x00001000U) /!< Bit mask for SIM_SCGC6_SPI0. /
mbed_official	324:406fd2029f23	2862	#define BS_SIM_SCGC6_SPI0 (1U) /!< Bit field size in bits for SIM_SCGC6_SPI0. /
mbed_official	324:406fd2029f23	2863
mbed_official	324:406fd2029f23	2864	/! @brief Read current value of the SIM_SCGC6_SPI0 field. /
mbed_official	324:406fd2029f23	2865	#define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0))
mbed_official	324:406fd2029f23	2866
mbed_official	324:406fd2029f23	2867	/! @brief Format value for bitfield SIM_SCGC6_SPI0. /
mbed_official	324:406fd2029f23	2868	#define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0)
mbed_official	324:406fd2029f23	2869
mbed_official	324:406fd2029f23	2870	/! @brief Set the SPI0 field to a new value. /
mbed_official	324:406fd2029f23	2871	#define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v))
mbed_official	324:406fd2029f23	2872	/@}/
mbed_official	324:406fd2029f23	2873
mbed_official	324:406fd2029f23	2874	/*!
mbed_official	324:406fd2029f23	2875	* @name Register SIM_SCGC6, field SPI1[13] (RW)
mbed_official	324:406fd2029f23	2876	*
mbed_official	324:406fd2029f23	2877	* This bit controls the clock gate to the SPI1 module.
mbed_official	324:406fd2029f23	2878	*
mbed_official	324:406fd2029f23	2879	* Values:
mbed_official	324:406fd2029f23	2880	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2881	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2882	*/
mbed_official	324:406fd2029f23	2883	/@{/
mbed_official	324:406fd2029f23	2884	#define BP_SIM_SCGC6_SPI1 (13U) /!< Bit position for SIM_SCGC6_SPI1. /
mbed_official	324:406fd2029f23	2885	#define BM_SIM_SCGC6_SPI1 (0x00002000U) /!< Bit mask for SIM_SCGC6_SPI1. /
mbed_official	324:406fd2029f23	2886	#define BS_SIM_SCGC6_SPI1 (1U) /!< Bit field size in bits for SIM_SCGC6_SPI1. /
mbed_official	324:406fd2029f23	2887
mbed_official	324:406fd2029f23	2888	/! @brief Read current value of the SIM_SCGC6_SPI1 field. /
mbed_official	324:406fd2029f23	2889	#define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1))
mbed_official	324:406fd2029f23	2890
mbed_official	324:406fd2029f23	2891	/! @brief Format value for bitfield SIM_SCGC6_SPI1. /
mbed_official	324:406fd2029f23	2892	#define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1)
mbed_official	324:406fd2029f23	2893
mbed_official	324:406fd2029f23	2894	/! @brief Set the SPI1 field to a new value. /
mbed_official	324:406fd2029f23	2895	#define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v))
mbed_official	324:406fd2029f23	2896	/@}/
mbed_official	324:406fd2029f23	2897
mbed_official	324:406fd2029f23	2898	/*!
mbed_official	324:406fd2029f23	2899	* @name Register SIM_SCGC6, field I2S[15] (RW)
mbed_official	324:406fd2029f23	2900	*
mbed_official	324:406fd2029f23	2901	* This bit controls the clock gate to the I 2 S module.
mbed_official	324:406fd2029f23	2902	*
mbed_official	324:406fd2029f23	2903	* Values:
mbed_official	324:406fd2029f23	2904	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2905	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2906	*/
mbed_official	324:406fd2029f23	2907	/@{/
mbed_official	324:406fd2029f23	2908	#define BP_SIM_SCGC6_I2S (15U) /!< Bit position for SIM_SCGC6_I2S. /
mbed_official	324:406fd2029f23	2909	#define BM_SIM_SCGC6_I2S (0x00008000U) /!< Bit mask for SIM_SCGC6_I2S. /
mbed_official	324:406fd2029f23	2910	#define BS_SIM_SCGC6_I2S (1U) /!< Bit field size in bits for SIM_SCGC6_I2S. /
mbed_official	324:406fd2029f23	2911
mbed_official	324:406fd2029f23	2912	/! @brief Read current value of the SIM_SCGC6_I2S field. /
mbed_official	324:406fd2029f23	2913	#define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S))
mbed_official	324:406fd2029f23	2914
mbed_official	324:406fd2029f23	2915	/! @brief Format value for bitfield SIM_SCGC6_I2S. /
mbed_official	324:406fd2029f23	2916	#define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S)
mbed_official	324:406fd2029f23	2917
mbed_official	324:406fd2029f23	2918	/! @brief Set the I2S field to a new value. /
mbed_official	324:406fd2029f23	2919	#define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v))
mbed_official	324:406fd2029f23	2920	/@}/
mbed_official	324:406fd2029f23	2921
mbed_official	324:406fd2029f23	2922	/*!
mbed_official	324:406fd2029f23	2923	* @name Register SIM_SCGC6, field CRC[18] (RW)
mbed_official	324:406fd2029f23	2924	*
mbed_official	324:406fd2029f23	2925	* This bit controls the clock gate to the CRC module.
mbed_official	324:406fd2029f23	2926	*
mbed_official	324:406fd2029f23	2927	* Values:
mbed_official	324:406fd2029f23	2928	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2929	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2930	*/
mbed_official	324:406fd2029f23	2931	/@{/
mbed_official	324:406fd2029f23	2932	#define BP_SIM_SCGC6_CRC (18U) /!< Bit position for SIM_SCGC6_CRC. /
mbed_official	324:406fd2029f23	2933	#define BM_SIM_SCGC6_CRC (0x00040000U) /!< Bit mask for SIM_SCGC6_CRC. /
mbed_official	324:406fd2029f23	2934	#define BS_SIM_SCGC6_CRC (1U) /!< Bit field size in bits for SIM_SCGC6_CRC. /
mbed_official	324:406fd2029f23	2935
mbed_official	324:406fd2029f23	2936	/! @brief Read current value of the SIM_SCGC6_CRC field. /
mbed_official	324:406fd2029f23	2937	#define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))
mbed_official	324:406fd2029f23	2938
mbed_official	324:406fd2029f23	2939	/! @brief Format value for bitfield SIM_SCGC6_CRC. /
mbed_official	324:406fd2029f23	2940	#define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC)
mbed_official	324:406fd2029f23	2941
mbed_official	324:406fd2029f23	2942	/! @brief Set the CRC field to a new value. /
mbed_official	324:406fd2029f23	2943	#define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v))
mbed_official	324:406fd2029f23	2944	/@}/
mbed_official	324:406fd2029f23	2945
mbed_official	324:406fd2029f23	2946	/*!
mbed_official	324:406fd2029f23	2947	* @name Register SIM_SCGC6, field USBDCD[21] (RW)
mbed_official	324:406fd2029f23	2948	*
mbed_official	324:406fd2029f23	2949	* This bit controls the clock gate to the USB DCD module.
mbed_official	324:406fd2029f23	2950	*
mbed_official	324:406fd2029f23	2951	* Values:
mbed_official	324:406fd2029f23	2952	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2953	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2954	*/
mbed_official	324:406fd2029f23	2955	/@{/
mbed_official	324:406fd2029f23	2956	#define BP_SIM_SCGC6_USBDCD (21U) /!< Bit position for SIM_SCGC6_USBDCD. /
mbed_official	324:406fd2029f23	2957	#define BM_SIM_SCGC6_USBDCD (0x00200000U) /!< Bit mask for SIM_SCGC6_USBDCD. /
mbed_official	324:406fd2029f23	2958	#define BS_SIM_SCGC6_USBDCD (1U) /!< Bit field size in bits for SIM_SCGC6_USBDCD. /
mbed_official	324:406fd2029f23	2959
mbed_official	324:406fd2029f23	2960	/! @brief Read current value of the SIM_SCGC6_USBDCD field. /
mbed_official	324:406fd2029f23	2961	#define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD))
mbed_official	324:406fd2029f23	2962
mbed_official	324:406fd2029f23	2963	/! @brief Format value for bitfield SIM_SCGC6_USBDCD. /
mbed_official	324:406fd2029f23	2964	#define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD)
mbed_official	324:406fd2029f23	2965
mbed_official	324:406fd2029f23	2966	/! @brief Set the USBDCD field to a new value. /
mbed_official	324:406fd2029f23	2967	#define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v))
mbed_official	324:406fd2029f23	2968	/@}/
mbed_official	324:406fd2029f23	2969
mbed_official	324:406fd2029f23	2970	/*!
mbed_official	324:406fd2029f23	2971	* @name Register SIM_SCGC6, field PDB[22] (RW)
mbed_official	324:406fd2029f23	2972	*
mbed_official	324:406fd2029f23	2973	* This bit controls the clock gate to the PDB module.
mbed_official	324:406fd2029f23	2974	*
mbed_official	324:406fd2029f23	2975	* Values:
mbed_official	324:406fd2029f23	2976	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	2977	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	2978	*/
mbed_official	324:406fd2029f23	2979	/@{/
mbed_official	324:406fd2029f23	2980	#define BP_SIM_SCGC6_PDB (22U) /!< Bit position for SIM_SCGC6_PDB. /
mbed_official	324:406fd2029f23	2981	#define BM_SIM_SCGC6_PDB (0x00400000U) /!< Bit mask for SIM_SCGC6_PDB. /
mbed_official	324:406fd2029f23	2982	#define BS_SIM_SCGC6_PDB (1U) /!< Bit field size in bits for SIM_SCGC6_PDB. /
mbed_official	324:406fd2029f23	2983
mbed_official	324:406fd2029f23	2984	/! @brief Read current value of the SIM_SCGC6_PDB field. /
mbed_official	324:406fd2029f23	2985	#define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))
mbed_official	324:406fd2029f23	2986
mbed_official	324:406fd2029f23	2987	/! @brief Format value for bitfield SIM_SCGC6_PDB. /
mbed_official	324:406fd2029f23	2988	#define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB)
mbed_official	324:406fd2029f23	2989
mbed_official	324:406fd2029f23	2990	/! @brief Set the PDB field to a new value. /
mbed_official	324:406fd2029f23	2991	#define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v))
mbed_official	324:406fd2029f23	2992	/@}/
mbed_official	324:406fd2029f23	2993
mbed_official	324:406fd2029f23	2994	/*!
mbed_official	324:406fd2029f23	2995	* @name Register SIM_SCGC6, field PIT[23] (RW)
mbed_official	324:406fd2029f23	2996	*
mbed_official	324:406fd2029f23	2997	* This bit controls the clock gate to the PIT module.
mbed_official	324:406fd2029f23	2998	*
mbed_official	324:406fd2029f23	2999	* Values:
mbed_official	324:406fd2029f23	3000	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3001	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3002	*/
mbed_official	324:406fd2029f23	3003	/@{/
mbed_official	324:406fd2029f23	3004	#define BP_SIM_SCGC6_PIT (23U) /!< Bit position for SIM_SCGC6_PIT. /
mbed_official	324:406fd2029f23	3005	#define BM_SIM_SCGC6_PIT (0x00800000U) /!< Bit mask for SIM_SCGC6_PIT. /
mbed_official	324:406fd2029f23	3006	#define BS_SIM_SCGC6_PIT (1U) /!< Bit field size in bits for SIM_SCGC6_PIT. /
mbed_official	324:406fd2029f23	3007
mbed_official	324:406fd2029f23	3008	/! @brief Read current value of the SIM_SCGC6_PIT field. /
mbed_official	324:406fd2029f23	3009	#define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))
mbed_official	324:406fd2029f23	3010
mbed_official	324:406fd2029f23	3011	/! @brief Format value for bitfield SIM_SCGC6_PIT. /
mbed_official	324:406fd2029f23	3012	#define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT)
mbed_official	324:406fd2029f23	3013
mbed_official	324:406fd2029f23	3014	/! @brief Set the PIT field to a new value. /
mbed_official	324:406fd2029f23	3015	#define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v))
mbed_official	324:406fd2029f23	3016	/@}/
mbed_official	324:406fd2029f23	3017
mbed_official	324:406fd2029f23	3018	/*!
mbed_official	324:406fd2029f23	3019	* @name Register SIM_SCGC6, field FTM0[24] (RW)
mbed_official	324:406fd2029f23	3020	*
mbed_official	324:406fd2029f23	3021	* This bit controls the clock gate to the FTM0 module.
mbed_official	324:406fd2029f23	3022	*
mbed_official	324:406fd2029f23	3023	* Values:
mbed_official	324:406fd2029f23	3024	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3025	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3026	*/
mbed_official	324:406fd2029f23	3027	/@{/
mbed_official	324:406fd2029f23	3028	#define BP_SIM_SCGC6_FTM0 (24U) /!< Bit position for SIM_SCGC6_FTM0. /
mbed_official	324:406fd2029f23	3029	#define BM_SIM_SCGC6_FTM0 (0x01000000U) /!< Bit mask for SIM_SCGC6_FTM0. /
mbed_official	324:406fd2029f23	3030	#define BS_SIM_SCGC6_FTM0 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM0. /
mbed_official	324:406fd2029f23	3031
mbed_official	324:406fd2029f23	3032	/! @brief Read current value of the SIM_SCGC6_FTM0 field. /
mbed_official	324:406fd2029f23	3033	#define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))
mbed_official	324:406fd2029f23	3034
mbed_official	324:406fd2029f23	3035	/! @brief Format value for bitfield SIM_SCGC6_FTM0. /
mbed_official	324:406fd2029f23	3036	#define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0)
mbed_official	324:406fd2029f23	3037
mbed_official	324:406fd2029f23	3038	/! @brief Set the FTM0 field to a new value. /
mbed_official	324:406fd2029f23	3039	#define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v))
mbed_official	324:406fd2029f23	3040	/@}/
mbed_official	324:406fd2029f23	3041
mbed_official	324:406fd2029f23	3042	/*!
mbed_official	324:406fd2029f23	3043	* @name Register SIM_SCGC6, field FTM1[25] (RW)
mbed_official	324:406fd2029f23	3044	*
mbed_official	324:406fd2029f23	3045	* This bit controls the clock gate to the FTM1 module.
mbed_official	324:406fd2029f23	3046	*
mbed_official	324:406fd2029f23	3047	* Values:
mbed_official	324:406fd2029f23	3048	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3049	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3050	*/
mbed_official	324:406fd2029f23	3051	/@{/
mbed_official	324:406fd2029f23	3052	#define BP_SIM_SCGC6_FTM1 (25U) /!< Bit position for SIM_SCGC6_FTM1. /
mbed_official	324:406fd2029f23	3053	#define BM_SIM_SCGC6_FTM1 (0x02000000U) /!< Bit mask for SIM_SCGC6_FTM1. /
mbed_official	324:406fd2029f23	3054	#define BS_SIM_SCGC6_FTM1 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM1. /
mbed_official	324:406fd2029f23	3055
mbed_official	324:406fd2029f23	3056	/! @brief Read current value of the SIM_SCGC6_FTM1 field. /
mbed_official	324:406fd2029f23	3057	#define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))
mbed_official	324:406fd2029f23	3058
mbed_official	324:406fd2029f23	3059	/! @brief Format value for bitfield SIM_SCGC6_FTM1. /
mbed_official	324:406fd2029f23	3060	#define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1)
mbed_official	324:406fd2029f23	3061
mbed_official	324:406fd2029f23	3062	/! @brief Set the FTM1 field to a new value. /
mbed_official	324:406fd2029f23	3063	#define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v))
mbed_official	324:406fd2029f23	3064	/@}/
mbed_official	324:406fd2029f23	3065
mbed_official	324:406fd2029f23	3066	/*!
mbed_official	324:406fd2029f23	3067	* @name Register SIM_SCGC6, field FTM2[26] (RW)
mbed_official	324:406fd2029f23	3068	*
mbed_official	324:406fd2029f23	3069	* This bit controls the clock gate to the FTM2 module.
mbed_official	324:406fd2029f23	3070	*
mbed_official	324:406fd2029f23	3071	* Values:
mbed_official	324:406fd2029f23	3072	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3073	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3074	*/
mbed_official	324:406fd2029f23	3075	/@{/
mbed_official	324:406fd2029f23	3076	#define BP_SIM_SCGC6_FTM2 (26U) /!< Bit position for SIM_SCGC6_FTM2. /
mbed_official	324:406fd2029f23	3077	#define BM_SIM_SCGC6_FTM2 (0x04000000U) /!< Bit mask for SIM_SCGC6_FTM2. /
mbed_official	324:406fd2029f23	3078	#define BS_SIM_SCGC6_FTM2 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM2. /
mbed_official	324:406fd2029f23	3079
mbed_official	324:406fd2029f23	3080	/! @brief Read current value of the SIM_SCGC6_FTM2 field. /
mbed_official	324:406fd2029f23	3081	#define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2))
mbed_official	324:406fd2029f23	3082
mbed_official	324:406fd2029f23	3083	/! @brief Format value for bitfield SIM_SCGC6_FTM2. /
mbed_official	324:406fd2029f23	3084	#define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2)
mbed_official	324:406fd2029f23	3085
mbed_official	324:406fd2029f23	3086	/! @brief Set the FTM2 field to a new value. /
mbed_official	324:406fd2029f23	3087	#define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v))
mbed_official	324:406fd2029f23	3088	/@}/
mbed_official	324:406fd2029f23	3089
mbed_official	324:406fd2029f23	3090	/*!
mbed_official	324:406fd2029f23	3091	* @name Register SIM_SCGC6, field ADC0[27] (RW)
mbed_official	324:406fd2029f23	3092	*
mbed_official	324:406fd2029f23	3093	* This bit controls the clock gate to the ADC0 module.
mbed_official	324:406fd2029f23	3094	*
mbed_official	324:406fd2029f23	3095	* Values:
mbed_official	324:406fd2029f23	3096	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3097	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3098	*/
mbed_official	324:406fd2029f23	3099	/@{/
mbed_official	324:406fd2029f23	3100	#define BP_SIM_SCGC6_ADC0 (27U) /!< Bit position for SIM_SCGC6_ADC0. /
mbed_official	324:406fd2029f23	3101	#define BM_SIM_SCGC6_ADC0 (0x08000000U) /!< Bit mask for SIM_SCGC6_ADC0. /
mbed_official	324:406fd2029f23	3102	#define BS_SIM_SCGC6_ADC0 (1U) /!< Bit field size in bits for SIM_SCGC6_ADC0. /
mbed_official	324:406fd2029f23	3103
mbed_official	324:406fd2029f23	3104	/! @brief Read current value of the SIM_SCGC6_ADC0 field. /
mbed_official	324:406fd2029f23	3105	#define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))
mbed_official	324:406fd2029f23	3106
mbed_official	324:406fd2029f23	3107	/! @brief Format value for bitfield SIM_SCGC6_ADC0. /
mbed_official	324:406fd2029f23	3108	#define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0)
mbed_official	324:406fd2029f23	3109
mbed_official	324:406fd2029f23	3110	/! @brief Set the ADC0 field to a new value. /
mbed_official	324:406fd2029f23	3111	#define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v))
mbed_official	324:406fd2029f23	3112	/@}/
mbed_official	324:406fd2029f23	3113
mbed_official	324:406fd2029f23	3114	/*!
mbed_official	324:406fd2029f23	3115	* @name Register SIM_SCGC6, field RTC[29] (RW)
mbed_official	324:406fd2029f23	3116	*
mbed_official	324:406fd2029f23	3117	* This bit controls software access and interrupts to the RTC module.
mbed_official	324:406fd2029f23	3118	*
mbed_official	324:406fd2029f23	3119	* Values:
mbed_official	324:406fd2029f23	3120	* - 0 - Access and interrupts disabled
mbed_official	324:406fd2029f23	3121	* - 1 - Access and interrupts enabled
mbed_official	324:406fd2029f23	3122	*/
mbed_official	324:406fd2029f23	3123	/@{/
mbed_official	324:406fd2029f23	3124	#define BP_SIM_SCGC6_RTC (29U) /!< Bit position for SIM_SCGC6_RTC. /
mbed_official	324:406fd2029f23	3125	#define BM_SIM_SCGC6_RTC (0x20000000U) /!< Bit mask for SIM_SCGC6_RTC. /
mbed_official	324:406fd2029f23	3126	#define BS_SIM_SCGC6_RTC (1U) /!< Bit field size in bits for SIM_SCGC6_RTC. /
mbed_official	324:406fd2029f23	3127
mbed_official	324:406fd2029f23	3128	/! @brief Read current value of the SIM_SCGC6_RTC field. /
mbed_official	324:406fd2029f23	3129	#define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))
mbed_official	324:406fd2029f23	3130
mbed_official	324:406fd2029f23	3131	/! @brief Format value for bitfield SIM_SCGC6_RTC. /
mbed_official	324:406fd2029f23	3132	#define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC)
mbed_official	324:406fd2029f23	3133
mbed_official	324:406fd2029f23	3134	/! @brief Set the RTC field to a new value. /
mbed_official	324:406fd2029f23	3135	#define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v))
mbed_official	324:406fd2029f23	3136	/@}/
mbed_official	324:406fd2029f23	3137
mbed_official	324:406fd2029f23	3138	/*!
mbed_official	324:406fd2029f23	3139	* @name Register SIM_SCGC6, field DAC0[31] (RW)
mbed_official	324:406fd2029f23	3140	*
mbed_official	324:406fd2029f23	3141	* This bit controls the clock gate to the DAC0 module.
mbed_official	324:406fd2029f23	3142	*
mbed_official	324:406fd2029f23	3143	* Values:
mbed_official	324:406fd2029f23	3144	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3145	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3146	*/
mbed_official	324:406fd2029f23	3147	/@{/
mbed_official	324:406fd2029f23	3148	#define BP_SIM_SCGC6_DAC0 (31U) /!< Bit position for SIM_SCGC6_DAC0. /
mbed_official	324:406fd2029f23	3149	#define BM_SIM_SCGC6_DAC0 (0x80000000U) /!< Bit mask for SIM_SCGC6_DAC0. /
mbed_official	324:406fd2029f23	3150	#define BS_SIM_SCGC6_DAC0 (1U) /!< Bit field size in bits for SIM_SCGC6_DAC0. /
mbed_official	324:406fd2029f23	3151
mbed_official	324:406fd2029f23	3152	/! @brief Read current value of the SIM_SCGC6_DAC0 field. /
mbed_official	324:406fd2029f23	3153	#define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0))
mbed_official	324:406fd2029f23	3154
mbed_official	324:406fd2029f23	3155	/! @brief Format value for bitfield SIM_SCGC6_DAC0. /
mbed_official	324:406fd2029f23	3156	#define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0)
mbed_official	324:406fd2029f23	3157
mbed_official	324:406fd2029f23	3158	/! @brief Set the DAC0 field to a new value. /
mbed_official	324:406fd2029f23	3159	#define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v))
mbed_official	324:406fd2029f23	3160	/@}/
mbed_official	324:406fd2029f23	3161
mbed_official	324:406fd2029f23	3162	/*******************************************************************************
mbed_official	324:406fd2029f23	3163	* HW_SIM_SCGC7 - System Clock Gating Control Register 7
mbed_official	324:406fd2029f23	3164	******************************************************************************/
mbed_official	324:406fd2029f23	3165
mbed_official	324:406fd2029f23	3166	/*!
mbed_official	324:406fd2029f23	3167	* @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
mbed_official	324:406fd2029f23	3168	*
mbed_official	324:406fd2029f23	3169	* Reset value: 0x00000006U
mbed_official	324:406fd2029f23	3170	*/
mbed_official	324:406fd2029f23	3171	typedef union _hw_sim_scgc7
mbed_official	324:406fd2029f23	3172	{
mbed_official	324:406fd2029f23	3173	uint32_t U;
mbed_official	324:406fd2029f23	3174	struct _hw_sim_scgc7_bitfields
mbed_official	324:406fd2029f23	3175	{
mbed_official	324:406fd2029f23	3176	uint32_t FLEXBUS : 1; /!< [0] FlexBus Clock Gate Control /
mbed_official	324:406fd2029f23	3177	uint32_t DMA : 1; /!< [1] DMA Clock Gate Control /
mbed_official	324:406fd2029f23	3178	uint32_t MPUb : 1; /!< [2] MPU Clock Gate Control /
mbed_official	324:406fd2029f23	3179	uint32_t RESERVED0 : 29; /!< [31:3] /
mbed_official	324:406fd2029f23	3180	} B;
mbed_official	324:406fd2029f23	3181	} hw_sim_scgc7_t;
mbed_official	324:406fd2029f23	3182
mbed_official	324:406fd2029f23	3183	/*!
mbed_official	324:406fd2029f23	3184	* @name Constants and macros for entire SIM_SCGC7 register
mbed_official	324:406fd2029f23	3185	*/
mbed_official	324:406fd2029f23	3186	/@{/
mbed_official	324:406fd2029f23	3187	#define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U)
mbed_official	324:406fd2029f23	3188
mbed_official	324:406fd2029f23	3189	#define HW_SIM_SCGC7(x) ((__IO hw_sim_scgc7_t ) HW_SIM_SCGC7_ADDR(x))
mbed_official	324:406fd2029f23	3190	#define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U)
mbed_official	324:406fd2029f23	3191	#define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v))
mbed_official	324:406fd2029f23	3192	#define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3193	#define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3194	#define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3195	/@}/
mbed_official	324:406fd2029f23	3196
mbed_official	324:406fd2029f23	3197	/*
mbed_official	324:406fd2029f23	3198	* Constants & macros for individual SIM_SCGC7 bitfields
mbed_official	324:406fd2029f23	3199	*/
mbed_official	324:406fd2029f23	3200
mbed_official	324:406fd2029f23	3201	/*!
mbed_official	324:406fd2029f23	3202	* @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
mbed_official	324:406fd2029f23	3203	*
mbed_official	324:406fd2029f23	3204	* This bit controls the clock gate to the FlexBus module.
mbed_official	324:406fd2029f23	3205	*
mbed_official	324:406fd2029f23	3206	* Values:
mbed_official	324:406fd2029f23	3207	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3208	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3209	*/
mbed_official	324:406fd2029f23	3210	/@{/
mbed_official	324:406fd2029f23	3211	#define BP_SIM_SCGC7_FLEXBUS (0U) /!< Bit position for SIM_SCGC7_FLEXBUS. /
mbed_official	324:406fd2029f23	3212	#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /!< Bit mask for SIM_SCGC7_FLEXBUS. /
mbed_official	324:406fd2029f23	3213	#define BS_SIM_SCGC7_FLEXBUS (1U) /!< Bit field size in bits for SIM_SCGC7_FLEXBUS. /
mbed_official	324:406fd2029f23	3214
mbed_official	324:406fd2029f23	3215	/! @brief Read current value of the SIM_SCGC7_FLEXBUS field. /
mbed_official	324:406fd2029f23	3216	#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))
mbed_official	324:406fd2029f23	3217
mbed_official	324:406fd2029f23	3218	/! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. /
mbed_official	324:406fd2029f23	3219	#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS)
mbed_official	324:406fd2029f23	3220
mbed_official	324:406fd2029f23	3221	/! @brief Set the FLEXBUS field to a new value. /
mbed_official	324:406fd2029f23	3222	#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v))
mbed_official	324:406fd2029f23	3223	/@}/
mbed_official	324:406fd2029f23	3224
mbed_official	324:406fd2029f23	3225	/*!
mbed_official	324:406fd2029f23	3226	* @name Register SIM_SCGC7, field DMA[1] (RW)
mbed_official	324:406fd2029f23	3227	*
mbed_official	324:406fd2029f23	3228	* This bit controls the clock gate to the DMA module.
mbed_official	324:406fd2029f23	3229	*
mbed_official	324:406fd2029f23	3230	* Values:
mbed_official	324:406fd2029f23	3231	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3232	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3233	*/
mbed_official	324:406fd2029f23	3234	/@{/
mbed_official	324:406fd2029f23	3235	#define BP_SIM_SCGC7_DMA (1U) /!< Bit position for SIM_SCGC7_DMA. /
mbed_official	324:406fd2029f23	3236	#define BM_SIM_SCGC7_DMA (0x00000002U) /!< Bit mask for SIM_SCGC7_DMA. /
mbed_official	324:406fd2029f23	3237	#define BS_SIM_SCGC7_DMA (1U) /!< Bit field size in bits for SIM_SCGC7_DMA. /
mbed_official	324:406fd2029f23	3238
mbed_official	324:406fd2029f23	3239	/! @brief Read current value of the SIM_SCGC7_DMA field. /
mbed_official	324:406fd2029f23	3240	#define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))
mbed_official	324:406fd2029f23	3241
mbed_official	324:406fd2029f23	3242	/! @brief Format value for bitfield SIM_SCGC7_DMA. /
mbed_official	324:406fd2029f23	3243	#define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA)
mbed_official	324:406fd2029f23	3244
mbed_official	324:406fd2029f23	3245	/! @brief Set the DMA field to a new value. /
mbed_official	324:406fd2029f23	3246	#define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v))
mbed_official	324:406fd2029f23	3247	/@}/
mbed_official	324:406fd2029f23	3248
mbed_official	324:406fd2029f23	3249	/*!
mbed_official	324:406fd2029f23	3250	* @name Register SIM_SCGC7, field MPU[2] (RW)
mbed_official	324:406fd2029f23	3251	*
mbed_official	324:406fd2029f23	3252	* This bit controls the clock gate to the MPU module.
mbed_official	324:406fd2029f23	3253	*
mbed_official	324:406fd2029f23	3254	* Values:
mbed_official	324:406fd2029f23	3255	* - 0 - Clock disabled
mbed_official	324:406fd2029f23	3256	* - 1 - Clock enabled
mbed_official	324:406fd2029f23	3257	*/
mbed_official	324:406fd2029f23	3258	/@{/
mbed_official	324:406fd2029f23	3259	#define BP_SIM_SCGC7_MPU (2U) /!< Bit position for SIM_SCGC7_MPU. /
mbed_official	324:406fd2029f23	3260	#define BM_SIM_SCGC7_MPU (0x00000004U) /!< Bit mask for SIM_SCGC7_MPU. /
mbed_official	324:406fd2029f23	3261	#define BS_SIM_SCGC7_MPU (1U) /!< Bit field size in bits for SIM_SCGC7_MPU. /
mbed_official	324:406fd2029f23	3262
mbed_official	324:406fd2029f23	3263	/! @brief Read current value of the SIM_SCGC7_MPU field. /
mbed_official	324:406fd2029f23	3264	#define BR_SIM_SCGC7_MPU(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU))
mbed_official	324:406fd2029f23	3265
mbed_official	324:406fd2029f23	3266	/! @brief Format value for bitfield SIM_SCGC7_MPU. /
mbed_official	324:406fd2029f23	3267	#define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU)
mbed_official	324:406fd2029f23	3268
mbed_official	324:406fd2029f23	3269	/! @brief Set the MPU field to a new value. /
mbed_official	324:406fd2029f23	3270	#define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v))
mbed_official	324:406fd2029f23	3271	/@}/
mbed_official	324:406fd2029f23	3272
mbed_official	324:406fd2029f23	3273	/*******************************************************************************
mbed_official	324:406fd2029f23	3274	* HW_SIM_CLKDIV1 - System Clock Divider Register 1
mbed_official	324:406fd2029f23	3275	******************************************************************************/
mbed_official	324:406fd2029f23	3276
mbed_official	324:406fd2029f23	3277	/*!
mbed_official	324:406fd2029f23	3278	* @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
mbed_official	324:406fd2029f23	3279	*
mbed_official	324:406fd2029f23	3280	* Reset value: 0x00010000U
mbed_official	324:406fd2029f23	3281	*
mbed_official	324:406fd2029f23	3282	* When updating CLKDIV1, update all fields using the one write command.
mbed_official	324:406fd2029f23	3283	* Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
mbed_official	324:406fd2029f23	3284	* write to be ignored. The maximum divide ratio that can be programmed between
mbed_official	324:406fd2029f23	3285	* core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
mbed_official	324:406fd2029f23	3286	* 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
mbed_official	324:406fd2029f23	3287	* by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
mbed_official	324:406fd2029f23	3288	* mode.
mbed_official	324:406fd2029f23	3289	*/
mbed_official	324:406fd2029f23	3290	typedef union _hw_sim_clkdiv1
mbed_official	324:406fd2029f23	3291	{
mbed_official	324:406fd2029f23	3292	uint32_t U;
mbed_official	324:406fd2029f23	3293	struct _hw_sim_clkdiv1_bitfields
mbed_official	324:406fd2029f23	3294	{
mbed_official	324:406fd2029f23	3295	uint32_t RESERVED0 : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	3296	uint32_t OUTDIV4 : 4; /!< [19:16] Clock 4 output divider value /
mbed_official	324:406fd2029f23	3297	uint32_t OUTDIV3 : 4; /!< [23:20] Clock 3 output divider value /
mbed_official	324:406fd2029f23	3298	uint32_t OUTDIV2 : 4; /!< [27:24] Clock 2 output divider value /
mbed_official	324:406fd2029f23	3299	uint32_t OUTDIV1 : 4; /!< [31:28] Clock 1 output divider value /
mbed_official	324:406fd2029f23	3300	} B;
mbed_official	324:406fd2029f23	3301	} hw_sim_clkdiv1_t;
mbed_official	324:406fd2029f23	3302
mbed_official	324:406fd2029f23	3303	/*!
mbed_official	324:406fd2029f23	3304	* @name Constants and macros for entire SIM_CLKDIV1 register
mbed_official	324:406fd2029f23	3305	*/
mbed_official	324:406fd2029f23	3306	/@{/
mbed_official	324:406fd2029f23	3307	#define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U)
mbed_official	324:406fd2029f23	3308
mbed_official	324:406fd2029f23	3309	#define HW_SIM_CLKDIV1(x) ((__IO hw_sim_clkdiv1_t ) HW_SIM_CLKDIV1_ADDR(x))
mbed_official	324:406fd2029f23	3310	#define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U)
mbed_official	324:406fd2029f23	3311	#define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v))
mbed_official	324:406fd2029f23	3312	#define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3313	#define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3314	#define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3315	/@}/
mbed_official	324:406fd2029f23	3316
mbed_official	324:406fd2029f23	3317	/*
mbed_official	324:406fd2029f23	3318	* Constants & macros for individual SIM_CLKDIV1 bitfields
mbed_official	324:406fd2029f23	3319	*/
mbed_official	324:406fd2029f23	3320
mbed_official	324:406fd2029f23	3321	/*!
mbed_official	324:406fd2029f23	3322	* @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
mbed_official	324:406fd2029f23	3323	*
mbed_official	324:406fd2029f23	3324	* This field sets the divide value for the flash clock from MCGOUTCLK. At the
mbed_official	324:406fd2029f23	3325	* end of reset, it is loaded with either 0001 or 1111 depending on
mbed_official	324:406fd2029f23	3326	* FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
mbed_official	324:406fd2029f23	3327	* frequency.
mbed_official	324:406fd2029f23	3328	*
mbed_official	324:406fd2029f23	3329	* Values:
mbed_official	324:406fd2029f23	3330	* - 0000 - Divide-by-1.
mbed_official	324:406fd2029f23	3331	* - 0001 - Divide-by-2.
mbed_official	324:406fd2029f23	3332	* - 0010 - Divide-by-3.
mbed_official	324:406fd2029f23	3333	* - 0011 - Divide-by-4.
mbed_official	324:406fd2029f23	3334	* - 0100 - Divide-by-5.
mbed_official	324:406fd2029f23	3335	* - 0101 - Divide-by-6.
mbed_official	324:406fd2029f23	3336	* - 0110 - Divide-by-7.
mbed_official	324:406fd2029f23	3337	* - 0111 - Divide-by-8.
mbed_official	324:406fd2029f23	3338	* - 1000 - Divide-by-9.
mbed_official	324:406fd2029f23	3339	* - 1001 - Divide-by-10.
mbed_official	324:406fd2029f23	3340	* - 1010 - Divide-by-11.
mbed_official	324:406fd2029f23	3341	* - 1011 - Divide-by-12.
mbed_official	324:406fd2029f23	3342	* - 1100 - Divide-by-13.
mbed_official	324:406fd2029f23	3343	* - 1101 - Divide-by-14.
mbed_official	324:406fd2029f23	3344	* - 1110 - Divide-by-15.
mbed_official	324:406fd2029f23	3345	* - 1111 - Divide-by-16.
mbed_official	324:406fd2029f23	3346	*/
mbed_official	324:406fd2029f23	3347	/@{/
mbed_official	324:406fd2029f23	3348	#define BP_SIM_CLKDIV1_OUTDIV4 (16U) /!< Bit position for SIM_CLKDIV1_OUTDIV4. /
mbed_official	324:406fd2029f23	3349	#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV4. /
mbed_official	324:406fd2029f23	3350	#define BS_SIM_CLKDIV1_OUTDIV4 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. /
mbed_official	324:406fd2029f23	3351
mbed_official	324:406fd2029f23	3352	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. /
mbed_official	324:406fd2029f23	3353	#define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4)
mbed_official	324:406fd2029f23	3354
mbed_official	324:406fd2029f23	3355	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. /
mbed_official	324:406fd2029f23	3356	#define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4)
mbed_official	324:406fd2029f23	3357
mbed_official	324:406fd2029f23	3358	/! @brief Set the OUTDIV4 field to a new value. /
mbed_official	324:406fd2029f23	3359	#define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) \| BF_SIM_CLKDIV1_OUTDIV4(v)))
mbed_official	324:406fd2029f23	3360	/@}/
mbed_official	324:406fd2029f23	3361
mbed_official	324:406fd2029f23	3362	/*!
mbed_official	324:406fd2029f23	3363	* @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
mbed_official	324:406fd2029f23	3364	*
mbed_official	324:406fd2029f23	3365	* This field sets the divide value for the FlexBus clock (external pin FB_CLK)
mbed_official	324:406fd2029f23	3366	* from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
mbed_official	324:406fd2029f23	3367	* depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
mbed_official	324:406fd2029f23	3368	* divide of the system clock frequency.
mbed_official	324:406fd2029f23	3369	*
mbed_official	324:406fd2029f23	3370	* Values:
mbed_official	324:406fd2029f23	3371	* - 0000 - Divide-by-1.
mbed_official	324:406fd2029f23	3372	* - 0001 - Divide-by-2.
mbed_official	324:406fd2029f23	3373	* - 0010 - Divide-by-3.
mbed_official	324:406fd2029f23	3374	* - 0011 - Divide-by-4.
mbed_official	324:406fd2029f23	3375	* - 0100 - Divide-by-5.
mbed_official	324:406fd2029f23	3376	* - 0101 - Divide-by-6.
mbed_official	324:406fd2029f23	3377	* - 0110 - Divide-by-7.
mbed_official	324:406fd2029f23	3378	* - 0111 - Divide-by-8.
mbed_official	324:406fd2029f23	3379	* - 1000 - Divide-by-9.
mbed_official	324:406fd2029f23	3380	* - 1001 - Divide-by-10.
mbed_official	324:406fd2029f23	3381	* - 1010 - Divide-by-11.
mbed_official	324:406fd2029f23	3382	* - 1011 - Divide-by-12.
mbed_official	324:406fd2029f23	3383	* - 1100 - Divide-by-13.
mbed_official	324:406fd2029f23	3384	* - 1101 - Divide-by-14.
mbed_official	324:406fd2029f23	3385	* - 1110 - Divide-by-15.
mbed_official	324:406fd2029f23	3386	* - 1111 - Divide-by-16.
mbed_official	324:406fd2029f23	3387	*/
mbed_official	324:406fd2029f23	3388	/@{/
mbed_official	324:406fd2029f23	3389	#define BP_SIM_CLKDIV1_OUTDIV3 (20U) /!< Bit position for SIM_CLKDIV1_OUTDIV3. /
mbed_official	324:406fd2029f23	3390	#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV3. /
mbed_official	324:406fd2029f23	3391	#define BS_SIM_CLKDIV1_OUTDIV3 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. /
mbed_official	324:406fd2029f23	3392
mbed_official	324:406fd2029f23	3393	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. /
mbed_official	324:406fd2029f23	3394	#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3)
mbed_official	324:406fd2029f23	3395
mbed_official	324:406fd2029f23	3396	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. /
mbed_official	324:406fd2029f23	3397	#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3)
mbed_official	324:406fd2029f23	3398
mbed_official	324:406fd2029f23	3399	/! @brief Set the OUTDIV3 field to a new value. /
mbed_official	324:406fd2029f23	3400	#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) \| BF_SIM_CLKDIV1_OUTDIV3(v)))
mbed_official	324:406fd2029f23	3401	/@}/
mbed_official	324:406fd2029f23	3402
mbed_official	324:406fd2029f23	3403	/*!
mbed_official	324:406fd2029f23	3404	* @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
mbed_official	324:406fd2029f23	3405	*
mbed_official	324:406fd2029f23	3406	* This field sets the divide value for the bus clock from MCGOUTCLK. At the end
mbed_official	324:406fd2029f23	3407	* of reset, it is loaded with either 0000 or 0111 depending on
mbed_official	324:406fd2029f23	3408	* FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
mbed_official	324:406fd2029f23	3409	* frequency.
mbed_official	324:406fd2029f23	3410	*
mbed_official	324:406fd2029f23	3411	* Values:
mbed_official	324:406fd2029f23	3412	* - 0000 - Divide-by-1.
mbed_official	324:406fd2029f23	3413	* - 0001 - Divide-by-2.
mbed_official	324:406fd2029f23	3414	* - 0010 - Divide-by-3.
mbed_official	324:406fd2029f23	3415	* - 0011 - Divide-by-4.
mbed_official	324:406fd2029f23	3416	* - 0100 - Divide-by-5.
mbed_official	324:406fd2029f23	3417	* - 0101 - Divide-by-6.
mbed_official	324:406fd2029f23	3418	* - 0110 - Divide-by-7.
mbed_official	324:406fd2029f23	3419	* - 0111 - Divide-by-8.
mbed_official	324:406fd2029f23	3420	* - 1000 - Divide-by-9.
mbed_official	324:406fd2029f23	3421	* - 1001 - Divide-by-10.
mbed_official	324:406fd2029f23	3422	* - 1010 - Divide-by-11.
mbed_official	324:406fd2029f23	3423	* - 1011 - Divide-by-12.
mbed_official	324:406fd2029f23	3424	* - 1100 - Divide-by-13.
mbed_official	324:406fd2029f23	3425	* - 1101 - Divide-by-14.
mbed_official	324:406fd2029f23	3426	* - 1110 - Divide-by-15.
mbed_official	324:406fd2029f23	3427	* - 1111 - Divide-by-16.
mbed_official	324:406fd2029f23	3428	*/
mbed_official	324:406fd2029f23	3429	/@{/
mbed_official	324:406fd2029f23	3430	#define BP_SIM_CLKDIV1_OUTDIV2 (24U) /!< Bit position for SIM_CLKDIV1_OUTDIV2. /
mbed_official	324:406fd2029f23	3431	#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV2. /
mbed_official	324:406fd2029f23	3432	#define BS_SIM_CLKDIV1_OUTDIV2 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. /
mbed_official	324:406fd2029f23	3433
mbed_official	324:406fd2029f23	3434	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. /
mbed_official	324:406fd2029f23	3435	#define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2)
mbed_official	324:406fd2029f23	3436
mbed_official	324:406fd2029f23	3437	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. /
mbed_official	324:406fd2029f23	3438	#define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2)
mbed_official	324:406fd2029f23	3439
mbed_official	324:406fd2029f23	3440	/! @brief Set the OUTDIV2 field to a new value. /
mbed_official	324:406fd2029f23	3441	#define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) \| BF_SIM_CLKDIV1_OUTDIV2(v)))
mbed_official	324:406fd2029f23	3442	/@}/
mbed_official	324:406fd2029f23	3443
mbed_official	324:406fd2029f23	3444	/*!
mbed_official	324:406fd2029f23	3445	* @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
mbed_official	324:406fd2029f23	3446	*
mbed_official	324:406fd2029f23	3447	* This field sets the divide value for the core/system clock from MCGOUTCLK. At
mbed_official	324:406fd2029f23	3448	* the end of reset, it is loaded with either 0000 or 0111 depending on
mbed_official	324:406fd2029f23	3449	* FTF_FOPT[LPBOOT].
mbed_official	324:406fd2029f23	3450	*
mbed_official	324:406fd2029f23	3451	* Values:
mbed_official	324:406fd2029f23	3452	* - 0000 - Divide-by-1.
mbed_official	324:406fd2029f23	3453	* - 0001 - Divide-by-2.
mbed_official	324:406fd2029f23	3454	* - 0010 - Divide-by-3.
mbed_official	324:406fd2029f23	3455	* - 0011 - Divide-by-4.
mbed_official	324:406fd2029f23	3456	* - 0100 - Divide-by-5.
mbed_official	324:406fd2029f23	3457	* - 0101 - Divide-by-6.
mbed_official	324:406fd2029f23	3458	* - 0110 - Divide-by-7.
mbed_official	324:406fd2029f23	3459	* - 0111 - Divide-by-8.
mbed_official	324:406fd2029f23	3460	* - 1000 - Divide-by-9.
mbed_official	324:406fd2029f23	3461	* - 1001 - Divide-by-10.
mbed_official	324:406fd2029f23	3462	* - 1010 - Divide-by-11.
mbed_official	324:406fd2029f23	3463	* - 1011 - Divide-by-12.
mbed_official	324:406fd2029f23	3464	* - 1100 - Divide-by-13.
mbed_official	324:406fd2029f23	3465	* - 1101 - Divide-by-14.
mbed_official	324:406fd2029f23	3466	* - 1110 - Divide-by-15.
mbed_official	324:406fd2029f23	3467	* - 1111 - Divide-by-16.
mbed_official	324:406fd2029f23	3468	*/
mbed_official	324:406fd2029f23	3469	/@{/
mbed_official	324:406fd2029f23	3470	#define BP_SIM_CLKDIV1_OUTDIV1 (28U) /!< Bit position for SIM_CLKDIV1_OUTDIV1. /
mbed_official	324:406fd2029f23	3471	#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV1. /
mbed_official	324:406fd2029f23	3472	#define BS_SIM_CLKDIV1_OUTDIV1 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. /
mbed_official	324:406fd2029f23	3473
mbed_official	324:406fd2029f23	3474	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. /
mbed_official	324:406fd2029f23	3475	#define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1)
mbed_official	324:406fd2029f23	3476
mbed_official	324:406fd2029f23	3477	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. /
mbed_official	324:406fd2029f23	3478	#define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1)
mbed_official	324:406fd2029f23	3479
mbed_official	324:406fd2029f23	3480	/! @brief Set the OUTDIV1 field to a new value. /
mbed_official	324:406fd2029f23	3481	#define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) \| BF_SIM_CLKDIV1_OUTDIV1(v)))
mbed_official	324:406fd2029f23	3482	/@}/
mbed_official	324:406fd2029f23	3483
mbed_official	324:406fd2029f23	3484	/*******************************************************************************
mbed_official	324:406fd2029f23	3485	* HW_SIM_CLKDIV2 - System Clock Divider Register 2
mbed_official	324:406fd2029f23	3486	******************************************************************************/
mbed_official	324:406fd2029f23	3487
mbed_official	324:406fd2029f23	3488	/*!
mbed_official	324:406fd2029f23	3489	* @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
mbed_official	324:406fd2029f23	3490	*
mbed_official	324:406fd2029f23	3491	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3492	*/
mbed_official	324:406fd2029f23	3493	typedef union _hw_sim_clkdiv2
mbed_official	324:406fd2029f23	3494	{
mbed_official	324:406fd2029f23	3495	uint32_t U;
mbed_official	324:406fd2029f23	3496	struct _hw_sim_clkdiv2_bitfields
mbed_official	324:406fd2029f23	3497	{
mbed_official	324:406fd2029f23	3498	uint32_t USBFRAC : 1; /!< [0] USB clock divider fraction /
mbed_official	324:406fd2029f23	3499	uint32_t USBDIV : 3; /!< [3:1] USB clock divider divisor /
mbed_official	324:406fd2029f23	3500	uint32_t RESERVED0 : 28; /!< [31:4] /
mbed_official	324:406fd2029f23	3501	} B;
mbed_official	324:406fd2029f23	3502	} hw_sim_clkdiv2_t;
mbed_official	324:406fd2029f23	3503
mbed_official	324:406fd2029f23	3504	/*!
mbed_official	324:406fd2029f23	3505	* @name Constants and macros for entire SIM_CLKDIV2 register
mbed_official	324:406fd2029f23	3506	*/
mbed_official	324:406fd2029f23	3507	/@{/
mbed_official	324:406fd2029f23	3508	#define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U)
mbed_official	324:406fd2029f23	3509
mbed_official	324:406fd2029f23	3510	#define HW_SIM_CLKDIV2(x) ((__IO hw_sim_clkdiv2_t ) HW_SIM_CLKDIV2_ADDR(x))
mbed_official	324:406fd2029f23	3511	#define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U)
mbed_official	324:406fd2029f23	3512	#define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v))
mbed_official	324:406fd2029f23	3513	#define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3514	#define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3515	#define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3516	/@}/
mbed_official	324:406fd2029f23	3517
mbed_official	324:406fd2029f23	3518	/*
mbed_official	324:406fd2029f23	3519	* Constants & macros for individual SIM_CLKDIV2 bitfields
mbed_official	324:406fd2029f23	3520	*/
mbed_official	324:406fd2029f23	3521
mbed_official	324:406fd2029f23	3522	/*!
mbed_official	324:406fd2029f23	3523	* @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
mbed_official	324:406fd2029f23	3524	*
mbed_official	324:406fd2029f23	3525	* This field sets the fraction multiply value for the fractional clock divider
mbed_official	324:406fd2029f23	3526	* when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
mbed_official	324:406fd2029f23	3527	* 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
mbed_official	324:406fd2029f23	3528	*/
mbed_official	324:406fd2029f23	3529	/@{/
mbed_official	324:406fd2029f23	3530	#define BP_SIM_CLKDIV2_USBFRAC (0U) /!< Bit position for SIM_CLKDIV2_USBFRAC. /
mbed_official	324:406fd2029f23	3531	#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /!< Bit mask for SIM_CLKDIV2_USBFRAC. /
mbed_official	324:406fd2029f23	3532	#define BS_SIM_CLKDIV2_USBFRAC (1U) /!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. /
mbed_official	324:406fd2029f23	3533
mbed_official	324:406fd2029f23	3534	/! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. /
mbed_official	324:406fd2029f23	3535	#define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC))
mbed_official	324:406fd2029f23	3536
mbed_official	324:406fd2029f23	3537	/! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. /
mbed_official	324:406fd2029f23	3538	#define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC)
mbed_official	324:406fd2029f23	3539
mbed_official	324:406fd2029f23	3540	/! @brief Set the USBFRAC field to a new value. /
mbed_official	324:406fd2029f23	3541	#define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v))
mbed_official	324:406fd2029f23	3542	/@}/
mbed_official	324:406fd2029f23	3543
mbed_official	324:406fd2029f23	3544	/*!
mbed_official	324:406fd2029f23	3545	* @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
mbed_official	324:406fd2029f23	3546	*
mbed_official	324:406fd2029f23	3547	* This field sets the divide value for the fractional clock divider when the
mbed_official	324:406fd2029f23	3548	* MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
mbed_official	324:406fd2029f23	3549	* output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
mbed_official	324:406fd2029f23	3550	*/
mbed_official	324:406fd2029f23	3551	/@{/
mbed_official	324:406fd2029f23	3552	#define BP_SIM_CLKDIV2_USBDIV (1U) /!< Bit position for SIM_CLKDIV2_USBDIV. /
mbed_official	324:406fd2029f23	3553	#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /!< Bit mask for SIM_CLKDIV2_USBDIV. /
mbed_official	324:406fd2029f23	3554	#define BS_SIM_CLKDIV2_USBDIV (3U) /!< Bit field size in bits for SIM_CLKDIV2_USBDIV. /
mbed_official	324:406fd2029f23	3555
mbed_official	324:406fd2029f23	3556	/! @brief Read current value of the SIM_CLKDIV2_USBDIV field. /
mbed_official	324:406fd2029f23	3557	#define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV)
mbed_official	324:406fd2029f23	3558
mbed_official	324:406fd2029f23	3559	/! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. /
mbed_official	324:406fd2029f23	3560	#define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV)
mbed_official	324:406fd2029f23	3561
mbed_official	324:406fd2029f23	3562	/! @brief Set the USBDIV field to a new value. /
mbed_official	324:406fd2029f23	3563	#define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) \| BF_SIM_CLKDIV2_USBDIV(v)))
mbed_official	324:406fd2029f23	3564	/@}/
mbed_official	324:406fd2029f23	3565
mbed_official	324:406fd2029f23	3566	/*******************************************************************************
mbed_official	324:406fd2029f23	3567	* HW_SIM_FCFG1 - Flash Configuration Register 1
mbed_official	324:406fd2029f23	3568	******************************************************************************/
mbed_official	324:406fd2029f23	3569
mbed_official	324:406fd2029f23	3570	/*!
mbed_official	324:406fd2029f23	3571	* @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
mbed_official	324:406fd2029f23	3572	*
mbed_official	324:406fd2029f23	3573	* Reset value: 0xFF0F0F00U
mbed_official	324:406fd2029f23	3574	*
mbed_official	324:406fd2029f23	3575	* For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
mbed_official	324:406fd2029f23	3576	* user programming in user IFR via the PGMPART flash command. For devices with
mbed_official	324:406fd2029f23	3577	* program flash only:
mbed_official	324:406fd2029f23	3578	*/
mbed_official	324:406fd2029f23	3579	typedef union _hw_sim_fcfg1
mbed_official	324:406fd2029f23	3580	{
mbed_official	324:406fd2029f23	3581	uint32_t U;
mbed_official	324:406fd2029f23	3582	struct _hw_sim_fcfg1_bitfields
mbed_official	324:406fd2029f23	3583	{
mbed_official	324:406fd2029f23	3584	uint32_t FLASHDIS : 1; /!< [0] Flash Disable /
mbed_official	324:406fd2029f23	3585	uint32_t FLASHDOZE : 1; /!< [1] Flash Doze /
mbed_official	324:406fd2029f23	3586	uint32_t RESERVED0 : 6; /!< [7:2] /
mbed_official	324:406fd2029f23	3587	uint32_t DEPART : 4; /!< [11:8] FlexNVM partition /
mbed_official	324:406fd2029f23	3588	uint32_t RESERVED1 : 4; /!< [15:12] /
mbed_official	324:406fd2029f23	3589	uint32_t EESIZE : 4; /!< [19:16] EEPROM size /
mbed_official	324:406fd2029f23	3590	uint32_t RESERVED2 : 4; /!< [23:20] /
mbed_official	324:406fd2029f23	3591	uint32_t PFSIZE : 4; /!< [27:24] Program flash size /
mbed_official	324:406fd2029f23	3592	uint32_t NVMSIZE : 4; /!< [31:28] FlexNVM size /
mbed_official	324:406fd2029f23	3593	} B;
mbed_official	324:406fd2029f23	3594	} hw_sim_fcfg1_t;
mbed_official	324:406fd2029f23	3595
mbed_official	324:406fd2029f23	3596	/*!
mbed_official	324:406fd2029f23	3597	* @name Constants and macros for entire SIM_FCFG1 register
mbed_official	324:406fd2029f23	3598	*/
mbed_official	324:406fd2029f23	3599	/@{/
mbed_official	324:406fd2029f23	3600	#define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU)
mbed_official	324:406fd2029f23	3601
mbed_official	324:406fd2029f23	3602	#define HW_SIM_FCFG1(x) ((__IO hw_sim_fcfg1_t ) HW_SIM_FCFG1_ADDR(x))
mbed_official	324:406fd2029f23	3603	#define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U)
mbed_official	324:406fd2029f23	3604	#define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v))
mbed_official	324:406fd2029f23	3605	#define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3606	#define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3607	#define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3608	/@}/
mbed_official	324:406fd2029f23	3609
mbed_official	324:406fd2029f23	3610	/*
mbed_official	324:406fd2029f23	3611	* Constants & macros for individual SIM_FCFG1 bitfields
mbed_official	324:406fd2029f23	3612	*/
mbed_official	324:406fd2029f23	3613
mbed_official	324:406fd2029f23	3614	/*!
mbed_official	324:406fd2029f23	3615	* @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
mbed_official	324:406fd2029f23	3616	*
mbed_official	324:406fd2029f23	3617	* Flash accesses are disabled (and generate a bus error) and the Flash memory
mbed_official	324:406fd2029f23	3618	* is placed in a low power state. This bit should not be changed during VLP
mbed_official	324:406fd2029f23	3619	* modes. Relocate the interrupt vectors out of Flash memory before disabling the
mbed_official	324:406fd2029f23	3620	* Flash.
mbed_official	324:406fd2029f23	3621	*
mbed_official	324:406fd2029f23	3622	* Values:
mbed_official	324:406fd2029f23	3623	* - 0 - Flash is enabled
mbed_official	324:406fd2029f23	3624	* - 1 - Flash is disabled
mbed_official	324:406fd2029f23	3625	*/
mbed_official	324:406fd2029f23	3626	/@{/
mbed_official	324:406fd2029f23	3627	#define BP_SIM_FCFG1_FLASHDIS (0U) /!< Bit position for SIM_FCFG1_FLASHDIS. /
mbed_official	324:406fd2029f23	3628	#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /!< Bit mask for SIM_FCFG1_FLASHDIS. /
mbed_official	324:406fd2029f23	3629	#define BS_SIM_FCFG1_FLASHDIS (1U) /!< Bit field size in bits for SIM_FCFG1_FLASHDIS. /
mbed_official	324:406fd2029f23	3630
mbed_official	324:406fd2029f23	3631	/! @brief Read current value of the SIM_FCFG1_FLASHDIS field. /
mbed_official	324:406fd2029f23	3632	#define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS))
mbed_official	324:406fd2029f23	3633
mbed_official	324:406fd2029f23	3634	/! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. /
mbed_official	324:406fd2029f23	3635	#define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS)
mbed_official	324:406fd2029f23	3636
mbed_official	324:406fd2029f23	3637	/! @brief Set the FLASHDIS field to a new value. /
mbed_official	324:406fd2029f23	3638	#define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v))
mbed_official	324:406fd2029f23	3639	/@}/
mbed_official	324:406fd2029f23	3640
mbed_official	324:406fd2029f23	3641	/*!
mbed_official	324:406fd2029f23	3642	* @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
mbed_official	324:406fd2029f23	3643	*
mbed_official	324:406fd2029f23	3644	* When set, Flash memory is disabled for the duration of Wait mode. An attempt
mbed_official	324:406fd2029f23	3645	* by the DMA or other bus master to access the Flash when the Flash is disabled
mbed_official	324:406fd2029f23	3646	* will result in a bus error. This bit should be clear during VLP modes. The
mbed_official	324:406fd2029f23	3647	* Flash will be automatically enabled again at the end of Wait mode so interrupt
mbed_official	324:406fd2029f23	3648	* vectors do not need to be relocated out of Flash memory. The wakeup time from
mbed_official	324:406fd2029f23	3649	* Wait mode is extended when this bit is set.
mbed_official	324:406fd2029f23	3650	*
mbed_official	324:406fd2029f23	3651	* Values:
mbed_official	324:406fd2029f23	3652	* - 0 - Flash remains enabled during Wait mode
mbed_official	324:406fd2029f23	3653	* - 1 - Flash is disabled for the duration of Wait mode
mbed_official	324:406fd2029f23	3654	*/
mbed_official	324:406fd2029f23	3655	/@{/
mbed_official	324:406fd2029f23	3656	#define BP_SIM_FCFG1_FLASHDOZE (1U) /!< Bit position for SIM_FCFG1_FLASHDOZE. /
mbed_official	324:406fd2029f23	3657	#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /!< Bit mask for SIM_FCFG1_FLASHDOZE. /
mbed_official	324:406fd2029f23	3658	#define BS_SIM_FCFG1_FLASHDOZE (1U) /!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. /
mbed_official	324:406fd2029f23	3659
mbed_official	324:406fd2029f23	3660	/! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. /
mbed_official	324:406fd2029f23	3661	#define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE))
mbed_official	324:406fd2029f23	3662
mbed_official	324:406fd2029f23	3663	/! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. /
mbed_official	324:406fd2029f23	3664	#define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE)
mbed_official	324:406fd2029f23	3665
mbed_official	324:406fd2029f23	3666	/! @brief Set the FLASHDOZE field to a new value. /
mbed_official	324:406fd2029f23	3667	#define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v))
mbed_official	324:406fd2029f23	3668	/@}/
mbed_official	324:406fd2029f23	3669
mbed_official	324:406fd2029f23	3670	/*!
mbed_official	324:406fd2029f23	3671	* @name Register SIM_FCFG1, field DEPART[11:8] (RO)
mbed_official	324:406fd2029f23	3672	*
mbed_official	324:406fd2029f23	3673	* For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
mbed_official	324:406fd2029f23	3674	* description in FTFE chapter. For devices without FlexNVM: Reserved
mbed_official	324:406fd2029f23	3675	*/
mbed_official	324:406fd2029f23	3676	/@{/
mbed_official	324:406fd2029f23	3677	#define BP_SIM_FCFG1_DEPART (8U) /!< Bit position for SIM_FCFG1_DEPART. /
mbed_official	324:406fd2029f23	3678	#define BM_SIM_FCFG1_DEPART (0x00000F00U) /!< Bit mask for SIM_FCFG1_DEPART. /
mbed_official	324:406fd2029f23	3679	#define BS_SIM_FCFG1_DEPART (4U) /!< Bit field size in bits for SIM_FCFG1_DEPART. /
mbed_official	324:406fd2029f23	3680
mbed_official	324:406fd2029f23	3681	/! @brief Read current value of the SIM_FCFG1_DEPART field. /
mbed_official	324:406fd2029f23	3682	#define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART)
mbed_official	324:406fd2029f23	3683	/@}/
mbed_official	324:406fd2029f23	3684
mbed_official	324:406fd2029f23	3685	/*!
mbed_official	324:406fd2029f23	3686	* @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
mbed_official	324:406fd2029f23	3687	*
mbed_official	324:406fd2029f23	3688	* EEPROM data size .
mbed_official	324:406fd2029f23	3689	*
mbed_official	324:406fd2029f23	3690	* Values:
mbed_official	324:406fd2029f23	3691	* - 0000 - 16 KB
mbed_official	324:406fd2029f23	3692	* - 0001 - 8 KB
mbed_official	324:406fd2029f23	3693	* - 0010 - 4 KB
mbed_official	324:406fd2029f23	3694	* - 0011 - 2 KB
mbed_official	324:406fd2029f23	3695	* - 0100 - 1 KB
mbed_official	324:406fd2029f23	3696	* - 0101 - 512 Bytes
mbed_official	324:406fd2029f23	3697	* - 0110 - 256 Bytes
mbed_official	324:406fd2029f23	3698	* - 0111 - 128 Bytes
mbed_official	324:406fd2029f23	3699	* - 1000 - 64 Bytes
mbed_official	324:406fd2029f23	3700	* - 1001 - 32 Bytes
mbed_official	324:406fd2029f23	3701	* - 1111 - 0 Bytes
mbed_official	324:406fd2029f23	3702	*/
mbed_official	324:406fd2029f23	3703	/@{/
mbed_official	324:406fd2029f23	3704	#define BP_SIM_FCFG1_EESIZE (16U) /!< Bit position for SIM_FCFG1_EESIZE. /
mbed_official	324:406fd2029f23	3705	#define BM_SIM_FCFG1_EESIZE (0x000F0000U) /!< Bit mask for SIM_FCFG1_EESIZE. /
mbed_official	324:406fd2029f23	3706	#define BS_SIM_FCFG1_EESIZE (4U) /!< Bit field size in bits for SIM_FCFG1_EESIZE. /
mbed_official	324:406fd2029f23	3707
mbed_official	324:406fd2029f23	3708	/! @brief Read current value of the SIM_FCFG1_EESIZE field. /
mbed_official	324:406fd2029f23	3709	#define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE)
mbed_official	324:406fd2029f23	3710	/@}/
mbed_official	324:406fd2029f23	3711
mbed_official	324:406fd2029f23	3712	/*!
mbed_official	324:406fd2029f23	3713	* @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
mbed_official	324:406fd2029f23	3714	*
mbed_official	324:406fd2029f23	3715	* This field specifies the amount of program flash memory available on the
mbed_official	324:406fd2029f23	3716	* device . Undefined values are reserved.
mbed_official	324:406fd2029f23	3717	*
mbed_official	324:406fd2029f23	3718	* Values:
mbed_official	324:406fd2029f23	3719	* - 0011 - 32 KB of program flash memory
mbed_official	324:406fd2029f23	3720	* - 0101 - 64 KB of program flash memory
mbed_official	324:406fd2029f23	3721	* - 0111 - 128 KB of program flash memory
mbed_official	324:406fd2029f23	3722	* - 1001 - 256 KB of program flash memory
mbed_official	324:406fd2029f23	3723	* - 1011 - 512 KB of program flash memory
mbed_official	324:406fd2029f23	3724	* - 1101 - 1024 KB of program flash memory
mbed_official	324:406fd2029f23	3725	* - 1111 - 1024 KB of program flash memory
mbed_official	324:406fd2029f23	3726	*/
mbed_official	324:406fd2029f23	3727	/@{/
mbed_official	324:406fd2029f23	3728	#define BP_SIM_FCFG1_PFSIZE (24U) /!< Bit position for SIM_FCFG1_PFSIZE. /
mbed_official	324:406fd2029f23	3729	#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /!< Bit mask for SIM_FCFG1_PFSIZE. /
mbed_official	324:406fd2029f23	3730	#define BS_SIM_FCFG1_PFSIZE (4U) /!< Bit field size in bits for SIM_FCFG1_PFSIZE. /
mbed_official	324:406fd2029f23	3731
mbed_official	324:406fd2029f23	3732	/! @brief Read current value of the SIM_FCFG1_PFSIZE field. /
mbed_official	324:406fd2029f23	3733	#define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE)
mbed_official	324:406fd2029f23	3734	/@}/
mbed_official	324:406fd2029f23	3735
mbed_official	324:406fd2029f23	3736	/*!
mbed_official	324:406fd2029f23	3737	* @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
mbed_official	324:406fd2029f23	3738	*
mbed_official	324:406fd2029f23	3739	* This field specifies the amount of FlexNVM memory available on the device .
mbed_official	324:406fd2029f23	3740	* Undefined values are reserved.
mbed_official	324:406fd2029f23	3741	*
mbed_official	324:406fd2029f23	3742	* Values:
mbed_official	324:406fd2029f23	3743	* - 0000 - 0 KB of FlexNVM
mbed_official	324:406fd2029f23	3744	* - 0011 - 32 KB of FlexNVM
mbed_official	324:406fd2029f23	3745	* - 0101 - 64 KB of FlexNVM
mbed_official	324:406fd2029f23	3746	* - 0111 - 128 KB of FlexNVM
mbed_official	324:406fd2029f23	3747	* - 1001 - 256 KB of FlexNVM
mbed_official	324:406fd2029f23	3748	* - 1011 - 512 KB of FlexNVM
mbed_official	324:406fd2029f23	3749	* - 1111 - 512 KB of FlexNVM
mbed_official	324:406fd2029f23	3750	*/
mbed_official	324:406fd2029f23	3751	/@{/
mbed_official	324:406fd2029f23	3752	#define BP_SIM_FCFG1_NVMSIZE (28U) /!< Bit position for SIM_FCFG1_NVMSIZE. /
mbed_official	324:406fd2029f23	3753	#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /!< Bit mask for SIM_FCFG1_NVMSIZE. /
mbed_official	324:406fd2029f23	3754	#define BS_SIM_FCFG1_NVMSIZE (4U) /!< Bit field size in bits for SIM_FCFG1_NVMSIZE. /
mbed_official	324:406fd2029f23	3755
mbed_official	324:406fd2029f23	3756	/! @brief Read current value of the SIM_FCFG1_NVMSIZE field. /
mbed_official	324:406fd2029f23	3757	#define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE)
mbed_official	324:406fd2029f23	3758	/@}/
mbed_official	324:406fd2029f23	3759
mbed_official	324:406fd2029f23	3760	/*******************************************************************************
mbed_official	324:406fd2029f23	3761	* HW_SIM_FCFG2 - Flash Configuration Register 2
mbed_official	324:406fd2029f23	3762	******************************************************************************/
mbed_official	324:406fd2029f23	3763
mbed_official	324:406fd2029f23	3764	/*!
mbed_official	324:406fd2029f23	3765	* @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
mbed_official	324:406fd2029f23	3766	*
mbed_official	324:406fd2029f23	3767	* Reset value: 0x7F7F0000U
mbed_official	324:406fd2029f23	3768	*/
mbed_official	324:406fd2029f23	3769	typedef union _hw_sim_fcfg2
mbed_official	324:406fd2029f23	3770	{
mbed_official	324:406fd2029f23	3771	uint32_t U;
mbed_official	324:406fd2029f23	3772	struct _hw_sim_fcfg2_bitfields
mbed_official	324:406fd2029f23	3773	{
mbed_official	324:406fd2029f23	3774	uint32_t RESERVED0 : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	3775	uint32_t MAXADDR1 : 7; /!< [22:16] Max address block 1 /
mbed_official	324:406fd2029f23	3776	uint32_t PFLSH : 1; /!< [23] Program flash only /
mbed_official	324:406fd2029f23	3777	uint32_t MAXADDR0 : 7; /!< [30:24] Max address block 0 /
mbed_official	324:406fd2029f23	3778	uint32_t RESERVED1 : 1; /!< [31] /
mbed_official	324:406fd2029f23	3779	} B;
mbed_official	324:406fd2029f23	3780	} hw_sim_fcfg2_t;
mbed_official	324:406fd2029f23	3781
mbed_official	324:406fd2029f23	3782	/*!
mbed_official	324:406fd2029f23	3783	* @name Constants and macros for entire SIM_FCFG2 register
mbed_official	324:406fd2029f23	3784	*/
mbed_official	324:406fd2029f23	3785	/@{/
mbed_official	324:406fd2029f23	3786	#define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U)
mbed_official	324:406fd2029f23	3787
mbed_official	324:406fd2029f23	3788	#define HW_SIM_FCFG2(x) ((__I hw_sim_fcfg2_t ) HW_SIM_FCFG2_ADDR(x))
mbed_official	324:406fd2029f23	3789	#define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U)
mbed_official	324:406fd2029f23	3790	/@}/
mbed_official	324:406fd2029f23	3791
mbed_official	324:406fd2029f23	3792	/*
mbed_official	324:406fd2029f23	3793	* Constants & macros for individual SIM_FCFG2 bitfields
mbed_official	324:406fd2029f23	3794	*/
mbed_official	324:406fd2029f23	3795
mbed_official	324:406fd2029f23	3796	/*!
mbed_official	324:406fd2029f23	3797	* @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
mbed_official	324:406fd2029f23	3798	*
mbed_official	324:406fd2029f23	3799	* For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
mbed_official	324:406fd2029f23	3800	* the FlexNVM base address indicates the first invalid address of the FlexNVM
mbed_official	324:406fd2029f23	3801	* flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
mbed_official	324:406fd2029f23	3802	* FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
mbed_official	324:406fd2029f23	3803	* for a device with 256 KB FlexNVM. For devices with program flash only: This
mbed_official	324:406fd2029f23	3804	* field equals zero if there is only one program flash block, otherwise it equals
mbed_official	324:406fd2029f23	3805	* the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
mbed_official	324:406fd2029f23	3806	* the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
mbed_official	324:406fd2029f23	3807	* the MAXADDR1 value for a device with 512 KB program flash memory across two
mbed_official	324:406fd2029f23	3808	* flash blocks and no FlexNVM.
mbed_official	324:406fd2029f23	3809	*/
mbed_official	324:406fd2029f23	3810	/@{/
mbed_official	324:406fd2029f23	3811	#define BP_SIM_FCFG2_MAXADDR1 (16U) /!< Bit position for SIM_FCFG2_MAXADDR1. /
mbed_official	324:406fd2029f23	3812	#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /!< Bit mask for SIM_FCFG2_MAXADDR1. /
mbed_official	324:406fd2029f23	3813	#define BS_SIM_FCFG2_MAXADDR1 (7U) /!< Bit field size in bits for SIM_FCFG2_MAXADDR1. /
mbed_official	324:406fd2029f23	3814
mbed_official	324:406fd2029f23	3815	/! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. /
mbed_official	324:406fd2029f23	3816	#define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1)
mbed_official	324:406fd2029f23	3817	/@}/
mbed_official	324:406fd2029f23	3818
mbed_official	324:406fd2029f23	3819	/*!
mbed_official	324:406fd2029f23	3820	* @name Register SIM_FCFG2, field PFLSH[23] (RO)
mbed_official	324:406fd2029f23	3821	*
mbed_official	324:406fd2029f23	3822	* For devices with FlexNVM, this bit is always clear. For devices without
mbed_official	324:406fd2029f23	3823	* FlexNVM, this bit is always set.
mbed_official	324:406fd2029f23	3824	*
mbed_official	324:406fd2029f23	3825	* Values:
mbed_official	324:406fd2029f23	3826	* - 0 - Device supports FlexNVM
mbed_official	324:406fd2029f23	3827	* - 1 - Program Flash only, device does not support FlexNVM
mbed_official	324:406fd2029f23	3828	*/
mbed_official	324:406fd2029f23	3829	/@{/
mbed_official	324:406fd2029f23	3830	#define BP_SIM_FCFG2_PFLSH (23U) /!< Bit position for SIM_FCFG2_PFLSH. /
mbed_official	324:406fd2029f23	3831	#define BM_SIM_FCFG2_PFLSH (0x00800000U) /!< Bit mask for SIM_FCFG2_PFLSH. /
mbed_official	324:406fd2029f23	3832	#define BS_SIM_FCFG2_PFLSH (1U) /!< Bit field size in bits for SIM_FCFG2_PFLSH. /
mbed_official	324:406fd2029f23	3833
mbed_official	324:406fd2029f23	3834	/! @brief Read current value of the SIM_FCFG2_PFLSH field. /
mbed_official	324:406fd2029f23	3835	#define BR_SIM_FCFG2_PFLSH(x) (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH))
mbed_official	324:406fd2029f23	3836	/@}/
mbed_official	324:406fd2029f23	3837
mbed_official	324:406fd2029f23	3838	/*!
mbed_official	324:406fd2029f23	3839	* @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
mbed_official	324:406fd2029f23	3840	*
mbed_official	324:406fd2029f23	3841	* This field concatenated with 13 trailing zeros indicates the first invalid
mbed_official	324:406fd2029f23	3842	* address of each program flash block. For example, if MAXADDR0 = 0x20 the first
mbed_official	324:406fd2029f23	3843	* invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
mbed_official	324:406fd2029f23	3844	* value for a device with 256 KB program flash in flash block 0.
mbed_official	324:406fd2029f23	3845	*/
mbed_official	324:406fd2029f23	3846	/@{/
mbed_official	324:406fd2029f23	3847	#define BP_SIM_FCFG2_MAXADDR0 (24U) /!< Bit position for SIM_FCFG2_MAXADDR0. /
mbed_official	324:406fd2029f23	3848	#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /!< Bit mask for SIM_FCFG2_MAXADDR0. /
mbed_official	324:406fd2029f23	3849	#define BS_SIM_FCFG2_MAXADDR0 (7U) /!< Bit field size in bits for SIM_FCFG2_MAXADDR0. /
mbed_official	324:406fd2029f23	3850
mbed_official	324:406fd2029f23	3851	/! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. /
mbed_official	324:406fd2029f23	3852	#define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0)
mbed_official	324:406fd2029f23	3853	/@}/
mbed_official	324:406fd2029f23	3854
mbed_official	324:406fd2029f23	3855	/*******************************************************************************
mbed_official	324:406fd2029f23	3856	* HW_SIM_UIDH - Unique Identification Register High
mbed_official	324:406fd2029f23	3857	******************************************************************************/
mbed_official	324:406fd2029f23	3858
mbed_official	324:406fd2029f23	3859	/*!
mbed_official	324:406fd2029f23	3860	* @brief HW_SIM_UIDH - Unique Identification Register High (RO)
mbed_official	324:406fd2029f23	3861	*
mbed_official	324:406fd2029f23	3862	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3863	*/
mbed_official	324:406fd2029f23	3864	typedef union _hw_sim_uidh
mbed_official	324:406fd2029f23	3865	{
mbed_official	324:406fd2029f23	3866	uint32_t U;
mbed_official	324:406fd2029f23	3867	struct _hw_sim_uidh_bitfields
mbed_official	324:406fd2029f23	3868	{
mbed_official	324:406fd2029f23	3869	uint32_t UID : 32; /!< [31:0] Unique Identification /
mbed_official	324:406fd2029f23	3870	} B;
mbed_official	324:406fd2029f23	3871	} hw_sim_uidh_t;
mbed_official	324:406fd2029f23	3872
mbed_official	324:406fd2029f23	3873	/*!
mbed_official	324:406fd2029f23	3874	* @name Constants and macros for entire SIM_UIDH register
mbed_official	324:406fd2029f23	3875	*/
mbed_official	324:406fd2029f23	3876	/@{/
mbed_official	324:406fd2029f23	3877	#define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U)
mbed_official	324:406fd2029f23	3878
mbed_official	324:406fd2029f23	3879	#define HW_SIM_UIDH(x) ((__I hw_sim_uidh_t ) HW_SIM_UIDH_ADDR(x))
mbed_official	324:406fd2029f23	3880	#define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U)
mbed_official	324:406fd2029f23	3881	/@}/
mbed_official	324:406fd2029f23	3882
mbed_official	324:406fd2029f23	3883	/*
mbed_official	324:406fd2029f23	3884	* Constants & macros for individual SIM_UIDH bitfields
mbed_official	324:406fd2029f23	3885	*/
mbed_official	324:406fd2029f23	3886
mbed_official	324:406fd2029f23	3887	/*!
mbed_official	324:406fd2029f23	3888	* @name Register SIM_UIDH, field UID[31:0] (RO)
mbed_official	324:406fd2029f23	3889	*
mbed_official	324:406fd2029f23	3890	* Unique identification for the device.
mbed_official	324:406fd2029f23	3891	*/
mbed_official	324:406fd2029f23	3892	/@{/
mbed_official	324:406fd2029f23	3893	#define BP_SIM_UIDH_UID (0U) /!< Bit position for SIM_UIDH_UID. /
mbed_official	324:406fd2029f23	3894	#define BM_SIM_UIDH_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDH_UID. /
mbed_official	324:406fd2029f23	3895	#define BS_SIM_UIDH_UID (32U) /!< Bit field size in bits for SIM_UIDH_UID. /
mbed_official	324:406fd2029f23	3896
mbed_official	324:406fd2029f23	3897	/! @brief Read current value of the SIM_UIDH_UID field. /
mbed_official	324:406fd2029f23	3898	#define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U)
mbed_official	324:406fd2029f23	3899	/@}/
mbed_official	324:406fd2029f23	3900
mbed_official	324:406fd2029f23	3901	/*******************************************************************************
mbed_official	324:406fd2029f23	3902	* HW_SIM_UIDMH - Unique Identification Register Mid-High
mbed_official	324:406fd2029f23	3903	******************************************************************************/
mbed_official	324:406fd2029f23	3904
mbed_official	324:406fd2029f23	3905	/*!
mbed_official	324:406fd2029f23	3906	* @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
mbed_official	324:406fd2029f23	3907	*
mbed_official	324:406fd2029f23	3908	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3909	*/
mbed_official	324:406fd2029f23	3910	typedef union _hw_sim_uidmh
mbed_official	324:406fd2029f23	3911	{
mbed_official	324:406fd2029f23	3912	uint32_t U;
mbed_official	324:406fd2029f23	3913	struct _hw_sim_uidmh_bitfields
mbed_official	324:406fd2029f23	3914	{
mbed_official	324:406fd2029f23	3915	uint32_t UID : 32; /!< [31:0] Unique Identification /
mbed_official	324:406fd2029f23	3916	} B;
mbed_official	324:406fd2029f23	3917	} hw_sim_uidmh_t;
mbed_official	324:406fd2029f23	3918
mbed_official	324:406fd2029f23	3919	/*!
mbed_official	324:406fd2029f23	3920	* @name Constants and macros for entire SIM_UIDMH register
mbed_official	324:406fd2029f23	3921	*/
mbed_official	324:406fd2029f23	3922	/@{/
mbed_official	324:406fd2029f23	3923	#define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U)
mbed_official	324:406fd2029f23	3924
mbed_official	324:406fd2029f23	3925	#define HW_SIM_UIDMH(x) ((__I hw_sim_uidmh_t ) HW_SIM_UIDMH_ADDR(x))
mbed_official	324:406fd2029f23	3926	#define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U)
mbed_official	324:406fd2029f23	3927	/@}/
mbed_official	324:406fd2029f23	3928
mbed_official	324:406fd2029f23	3929	/*
mbed_official	324:406fd2029f23	3930	* Constants & macros for individual SIM_UIDMH bitfields
mbed_official	324:406fd2029f23	3931	*/
mbed_official	324:406fd2029f23	3932
mbed_official	324:406fd2029f23	3933	/*!
mbed_official	324:406fd2029f23	3934	* @name Register SIM_UIDMH, field UID[31:0] (RO)
mbed_official	324:406fd2029f23	3935	*
mbed_official	324:406fd2029f23	3936	* Unique identification for the device.
mbed_official	324:406fd2029f23	3937	*/
mbed_official	324:406fd2029f23	3938	/@{/
mbed_official	324:406fd2029f23	3939	#define BP_SIM_UIDMH_UID (0U) /!< Bit position for SIM_UIDMH_UID. /
mbed_official	324:406fd2029f23	3940	#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDMH_UID. /
mbed_official	324:406fd2029f23	3941	#define BS_SIM_UIDMH_UID (32U) /!< Bit field size in bits for SIM_UIDMH_UID. /
mbed_official	324:406fd2029f23	3942
mbed_official	324:406fd2029f23	3943	/! @brief Read current value of the SIM_UIDMH_UID field. /
mbed_official	324:406fd2029f23	3944	#define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U)
mbed_official	324:406fd2029f23	3945	/@}/
mbed_official	324:406fd2029f23	3946
mbed_official	324:406fd2029f23	3947	/*******************************************************************************
mbed_official	324:406fd2029f23	3948	* HW_SIM_UIDML - Unique Identification Register Mid Low
mbed_official	324:406fd2029f23	3949	******************************************************************************/
mbed_official	324:406fd2029f23	3950
mbed_official	324:406fd2029f23	3951	/*!
mbed_official	324:406fd2029f23	3952	* @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
mbed_official	324:406fd2029f23	3953	*
mbed_official	324:406fd2029f23	3954	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3955	*/
mbed_official	324:406fd2029f23	3956	typedef union _hw_sim_uidml
mbed_official	324:406fd2029f23	3957	{
mbed_official	324:406fd2029f23	3958	uint32_t U;
mbed_official	324:406fd2029f23	3959	struct _hw_sim_uidml_bitfields
mbed_official	324:406fd2029f23	3960	{
mbed_official	324:406fd2029f23	3961	uint32_t UID : 32; /!< [31:0] Unique Identification /
mbed_official	324:406fd2029f23	3962	} B;
mbed_official	324:406fd2029f23	3963	} hw_sim_uidml_t;
mbed_official	324:406fd2029f23	3964
mbed_official	324:406fd2029f23	3965	/*!
mbed_official	324:406fd2029f23	3966	* @name Constants and macros for entire SIM_UIDML register
mbed_official	324:406fd2029f23	3967	*/
mbed_official	324:406fd2029f23	3968	/@{/
mbed_official	324:406fd2029f23	3969	#define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU)
mbed_official	324:406fd2029f23	3970
mbed_official	324:406fd2029f23	3971	#define HW_SIM_UIDML(x) ((__I hw_sim_uidml_t ) HW_SIM_UIDML_ADDR(x))
mbed_official	324:406fd2029f23	3972	#define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U)
mbed_official	324:406fd2029f23	3973	/@}/
mbed_official	324:406fd2029f23	3974
mbed_official	324:406fd2029f23	3975	/*
mbed_official	324:406fd2029f23	3976	* Constants & macros for individual SIM_UIDML bitfields
mbed_official	324:406fd2029f23	3977	*/
mbed_official	324:406fd2029f23	3978
mbed_official	324:406fd2029f23	3979	/*!
mbed_official	324:406fd2029f23	3980	* @name Register SIM_UIDML, field UID[31:0] (RO)
mbed_official	324:406fd2029f23	3981	*
mbed_official	324:406fd2029f23	3982	* Unique identification for the device.
mbed_official	324:406fd2029f23	3983	*/
mbed_official	324:406fd2029f23	3984	/@{/
mbed_official	324:406fd2029f23	3985	#define BP_SIM_UIDML_UID (0U) /!< Bit position for SIM_UIDML_UID. /
mbed_official	324:406fd2029f23	3986	#define BM_SIM_UIDML_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDML_UID. /
mbed_official	324:406fd2029f23	3987	#define BS_SIM_UIDML_UID (32U) /!< Bit field size in bits for SIM_UIDML_UID. /
mbed_official	324:406fd2029f23	3988
mbed_official	324:406fd2029f23	3989	/! @brief Read current value of the SIM_UIDML_UID field. /
mbed_official	324:406fd2029f23	3990	#define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U)
mbed_official	324:406fd2029f23	3991	/@}/
mbed_official	324:406fd2029f23	3992
mbed_official	324:406fd2029f23	3993	/*******************************************************************************
mbed_official	324:406fd2029f23	3994	* HW_SIM_UIDL - Unique Identification Register Low
mbed_official	324:406fd2029f23	3995	******************************************************************************/
mbed_official	324:406fd2029f23	3996
mbed_official	324:406fd2029f23	3997	/*!
mbed_official	324:406fd2029f23	3998	* @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
mbed_official	324:406fd2029f23	3999	*
mbed_official	324:406fd2029f23	4000	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	4001	*/
mbed_official	324:406fd2029f23	4002	typedef union _hw_sim_uidl
mbed_official	324:406fd2029f23	4003	{
mbed_official	324:406fd2029f23	4004	uint32_t U;
mbed_official	324:406fd2029f23	4005	struct _hw_sim_uidl_bitfields
mbed_official	324:406fd2029f23	4006	{
mbed_official	324:406fd2029f23	4007	uint32_t UID : 32; /!< [31:0] Unique Identification /
mbed_official	324:406fd2029f23	4008	} B;
mbed_official	324:406fd2029f23	4009	} hw_sim_uidl_t;
mbed_official	324:406fd2029f23	4010
mbed_official	324:406fd2029f23	4011	/*!
mbed_official	324:406fd2029f23	4012	* @name Constants and macros for entire SIM_UIDL register
mbed_official	324:406fd2029f23	4013	*/
mbed_official	324:406fd2029f23	4014	/@{/
mbed_official	324:406fd2029f23	4015	#define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U)
mbed_official	324:406fd2029f23	4016
mbed_official	324:406fd2029f23	4017	#define HW_SIM_UIDL(x) ((__I hw_sim_uidl_t ) HW_SIM_UIDL_ADDR(x))
mbed_official	324:406fd2029f23	4018	#define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U)
mbed_official	324:406fd2029f23	4019	/@}/
mbed_official	324:406fd2029f23	4020
mbed_official	324:406fd2029f23	4021	/*
mbed_official	324:406fd2029f23	4022	* Constants & macros for individual SIM_UIDL bitfields
mbed_official	324:406fd2029f23	4023	*/
mbed_official	324:406fd2029f23	4024
mbed_official	324:406fd2029f23	4025	/*!
mbed_official	324:406fd2029f23	4026	* @name Register SIM_UIDL, field UID[31:0] (RO)
mbed_official	324:406fd2029f23	4027	*
mbed_official	324:406fd2029f23	4028	* Unique identification for the device.
mbed_official	324:406fd2029f23	4029	*/
mbed_official	324:406fd2029f23	4030	/@{/
mbed_official	324:406fd2029f23	4031	#define BP_SIM_UIDL_UID (0U) /!< Bit position for SIM_UIDL_UID. /
mbed_official	324:406fd2029f23	4032	#define BM_SIM_UIDL_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDL_UID. /
mbed_official	324:406fd2029f23	4033	#define BS_SIM_UIDL_UID (32U) /!< Bit field size in bits for SIM_UIDL_UID. /
mbed_official	324:406fd2029f23	4034
mbed_official	324:406fd2029f23	4035	/! @brief Read current value of the SIM_UIDL_UID field. /
mbed_official	324:406fd2029f23	4036	#define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U)
mbed_official	324:406fd2029f23	4037	/@}/
mbed_official	324:406fd2029f23	4038
mbed_official	324:406fd2029f23	4039	/*******************************************************************************
mbed_official	324:406fd2029f23	4040	* hw_sim_t - module struct
mbed_official	324:406fd2029f23	4041	******************************************************************************/
mbed_official	324:406fd2029f23	4042	/*!
mbed_official	324:406fd2029f23	4043	* @brief All SIM module registers.
mbed_official	324:406fd2029f23	4044	*/
mbed_official	324:406fd2029f23	4045	#pragma pack(1)
mbed_official	324:406fd2029f23	4046	typedef struct _hw_sim
mbed_official	324:406fd2029f23	4047	{
mbed_official	324:406fd2029f23	4048	__IO hw_sim_sopt1_t SOPT1; /!< [0x0] System Options Register 1 /
mbed_official	324:406fd2029f23	4049	__IO hw_sim_sopt1cfg_t SOPT1CFG; /!< [0x4] SOPT1 Configuration Register /
mbed_official	324:406fd2029f23	4050	uint8_t _reserved0[4092];
mbed_official	324:406fd2029f23	4051	__IO hw_sim_sopt2_t SOPT2; /!< [0x1004] System Options Register 2 /
mbed_official	324:406fd2029f23	4052	uint8_t _reserved1[4];
mbed_official	324:406fd2029f23	4053	__IO hw_sim_sopt4_t SOPT4; /!< [0x100C] System Options Register 4 /
mbed_official	324:406fd2029f23	4054	__IO hw_sim_sopt5_t SOPT5; /!< [0x1010] System Options Register 5 /
mbed_official	324:406fd2029f23	4055	uint8_t _reserved2[4];
mbed_official	324:406fd2029f23	4056	__IO hw_sim_sopt7_t SOPT7; /!< [0x1018] System Options Register 7 /
mbed_official	324:406fd2029f23	4057	uint8_t _reserved3[8];
mbed_official	324:406fd2029f23	4058	__I hw_sim_sdid_t SDID; /!< [0x1024] System Device Identification Register /
mbed_official	324:406fd2029f23	4059	__IO hw_sim_scgc1_t SCGC1; /!< [0x1028] System Clock Gating Control Register 1 /
mbed_official	324:406fd2029f23	4060	__IO hw_sim_scgc2_t SCGC2; /!< [0x102C] System Clock Gating Control Register 2 /
mbed_official	324:406fd2029f23	4061	__IO hw_sim_scgc3_t SCGC3; /!< [0x1030] System Clock Gating Control Register 3 /
mbed_official	324:406fd2029f23	4062	__IO hw_sim_scgc4_t SCGC4; /!< [0x1034] System Clock Gating Control Register 4 /
mbed_official	324:406fd2029f23	4063	__IO hw_sim_scgc5_t SCGC5; /!< [0x1038] System Clock Gating Control Register 5 /
mbed_official	324:406fd2029f23	4064	__IO hw_sim_scgc6_t SCGC6; /!< [0x103C] System Clock Gating Control Register 6 /
mbed_official	324:406fd2029f23	4065	__IO hw_sim_scgc7_t SCGC7; /!< [0x1040] System Clock Gating Control Register 7 /
mbed_official	324:406fd2029f23	4066	__IO hw_sim_clkdiv1_t CLKDIV1; /!< [0x1044] System Clock Divider Register 1 /
mbed_official	324:406fd2029f23	4067	__IO hw_sim_clkdiv2_t CLKDIV2; /!< [0x1048] System Clock Divider Register 2 /
mbed_official	324:406fd2029f23	4068	__IO hw_sim_fcfg1_t FCFG1; /!< [0x104C] Flash Configuration Register 1 /
mbed_official	324:406fd2029f23	4069	__I hw_sim_fcfg2_t FCFG2; /!< [0x1050] Flash Configuration Register 2 /
mbed_official	324:406fd2029f23	4070	__I hw_sim_uidh_t UIDH; /!< [0x1054] Unique Identification Register High /
mbed_official	324:406fd2029f23	4071	__I hw_sim_uidmh_t UIDMH; /!< [0x1058] Unique Identification Register Mid-High /
mbed_official	324:406fd2029f23	4072	__I hw_sim_uidml_t UIDML; /!< [0x105C] Unique Identification Register Mid Low /
mbed_official	324:406fd2029f23	4073	__I hw_sim_uidl_t UIDL; /!< [0x1060] Unique Identification Register Low /
mbed_official	324:406fd2029f23	4074	} hw_sim_t;
mbed_official	324:406fd2029f23	4075	#pragma pack()
mbed_official	324:406fd2029f23	4076
mbed_official	324:406fd2029f23	4077	/! @brief Macro to access all SIM registers. /
mbed_official	324:406fd2029f23	4078	/! @param x SIM module instance base address. /
mbed_official	324:406fd2029f23	4079	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	4080	* use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */
mbed_official	324:406fd2029f23	4081	#define HW_SIM(x) ((hw_sim_t )(x))
mbed_official	324:406fd2029f23	4082
mbed_official	324:406fd2029f23	4083	#endif /* __HW_SIM_REGISTERS_H__ */
mbed_official	324:406fd2029f23	4084	/* EOF */