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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_RNG_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_RNG_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 RNG
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Random Number Generator Accelerator
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_RNG_CR - RNGA Control Register
mbed_official 324:406fd2029f23 93 * - HW_RNG_SR - RNGA Status Register
mbed_official 324:406fd2029f23 94 * - HW_RNG_ER - RNGA Entropy Register
mbed_official 324:406fd2029f23 95 * - HW_RNG_OR - RNGA Output Register
mbed_official 324:406fd2029f23 96 *
mbed_official 324:406fd2029f23 97 * - hw_rng_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 98 */
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
mbed_official 324:406fd2029f23 101
mbed_official 324:406fd2029f23 102 /*******************************************************************************
mbed_official 324:406fd2029f23 103 * HW_RNG_CR - RNGA Control Register
mbed_official 324:406fd2029f23 104 ******************************************************************************/
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 /*!
mbed_official 324:406fd2029f23 107 * @brief HW_RNG_CR - RNGA Control Register (RW)
mbed_official 324:406fd2029f23 108 *
mbed_official 324:406fd2029f23 109 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 110 *
mbed_official 324:406fd2029f23 111 * Controls the operation of RNGA.
mbed_official 324:406fd2029f23 112 */
mbed_official 324:406fd2029f23 113 typedef union _hw_rng_cr
mbed_official 324:406fd2029f23 114 {
mbed_official 324:406fd2029f23 115 uint32_t U;
mbed_official 324:406fd2029f23 116 struct _hw_rng_cr_bitfields
mbed_official 324:406fd2029f23 117 {
mbed_official 324:406fd2029f23 118 uint32_t GO : 1; /*!< [0] Go */
mbed_official 324:406fd2029f23 119 uint32_t HA : 1; /*!< [1] High Assurance */
mbed_official 324:406fd2029f23 120 uint32_t INTM : 1; /*!< [2] Interrupt Mask */
mbed_official 324:406fd2029f23 121 uint32_t CLRI : 1; /*!< [3] Clear Interrupt */
mbed_official 324:406fd2029f23 122 uint32_t SLP : 1; /*!< [4] Sleep */
mbed_official 324:406fd2029f23 123 uint32_t RESERVED0 : 27; /*!< [31:5] */
mbed_official 324:406fd2029f23 124 } B;
mbed_official 324:406fd2029f23 125 } hw_rng_cr_t;
mbed_official 324:406fd2029f23 126
mbed_official 324:406fd2029f23 127 /*!
mbed_official 324:406fd2029f23 128 * @name Constants and macros for entire RNG_CR register
mbed_official 324:406fd2029f23 129 */
mbed_official 324:406fd2029f23 130 /*@{*/
mbed_official 324:406fd2029f23 131 #define HW_RNG_CR_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 132
mbed_official 324:406fd2029f23 133 #define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
mbed_official 324:406fd2029f23 134 #define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U)
mbed_official 324:406fd2029f23 135 #define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v))
mbed_official 324:406fd2029f23 136 #define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v)))
mbed_official 324:406fd2029f23 137 #define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 138 #define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 139 /*@}*/
mbed_official 324:406fd2029f23 140
mbed_official 324:406fd2029f23 141 /*
mbed_official 324:406fd2029f23 142 * Constants & macros for individual RNG_CR bitfields
mbed_official 324:406fd2029f23 143 */
mbed_official 324:406fd2029f23 144
mbed_official 324:406fd2029f23 145 /*!
mbed_official 324:406fd2029f23 146 * @name Register RNG_CR, field GO[0] (RW)
mbed_official 324:406fd2029f23 147 *
mbed_official 324:406fd2029f23 148 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
mbed_official 324:406fd2029f23 149 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
mbed_official 324:406fd2029f23 150 * OR[RANDOUT] with data.
mbed_official 324:406fd2029f23 151 *
mbed_official 324:406fd2029f23 152 * Values:
mbed_official 324:406fd2029f23 153 * - 0 - Disabled
mbed_official 324:406fd2029f23 154 * - 1 - Enabled
mbed_official 324:406fd2029f23 155 */
mbed_official 324:406fd2029f23 156 /*@{*/
mbed_official 324:406fd2029f23 157 #define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */
mbed_official 324:406fd2029f23 158 #define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
mbed_official 324:406fd2029f23 159 #define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */
mbed_official 324:406fd2029f23 160
mbed_official 324:406fd2029f23 161 /*! @brief Read current value of the RNG_CR_GO field. */
mbed_official 324:406fd2029f23 162 #define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
mbed_official 324:406fd2029f23 163
mbed_official 324:406fd2029f23 164 /*! @brief Format value for bitfield RNG_CR_GO. */
mbed_official 324:406fd2029f23 165 #define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 /*! @brief Set the GO field to a new value. */
mbed_official 324:406fd2029f23 168 #define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
mbed_official 324:406fd2029f23 169 /*@}*/
mbed_official 324:406fd2029f23 170
mbed_official 324:406fd2029f23 171 /*!
mbed_official 324:406fd2029f23 172 * @name Register RNG_CR, field HA[1] (RW)
mbed_official 324:406fd2029f23 173 *
mbed_official 324:406fd2029f23 174 * Enables notification of security violations (via SR[SECV]). A security
mbed_official 324:406fd2029f23 175 * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
mbed_official 324:406fd2029f23 176 * After enabling notification of security violations, you must reset RNGA to
mbed_official 324:406fd2029f23 177 * disable them again.
mbed_official 324:406fd2029f23 178 *
mbed_official 324:406fd2029f23 179 * Values:
mbed_official 324:406fd2029f23 180 * - 0 - Disabled
mbed_official 324:406fd2029f23 181 * - 1 - Enabled
mbed_official 324:406fd2029f23 182 */
mbed_official 324:406fd2029f23 183 /*@{*/
mbed_official 324:406fd2029f23 184 #define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */
mbed_official 324:406fd2029f23 185 #define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
mbed_official 324:406fd2029f23 186 #define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */
mbed_official 324:406fd2029f23 187
mbed_official 324:406fd2029f23 188 /*! @brief Read current value of the RNG_CR_HA field. */
mbed_official 324:406fd2029f23 189 #define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
mbed_official 324:406fd2029f23 190
mbed_official 324:406fd2029f23 191 /*! @brief Format value for bitfield RNG_CR_HA. */
mbed_official 324:406fd2029f23 192 #define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
mbed_official 324:406fd2029f23 193
mbed_official 324:406fd2029f23 194 /*! @brief Set the HA field to a new value. */
mbed_official 324:406fd2029f23 195 #define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
mbed_official 324:406fd2029f23 196 /*@}*/
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*!
mbed_official 324:406fd2029f23 199 * @name Register RNG_CR, field INTM[2] (RW)
mbed_official 324:406fd2029f23 200 *
mbed_official 324:406fd2029f23 201 * Masks the triggering of an error interrupt to the interrupt controller when
mbed_official 324:406fd2029f23 202 * an OR underflow condition occurs. An OR underflow condition occurs when you
mbed_official 324:406fd2029f23 203 * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
mbed_official 324:406fd2029f23 204 *
mbed_official 324:406fd2029f23 205 * Values:
mbed_official 324:406fd2029f23 206 * - 0 - Not masked
mbed_official 324:406fd2029f23 207 * - 1 - Masked
mbed_official 324:406fd2029f23 208 */
mbed_official 324:406fd2029f23 209 /*@{*/
mbed_official 324:406fd2029f23 210 #define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */
mbed_official 324:406fd2029f23 211 #define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
mbed_official 324:406fd2029f23 212 #define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */
mbed_official 324:406fd2029f23 213
mbed_official 324:406fd2029f23 214 /*! @brief Read current value of the RNG_CR_INTM field. */
mbed_official 324:406fd2029f23 215 #define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
mbed_official 324:406fd2029f23 216
mbed_official 324:406fd2029f23 217 /*! @brief Format value for bitfield RNG_CR_INTM. */
mbed_official 324:406fd2029f23 218 #define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
mbed_official 324:406fd2029f23 219
mbed_official 324:406fd2029f23 220 /*! @brief Set the INTM field to a new value. */
mbed_official 324:406fd2029f23 221 #define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
mbed_official 324:406fd2029f23 222 /*@}*/
mbed_official 324:406fd2029f23 223
mbed_official 324:406fd2029f23 224 /*!
mbed_official 324:406fd2029f23 225 * @name Register RNG_CR, field CLRI[3] (WORZ)
mbed_official 324:406fd2029f23 226 *
mbed_official 324:406fd2029f23 227 * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
mbed_official 324:406fd2029f23 228 *
mbed_official 324:406fd2029f23 229 * Values:
mbed_official 324:406fd2029f23 230 * - 0 - Do not clear the interrupt.
mbed_official 324:406fd2029f23 231 * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
mbed_official 324:406fd2029f23 232 * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
mbed_official 324:406fd2029f23 233 */
mbed_official 324:406fd2029f23 234 /*@{*/
mbed_official 324:406fd2029f23 235 #define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */
mbed_official 324:406fd2029f23 236 #define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
mbed_official 324:406fd2029f23 237 #define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*! @brief Format value for bitfield RNG_CR_CLRI. */
mbed_official 324:406fd2029f23 240 #define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
mbed_official 324:406fd2029f23 241
mbed_official 324:406fd2029f23 242 /*! @brief Set the CLRI field to a new value. */
mbed_official 324:406fd2029f23 243 #define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
mbed_official 324:406fd2029f23 244 /*@}*/
mbed_official 324:406fd2029f23 245
mbed_official 324:406fd2029f23 246 /*!
mbed_official 324:406fd2029f23 247 * @name Register RNG_CR, field SLP[4] (RW)
mbed_official 324:406fd2029f23 248 *
mbed_official 324:406fd2029f23 249 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
mbed_official 324:406fd2029f23 250 * mode by asserting the DOZE signal.
mbed_official 324:406fd2029f23 251 *
mbed_official 324:406fd2029f23 252 * Values:
mbed_official 324:406fd2029f23 253 * - 0 - Normal mode
mbed_official 324:406fd2029f23 254 * - 1 - Sleep (low-power) mode
mbed_official 324:406fd2029f23 255 */
mbed_official 324:406fd2029f23 256 /*@{*/
mbed_official 324:406fd2029f23 257 #define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */
mbed_official 324:406fd2029f23 258 #define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
mbed_official 324:406fd2029f23 259 #define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*! @brief Read current value of the RNG_CR_SLP field. */
mbed_official 324:406fd2029f23 262 #define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
mbed_official 324:406fd2029f23 263
mbed_official 324:406fd2029f23 264 /*! @brief Format value for bitfield RNG_CR_SLP. */
mbed_official 324:406fd2029f23 265 #define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
mbed_official 324:406fd2029f23 266
mbed_official 324:406fd2029f23 267 /*! @brief Set the SLP field to a new value. */
mbed_official 324:406fd2029f23 268 #define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
mbed_official 324:406fd2029f23 269 /*@}*/
mbed_official 324:406fd2029f23 270
mbed_official 324:406fd2029f23 271 /*******************************************************************************
mbed_official 324:406fd2029f23 272 * HW_RNG_SR - RNGA Status Register
mbed_official 324:406fd2029f23 273 ******************************************************************************/
mbed_official 324:406fd2029f23 274
mbed_official 324:406fd2029f23 275 /*!
mbed_official 324:406fd2029f23 276 * @brief HW_RNG_SR - RNGA Status Register (RO)
mbed_official 324:406fd2029f23 277 *
mbed_official 324:406fd2029f23 278 * Reset value: 0x00010000U
mbed_official 324:406fd2029f23 279 *
mbed_official 324:406fd2029f23 280 * Indicates the status of RNGA. This register is read-only.
mbed_official 324:406fd2029f23 281 */
mbed_official 324:406fd2029f23 282 typedef union _hw_rng_sr
mbed_official 324:406fd2029f23 283 {
mbed_official 324:406fd2029f23 284 uint32_t U;
mbed_official 324:406fd2029f23 285 struct _hw_rng_sr_bitfields
mbed_official 324:406fd2029f23 286 {
mbed_official 324:406fd2029f23 287 uint32_t SECV : 1; /*!< [0] Security Violation */
mbed_official 324:406fd2029f23 288 uint32_t LRS : 1; /*!< [1] Last Read Status */
mbed_official 324:406fd2029f23 289 uint32_t ORU : 1; /*!< [2] Output Register Underflow */
mbed_official 324:406fd2029f23 290 uint32_t ERRI : 1; /*!< [3] Error Interrupt */
mbed_official 324:406fd2029f23 291 uint32_t SLP : 1; /*!< [4] Sleep */
mbed_official 324:406fd2029f23 292 uint32_t RESERVED0 : 3; /*!< [7:5] */
mbed_official 324:406fd2029f23 293 uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */
mbed_official 324:406fd2029f23 294 uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */
mbed_official 324:406fd2029f23 295 uint32_t RESERVED1 : 8; /*!< [31:24] */
mbed_official 324:406fd2029f23 296 } B;
mbed_official 324:406fd2029f23 297 } hw_rng_sr_t;
mbed_official 324:406fd2029f23 298
mbed_official 324:406fd2029f23 299 /*!
mbed_official 324:406fd2029f23 300 * @name Constants and macros for entire RNG_SR register
mbed_official 324:406fd2029f23 301 */
mbed_official 324:406fd2029f23 302 /*@{*/
mbed_official 324:406fd2029f23 303 #define HW_RNG_SR_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 304
mbed_official 324:406fd2029f23 305 #define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
mbed_official 324:406fd2029f23 306 #define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U)
mbed_official 324:406fd2029f23 307 /*@}*/
mbed_official 324:406fd2029f23 308
mbed_official 324:406fd2029f23 309 /*
mbed_official 324:406fd2029f23 310 * Constants & macros for individual RNG_SR bitfields
mbed_official 324:406fd2029f23 311 */
mbed_official 324:406fd2029f23 312
mbed_official 324:406fd2029f23 313 /*!
mbed_official 324:406fd2029f23 314 * @name Register RNG_SR, field SECV[0] (RO)
mbed_official 324:406fd2029f23 315 *
mbed_official 324:406fd2029f23 316 * Used only when high assurance is enabled (CR[HA]). Indicates that a security
mbed_official 324:406fd2029f23 317 * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
mbed_official 324:406fd2029f23 318 * RNGA.
mbed_official 324:406fd2029f23 319 *
mbed_official 324:406fd2029f23 320 * Values:
mbed_official 324:406fd2029f23 321 * - 0 - No security violation
mbed_official 324:406fd2029f23 322 * - 1 - Security violation
mbed_official 324:406fd2029f23 323 */
mbed_official 324:406fd2029f23 324 /*@{*/
mbed_official 324:406fd2029f23 325 #define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */
mbed_official 324:406fd2029f23 326 #define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
mbed_official 324:406fd2029f23 327 #define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */
mbed_official 324:406fd2029f23 328
mbed_official 324:406fd2029f23 329 /*! @brief Read current value of the RNG_SR_SECV field. */
mbed_official 324:406fd2029f23 330 #define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
mbed_official 324:406fd2029f23 331 /*@}*/
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 /*!
mbed_official 324:406fd2029f23 334 * @name Register RNG_SR, field LRS[1] (RO)
mbed_official 324:406fd2029f23 335 *
mbed_official 324:406fd2029f23 336 * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
mbed_official 324:406fd2029f23 337 * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
mbed_official 324:406fd2029f23 338 * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
mbed_official 324:406fd2029f23 339 * After you read this register, RNGA writes 0 to this field.
mbed_official 324:406fd2029f23 340 *
mbed_official 324:406fd2029f23 341 * Values:
mbed_official 324:406fd2029f23 342 * - 0 - No underflow
mbed_official 324:406fd2029f23 343 * - 1 - Underflow
mbed_official 324:406fd2029f23 344 */
mbed_official 324:406fd2029f23 345 /*@{*/
mbed_official 324:406fd2029f23 346 #define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */
mbed_official 324:406fd2029f23 347 #define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
mbed_official 324:406fd2029f23 348 #define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */
mbed_official 324:406fd2029f23 349
mbed_official 324:406fd2029f23 350 /*! @brief Read current value of the RNG_SR_LRS field. */
mbed_official 324:406fd2029f23 351 #define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
mbed_official 324:406fd2029f23 352 /*@}*/
mbed_official 324:406fd2029f23 353
mbed_official 324:406fd2029f23 354 /*!
mbed_official 324:406fd2029f23 355 * @name Register RNG_SR, field ORU[2] (RO)
mbed_official 324:406fd2029f23 356 *
mbed_official 324:406fd2029f23 357 * Indicates whether an OR underflow condition has occurred since you last read
mbed_official 324:406fd2029f23 358 * this register (SR) or RNGA was reset, regardless of whether the error
mbed_official 324:406fd2029f23 359 * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
mbed_official 324:406fd2029f23 360 * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
mbed_official 324:406fd2029f23 361 * field.
mbed_official 324:406fd2029f23 362 *
mbed_official 324:406fd2029f23 363 * Values:
mbed_official 324:406fd2029f23 364 * - 0 - No underflow
mbed_official 324:406fd2029f23 365 * - 1 - Underflow
mbed_official 324:406fd2029f23 366 */
mbed_official 324:406fd2029f23 367 /*@{*/
mbed_official 324:406fd2029f23 368 #define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */
mbed_official 324:406fd2029f23 369 #define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
mbed_official 324:406fd2029f23 370 #define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */
mbed_official 324:406fd2029f23 371
mbed_official 324:406fd2029f23 372 /*! @brief Read current value of the RNG_SR_ORU field. */
mbed_official 324:406fd2029f23 373 #define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
mbed_official 324:406fd2029f23 374 /*@}*/
mbed_official 324:406fd2029f23 375
mbed_official 324:406fd2029f23 376 /*!
mbed_official 324:406fd2029f23 377 * @name Register RNG_SR, field ERRI[3] (RO)
mbed_official 324:406fd2029f23 378 *
mbed_official 324:406fd2029f23 379 * Indicates whether an OR underflow condition has occurred since you last
mbed_official 324:406fd2029f23 380 * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
mbed_official 324:406fd2029f23 381 * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
mbed_official 324:406fd2029f23 382 * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
mbed_official 324:406fd2029f23 383 * indicator (via CR[CLRI]), RNGA writes 0 to this field.
mbed_official 324:406fd2029f23 384 *
mbed_official 324:406fd2029f23 385 * Values:
mbed_official 324:406fd2029f23 386 * - 0 - No underflow
mbed_official 324:406fd2029f23 387 * - 1 - Underflow
mbed_official 324:406fd2029f23 388 */
mbed_official 324:406fd2029f23 389 /*@{*/
mbed_official 324:406fd2029f23 390 #define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */
mbed_official 324:406fd2029f23 391 #define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
mbed_official 324:406fd2029f23 392 #define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */
mbed_official 324:406fd2029f23 393
mbed_official 324:406fd2029f23 394 /*! @brief Read current value of the RNG_SR_ERRI field. */
mbed_official 324:406fd2029f23 395 #define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
mbed_official 324:406fd2029f23 396 /*@}*/
mbed_official 324:406fd2029f23 397
mbed_official 324:406fd2029f23 398 /*!
mbed_official 324:406fd2029f23 399 * @name Register RNG_SR, field SLP[4] (RO)
mbed_official 324:406fd2029f23 400 *
mbed_official 324:406fd2029f23 401 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
mbed_official 324:406fd2029f23 402 * mode by asserting the DOZE signal.
mbed_official 324:406fd2029f23 403 *
mbed_official 324:406fd2029f23 404 * Values:
mbed_official 324:406fd2029f23 405 * - 0 - Normal mode
mbed_official 324:406fd2029f23 406 * - 1 - Sleep (low-power) mode
mbed_official 324:406fd2029f23 407 */
mbed_official 324:406fd2029f23 408 /*@{*/
mbed_official 324:406fd2029f23 409 #define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */
mbed_official 324:406fd2029f23 410 #define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
mbed_official 324:406fd2029f23 411 #define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */
mbed_official 324:406fd2029f23 412
mbed_official 324:406fd2029f23 413 /*! @brief Read current value of the RNG_SR_SLP field. */
mbed_official 324:406fd2029f23 414 #define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
mbed_official 324:406fd2029f23 415 /*@}*/
mbed_official 324:406fd2029f23 416
mbed_official 324:406fd2029f23 417 /*!
mbed_official 324:406fd2029f23 418 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
mbed_official 324:406fd2029f23 419 *
mbed_official 324:406fd2029f23 420 * Indicates the number of random-data words that are in OR[RANDOUT], which
mbed_official 324:406fd2029f23 421 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
mbed_official 324:406fd2029f23 422 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
mbed_official 324:406fd2029f23 423 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
mbed_official 324:406fd2029f23 424 *
mbed_official 324:406fd2029f23 425 * Values:
mbed_official 324:406fd2029f23 426 * - 0 - No words (empty)
mbed_official 324:406fd2029f23 427 * - 1 - One word (valid)
mbed_official 324:406fd2029f23 428 */
mbed_official 324:406fd2029f23 429 /*@{*/
mbed_official 324:406fd2029f23 430 #define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */
mbed_official 324:406fd2029f23 431 #define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
mbed_official 324:406fd2029f23 432 #define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
mbed_official 324:406fd2029f23 433
mbed_official 324:406fd2029f23 434 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
mbed_official 324:406fd2029f23 435 #define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
mbed_official 324:406fd2029f23 436 /*@}*/
mbed_official 324:406fd2029f23 437
mbed_official 324:406fd2029f23 438 /*!
mbed_official 324:406fd2029f23 439 * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
mbed_official 324:406fd2029f23 440 *
mbed_official 324:406fd2029f23 441 * Indicates the size of the Output (OR) register in terms of the number of
mbed_official 324:406fd2029f23 442 * 32-bit random-data words it can hold.
mbed_official 324:406fd2029f23 443 *
mbed_official 324:406fd2029f23 444 * Values:
mbed_official 324:406fd2029f23 445 * - 1 - One word (this value is fixed)
mbed_official 324:406fd2029f23 446 */
mbed_official 324:406fd2029f23 447 /*@{*/
mbed_official 324:406fd2029f23 448 #define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */
mbed_official 324:406fd2029f23 449 #define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
mbed_official 324:406fd2029f23 450 #define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
mbed_official 324:406fd2029f23 451
mbed_official 324:406fd2029f23 452 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
mbed_official 324:406fd2029f23 453 #define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
mbed_official 324:406fd2029f23 454 /*@}*/
mbed_official 324:406fd2029f23 455
mbed_official 324:406fd2029f23 456 /*******************************************************************************
mbed_official 324:406fd2029f23 457 * HW_RNG_ER - RNGA Entropy Register
mbed_official 324:406fd2029f23 458 ******************************************************************************/
mbed_official 324:406fd2029f23 459
mbed_official 324:406fd2029f23 460 /*!
mbed_official 324:406fd2029f23 461 * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
mbed_official 324:406fd2029f23 462 *
mbed_official 324:406fd2029f23 463 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 464 *
mbed_official 324:406fd2029f23 465 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
mbed_official 324:406fd2029f23 466 * to seed its pseudorandom algorithm. This is a write-only register; reads
mbed_official 324:406fd2029f23 467 * return all zeros.
mbed_official 324:406fd2029f23 468 */
mbed_official 324:406fd2029f23 469 typedef union _hw_rng_er
mbed_official 324:406fd2029f23 470 {
mbed_official 324:406fd2029f23 471 uint32_t U;
mbed_official 324:406fd2029f23 472 struct _hw_rng_er_bitfields
mbed_official 324:406fd2029f23 473 {
mbed_official 324:406fd2029f23 474 uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */
mbed_official 324:406fd2029f23 475 } B;
mbed_official 324:406fd2029f23 476 } hw_rng_er_t;
mbed_official 324:406fd2029f23 477
mbed_official 324:406fd2029f23 478 /*!
mbed_official 324:406fd2029f23 479 * @name Constants and macros for entire RNG_ER register
mbed_official 324:406fd2029f23 480 */
mbed_official 324:406fd2029f23 481 /*@{*/
mbed_official 324:406fd2029f23 482 #define HW_RNG_ER_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 483
mbed_official 324:406fd2029f23 484 #define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
mbed_official 324:406fd2029f23 485 #define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U)
mbed_official 324:406fd2029f23 486 #define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v))
mbed_official 324:406fd2029f23 487 /*@}*/
mbed_official 324:406fd2029f23 488
mbed_official 324:406fd2029f23 489 /*
mbed_official 324:406fd2029f23 490 * Constants & macros for individual RNG_ER bitfields
mbed_official 324:406fd2029f23 491 */
mbed_official 324:406fd2029f23 492
mbed_official 324:406fd2029f23 493 /*!
mbed_official 324:406fd2029f23 494 * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
mbed_official 324:406fd2029f23 495 *
mbed_official 324:406fd2029f23 496 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
mbed_official 324:406fd2029f23 497 * to seed its pseudorandom algorithm.Specifying a value for this field is
mbed_official 324:406fd2029f23 498 * optional but recommended. You can write to this field at any time during operation.
mbed_official 324:406fd2029f23 499 */
mbed_official 324:406fd2029f23 500 /*@{*/
mbed_official 324:406fd2029f23 501 #define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */
mbed_official 324:406fd2029f23 502 #define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
mbed_official 324:406fd2029f23 503 #define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
mbed_official 324:406fd2029f23 504
mbed_official 324:406fd2029f23 505 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
mbed_official 324:406fd2029f23 506 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
mbed_official 324:406fd2029f23 507
mbed_official 324:406fd2029f23 508 /*! @brief Set the EXT_ENT field to a new value. */
mbed_official 324:406fd2029f23 509 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
mbed_official 324:406fd2029f23 510 /*@}*/
mbed_official 324:406fd2029f23 511
mbed_official 324:406fd2029f23 512 /*******************************************************************************
mbed_official 324:406fd2029f23 513 * HW_RNG_OR - RNGA Output Register
mbed_official 324:406fd2029f23 514 ******************************************************************************/
mbed_official 324:406fd2029f23 515
mbed_official 324:406fd2029f23 516 /*!
mbed_official 324:406fd2029f23 517 * @brief HW_RNG_OR - RNGA Output Register (RO)
mbed_official 324:406fd2029f23 518 *
mbed_official 324:406fd2029f23 519 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 520 *
mbed_official 324:406fd2029f23 521 * Stores a random-data word generated by RNGA.
mbed_official 324:406fd2029f23 522 */
mbed_official 324:406fd2029f23 523 typedef union _hw_rng_or
mbed_official 324:406fd2029f23 524 {
mbed_official 324:406fd2029f23 525 uint32_t U;
mbed_official 324:406fd2029f23 526 struct _hw_rng_or_bitfields
mbed_official 324:406fd2029f23 527 {
mbed_official 324:406fd2029f23 528 uint32_t RANDOUT : 32; /*!< [31:0] Random Output */
mbed_official 324:406fd2029f23 529 } B;
mbed_official 324:406fd2029f23 530 } hw_rng_or_t;
mbed_official 324:406fd2029f23 531
mbed_official 324:406fd2029f23 532 /*!
mbed_official 324:406fd2029f23 533 * @name Constants and macros for entire RNG_OR register
mbed_official 324:406fd2029f23 534 */
mbed_official 324:406fd2029f23 535 /*@{*/
mbed_official 324:406fd2029f23 536 #define HW_RNG_OR_ADDR(x) ((x) + 0xCU)
mbed_official 324:406fd2029f23 537
mbed_official 324:406fd2029f23 538 #define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
mbed_official 324:406fd2029f23 539 #define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U)
mbed_official 324:406fd2029f23 540 /*@}*/
mbed_official 324:406fd2029f23 541
mbed_official 324:406fd2029f23 542 /*
mbed_official 324:406fd2029f23 543 * Constants & macros for individual RNG_OR bitfields
mbed_official 324:406fd2029f23 544 */
mbed_official 324:406fd2029f23 545
mbed_official 324:406fd2029f23 546 /*!
mbed_official 324:406fd2029f23 547 * @name Register RNG_OR, field RANDOUT[31:0] (RO)
mbed_official 324:406fd2029f23 548 *
mbed_official 324:406fd2029f23 549 * Stores a random-data word generated by RNGA. This is a read-only field.Before
mbed_official 324:406fd2029f23 550 * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
mbed_official 324:406fd2029f23 551 *
mbed_official 324:406fd2029f23 552 * Values:
mbed_official 324:406fd2029f23 553 * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
mbed_official 324:406fd2029f23 554 * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
mbed_official 324:406fd2029f23 555 * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
mbed_official 324:406fd2029f23 556 * request to the interrupt controller).
mbed_official 324:406fd2029f23 557 */
mbed_official 324:406fd2029f23 558 /*@{*/
mbed_official 324:406fd2029f23 559 #define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */
mbed_official 324:406fd2029f23 560 #define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
mbed_official 324:406fd2029f23 561 #define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */
mbed_official 324:406fd2029f23 562
mbed_official 324:406fd2029f23 563 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
mbed_official 324:406fd2029f23 564 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
mbed_official 324:406fd2029f23 565 /*@}*/
mbed_official 324:406fd2029f23 566
mbed_official 324:406fd2029f23 567 /*******************************************************************************
mbed_official 324:406fd2029f23 568 * hw_rng_t - module struct
mbed_official 324:406fd2029f23 569 ******************************************************************************/
mbed_official 324:406fd2029f23 570 /*!
mbed_official 324:406fd2029f23 571 * @brief All RNG module registers.
mbed_official 324:406fd2029f23 572 */
mbed_official 324:406fd2029f23 573 #pragma pack(1)
mbed_official 324:406fd2029f23 574 typedef struct _hw_rng
mbed_official 324:406fd2029f23 575 {
mbed_official 324:406fd2029f23 576 __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */
mbed_official 324:406fd2029f23 577 __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */
mbed_official 324:406fd2029f23 578 __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */
mbed_official 324:406fd2029f23 579 __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */
mbed_official 324:406fd2029f23 580 } hw_rng_t;
mbed_official 324:406fd2029f23 581 #pragma pack()
mbed_official 324:406fd2029f23 582
mbed_official 324:406fd2029f23 583 /*! @brief Macro to access all RNG registers. */
mbed_official 324:406fd2029f23 584 /*! @param x RNG module instance base address. */
mbed_official 324:406fd2029f23 585 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 586 * use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
mbed_official 324:406fd2029f23 587 #define HW_RNG(x) (*(hw_rng_t *)(x))
mbed_official 324:406fd2029f23 588
mbed_official 324:406fd2029f23 589 #endif /* __HW_RNG_REGISTERS_H__ */
mbed_official 324:406fd2029f23 590 /* EOF */