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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_PMC_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_PMC_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 PMC
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Power Management Controller
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
mbed_official 324:406fd2029f23 93 * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
mbed_official 324:406fd2029f23 94 * - HW_PMC_REGSC - Regulator Status And Control register
mbed_official 324:406fd2029f23 95 *
mbed_official 324:406fd2029f23 96 * - hw_pmc_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 97 */
mbed_official 324:406fd2029f23 98
mbed_official 324:406fd2029f23 99 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
mbed_official 324:406fd2029f23 100
mbed_official 324:406fd2029f23 101 /*******************************************************************************
mbed_official 324:406fd2029f23 102 * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
mbed_official 324:406fd2029f23 103 ******************************************************************************/
mbed_official 324:406fd2029f23 104
mbed_official 324:406fd2029f23 105 /*!
mbed_official 324:406fd2029f23 106 * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
mbed_official 324:406fd2029f23 107 *
mbed_official 324:406fd2029f23 108 * Reset value: 0x10U
mbed_official 324:406fd2029f23 109 *
mbed_official 324:406fd2029f23 110 * This register contains status and control bits to support the low voltage
mbed_official 324:406fd2029f23 111 * detect function. This register should be written during the reset initialization
mbed_official 324:406fd2029f23 112 * program to set the desired controls even if the desired settings are the same
mbed_official 324:406fd2029f23 113 * as the reset settings. While the device is in the very low power or low
mbed_official 324:406fd2029f23 114 * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
mbed_official 324:406fd2029f23 115 * systems that must have LVD always on, configure the Power Mode Protection
mbed_official 324:406fd2029f23 116 * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
mbed_official 324:406fd2029f23 117 * low leakage modes from being enabled. See the device's data sheet for the
mbed_official 324:406fd2029f23 118 * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
mbed_official 324:406fd2029f23 119 * register's other bits are reset on Chip Reset Not VLLS. For more information
mbed_official 324:406fd2029f23 120 * about these reset types, refer to the Reset section details.
mbed_official 324:406fd2029f23 121 */
mbed_official 324:406fd2029f23 122 typedef union _hw_pmc_lvdsc1
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 uint8_t U;
mbed_official 324:406fd2029f23 125 struct _hw_pmc_lvdsc1_bitfields
mbed_official 324:406fd2029f23 126 {
mbed_official 324:406fd2029f23 127 uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */
mbed_official 324:406fd2029f23 128 uint8_t RESERVED0 : 2; /*!< [3:2] */
mbed_official 324:406fd2029f23 129 uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */
mbed_official 324:406fd2029f23 130 uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */
mbed_official 324:406fd2029f23 131 uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */
mbed_official 324:406fd2029f23 132 uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */
mbed_official 324:406fd2029f23 133 } B;
mbed_official 324:406fd2029f23 134 } hw_pmc_lvdsc1_t;
mbed_official 324:406fd2029f23 135
mbed_official 324:406fd2029f23 136 /*!
mbed_official 324:406fd2029f23 137 * @name Constants and macros for entire PMC_LVDSC1 register
mbed_official 324:406fd2029f23 138 */
mbed_official 324:406fd2029f23 139 /*@{*/
mbed_official 324:406fd2029f23 140 #define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 141
mbed_official 324:406fd2029f23 142 #define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
mbed_official 324:406fd2029f23 143 #define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U)
mbed_official 324:406fd2029f23 144 #define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v))
mbed_official 324:406fd2029f23 145 #define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v)))
mbed_official 324:406fd2029f23 146 #define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 147 #define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 148 /*@}*/
mbed_official 324:406fd2029f23 149
mbed_official 324:406fd2029f23 150 /*
mbed_official 324:406fd2029f23 151 * Constants & macros for individual PMC_LVDSC1 bitfields
mbed_official 324:406fd2029f23 152 */
mbed_official 324:406fd2029f23 153
mbed_official 324:406fd2029f23 154 /*!
mbed_official 324:406fd2029f23 155 * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
mbed_official 324:406fd2029f23 156 *
mbed_official 324:406fd2029f23 157 * Selects the LVD trip point voltage (V LVD ).
mbed_official 324:406fd2029f23 158 *
mbed_official 324:406fd2029f23 159 * Values:
mbed_official 324:406fd2029f23 160 * - 00 - Low trip point selected (V LVD = V LVDL )
mbed_official 324:406fd2029f23 161 * - 01 - High trip point selected (V LVD = V LVDH )
mbed_official 324:406fd2029f23 162 * - 10 - Reserved
mbed_official 324:406fd2029f23 163 * - 11 - Reserved
mbed_official 324:406fd2029f23 164 */
mbed_official 324:406fd2029f23 165 /*@{*/
mbed_official 324:406fd2029f23 166 #define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */
mbed_official 324:406fd2029f23 167 #define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */
mbed_official 324:406fd2029f23 168 #define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
mbed_official 324:406fd2029f23 169
mbed_official 324:406fd2029f23 170 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
mbed_official 324:406fd2029f23 171 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
mbed_official 324:406fd2029f23 172
mbed_official 324:406fd2029f23 173 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
mbed_official 324:406fd2029f23 174 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
mbed_official 324:406fd2029f23 175
mbed_official 324:406fd2029f23 176 /*! @brief Set the LVDV field to a new value. */
mbed_official 324:406fd2029f23 177 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
mbed_official 324:406fd2029f23 178 /*@}*/
mbed_official 324:406fd2029f23 179
mbed_official 324:406fd2029f23 180 /*!
mbed_official 324:406fd2029f23 181 * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
mbed_official 324:406fd2029f23 182 *
mbed_official 324:406fd2029f23 183 * This write-once bit enables LVDF events to generate a hardware reset.
mbed_official 324:406fd2029f23 184 * Additional writes are ignored.
mbed_official 324:406fd2029f23 185 *
mbed_official 324:406fd2029f23 186 * Values:
mbed_official 324:406fd2029f23 187 * - 0 - LVDF does not generate hardware resets
mbed_official 324:406fd2029f23 188 * - 1 - Force an MCU reset when LVDF = 1
mbed_official 324:406fd2029f23 189 */
mbed_official 324:406fd2029f23 190 /*@{*/
mbed_official 324:406fd2029f23 191 #define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */
mbed_official 324:406fd2029f23 192 #define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */
mbed_official 324:406fd2029f23 193 #define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
mbed_official 324:406fd2029f23 194
mbed_official 324:406fd2029f23 195 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
mbed_official 324:406fd2029f23 196 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
mbed_official 324:406fd2029f23 199 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 /*! @brief Set the LVDRE field to a new value. */
mbed_official 324:406fd2029f23 202 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
mbed_official 324:406fd2029f23 203 /*@}*/
mbed_official 324:406fd2029f23 204
mbed_official 324:406fd2029f23 205 /*!
mbed_official 324:406fd2029f23 206 * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
mbed_official 324:406fd2029f23 207 *
mbed_official 324:406fd2029f23 208 * Enables hardware interrupt requests for LVDF.
mbed_official 324:406fd2029f23 209 *
mbed_official 324:406fd2029f23 210 * Values:
mbed_official 324:406fd2029f23 211 * - 0 - Hardware interrupt disabled (use polling)
mbed_official 324:406fd2029f23 212 * - 1 - Request a hardware interrupt when LVDF = 1
mbed_official 324:406fd2029f23 213 */
mbed_official 324:406fd2029f23 214 /*@{*/
mbed_official 324:406fd2029f23 215 #define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */
mbed_official 324:406fd2029f23 216 #define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */
mbed_official 324:406fd2029f23 217 #define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
mbed_official 324:406fd2029f23 220 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
mbed_official 324:406fd2029f23 221
mbed_official 324:406fd2029f23 222 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
mbed_official 324:406fd2029f23 223 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
mbed_official 324:406fd2029f23 224
mbed_official 324:406fd2029f23 225 /*! @brief Set the LVDIE field to a new value. */
mbed_official 324:406fd2029f23 226 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
mbed_official 324:406fd2029f23 227 /*@}*/
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*!
mbed_official 324:406fd2029f23 230 * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
mbed_official 324:406fd2029f23 231 *
mbed_official 324:406fd2029f23 232 * This write-only field is used to acknowledge low voltage detection errors.
mbed_official 324:406fd2029f23 233 * Write 1 to clear LVDF. Reads always return 0.
mbed_official 324:406fd2029f23 234 */
mbed_official 324:406fd2029f23 235 /*@{*/
mbed_official 324:406fd2029f23 236 #define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */
mbed_official 324:406fd2029f23 237 #define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */
mbed_official 324:406fd2029f23 238 #define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
mbed_official 324:406fd2029f23 239
mbed_official 324:406fd2029f23 240 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
mbed_official 324:406fd2029f23 241 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
mbed_official 324:406fd2029f23 242
mbed_official 324:406fd2029f23 243 /*! @brief Set the LVDACK field to a new value. */
mbed_official 324:406fd2029f23 244 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
mbed_official 324:406fd2029f23 245 /*@}*/
mbed_official 324:406fd2029f23 246
mbed_official 324:406fd2029f23 247 /*!
mbed_official 324:406fd2029f23 248 * @name Register PMC_LVDSC1, field LVDF[7] (RO)
mbed_official 324:406fd2029f23 249 *
mbed_official 324:406fd2029f23 250 * This read-only status field indicates a low-voltage detect event.
mbed_official 324:406fd2029f23 251 *
mbed_official 324:406fd2029f23 252 * Values:
mbed_official 324:406fd2029f23 253 * - 0 - Low-voltage event not detected
mbed_official 324:406fd2029f23 254 * - 1 - Low-voltage event detected
mbed_official 324:406fd2029f23 255 */
mbed_official 324:406fd2029f23 256 /*@{*/
mbed_official 324:406fd2029f23 257 #define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */
mbed_official 324:406fd2029f23 258 #define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */
mbed_official 324:406fd2029f23 259 #define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
mbed_official 324:406fd2029f23 262 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
mbed_official 324:406fd2029f23 263 /*@}*/
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*******************************************************************************
mbed_official 324:406fd2029f23 266 * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
mbed_official 324:406fd2029f23 267 ******************************************************************************/
mbed_official 324:406fd2029f23 268
mbed_official 324:406fd2029f23 269 /*!
mbed_official 324:406fd2029f23 270 * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
mbed_official 324:406fd2029f23 271 *
mbed_official 324:406fd2029f23 272 * Reset value: 0x00U
mbed_official 324:406fd2029f23 273 *
mbed_official 324:406fd2029f23 274 * This register contains status and control bits to support the low voltage
mbed_official 324:406fd2029f23 275 * warning function. While the device is in the very low power or low leakage modes,
mbed_official 324:406fd2029f23 276 * the LVD system is disabled regardless of LVDSC2 settings. See the device's
mbed_official 324:406fd2029f23 277 * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
mbed_official 324:406fd2029f23 278 * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
mbed_official 324:406fd2029f23 279 * register are reset on Chip Reset Not VLLS. For more information about these
mbed_official 324:406fd2029f23 280 * reset types, refer to the Reset section details.
mbed_official 324:406fd2029f23 281 */
mbed_official 324:406fd2029f23 282 typedef union _hw_pmc_lvdsc2
mbed_official 324:406fd2029f23 283 {
mbed_official 324:406fd2029f23 284 uint8_t U;
mbed_official 324:406fd2029f23 285 struct _hw_pmc_lvdsc2_bitfields
mbed_official 324:406fd2029f23 286 {
mbed_official 324:406fd2029f23 287 uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */
mbed_official 324:406fd2029f23 288 uint8_t RESERVED0 : 3; /*!< [4:2] */
mbed_official 324:406fd2029f23 289 uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */
mbed_official 324:406fd2029f23 290 uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */
mbed_official 324:406fd2029f23 291 uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */
mbed_official 324:406fd2029f23 292 } B;
mbed_official 324:406fd2029f23 293 } hw_pmc_lvdsc2_t;
mbed_official 324:406fd2029f23 294
mbed_official 324:406fd2029f23 295 /*!
mbed_official 324:406fd2029f23 296 * @name Constants and macros for entire PMC_LVDSC2 register
mbed_official 324:406fd2029f23 297 */
mbed_official 324:406fd2029f23 298 /*@{*/
mbed_official 324:406fd2029f23 299 #define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 300
mbed_official 324:406fd2029f23 301 #define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
mbed_official 324:406fd2029f23 302 #define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U)
mbed_official 324:406fd2029f23 303 #define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v))
mbed_official 324:406fd2029f23 304 #define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v)))
mbed_official 324:406fd2029f23 305 #define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 306 #define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 307 /*@}*/
mbed_official 324:406fd2029f23 308
mbed_official 324:406fd2029f23 309 /*
mbed_official 324:406fd2029f23 310 * Constants & macros for individual PMC_LVDSC2 bitfields
mbed_official 324:406fd2029f23 311 */
mbed_official 324:406fd2029f23 312
mbed_official 324:406fd2029f23 313 /*!
mbed_official 324:406fd2029f23 314 * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
mbed_official 324:406fd2029f23 315 *
mbed_official 324:406fd2029f23 316 * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
mbed_official 324:406fd2029f23 317 * depends on LVDSC1[LVDV].
mbed_official 324:406fd2029f23 318 *
mbed_official 324:406fd2029f23 319 * Values:
mbed_official 324:406fd2029f23 320 * - 00 - Low trip point selected (VLVW = VLVW1)
mbed_official 324:406fd2029f23 321 * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
mbed_official 324:406fd2029f23 322 * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
mbed_official 324:406fd2029f23 323 * - 11 - High trip point selected (VLVW = VLVW4)
mbed_official 324:406fd2029f23 324 */
mbed_official 324:406fd2029f23 325 /*@{*/
mbed_official 324:406fd2029f23 326 #define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */
mbed_official 324:406fd2029f23 327 #define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */
mbed_official 324:406fd2029f23 328 #define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
mbed_official 324:406fd2029f23 329
mbed_official 324:406fd2029f23 330 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
mbed_official 324:406fd2029f23 331 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
mbed_official 324:406fd2029f23 334 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
mbed_official 324:406fd2029f23 335
mbed_official 324:406fd2029f23 336 /*! @brief Set the LVWV field to a new value. */
mbed_official 324:406fd2029f23 337 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
mbed_official 324:406fd2029f23 338 /*@}*/
mbed_official 324:406fd2029f23 339
mbed_official 324:406fd2029f23 340 /*!
mbed_official 324:406fd2029f23 341 * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
mbed_official 324:406fd2029f23 342 *
mbed_official 324:406fd2029f23 343 * Enables hardware interrupt requests for LVWF.
mbed_official 324:406fd2029f23 344 *
mbed_official 324:406fd2029f23 345 * Values:
mbed_official 324:406fd2029f23 346 * - 0 - Hardware interrupt disabled (use polling)
mbed_official 324:406fd2029f23 347 * - 1 - Request a hardware interrupt when LVWF = 1
mbed_official 324:406fd2029f23 348 */
mbed_official 324:406fd2029f23 349 /*@{*/
mbed_official 324:406fd2029f23 350 #define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */
mbed_official 324:406fd2029f23 351 #define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */
mbed_official 324:406fd2029f23 352 #define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
mbed_official 324:406fd2029f23 353
mbed_official 324:406fd2029f23 354 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
mbed_official 324:406fd2029f23 355 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
mbed_official 324:406fd2029f23 356
mbed_official 324:406fd2029f23 357 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
mbed_official 324:406fd2029f23 358 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
mbed_official 324:406fd2029f23 359
mbed_official 324:406fd2029f23 360 /*! @brief Set the LVWIE field to a new value. */
mbed_official 324:406fd2029f23 361 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
mbed_official 324:406fd2029f23 362 /*@}*/
mbed_official 324:406fd2029f23 363
mbed_official 324:406fd2029f23 364 /*!
mbed_official 324:406fd2029f23 365 * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
mbed_official 324:406fd2029f23 366 *
mbed_official 324:406fd2029f23 367 * This write-only field is used to acknowledge low voltage warning errors.
mbed_official 324:406fd2029f23 368 * Write 1 to clear LVWF. Reads always return 0.
mbed_official 324:406fd2029f23 369 */
mbed_official 324:406fd2029f23 370 /*@{*/
mbed_official 324:406fd2029f23 371 #define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */
mbed_official 324:406fd2029f23 372 #define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */
mbed_official 324:406fd2029f23 373 #define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
mbed_official 324:406fd2029f23 374
mbed_official 324:406fd2029f23 375 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
mbed_official 324:406fd2029f23 376 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
mbed_official 324:406fd2029f23 377
mbed_official 324:406fd2029f23 378 /*! @brief Set the LVWACK field to a new value. */
mbed_official 324:406fd2029f23 379 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
mbed_official 324:406fd2029f23 380 /*@}*/
mbed_official 324:406fd2029f23 381
mbed_official 324:406fd2029f23 382 /*!
mbed_official 324:406fd2029f23 383 * @name Register PMC_LVDSC2, field LVWF[7] (RO)
mbed_official 324:406fd2029f23 384 *
mbed_official 324:406fd2029f23 385 * This read-only status field indicates a low-voltage warning event. LVWF is
mbed_official 324:406fd2029f23 386 * set when VSupply transitions below the trip point, or after reset and VSupply is
mbed_official 324:406fd2029f23 387 * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
mbed_official 324:406fd2029f23 388 * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
mbed_official 324:406fd2029f23 389 * LVWACK first.
mbed_official 324:406fd2029f23 390 *
mbed_official 324:406fd2029f23 391 * Values:
mbed_official 324:406fd2029f23 392 * - 0 - Low-voltage warning event not detected
mbed_official 324:406fd2029f23 393 * - 1 - Low-voltage warning event detected
mbed_official 324:406fd2029f23 394 */
mbed_official 324:406fd2029f23 395 /*@{*/
mbed_official 324:406fd2029f23 396 #define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */
mbed_official 324:406fd2029f23 397 #define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */
mbed_official 324:406fd2029f23 398 #define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
mbed_official 324:406fd2029f23 399
mbed_official 324:406fd2029f23 400 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
mbed_official 324:406fd2029f23 401 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
mbed_official 324:406fd2029f23 402 /*@}*/
mbed_official 324:406fd2029f23 403
mbed_official 324:406fd2029f23 404 /*******************************************************************************
mbed_official 324:406fd2029f23 405 * HW_PMC_REGSC - Regulator Status And Control register
mbed_official 324:406fd2029f23 406 ******************************************************************************/
mbed_official 324:406fd2029f23 407
mbed_official 324:406fd2029f23 408 /*!
mbed_official 324:406fd2029f23 409 * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
mbed_official 324:406fd2029f23 410 *
mbed_official 324:406fd2029f23 411 * Reset value: 0x04U
mbed_official 324:406fd2029f23 412 *
mbed_official 324:406fd2029f23 413 * The PMC contains an internal voltage regulator. The voltage regulator design
mbed_official 324:406fd2029f23 414 * uses a bandgap reference that is also available through a buffer as input to
mbed_official 324:406fd2029f23 415 * certain internal peripherals, such as the CMP and ADC. The internal regulator
mbed_official 324:406fd2029f23 416 * provides a status bit (REGONS) indicating the regulator is in run regulation.
mbed_official 324:406fd2029f23 417 * This register is reset on Chip Reset Not VLLS and by reset types that trigger
mbed_official 324:406fd2029f23 418 * Chip Reset not VLLS. See the Reset section details for more information.
mbed_official 324:406fd2029f23 419 */
mbed_official 324:406fd2029f23 420 typedef union _hw_pmc_regsc
mbed_official 324:406fd2029f23 421 {
mbed_official 324:406fd2029f23 422 uint8_t U;
mbed_official 324:406fd2029f23 423 struct _hw_pmc_regsc_bitfields
mbed_official 324:406fd2029f23 424 {
mbed_official 324:406fd2029f23 425 uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */
mbed_official 324:406fd2029f23 426 uint8_t RESERVED0 : 1; /*!< [1] */
mbed_official 324:406fd2029f23 427 uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */
mbed_official 324:406fd2029f23 428 uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */
mbed_official 324:406fd2029f23 429 uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */
mbed_official 324:406fd2029f23 430 uint8_t RESERVED1 : 3; /*!< [7:5] */
mbed_official 324:406fd2029f23 431 } B;
mbed_official 324:406fd2029f23 432 } hw_pmc_regsc_t;
mbed_official 324:406fd2029f23 433
mbed_official 324:406fd2029f23 434 /*!
mbed_official 324:406fd2029f23 435 * @name Constants and macros for entire PMC_REGSC register
mbed_official 324:406fd2029f23 436 */
mbed_official 324:406fd2029f23 437 /*@{*/
mbed_official 324:406fd2029f23 438 #define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 439
mbed_official 324:406fd2029f23 440 #define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
mbed_official 324:406fd2029f23 441 #define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U)
mbed_official 324:406fd2029f23 442 #define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v))
mbed_official 324:406fd2029f23 443 #define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v)))
mbed_official 324:406fd2029f23 444 #define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 445 #define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 446 /*@}*/
mbed_official 324:406fd2029f23 447
mbed_official 324:406fd2029f23 448 /*
mbed_official 324:406fd2029f23 449 * Constants & macros for individual PMC_REGSC bitfields
mbed_official 324:406fd2029f23 450 */
mbed_official 324:406fd2029f23 451
mbed_official 324:406fd2029f23 452 /*!
mbed_official 324:406fd2029f23 453 * @name Register PMC_REGSC, field BGBE[0] (RW)
mbed_official 324:406fd2029f23 454 *
mbed_official 324:406fd2029f23 455 * Enables the bandgap buffer.
mbed_official 324:406fd2029f23 456 *
mbed_official 324:406fd2029f23 457 * Values:
mbed_official 324:406fd2029f23 458 * - 0 - Bandgap buffer not enabled
mbed_official 324:406fd2029f23 459 * - 1 - Bandgap buffer enabled
mbed_official 324:406fd2029f23 460 */
mbed_official 324:406fd2029f23 461 /*@{*/
mbed_official 324:406fd2029f23 462 #define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */
mbed_official 324:406fd2029f23 463 #define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */
mbed_official 324:406fd2029f23 464 #define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */
mbed_official 324:406fd2029f23 465
mbed_official 324:406fd2029f23 466 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
mbed_official 324:406fd2029f23 467 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
mbed_official 324:406fd2029f23 468
mbed_official 324:406fd2029f23 469 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
mbed_official 324:406fd2029f23 470 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
mbed_official 324:406fd2029f23 471
mbed_official 324:406fd2029f23 472 /*! @brief Set the BGBE field to a new value. */
mbed_official 324:406fd2029f23 473 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
mbed_official 324:406fd2029f23 474 /*@}*/
mbed_official 324:406fd2029f23 475
mbed_official 324:406fd2029f23 476 /*!
mbed_official 324:406fd2029f23 477 * @name Register PMC_REGSC, field REGONS[2] (RO)
mbed_official 324:406fd2029f23 478 *
mbed_official 324:406fd2029f23 479 * This read-only field provides the current status of the internal voltage
mbed_official 324:406fd2029f23 480 * regulator.
mbed_official 324:406fd2029f23 481 *
mbed_official 324:406fd2029f23 482 * Values:
mbed_official 324:406fd2029f23 483 * - 0 - Regulator is in stop regulation or in transition to/from it
mbed_official 324:406fd2029f23 484 * - 1 - Regulator is in run regulation
mbed_official 324:406fd2029f23 485 */
mbed_official 324:406fd2029f23 486 /*@{*/
mbed_official 324:406fd2029f23 487 #define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */
mbed_official 324:406fd2029f23 488 #define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */
mbed_official 324:406fd2029f23 489 #define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */
mbed_official 324:406fd2029f23 490
mbed_official 324:406fd2029f23 491 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
mbed_official 324:406fd2029f23 492 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
mbed_official 324:406fd2029f23 493 /*@}*/
mbed_official 324:406fd2029f23 494
mbed_official 324:406fd2029f23 495 /*!
mbed_official 324:406fd2029f23 496 * @name Register PMC_REGSC, field ACKISO[3] (W1C)
mbed_official 324:406fd2029f23 497 *
mbed_official 324:406fd2029f23 498 * Reading this field indicates whether certain peripherals and the I/O pads are
mbed_official 324:406fd2029f23 499 * in a latched state as a result of having been in a VLLS mode. Writing 1 to
mbed_official 324:406fd2029f23 500 * this field when it is set releases the I/O pads and certain peripherals to their
mbed_official 324:406fd2029f23 501 * normal run mode state. After recovering from a VLLS mode, user should restore
mbed_official 324:406fd2029f23 502 * chip configuration before clearing ACKISO. In particular, pin configuration
mbed_official 324:406fd2029f23 503 * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
mbed_official 324:406fd2029f23 504 * being falsely set when ACKISO is cleared.
mbed_official 324:406fd2029f23 505 *
mbed_official 324:406fd2029f23 506 * Values:
mbed_official 324:406fd2029f23 507 * - 0 - Peripherals and I/O pads are in normal run state.
mbed_official 324:406fd2029f23 508 * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
mbed_official 324:406fd2029f23 509 */
mbed_official 324:406fd2029f23 510 /*@{*/
mbed_official 324:406fd2029f23 511 #define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */
mbed_official 324:406fd2029f23 512 #define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */
mbed_official 324:406fd2029f23 513 #define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
mbed_official 324:406fd2029f23 514
mbed_official 324:406fd2029f23 515 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
mbed_official 324:406fd2029f23 516 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
mbed_official 324:406fd2029f23 517
mbed_official 324:406fd2029f23 518 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
mbed_official 324:406fd2029f23 519 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
mbed_official 324:406fd2029f23 520
mbed_official 324:406fd2029f23 521 /*! @brief Set the ACKISO field to a new value. */
mbed_official 324:406fd2029f23 522 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
mbed_official 324:406fd2029f23 523 /*@}*/
mbed_official 324:406fd2029f23 524
mbed_official 324:406fd2029f23 525 /*!
mbed_official 324:406fd2029f23 526 * @name Register PMC_REGSC, field BGEN[4] (RW)
mbed_official 324:406fd2029f23 527 *
mbed_official 324:406fd2029f23 528 * BGEN controls whether the bandgap is enabled in lower power modes of
mbed_official 324:406fd2029f23 529 * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
mbed_official 324:406fd2029f23 530 * reference in low power modes of operation, set BGEN to continue to enable the
mbed_official 324:406fd2029f23 531 * bandgap operation. When the bandgap voltage reference is not needed in low
mbed_official 324:406fd2029f23 532 * power modes, clear BGEN to avoid excess power consumption.
mbed_official 324:406fd2029f23 533 *
mbed_official 324:406fd2029f23 534 * Values:
mbed_official 324:406fd2029f23 535 * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
mbed_official 324:406fd2029f23 536 * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
mbed_official 324:406fd2029f23 537 */
mbed_official 324:406fd2029f23 538 /*@{*/
mbed_official 324:406fd2029f23 539 #define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */
mbed_official 324:406fd2029f23 540 #define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */
mbed_official 324:406fd2029f23 541 #define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */
mbed_official 324:406fd2029f23 542
mbed_official 324:406fd2029f23 543 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
mbed_official 324:406fd2029f23 544 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
mbed_official 324:406fd2029f23 545
mbed_official 324:406fd2029f23 546 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
mbed_official 324:406fd2029f23 547 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
mbed_official 324:406fd2029f23 548
mbed_official 324:406fd2029f23 549 /*! @brief Set the BGEN field to a new value. */
mbed_official 324:406fd2029f23 550 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
mbed_official 324:406fd2029f23 551 /*@}*/
mbed_official 324:406fd2029f23 552
mbed_official 324:406fd2029f23 553 /*******************************************************************************
mbed_official 324:406fd2029f23 554 * hw_pmc_t - module struct
mbed_official 324:406fd2029f23 555 ******************************************************************************/
mbed_official 324:406fd2029f23 556 /*!
mbed_official 324:406fd2029f23 557 * @brief All PMC module registers.
mbed_official 324:406fd2029f23 558 */
mbed_official 324:406fd2029f23 559 #pragma pack(1)
mbed_official 324:406fd2029f23 560 typedef struct _hw_pmc
mbed_official 324:406fd2029f23 561 {
mbed_official 324:406fd2029f23 562 __IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */
mbed_official 324:406fd2029f23 563 __IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */
mbed_official 324:406fd2029f23 564 __IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */
mbed_official 324:406fd2029f23 565 } hw_pmc_t;
mbed_official 324:406fd2029f23 566 #pragma pack()
mbed_official 324:406fd2029f23 567
mbed_official 324:406fd2029f23 568 /*! @brief Macro to access all PMC registers. */
mbed_official 324:406fd2029f23 569 /*! @param x PMC module instance base address. */
mbed_official 324:406fd2029f23 570 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 571 * use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
mbed_official 324:406fd2029f23 572 #define HW_PMC(x) (*(hw_pmc_t *)(x))
mbed_official 324:406fd2029f23 573
mbed_official 324:406fd2029f23 574 #endif /* __HW_PMC_REGISTERS_H__ */
mbed_official 324:406fd2029f23 575 /* EOF */