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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_MPU_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_MPU_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 MPU
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Memory protection unit
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_MPU_CESR - Control/Error Status Register
mbed_official	324:406fd2029f23	93	* - HW_MPU_EARn - Error Address Register, slave port n
mbed_official	324:406fd2029f23	94	* - HW_MPU_EDRn - Error Detail Register, slave port n
mbed_official	324:406fd2029f23	95	* - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
mbed_official	324:406fd2029f23	96	* - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
mbed_official	324:406fd2029f23	97	* - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
mbed_official	324:406fd2029f23	98	* - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
mbed_official	324:406fd2029f23	99	* - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
mbed_official	324:406fd2029f23	100	*
mbed_official	324:406fd2029f23	101	* - hw_mpu_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	102	*/
mbed_official	324:406fd2029f23	103
mbed_official	324:406fd2029f23	104	#define HW_MPU_INSTANCE_COUNT (1U) /!< Number of instances of the MPU module. /
mbed_official	324:406fd2029f23	105
mbed_official	324:406fd2029f23	106	/*******************************************************************************
mbed_official	324:406fd2029f23	107	* HW_MPU_CESR - Control/Error Status Register
mbed_official	324:406fd2029f23	108	******************************************************************************/
mbed_official	324:406fd2029f23	109
mbed_official	324:406fd2029f23	110	/*!
mbed_official	324:406fd2029f23	111	* @brief HW_MPU_CESR - Control/Error Status Register (RW)
mbed_official	324:406fd2029f23	112	*
mbed_official	324:406fd2029f23	113	* Reset value: 0x00815101U
mbed_official	324:406fd2029f23	114	*/
mbed_official	324:406fd2029f23	115	typedef union _hw_mpu_cesr
mbed_official	324:406fd2029f23	116	{
mbed_official	324:406fd2029f23	117	uint32_t U;
mbed_official	324:406fd2029f23	118	struct _hw_mpu_cesr_bitfields
mbed_official	324:406fd2029f23	119	{
mbed_official	324:406fd2029f23	120	uint32_t VLD : 1; /!< [0] Valid /
mbed_official	324:406fd2029f23	121	uint32_t RESERVED0 : 7; /!< [7:1] /
mbed_official	324:406fd2029f23	122	uint32_t NRGD : 4; /!< [11:8] Number Of Region Descriptors /
mbed_official	324:406fd2029f23	123	uint32_t NSP : 4; /!< [15:12] Number Of Slave Ports /
mbed_official	324:406fd2029f23	124	uint32_t HRL : 4; /!< [19:16] Hardware Revision Level /
mbed_official	324:406fd2029f23	125	uint32_t RESERVED1 : 7; /!< [26:20] /
mbed_official	324:406fd2029f23	126	uint32_t SPERR : 5; /!< [31:27] Slave Port n Error /
mbed_official	324:406fd2029f23	127	} B;
mbed_official	324:406fd2029f23	128	} hw_mpu_cesr_t;
mbed_official	324:406fd2029f23	129
mbed_official	324:406fd2029f23	130	/*!
mbed_official	324:406fd2029f23	131	* @name Constants and macros for entire MPU_CESR register
mbed_official	324:406fd2029f23	132	*/
mbed_official	324:406fd2029f23	133	/@{/
mbed_official	324:406fd2029f23	134	#define HW_MPU_CESR_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	135
mbed_official	324:406fd2029f23	136	#define HW_MPU_CESR(x) ((__IO hw_mpu_cesr_t ) HW_MPU_CESR_ADDR(x))
mbed_official	324:406fd2029f23	137	#define HW_MPU_CESR_RD(x) (HW_MPU_CESR(x).U)
mbed_official	324:406fd2029f23	138	#define HW_MPU_CESR_WR(x, v) (HW_MPU_CESR(x).U = (v))
mbed_official	324:406fd2029f23	139	#define HW_MPU_CESR_SET(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) \| (v)))
mbed_official	324:406fd2029f23	140	#define HW_MPU_CESR_CLR(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	141	#define HW_MPU_CESR_TOG(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	142	/@}/
mbed_official	324:406fd2029f23	143
mbed_official	324:406fd2029f23	144	/*
mbed_official	324:406fd2029f23	145	* Constants & macros for individual MPU_CESR bitfields
mbed_official	324:406fd2029f23	146	*/
mbed_official	324:406fd2029f23	147
mbed_official	324:406fd2029f23	148	/*!
mbed_official	324:406fd2029f23	149	* @name Register MPU_CESR, field VLD[0] (RW)
mbed_official	324:406fd2029f23	150	*
mbed_official	324:406fd2029f23	151	* Global enable/disable for the MPU.
mbed_official	324:406fd2029f23	152	*
mbed_official	324:406fd2029f23	153	* Values:
mbed_official	324:406fd2029f23	154	* - 0 - MPU is disabled. All accesses from all bus masters are allowed.
mbed_official	324:406fd2029f23	155	* - 1 - MPU is enabled
mbed_official	324:406fd2029f23	156	*/
mbed_official	324:406fd2029f23	157	/@{/
mbed_official	324:406fd2029f23	158	#define BP_MPU_CESR_VLD (0U) /!< Bit position for MPU_CESR_VLD. /
mbed_official	324:406fd2029f23	159	#define BM_MPU_CESR_VLD (0x00000001U) /!< Bit mask for MPU_CESR_VLD. /
mbed_official	324:406fd2029f23	160	#define BS_MPU_CESR_VLD (1U) /!< Bit field size in bits for MPU_CESR_VLD. /
mbed_official	324:406fd2029f23	161
mbed_official	324:406fd2029f23	162	/! @brief Read current value of the MPU_CESR_VLD field. /
mbed_official	324:406fd2029f23	163	#define BR_MPU_CESR_VLD(x) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD))
mbed_official	324:406fd2029f23	164
mbed_official	324:406fd2029f23	165	/! @brief Format value for bitfield MPU_CESR_VLD. /
mbed_official	324:406fd2029f23	166	#define BF_MPU_CESR_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_VLD) & BM_MPU_CESR_VLD)
mbed_official	324:406fd2029f23	167
mbed_official	324:406fd2029f23	168	/! @brief Set the VLD field to a new value. /
mbed_official	324:406fd2029f23	169	#define BW_MPU_CESR_VLD(x, v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD) = (v))
mbed_official	324:406fd2029f23	170	/@}/
mbed_official	324:406fd2029f23	171
mbed_official	324:406fd2029f23	172	/*!
mbed_official	324:406fd2029f23	173	* @name Register MPU_CESR, field NRGD[11:8] (RO)
mbed_official	324:406fd2029f23	174	*
mbed_official	324:406fd2029f23	175	* Indicates the number of region descriptors implemented in the MPU.
mbed_official	324:406fd2029f23	176	*
mbed_official	324:406fd2029f23	177	* Values:
mbed_official	324:406fd2029f23	178	* - 0000 - 8 region descriptors
mbed_official	324:406fd2029f23	179	* - 0001 - 12 region descriptors
mbed_official	324:406fd2029f23	180	* - 0010 - 16 region descriptors
mbed_official	324:406fd2029f23	181	*/
mbed_official	324:406fd2029f23	182	/@{/
mbed_official	324:406fd2029f23	183	#define BP_MPU_CESR_NRGD (8U) /!< Bit position for MPU_CESR_NRGD. /
mbed_official	324:406fd2029f23	184	#define BM_MPU_CESR_NRGD (0x00000F00U) /!< Bit mask for MPU_CESR_NRGD. /
mbed_official	324:406fd2029f23	185	#define BS_MPU_CESR_NRGD (4U) /!< Bit field size in bits for MPU_CESR_NRGD. /
mbed_official	324:406fd2029f23	186
mbed_official	324:406fd2029f23	187	/! @brief Read current value of the MPU_CESR_NRGD field. /
mbed_official	324:406fd2029f23	188	#define BR_MPU_CESR_NRGD(x) (HW_MPU_CESR(x).B.NRGD)
mbed_official	324:406fd2029f23	189	/@}/
mbed_official	324:406fd2029f23	190
mbed_official	324:406fd2029f23	191	/*!
mbed_official	324:406fd2029f23	192	* @name Register MPU_CESR, field NSP[15:12] (RO)
mbed_official	324:406fd2029f23	193	*
mbed_official	324:406fd2029f23	194	* Specifies the number of slave ports connected to the MPU.
mbed_official	324:406fd2029f23	195	*/
mbed_official	324:406fd2029f23	196	/@{/
mbed_official	324:406fd2029f23	197	#define BP_MPU_CESR_NSP (12U) /!< Bit position for MPU_CESR_NSP. /
mbed_official	324:406fd2029f23	198	#define BM_MPU_CESR_NSP (0x0000F000U) /!< Bit mask for MPU_CESR_NSP. /
mbed_official	324:406fd2029f23	199	#define BS_MPU_CESR_NSP (4U) /!< Bit field size in bits for MPU_CESR_NSP. /
mbed_official	324:406fd2029f23	200
mbed_official	324:406fd2029f23	201	/! @brief Read current value of the MPU_CESR_NSP field. /
mbed_official	324:406fd2029f23	202	#define BR_MPU_CESR_NSP(x) (HW_MPU_CESR(x).B.NSP)
mbed_official	324:406fd2029f23	203	/@}/
mbed_official	324:406fd2029f23	204
mbed_official	324:406fd2029f23	205	/*!
mbed_official	324:406fd2029f23	206	* @name Register MPU_CESR, field HRL[19:16] (RO)
mbed_official	324:406fd2029f23	207	*
mbed_official	324:406fd2029f23	208	* Specifies the MPU's hardware and definition revision level. It can be read by
mbed_official	324:406fd2029f23	209	* software to determine the functional definition of the module.
mbed_official	324:406fd2029f23	210	*/
mbed_official	324:406fd2029f23	211	/@{/
mbed_official	324:406fd2029f23	212	#define BP_MPU_CESR_HRL (16U) /!< Bit position for MPU_CESR_HRL. /
mbed_official	324:406fd2029f23	213	#define BM_MPU_CESR_HRL (0x000F0000U) /!< Bit mask for MPU_CESR_HRL. /
mbed_official	324:406fd2029f23	214	#define BS_MPU_CESR_HRL (4U) /!< Bit field size in bits for MPU_CESR_HRL. /
mbed_official	324:406fd2029f23	215
mbed_official	324:406fd2029f23	216	/! @brief Read current value of the MPU_CESR_HRL field. /
mbed_official	324:406fd2029f23	217	#define BR_MPU_CESR_HRL(x) (HW_MPU_CESR(x).B.HRL)
mbed_official	324:406fd2029f23	218	/@}/
mbed_official	324:406fd2029f23	219
mbed_official	324:406fd2029f23	220	/*!
mbed_official	324:406fd2029f23	221	* @name Register MPU_CESR, field SPERR[31:27] (W1C)
mbed_official	324:406fd2029f23	222	*
mbed_official	324:406fd2029f23	223	* Indicates a captured error in EARn and EDRn. This bit is set when the
mbed_official	324:406fd2029f23	224	* hardware detects an error and records the faulting address and attributes. It is
mbed_official	324:406fd2029f23	225	* cleared by writing one to it. If another error is captured at the exact same cycle
mbed_official	324:406fd2029f23	226	* as the write, the flag remains set. A find-first-one instruction or
mbed_official	324:406fd2029f23	227	* equivalent can detect the presence of a captured error. The following shows the
mbed_official	324:406fd2029f23	228	* correspondence between the bit number and slave port number: Bit 31 corresponds to
mbed_official	324:406fd2029f23	229	* slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
mbed_official	324:406fd2029f23	230	* port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
mbed_official	324:406fd2029f23	231	*
mbed_official	324:406fd2029f23	232	* Values:
mbed_official	324:406fd2029f23	233	* - 0 - No error has occurred for slave port n.
mbed_official	324:406fd2029f23	234	* - 1 - An error has occurred for slave port n.
mbed_official	324:406fd2029f23	235	*/
mbed_official	324:406fd2029f23	236	/@{/
mbed_official	324:406fd2029f23	237	#define BP_MPU_CESR_SPERR (27U) /!< Bit position for MPU_CESR_SPERR. /
mbed_official	324:406fd2029f23	238	#define BM_MPU_CESR_SPERR (0xF8000000U) /!< Bit mask for MPU_CESR_SPERR. /
mbed_official	324:406fd2029f23	239	#define BS_MPU_CESR_SPERR (5U) /!< Bit field size in bits for MPU_CESR_SPERR. /
mbed_official	324:406fd2029f23	240
mbed_official	324:406fd2029f23	241	/! @brief Read current value of the MPU_CESR_SPERR field. /
mbed_official	324:406fd2029f23	242	#define BR_MPU_CESR_SPERR(x) (HW_MPU_CESR(x).B.SPERR)
mbed_official	324:406fd2029f23	243
mbed_official	324:406fd2029f23	244	/! @brief Format value for bitfield MPU_CESR_SPERR. /
mbed_official	324:406fd2029f23	245	#define BF_MPU_CESR_SPERR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_SPERR) & BM_MPU_CESR_SPERR)
mbed_official	324:406fd2029f23	246
mbed_official	324:406fd2029f23	247	/! @brief Set the SPERR field to a new value. /
mbed_official	324:406fd2029f23	248	#define BW_MPU_CESR_SPERR(x, v) (HW_MPU_CESR_WR(x, (HW_MPU_CESR_RD(x) & ~BM_MPU_CESR_SPERR) \| BF_MPU_CESR_SPERR(v)))
mbed_official	324:406fd2029f23	249	/@}/
mbed_official	324:406fd2029f23	250
mbed_official	324:406fd2029f23	251	/*******************************************************************************
mbed_official	324:406fd2029f23	252	* HW_MPU_EARn - Error Address Register, slave port n
mbed_official	324:406fd2029f23	253	******************************************************************************/
mbed_official	324:406fd2029f23	254
mbed_official	324:406fd2029f23	255	/*!
mbed_official	324:406fd2029f23	256	* @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
mbed_official	324:406fd2029f23	257	*
mbed_official	324:406fd2029f23	258	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	259	*
mbed_official	324:406fd2029f23	260	* When the MPU detects an access error on slave port n, the 32-bit reference
mbed_official	324:406fd2029f23	261	* address is captured in this read-only register and the corresponding bit in
mbed_official	324:406fd2029f23	262	* CESR[SPERR] set. Additional information about the faulting access is captured in
mbed_official	324:406fd2029f23	263	* the corresponding EDRn at the same time. This register and the corresponding
mbed_official	324:406fd2029f23	264	* EDRn contain the most recent access error; there are no hardware interlocks with
mbed_official	324:406fd2029f23	265	* CESR[SPERR], as the error registers are always loaded upon the occurrence of
mbed_official	324:406fd2029f23	266	* each protection violation.
mbed_official	324:406fd2029f23	267	*/
mbed_official	324:406fd2029f23	268	typedef union _hw_mpu_earn
mbed_official	324:406fd2029f23	269	{
mbed_official	324:406fd2029f23	270	uint32_t U;
mbed_official	324:406fd2029f23	271	struct _hw_mpu_earn_bitfields
mbed_official	324:406fd2029f23	272	{
mbed_official	324:406fd2029f23	273	uint32_t EADDR : 32; /!< [31:0] Error Address /
mbed_official	324:406fd2029f23	274	} B;
mbed_official	324:406fd2029f23	275	} hw_mpu_earn_t;
mbed_official	324:406fd2029f23	276
mbed_official	324:406fd2029f23	277	/*!
mbed_official	324:406fd2029f23	278	* @name Constants and macros for entire MPU_EARn register
mbed_official	324:406fd2029f23	279	*/
mbed_official	324:406fd2029f23	280	/@{/
mbed_official	324:406fd2029f23	281	#define HW_MPU_EARn_COUNT (5U)
mbed_official	324:406fd2029f23	282
mbed_official	324:406fd2029f23	283	#define HW_MPU_EARn_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
mbed_official	324:406fd2029f23	284
mbed_official	324:406fd2029f23	285	#define HW_MPU_EARn(x, n) ((__I hw_mpu_earn_t ) HW_MPU_EARn_ADDR(x, n))
mbed_official	324:406fd2029f23	286	#define HW_MPU_EARn_RD(x, n) (HW_MPU_EARn(x, n).U)
mbed_official	324:406fd2029f23	287	/@}/
mbed_official	324:406fd2029f23	288
mbed_official	324:406fd2029f23	289	/*
mbed_official	324:406fd2029f23	290	* Constants & macros for individual MPU_EARn bitfields
mbed_official	324:406fd2029f23	291	*/
mbed_official	324:406fd2029f23	292
mbed_official	324:406fd2029f23	293	/*!
mbed_official	324:406fd2029f23	294	* @name Register MPU_EARn, field EADDR[31:0] (RO)
mbed_official	324:406fd2029f23	295	*
mbed_official	324:406fd2029f23	296	* Indicates the reference address from slave port n that generated the access
mbed_official	324:406fd2029f23	297	* error
mbed_official	324:406fd2029f23	298	*/
mbed_official	324:406fd2029f23	299	/@{/
mbed_official	324:406fd2029f23	300	#define BP_MPU_EARn_EADDR (0U) /!< Bit position for MPU_EARn_EADDR. /
mbed_official	324:406fd2029f23	301	#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) /!< Bit mask for MPU_EARn_EADDR. /
mbed_official	324:406fd2029f23	302	#define BS_MPU_EARn_EADDR (32U) /!< Bit field size in bits for MPU_EARn_EADDR. /
mbed_official	324:406fd2029f23	303
mbed_official	324:406fd2029f23	304	/! @brief Read current value of the MPU_EARn_EADDR field. /
mbed_official	324:406fd2029f23	305	#define BR_MPU_EARn_EADDR(x, n) (HW_MPU_EARn(x, n).U)
mbed_official	324:406fd2029f23	306	/@}/
mbed_official	324:406fd2029f23	307	/*******************************************************************************
mbed_official	324:406fd2029f23	308	* HW_MPU_EDRn - Error Detail Register, slave port n
mbed_official	324:406fd2029f23	309	******************************************************************************/
mbed_official	324:406fd2029f23	310
mbed_official	324:406fd2029f23	311	/*!
mbed_official	324:406fd2029f23	312	* @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
mbed_official	324:406fd2029f23	313	*
mbed_official	324:406fd2029f23	314	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	315	*
mbed_official	324:406fd2029f23	316	* When the MPU detects an access error on slave port n, 32 bits of error detail
mbed_official	324:406fd2029f23	317	* are captured in this read-only register and the corresponding bit in
mbed_official	324:406fd2029f23	318	* CESR[SPERR] is set. Information on the faulting address is captured in the
mbed_official	324:406fd2029f23	319	* corresponding EARn register at the same time. This register and the corresponding EARn
mbed_official	324:406fd2029f23	320	* register contain the most recent access error; there are no hardware interlocks
mbed_official	324:406fd2029f23	321	* with CESR[SPERR] as the error registers are always loaded upon the occurrence
mbed_official	324:406fd2029f23	322	* of each protection violation.
mbed_official	324:406fd2029f23	323	*/
mbed_official	324:406fd2029f23	324	typedef union _hw_mpu_edrn
mbed_official	324:406fd2029f23	325	{
mbed_official	324:406fd2029f23	326	uint32_t U;
mbed_official	324:406fd2029f23	327	struct _hw_mpu_edrn_bitfields
mbed_official	324:406fd2029f23	328	{
mbed_official	324:406fd2029f23	329	uint32_t ERW : 1; /!< [0] Error Read/Write /
mbed_official	324:406fd2029f23	330	uint32_t EATTR : 3; /!< [3:1] Error Attributes /
mbed_official	324:406fd2029f23	331	uint32_t EMN : 4; /!< [7:4] Error Master Number /
mbed_official	324:406fd2029f23	332	uint32_t EPID : 8; /!< [15:8] Error Process Identification /
mbed_official	324:406fd2029f23	333	uint32_t EACD : 16; /!< [31:16] Error Access Control Detail /
mbed_official	324:406fd2029f23	334	} B;
mbed_official	324:406fd2029f23	335	} hw_mpu_edrn_t;
mbed_official	324:406fd2029f23	336
mbed_official	324:406fd2029f23	337	/*!
mbed_official	324:406fd2029f23	338	* @name Constants and macros for entire MPU_EDRn register
mbed_official	324:406fd2029f23	339	*/
mbed_official	324:406fd2029f23	340	/@{/
mbed_official	324:406fd2029f23	341	#define HW_MPU_EDRn_COUNT (5U)
mbed_official	324:406fd2029f23	342
mbed_official	324:406fd2029f23	343	#define HW_MPU_EDRn_ADDR(x, n) ((x) + 0x14U + (0x8U * (n)))
mbed_official	324:406fd2029f23	344
mbed_official	324:406fd2029f23	345	#define HW_MPU_EDRn(x, n) ((__I hw_mpu_edrn_t ) HW_MPU_EDRn_ADDR(x, n))
mbed_official	324:406fd2029f23	346	#define HW_MPU_EDRn_RD(x, n) (HW_MPU_EDRn(x, n).U)
mbed_official	324:406fd2029f23	347	/@}/
mbed_official	324:406fd2029f23	348
mbed_official	324:406fd2029f23	349	/*
mbed_official	324:406fd2029f23	350	* Constants & macros for individual MPU_EDRn bitfields
mbed_official	324:406fd2029f23	351	*/
mbed_official	324:406fd2029f23	352
mbed_official	324:406fd2029f23	353	/*!
mbed_official	324:406fd2029f23	354	* @name Register MPU_EDRn, field ERW[0] (RO)
mbed_official	324:406fd2029f23	355	*
mbed_official	324:406fd2029f23	356	* Indicates the access type of the faulting reference.
mbed_official	324:406fd2029f23	357	*
mbed_official	324:406fd2029f23	358	* Values:
mbed_official	324:406fd2029f23	359	* - 0 - Read
mbed_official	324:406fd2029f23	360	* - 1 - Write
mbed_official	324:406fd2029f23	361	*/
mbed_official	324:406fd2029f23	362	/@{/
mbed_official	324:406fd2029f23	363	#define BP_MPU_EDRn_ERW (0U) /!< Bit position for MPU_EDRn_ERW. /
mbed_official	324:406fd2029f23	364	#define BM_MPU_EDRn_ERW (0x00000001U) /!< Bit mask for MPU_EDRn_ERW. /
mbed_official	324:406fd2029f23	365	#define BS_MPU_EDRn_ERW (1U) /!< Bit field size in bits for MPU_EDRn_ERW. /
mbed_official	324:406fd2029f23	366
mbed_official	324:406fd2029f23	367	/! @brief Read current value of the MPU_EDRn_ERW field. /
mbed_official	324:406fd2029f23	368	#define BR_MPU_EDRn_ERW(x, n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(x, n), BP_MPU_EDRn_ERW))
mbed_official	324:406fd2029f23	369	/@}/
mbed_official	324:406fd2029f23	370
mbed_official	324:406fd2029f23	371	/*!
mbed_official	324:406fd2029f23	372	* @name Register MPU_EDRn, field EATTR[3:1] (RO)
mbed_official	324:406fd2029f23	373	*
mbed_official	324:406fd2029f23	374	* Indicates attribute information about the faulting reference. All other
mbed_official	324:406fd2029f23	375	* encodings are reserved.
mbed_official	324:406fd2029f23	376	*
mbed_official	324:406fd2029f23	377	* Values:
mbed_official	324:406fd2029f23	378	* - 000 - User mode, instruction access
mbed_official	324:406fd2029f23	379	* - 001 - User mode, data access
mbed_official	324:406fd2029f23	380	* - 010 - Supervisor mode, instruction access
mbed_official	324:406fd2029f23	381	* - 011 - Supervisor mode, data access
mbed_official	324:406fd2029f23	382	*/
mbed_official	324:406fd2029f23	383	/@{/
mbed_official	324:406fd2029f23	384	#define BP_MPU_EDRn_EATTR (1U) /!< Bit position for MPU_EDRn_EATTR. /
mbed_official	324:406fd2029f23	385	#define BM_MPU_EDRn_EATTR (0x0000000EU) /!< Bit mask for MPU_EDRn_EATTR. /
mbed_official	324:406fd2029f23	386	#define BS_MPU_EDRn_EATTR (3U) /!< Bit field size in bits for MPU_EDRn_EATTR. /
mbed_official	324:406fd2029f23	387
mbed_official	324:406fd2029f23	388	/! @brief Read current value of the MPU_EDRn_EATTR field. /
mbed_official	324:406fd2029f23	389	#define BR_MPU_EDRn_EATTR(x, n) (HW_MPU_EDRn(x, n).B.EATTR)
mbed_official	324:406fd2029f23	390	/@}/
mbed_official	324:406fd2029f23	391
mbed_official	324:406fd2029f23	392	/*!
mbed_official	324:406fd2029f23	393	* @name Register MPU_EDRn, field EMN[7:4] (RO)
mbed_official	324:406fd2029f23	394	*
mbed_official	324:406fd2029f23	395	* Indicates the bus master that generated the access error.
mbed_official	324:406fd2029f23	396	*/
mbed_official	324:406fd2029f23	397	/@{/
mbed_official	324:406fd2029f23	398	#define BP_MPU_EDRn_EMN (4U) /!< Bit position for MPU_EDRn_EMN. /
mbed_official	324:406fd2029f23	399	#define BM_MPU_EDRn_EMN (0x000000F0U) /!< Bit mask for MPU_EDRn_EMN. /
mbed_official	324:406fd2029f23	400	#define BS_MPU_EDRn_EMN (4U) /!< Bit field size in bits for MPU_EDRn_EMN. /
mbed_official	324:406fd2029f23	401
mbed_official	324:406fd2029f23	402	/! @brief Read current value of the MPU_EDRn_EMN field. /
mbed_official	324:406fd2029f23	403	#define BR_MPU_EDRn_EMN(x, n) (HW_MPU_EDRn(x, n).B.EMN)
mbed_official	324:406fd2029f23	404	/@}/
mbed_official	324:406fd2029f23	405
mbed_official	324:406fd2029f23	406	/*!
mbed_official	324:406fd2029f23	407	* @name Register MPU_EDRn, field EPID[15:8] (RO)
mbed_official	324:406fd2029f23	408	*
mbed_official	324:406fd2029f23	409	* Records the process identifier of the faulting reference. The process
mbed_official	324:406fd2029f23	410	* identifier is typically driven only by processor cores; for other bus masters, this
mbed_official	324:406fd2029f23	411	* field is cleared.
mbed_official	324:406fd2029f23	412	*/
mbed_official	324:406fd2029f23	413	/@{/
mbed_official	324:406fd2029f23	414	#define BP_MPU_EDRn_EPID (8U) /!< Bit position for MPU_EDRn_EPID. /
mbed_official	324:406fd2029f23	415	#define BM_MPU_EDRn_EPID (0x0000FF00U) /!< Bit mask for MPU_EDRn_EPID. /
mbed_official	324:406fd2029f23	416	#define BS_MPU_EDRn_EPID (8U) /!< Bit field size in bits for MPU_EDRn_EPID. /
mbed_official	324:406fd2029f23	417
mbed_official	324:406fd2029f23	418	/! @brief Read current value of the MPU_EDRn_EPID field. /
mbed_official	324:406fd2029f23	419	#define BR_MPU_EDRn_EPID(x, n) (HW_MPU_EDRn(x, n).B.EPID)
mbed_official	324:406fd2029f23	420	/@}/
mbed_official	324:406fd2029f23	421
mbed_official	324:406fd2029f23	422	/*!
mbed_official	324:406fd2029f23	423	* @name Register MPU_EDRn, field EACD[31:16] (RO)
mbed_official	324:406fd2029f23	424	*
mbed_official	324:406fd2029f23	425	* Indicates the region descriptor with the access error. If EDRn contains a
mbed_official	324:406fd2029f23	426	* captured error and EACD is cleared, an access did not hit in any region
mbed_official	324:406fd2029f23	427	* descriptor. If only a single EACD bit is set, the protection error was caused by a
mbed_official	324:406fd2029f23	428	* single non-overlapping region descriptor. If two or more EACD bits are set, the
mbed_official	324:406fd2029f23	429	* protection error was caused by an overlapping set of region descriptors.
mbed_official	324:406fd2029f23	430	*/
mbed_official	324:406fd2029f23	431	/@{/
mbed_official	324:406fd2029f23	432	#define BP_MPU_EDRn_EACD (16U) /!< Bit position for MPU_EDRn_EACD. /
mbed_official	324:406fd2029f23	433	#define BM_MPU_EDRn_EACD (0xFFFF0000U) /!< Bit mask for MPU_EDRn_EACD. /
mbed_official	324:406fd2029f23	434	#define BS_MPU_EDRn_EACD (16U) /!< Bit field size in bits for MPU_EDRn_EACD. /
mbed_official	324:406fd2029f23	435
mbed_official	324:406fd2029f23	436	/! @brief Read current value of the MPU_EDRn_EACD field. /
mbed_official	324:406fd2029f23	437	#define BR_MPU_EDRn_EACD(x, n) (HW_MPU_EDRn(x, n).B.EACD)
mbed_official	324:406fd2029f23	438	/@}/
mbed_official	324:406fd2029f23	439
mbed_official	324:406fd2029f23	440	/*******************************************************************************
mbed_official	324:406fd2029f23	441	* HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
mbed_official	324:406fd2029f23	442	******************************************************************************/
mbed_official	324:406fd2029f23	443
mbed_official	324:406fd2029f23	444	/*!
mbed_official	324:406fd2029f23	445	* @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
mbed_official	324:406fd2029f23	446	*
mbed_official	324:406fd2029f23	447	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	448	*
mbed_official	324:406fd2029f23	449	* The first word of the region descriptor defines the 0-modulo-32 byte start
mbed_official	324:406fd2029f23	450	* address of the memory region. Writes to this register clear the region
mbed_official	324:406fd2029f23	451	* descriptor's valid bit (RGDn_WORD3[VLD]).
mbed_official	324:406fd2029f23	452	*/
mbed_official	324:406fd2029f23	453	typedef union _hw_mpu_rgdn_word0
mbed_official	324:406fd2029f23	454	{
mbed_official	324:406fd2029f23	455	uint32_t U;
mbed_official	324:406fd2029f23	456	struct _hw_mpu_rgdn_word0_bitfields
mbed_official	324:406fd2029f23	457	{
mbed_official	324:406fd2029f23	458	uint32_t RESERVED0 : 5; /!< [4:0] /
mbed_official	324:406fd2029f23	459	uint32_t SRTADDR : 27; /!< [31:5] Start Address /
mbed_official	324:406fd2029f23	460	} B;
mbed_official	324:406fd2029f23	461	} hw_mpu_rgdn_word0_t;
mbed_official	324:406fd2029f23	462
mbed_official	324:406fd2029f23	463	/*!
mbed_official	324:406fd2029f23	464	* @name Constants and macros for entire MPU_RGDn_WORD0 register
mbed_official	324:406fd2029f23	465	*/
mbed_official	324:406fd2029f23	466	/@{/
mbed_official	324:406fd2029f23	467	#define HW_MPU_RGDn_WORD0_COUNT (12U)
mbed_official	324:406fd2029f23	468
mbed_official	324:406fd2029f23	469	#define HW_MPU_RGDn_WORD0_ADDR(x, n) ((x) + 0x400U + (0x10U * (n)))
mbed_official	324:406fd2029f23	470
mbed_official	324:406fd2029f23	471	#define HW_MPU_RGDn_WORD0(x, n) ((__IO hw_mpu_rgdn_word0_t ) HW_MPU_RGDn_WORD0_ADDR(x, n))
mbed_official	324:406fd2029f23	472	#define HW_MPU_RGDn_WORD0_RD(x, n) (HW_MPU_RGDn_WORD0(x, n).U)
mbed_official	324:406fd2029f23	473	#define HW_MPU_RGDn_WORD0_WR(x, n, v) (HW_MPU_RGDn_WORD0(x, n).U = (v))
mbed_official	324:406fd2029f23	474	#define HW_MPU_RGDn_WORD0_SET(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	475	#define HW_MPU_RGDn_WORD0_CLR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	476	#define HW_MPU_RGDn_WORD0_TOG(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	477	/@}/
mbed_official	324:406fd2029f23	478
mbed_official	324:406fd2029f23	479	/*
mbed_official	324:406fd2029f23	480	* Constants & macros for individual MPU_RGDn_WORD0 bitfields
mbed_official	324:406fd2029f23	481	*/
mbed_official	324:406fd2029f23	482
mbed_official	324:406fd2029f23	483	/*!
mbed_official	324:406fd2029f23	484	* @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
mbed_official	324:406fd2029f23	485	*
mbed_official	324:406fd2029f23	486	* Defines the most significant bits of the 0-modulo-32 byte start address of
mbed_official	324:406fd2029f23	487	* the memory region.
mbed_official	324:406fd2029f23	488	*/
mbed_official	324:406fd2029f23	489	/@{/
mbed_official	324:406fd2029f23	490	#define BP_MPU_RGDn_WORD0_SRTADDR (5U) /!< Bit position for MPU_RGDn_WORD0_SRTADDR. /
mbed_official	324:406fd2029f23	491	#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) /!< Bit mask for MPU_RGDn_WORD0_SRTADDR. /
mbed_official	324:406fd2029f23	492	#define BS_MPU_RGDn_WORD0_SRTADDR (27U) /!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR. /
mbed_official	324:406fd2029f23	493
mbed_official	324:406fd2029f23	494	/! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field. /
mbed_official	324:406fd2029f23	495	#define BR_MPU_RGDn_WORD0_SRTADDR(x, n) (HW_MPU_RGDn_WORD0(x, n).B.SRTADDR)
mbed_official	324:406fd2029f23	496
mbed_official	324:406fd2029f23	497	/! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR. /
mbed_official	324:406fd2029f23	498	#define BF_MPU_RGDn_WORD0_SRTADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD0_SRTADDR) & BM_MPU_RGDn_WORD0_SRTADDR)
mbed_official	324:406fd2029f23	499
mbed_official	324:406fd2029f23	500	/! @brief Set the SRTADDR field to a new value. /
mbed_official	324:406fd2029f23	501	#define BW_MPU_RGDn_WORD0_SRTADDR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, (HW_MPU_RGDn_WORD0_RD(x, n) & ~BM_MPU_RGDn_WORD0_SRTADDR) \| BF_MPU_RGDn_WORD0_SRTADDR(v)))
mbed_official	324:406fd2029f23	502	/@}/
mbed_official	324:406fd2029f23	503	/*******************************************************************************
mbed_official	324:406fd2029f23	504	* HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
mbed_official	324:406fd2029f23	505	******************************************************************************/
mbed_official	324:406fd2029f23	506
mbed_official	324:406fd2029f23	507	/*!
mbed_official	324:406fd2029f23	508	* @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
mbed_official	324:406fd2029f23	509	*
mbed_official	324:406fd2029f23	510	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	511	*
mbed_official	324:406fd2029f23	512	* The second word of the region descriptor defines the 31-modulo-32 byte end
mbed_official	324:406fd2029f23	513	* address of the memory region. Writes to this register clear the region
mbed_official	324:406fd2029f23	514	* descriptor's valid bit (RGDn_WORD3[VLD]).
mbed_official	324:406fd2029f23	515	*/
mbed_official	324:406fd2029f23	516	typedef union _hw_mpu_rgdn_word1
mbed_official	324:406fd2029f23	517	{
mbed_official	324:406fd2029f23	518	uint32_t U;
mbed_official	324:406fd2029f23	519	struct _hw_mpu_rgdn_word1_bitfields
mbed_official	324:406fd2029f23	520	{
mbed_official	324:406fd2029f23	521	uint32_t RESERVED0 : 5; /!< [4:0] /
mbed_official	324:406fd2029f23	522	uint32_t ENDADDR : 27; /!< [31:5] End Address /
mbed_official	324:406fd2029f23	523	} B;
mbed_official	324:406fd2029f23	524	} hw_mpu_rgdn_word1_t;
mbed_official	324:406fd2029f23	525
mbed_official	324:406fd2029f23	526	/*!
mbed_official	324:406fd2029f23	527	* @name Constants and macros for entire MPU_RGDn_WORD1 register
mbed_official	324:406fd2029f23	528	*/
mbed_official	324:406fd2029f23	529	/@{/
mbed_official	324:406fd2029f23	530	#define HW_MPU_RGDn_WORD1_COUNT (12U)
mbed_official	324:406fd2029f23	531
mbed_official	324:406fd2029f23	532	#define HW_MPU_RGDn_WORD1_ADDR(x, n) ((x) + 0x404U + (0x10U * (n)))
mbed_official	324:406fd2029f23	533
mbed_official	324:406fd2029f23	534	#define HW_MPU_RGDn_WORD1(x, n) ((__IO hw_mpu_rgdn_word1_t ) HW_MPU_RGDn_WORD1_ADDR(x, n))
mbed_official	324:406fd2029f23	535	#define HW_MPU_RGDn_WORD1_RD(x, n) (HW_MPU_RGDn_WORD1(x, n).U)
mbed_official	324:406fd2029f23	536	#define HW_MPU_RGDn_WORD1_WR(x, n, v) (HW_MPU_RGDn_WORD1(x, n).U = (v))
mbed_official	324:406fd2029f23	537	#define HW_MPU_RGDn_WORD1_SET(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	538	#define HW_MPU_RGDn_WORD1_CLR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	539	#define HW_MPU_RGDn_WORD1_TOG(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	540	/@}/
mbed_official	324:406fd2029f23	541
mbed_official	324:406fd2029f23	542	/*
mbed_official	324:406fd2029f23	543	* Constants & macros for individual MPU_RGDn_WORD1 bitfields
mbed_official	324:406fd2029f23	544	*/
mbed_official	324:406fd2029f23	545
mbed_official	324:406fd2029f23	546	/*!
mbed_official	324:406fd2029f23	547	* @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
mbed_official	324:406fd2029f23	548	*
mbed_official	324:406fd2029f23	549	* Defines the most significant bits of the 31-modulo-32 byte end address of the
mbed_official	324:406fd2029f23	550	* memory region. The MPU does not verify that ENDADDR >= SRTADDR.
mbed_official	324:406fd2029f23	551	*/
mbed_official	324:406fd2029f23	552	/@{/
mbed_official	324:406fd2029f23	553	#define BP_MPU_RGDn_WORD1_ENDADDR (5U) /!< Bit position for MPU_RGDn_WORD1_ENDADDR. /
mbed_official	324:406fd2029f23	554	#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) /!< Bit mask for MPU_RGDn_WORD1_ENDADDR. /
mbed_official	324:406fd2029f23	555	#define BS_MPU_RGDn_WORD1_ENDADDR (27U) /!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR. /
mbed_official	324:406fd2029f23	556
mbed_official	324:406fd2029f23	557	/! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field. /
mbed_official	324:406fd2029f23	558	#define BR_MPU_RGDn_WORD1_ENDADDR(x, n) (HW_MPU_RGDn_WORD1(x, n).B.ENDADDR)
mbed_official	324:406fd2029f23	559
mbed_official	324:406fd2029f23	560	/! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR. /
mbed_official	324:406fd2029f23	561	#define BF_MPU_RGDn_WORD1_ENDADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD1_ENDADDR) & BM_MPU_RGDn_WORD1_ENDADDR)
mbed_official	324:406fd2029f23	562
mbed_official	324:406fd2029f23	563	/! @brief Set the ENDADDR field to a new value. /
mbed_official	324:406fd2029f23	564	#define BW_MPU_RGDn_WORD1_ENDADDR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, (HW_MPU_RGDn_WORD1_RD(x, n) & ~BM_MPU_RGDn_WORD1_ENDADDR) \| BF_MPU_RGDn_WORD1_ENDADDR(v)))
mbed_official	324:406fd2029f23	565	/@}/
mbed_official	324:406fd2029f23	566	/*******************************************************************************
mbed_official	324:406fd2029f23	567	* HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
mbed_official	324:406fd2029f23	568	******************************************************************************/
mbed_official	324:406fd2029f23	569
mbed_official	324:406fd2029f23	570	/*!
mbed_official	324:406fd2029f23	571	* @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
mbed_official	324:406fd2029f23	572	*
mbed_official	324:406fd2029f23	573	* Reset value: 0x0061F7DFU
mbed_official	324:406fd2029f23	574	*
mbed_official	324:406fd2029f23	575	* The third word of the region descriptor defines the access control rights of
mbed_official	324:406fd2029f23	576	* the memory region. The access control privileges depend on two broad
mbed_official	324:406fd2029f23	577	* classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
mbed_official	324:406fd2029f23	578	* privilege rights for user and supervisor mode accesses, as well as the optional
mbed_official	324:406fd2029f23	579	* inclusion of a process identification field within the definition. Bus masters
mbed_official	324:406fd2029f23	580	* 4-7 are limited to separate read and write permissions. For the privilege
mbed_official	324:406fd2029f23	581	* rights of bus masters 0-3, there are three flags associated with this function:
mbed_official	324:406fd2029f23	582	* Read (r) refers to accessing the referenced memory address using an operand
mbed_official	324:406fd2029f23	583	* (data) fetch Write (w) refers to updating the referenced memory address using a
mbed_official	324:406fd2029f23	584	* store (data) instruction Execute (x) refers to reading the referenced memory
mbed_official	324:406fd2029f23	585	* address using an instruction fetch Writes to RGDn_WORD2 clear the region
mbed_official	324:406fd2029f23	586	* descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
mbed_official	324:406fd2029f23	587	* to RGDAACn instead because stores to these locations do not affect the
mbed_official	324:406fd2029f23	588	* descriptor's valid bit.
mbed_official	324:406fd2029f23	589	*/
mbed_official	324:406fd2029f23	590	typedef union _hw_mpu_rgdn_word2
mbed_official	324:406fd2029f23	591	{
mbed_official	324:406fd2029f23	592	uint32_t U;
mbed_official	324:406fd2029f23	593	struct _hw_mpu_rgdn_word2_bitfields
mbed_official	324:406fd2029f23	594	{
mbed_official	324:406fd2029f23	595	uint32_t M0UM : 3; /!< [2:0] Bus Master 0 User Mode Access Control /
mbed_official	324:406fd2029f23	596	uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access
mbed_official	324:406fd2029f23	597	* Control */
mbed_official	324:406fd2029f23	598	uint32_t M0PE : 1; /!< [5] Bus Master 0 Process Identifier enable /
mbed_official	324:406fd2029f23	599	uint32_t M1UM : 3; /!< [8:6] Bus Master 1 User Mode Access Control /
mbed_official	324:406fd2029f23	600	uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access
mbed_official	324:406fd2029f23	601	* Control */
mbed_official	324:406fd2029f23	602	uint32_t M1PE : 1; /!< [11] Bus Master 1 Process Identifier enable /
mbed_official	324:406fd2029f23	603	uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access control
mbed_official	324:406fd2029f23	604	* */
mbed_official	324:406fd2029f23	605	uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access
mbed_official	324:406fd2029f23	606	* Control */
mbed_official	324:406fd2029f23	607	uint32_t M2PE : 1; /!< [17] Bus Master 2 Process Identifier Enable /
mbed_official	324:406fd2029f23	608	uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control
mbed_official	324:406fd2029f23	609	* */
mbed_official	324:406fd2029f23	610	uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access
mbed_official	324:406fd2029f23	611	* Control */
mbed_official	324:406fd2029f23	612	uint32_t M3PE : 1; /!< [23] Bus Master 3 Process Identifier Enable /
mbed_official	324:406fd2029f23	613	uint32_t M4WE : 1; /!< [24] Bus Master 4 Write Enable /
mbed_official	324:406fd2029f23	614	uint32_t M4RE : 1; /!< [25] Bus Master 4 Read Enable /
mbed_official	324:406fd2029f23	615	uint32_t M5WE : 1; /!< [26] Bus Master 5 Write Enable /
mbed_official	324:406fd2029f23	616	uint32_t M5RE : 1; /!< [27] Bus Master 5 Read Enable /
mbed_official	324:406fd2029f23	617	uint32_t M6WE : 1; /!< [28] Bus Master 6 Write Enable /
mbed_official	324:406fd2029f23	618	uint32_t M6RE : 1; /!< [29] Bus Master 6 Read Enable /
mbed_official	324:406fd2029f23	619	uint32_t M7WE : 1; /!< [30] Bus Master 7 Write Enable /
mbed_official	324:406fd2029f23	620	uint32_t M7RE : 1; /!< [31] Bus Master 7 Read Enable /
mbed_official	324:406fd2029f23	621	} B;
mbed_official	324:406fd2029f23	622	} hw_mpu_rgdn_word2_t;
mbed_official	324:406fd2029f23	623
mbed_official	324:406fd2029f23	624	/*!
mbed_official	324:406fd2029f23	625	* @name Constants and macros for entire MPU_RGDn_WORD2 register
mbed_official	324:406fd2029f23	626	*/
mbed_official	324:406fd2029f23	627	/@{/
mbed_official	324:406fd2029f23	628	#define HW_MPU_RGDn_WORD2_COUNT (12U)
mbed_official	324:406fd2029f23	629
mbed_official	324:406fd2029f23	630	#define HW_MPU_RGDn_WORD2_ADDR(x, n) ((x) + 0x408U + (0x10U * (n)))
mbed_official	324:406fd2029f23	631
mbed_official	324:406fd2029f23	632	#define HW_MPU_RGDn_WORD2(x, n) ((__IO hw_mpu_rgdn_word2_t ) HW_MPU_RGDn_WORD2_ADDR(x, n))
mbed_official	324:406fd2029f23	633	#define HW_MPU_RGDn_WORD2_RD(x, n) (HW_MPU_RGDn_WORD2(x, n).U)
mbed_official	324:406fd2029f23	634	#define HW_MPU_RGDn_WORD2_WR(x, n, v) (HW_MPU_RGDn_WORD2(x, n).U = (v))
mbed_official	324:406fd2029f23	635	#define HW_MPU_RGDn_WORD2_SET(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	636	#define HW_MPU_RGDn_WORD2_CLR(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	637	#define HW_MPU_RGDn_WORD2_TOG(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	638	/@}/
mbed_official	324:406fd2029f23	639
mbed_official	324:406fd2029f23	640	/*
mbed_official	324:406fd2029f23	641	* Constants & macros for individual MPU_RGDn_WORD2 bitfields
mbed_official	324:406fd2029f23	642	*/
mbed_official	324:406fd2029f23	643
mbed_official	324:406fd2029f23	644	/*!
mbed_official	324:406fd2029f23	645	* @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
mbed_official	324:406fd2029f23	646	*
mbed_official	324:406fd2029f23	647	* See M3UM description.
mbed_official	324:406fd2029f23	648	*/
mbed_official	324:406fd2029f23	649	/@{/
mbed_official	324:406fd2029f23	650	#define BP_MPU_RGDn_WORD2_M0UM (0U) /!< Bit position for MPU_RGDn_WORD2_M0UM. /
mbed_official	324:406fd2029f23	651	#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) /!< Bit mask for MPU_RGDn_WORD2_M0UM. /
mbed_official	324:406fd2029f23	652	#define BS_MPU_RGDn_WORD2_M0UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0UM. /
mbed_official	324:406fd2029f23	653
mbed_official	324:406fd2029f23	654	/! @brief Read current value of the MPU_RGDn_WORD2_M0UM field. /
mbed_official	324:406fd2029f23	655	#define BR_MPU_RGDn_WORD2_M0UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0UM)
mbed_official	324:406fd2029f23	656
mbed_official	324:406fd2029f23	657	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM. /
mbed_official	324:406fd2029f23	658	#define BF_MPU_RGDn_WORD2_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0UM) & BM_MPU_RGDn_WORD2_M0UM)
mbed_official	324:406fd2029f23	659
mbed_official	324:406fd2029f23	660	/! @brief Set the M0UM field to a new value. /
mbed_official	324:406fd2029f23	661	#define BW_MPU_RGDn_WORD2_M0UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0UM) \| BF_MPU_RGDn_WORD2_M0UM(v)))
mbed_official	324:406fd2029f23	662	/@}/
mbed_official	324:406fd2029f23	663
mbed_official	324:406fd2029f23	664	/*!
mbed_official	324:406fd2029f23	665	* @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
mbed_official	324:406fd2029f23	666	*
mbed_official	324:406fd2029f23	667	* See M3SM description.
mbed_official	324:406fd2029f23	668	*/
mbed_official	324:406fd2029f23	669	/@{/
mbed_official	324:406fd2029f23	670	#define BP_MPU_RGDn_WORD2_M0SM (3U) /!< Bit position for MPU_RGDn_WORD2_M0SM. /
mbed_official	324:406fd2029f23	671	#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) /!< Bit mask for MPU_RGDn_WORD2_M0SM. /
mbed_official	324:406fd2029f23	672	#define BS_MPU_RGDn_WORD2_M0SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0SM. /
mbed_official	324:406fd2029f23	673
mbed_official	324:406fd2029f23	674	/! @brief Read current value of the MPU_RGDn_WORD2_M0SM field. /
mbed_official	324:406fd2029f23	675	#define BR_MPU_RGDn_WORD2_M0SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0SM)
mbed_official	324:406fd2029f23	676
mbed_official	324:406fd2029f23	677	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM. /
mbed_official	324:406fd2029f23	678	#define BF_MPU_RGDn_WORD2_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0SM) & BM_MPU_RGDn_WORD2_M0SM)
mbed_official	324:406fd2029f23	679
mbed_official	324:406fd2029f23	680	/! @brief Set the M0SM field to a new value. /
mbed_official	324:406fd2029f23	681	#define BW_MPU_RGDn_WORD2_M0SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0SM) \| BF_MPU_RGDn_WORD2_M0SM(v)))
mbed_official	324:406fd2029f23	682	/@}/
mbed_official	324:406fd2029f23	683
mbed_official	324:406fd2029f23	684	/*!
mbed_official	324:406fd2029f23	685	* @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
mbed_official	324:406fd2029f23	686	*
mbed_official	324:406fd2029f23	687	* See M0PE description.
mbed_official	324:406fd2029f23	688	*/
mbed_official	324:406fd2029f23	689	/@{/
mbed_official	324:406fd2029f23	690	#define BP_MPU_RGDn_WORD2_M0PE (5U) /!< Bit position for MPU_RGDn_WORD2_M0PE. /
mbed_official	324:406fd2029f23	691	#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) /!< Bit mask for MPU_RGDn_WORD2_M0PE. /
mbed_official	324:406fd2029f23	692	#define BS_MPU_RGDn_WORD2_M0PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0PE. /
mbed_official	324:406fd2029f23	693
mbed_official	324:406fd2029f23	694	/! @brief Read current value of the MPU_RGDn_WORD2_M0PE field. /
mbed_official	324:406fd2029f23	695	#define BR_MPU_RGDn_WORD2_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE))
mbed_official	324:406fd2029f23	696
mbed_official	324:406fd2029f23	697	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE. /
mbed_official	324:406fd2029f23	698	#define BF_MPU_RGDn_WORD2_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0PE) & BM_MPU_RGDn_WORD2_M0PE)
mbed_official	324:406fd2029f23	699
mbed_official	324:406fd2029f23	700	/! @brief Set the M0PE field to a new value. /
mbed_official	324:406fd2029f23	701	#define BW_MPU_RGDn_WORD2_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE) = (v))
mbed_official	324:406fd2029f23	702	/@}/
mbed_official	324:406fd2029f23	703
mbed_official	324:406fd2029f23	704	/*!
mbed_official	324:406fd2029f23	705	* @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
mbed_official	324:406fd2029f23	706	*
mbed_official	324:406fd2029f23	707	* See M3UM description.
mbed_official	324:406fd2029f23	708	*/
mbed_official	324:406fd2029f23	709	/@{/
mbed_official	324:406fd2029f23	710	#define BP_MPU_RGDn_WORD2_M1UM (6U) /!< Bit position for MPU_RGDn_WORD2_M1UM. /
mbed_official	324:406fd2029f23	711	#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) /!< Bit mask for MPU_RGDn_WORD2_M1UM. /
mbed_official	324:406fd2029f23	712	#define BS_MPU_RGDn_WORD2_M1UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1UM. /
mbed_official	324:406fd2029f23	713
mbed_official	324:406fd2029f23	714	/! @brief Read current value of the MPU_RGDn_WORD2_M1UM field. /
mbed_official	324:406fd2029f23	715	#define BR_MPU_RGDn_WORD2_M1UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1UM)
mbed_official	324:406fd2029f23	716
mbed_official	324:406fd2029f23	717	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM. /
mbed_official	324:406fd2029f23	718	#define BF_MPU_RGDn_WORD2_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1UM) & BM_MPU_RGDn_WORD2_M1UM)
mbed_official	324:406fd2029f23	719
mbed_official	324:406fd2029f23	720	/! @brief Set the M1UM field to a new value. /
mbed_official	324:406fd2029f23	721	#define BW_MPU_RGDn_WORD2_M1UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1UM) \| BF_MPU_RGDn_WORD2_M1UM(v)))
mbed_official	324:406fd2029f23	722	/@}/
mbed_official	324:406fd2029f23	723
mbed_official	324:406fd2029f23	724	/*!
mbed_official	324:406fd2029f23	725	* @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
mbed_official	324:406fd2029f23	726	*
mbed_official	324:406fd2029f23	727	* See M3SM description.
mbed_official	324:406fd2029f23	728	*/
mbed_official	324:406fd2029f23	729	/@{/
mbed_official	324:406fd2029f23	730	#define BP_MPU_RGDn_WORD2_M1SM (9U) /!< Bit position for MPU_RGDn_WORD2_M1SM. /
mbed_official	324:406fd2029f23	731	#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) /!< Bit mask for MPU_RGDn_WORD2_M1SM. /
mbed_official	324:406fd2029f23	732	#define BS_MPU_RGDn_WORD2_M1SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1SM. /
mbed_official	324:406fd2029f23	733
mbed_official	324:406fd2029f23	734	/! @brief Read current value of the MPU_RGDn_WORD2_M1SM field. /
mbed_official	324:406fd2029f23	735	#define BR_MPU_RGDn_WORD2_M1SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1SM)
mbed_official	324:406fd2029f23	736
mbed_official	324:406fd2029f23	737	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM. /
mbed_official	324:406fd2029f23	738	#define BF_MPU_RGDn_WORD2_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1SM) & BM_MPU_RGDn_WORD2_M1SM)
mbed_official	324:406fd2029f23	739
mbed_official	324:406fd2029f23	740	/! @brief Set the M1SM field to a new value. /
mbed_official	324:406fd2029f23	741	#define BW_MPU_RGDn_WORD2_M1SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1SM) \| BF_MPU_RGDn_WORD2_M1SM(v)))
mbed_official	324:406fd2029f23	742	/@}/
mbed_official	324:406fd2029f23	743
mbed_official	324:406fd2029f23	744	/*!
mbed_official	324:406fd2029f23	745	* @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
mbed_official	324:406fd2029f23	746	*
mbed_official	324:406fd2029f23	747	* See M3PE description.
mbed_official	324:406fd2029f23	748	*/
mbed_official	324:406fd2029f23	749	/@{/
mbed_official	324:406fd2029f23	750	#define BP_MPU_RGDn_WORD2_M1PE (11U) /!< Bit position for MPU_RGDn_WORD2_M1PE. /
mbed_official	324:406fd2029f23	751	#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) /!< Bit mask for MPU_RGDn_WORD2_M1PE. /
mbed_official	324:406fd2029f23	752	#define BS_MPU_RGDn_WORD2_M1PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1PE. /
mbed_official	324:406fd2029f23	753
mbed_official	324:406fd2029f23	754	/! @brief Read current value of the MPU_RGDn_WORD2_M1PE field. /
mbed_official	324:406fd2029f23	755	#define BR_MPU_RGDn_WORD2_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE))
mbed_official	324:406fd2029f23	756
mbed_official	324:406fd2029f23	757	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE. /
mbed_official	324:406fd2029f23	758	#define BF_MPU_RGDn_WORD2_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1PE) & BM_MPU_RGDn_WORD2_M1PE)
mbed_official	324:406fd2029f23	759
mbed_official	324:406fd2029f23	760	/! @brief Set the M1PE field to a new value. /
mbed_official	324:406fd2029f23	761	#define BW_MPU_RGDn_WORD2_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE) = (v))
mbed_official	324:406fd2029f23	762	/@}/
mbed_official	324:406fd2029f23	763
mbed_official	324:406fd2029f23	764	/*!
mbed_official	324:406fd2029f23	765	* @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
mbed_official	324:406fd2029f23	766	*
mbed_official	324:406fd2029f23	767	* See M3UM description.
mbed_official	324:406fd2029f23	768	*/
mbed_official	324:406fd2029f23	769	/@{/
mbed_official	324:406fd2029f23	770	#define BP_MPU_RGDn_WORD2_M2UM (12U) /!< Bit position for MPU_RGDn_WORD2_M2UM. /
mbed_official	324:406fd2029f23	771	#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) /!< Bit mask for MPU_RGDn_WORD2_M2UM. /
mbed_official	324:406fd2029f23	772	#define BS_MPU_RGDn_WORD2_M2UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2UM. /
mbed_official	324:406fd2029f23	773
mbed_official	324:406fd2029f23	774	/! @brief Read current value of the MPU_RGDn_WORD2_M2UM field. /
mbed_official	324:406fd2029f23	775	#define BR_MPU_RGDn_WORD2_M2UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2UM)
mbed_official	324:406fd2029f23	776
mbed_official	324:406fd2029f23	777	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM. /
mbed_official	324:406fd2029f23	778	#define BF_MPU_RGDn_WORD2_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2UM) & BM_MPU_RGDn_WORD2_M2UM)
mbed_official	324:406fd2029f23	779
mbed_official	324:406fd2029f23	780	/! @brief Set the M2UM field to a new value. /
mbed_official	324:406fd2029f23	781	#define BW_MPU_RGDn_WORD2_M2UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2UM) \| BF_MPU_RGDn_WORD2_M2UM(v)))
mbed_official	324:406fd2029f23	782	/@}/
mbed_official	324:406fd2029f23	783
mbed_official	324:406fd2029f23	784	/*!
mbed_official	324:406fd2029f23	785	* @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
mbed_official	324:406fd2029f23	786	*
mbed_official	324:406fd2029f23	787	* See M3SM description.
mbed_official	324:406fd2029f23	788	*/
mbed_official	324:406fd2029f23	789	/@{/
mbed_official	324:406fd2029f23	790	#define BP_MPU_RGDn_WORD2_M2SM (15U) /!< Bit position for MPU_RGDn_WORD2_M2SM. /
mbed_official	324:406fd2029f23	791	#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) /!< Bit mask for MPU_RGDn_WORD2_M2SM. /
mbed_official	324:406fd2029f23	792	#define BS_MPU_RGDn_WORD2_M2SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2SM. /
mbed_official	324:406fd2029f23	793
mbed_official	324:406fd2029f23	794	/! @brief Read current value of the MPU_RGDn_WORD2_M2SM field. /
mbed_official	324:406fd2029f23	795	#define BR_MPU_RGDn_WORD2_M2SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2SM)
mbed_official	324:406fd2029f23	796
mbed_official	324:406fd2029f23	797	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM. /
mbed_official	324:406fd2029f23	798	#define BF_MPU_RGDn_WORD2_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2SM) & BM_MPU_RGDn_WORD2_M2SM)
mbed_official	324:406fd2029f23	799
mbed_official	324:406fd2029f23	800	/! @brief Set the M2SM field to a new value. /
mbed_official	324:406fd2029f23	801	#define BW_MPU_RGDn_WORD2_M2SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2SM) \| BF_MPU_RGDn_WORD2_M2SM(v)))
mbed_official	324:406fd2029f23	802	/@}/
mbed_official	324:406fd2029f23	803
mbed_official	324:406fd2029f23	804	/*!
mbed_official	324:406fd2029f23	805	* @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
mbed_official	324:406fd2029f23	806	*
mbed_official	324:406fd2029f23	807	* See M3PE description.
mbed_official	324:406fd2029f23	808	*/
mbed_official	324:406fd2029f23	809	/@{/
mbed_official	324:406fd2029f23	810	#define BP_MPU_RGDn_WORD2_M2PE (17U) /!< Bit position for MPU_RGDn_WORD2_M2PE. /
mbed_official	324:406fd2029f23	811	#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) /!< Bit mask for MPU_RGDn_WORD2_M2PE. /
mbed_official	324:406fd2029f23	812	#define BS_MPU_RGDn_WORD2_M2PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2PE. /
mbed_official	324:406fd2029f23	813
mbed_official	324:406fd2029f23	814	/! @brief Read current value of the MPU_RGDn_WORD2_M2PE field. /
mbed_official	324:406fd2029f23	815	#define BR_MPU_RGDn_WORD2_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE))
mbed_official	324:406fd2029f23	816
mbed_official	324:406fd2029f23	817	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE. /
mbed_official	324:406fd2029f23	818	#define BF_MPU_RGDn_WORD2_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2PE) & BM_MPU_RGDn_WORD2_M2PE)
mbed_official	324:406fd2029f23	819
mbed_official	324:406fd2029f23	820	/! @brief Set the M2PE field to a new value. /
mbed_official	324:406fd2029f23	821	#define BW_MPU_RGDn_WORD2_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE) = (v))
mbed_official	324:406fd2029f23	822	/@}/
mbed_official	324:406fd2029f23	823
mbed_official	324:406fd2029f23	824	/*!
mbed_official	324:406fd2029f23	825	* @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
mbed_official	324:406fd2029f23	826	*
mbed_official	324:406fd2029f23	827	* Defines the access controls for bus master 3 in User mode. M3UM consists of
mbed_official	324:406fd2029f23	828	* three independent bits, enabling read (r), write (w), and execute (x)
mbed_official	324:406fd2029f23	829	* permissions.
mbed_official	324:406fd2029f23	830	*
mbed_official	324:406fd2029f23	831	* Values:
mbed_official	324:406fd2029f23	832	* - 0 - An attempted access of that mode may be terminated with an access error
mbed_official	324:406fd2029f23	833	* (if not allowed by another descriptor) and the access not performed.
mbed_official	324:406fd2029f23	834	* - 1 - Allows the given access type to occur
mbed_official	324:406fd2029f23	835	*/
mbed_official	324:406fd2029f23	836	/@{/
mbed_official	324:406fd2029f23	837	#define BP_MPU_RGDn_WORD2_M3UM (18U) /!< Bit position for MPU_RGDn_WORD2_M3UM. /
mbed_official	324:406fd2029f23	838	#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) /!< Bit mask for MPU_RGDn_WORD2_M3UM. /
mbed_official	324:406fd2029f23	839	#define BS_MPU_RGDn_WORD2_M3UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3UM. /
mbed_official	324:406fd2029f23	840
mbed_official	324:406fd2029f23	841	/! @brief Read current value of the MPU_RGDn_WORD2_M3UM field. /
mbed_official	324:406fd2029f23	842	#define BR_MPU_RGDn_WORD2_M3UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3UM)
mbed_official	324:406fd2029f23	843
mbed_official	324:406fd2029f23	844	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM. /
mbed_official	324:406fd2029f23	845	#define BF_MPU_RGDn_WORD2_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3UM) & BM_MPU_RGDn_WORD2_M3UM)
mbed_official	324:406fd2029f23	846
mbed_official	324:406fd2029f23	847	/! @brief Set the M3UM field to a new value. /
mbed_official	324:406fd2029f23	848	#define BW_MPU_RGDn_WORD2_M3UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3UM) \| BF_MPU_RGDn_WORD2_M3UM(v)))
mbed_official	324:406fd2029f23	849	/@}/
mbed_official	324:406fd2029f23	850
mbed_official	324:406fd2029f23	851	/*!
mbed_official	324:406fd2029f23	852	* @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
mbed_official	324:406fd2029f23	853	*
mbed_official	324:406fd2029f23	854	* Defines the access controls for bus master 3 in Supervisor mode.
mbed_official	324:406fd2029f23	855	*
mbed_official	324:406fd2029f23	856	* Values:
mbed_official	324:406fd2029f23	857	* - 00 - r/w/x; read, write and execute allowed
mbed_official	324:406fd2029f23	858	* - 01 - r/x; read and execute allowed, but no write
mbed_official	324:406fd2029f23	859	* - 10 - r/w; read and write allowed, but no execute
mbed_official	324:406fd2029f23	860	* - 11 - Same as User mode defined in M3UM
mbed_official	324:406fd2029f23	861	*/
mbed_official	324:406fd2029f23	862	/@{/
mbed_official	324:406fd2029f23	863	#define BP_MPU_RGDn_WORD2_M3SM (21U) /!< Bit position for MPU_RGDn_WORD2_M3SM. /
mbed_official	324:406fd2029f23	864	#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) /!< Bit mask for MPU_RGDn_WORD2_M3SM. /
mbed_official	324:406fd2029f23	865	#define BS_MPU_RGDn_WORD2_M3SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3SM. /
mbed_official	324:406fd2029f23	866
mbed_official	324:406fd2029f23	867	/! @brief Read current value of the MPU_RGDn_WORD2_M3SM field. /
mbed_official	324:406fd2029f23	868	#define BR_MPU_RGDn_WORD2_M3SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3SM)
mbed_official	324:406fd2029f23	869
mbed_official	324:406fd2029f23	870	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM. /
mbed_official	324:406fd2029f23	871	#define BF_MPU_RGDn_WORD2_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3SM) & BM_MPU_RGDn_WORD2_M3SM)
mbed_official	324:406fd2029f23	872
mbed_official	324:406fd2029f23	873	/! @brief Set the M3SM field to a new value. /
mbed_official	324:406fd2029f23	874	#define BW_MPU_RGDn_WORD2_M3SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3SM) \| BF_MPU_RGDn_WORD2_M3SM(v)))
mbed_official	324:406fd2029f23	875	/@}/
mbed_official	324:406fd2029f23	876
mbed_official	324:406fd2029f23	877	/*!
mbed_official	324:406fd2029f23	878	* @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
mbed_official	324:406fd2029f23	879	*
mbed_official	324:406fd2029f23	880	* Values:
mbed_official	324:406fd2029f23	881	* - 0 - Do not include the process identifier in the evaluation
mbed_official	324:406fd2029f23	882	* - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
mbed_official	324:406fd2029f23	883	* evaluation
mbed_official	324:406fd2029f23	884	*/
mbed_official	324:406fd2029f23	885	/@{/
mbed_official	324:406fd2029f23	886	#define BP_MPU_RGDn_WORD2_M3PE (23U) /!< Bit position for MPU_RGDn_WORD2_M3PE. /
mbed_official	324:406fd2029f23	887	#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) /!< Bit mask for MPU_RGDn_WORD2_M3PE. /
mbed_official	324:406fd2029f23	888	#define BS_MPU_RGDn_WORD2_M3PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3PE. /
mbed_official	324:406fd2029f23	889
mbed_official	324:406fd2029f23	890	/! @brief Read current value of the MPU_RGDn_WORD2_M3PE field. /
mbed_official	324:406fd2029f23	891	#define BR_MPU_RGDn_WORD2_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE))
mbed_official	324:406fd2029f23	892
mbed_official	324:406fd2029f23	893	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE. /
mbed_official	324:406fd2029f23	894	#define BF_MPU_RGDn_WORD2_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3PE) & BM_MPU_RGDn_WORD2_M3PE)
mbed_official	324:406fd2029f23	895
mbed_official	324:406fd2029f23	896	/! @brief Set the M3PE field to a new value. /
mbed_official	324:406fd2029f23	897	#define BW_MPU_RGDn_WORD2_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE) = (v))
mbed_official	324:406fd2029f23	898	/@}/
mbed_official	324:406fd2029f23	899
mbed_official	324:406fd2029f23	900	/*!
mbed_official	324:406fd2029f23	901	* @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
mbed_official	324:406fd2029f23	902	*
mbed_official	324:406fd2029f23	903	* Values:
mbed_official	324:406fd2029f23	904	* - 0 - Bus master 4 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	905	* performed
mbed_official	324:406fd2029f23	906	* - 1 - Bus master 4 writes allowed
mbed_official	324:406fd2029f23	907	*/
mbed_official	324:406fd2029f23	908	/@{/
mbed_official	324:406fd2029f23	909	#define BP_MPU_RGDn_WORD2_M4WE (24U) /!< Bit position for MPU_RGDn_WORD2_M4WE. /
mbed_official	324:406fd2029f23	910	#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) /!< Bit mask for MPU_RGDn_WORD2_M4WE. /
mbed_official	324:406fd2029f23	911	#define BS_MPU_RGDn_WORD2_M4WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M4WE. /
mbed_official	324:406fd2029f23	912
mbed_official	324:406fd2029f23	913	/! @brief Read current value of the MPU_RGDn_WORD2_M4WE field. /
mbed_official	324:406fd2029f23	914	#define BR_MPU_RGDn_WORD2_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE))
mbed_official	324:406fd2029f23	915
mbed_official	324:406fd2029f23	916	/! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE. /
mbed_official	324:406fd2029f23	917	#define BF_MPU_RGDn_WORD2_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4WE) & BM_MPU_RGDn_WORD2_M4WE)
mbed_official	324:406fd2029f23	918
mbed_official	324:406fd2029f23	919	/! @brief Set the M4WE field to a new value. /
mbed_official	324:406fd2029f23	920	#define BW_MPU_RGDn_WORD2_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE) = (v))
mbed_official	324:406fd2029f23	921	/@}/
mbed_official	324:406fd2029f23	922
mbed_official	324:406fd2029f23	923	/*!
mbed_official	324:406fd2029f23	924	* @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
mbed_official	324:406fd2029f23	925	*
mbed_official	324:406fd2029f23	926	* Values:
mbed_official	324:406fd2029f23	927	* - 0 - Bus master 4 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	928	* performed
mbed_official	324:406fd2029f23	929	* - 1 - Bus master 4 reads allowed
mbed_official	324:406fd2029f23	930	*/
mbed_official	324:406fd2029f23	931	/@{/
mbed_official	324:406fd2029f23	932	#define BP_MPU_RGDn_WORD2_M4RE (25U) /!< Bit position for MPU_RGDn_WORD2_M4RE. /
mbed_official	324:406fd2029f23	933	#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) /!< Bit mask for MPU_RGDn_WORD2_M4RE. /
mbed_official	324:406fd2029f23	934	#define BS_MPU_RGDn_WORD2_M4RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M4RE. /
mbed_official	324:406fd2029f23	935
mbed_official	324:406fd2029f23	936	/! @brief Read current value of the MPU_RGDn_WORD2_M4RE field. /
mbed_official	324:406fd2029f23	937	#define BR_MPU_RGDn_WORD2_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE))
mbed_official	324:406fd2029f23	938
mbed_official	324:406fd2029f23	939	/! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE. /
mbed_official	324:406fd2029f23	940	#define BF_MPU_RGDn_WORD2_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4RE) & BM_MPU_RGDn_WORD2_M4RE)
mbed_official	324:406fd2029f23	941
mbed_official	324:406fd2029f23	942	/! @brief Set the M4RE field to a new value. /
mbed_official	324:406fd2029f23	943	#define BW_MPU_RGDn_WORD2_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE) = (v))
mbed_official	324:406fd2029f23	944	/@}/
mbed_official	324:406fd2029f23	945
mbed_official	324:406fd2029f23	946	/*!
mbed_official	324:406fd2029f23	947	* @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
mbed_official	324:406fd2029f23	948	*
mbed_official	324:406fd2029f23	949	* Values:
mbed_official	324:406fd2029f23	950	* - 0 - Bus master 5 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	951	* performed
mbed_official	324:406fd2029f23	952	* - 1 - Bus master 5 writes allowed
mbed_official	324:406fd2029f23	953	*/
mbed_official	324:406fd2029f23	954	/@{/
mbed_official	324:406fd2029f23	955	#define BP_MPU_RGDn_WORD2_M5WE (26U) /!< Bit position for MPU_RGDn_WORD2_M5WE. /
mbed_official	324:406fd2029f23	956	#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) /!< Bit mask for MPU_RGDn_WORD2_M5WE. /
mbed_official	324:406fd2029f23	957	#define BS_MPU_RGDn_WORD2_M5WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M5WE. /
mbed_official	324:406fd2029f23	958
mbed_official	324:406fd2029f23	959	/! @brief Read current value of the MPU_RGDn_WORD2_M5WE field. /
mbed_official	324:406fd2029f23	960	#define BR_MPU_RGDn_WORD2_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE))
mbed_official	324:406fd2029f23	961
mbed_official	324:406fd2029f23	962	/! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE. /
mbed_official	324:406fd2029f23	963	#define BF_MPU_RGDn_WORD2_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5WE) & BM_MPU_RGDn_WORD2_M5WE)
mbed_official	324:406fd2029f23	964
mbed_official	324:406fd2029f23	965	/! @brief Set the M5WE field to a new value. /
mbed_official	324:406fd2029f23	966	#define BW_MPU_RGDn_WORD2_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE) = (v))
mbed_official	324:406fd2029f23	967	/@}/
mbed_official	324:406fd2029f23	968
mbed_official	324:406fd2029f23	969	/*!
mbed_official	324:406fd2029f23	970	* @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
mbed_official	324:406fd2029f23	971	*
mbed_official	324:406fd2029f23	972	* Values:
mbed_official	324:406fd2029f23	973	* - 0 - Bus master 5 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	974	* performed
mbed_official	324:406fd2029f23	975	* - 1 - Bus master 5 reads allowed
mbed_official	324:406fd2029f23	976	*/
mbed_official	324:406fd2029f23	977	/@{/
mbed_official	324:406fd2029f23	978	#define BP_MPU_RGDn_WORD2_M5RE (27U) /!< Bit position for MPU_RGDn_WORD2_M5RE. /
mbed_official	324:406fd2029f23	979	#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) /!< Bit mask for MPU_RGDn_WORD2_M5RE. /
mbed_official	324:406fd2029f23	980	#define BS_MPU_RGDn_WORD2_M5RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M5RE. /
mbed_official	324:406fd2029f23	981
mbed_official	324:406fd2029f23	982	/! @brief Read current value of the MPU_RGDn_WORD2_M5RE field. /
mbed_official	324:406fd2029f23	983	#define BR_MPU_RGDn_WORD2_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE))
mbed_official	324:406fd2029f23	984
mbed_official	324:406fd2029f23	985	/! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE. /
mbed_official	324:406fd2029f23	986	#define BF_MPU_RGDn_WORD2_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5RE) & BM_MPU_RGDn_WORD2_M5RE)
mbed_official	324:406fd2029f23	987
mbed_official	324:406fd2029f23	988	/! @brief Set the M5RE field to a new value. /
mbed_official	324:406fd2029f23	989	#define BW_MPU_RGDn_WORD2_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE) = (v))
mbed_official	324:406fd2029f23	990	/@}/
mbed_official	324:406fd2029f23	991
mbed_official	324:406fd2029f23	992	/*!
mbed_official	324:406fd2029f23	993	* @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
mbed_official	324:406fd2029f23	994	*
mbed_official	324:406fd2029f23	995	* Values:
mbed_official	324:406fd2029f23	996	* - 0 - Bus master 6 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	997	* performed
mbed_official	324:406fd2029f23	998	* - 1 - Bus master 6 writes allowed
mbed_official	324:406fd2029f23	999	*/
mbed_official	324:406fd2029f23	1000	/@{/
mbed_official	324:406fd2029f23	1001	#define BP_MPU_RGDn_WORD2_M6WE (28U) /!< Bit position for MPU_RGDn_WORD2_M6WE. /
mbed_official	324:406fd2029f23	1002	#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) /!< Bit mask for MPU_RGDn_WORD2_M6WE. /
mbed_official	324:406fd2029f23	1003	#define BS_MPU_RGDn_WORD2_M6WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M6WE. /
mbed_official	324:406fd2029f23	1004
mbed_official	324:406fd2029f23	1005	/! @brief Read current value of the MPU_RGDn_WORD2_M6WE field. /
mbed_official	324:406fd2029f23	1006	#define BR_MPU_RGDn_WORD2_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE))
mbed_official	324:406fd2029f23	1007
mbed_official	324:406fd2029f23	1008	/! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE. /
mbed_official	324:406fd2029f23	1009	#define BF_MPU_RGDn_WORD2_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6WE) & BM_MPU_RGDn_WORD2_M6WE)
mbed_official	324:406fd2029f23	1010
mbed_official	324:406fd2029f23	1011	/! @brief Set the M6WE field to a new value. /
mbed_official	324:406fd2029f23	1012	#define BW_MPU_RGDn_WORD2_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE) = (v))
mbed_official	324:406fd2029f23	1013	/@}/
mbed_official	324:406fd2029f23	1014
mbed_official	324:406fd2029f23	1015	/*!
mbed_official	324:406fd2029f23	1016	* @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
mbed_official	324:406fd2029f23	1017	*
mbed_official	324:406fd2029f23	1018	* Values:
mbed_official	324:406fd2029f23	1019	* - 0 - Bus master 6 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1020	* performed
mbed_official	324:406fd2029f23	1021	* - 1 - Bus master 6 reads allowed
mbed_official	324:406fd2029f23	1022	*/
mbed_official	324:406fd2029f23	1023	/@{/
mbed_official	324:406fd2029f23	1024	#define BP_MPU_RGDn_WORD2_M6RE (29U) /!< Bit position for MPU_RGDn_WORD2_M6RE. /
mbed_official	324:406fd2029f23	1025	#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) /!< Bit mask for MPU_RGDn_WORD2_M6RE. /
mbed_official	324:406fd2029f23	1026	#define BS_MPU_RGDn_WORD2_M6RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M6RE. /
mbed_official	324:406fd2029f23	1027
mbed_official	324:406fd2029f23	1028	/! @brief Read current value of the MPU_RGDn_WORD2_M6RE field. /
mbed_official	324:406fd2029f23	1029	#define BR_MPU_RGDn_WORD2_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE))
mbed_official	324:406fd2029f23	1030
mbed_official	324:406fd2029f23	1031	/! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE. /
mbed_official	324:406fd2029f23	1032	#define BF_MPU_RGDn_WORD2_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6RE) & BM_MPU_RGDn_WORD2_M6RE)
mbed_official	324:406fd2029f23	1033
mbed_official	324:406fd2029f23	1034	/! @brief Set the M6RE field to a new value. /
mbed_official	324:406fd2029f23	1035	#define BW_MPU_RGDn_WORD2_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE) = (v))
mbed_official	324:406fd2029f23	1036	/@}/
mbed_official	324:406fd2029f23	1037
mbed_official	324:406fd2029f23	1038	/*!
mbed_official	324:406fd2029f23	1039	* @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
mbed_official	324:406fd2029f23	1040	*
mbed_official	324:406fd2029f23	1041	* Values:
mbed_official	324:406fd2029f23	1042	* - 0 - Bus master 7 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	1043	* performed
mbed_official	324:406fd2029f23	1044	* - 1 - Bus master 7 writes allowed
mbed_official	324:406fd2029f23	1045	*/
mbed_official	324:406fd2029f23	1046	/@{/
mbed_official	324:406fd2029f23	1047	#define BP_MPU_RGDn_WORD2_M7WE (30U) /!< Bit position for MPU_RGDn_WORD2_M7WE. /
mbed_official	324:406fd2029f23	1048	#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) /!< Bit mask for MPU_RGDn_WORD2_M7WE. /
mbed_official	324:406fd2029f23	1049	#define BS_MPU_RGDn_WORD2_M7WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M7WE. /
mbed_official	324:406fd2029f23	1050
mbed_official	324:406fd2029f23	1051	/! @brief Read current value of the MPU_RGDn_WORD2_M7WE field. /
mbed_official	324:406fd2029f23	1052	#define BR_MPU_RGDn_WORD2_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE))
mbed_official	324:406fd2029f23	1053
mbed_official	324:406fd2029f23	1054	/! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE. /
mbed_official	324:406fd2029f23	1055	#define BF_MPU_RGDn_WORD2_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7WE) & BM_MPU_RGDn_WORD2_M7WE)
mbed_official	324:406fd2029f23	1056
mbed_official	324:406fd2029f23	1057	/! @brief Set the M7WE field to a new value. /
mbed_official	324:406fd2029f23	1058	#define BW_MPU_RGDn_WORD2_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE) = (v))
mbed_official	324:406fd2029f23	1059	/@}/
mbed_official	324:406fd2029f23	1060
mbed_official	324:406fd2029f23	1061	/*!
mbed_official	324:406fd2029f23	1062	* @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
mbed_official	324:406fd2029f23	1063	*
mbed_official	324:406fd2029f23	1064	* Values:
mbed_official	324:406fd2029f23	1065	* - 0 - Bus master 7 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1066	* performed
mbed_official	324:406fd2029f23	1067	* - 1 - Bus master 7 reads allowed
mbed_official	324:406fd2029f23	1068	*/
mbed_official	324:406fd2029f23	1069	/@{/
mbed_official	324:406fd2029f23	1070	#define BP_MPU_RGDn_WORD2_M7RE (31U) /!< Bit position for MPU_RGDn_WORD2_M7RE. /
mbed_official	324:406fd2029f23	1071	#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) /!< Bit mask for MPU_RGDn_WORD2_M7RE. /
mbed_official	324:406fd2029f23	1072	#define BS_MPU_RGDn_WORD2_M7RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M7RE. /
mbed_official	324:406fd2029f23	1073
mbed_official	324:406fd2029f23	1074	/! @brief Read current value of the MPU_RGDn_WORD2_M7RE field. /
mbed_official	324:406fd2029f23	1075	#define BR_MPU_RGDn_WORD2_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE))
mbed_official	324:406fd2029f23	1076
mbed_official	324:406fd2029f23	1077	/! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE. /
mbed_official	324:406fd2029f23	1078	#define BF_MPU_RGDn_WORD2_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7RE) & BM_MPU_RGDn_WORD2_M7RE)
mbed_official	324:406fd2029f23	1079
mbed_official	324:406fd2029f23	1080	/! @brief Set the M7RE field to a new value. /
mbed_official	324:406fd2029f23	1081	#define BW_MPU_RGDn_WORD2_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE) = (v))
mbed_official	324:406fd2029f23	1082	/@}/
mbed_official	324:406fd2029f23	1083	/*******************************************************************************
mbed_official	324:406fd2029f23	1084	* HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
mbed_official	324:406fd2029f23	1085	******************************************************************************/
mbed_official	324:406fd2029f23	1086
mbed_official	324:406fd2029f23	1087	/*!
mbed_official	324:406fd2029f23	1088	* @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
mbed_official	324:406fd2029f23	1089	*
mbed_official	324:406fd2029f23	1090	* Reset value: 0x00000001U
mbed_official	324:406fd2029f23	1091	*
mbed_official	324:406fd2029f23	1092	* The fourth word of the region descriptor contains the optional process
mbed_official	324:406fd2029f23	1093	* identifier and mask, plus the region descriptor's valid bit.
mbed_official	324:406fd2029f23	1094	*/
mbed_official	324:406fd2029f23	1095	typedef union _hw_mpu_rgdn_word3
mbed_official	324:406fd2029f23	1096	{
mbed_official	324:406fd2029f23	1097	uint32_t U;
mbed_official	324:406fd2029f23	1098	struct _hw_mpu_rgdn_word3_bitfields
mbed_official	324:406fd2029f23	1099	{
mbed_official	324:406fd2029f23	1100	uint32_t VLD : 1; /!< [0] Valid /
mbed_official	324:406fd2029f23	1101	uint32_t RESERVED0 : 15; /!< [15:1] /
mbed_official	324:406fd2029f23	1102	uint32_t PIDMASK : 8; /!< [23:16] Process Identifier Mask /
mbed_official	324:406fd2029f23	1103	uint32_t PID : 8; /!< [31:24] Process Identifier /
mbed_official	324:406fd2029f23	1104	} B;
mbed_official	324:406fd2029f23	1105	} hw_mpu_rgdn_word3_t;
mbed_official	324:406fd2029f23	1106
mbed_official	324:406fd2029f23	1107	/*!
mbed_official	324:406fd2029f23	1108	* @name Constants and macros for entire MPU_RGDn_WORD3 register
mbed_official	324:406fd2029f23	1109	*/
mbed_official	324:406fd2029f23	1110	/@{/
mbed_official	324:406fd2029f23	1111	#define HW_MPU_RGDn_WORD3_COUNT (12U)
mbed_official	324:406fd2029f23	1112
mbed_official	324:406fd2029f23	1113	#define HW_MPU_RGDn_WORD3_ADDR(x, n) ((x) + 0x40CU + (0x10U * (n)))
mbed_official	324:406fd2029f23	1114
mbed_official	324:406fd2029f23	1115	#define HW_MPU_RGDn_WORD3(x, n) ((__IO hw_mpu_rgdn_word3_t ) HW_MPU_RGDn_WORD3_ADDR(x, n))
mbed_official	324:406fd2029f23	1116	#define HW_MPU_RGDn_WORD3_RD(x, n) (HW_MPU_RGDn_WORD3(x, n).U)
mbed_official	324:406fd2029f23	1117	#define HW_MPU_RGDn_WORD3_WR(x, n, v) (HW_MPU_RGDn_WORD3(x, n).U = (v))
mbed_official	324:406fd2029f23	1118	#define HW_MPU_RGDn_WORD3_SET(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	1119	#define HW_MPU_RGDn_WORD3_CLR(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	1120	#define HW_MPU_RGDn_WORD3_TOG(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	1121	/@}/
mbed_official	324:406fd2029f23	1122
mbed_official	324:406fd2029f23	1123	/*
mbed_official	324:406fd2029f23	1124	* Constants & macros for individual MPU_RGDn_WORD3 bitfields
mbed_official	324:406fd2029f23	1125	*/
mbed_official	324:406fd2029f23	1126
mbed_official	324:406fd2029f23	1127	/*!
mbed_official	324:406fd2029f23	1128	* @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
mbed_official	324:406fd2029f23	1129	*
mbed_official	324:406fd2029f23	1130	* Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
mbed_official	324:406fd2029f23	1131	* bit.
mbed_official	324:406fd2029f23	1132	*
mbed_official	324:406fd2029f23	1133	* Values:
mbed_official	324:406fd2029f23	1134	* - 0 - Region descriptor is invalid
mbed_official	324:406fd2029f23	1135	* - 1 - Region descriptor is valid
mbed_official	324:406fd2029f23	1136	*/
mbed_official	324:406fd2029f23	1137	/@{/
mbed_official	324:406fd2029f23	1138	#define BP_MPU_RGDn_WORD3_VLD (0U) /!< Bit position for MPU_RGDn_WORD3_VLD. /
mbed_official	324:406fd2029f23	1139	#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) /!< Bit mask for MPU_RGDn_WORD3_VLD. /
mbed_official	324:406fd2029f23	1140	#define BS_MPU_RGDn_WORD3_VLD (1U) /!< Bit field size in bits for MPU_RGDn_WORD3_VLD. /
mbed_official	324:406fd2029f23	1141
mbed_official	324:406fd2029f23	1142	/! @brief Read current value of the MPU_RGDn_WORD3_VLD field. /
mbed_official	324:406fd2029f23	1143	#define BR_MPU_RGDn_WORD3_VLD(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD))
mbed_official	324:406fd2029f23	1144
mbed_official	324:406fd2029f23	1145	/! @brief Format value for bitfield MPU_RGDn_WORD3_VLD. /
mbed_official	324:406fd2029f23	1146	#define BF_MPU_RGDn_WORD3_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_VLD) & BM_MPU_RGDn_WORD3_VLD)
mbed_official	324:406fd2029f23	1147
mbed_official	324:406fd2029f23	1148	/! @brief Set the VLD field to a new value. /
mbed_official	324:406fd2029f23	1149	#define BW_MPU_RGDn_WORD3_VLD(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD) = (v))
mbed_official	324:406fd2029f23	1150	/@}/
mbed_official	324:406fd2029f23	1151
mbed_official	324:406fd2029f23	1152	/*!
mbed_official	324:406fd2029f23	1153	* @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
mbed_official	324:406fd2029f23	1154	*
mbed_official	324:406fd2029f23	1155	* Provides a masking capability so that multiple process identifiers can be
mbed_official	324:406fd2029f23	1156	* included as part of the region hit determination. If a bit in PIDMASK is set,
mbed_official	324:406fd2029f23	1157	* then the corresponding PID bit is ignored in the comparison. This field and PID
mbed_official	324:406fd2029f23	1158	* are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
mbed_official	324:406fd2029f23	1159	* more information on the handling of the PID and PIDMASK, see "Access Evaluation
mbed_official	324:406fd2029f23	1160	* - Hit Determination."
mbed_official	324:406fd2029f23	1161	*/
mbed_official	324:406fd2029f23	1162	/@{/
mbed_official	324:406fd2029f23	1163	#define BP_MPU_RGDn_WORD3_PIDMASK (16U) /!< Bit position for MPU_RGDn_WORD3_PIDMASK. /
mbed_official	324:406fd2029f23	1164	#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) /!< Bit mask for MPU_RGDn_WORD3_PIDMASK. /
mbed_official	324:406fd2029f23	1165	#define BS_MPU_RGDn_WORD3_PIDMASK (8U) /!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK. /
mbed_official	324:406fd2029f23	1166
mbed_official	324:406fd2029f23	1167	/! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field. /
mbed_official	324:406fd2029f23	1168	#define BR_MPU_RGDn_WORD3_PIDMASK(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PIDMASK)
mbed_official	324:406fd2029f23	1169
mbed_official	324:406fd2029f23	1170	/! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK. /
mbed_official	324:406fd2029f23	1171	#define BF_MPU_RGDn_WORD3_PIDMASK(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PIDMASK) & BM_MPU_RGDn_WORD3_PIDMASK)
mbed_official	324:406fd2029f23	1172
mbed_official	324:406fd2029f23	1173	/! @brief Set the PIDMASK field to a new value. /
mbed_official	324:406fd2029f23	1174	#define BW_MPU_RGDn_WORD3_PIDMASK(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PIDMASK) \| BF_MPU_RGDn_WORD3_PIDMASK(v)))
mbed_official	324:406fd2029f23	1175	/@}/
mbed_official	324:406fd2029f23	1176
mbed_official	324:406fd2029f23	1177	/*!
mbed_official	324:406fd2029f23	1178	* @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
mbed_official	324:406fd2029f23	1179	*
mbed_official	324:406fd2029f23	1180	* Specifies the process identifier that is included in the region hit
mbed_official	324:406fd2029f23	1181	* determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
mbed_official	324:406fd2029f23	1182	* field.
mbed_official	324:406fd2029f23	1183	*/
mbed_official	324:406fd2029f23	1184	/@{/
mbed_official	324:406fd2029f23	1185	#define BP_MPU_RGDn_WORD3_PID (24U) /!< Bit position for MPU_RGDn_WORD3_PID. /
mbed_official	324:406fd2029f23	1186	#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) /!< Bit mask for MPU_RGDn_WORD3_PID. /
mbed_official	324:406fd2029f23	1187	#define BS_MPU_RGDn_WORD3_PID (8U) /!< Bit field size in bits for MPU_RGDn_WORD3_PID. /
mbed_official	324:406fd2029f23	1188
mbed_official	324:406fd2029f23	1189	/! @brief Read current value of the MPU_RGDn_WORD3_PID field. /
mbed_official	324:406fd2029f23	1190	#define BR_MPU_RGDn_WORD3_PID(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PID)
mbed_official	324:406fd2029f23	1191
mbed_official	324:406fd2029f23	1192	/! @brief Format value for bitfield MPU_RGDn_WORD3_PID. /
mbed_official	324:406fd2029f23	1193	#define BF_MPU_RGDn_WORD3_PID(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PID) & BM_MPU_RGDn_WORD3_PID)
mbed_official	324:406fd2029f23	1194
mbed_official	324:406fd2029f23	1195	/! @brief Set the PID field to a new value. /
mbed_official	324:406fd2029f23	1196	#define BW_MPU_RGDn_WORD3_PID(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PID) \| BF_MPU_RGDn_WORD3_PID(v)))
mbed_official	324:406fd2029f23	1197	/@}/
mbed_official	324:406fd2029f23	1198
mbed_official	324:406fd2029f23	1199	/*******************************************************************************
mbed_official	324:406fd2029f23	1200	* HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
mbed_official	324:406fd2029f23	1201	******************************************************************************/
mbed_official	324:406fd2029f23	1202
mbed_official	324:406fd2029f23	1203	/*!
mbed_official	324:406fd2029f23	1204	* @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
mbed_official	324:406fd2029f23	1205	*
mbed_official	324:406fd2029f23	1206	* Reset value: 0x0061F7DFU
mbed_official	324:406fd2029f23	1207	*
mbed_official	324:406fd2029f23	1208	* Because software may adjust only the access controls within a region
mbed_official	324:406fd2029f23	1209	* descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
mbed_official	324:406fd2029f23	1210	* this 32-bit entity is available. Writing to this register does not affect the
mbed_official	324:406fd2029f23	1211	* descriptor's valid bit.
mbed_official	324:406fd2029f23	1212	*/
mbed_official	324:406fd2029f23	1213	typedef union _hw_mpu_rgdaacn
mbed_official	324:406fd2029f23	1214	{
mbed_official	324:406fd2029f23	1215	uint32_t U;
mbed_official	324:406fd2029f23	1216	struct _hw_mpu_rgdaacn_bitfields
mbed_official	324:406fd2029f23	1217	{
mbed_official	324:406fd2029f23	1218	uint32_t M0UM : 3; /!< [2:0] Bus Master 0 User Mode Access Control /
mbed_official	324:406fd2029f23	1219	uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access
mbed_official	324:406fd2029f23	1220	* Control */
mbed_official	324:406fd2029f23	1221	uint32_t M0PE : 1; /!< [5] Bus Master 0 Process Identifier Enable /
mbed_official	324:406fd2029f23	1222	uint32_t M1UM : 3; /!< [8:6] Bus Master 1 User Mode Access Control /
mbed_official	324:406fd2029f23	1223	uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access
mbed_official	324:406fd2029f23	1224	* Control */
mbed_official	324:406fd2029f23	1225	uint32_t M1PE : 1; /!< [11] Bus Master 1 Process Identifier Enable /
mbed_official	324:406fd2029f23	1226	uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access Control
mbed_official	324:406fd2029f23	1227	* */
mbed_official	324:406fd2029f23	1228	uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access
mbed_official	324:406fd2029f23	1229	* Control */
mbed_official	324:406fd2029f23	1230	uint32_t M2PE : 1; /!< [17] Bus Master 2 Process Identifier Enable /
mbed_official	324:406fd2029f23	1231	uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control
mbed_official	324:406fd2029f23	1232	* */
mbed_official	324:406fd2029f23	1233	uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access
mbed_official	324:406fd2029f23	1234	* Control */
mbed_official	324:406fd2029f23	1235	uint32_t M3PE : 1; /!< [23] Bus Master 3 Process Identifier Enable /
mbed_official	324:406fd2029f23	1236	uint32_t M4WE : 1; /!< [24] Bus Master 4 Write Enable /
mbed_official	324:406fd2029f23	1237	uint32_t M4RE : 1; /!< [25] Bus Master 4 Read Enable /
mbed_official	324:406fd2029f23	1238	uint32_t M5WE : 1; /!< [26] Bus Master 5 Write Enable /
mbed_official	324:406fd2029f23	1239	uint32_t M5RE : 1; /!< [27] Bus Master 5 Read Enable /
mbed_official	324:406fd2029f23	1240	uint32_t M6WE : 1; /!< [28] Bus Master 6 Write Enable /
mbed_official	324:406fd2029f23	1241	uint32_t M6RE : 1; /!< [29] Bus Master 6 Read Enable /
mbed_official	324:406fd2029f23	1242	uint32_t M7WE : 1; /!< [30] Bus Master 7 Write Enable /
mbed_official	324:406fd2029f23	1243	uint32_t M7RE : 1; /!< [31] Bus Master 7 Read Enable /
mbed_official	324:406fd2029f23	1244	} B;
mbed_official	324:406fd2029f23	1245	} hw_mpu_rgdaacn_t;
mbed_official	324:406fd2029f23	1246
mbed_official	324:406fd2029f23	1247	/*!
mbed_official	324:406fd2029f23	1248	* @name Constants and macros for entire MPU_RGDAACn register
mbed_official	324:406fd2029f23	1249	*/
mbed_official	324:406fd2029f23	1250	/@{/
mbed_official	324:406fd2029f23	1251	#define HW_MPU_RGDAACn_COUNT (12U)
mbed_official	324:406fd2029f23	1252
mbed_official	324:406fd2029f23	1253	#define HW_MPU_RGDAACn_ADDR(x, n) ((x) + 0x800U + (0x4U * (n)))
mbed_official	324:406fd2029f23	1254
mbed_official	324:406fd2029f23	1255	#define HW_MPU_RGDAACn(x, n) ((__IO hw_mpu_rgdaacn_t ) HW_MPU_RGDAACn_ADDR(x, n))
mbed_official	324:406fd2029f23	1256	#define HW_MPU_RGDAACn_RD(x, n) (HW_MPU_RGDAACn(x, n).U)
mbed_official	324:406fd2029f23	1257	#define HW_MPU_RGDAACn_WR(x, n, v) (HW_MPU_RGDAACn(x, n).U = (v))
mbed_official	324:406fd2029f23	1258	#define HW_MPU_RGDAACn_SET(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	1259	#define HW_MPU_RGDAACn_CLR(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	1260	#define HW_MPU_RGDAACn_TOG(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	1261	/@}/
mbed_official	324:406fd2029f23	1262
mbed_official	324:406fd2029f23	1263	/*
mbed_official	324:406fd2029f23	1264	* Constants & macros for individual MPU_RGDAACn bitfields
mbed_official	324:406fd2029f23	1265	*/
mbed_official	324:406fd2029f23	1266
mbed_official	324:406fd2029f23	1267	/*!
mbed_official	324:406fd2029f23	1268	* @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
mbed_official	324:406fd2029f23	1269	*
mbed_official	324:406fd2029f23	1270	* See M3UM description.
mbed_official	324:406fd2029f23	1271	*/
mbed_official	324:406fd2029f23	1272	/@{/
mbed_official	324:406fd2029f23	1273	#define BP_MPU_RGDAACn_M0UM (0U) /!< Bit position for MPU_RGDAACn_M0UM. /
mbed_official	324:406fd2029f23	1274	#define BM_MPU_RGDAACn_M0UM (0x00000007U) /!< Bit mask for MPU_RGDAACn_M0UM. /
mbed_official	324:406fd2029f23	1275	#define BS_MPU_RGDAACn_M0UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M0UM. /
mbed_official	324:406fd2029f23	1276
mbed_official	324:406fd2029f23	1277	/! @brief Read current value of the MPU_RGDAACn_M0UM field. /
mbed_official	324:406fd2029f23	1278	#define BR_MPU_RGDAACn_M0UM(x, n) (HW_MPU_RGDAACn(x, n).B.M0UM)
mbed_official	324:406fd2029f23	1279
mbed_official	324:406fd2029f23	1280	/! @brief Format value for bitfield MPU_RGDAACn_M0UM. /
mbed_official	324:406fd2029f23	1281	#define BF_MPU_RGDAACn_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0UM) & BM_MPU_RGDAACn_M0UM)
mbed_official	324:406fd2029f23	1282
mbed_official	324:406fd2029f23	1283	/! @brief Set the M0UM field to a new value. /
mbed_official	324:406fd2029f23	1284	#define BW_MPU_RGDAACn_M0UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0UM) \| BF_MPU_RGDAACn_M0UM(v)))
mbed_official	324:406fd2029f23	1285	/@}/
mbed_official	324:406fd2029f23	1286
mbed_official	324:406fd2029f23	1287	/*!
mbed_official	324:406fd2029f23	1288	* @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
mbed_official	324:406fd2029f23	1289	*
mbed_official	324:406fd2029f23	1290	* See M3SM description.
mbed_official	324:406fd2029f23	1291	*/
mbed_official	324:406fd2029f23	1292	/@{/
mbed_official	324:406fd2029f23	1293	#define BP_MPU_RGDAACn_M0SM (3U) /!< Bit position for MPU_RGDAACn_M0SM. /
mbed_official	324:406fd2029f23	1294	#define BM_MPU_RGDAACn_M0SM (0x00000018U) /!< Bit mask for MPU_RGDAACn_M0SM. /
mbed_official	324:406fd2029f23	1295	#define BS_MPU_RGDAACn_M0SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M0SM. /
mbed_official	324:406fd2029f23	1296
mbed_official	324:406fd2029f23	1297	/! @brief Read current value of the MPU_RGDAACn_M0SM field. /
mbed_official	324:406fd2029f23	1298	#define BR_MPU_RGDAACn_M0SM(x, n) (HW_MPU_RGDAACn(x, n).B.M0SM)
mbed_official	324:406fd2029f23	1299
mbed_official	324:406fd2029f23	1300	/! @brief Format value for bitfield MPU_RGDAACn_M0SM. /
mbed_official	324:406fd2029f23	1301	#define BF_MPU_RGDAACn_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0SM) & BM_MPU_RGDAACn_M0SM)
mbed_official	324:406fd2029f23	1302
mbed_official	324:406fd2029f23	1303	/! @brief Set the M0SM field to a new value. /
mbed_official	324:406fd2029f23	1304	#define BW_MPU_RGDAACn_M0SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0SM) \| BF_MPU_RGDAACn_M0SM(v)))
mbed_official	324:406fd2029f23	1305	/@}/
mbed_official	324:406fd2029f23	1306
mbed_official	324:406fd2029f23	1307	/*!
mbed_official	324:406fd2029f23	1308	* @name Register MPU_RGDAACn, field M0PE[5] (RW)
mbed_official	324:406fd2029f23	1309	*
mbed_official	324:406fd2029f23	1310	* See M3PE description.
mbed_official	324:406fd2029f23	1311	*/
mbed_official	324:406fd2029f23	1312	/@{/
mbed_official	324:406fd2029f23	1313	#define BP_MPU_RGDAACn_M0PE (5U) /!< Bit position for MPU_RGDAACn_M0PE. /
mbed_official	324:406fd2029f23	1314	#define BM_MPU_RGDAACn_M0PE (0x00000020U) /!< Bit mask for MPU_RGDAACn_M0PE. /
mbed_official	324:406fd2029f23	1315	#define BS_MPU_RGDAACn_M0PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M0PE. /
mbed_official	324:406fd2029f23	1316
mbed_official	324:406fd2029f23	1317	/! @brief Read current value of the MPU_RGDAACn_M0PE field. /
mbed_official	324:406fd2029f23	1318	#define BR_MPU_RGDAACn_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE))
mbed_official	324:406fd2029f23	1319
mbed_official	324:406fd2029f23	1320	/! @brief Format value for bitfield MPU_RGDAACn_M0PE. /
mbed_official	324:406fd2029f23	1321	#define BF_MPU_RGDAACn_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0PE) & BM_MPU_RGDAACn_M0PE)
mbed_official	324:406fd2029f23	1322
mbed_official	324:406fd2029f23	1323	/! @brief Set the M0PE field to a new value. /
mbed_official	324:406fd2029f23	1324	#define BW_MPU_RGDAACn_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE) = (v))
mbed_official	324:406fd2029f23	1325	/@}/
mbed_official	324:406fd2029f23	1326
mbed_official	324:406fd2029f23	1327	/*!
mbed_official	324:406fd2029f23	1328	* @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
mbed_official	324:406fd2029f23	1329	*
mbed_official	324:406fd2029f23	1330	* See M3UM description.
mbed_official	324:406fd2029f23	1331	*/
mbed_official	324:406fd2029f23	1332	/@{/
mbed_official	324:406fd2029f23	1333	#define BP_MPU_RGDAACn_M1UM (6U) /!< Bit position for MPU_RGDAACn_M1UM. /
mbed_official	324:406fd2029f23	1334	#define BM_MPU_RGDAACn_M1UM (0x000001C0U) /!< Bit mask for MPU_RGDAACn_M1UM. /
mbed_official	324:406fd2029f23	1335	#define BS_MPU_RGDAACn_M1UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M1UM. /
mbed_official	324:406fd2029f23	1336
mbed_official	324:406fd2029f23	1337	/! @brief Read current value of the MPU_RGDAACn_M1UM field. /
mbed_official	324:406fd2029f23	1338	#define BR_MPU_RGDAACn_M1UM(x, n) (HW_MPU_RGDAACn(x, n).B.M1UM)
mbed_official	324:406fd2029f23	1339
mbed_official	324:406fd2029f23	1340	/! @brief Format value for bitfield MPU_RGDAACn_M1UM. /
mbed_official	324:406fd2029f23	1341	#define BF_MPU_RGDAACn_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1UM) & BM_MPU_RGDAACn_M1UM)
mbed_official	324:406fd2029f23	1342
mbed_official	324:406fd2029f23	1343	/! @brief Set the M1UM field to a new value. /
mbed_official	324:406fd2029f23	1344	#define BW_MPU_RGDAACn_M1UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1UM) \| BF_MPU_RGDAACn_M1UM(v)))
mbed_official	324:406fd2029f23	1345	/@}/
mbed_official	324:406fd2029f23	1346
mbed_official	324:406fd2029f23	1347	/*!
mbed_official	324:406fd2029f23	1348	* @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
mbed_official	324:406fd2029f23	1349	*
mbed_official	324:406fd2029f23	1350	* See M3SM description.
mbed_official	324:406fd2029f23	1351	*/
mbed_official	324:406fd2029f23	1352	/@{/
mbed_official	324:406fd2029f23	1353	#define BP_MPU_RGDAACn_M1SM (9U) /!< Bit position for MPU_RGDAACn_M1SM. /
mbed_official	324:406fd2029f23	1354	#define BM_MPU_RGDAACn_M1SM (0x00000600U) /!< Bit mask for MPU_RGDAACn_M1SM. /
mbed_official	324:406fd2029f23	1355	#define BS_MPU_RGDAACn_M1SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M1SM. /
mbed_official	324:406fd2029f23	1356
mbed_official	324:406fd2029f23	1357	/! @brief Read current value of the MPU_RGDAACn_M1SM field. /
mbed_official	324:406fd2029f23	1358	#define BR_MPU_RGDAACn_M1SM(x, n) (HW_MPU_RGDAACn(x, n).B.M1SM)
mbed_official	324:406fd2029f23	1359
mbed_official	324:406fd2029f23	1360	/! @brief Format value for bitfield MPU_RGDAACn_M1SM. /
mbed_official	324:406fd2029f23	1361	#define BF_MPU_RGDAACn_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1SM) & BM_MPU_RGDAACn_M1SM)
mbed_official	324:406fd2029f23	1362
mbed_official	324:406fd2029f23	1363	/! @brief Set the M1SM field to a new value. /
mbed_official	324:406fd2029f23	1364	#define BW_MPU_RGDAACn_M1SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1SM) \| BF_MPU_RGDAACn_M1SM(v)))
mbed_official	324:406fd2029f23	1365	/@}/
mbed_official	324:406fd2029f23	1366
mbed_official	324:406fd2029f23	1367	/*!
mbed_official	324:406fd2029f23	1368	* @name Register MPU_RGDAACn, field M1PE[11] (RW)
mbed_official	324:406fd2029f23	1369	*
mbed_official	324:406fd2029f23	1370	* See M3PE description.
mbed_official	324:406fd2029f23	1371	*/
mbed_official	324:406fd2029f23	1372	/@{/
mbed_official	324:406fd2029f23	1373	#define BP_MPU_RGDAACn_M1PE (11U) /!< Bit position for MPU_RGDAACn_M1PE. /
mbed_official	324:406fd2029f23	1374	#define BM_MPU_RGDAACn_M1PE (0x00000800U) /!< Bit mask for MPU_RGDAACn_M1PE. /
mbed_official	324:406fd2029f23	1375	#define BS_MPU_RGDAACn_M1PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M1PE. /
mbed_official	324:406fd2029f23	1376
mbed_official	324:406fd2029f23	1377	/! @brief Read current value of the MPU_RGDAACn_M1PE field. /
mbed_official	324:406fd2029f23	1378	#define BR_MPU_RGDAACn_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE))
mbed_official	324:406fd2029f23	1379
mbed_official	324:406fd2029f23	1380	/! @brief Format value for bitfield MPU_RGDAACn_M1PE. /
mbed_official	324:406fd2029f23	1381	#define BF_MPU_RGDAACn_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1PE) & BM_MPU_RGDAACn_M1PE)
mbed_official	324:406fd2029f23	1382
mbed_official	324:406fd2029f23	1383	/! @brief Set the M1PE field to a new value. /
mbed_official	324:406fd2029f23	1384	#define BW_MPU_RGDAACn_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE) = (v))
mbed_official	324:406fd2029f23	1385	/@}/
mbed_official	324:406fd2029f23	1386
mbed_official	324:406fd2029f23	1387	/*!
mbed_official	324:406fd2029f23	1388	* @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
mbed_official	324:406fd2029f23	1389	*
mbed_official	324:406fd2029f23	1390	* See M3UM description.
mbed_official	324:406fd2029f23	1391	*/
mbed_official	324:406fd2029f23	1392	/@{/
mbed_official	324:406fd2029f23	1393	#define BP_MPU_RGDAACn_M2UM (12U) /!< Bit position for MPU_RGDAACn_M2UM. /
mbed_official	324:406fd2029f23	1394	#define BM_MPU_RGDAACn_M2UM (0x00007000U) /!< Bit mask for MPU_RGDAACn_M2UM. /
mbed_official	324:406fd2029f23	1395	#define BS_MPU_RGDAACn_M2UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M2UM. /
mbed_official	324:406fd2029f23	1396
mbed_official	324:406fd2029f23	1397	/! @brief Read current value of the MPU_RGDAACn_M2UM field. /
mbed_official	324:406fd2029f23	1398	#define BR_MPU_RGDAACn_M2UM(x, n) (HW_MPU_RGDAACn(x, n).B.M2UM)
mbed_official	324:406fd2029f23	1399
mbed_official	324:406fd2029f23	1400	/! @brief Format value for bitfield MPU_RGDAACn_M2UM. /
mbed_official	324:406fd2029f23	1401	#define BF_MPU_RGDAACn_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2UM) & BM_MPU_RGDAACn_M2UM)
mbed_official	324:406fd2029f23	1402
mbed_official	324:406fd2029f23	1403	/! @brief Set the M2UM field to a new value. /
mbed_official	324:406fd2029f23	1404	#define BW_MPU_RGDAACn_M2UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2UM) \| BF_MPU_RGDAACn_M2UM(v)))
mbed_official	324:406fd2029f23	1405	/@}/
mbed_official	324:406fd2029f23	1406
mbed_official	324:406fd2029f23	1407	/*!
mbed_official	324:406fd2029f23	1408	* @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
mbed_official	324:406fd2029f23	1409	*
mbed_official	324:406fd2029f23	1410	* See M3SM description.
mbed_official	324:406fd2029f23	1411	*/
mbed_official	324:406fd2029f23	1412	/@{/
mbed_official	324:406fd2029f23	1413	#define BP_MPU_RGDAACn_M2SM (15U) /!< Bit position for MPU_RGDAACn_M2SM. /
mbed_official	324:406fd2029f23	1414	#define BM_MPU_RGDAACn_M2SM (0x00018000U) /!< Bit mask for MPU_RGDAACn_M2SM. /
mbed_official	324:406fd2029f23	1415	#define BS_MPU_RGDAACn_M2SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M2SM. /
mbed_official	324:406fd2029f23	1416
mbed_official	324:406fd2029f23	1417	/! @brief Read current value of the MPU_RGDAACn_M2SM field. /
mbed_official	324:406fd2029f23	1418	#define BR_MPU_RGDAACn_M2SM(x, n) (HW_MPU_RGDAACn(x, n).B.M2SM)
mbed_official	324:406fd2029f23	1419
mbed_official	324:406fd2029f23	1420	/! @brief Format value for bitfield MPU_RGDAACn_M2SM. /
mbed_official	324:406fd2029f23	1421	#define BF_MPU_RGDAACn_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2SM) & BM_MPU_RGDAACn_M2SM)
mbed_official	324:406fd2029f23	1422
mbed_official	324:406fd2029f23	1423	/! @brief Set the M2SM field to a new value. /
mbed_official	324:406fd2029f23	1424	#define BW_MPU_RGDAACn_M2SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2SM) \| BF_MPU_RGDAACn_M2SM(v)))
mbed_official	324:406fd2029f23	1425	/@}/
mbed_official	324:406fd2029f23	1426
mbed_official	324:406fd2029f23	1427	/*!
mbed_official	324:406fd2029f23	1428	* @name Register MPU_RGDAACn, field M2PE[17] (RW)
mbed_official	324:406fd2029f23	1429	*
mbed_official	324:406fd2029f23	1430	* See M3PE description.
mbed_official	324:406fd2029f23	1431	*/
mbed_official	324:406fd2029f23	1432	/@{/
mbed_official	324:406fd2029f23	1433	#define BP_MPU_RGDAACn_M2PE (17U) /!< Bit position for MPU_RGDAACn_M2PE. /
mbed_official	324:406fd2029f23	1434	#define BM_MPU_RGDAACn_M2PE (0x00020000U) /!< Bit mask for MPU_RGDAACn_M2PE. /
mbed_official	324:406fd2029f23	1435	#define BS_MPU_RGDAACn_M2PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M2PE. /
mbed_official	324:406fd2029f23	1436
mbed_official	324:406fd2029f23	1437	/! @brief Read current value of the MPU_RGDAACn_M2PE field. /
mbed_official	324:406fd2029f23	1438	#define BR_MPU_RGDAACn_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE))
mbed_official	324:406fd2029f23	1439
mbed_official	324:406fd2029f23	1440	/! @brief Format value for bitfield MPU_RGDAACn_M2PE. /
mbed_official	324:406fd2029f23	1441	#define BF_MPU_RGDAACn_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2PE) & BM_MPU_RGDAACn_M2PE)
mbed_official	324:406fd2029f23	1442
mbed_official	324:406fd2029f23	1443	/! @brief Set the M2PE field to a new value. /
mbed_official	324:406fd2029f23	1444	#define BW_MPU_RGDAACn_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE) = (v))
mbed_official	324:406fd2029f23	1445	/@}/
mbed_official	324:406fd2029f23	1446
mbed_official	324:406fd2029f23	1447	/*!
mbed_official	324:406fd2029f23	1448	* @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
mbed_official	324:406fd2029f23	1449	*
mbed_official	324:406fd2029f23	1450	* Defines the access controls for bus master 3 in user mode. M3UM consists of
mbed_official	324:406fd2029f23	1451	* three independent bits, enabling read (r), write (w), and execute (x)
mbed_official	324:406fd2029f23	1452	* permissions.
mbed_official	324:406fd2029f23	1453	*
mbed_official	324:406fd2029f23	1454	* Values:
mbed_official	324:406fd2029f23	1455	* - 0 - An attempted access of that mode may be terminated with an access error
mbed_official	324:406fd2029f23	1456	* (if not allowed by another descriptor) and the access not performed.
mbed_official	324:406fd2029f23	1457	* - 1 - Allows the given access type to occur
mbed_official	324:406fd2029f23	1458	*/
mbed_official	324:406fd2029f23	1459	/@{/
mbed_official	324:406fd2029f23	1460	#define BP_MPU_RGDAACn_M3UM (18U) /!< Bit position for MPU_RGDAACn_M3UM. /
mbed_official	324:406fd2029f23	1461	#define BM_MPU_RGDAACn_M3UM (0x001C0000U) /!< Bit mask for MPU_RGDAACn_M3UM. /
mbed_official	324:406fd2029f23	1462	#define BS_MPU_RGDAACn_M3UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M3UM. /
mbed_official	324:406fd2029f23	1463
mbed_official	324:406fd2029f23	1464	/! @brief Read current value of the MPU_RGDAACn_M3UM field. /
mbed_official	324:406fd2029f23	1465	#define BR_MPU_RGDAACn_M3UM(x, n) (HW_MPU_RGDAACn(x, n).B.M3UM)
mbed_official	324:406fd2029f23	1466
mbed_official	324:406fd2029f23	1467	/! @brief Format value for bitfield MPU_RGDAACn_M3UM. /
mbed_official	324:406fd2029f23	1468	#define BF_MPU_RGDAACn_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3UM) & BM_MPU_RGDAACn_M3UM)
mbed_official	324:406fd2029f23	1469
mbed_official	324:406fd2029f23	1470	/! @brief Set the M3UM field to a new value. /
mbed_official	324:406fd2029f23	1471	#define BW_MPU_RGDAACn_M3UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3UM) \| BF_MPU_RGDAACn_M3UM(v)))
mbed_official	324:406fd2029f23	1472	/@}/
mbed_official	324:406fd2029f23	1473
mbed_official	324:406fd2029f23	1474	/*!
mbed_official	324:406fd2029f23	1475	* @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
mbed_official	324:406fd2029f23	1476	*
mbed_official	324:406fd2029f23	1477	* Defines the access controls for bus master 3 in Supervisor mode.
mbed_official	324:406fd2029f23	1478	*
mbed_official	324:406fd2029f23	1479	* Values:
mbed_official	324:406fd2029f23	1480	* - 00 - r/w/x; read, write and execute allowed
mbed_official	324:406fd2029f23	1481	* - 01 - r/x; read and execute allowed, but no write
mbed_official	324:406fd2029f23	1482	* - 10 - r/w; read and write allowed, but no execute
mbed_official	324:406fd2029f23	1483	* - 11 - Same as User mode defined in M3UM
mbed_official	324:406fd2029f23	1484	*/
mbed_official	324:406fd2029f23	1485	/@{/
mbed_official	324:406fd2029f23	1486	#define BP_MPU_RGDAACn_M3SM (21U) /!< Bit position for MPU_RGDAACn_M3SM. /
mbed_official	324:406fd2029f23	1487	#define BM_MPU_RGDAACn_M3SM (0x00600000U) /!< Bit mask for MPU_RGDAACn_M3SM. /
mbed_official	324:406fd2029f23	1488	#define BS_MPU_RGDAACn_M3SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M3SM. /
mbed_official	324:406fd2029f23	1489
mbed_official	324:406fd2029f23	1490	/! @brief Read current value of the MPU_RGDAACn_M3SM field. /
mbed_official	324:406fd2029f23	1491	#define BR_MPU_RGDAACn_M3SM(x, n) (HW_MPU_RGDAACn(x, n).B.M3SM)
mbed_official	324:406fd2029f23	1492
mbed_official	324:406fd2029f23	1493	/! @brief Format value for bitfield MPU_RGDAACn_M3SM. /
mbed_official	324:406fd2029f23	1494	#define BF_MPU_RGDAACn_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3SM) & BM_MPU_RGDAACn_M3SM)
mbed_official	324:406fd2029f23	1495
mbed_official	324:406fd2029f23	1496	/! @brief Set the M3SM field to a new value. /
mbed_official	324:406fd2029f23	1497	#define BW_MPU_RGDAACn_M3SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3SM) \| BF_MPU_RGDAACn_M3SM(v)))
mbed_official	324:406fd2029f23	1498	/@}/
mbed_official	324:406fd2029f23	1499
mbed_official	324:406fd2029f23	1500	/*!
mbed_official	324:406fd2029f23	1501	* @name Register MPU_RGDAACn, field M3PE[23] (RW)
mbed_official	324:406fd2029f23	1502	*
mbed_official	324:406fd2029f23	1503	* Values:
mbed_official	324:406fd2029f23	1504	* - 0 - Do not include the process identifier in the evaluation
mbed_official	324:406fd2029f23	1505	* - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
mbed_official	324:406fd2029f23	1506	* evaluation
mbed_official	324:406fd2029f23	1507	*/
mbed_official	324:406fd2029f23	1508	/@{/
mbed_official	324:406fd2029f23	1509	#define BP_MPU_RGDAACn_M3PE (23U) /!< Bit position for MPU_RGDAACn_M3PE. /
mbed_official	324:406fd2029f23	1510	#define BM_MPU_RGDAACn_M3PE (0x00800000U) /!< Bit mask for MPU_RGDAACn_M3PE. /
mbed_official	324:406fd2029f23	1511	#define BS_MPU_RGDAACn_M3PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M3PE. /
mbed_official	324:406fd2029f23	1512
mbed_official	324:406fd2029f23	1513	/! @brief Read current value of the MPU_RGDAACn_M3PE field. /
mbed_official	324:406fd2029f23	1514	#define BR_MPU_RGDAACn_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE))
mbed_official	324:406fd2029f23	1515
mbed_official	324:406fd2029f23	1516	/! @brief Format value for bitfield MPU_RGDAACn_M3PE. /
mbed_official	324:406fd2029f23	1517	#define BF_MPU_RGDAACn_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3PE) & BM_MPU_RGDAACn_M3PE)
mbed_official	324:406fd2029f23	1518
mbed_official	324:406fd2029f23	1519	/! @brief Set the M3PE field to a new value. /
mbed_official	324:406fd2029f23	1520	#define BW_MPU_RGDAACn_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE) = (v))
mbed_official	324:406fd2029f23	1521	/@}/
mbed_official	324:406fd2029f23	1522
mbed_official	324:406fd2029f23	1523	/*!
mbed_official	324:406fd2029f23	1524	* @name Register MPU_RGDAACn, field M4WE[24] (RW)
mbed_official	324:406fd2029f23	1525	*
mbed_official	324:406fd2029f23	1526	* Values:
mbed_official	324:406fd2029f23	1527	* - 0 - Bus master 4 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	1528	* performed
mbed_official	324:406fd2029f23	1529	* - 1 - Bus master 4 writes allowed
mbed_official	324:406fd2029f23	1530	*/
mbed_official	324:406fd2029f23	1531	/@{/
mbed_official	324:406fd2029f23	1532	#define BP_MPU_RGDAACn_M4WE (24U) /!< Bit position for MPU_RGDAACn_M4WE. /
mbed_official	324:406fd2029f23	1533	#define BM_MPU_RGDAACn_M4WE (0x01000000U) /!< Bit mask for MPU_RGDAACn_M4WE. /
mbed_official	324:406fd2029f23	1534	#define BS_MPU_RGDAACn_M4WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M4WE. /
mbed_official	324:406fd2029f23	1535
mbed_official	324:406fd2029f23	1536	/! @brief Read current value of the MPU_RGDAACn_M4WE field. /
mbed_official	324:406fd2029f23	1537	#define BR_MPU_RGDAACn_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE))
mbed_official	324:406fd2029f23	1538
mbed_official	324:406fd2029f23	1539	/! @brief Format value for bitfield MPU_RGDAACn_M4WE. /
mbed_official	324:406fd2029f23	1540	#define BF_MPU_RGDAACn_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4WE) & BM_MPU_RGDAACn_M4WE)
mbed_official	324:406fd2029f23	1541
mbed_official	324:406fd2029f23	1542	/! @brief Set the M4WE field to a new value. /
mbed_official	324:406fd2029f23	1543	#define BW_MPU_RGDAACn_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE) = (v))
mbed_official	324:406fd2029f23	1544	/@}/
mbed_official	324:406fd2029f23	1545
mbed_official	324:406fd2029f23	1546	/*!
mbed_official	324:406fd2029f23	1547	* @name Register MPU_RGDAACn, field M4RE[25] (RW)
mbed_official	324:406fd2029f23	1548	*
mbed_official	324:406fd2029f23	1549	* Values:
mbed_official	324:406fd2029f23	1550	* - 0 - Bus master 4 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1551	* performed
mbed_official	324:406fd2029f23	1552	* - 1 - Bus master 4 reads allowed
mbed_official	324:406fd2029f23	1553	*/
mbed_official	324:406fd2029f23	1554	/@{/
mbed_official	324:406fd2029f23	1555	#define BP_MPU_RGDAACn_M4RE (25U) /!< Bit position for MPU_RGDAACn_M4RE. /
mbed_official	324:406fd2029f23	1556	#define BM_MPU_RGDAACn_M4RE (0x02000000U) /!< Bit mask for MPU_RGDAACn_M4RE. /
mbed_official	324:406fd2029f23	1557	#define BS_MPU_RGDAACn_M4RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M4RE. /
mbed_official	324:406fd2029f23	1558
mbed_official	324:406fd2029f23	1559	/! @brief Read current value of the MPU_RGDAACn_M4RE field. /
mbed_official	324:406fd2029f23	1560	#define BR_MPU_RGDAACn_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE))
mbed_official	324:406fd2029f23	1561
mbed_official	324:406fd2029f23	1562	/! @brief Format value for bitfield MPU_RGDAACn_M4RE. /
mbed_official	324:406fd2029f23	1563	#define BF_MPU_RGDAACn_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4RE) & BM_MPU_RGDAACn_M4RE)
mbed_official	324:406fd2029f23	1564
mbed_official	324:406fd2029f23	1565	/! @brief Set the M4RE field to a new value. /
mbed_official	324:406fd2029f23	1566	#define BW_MPU_RGDAACn_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE) = (v))
mbed_official	324:406fd2029f23	1567	/@}/
mbed_official	324:406fd2029f23	1568
mbed_official	324:406fd2029f23	1569	/*!
mbed_official	324:406fd2029f23	1570	* @name Register MPU_RGDAACn, field M5WE[26] (RW)
mbed_official	324:406fd2029f23	1571	*
mbed_official	324:406fd2029f23	1572	* Values:
mbed_official	324:406fd2029f23	1573	* - 0 - Bus master 5 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	1574	* performed
mbed_official	324:406fd2029f23	1575	* - 1 - Bus master 5 writes allowed
mbed_official	324:406fd2029f23	1576	*/
mbed_official	324:406fd2029f23	1577	/@{/
mbed_official	324:406fd2029f23	1578	#define BP_MPU_RGDAACn_M5WE (26U) /!< Bit position for MPU_RGDAACn_M5WE. /
mbed_official	324:406fd2029f23	1579	#define BM_MPU_RGDAACn_M5WE (0x04000000U) /!< Bit mask for MPU_RGDAACn_M5WE. /
mbed_official	324:406fd2029f23	1580	#define BS_MPU_RGDAACn_M5WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M5WE. /
mbed_official	324:406fd2029f23	1581
mbed_official	324:406fd2029f23	1582	/! @brief Read current value of the MPU_RGDAACn_M5WE field. /
mbed_official	324:406fd2029f23	1583	#define BR_MPU_RGDAACn_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE))
mbed_official	324:406fd2029f23	1584
mbed_official	324:406fd2029f23	1585	/! @brief Format value for bitfield MPU_RGDAACn_M5WE. /
mbed_official	324:406fd2029f23	1586	#define BF_MPU_RGDAACn_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5WE) & BM_MPU_RGDAACn_M5WE)
mbed_official	324:406fd2029f23	1587
mbed_official	324:406fd2029f23	1588	/! @brief Set the M5WE field to a new value. /
mbed_official	324:406fd2029f23	1589	#define BW_MPU_RGDAACn_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE) = (v))
mbed_official	324:406fd2029f23	1590	/@}/
mbed_official	324:406fd2029f23	1591
mbed_official	324:406fd2029f23	1592	/*!
mbed_official	324:406fd2029f23	1593	* @name Register MPU_RGDAACn, field M5RE[27] (RW)
mbed_official	324:406fd2029f23	1594	*
mbed_official	324:406fd2029f23	1595	* Values:
mbed_official	324:406fd2029f23	1596	* - 0 - Bus master 5 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1597	* performed
mbed_official	324:406fd2029f23	1598	* - 1 - Bus master 5 reads allowed
mbed_official	324:406fd2029f23	1599	*/
mbed_official	324:406fd2029f23	1600	/@{/
mbed_official	324:406fd2029f23	1601	#define BP_MPU_RGDAACn_M5RE (27U) /!< Bit position for MPU_RGDAACn_M5RE. /
mbed_official	324:406fd2029f23	1602	#define BM_MPU_RGDAACn_M5RE (0x08000000U) /!< Bit mask for MPU_RGDAACn_M5RE. /
mbed_official	324:406fd2029f23	1603	#define BS_MPU_RGDAACn_M5RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M5RE. /
mbed_official	324:406fd2029f23	1604
mbed_official	324:406fd2029f23	1605	/! @brief Read current value of the MPU_RGDAACn_M5RE field. /
mbed_official	324:406fd2029f23	1606	#define BR_MPU_RGDAACn_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE))
mbed_official	324:406fd2029f23	1607
mbed_official	324:406fd2029f23	1608	/! @brief Format value for bitfield MPU_RGDAACn_M5RE. /
mbed_official	324:406fd2029f23	1609	#define BF_MPU_RGDAACn_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5RE) & BM_MPU_RGDAACn_M5RE)
mbed_official	324:406fd2029f23	1610
mbed_official	324:406fd2029f23	1611	/! @brief Set the M5RE field to a new value. /
mbed_official	324:406fd2029f23	1612	#define BW_MPU_RGDAACn_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE) = (v))
mbed_official	324:406fd2029f23	1613	/@}/
mbed_official	324:406fd2029f23	1614
mbed_official	324:406fd2029f23	1615	/*!
mbed_official	324:406fd2029f23	1616	* @name Register MPU_RGDAACn, field M6WE[28] (RW)
mbed_official	324:406fd2029f23	1617	*
mbed_official	324:406fd2029f23	1618	* Values:
mbed_official	324:406fd2029f23	1619	* - 0 - Bus master 6 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	1620	* performed
mbed_official	324:406fd2029f23	1621	* - 1 - Bus master 6 writes allowed
mbed_official	324:406fd2029f23	1622	*/
mbed_official	324:406fd2029f23	1623	/@{/
mbed_official	324:406fd2029f23	1624	#define BP_MPU_RGDAACn_M6WE (28U) /!< Bit position for MPU_RGDAACn_M6WE. /
mbed_official	324:406fd2029f23	1625	#define BM_MPU_RGDAACn_M6WE (0x10000000U) /!< Bit mask for MPU_RGDAACn_M6WE. /
mbed_official	324:406fd2029f23	1626	#define BS_MPU_RGDAACn_M6WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M6WE. /
mbed_official	324:406fd2029f23	1627
mbed_official	324:406fd2029f23	1628	/! @brief Read current value of the MPU_RGDAACn_M6WE field. /
mbed_official	324:406fd2029f23	1629	#define BR_MPU_RGDAACn_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE))
mbed_official	324:406fd2029f23	1630
mbed_official	324:406fd2029f23	1631	/! @brief Format value for bitfield MPU_RGDAACn_M6WE. /
mbed_official	324:406fd2029f23	1632	#define BF_MPU_RGDAACn_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6WE) & BM_MPU_RGDAACn_M6WE)
mbed_official	324:406fd2029f23	1633
mbed_official	324:406fd2029f23	1634	/! @brief Set the M6WE field to a new value. /
mbed_official	324:406fd2029f23	1635	#define BW_MPU_RGDAACn_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE) = (v))
mbed_official	324:406fd2029f23	1636	/@}/
mbed_official	324:406fd2029f23	1637
mbed_official	324:406fd2029f23	1638	/*!
mbed_official	324:406fd2029f23	1639	* @name Register MPU_RGDAACn, field M6RE[29] (RW)
mbed_official	324:406fd2029f23	1640	*
mbed_official	324:406fd2029f23	1641	* Values:
mbed_official	324:406fd2029f23	1642	* - 0 - Bus master 6 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1643	* performed
mbed_official	324:406fd2029f23	1644	* - 1 - Bus master 6 reads allowed
mbed_official	324:406fd2029f23	1645	*/
mbed_official	324:406fd2029f23	1646	/@{/
mbed_official	324:406fd2029f23	1647	#define BP_MPU_RGDAACn_M6RE (29U) /!< Bit position for MPU_RGDAACn_M6RE. /
mbed_official	324:406fd2029f23	1648	#define BM_MPU_RGDAACn_M6RE (0x20000000U) /!< Bit mask for MPU_RGDAACn_M6RE. /
mbed_official	324:406fd2029f23	1649	#define BS_MPU_RGDAACn_M6RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M6RE. /
mbed_official	324:406fd2029f23	1650
mbed_official	324:406fd2029f23	1651	/! @brief Read current value of the MPU_RGDAACn_M6RE field. /
mbed_official	324:406fd2029f23	1652	#define BR_MPU_RGDAACn_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE))
mbed_official	324:406fd2029f23	1653
mbed_official	324:406fd2029f23	1654	/! @brief Format value for bitfield MPU_RGDAACn_M6RE. /
mbed_official	324:406fd2029f23	1655	#define BF_MPU_RGDAACn_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6RE) & BM_MPU_RGDAACn_M6RE)
mbed_official	324:406fd2029f23	1656
mbed_official	324:406fd2029f23	1657	/! @brief Set the M6RE field to a new value. /
mbed_official	324:406fd2029f23	1658	#define BW_MPU_RGDAACn_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE) = (v))
mbed_official	324:406fd2029f23	1659	/@}/
mbed_official	324:406fd2029f23	1660
mbed_official	324:406fd2029f23	1661	/*!
mbed_official	324:406fd2029f23	1662	* @name Register MPU_RGDAACn, field M7WE[30] (RW)
mbed_official	324:406fd2029f23	1663	*
mbed_official	324:406fd2029f23	1664	* Values:
mbed_official	324:406fd2029f23	1665	* - 0 - Bus master 7 writes terminate with an access error and the write is not
mbed_official	324:406fd2029f23	1666	* performed
mbed_official	324:406fd2029f23	1667	* - 1 - Bus master 7 writes allowed
mbed_official	324:406fd2029f23	1668	*/
mbed_official	324:406fd2029f23	1669	/@{/
mbed_official	324:406fd2029f23	1670	#define BP_MPU_RGDAACn_M7WE (30U) /!< Bit position for MPU_RGDAACn_M7WE. /
mbed_official	324:406fd2029f23	1671	#define BM_MPU_RGDAACn_M7WE (0x40000000U) /!< Bit mask for MPU_RGDAACn_M7WE. /
mbed_official	324:406fd2029f23	1672	#define BS_MPU_RGDAACn_M7WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M7WE. /
mbed_official	324:406fd2029f23	1673
mbed_official	324:406fd2029f23	1674	/! @brief Read current value of the MPU_RGDAACn_M7WE field. /
mbed_official	324:406fd2029f23	1675	#define BR_MPU_RGDAACn_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE))
mbed_official	324:406fd2029f23	1676
mbed_official	324:406fd2029f23	1677	/! @brief Format value for bitfield MPU_RGDAACn_M7WE. /
mbed_official	324:406fd2029f23	1678	#define BF_MPU_RGDAACn_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7WE) & BM_MPU_RGDAACn_M7WE)
mbed_official	324:406fd2029f23	1679
mbed_official	324:406fd2029f23	1680	/! @brief Set the M7WE field to a new value. /
mbed_official	324:406fd2029f23	1681	#define BW_MPU_RGDAACn_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE) = (v))
mbed_official	324:406fd2029f23	1682	/@}/
mbed_official	324:406fd2029f23	1683
mbed_official	324:406fd2029f23	1684	/*!
mbed_official	324:406fd2029f23	1685	* @name Register MPU_RGDAACn, field M7RE[31] (RW)
mbed_official	324:406fd2029f23	1686	*
mbed_official	324:406fd2029f23	1687	* Values:
mbed_official	324:406fd2029f23	1688	* - 0 - Bus master 7 reads terminate with an access error and the read is not
mbed_official	324:406fd2029f23	1689	* performed
mbed_official	324:406fd2029f23	1690	* - 1 - Bus master 7 reads allowed
mbed_official	324:406fd2029f23	1691	*/
mbed_official	324:406fd2029f23	1692	/@{/
mbed_official	324:406fd2029f23	1693	#define BP_MPU_RGDAACn_M7RE (31U) /!< Bit position for MPU_RGDAACn_M7RE. /
mbed_official	324:406fd2029f23	1694	#define BM_MPU_RGDAACn_M7RE (0x80000000U) /!< Bit mask for MPU_RGDAACn_M7RE. /
mbed_official	324:406fd2029f23	1695	#define BS_MPU_RGDAACn_M7RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M7RE. /
mbed_official	324:406fd2029f23	1696
mbed_official	324:406fd2029f23	1697	/! @brief Read current value of the MPU_RGDAACn_M7RE field. /
mbed_official	324:406fd2029f23	1698	#define BR_MPU_RGDAACn_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE))
mbed_official	324:406fd2029f23	1699
mbed_official	324:406fd2029f23	1700	/! @brief Format value for bitfield MPU_RGDAACn_M7RE. /
mbed_official	324:406fd2029f23	1701	#define BF_MPU_RGDAACn_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7RE) & BM_MPU_RGDAACn_M7RE)
mbed_official	324:406fd2029f23	1702
mbed_official	324:406fd2029f23	1703	/! @brief Set the M7RE field to a new value. /
mbed_official	324:406fd2029f23	1704	#define BW_MPU_RGDAACn_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE) = (v))
mbed_official	324:406fd2029f23	1705	/@}/
mbed_official	324:406fd2029f23	1706
mbed_official	324:406fd2029f23	1707	/*******************************************************************************
mbed_official	324:406fd2029f23	1708	* hw_mpu_t - module struct
mbed_official	324:406fd2029f23	1709	******************************************************************************/
mbed_official	324:406fd2029f23	1710	/*!
mbed_official	324:406fd2029f23	1711	* @brief All MPU module registers.
mbed_official	324:406fd2029f23	1712	*/
mbed_official	324:406fd2029f23	1713	#pragma pack(1)
mbed_official	324:406fd2029f23	1714	typedef struct _hw_mpu
mbed_official	324:406fd2029f23	1715	{
mbed_official	324:406fd2029f23	1716	__IO hw_mpu_cesr_t CESR; /!< [0x0] Control/Error Status Register /
mbed_official	324:406fd2029f23	1717	uint8_t _reserved0[12];
mbed_official	324:406fd2029f23	1718	struct {
mbed_official	324:406fd2029f23	1719	__I hw_mpu_earn_t EARn; /!< [0x10] Error Address Register, slave port n /
mbed_official	324:406fd2029f23	1720	__I hw_mpu_edrn_t EDRn; /!< [0x14] Error Detail Register, slave port n /
mbed_official	324:406fd2029f23	1721	} SP[5];
mbed_official	324:406fd2029f23	1722	uint8_t _reserved1[968];
mbed_official	324:406fd2029f23	1723	struct {
mbed_official	324:406fd2029f23	1724	__IO hw_mpu_rgdn_word0_t RGDn_WORD0; /!< [0x400] Region Descriptor n, Word 0 /
mbed_official	324:406fd2029f23	1725	__IO hw_mpu_rgdn_word1_t RGDn_WORD1; /!< [0x404] Region Descriptor n, Word 1 /
mbed_official	324:406fd2029f23	1726	__IO hw_mpu_rgdn_word2_t RGDn_WORD2; /!< [0x408] Region Descriptor n, Word 2 /
mbed_official	324:406fd2029f23	1727	__IO hw_mpu_rgdn_word3_t RGDn_WORD3; /!< [0x40C] Region Descriptor n, Word 3 /
mbed_official	324:406fd2029f23	1728	} RGD[12];
mbed_official	324:406fd2029f23	1729	uint8_t _reserved2[832];
mbed_official	324:406fd2029f23	1730	__IO hw_mpu_rgdaacn_t RGDAACn[12]; /!< [0x800] Region Descriptor Alternate Access Control n /
mbed_official	324:406fd2029f23	1731	} hw_mpu_t;
mbed_official	324:406fd2029f23	1732	#pragma pack()
mbed_official	324:406fd2029f23	1733
mbed_official	324:406fd2029f23	1734	/! @brief Macro to access all MPU registers. /
mbed_official	324:406fd2029f23	1735	/! @param x MPU module instance base address. /
mbed_official	324:406fd2029f23	1736	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	1737	* use the '&' operator, like <code>&HW_MPU(MPU_BASE)</code>. */
mbed_official	324:406fd2029f23	1738	#define HW_MPU(x) ((hw_mpu_t )(x))
mbed_official	324:406fd2029f23	1739
mbed_official	324:406fd2029f23	1740	#endif /* __HW_MPU_REGISTERS_H__ */
mbed_official	324:406fd2029f23	1741	/* EOF */