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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_I2C_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_I2C_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 I2C
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Inter-Integrated Circuit
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_I2C_A1 - I2C Address Register 1
mbed_official 324:406fd2029f23 93 * - HW_I2C_F - I2C Frequency Divider register
mbed_official 324:406fd2029f23 94 * - HW_I2C_C1 - I2C Control Register 1
mbed_official 324:406fd2029f23 95 * - HW_I2C_S - I2C Status register
mbed_official 324:406fd2029f23 96 * - HW_I2C_D - I2C Data I/O register
mbed_official 324:406fd2029f23 97 * - HW_I2C_C2 - I2C Control Register 2
mbed_official 324:406fd2029f23 98 * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
mbed_official 324:406fd2029f23 99 * - HW_I2C_RA - I2C Range Address register
mbed_official 324:406fd2029f23 100 * - HW_I2C_SMB - I2C SMBus Control and Status register
mbed_official 324:406fd2029f23 101 * - HW_I2C_A2 - I2C Address Register 2
mbed_official 324:406fd2029f23 102 * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
mbed_official 324:406fd2029f23 103 * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
mbed_official 324:406fd2029f23 104 *
mbed_official 324:406fd2029f23 105 * - hw_i2c_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 106 */
mbed_official 324:406fd2029f23 107
mbed_official 324:406fd2029f23 108 #define HW_I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
mbed_official 324:406fd2029f23 109 #define HW_I2C0 (0U) /*!< Instance number for I2C0. */
mbed_official 324:406fd2029f23 110 #define HW_I2C1 (1U) /*!< Instance number for I2C1. */
mbed_official 324:406fd2029f23 111 #define HW_I2C2 (2U) /*!< Instance number for I2C2. */
mbed_official 324:406fd2029f23 112
mbed_official 324:406fd2029f23 113 /*******************************************************************************
mbed_official 324:406fd2029f23 114 * HW_I2C_A1 - I2C Address Register 1
mbed_official 324:406fd2029f23 115 ******************************************************************************/
mbed_official 324:406fd2029f23 116
mbed_official 324:406fd2029f23 117 /*!
mbed_official 324:406fd2029f23 118 * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
mbed_official 324:406fd2029f23 119 *
mbed_official 324:406fd2029f23 120 * Reset value: 0x00U
mbed_official 324:406fd2029f23 121 *
mbed_official 324:406fd2029f23 122 * This register contains the slave address to be used by the I2C module.
mbed_official 324:406fd2029f23 123 */
mbed_official 324:406fd2029f23 124 typedef union _hw_i2c_a1
mbed_official 324:406fd2029f23 125 {
mbed_official 324:406fd2029f23 126 uint8_t U;
mbed_official 324:406fd2029f23 127 struct _hw_i2c_a1_bitfields
mbed_official 324:406fd2029f23 128 {
mbed_official 324:406fd2029f23 129 uint8_t RESERVED0 : 1; /*!< [0] */
mbed_official 324:406fd2029f23 130 uint8_t AD : 7; /*!< [7:1] Address */
mbed_official 324:406fd2029f23 131 } B;
mbed_official 324:406fd2029f23 132 } hw_i2c_a1_t;
mbed_official 324:406fd2029f23 133
mbed_official 324:406fd2029f23 134 /*!
mbed_official 324:406fd2029f23 135 * @name Constants and macros for entire I2C_A1 register
mbed_official 324:406fd2029f23 136 */
mbed_official 324:406fd2029f23 137 /*@{*/
mbed_official 324:406fd2029f23 138 #define HW_I2C_A1_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 139
mbed_official 324:406fd2029f23 140 #define HW_I2C_A1(x) (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
mbed_official 324:406fd2029f23 141 #define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U)
mbed_official 324:406fd2029f23 142 #define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v))
mbed_official 324:406fd2029f23 143 #define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) | (v)))
mbed_official 324:406fd2029f23 144 #define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 145 #define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 146 /*@}*/
mbed_official 324:406fd2029f23 147
mbed_official 324:406fd2029f23 148 /*
mbed_official 324:406fd2029f23 149 * Constants & macros for individual I2C_A1 bitfields
mbed_official 324:406fd2029f23 150 */
mbed_official 324:406fd2029f23 151
mbed_official 324:406fd2029f23 152 /*!
mbed_official 324:406fd2029f23 153 * @name Register I2C_A1, field AD[7:1] (RW)
mbed_official 324:406fd2029f23 154 *
mbed_official 324:406fd2029f23 155 * Contains the primary slave address used by the I2C module when it is
mbed_official 324:406fd2029f23 156 * addressed as a slave. This field is used in the 7-bit address scheme and the lower
mbed_official 324:406fd2029f23 157 * seven bits in the 10-bit address scheme.
mbed_official 324:406fd2029f23 158 */
mbed_official 324:406fd2029f23 159 /*@{*/
mbed_official 324:406fd2029f23 160 #define BP_I2C_A1_AD (1U) /*!< Bit position for I2C_A1_AD. */
mbed_official 324:406fd2029f23 161 #define BM_I2C_A1_AD (0xFEU) /*!< Bit mask for I2C_A1_AD. */
mbed_official 324:406fd2029f23 162 #define BS_I2C_A1_AD (7U) /*!< Bit field size in bits for I2C_A1_AD. */
mbed_official 324:406fd2029f23 163
mbed_official 324:406fd2029f23 164 /*! @brief Read current value of the I2C_A1_AD field. */
mbed_official 324:406fd2029f23 165 #define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD)
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 /*! @brief Format value for bitfield I2C_A1_AD. */
mbed_official 324:406fd2029f23 168 #define BF_I2C_A1_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD)
mbed_official 324:406fd2029f23 169
mbed_official 324:406fd2029f23 170 /*! @brief Set the AD field to a new value. */
mbed_official 324:406fd2029f23 171 #define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
mbed_official 324:406fd2029f23 172 /*@}*/
mbed_official 324:406fd2029f23 173
mbed_official 324:406fd2029f23 174 /*******************************************************************************
mbed_official 324:406fd2029f23 175 * HW_I2C_F - I2C Frequency Divider register
mbed_official 324:406fd2029f23 176 ******************************************************************************/
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*!
mbed_official 324:406fd2029f23 179 * @brief HW_I2C_F - I2C Frequency Divider register (RW)
mbed_official 324:406fd2029f23 180 *
mbed_official 324:406fd2029f23 181 * Reset value: 0x00U
mbed_official 324:406fd2029f23 182 */
mbed_official 324:406fd2029f23 183 typedef union _hw_i2c_f
mbed_official 324:406fd2029f23 184 {
mbed_official 324:406fd2029f23 185 uint8_t U;
mbed_official 324:406fd2029f23 186 struct _hw_i2c_f_bitfields
mbed_official 324:406fd2029f23 187 {
mbed_official 324:406fd2029f23 188 uint8_t ICR : 6; /*!< [5:0] ClockRate */
mbed_official 324:406fd2029f23 189 uint8_t MULT : 2; /*!< [7:6] Multiplier Factor */
mbed_official 324:406fd2029f23 190 } B;
mbed_official 324:406fd2029f23 191 } hw_i2c_f_t;
mbed_official 324:406fd2029f23 192
mbed_official 324:406fd2029f23 193 /*!
mbed_official 324:406fd2029f23 194 * @name Constants and macros for entire I2C_F register
mbed_official 324:406fd2029f23 195 */
mbed_official 324:406fd2029f23 196 /*@{*/
mbed_official 324:406fd2029f23 197 #define HW_I2C_F_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 198
mbed_official 324:406fd2029f23 199 #define HW_I2C_F(x) (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
mbed_official 324:406fd2029f23 200 #define HW_I2C_F_RD(x) (HW_I2C_F(x).U)
mbed_official 324:406fd2029f23 201 #define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v))
mbed_official 324:406fd2029f23 202 #define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) | (v)))
mbed_official 324:406fd2029f23 203 #define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 204 #define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 205 /*@}*/
mbed_official 324:406fd2029f23 206
mbed_official 324:406fd2029f23 207 /*
mbed_official 324:406fd2029f23 208 * Constants & macros for individual I2C_F bitfields
mbed_official 324:406fd2029f23 209 */
mbed_official 324:406fd2029f23 210
mbed_official 324:406fd2029f23 211 /*!
mbed_official 324:406fd2029f23 212 * @name Register I2C_F, field ICR[5:0] (RW)
mbed_official 324:406fd2029f23 213 *
mbed_official 324:406fd2029f23 214 * Prescales the I2C module clock for bit rate selection. This field and the
mbed_official 324:406fd2029f23 215 * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
mbed_official 324:406fd2029f23 216 * time, and the SCL stop hold time. For a list of values corresponding to each ICR
mbed_official 324:406fd2029f23 217 * setting, see I2C divider and hold values. The SCL divider multiplied by
mbed_official 324:406fd2029f23 218 * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
mbed_official 324:406fd2029f23 219 * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
mbed_official 324:406fd2029f23 220 * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
mbed_official 324:406fd2029f23 221 * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
mbed_official 324:406fd2029f23 222 * the delay from the falling edge of SDA (I2C data) while SCL is high (start
mbed_official 324:406fd2029f23 223 * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
mbed_official 324:406fd2029f23 224 * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
mbed_official 324:406fd2029f23 225 * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
mbed_official 324:406fd2029f23 226 * data) while SCL is high (stop condition). SCL stop hold time = I2C module
mbed_official 324:406fd2029f23 227 * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
mbed_official 324:406fd2029f23 228 * speed is 8 MHz, the following table shows the possible hold time values with
mbed_official 324:406fd2029f23 229 * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
mbed_official 324:406fd2029f23 230 * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
mbed_official 324:406fd2029f23 231 * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
mbed_official 324:406fd2029f23 232 * 1.125 4.750 5.125
mbed_official 324:406fd2029f23 233 */
mbed_official 324:406fd2029f23 234 /*@{*/
mbed_official 324:406fd2029f23 235 #define BP_I2C_F_ICR (0U) /*!< Bit position for I2C_F_ICR. */
mbed_official 324:406fd2029f23 236 #define BM_I2C_F_ICR (0x3FU) /*!< Bit mask for I2C_F_ICR. */
mbed_official 324:406fd2029f23 237 #define BS_I2C_F_ICR (6U) /*!< Bit field size in bits for I2C_F_ICR. */
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*! @brief Read current value of the I2C_F_ICR field. */
mbed_official 324:406fd2029f23 240 #define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR)
mbed_official 324:406fd2029f23 241
mbed_official 324:406fd2029f23 242 /*! @brief Format value for bitfield I2C_F_ICR. */
mbed_official 324:406fd2029f23 243 #define BF_I2C_F_ICR(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR)
mbed_official 324:406fd2029f23 244
mbed_official 324:406fd2029f23 245 /*! @brief Set the ICR field to a new value. */
mbed_official 324:406fd2029f23 246 #define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
mbed_official 324:406fd2029f23 247 /*@}*/
mbed_official 324:406fd2029f23 248
mbed_official 324:406fd2029f23 249 /*!
mbed_official 324:406fd2029f23 250 * @name Register I2C_F, field MULT[7:6] (RW)
mbed_official 324:406fd2029f23 251 *
mbed_official 324:406fd2029f23 252 * Defines the multiplier factor (mul). This factor is used along with the SCL
mbed_official 324:406fd2029f23 253 * divider to generate the I2C baud rate.
mbed_official 324:406fd2029f23 254 *
mbed_official 324:406fd2029f23 255 * Values:
mbed_official 324:406fd2029f23 256 * - 00 - mul = 1
mbed_official 324:406fd2029f23 257 * - 01 - mul = 2
mbed_official 324:406fd2029f23 258 * - 10 - mul = 4
mbed_official 324:406fd2029f23 259 * - 11 - Reserved
mbed_official 324:406fd2029f23 260 */
mbed_official 324:406fd2029f23 261 /*@{*/
mbed_official 324:406fd2029f23 262 #define BP_I2C_F_MULT (6U) /*!< Bit position for I2C_F_MULT. */
mbed_official 324:406fd2029f23 263 #define BM_I2C_F_MULT (0xC0U) /*!< Bit mask for I2C_F_MULT. */
mbed_official 324:406fd2029f23 264 #define BS_I2C_F_MULT (2U) /*!< Bit field size in bits for I2C_F_MULT. */
mbed_official 324:406fd2029f23 265
mbed_official 324:406fd2029f23 266 /*! @brief Read current value of the I2C_F_MULT field. */
mbed_official 324:406fd2029f23 267 #define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT)
mbed_official 324:406fd2029f23 268
mbed_official 324:406fd2029f23 269 /*! @brief Format value for bitfield I2C_F_MULT. */
mbed_official 324:406fd2029f23 270 #define BF_I2C_F_MULT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT)
mbed_official 324:406fd2029f23 271
mbed_official 324:406fd2029f23 272 /*! @brief Set the MULT field to a new value. */
mbed_official 324:406fd2029f23 273 #define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
mbed_official 324:406fd2029f23 274 /*@}*/
mbed_official 324:406fd2029f23 275
mbed_official 324:406fd2029f23 276 /*******************************************************************************
mbed_official 324:406fd2029f23 277 * HW_I2C_C1 - I2C Control Register 1
mbed_official 324:406fd2029f23 278 ******************************************************************************/
mbed_official 324:406fd2029f23 279
mbed_official 324:406fd2029f23 280 /*!
mbed_official 324:406fd2029f23 281 * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
mbed_official 324:406fd2029f23 282 *
mbed_official 324:406fd2029f23 283 * Reset value: 0x00U
mbed_official 324:406fd2029f23 284 */
mbed_official 324:406fd2029f23 285 typedef union _hw_i2c_c1
mbed_official 324:406fd2029f23 286 {
mbed_official 324:406fd2029f23 287 uint8_t U;
mbed_official 324:406fd2029f23 288 struct _hw_i2c_c1_bitfields
mbed_official 324:406fd2029f23 289 {
mbed_official 324:406fd2029f23 290 uint8_t DMAEN : 1; /*!< [0] DMA Enable */
mbed_official 324:406fd2029f23 291 uint8_t WUEN : 1; /*!< [1] Wakeup Enable */
mbed_official 324:406fd2029f23 292 uint8_t RSTA : 1; /*!< [2] Repeat START */
mbed_official 324:406fd2029f23 293 uint8_t TXAK : 1; /*!< [3] Transmit Acknowledge Enable */
mbed_official 324:406fd2029f23 294 uint8_t TX : 1; /*!< [4] Transmit Mode Select */
mbed_official 324:406fd2029f23 295 uint8_t MST : 1; /*!< [5] Master Mode Select */
mbed_official 324:406fd2029f23 296 uint8_t IICIE : 1; /*!< [6] I2C Interrupt Enable */
mbed_official 324:406fd2029f23 297 uint8_t IICEN : 1; /*!< [7] I2C Enable */
mbed_official 324:406fd2029f23 298 } B;
mbed_official 324:406fd2029f23 299 } hw_i2c_c1_t;
mbed_official 324:406fd2029f23 300
mbed_official 324:406fd2029f23 301 /*!
mbed_official 324:406fd2029f23 302 * @name Constants and macros for entire I2C_C1 register
mbed_official 324:406fd2029f23 303 */
mbed_official 324:406fd2029f23 304 /*@{*/
mbed_official 324:406fd2029f23 305 #define HW_I2C_C1_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 306
mbed_official 324:406fd2029f23 307 #define HW_I2C_C1(x) (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
mbed_official 324:406fd2029f23 308 #define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U)
mbed_official 324:406fd2029f23 309 #define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v))
mbed_official 324:406fd2029f23 310 #define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) | (v)))
mbed_official 324:406fd2029f23 311 #define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 312 #define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 313 /*@}*/
mbed_official 324:406fd2029f23 314
mbed_official 324:406fd2029f23 315 /*
mbed_official 324:406fd2029f23 316 * Constants & macros for individual I2C_C1 bitfields
mbed_official 324:406fd2029f23 317 */
mbed_official 324:406fd2029f23 318
mbed_official 324:406fd2029f23 319 /*!
mbed_official 324:406fd2029f23 320 * @name Register I2C_C1, field DMAEN[0] (RW)
mbed_official 324:406fd2029f23 321 *
mbed_official 324:406fd2029f23 322 * Enables or disables the DMA function.
mbed_official 324:406fd2029f23 323 *
mbed_official 324:406fd2029f23 324 * Values:
mbed_official 324:406fd2029f23 325 * - 0 - All DMA signalling disabled.
mbed_official 324:406fd2029f23 326 * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
mbed_official 324:406fd2029f23 327 * trigger the DMA request: a data byte is received, and either address or
mbed_official 324:406fd2029f23 328 * data is transmitted. (ACK/NACK is automatic) the first byte received matches
mbed_official 324:406fd2029f23 329 * the A1 register or is a general call address. If any address matching
mbed_official 324:406fd2029f23 330 * occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
mbed_official 324:406fd2029f23 331 * from master to slave, then it is not required to check S[SRW]. With this
mbed_official 324:406fd2029f23 332 * assumption, DMA can also be used in this case. In other cases, if the master
mbed_official 324:406fd2029f23 333 * reads data from the slave, then it is required to rewrite the C1 register
mbed_official 324:406fd2029f23 334 * operation. With this assumption, DMA cannot be used. When FACK = 1, an
mbed_official 324:406fd2029f23 335 * address or a data byte is transmitted.
mbed_official 324:406fd2029f23 336 */
mbed_official 324:406fd2029f23 337 /*@{*/
mbed_official 324:406fd2029f23 338 #define BP_I2C_C1_DMAEN (0U) /*!< Bit position for I2C_C1_DMAEN. */
mbed_official 324:406fd2029f23 339 #define BM_I2C_C1_DMAEN (0x01U) /*!< Bit mask for I2C_C1_DMAEN. */
mbed_official 324:406fd2029f23 340 #define BS_I2C_C1_DMAEN (1U) /*!< Bit field size in bits for I2C_C1_DMAEN. */
mbed_official 324:406fd2029f23 341
mbed_official 324:406fd2029f23 342 /*! @brief Read current value of the I2C_C1_DMAEN field. */
mbed_official 324:406fd2029f23 343 #define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
mbed_official 324:406fd2029f23 344
mbed_official 324:406fd2029f23 345 /*! @brief Format value for bitfield I2C_C1_DMAEN. */
mbed_official 324:406fd2029f23 346 #define BF_I2C_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN)
mbed_official 324:406fd2029f23 347
mbed_official 324:406fd2029f23 348 /*! @brief Set the DMAEN field to a new value. */
mbed_official 324:406fd2029f23 349 #define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
mbed_official 324:406fd2029f23 350 /*@}*/
mbed_official 324:406fd2029f23 351
mbed_official 324:406fd2029f23 352 /*!
mbed_official 324:406fd2029f23 353 * @name Register I2C_C1, field WUEN[1] (RW)
mbed_official 324:406fd2029f23 354 *
mbed_official 324:406fd2029f23 355 * The I2C module can wake the MCU from low power mode with no peripheral bus
mbed_official 324:406fd2029f23 356 * running when slave address matching occurs.
mbed_official 324:406fd2029f23 357 *
mbed_official 324:406fd2029f23 358 * Values:
mbed_official 324:406fd2029f23 359 * - 0 - Normal operation. No interrupt generated when address matching in low
mbed_official 324:406fd2029f23 360 * power mode.
mbed_official 324:406fd2029f23 361 * - 1 - Enables the wakeup function in low power mode.
mbed_official 324:406fd2029f23 362 */
mbed_official 324:406fd2029f23 363 /*@{*/
mbed_official 324:406fd2029f23 364 #define BP_I2C_C1_WUEN (1U) /*!< Bit position for I2C_C1_WUEN. */
mbed_official 324:406fd2029f23 365 #define BM_I2C_C1_WUEN (0x02U) /*!< Bit mask for I2C_C1_WUEN. */
mbed_official 324:406fd2029f23 366 #define BS_I2C_C1_WUEN (1U) /*!< Bit field size in bits for I2C_C1_WUEN. */
mbed_official 324:406fd2029f23 367
mbed_official 324:406fd2029f23 368 /*! @brief Read current value of the I2C_C1_WUEN field. */
mbed_official 324:406fd2029f23 369 #define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
mbed_official 324:406fd2029f23 370
mbed_official 324:406fd2029f23 371 /*! @brief Format value for bitfield I2C_C1_WUEN. */
mbed_official 324:406fd2029f23 372 #define BF_I2C_C1_WUEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN)
mbed_official 324:406fd2029f23 373
mbed_official 324:406fd2029f23 374 /*! @brief Set the WUEN field to a new value. */
mbed_official 324:406fd2029f23 375 #define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
mbed_official 324:406fd2029f23 376 /*@}*/
mbed_official 324:406fd2029f23 377
mbed_official 324:406fd2029f23 378 /*!
mbed_official 324:406fd2029f23 379 * @name Register I2C_C1, field RSTA[2] (WORZ)
mbed_official 324:406fd2029f23 380 *
mbed_official 324:406fd2029f23 381 * Writing 1 to this bit generates a repeated START condition provided it is the
mbed_official 324:406fd2029f23 382 * current master. This bit will always be read as 0. Attempting a repeat at the
mbed_official 324:406fd2029f23 383 * wrong time results in loss of arbitration.
mbed_official 324:406fd2029f23 384 */
mbed_official 324:406fd2029f23 385 /*@{*/
mbed_official 324:406fd2029f23 386 #define BP_I2C_C1_RSTA (2U) /*!< Bit position for I2C_C1_RSTA. */
mbed_official 324:406fd2029f23 387 #define BM_I2C_C1_RSTA (0x04U) /*!< Bit mask for I2C_C1_RSTA. */
mbed_official 324:406fd2029f23 388 #define BS_I2C_C1_RSTA (1U) /*!< Bit field size in bits for I2C_C1_RSTA. */
mbed_official 324:406fd2029f23 389
mbed_official 324:406fd2029f23 390 /*! @brief Format value for bitfield I2C_C1_RSTA. */
mbed_official 324:406fd2029f23 391 #define BF_I2C_C1_RSTA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA)
mbed_official 324:406fd2029f23 392
mbed_official 324:406fd2029f23 393 /*! @brief Set the RSTA field to a new value. */
mbed_official 324:406fd2029f23 394 #define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
mbed_official 324:406fd2029f23 395 /*@}*/
mbed_official 324:406fd2029f23 396
mbed_official 324:406fd2029f23 397 /*!
mbed_official 324:406fd2029f23 398 * @name Register I2C_C1, field TXAK[3] (RW)
mbed_official 324:406fd2029f23 399 *
mbed_official 324:406fd2029f23 400 * Specifies the value driven onto the SDA during data acknowledge cycles for
mbed_official 324:406fd2029f23 401 * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
mbed_official 324:406fd2029f23 402 * generation. SCL is held low until TXAK is written.
mbed_official 324:406fd2029f23 403 *
mbed_official 324:406fd2029f23 404 * Values:
mbed_official 324:406fd2029f23 405 * - 0 - An acknowledge signal is sent to the bus on the following receiving
mbed_official 324:406fd2029f23 406 * byte (if FACK is cleared) or the current receiving byte (if FACK is set).
mbed_official 324:406fd2029f23 407 * - 1 - No acknowledge signal is sent to the bus on the following receiving
mbed_official 324:406fd2029f23 408 * data byte (if FACK is cleared) or the current receiving data byte (if FACK is
mbed_official 324:406fd2029f23 409 * set).
mbed_official 324:406fd2029f23 410 */
mbed_official 324:406fd2029f23 411 /*@{*/
mbed_official 324:406fd2029f23 412 #define BP_I2C_C1_TXAK (3U) /*!< Bit position for I2C_C1_TXAK. */
mbed_official 324:406fd2029f23 413 #define BM_I2C_C1_TXAK (0x08U) /*!< Bit mask for I2C_C1_TXAK. */
mbed_official 324:406fd2029f23 414 #define BS_I2C_C1_TXAK (1U) /*!< Bit field size in bits for I2C_C1_TXAK. */
mbed_official 324:406fd2029f23 415
mbed_official 324:406fd2029f23 416 /*! @brief Read current value of the I2C_C1_TXAK field. */
mbed_official 324:406fd2029f23 417 #define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
mbed_official 324:406fd2029f23 418
mbed_official 324:406fd2029f23 419 /*! @brief Format value for bitfield I2C_C1_TXAK. */
mbed_official 324:406fd2029f23 420 #define BF_I2C_C1_TXAK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK)
mbed_official 324:406fd2029f23 421
mbed_official 324:406fd2029f23 422 /*! @brief Set the TXAK field to a new value. */
mbed_official 324:406fd2029f23 423 #define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
mbed_official 324:406fd2029f23 424 /*@}*/
mbed_official 324:406fd2029f23 425
mbed_official 324:406fd2029f23 426 /*!
mbed_official 324:406fd2029f23 427 * @name Register I2C_C1, field TX[4] (RW)
mbed_official 324:406fd2029f23 428 *
mbed_official 324:406fd2029f23 429 * Selects the direction of master and slave transfers. In master mode this bit
mbed_official 324:406fd2029f23 430 * must be set according to the type of transfer required. Therefore, for address
mbed_official 324:406fd2029f23 431 * cycles, this bit is always set. When addressed as a slave this bit must be
mbed_official 324:406fd2029f23 432 * set by software according to the SRW bit in the status register.
mbed_official 324:406fd2029f23 433 *
mbed_official 324:406fd2029f23 434 * Values:
mbed_official 324:406fd2029f23 435 * - 0 - Receive
mbed_official 324:406fd2029f23 436 * - 1 - Transmit
mbed_official 324:406fd2029f23 437 */
mbed_official 324:406fd2029f23 438 /*@{*/
mbed_official 324:406fd2029f23 439 #define BP_I2C_C1_TX (4U) /*!< Bit position for I2C_C1_TX. */
mbed_official 324:406fd2029f23 440 #define BM_I2C_C1_TX (0x10U) /*!< Bit mask for I2C_C1_TX. */
mbed_official 324:406fd2029f23 441 #define BS_I2C_C1_TX (1U) /*!< Bit field size in bits for I2C_C1_TX. */
mbed_official 324:406fd2029f23 442
mbed_official 324:406fd2029f23 443 /*! @brief Read current value of the I2C_C1_TX field. */
mbed_official 324:406fd2029f23 444 #define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
mbed_official 324:406fd2029f23 445
mbed_official 324:406fd2029f23 446 /*! @brief Format value for bitfield I2C_C1_TX. */
mbed_official 324:406fd2029f23 447 #define BF_I2C_C1_TX(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX)
mbed_official 324:406fd2029f23 448
mbed_official 324:406fd2029f23 449 /*! @brief Set the TX field to a new value. */
mbed_official 324:406fd2029f23 450 #define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
mbed_official 324:406fd2029f23 451 /*@}*/
mbed_official 324:406fd2029f23 452
mbed_official 324:406fd2029f23 453 /*!
mbed_official 324:406fd2029f23 454 * @name Register I2C_C1, field MST[5] (RW)
mbed_official 324:406fd2029f23 455 *
mbed_official 324:406fd2029f23 456 * When MST is changed from 0 to 1, a START signal is generated on the bus and
mbed_official 324:406fd2029f23 457 * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
mbed_official 324:406fd2029f23 458 * generated and the mode of operation changes from master to slave.
mbed_official 324:406fd2029f23 459 *
mbed_official 324:406fd2029f23 460 * Values:
mbed_official 324:406fd2029f23 461 * - 0 - Slave mode
mbed_official 324:406fd2029f23 462 * - 1 - Master mode
mbed_official 324:406fd2029f23 463 */
mbed_official 324:406fd2029f23 464 /*@{*/
mbed_official 324:406fd2029f23 465 #define BP_I2C_C1_MST (5U) /*!< Bit position for I2C_C1_MST. */
mbed_official 324:406fd2029f23 466 #define BM_I2C_C1_MST (0x20U) /*!< Bit mask for I2C_C1_MST. */
mbed_official 324:406fd2029f23 467 #define BS_I2C_C1_MST (1U) /*!< Bit field size in bits for I2C_C1_MST. */
mbed_official 324:406fd2029f23 468
mbed_official 324:406fd2029f23 469 /*! @brief Read current value of the I2C_C1_MST field. */
mbed_official 324:406fd2029f23 470 #define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
mbed_official 324:406fd2029f23 471
mbed_official 324:406fd2029f23 472 /*! @brief Format value for bitfield I2C_C1_MST. */
mbed_official 324:406fd2029f23 473 #define BF_I2C_C1_MST(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST)
mbed_official 324:406fd2029f23 474
mbed_official 324:406fd2029f23 475 /*! @brief Set the MST field to a new value. */
mbed_official 324:406fd2029f23 476 #define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
mbed_official 324:406fd2029f23 477 /*@}*/
mbed_official 324:406fd2029f23 478
mbed_official 324:406fd2029f23 479 /*!
mbed_official 324:406fd2029f23 480 * @name Register I2C_C1, field IICIE[6] (RW)
mbed_official 324:406fd2029f23 481 *
mbed_official 324:406fd2029f23 482 * Enables I2C interrupt requests.
mbed_official 324:406fd2029f23 483 *
mbed_official 324:406fd2029f23 484 * Values:
mbed_official 324:406fd2029f23 485 * - 0 - Disabled
mbed_official 324:406fd2029f23 486 * - 1 - Enabled
mbed_official 324:406fd2029f23 487 */
mbed_official 324:406fd2029f23 488 /*@{*/
mbed_official 324:406fd2029f23 489 #define BP_I2C_C1_IICIE (6U) /*!< Bit position for I2C_C1_IICIE. */
mbed_official 324:406fd2029f23 490 #define BM_I2C_C1_IICIE (0x40U) /*!< Bit mask for I2C_C1_IICIE. */
mbed_official 324:406fd2029f23 491 #define BS_I2C_C1_IICIE (1U) /*!< Bit field size in bits for I2C_C1_IICIE. */
mbed_official 324:406fd2029f23 492
mbed_official 324:406fd2029f23 493 /*! @brief Read current value of the I2C_C1_IICIE field. */
mbed_official 324:406fd2029f23 494 #define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
mbed_official 324:406fd2029f23 495
mbed_official 324:406fd2029f23 496 /*! @brief Format value for bitfield I2C_C1_IICIE. */
mbed_official 324:406fd2029f23 497 #define BF_I2C_C1_IICIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE)
mbed_official 324:406fd2029f23 498
mbed_official 324:406fd2029f23 499 /*! @brief Set the IICIE field to a new value. */
mbed_official 324:406fd2029f23 500 #define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
mbed_official 324:406fd2029f23 501 /*@}*/
mbed_official 324:406fd2029f23 502
mbed_official 324:406fd2029f23 503 /*!
mbed_official 324:406fd2029f23 504 * @name Register I2C_C1, field IICEN[7] (RW)
mbed_official 324:406fd2029f23 505 *
mbed_official 324:406fd2029f23 506 * Enables I2C module operation.
mbed_official 324:406fd2029f23 507 *
mbed_official 324:406fd2029f23 508 * Values:
mbed_official 324:406fd2029f23 509 * - 0 - Disabled
mbed_official 324:406fd2029f23 510 * - 1 - Enabled
mbed_official 324:406fd2029f23 511 */
mbed_official 324:406fd2029f23 512 /*@{*/
mbed_official 324:406fd2029f23 513 #define BP_I2C_C1_IICEN (7U) /*!< Bit position for I2C_C1_IICEN. */
mbed_official 324:406fd2029f23 514 #define BM_I2C_C1_IICEN (0x80U) /*!< Bit mask for I2C_C1_IICEN. */
mbed_official 324:406fd2029f23 515 #define BS_I2C_C1_IICEN (1U) /*!< Bit field size in bits for I2C_C1_IICEN. */
mbed_official 324:406fd2029f23 516
mbed_official 324:406fd2029f23 517 /*! @brief Read current value of the I2C_C1_IICEN field. */
mbed_official 324:406fd2029f23 518 #define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
mbed_official 324:406fd2029f23 519
mbed_official 324:406fd2029f23 520 /*! @brief Format value for bitfield I2C_C1_IICEN. */
mbed_official 324:406fd2029f23 521 #define BF_I2C_C1_IICEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN)
mbed_official 324:406fd2029f23 522
mbed_official 324:406fd2029f23 523 /*! @brief Set the IICEN field to a new value. */
mbed_official 324:406fd2029f23 524 #define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
mbed_official 324:406fd2029f23 525 /*@}*/
mbed_official 324:406fd2029f23 526
mbed_official 324:406fd2029f23 527 /*******************************************************************************
mbed_official 324:406fd2029f23 528 * HW_I2C_S - I2C Status register
mbed_official 324:406fd2029f23 529 ******************************************************************************/
mbed_official 324:406fd2029f23 530
mbed_official 324:406fd2029f23 531 /*!
mbed_official 324:406fd2029f23 532 * @brief HW_I2C_S - I2C Status register (RW)
mbed_official 324:406fd2029f23 533 *
mbed_official 324:406fd2029f23 534 * Reset value: 0x80U
mbed_official 324:406fd2029f23 535 */
mbed_official 324:406fd2029f23 536 typedef union _hw_i2c_s
mbed_official 324:406fd2029f23 537 {
mbed_official 324:406fd2029f23 538 uint8_t U;
mbed_official 324:406fd2029f23 539 struct _hw_i2c_s_bitfields
mbed_official 324:406fd2029f23 540 {
mbed_official 324:406fd2029f23 541 uint8_t RXAK : 1; /*!< [0] Receive Acknowledge */
mbed_official 324:406fd2029f23 542 uint8_t IICIF : 1; /*!< [1] Interrupt Flag */
mbed_official 324:406fd2029f23 543 uint8_t SRW : 1; /*!< [2] Slave Read/Write */
mbed_official 324:406fd2029f23 544 uint8_t RAM : 1; /*!< [3] Range Address Match */
mbed_official 324:406fd2029f23 545 uint8_t ARBL : 1; /*!< [4] Arbitration Lost */
mbed_official 324:406fd2029f23 546 uint8_t BUSY : 1; /*!< [5] Bus Busy */
mbed_official 324:406fd2029f23 547 uint8_t IAAS : 1; /*!< [6] Addressed As A Slave */
mbed_official 324:406fd2029f23 548 uint8_t TCF : 1; /*!< [7] Transfer Complete Flag */
mbed_official 324:406fd2029f23 549 } B;
mbed_official 324:406fd2029f23 550 } hw_i2c_s_t;
mbed_official 324:406fd2029f23 551
mbed_official 324:406fd2029f23 552 /*!
mbed_official 324:406fd2029f23 553 * @name Constants and macros for entire I2C_S register
mbed_official 324:406fd2029f23 554 */
mbed_official 324:406fd2029f23 555 /*@{*/
mbed_official 324:406fd2029f23 556 #define HW_I2C_S_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 557
mbed_official 324:406fd2029f23 558 #define HW_I2C_S(x) (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
mbed_official 324:406fd2029f23 559 #define HW_I2C_S_RD(x) (HW_I2C_S(x).U)
mbed_official 324:406fd2029f23 560 #define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v))
mbed_official 324:406fd2029f23 561 #define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) | (v)))
mbed_official 324:406fd2029f23 562 #define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 563 #define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 564 /*@}*/
mbed_official 324:406fd2029f23 565
mbed_official 324:406fd2029f23 566 /*
mbed_official 324:406fd2029f23 567 * Constants & macros for individual I2C_S bitfields
mbed_official 324:406fd2029f23 568 */
mbed_official 324:406fd2029f23 569
mbed_official 324:406fd2029f23 570 /*!
mbed_official 324:406fd2029f23 571 * @name Register I2C_S, field RXAK[0] (RO)
mbed_official 324:406fd2029f23 572 *
mbed_official 324:406fd2029f23 573 * Values:
mbed_official 324:406fd2029f23 574 * - 0 - Acknowledge signal was received after the completion of one byte of
mbed_official 324:406fd2029f23 575 * data transmission on the bus
mbed_official 324:406fd2029f23 576 * - 1 - No acknowledge signal detected
mbed_official 324:406fd2029f23 577 */
mbed_official 324:406fd2029f23 578 /*@{*/
mbed_official 324:406fd2029f23 579 #define BP_I2C_S_RXAK (0U) /*!< Bit position for I2C_S_RXAK. */
mbed_official 324:406fd2029f23 580 #define BM_I2C_S_RXAK (0x01U) /*!< Bit mask for I2C_S_RXAK. */
mbed_official 324:406fd2029f23 581 #define BS_I2C_S_RXAK (1U) /*!< Bit field size in bits for I2C_S_RXAK. */
mbed_official 324:406fd2029f23 582
mbed_official 324:406fd2029f23 583 /*! @brief Read current value of the I2C_S_RXAK field. */
mbed_official 324:406fd2029f23 584 #define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
mbed_official 324:406fd2029f23 585 /*@}*/
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /*!
mbed_official 324:406fd2029f23 588 * @name Register I2C_S, field IICIF[1] (W1C)
mbed_official 324:406fd2029f23 589 *
mbed_official 324:406fd2029f23 590 * This bit sets when an interrupt is pending. This bit must be cleared by
mbed_official 324:406fd2029f23 591 * software by writing 1 to it, such as in the interrupt routine. One of the following
mbed_official 324:406fd2029f23 592 * events can set this bit: One byte transfer, including ACK/NACK bit, completes
mbed_official 324:406fd2029f23 593 * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
mbed_official 324:406fd2029f23 594 * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
mbed_official 324:406fd2029f23 595 * completes if FACK is 1. Match of slave address to calling address including
mbed_official 324:406fd2029f23 596 * primary slave address, range slave address , alert response address, second
mbed_official 324:406fd2029f23 597 * slave address, or general call address. Arbitration lost In SMBus mode, any
mbed_official 324:406fd2029f23 598 * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
mbed_official 324:406fd2029f23 599 * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
mbed_official 324:406fd2029f23 600 * start detection interrupt: In the interrupt service routine, first clear the
mbed_official 324:406fd2029f23 601 * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
mbed_official 324:406fd2029f23 602 * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
mbed_official 324:406fd2029f23 603 * asserted again.
mbed_official 324:406fd2029f23 604 *
mbed_official 324:406fd2029f23 605 * Values:
mbed_official 324:406fd2029f23 606 * - 0 - No interrupt pending
mbed_official 324:406fd2029f23 607 * - 1 - Interrupt pending
mbed_official 324:406fd2029f23 608 */
mbed_official 324:406fd2029f23 609 /*@{*/
mbed_official 324:406fd2029f23 610 #define BP_I2C_S_IICIF (1U) /*!< Bit position for I2C_S_IICIF. */
mbed_official 324:406fd2029f23 611 #define BM_I2C_S_IICIF (0x02U) /*!< Bit mask for I2C_S_IICIF. */
mbed_official 324:406fd2029f23 612 #define BS_I2C_S_IICIF (1U) /*!< Bit field size in bits for I2C_S_IICIF. */
mbed_official 324:406fd2029f23 613
mbed_official 324:406fd2029f23 614 /*! @brief Read current value of the I2C_S_IICIF field. */
mbed_official 324:406fd2029f23 615 #define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
mbed_official 324:406fd2029f23 616
mbed_official 324:406fd2029f23 617 /*! @brief Format value for bitfield I2C_S_IICIF. */
mbed_official 324:406fd2029f23 618 #define BF_I2C_S_IICIF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF)
mbed_official 324:406fd2029f23 619
mbed_official 324:406fd2029f23 620 /*! @brief Set the IICIF field to a new value. */
mbed_official 324:406fd2029f23 621 #define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
mbed_official 324:406fd2029f23 622 /*@}*/
mbed_official 324:406fd2029f23 623
mbed_official 324:406fd2029f23 624 /*!
mbed_official 324:406fd2029f23 625 * @name Register I2C_S, field SRW[2] (RO)
mbed_official 324:406fd2029f23 626 *
mbed_official 324:406fd2029f23 627 * When addressed as a slave, SRW indicates the value of the R/W command bit of
mbed_official 324:406fd2029f23 628 * the calling address sent to the master.
mbed_official 324:406fd2029f23 629 *
mbed_official 324:406fd2029f23 630 * Values:
mbed_official 324:406fd2029f23 631 * - 0 - Slave receive, master writing to slave
mbed_official 324:406fd2029f23 632 * - 1 - Slave transmit, master reading from slave
mbed_official 324:406fd2029f23 633 */
mbed_official 324:406fd2029f23 634 /*@{*/
mbed_official 324:406fd2029f23 635 #define BP_I2C_S_SRW (2U) /*!< Bit position for I2C_S_SRW. */
mbed_official 324:406fd2029f23 636 #define BM_I2C_S_SRW (0x04U) /*!< Bit mask for I2C_S_SRW. */
mbed_official 324:406fd2029f23 637 #define BS_I2C_S_SRW (1U) /*!< Bit field size in bits for I2C_S_SRW. */
mbed_official 324:406fd2029f23 638
mbed_official 324:406fd2029f23 639 /*! @brief Read current value of the I2C_S_SRW field. */
mbed_official 324:406fd2029f23 640 #define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
mbed_official 324:406fd2029f23 641 /*@}*/
mbed_official 324:406fd2029f23 642
mbed_official 324:406fd2029f23 643 /*!
mbed_official 324:406fd2029f23 644 * @name Register I2C_S, field RAM[3] (RW)
mbed_official 324:406fd2029f23 645 *
mbed_official 324:406fd2029f23 646 * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
mbed_official 324:406fd2029f23 647 * Any nonzero calling address is received that matches the address in the RA
mbed_official 324:406fd2029f23 648 * register. The calling address is within the range of values of the A1 and RA
mbed_official 324:406fd2029f23 649 * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
mbed_official 324:406fd2029f23 650 * Writing the C1 register with any value clears this bit to 0.
mbed_official 324:406fd2029f23 651 *
mbed_official 324:406fd2029f23 652 * Values:
mbed_official 324:406fd2029f23 653 * - 0 - Not addressed
mbed_official 324:406fd2029f23 654 * - 1 - Addressed as a slave
mbed_official 324:406fd2029f23 655 */
mbed_official 324:406fd2029f23 656 /*@{*/
mbed_official 324:406fd2029f23 657 #define BP_I2C_S_RAM (3U) /*!< Bit position for I2C_S_RAM. */
mbed_official 324:406fd2029f23 658 #define BM_I2C_S_RAM (0x08U) /*!< Bit mask for I2C_S_RAM. */
mbed_official 324:406fd2029f23 659 #define BS_I2C_S_RAM (1U) /*!< Bit field size in bits for I2C_S_RAM. */
mbed_official 324:406fd2029f23 660
mbed_official 324:406fd2029f23 661 /*! @brief Read current value of the I2C_S_RAM field. */
mbed_official 324:406fd2029f23 662 #define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
mbed_official 324:406fd2029f23 663
mbed_official 324:406fd2029f23 664 /*! @brief Format value for bitfield I2C_S_RAM. */
mbed_official 324:406fd2029f23 665 #define BF_I2C_S_RAM(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM)
mbed_official 324:406fd2029f23 666
mbed_official 324:406fd2029f23 667 /*! @brief Set the RAM field to a new value. */
mbed_official 324:406fd2029f23 668 #define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
mbed_official 324:406fd2029f23 669 /*@}*/
mbed_official 324:406fd2029f23 670
mbed_official 324:406fd2029f23 671 /*!
mbed_official 324:406fd2029f23 672 * @name Register I2C_S, field ARBL[4] (W1C)
mbed_official 324:406fd2029f23 673 *
mbed_official 324:406fd2029f23 674 * This bit is set by hardware when the arbitration procedure is lost. The ARBL
mbed_official 324:406fd2029f23 675 * bit must be cleared by software, by writing 1 to it.
mbed_official 324:406fd2029f23 676 *
mbed_official 324:406fd2029f23 677 * Values:
mbed_official 324:406fd2029f23 678 * - 0 - Standard bus operation.
mbed_official 324:406fd2029f23 679 * - 1 - Loss of arbitration.
mbed_official 324:406fd2029f23 680 */
mbed_official 324:406fd2029f23 681 /*@{*/
mbed_official 324:406fd2029f23 682 #define BP_I2C_S_ARBL (4U) /*!< Bit position for I2C_S_ARBL. */
mbed_official 324:406fd2029f23 683 #define BM_I2C_S_ARBL (0x10U) /*!< Bit mask for I2C_S_ARBL. */
mbed_official 324:406fd2029f23 684 #define BS_I2C_S_ARBL (1U) /*!< Bit field size in bits for I2C_S_ARBL. */
mbed_official 324:406fd2029f23 685
mbed_official 324:406fd2029f23 686 /*! @brief Read current value of the I2C_S_ARBL field. */
mbed_official 324:406fd2029f23 687 #define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
mbed_official 324:406fd2029f23 688
mbed_official 324:406fd2029f23 689 /*! @brief Format value for bitfield I2C_S_ARBL. */
mbed_official 324:406fd2029f23 690 #define BF_I2C_S_ARBL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL)
mbed_official 324:406fd2029f23 691
mbed_official 324:406fd2029f23 692 /*! @brief Set the ARBL field to a new value. */
mbed_official 324:406fd2029f23 693 #define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
mbed_official 324:406fd2029f23 694 /*@}*/
mbed_official 324:406fd2029f23 695
mbed_official 324:406fd2029f23 696 /*!
mbed_official 324:406fd2029f23 697 * @name Register I2C_S, field BUSY[5] (RO)
mbed_official 324:406fd2029f23 698 *
mbed_official 324:406fd2029f23 699 * Indicates the status of the bus regardless of slave or master mode. This bit
mbed_official 324:406fd2029f23 700 * is set when a START signal is detected and cleared when a STOP signal is
mbed_official 324:406fd2029f23 701 * detected.
mbed_official 324:406fd2029f23 702 *
mbed_official 324:406fd2029f23 703 * Values:
mbed_official 324:406fd2029f23 704 * - 0 - Bus is idle
mbed_official 324:406fd2029f23 705 * - 1 - Bus is busy
mbed_official 324:406fd2029f23 706 */
mbed_official 324:406fd2029f23 707 /*@{*/
mbed_official 324:406fd2029f23 708 #define BP_I2C_S_BUSY (5U) /*!< Bit position for I2C_S_BUSY. */
mbed_official 324:406fd2029f23 709 #define BM_I2C_S_BUSY (0x20U) /*!< Bit mask for I2C_S_BUSY. */
mbed_official 324:406fd2029f23 710 #define BS_I2C_S_BUSY (1U) /*!< Bit field size in bits for I2C_S_BUSY. */
mbed_official 324:406fd2029f23 711
mbed_official 324:406fd2029f23 712 /*! @brief Read current value of the I2C_S_BUSY field. */
mbed_official 324:406fd2029f23 713 #define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
mbed_official 324:406fd2029f23 714 /*@}*/
mbed_official 324:406fd2029f23 715
mbed_official 324:406fd2029f23 716 /*!
mbed_official 324:406fd2029f23 717 * @name Register I2C_S, field IAAS[6] (RW)
mbed_official 324:406fd2029f23 718 *
mbed_official 324:406fd2029f23 719 * This bit is set by one of the following conditions: The calling address
mbed_official 324:406fd2029f23 720 * matches the programmed primary slave address in the A1 register, or matches the
mbed_official 324:406fd2029f23 721 * range address in the RA register (which must be set to a nonzero value and under
mbed_official 324:406fd2029f23 722 * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
mbed_official 324:406fd2029f23 723 * received. SMB[SIICAEN] is set and the calling address matches the second programmed
mbed_official 324:406fd2029f23 724 * slave address. ALERTEN is set and an SMBus alert response address is received
mbed_official 324:406fd2029f23 725 * RMEN is set and an address is received that is within the range between the
mbed_official 324:406fd2029f23 726 * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
mbed_official 324:406fd2029f23 727 * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
mbed_official 324:406fd2029f23 728 * value clears this bit.
mbed_official 324:406fd2029f23 729 *
mbed_official 324:406fd2029f23 730 * Values:
mbed_official 324:406fd2029f23 731 * - 0 - Not addressed
mbed_official 324:406fd2029f23 732 * - 1 - Addressed as a slave
mbed_official 324:406fd2029f23 733 */
mbed_official 324:406fd2029f23 734 /*@{*/
mbed_official 324:406fd2029f23 735 #define BP_I2C_S_IAAS (6U) /*!< Bit position for I2C_S_IAAS. */
mbed_official 324:406fd2029f23 736 #define BM_I2C_S_IAAS (0x40U) /*!< Bit mask for I2C_S_IAAS. */
mbed_official 324:406fd2029f23 737 #define BS_I2C_S_IAAS (1U) /*!< Bit field size in bits for I2C_S_IAAS. */
mbed_official 324:406fd2029f23 738
mbed_official 324:406fd2029f23 739 /*! @brief Read current value of the I2C_S_IAAS field. */
mbed_official 324:406fd2029f23 740 #define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
mbed_official 324:406fd2029f23 741
mbed_official 324:406fd2029f23 742 /*! @brief Format value for bitfield I2C_S_IAAS. */
mbed_official 324:406fd2029f23 743 #define BF_I2C_S_IAAS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS)
mbed_official 324:406fd2029f23 744
mbed_official 324:406fd2029f23 745 /*! @brief Set the IAAS field to a new value. */
mbed_official 324:406fd2029f23 746 #define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
mbed_official 324:406fd2029f23 747 /*@}*/
mbed_official 324:406fd2029f23 748
mbed_official 324:406fd2029f23 749 /*!
mbed_official 324:406fd2029f23 750 * @name Register I2C_S, field TCF[7] (RO)
mbed_official 324:406fd2029f23 751 *
mbed_official 324:406fd2029f23 752 * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
mbed_official 324:406fd2029f23 753 * This bit is valid only during or immediately following a transfer to or from
mbed_official 324:406fd2029f23 754 * the I2C module. TCF is cleared by reading the I2C data register in receive mode
mbed_official 324:406fd2029f23 755 * or by writing to the I2C data register in transmit mode.
mbed_official 324:406fd2029f23 756 *
mbed_official 324:406fd2029f23 757 * Values:
mbed_official 324:406fd2029f23 758 * - 0 - Transfer in progress
mbed_official 324:406fd2029f23 759 * - 1 - Transfer complete
mbed_official 324:406fd2029f23 760 */
mbed_official 324:406fd2029f23 761 /*@{*/
mbed_official 324:406fd2029f23 762 #define BP_I2C_S_TCF (7U) /*!< Bit position for I2C_S_TCF. */
mbed_official 324:406fd2029f23 763 #define BM_I2C_S_TCF (0x80U) /*!< Bit mask for I2C_S_TCF. */
mbed_official 324:406fd2029f23 764 #define BS_I2C_S_TCF (1U) /*!< Bit field size in bits for I2C_S_TCF. */
mbed_official 324:406fd2029f23 765
mbed_official 324:406fd2029f23 766 /*! @brief Read current value of the I2C_S_TCF field. */
mbed_official 324:406fd2029f23 767 #define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
mbed_official 324:406fd2029f23 768 /*@}*/
mbed_official 324:406fd2029f23 769
mbed_official 324:406fd2029f23 770 /*******************************************************************************
mbed_official 324:406fd2029f23 771 * HW_I2C_D - I2C Data I/O register
mbed_official 324:406fd2029f23 772 ******************************************************************************/
mbed_official 324:406fd2029f23 773
mbed_official 324:406fd2029f23 774 /*!
mbed_official 324:406fd2029f23 775 * @brief HW_I2C_D - I2C Data I/O register (RW)
mbed_official 324:406fd2029f23 776 *
mbed_official 324:406fd2029f23 777 * Reset value: 0x00U
mbed_official 324:406fd2029f23 778 */
mbed_official 324:406fd2029f23 779 typedef union _hw_i2c_d
mbed_official 324:406fd2029f23 780 {
mbed_official 324:406fd2029f23 781 uint8_t U;
mbed_official 324:406fd2029f23 782 struct _hw_i2c_d_bitfields
mbed_official 324:406fd2029f23 783 {
mbed_official 324:406fd2029f23 784 uint8_t DATA : 8; /*!< [7:0] Data */
mbed_official 324:406fd2029f23 785 } B;
mbed_official 324:406fd2029f23 786 } hw_i2c_d_t;
mbed_official 324:406fd2029f23 787
mbed_official 324:406fd2029f23 788 /*!
mbed_official 324:406fd2029f23 789 * @name Constants and macros for entire I2C_D register
mbed_official 324:406fd2029f23 790 */
mbed_official 324:406fd2029f23 791 /*@{*/
mbed_official 324:406fd2029f23 792 #define HW_I2C_D_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 793
mbed_official 324:406fd2029f23 794 #define HW_I2C_D(x) (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
mbed_official 324:406fd2029f23 795 #define HW_I2C_D_RD(x) (HW_I2C_D(x).U)
mbed_official 324:406fd2029f23 796 #define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v))
mbed_official 324:406fd2029f23 797 #define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) | (v)))
mbed_official 324:406fd2029f23 798 #define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 799 #define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 800 /*@}*/
mbed_official 324:406fd2029f23 801
mbed_official 324:406fd2029f23 802 /*
mbed_official 324:406fd2029f23 803 * Constants & macros for individual I2C_D bitfields
mbed_official 324:406fd2029f23 804 */
mbed_official 324:406fd2029f23 805
mbed_official 324:406fd2029f23 806 /*!
mbed_official 324:406fd2029f23 807 * @name Register I2C_D, field DATA[7:0] (RW)
mbed_official 324:406fd2029f23 808 *
mbed_official 324:406fd2029f23 809 * In master transmit mode, when data is written to this register, a data
mbed_official 324:406fd2029f23 810 * transfer is initiated. The most significant bit is sent first. In master receive
mbed_official 324:406fd2029f23 811 * mode, reading this register initiates receiving of the next byte of data. When
mbed_official 324:406fd2029f23 812 * making the transition out of master receive mode, switch the I2C mode before
mbed_official 324:406fd2029f23 813 * reading the Data register to prevent an inadvertent initiation of a master
mbed_official 324:406fd2029f23 814 * receive data transfer. In slave mode, the same functions are available after an
mbed_official 324:406fd2029f23 815 * address match occurs. The C1[TX] bit must correctly reflect the desired direction
mbed_official 324:406fd2029f23 816 * of transfer in master and slave modes for the transmission to begin. For
mbed_official 324:406fd2029f23 817 * example, if the I2C module is configured for master transmit but a master receive
mbed_official 324:406fd2029f23 818 * is desired, reading the Data register does not initiate the receive. Reading
mbed_official 324:406fd2029f23 819 * the Data register returns the last byte received while the I2C module is
mbed_official 324:406fd2029f23 820 * configured in master receive or slave receive mode. The Data register does not
mbed_official 324:406fd2029f23 821 * reflect every byte that is transmitted on the I2C bus, and neither can software
mbed_official 324:406fd2029f23 822 * verify that a byte has been written to the Data register correctly by reading it
mbed_official 324:406fd2029f23 823 * back. In master transmit mode, the first byte of data written to the Data
mbed_official 324:406fd2029f23 824 * register following assertion of MST (start bit) or assertion of RSTA (repeated
mbed_official 324:406fd2029f23 825 * start bit) is used for the address transfer and must consist of the calling
mbed_official 324:406fd2029f23 826 * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
mbed_official 324:406fd2029f23 827 */
mbed_official 324:406fd2029f23 828 /*@{*/
mbed_official 324:406fd2029f23 829 #define BP_I2C_D_DATA (0U) /*!< Bit position for I2C_D_DATA. */
mbed_official 324:406fd2029f23 830 #define BM_I2C_D_DATA (0xFFU) /*!< Bit mask for I2C_D_DATA. */
mbed_official 324:406fd2029f23 831 #define BS_I2C_D_DATA (8U) /*!< Bit field size in bits for I2C_D_DATA. */
mbed_official 324:406fd2029f23 832
mbed_official 324:406fd2029f23 833 /*! @brief Read current value of the I2C_D_DATA field. */
mbed_official 324:406fd2029f23 834 #define BR_I2C_D_DATA(x) (HW_I2C_D(x).U)
mbed_official 324:406fd2029f23 835
mbed_official 324:406fd2029f23 836 /*! @brief Format value for bitfield I2C_D_DATA. */
mbed_official 324:406fd2029f23 837 #define BF_I2C_D_DATA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA)
mbed_official 324:406fd2029f23 838
mbed_official 324:406fd2029f23 839 /*! @brief Set the DATA field to a new value. */
mbed_official 324:406fd2029f23 840 #define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v))
mbed_official 324:406fd2029f23 841 /*@}*/
mbed_official 324:406fd2029f23 842
mbed_official 324:406fd2029f23 843 /*******************************************************************************
mbed_official 324:406fd2029f23 844 * HW_I2C_C2 - I2C Control Register 2
mbed_official 324:406fd2029f23 845 ******************************************************************************/
mbed_official 324:406fd2029f23 846
mbed_official 324:406fd2029f23 847 /*!
mbed_official 324:406fd2029f23 848 * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
mbed_official 324:406fd2029f23 849 *
mbed_official 324:406fd2029f23 850 * Reset value: 0x00U
mbed_official 324:406fd2029f23 851 */
mbed_official 324:406fd2029f23 852 typedef union _hw_i2c_c2
mbed_official 324:406fd2029f23 853 {
mbed_official 324:406fd2029f23 854 uint8_t U;
mbed_official 324:406fd2029f23 855 struct _hw_i2c_c2_bitfields
mbed_official 324:406fd2029f23 856 {
mbed_official 324:406fd2029f23 857 uint8_t AD : 3; /*!< [2:0] Slave Address */
mbed_official 324:406fd2029f23 858 uint8_t RMEN : 1; /*!< [3] Range Address Matching Enable */
mbed_official 324:406fd2029f23 859 uint8_t SBRC : 1; /*!< [4] Slave Baud Rate Control */
mbed_official 324:406fd2029f23 860 uint8_t HDRS : 1; /*!< [5] High Drive Select */
mbed_official 324:406fd2029f23 861 uint8_t ADEXT : 1; /*!< [6] Address Extension */
mbed_official 324:406fd2029f23 862 uint8_t GCAEN : 1; /*!< [7] General Call Address Enable */
mbed_official 324:406fd2029f23 863 } B;
mbed_official 324:406fd2029f23 864 } hw_i2c_c2_t;
mbed_official 324:406fd2029f23 865
mbed_official 324:406fd2029f23 866 /*!
mbed_official 324:406fd2029f23 867 * @name Constants and macros for entire I2C_C2 register
mbed_official 324:406fd2029f23 868 */
mbed_official 324:406fd2029f23 869 /*@{*/
mbed_official 324:406fd2029f23 870 #define HW_I2C_C2_ADDR(x) ((x) + 0x5U)
mbed_official 324:406fd2029f23 871
mbed_official 324:406fd2029f23 872 #define HW_I2C_C2(x) (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
mbed_official 324:406fd2029f23 873 #define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U)
mbed_official 324:406fd2029f23 874 #define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v))
mbed_official 324:406fd2029f23 875 #define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) | (v)))
mbed_official 324:406fd2029f23 876 #define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 877 #define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 878 /*@}*/
mbed_official 324:406fd2029f23 879
mbed_official 324:406fd2029f23 880 /*
mbed_official 324:406fd2029f23 881 * Constants & macros for individual I2C_C2 bitfields
mbed_official 324:406fd2029f23 882 */
mbed_official 324:406fd2029f23 883
mbed_official 324:406fd2029f23 884 /*!
mbed_official 324:406fd2029f23 885 * @name Register I2C_C2, field AD[2:0] (RW)
mbed_official 324:406fd2029f23 886 *
mbed_official 324:406fd2029f23 887 * Contains the upper three bits of the slave address in the 10-bit address
mbed_official 324:406fd2029f23 888 * scheme. This field is valid only while the ADEXT bit is set.
mbed_official 324:406fd2029f23 889 */
mbed_official 324:406fd2029f23 890 /*@{*/
mbed_official 324:406fd2029f23 891 #define BP_I2C_C2_AD (0U) /*!< Bit position for I2C_C2_AD. */
mbed_official 324:406fd2029f23 892 #define BM_I2C_C2_AD (0x07U) /*!< Bit mask for I2C_C2_AD. */
mbed_official 324:406fd2029f23 893 #define BS_I2C_C2_AD (3U) /*!< Bit field size in bits for I2C_C2_AD. */
mbed_official 324:406fd2029f23 894
mbed_official 324:406fd2029f23 895 /*! @brief Read current value of the I2C_C2_AD field. */
mbed_official 324:406fd2029f23 896 #define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD)
mbed_official 324:406fd2029f23 897
mbed_official 324:406fd2029f23 898 /*! @brief Format value for bitfield I2C_C2_AD. */
mbed_official 324:406fd2029f23 899 #define BF_I2C_C2_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD)
mbed_official 324:406fd2029f23 900
mbed_official 324:406fd2029f23 901 /*! @brief Set the AD field to a new value. */
mbed_official 324:406fd2029f23 902 #define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
mbed_official 324:406fd2029f23 903 /*@}*/
mbed_official 324:406fd2029f23 904
mbed_official 324:406fd2029f23 905 /*!
mbed_official 324:406fd2029f23 906 * @name Register I2C_C2, field RMEN[3] (RW)
mbed_official 324:406fd2029f23 907 *
mbed_official 324:406fd2029f23 908 * This bit controls the slave address matching for addresses between the values
mbed_official 324:406fd2029f23 909 * of the A1 and RA registers. When this bit is set, a slave address matching
mbed_official 324:406fd2029f23 910 * occurs for any address greater than the value of the A1 register and less than
mbed_official 324:406fd2029f23 911 * or equal to the value of the RA register.
mbed_official 324:406fd2029f23 912 *
mbed_official 324:406fd2029f23 913 * Values:
mbed_official 324:406fd2029f23 914 * - 0 - Range mode disabled. No address matching occurs for an address within
mbed_official 324:406fd2029f23 915 * the range of values of the A1 and RA registers.
mbed_official 324:406fd2029f23 916 * - 1 - Range mode enabled. Address matching occurs when a slave receives an
mbed_official 324:406fd2029f23 917 * address within the range of values of the A1 and RA registers.
mbed_official 324:406fd2029f23 918 */
mbed_official 324:406fd2029f23 919 /*@{*/
mbed_official 324:406fd2029f23 920 #define BP_I2C_C2_RMEN (3U) /*!< Bit position for I2C_C2_RMEN. */
mbed_official 324:406fd2029f23 921 #define BM_I2C_C2_RMEN (0x08U) /*!< Bit mask for I2C_C2_RMEN. */
mbed_official 324:406fd2029f23 922 #define BS_I2C_C2_RMEN (1U) /*!< Bit field size in bits for I2C_C2_RMEN. */
mbed_official 324:406fd2029f23 923
mbed_official 324:406fd2029f23 924 /*! @brief Read current value of the I2C_C2_RMEN field. */
mbed_official 324:406fd2029f23 925 #define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
mbed_official 324:406fd2029f23 926
mbed_official 324:406fd2029f23 927 /*! @brief Format value for bitfield I2C_C2_RMEN. */
mbed_official 324:406fd2029f23 928 #define BF_I2C_C2_RMEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN)
mbed_official 324:406fd2029f23 929
mbed_official 324:406fd2029f23 930 /*! @brief Set the RMEN field to a new value. */
mbed_official 324:406fd2029f23 931 #define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
mbed_official 324:406fd2029f23 932 /*@}*/
mbed_official 324:406fd2029f23 933
mbed_official 324:406fd2029f23 934 /*!
mbed_official 324:406fd2029f23 935 * @name Register I2C_C2, field SBRC[4] (RW)
mbed_official 324:406fd2029f23 936 *
mbed_official 324:406fd2029f23 937 * Enables independent slave mode baud rate at maximum frequency, which forces
mbed_official 324:406fd2029f23 938 * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
mbed_official 324:406fd2029f23 939 * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
mbed_official 324:406fd2029f23 940 * capture the master's data at only 10 kbit/s.
mbed_official 324:406fd2029f23 941 *
mbed_official 324:406fd2029f23 942 * Values:
mbed_official 324:406fd2029f23 943 * - 0 - The slave baud rate follows the master baud rate and clock stretching
mbed_official 324:406fd2029f23 944 * may occur
mbed_official 324:406fd2029f23 945 * - 1 - Slave baud rate is independent of the master baud rate
mbed_official 324:406fd2029f23 946 */
mbed_official 324:406fd2029f23 947 /*@{*/
mbed_official 324:406fd2029f23 948 #define BP_I2C_C2_SBRC (4U) /*!< Bit position for I2C_C2_SBRC. */
mbed_official 324:406fd2029f23 949 #define BM_I2C_C2_SBRC (0x10U) /*!< Bit mask for I2C_C2_SBRC. */
mbed_official 324:406fd2029f23 950 #define BS_I2C_C2_SBRC (1U) /*!< Bit field size in bits for I2C_C2_SBRC. */
mbed_official 324:406fd2029f23 951
mbed_official 324:406fd2029f23 952 /*! @brief Read current value of the I2C_C2_SBRC field. */
mbed_official 324:406fd2029f23 953 #define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
mbed_official 324:406fd2029f23 954
mbed_official 324:406fd2029f23 955 /*! @brief Format value for bitfield I2C_C2_SBRC. */
mbed_official 324:406fd2029f23 956 #define BF_I2C_C2_SBRC(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC)
mbed_official 324:406fd2029f23 957
mbed_official 324:406fd2029f23 958 /*! @brief Set the SBRC field to a new value. */
mbed_official 324:406fd2029f23 959 #define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
mbed_official 324:406fd2029f23 960 /*@}*/
mbed_official 324:406fd2029f23 961
mbed_official 324:406fd2029f23 962 /*!
mbed_official 324:406fd2029f23 963 * @name Register I2C_C2, field HDRS[5] (RW)
mbed_official 324:406fd2029f23 964 *
mbed_official 324:406fd2029f23 965 * Controls the drive capability of the I2C pads.
mbed_official 324:406fd2029f23 966 *
mbed_official 324:406fd2029f23 967 * Values:
mbed_official 324:406fd2029f23 968 * - 0 - Normal drive mode
mbed_official 324:406fd2029f23 969 * - 1 - High drive mode
mbed_official 324:406fd2029f23 970 */
mbed_official 324:406fd2029f23 971 /*@{*/
mbed_official 324:406fd2029f23 972 #define BP_I2C_C2_HDRS (5U) /*!< Bit position for I2C_C2_HDRS. */
mbed_official 324:406fd2029f23 973 #define BM_I2C_C2_HDRS (0x20U) /*!< Bit mask for I2C_C2_HDRS. */
mbed_official 324:406fd2029f23 974 #define BS_I2C_C2_HDRS (1U) /*!< Bit field size in bits for I2C_C2_HDRS. */
mbed_official 324:406fd2029f23 975
mbed_official 324:406fd2029f23 976 /*! @brief Read current value of the I2C_C2_HDRS field. */
mbed_official 324:406fd2029f23 977 #define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
mbed_official 324:406fd2029f23 978
mbed_official 324:406fd2029f23 979 /*! @brief Format value for bitfield I2C_C2_HDRS. */
mbed_official 324:406fd2029f23 980 #define BF_I2C_C2_HDRS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS)
mbed_official 324:406fd2029f23 981
mbed_official 324:406fd2029f23 982 /*! @brief Set the HDRS field to a new value. */
mbed_official 324:406fd2029f23 983 #define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
mbed_official 324:406fd2029f23 984 /*@}*/
mbed_official 324:406fd2029f23 985
mbed_official 324:406fd2029f23 986 /*!
mbed_official 324:406fd2029f23 987 * @name Register I2C_C2, field ADEXT[6] (RW)
mbed_official 324:406fd2029f23 988 *
mbed_official 324:406fd2029f23 989 * Controls the number of bits used for the slave address.
mbed_official 324:406fd2029f23 990 *
mbed_official 324:406fd2029f23 991 * Values:
mbed_official 324:406fd2029f23 992 * - 0 - 7-bit address scheme
mbed_official 324:406fd2029f23 993 * - 1 - 10-bit address scheme
mbed_official 324:406fd2029f23 994 */
mbed_official 324:406fd2029f23 995 /*@{*/
mbed_official 324:406fd2029f23 996 #define BP_I2C_C2_ADEXT (6U) /*!< Bit position for I2C_C2_ADEXT. */
mbed_official 324:406fd2029f23 997 #define BM_I2C_C2_ADEXT (0x40U) /*!< Bit mask for I2C_C2_ADEXT. */
mbed_official 324:406fd2029f23 998 #define BS_I2C_C2_ADEXT (1U) /*!< Bit field size in bits for I2C_C2_ADEXT. */
mbed_official 324:406fd2029f23 999
mbed_official 324:406fd2029f23 1000 /*! @brief Read current value of the I2C_C2_ADEXT field. */
mbed_official 324:406fd2029f23 1001 #define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
mbed_official 324:406fd2029f23 1002
mbed_official 324:406fd2029f23 1003 /*! @brief Format value for bitfield I2C_C2_ADEXT. */
mbed_official 324:406fd2029f23 1004 #define BF_I2C_C2_ADEXT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT)
mbed_official 324:406fd2029f23 1005
mbed_official 324:406fd2029f23 1006 /*! @brief Set the ADEXT field to a new value. */
mbed_official 324:406fd2029f23 1007 #define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
mbed_official 324:406fd2029f23 1008 /*@}*/
mbed_official 324:406fd2029f23 1009
mbed_official 324:406fd2029f23 1010 /*!
mbed_official 324:406fd2029f23 1011 * @name Register I2C_C2, field GCAEN[7] (RW)
mbed_official 324:406fd2029f23 1012 *
mbed_official 324:406fd2029f23 1013 * Enables general call address.
mbed_official 324:406fd2029f23 1014 *
mbed_official 324:406fd2029f23 1015 * Values:
mbed_official 324:406fd2029f23 1016 * - 0 - Disabled
mbed_official 324:406fd2029f23 1017 * - 1 - Enabled
mbed_official 324:406fd2029f23 1018 */
mbed_official 324:406fd2029f23 1019 /*@{*/
mbed_official 324:406fd2029f23 1020 #define BP_I2C_C2_GCAEN (7U) /*!< Bit position for I2C_C2_GCAEN. */
mbed_official 324:406fd2029f23 1021 #define BM_I2C_C2_GCAEN (0x80U) /*!< Bit mask for I2C_C2_GCAEN. */
mbed_official 324:406fd2029f23 1022 #define BS_I2C_C2_GCAEN (1U) /*!< Bit field size in bits for I2C_C2_GCAEN. */
mbed_official 324:406fd2029f23 1023
mbed_official 324:406fd2029f23 1024 /*! @brief Read current value of the I2C_C2_GCAEN field. */
mbed_official 324:406fd2029f23 1025 #define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
mbed_official 324:406fd2029f23 1026
mbed_official 324:406fd2029f23 1027 /*! @brief Format value for bitfield I2C_C2_GCAEN. */
mbed_official 324:406fd2029f23 1028 #define BF_I2C_C2_GCAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN)
mbed_official 324:406fd2029f23 1029
mbed_official 324:406fd2029f23 1030 /*! @brief Set the GCAEN field to a new value. */
mbed_official 324:406fd2029f23 1031 #define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
mbed_official 324:406fd2029f23 1032 /*@}*/
mbed_official 324:406fd2029f23 1033
mbed_official 324:406fd2029f23 1034 /*******************************************************************************
mbed_official 324:406fd2029f23 1035 * HW_I2C_FLT - I2C Programmable Input Glitch Filter register
mbed_official 324:406fd2029f23 1036 ******************************************************************************/
mbed_official 324:406fd2029f23 1037
mbed_official 324:406fd2029f23 1038 /*!
mbed_official 324:406fd2029f23 1039 * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
mbed_official 324:406fd2029f23 1040 *
mbed_official 324:406fd2029f23 1041 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1042 */
mbed_official 324:406fd2029f23 1043 typedef union _hw_i2c_flt
mbed_official 324:406fd2029f23 1044 {
mbed_official 324:406fd2029f23 1045 uint8_t U;
mbed_official 324:406fd2029f23 1046 struct _hw_i2c_flt_bitfields
mbed_official 324:406fd2029f23 1047 {
mbed_official 324:406fd2029f23 1048 uint8_t FLT : 4; /*!< [3:0] I2C Programmable Filter Factor */
mbed_official 324:406fd2029f23 1049 uint8_t STARTF : 1; /*!< [4] I2C Bus Start Detect Flag */
mbed_official 324:406fd2029f23 1050 uint8_t SSIE : 1; /*!< [5] I2C Bus Stop or Start Interrupt Enable */
mbed_official 324:406fd2029f23 1051 uint8_t STOPF : 1; /*!< [6] I2C Bus Stop Detect Flag */
mbed_official 324:406fd2029f23 1052 uint8_t SHEN : 1; /*!< [7] Stop Hold Enable */
mbed_official 324:406fd2029f23 1053 } B;
mbed_official 324:406fd2029f23 1054 } hw_i2c_flt_t;
mbed_official 324:406fd2029f23 1055
mbed_official 324:406fd2029f23 1056 /*!
mbed_official 324:406fd2029f23 1057 * @name Constants and macros for entire I2C_FLT register
mbed_official 324:406fd2029f23 1058 */
mbed_official 324:406fd2029f23 1059 /*@{*/
mbed_official 324:406fd2029f23 1060 #define HW_I2C_FLT_ADDR(x) ((x) + 0x6U)
mbed_official 324:406fd2029f23 1061
mbed_official 324:406fd2029f23 1062 #define HW_I2C_FLT(x) (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
mbed_official 324:406fd2029f23 1063 #define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U)
mbed_official 324:406fd2029f23 1064 #define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v))
mbed_official 324:406fd2029f23 1065 #define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) | (v)))
mbed_official 324:406fd2029f23 1066 #define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1067 #define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1068 /*@}*/
mbed_official 324:406fd2029f23 1069
mbed_official 324:406fd2029f23 1070 /*
mbed_official 324:406fd2029f23 1071 * Constants & macros for individual I2C_FLT bitfields
mbed_official 324:406fd2029f23 1072 */
mbed_official 324:406fd2029f23 1073
mbed_official 324:406fd2029f23 1074 /*!
mbed_official 324:406fd2029f23 1075 * @name Register I2C_FLT, field FLT[3:0] (RW)
mbed_official 324:406fd2029f23 1076 *
mbed_official 324:406fd2029f23 1077 * Controls the width of the glitch, in terms of I2C module clock cycles, that
mbed_official 324:406fd2029f23 1078 * the filter must absorb. For any glitch whose size is less than or equal to this
mbed_official 324:406fd2029f23 1079 * width setting, the filter does not allow the glitch to pass.
mbed_official 324:406fd2029f23 1080 *
mbed_official 324:406fd2029f23 1081 * Values:
mbed_official 324:406fd2029f23 1082 * - 0 - No filter/bypass
mbed_official 324:406fd2029f23 1083 */
mbed_official 324:406fd2029f23 1084 /*@{*/
mbed_official 324:406fd2029f23 1085 #define BP_I2C_FLT_FLT (0U) /*!< Bit position for I2C_FLT_FLT. */
mbed_official 324:406fd2029f23 1086 #define BM_I2C_FLT_FLT (0x0FU) /*!< Bit mask for I2C_FLT_FLT. */
mbed_official 324:406fd2029f23 1087 #define BS_I2C_FLT_FLT (4U) /*!< Bit field size in bits for I2C_FLT_FLT. */
mbed_official 324:406fd2029f23 1088
mbed_official 324:406fd2029f23 1089 /*! @brief Read current value of the I2C_FLT_FLT field. */
mbed_official 324:406fd2029f23 1090 #define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT)
mbed_official 324:406fd2029f23 1091
mbed_official 324:406fd2029f23 1092 /*! @brief Format value for bitfield I2C_FLT_FLT. */
mbed_official 324:406fd2029f23 1093 #define BF_I2C_FLT_FLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT)
mbed_official 324:406fd2029f23 1094
mbed_official 324:406fd2029f23 1095 /*! @brief Set the FLT field to a new value. */
mbed_official 324:406fd2029f23 1096 #define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
mbed_official 324:406fd2029f23 1097 /*@}*/
mbed_official 324:406fd2029f23 1098
mbed_official 324:406fd2029f23 1099 /*!
mbed_official 324:406fd2029f23 1100 * @name Register I2C_FLT, field STARTF[4] (W1C)
mbed_official 324:406fd2029f23 1101 *
mbed_official 324:406fd2029f23 1102 * Hardware sets this bit when the I2C bus's start status is detected. The
mbed_official 324:406fd2029f23 1103 * STARTF bit must be cleared by writing 1 to it.
mbed_official 324:406fd2029f23 1104 *
mbed_official 324:406fd2029f23 1105 * Values:
mbed_official 324:406fd2029f23 1106 * - 0 - No start happens on I2C bus
mbed_official 324:406fd2029f23 1107 * - 1 - Start detected on I2C bus
mbed_official 324:406fd2029f23 1108 */
mbed_official 324:406fd2029f23 1109 /*@{*/
mbed_official 324:406fd2029f23 1110 #define BP_I2C_FLT_STARTF (4U) /*!< Bit position for I2C_FLT_STARTF. */
mbed_official 324:406fd2029f23 1111 #define BM_I2C_FLT_STARTF (0x10U) /*!< Bit mask for I2C_FLT_STARTF. */
mbed_official 324:406fd2029f23 1112 #define BS_I2C_FLT_STARTF (1U) /*!< Bit field size in bits for I2C_FLT_STARTF. */
mbed_official 324:406fd2029f23 1113
mbed_official 324:406fd2029f23 1114 /*! @brief Read current value of the I2C_FLT_STARTF field. */
mbed_official 324:406fd2029f23 1115 #define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
mbed_official 324:406fd2029f23 1116
mbed_official 324:406fd2029f23 1117 /*! @brief Format value for bitfield I2C_FLT_STARTF. */
mbed_official 324:406fd2029f23 1118 #define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF)
mbed_official 324:406fd2029f23 1119
mbed_official 324:406fd2029f23 1120 /*! @brief Set the STARTF field to a new value. */
mbed_official 324:406fd2029f23 1121 #define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
mbed_official 324:406fd2029f23 1122 /*@}*/
mbed_official 324:406fd2029f23 1123
mbed_official 324:406fd2029f23 1124 /*!
mbed_official 324:406fd2029f23 1125 * @name Register I2C_FLT, field SSIE[5] (RW)
mbed_official 324:406fd2029f23 1126 *
mbed_official 324:406fd2029f23 1127 * This bit enables the interrupt for I2C bus stop or start detection. To clear
mbed_official 324:406fd2029f23 1128 * the I2C bus stop or start detection interrupt: In the interrupt service
mbed_official 324:406fd2029f23 1129 * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
mbed_official 324:406fd2029f23 1130 * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
mbed_official 324:406fd2029f23 1131 * is asserted again.
mbed_official 324:406fd2029f23 1132 *
mbed_official 324:406fd2029f23 1133 * Values:
mbed_official 324:406fd2029f23 1134 * - 0 - Stop or start detection interrupt is disabled
mbed_official 324:406fd2029f23 1135 * - 1 - Stop or start detection interrupt is enabled
mbed_official 324:406fd2029f23 1136 */
mbed_official 324:406fd2029f23 1137 /*@{*/
mbed_official 324:406fd2029f23 1138 #define BP_I2C_FLT_SSIE (5U) /*!< Bit position for I2C_FLT_SSIE. */
mbed_official 324:406fd2029f23 1139 #define BM_I2C_FLT_SSIE (0x20U) /*!< Bit mask for I2C_FLT_SSIE. */
mbed_official 324:406fd2029f23 1140 #define BS_I2C_FLT_SSIE (1U) /*!< Bit field size in bits for I2C_FLT_SSIE. */
mbed_official 324:406fd2029f23 1141
mbed_official 324:406fd2029f23 1142 /*! @brief Read current value of the I2C_FLT_SSIE field. */
mbed_official 324:406fd2029f23 1143 #define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
mbed_official 324:406fd2029f23 1144
mbed_official 324:406fd2029f23 1145 /*! @brief Format value for bitfield I2C_FLT_SSIE. */
mbed_official 324:406fd2029f23 1146 #define BF_I2C_FLT_SSIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE)
mbed_official 324:406fd2029f23 1147
mbed_official 324:406fd2029f23 1148 /*! @brief Set the SSIE field to a new value. */
mbed_official 324:406fd2029f23 1149 #define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
mbed_official 324:406fd2029f23 1150 /*@}*/
mbed_official 324:406fd2029f23 1151
mbed_official 324:406fd2029f23 1152 /*!
mbed_official 324:406fd2029f23 1153 * @name Register I2C_FLT, field STOPF[6] (W1C)
mbed_official 324:406fd2029f23 1154 *
mbed_official 324:406fd2029f23 1155 * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
mbed_official 324:406fd2029f23 1156 * bit must be cleared by writing 1 to it.
mbed_official 324:406fd2029f23 1157 *
mbed_official 324:406fd2029f23 1158 * Values:
mbed_official 324:406fd2029f23 1159 * - 0 - No stop happens on I2C bus
mbed_official 324:406fd2029f23 1160 * - 1 - Stop detected on I2C bus
mbed_official 324:406fd2029f23 1161 */
mbed_official 324:406fd2029f23 1162 /*@{*/
mbed_official 324:406fd2029f23 1163 #define BP_I2C_FLT_STOPF (6U) /*!< Bit position for I2C_FLT_STOPF. */
mbed_official 324:406fd2029f23 1164 #define BM_I2C_FLT_STOPF (0x40U) /*!< Bit mask for I2C_FLT_STOPF. */
mbed_official 324:406fd2029f23 1165 #define BS_I2C_FLT_STOPF (1U) /*!< Bit field size in bits for I2C_FLT_STOPF. */
mbed_official 324:406fd2029f23 1166
mbed_official 324:406fd2029f23 1167 /*! @brief Read current value of the I2C_FLT_STOPF field. */
mbed_official 324:406fd2029f23 1168 #define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
mbed_official 324:406fd2029f23 1169
mbed_official 324:406fd2029f23 1170 /*! @brief Format value for bitfield I2C_FLT_STOPF. */
mbed_official 324:406fd2029f23 1171 #define BF_I2C_FLT_STOPF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF)
mbed_official 324:406fd2029f23 1172
mbed_official 324:406fd2029f23 1173 /*! @brief Set the STOPF field to a new value. */
mbed_official 324:406fd2029f23 1174 #define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
mbed_official 324:406fd2029f23 1175 /*@}*/
mbed_official 324:406fd2029f23 1176
mbed_official 324:406fd2029f23 1177 /*!
mbed_official 324:406fd2029f23 1178 * @name Register I2C_FLT, field SHEN[7] (RW)
mbed_official 324:406fd2029f23 1179 *
mbed_official 324:406fd2029f23 1180 * Set this bit to hold off entry to stop mode when any data transmission or
mbed_official 324:406fd2029f23 1181 * reception is occurring. The following scenario explains the holdoff
mbed_official 324:406fd2029f23 1182 * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
mbed_official 324:406fd2029f23 1183 * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
mbed_official 324:406fd2029f23 1184 * byte currently being transferred, including both address and data, completes
mbed_official 324:406fd2029f23 1185 * its transfer. The I2C slave or master acknowledges that the in-transfer byte
mbed_official 324:406fd2029f23 1186 * completed its transfer and acknowledges the request to enter stop mode. After
mbed_official 324:406fd2029f23 1187 * receiving the I2C module's acknowledgment of the request to enter stop mode,
mbed_official 324:406fd2029f23 1188 * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
mbed_official 324:406fd2029f23 1189 * is set to 1 and the I2C module is in an idle or disabled state when the MCU
mbed_official 324:406fd2029f23 1190 * signals to enter stop mode, the module immediately acknowledges the request to
mbed_official 324:406fd2029f23 1191 * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
mbed_official 324:406fd2029f23 1192 * reception that was suspended by stop mode entry was incomplete: To resume the
mbed_official 324:406fd2029f23 1193 * overall transmission or reception after the MCU exits stop mode, software must
mbed_official 324:406fd2029f23 1194 * reinitialize the transfer by resending the address of the slave. If the I2C
mbed_official 324:406fd2029f23 1195 * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
mbed_official 324:406fd2029f23 1196 * system software will receive the interrupt triggered by the I2C Status Register's
mbed_official 324:406fd2029f23 1197 * TCF bit after the MCU wakes from the stop mode.
mbed_official 324:406fd2029f23 1198 *
mbed_official 324:406fd2029f23 1199 * Values:
mbed_official 324:406fd2029f23 1200 * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
mbed_official 324:406fd2029f23 1201 * - 1 - Stop holdoff is enabled.
mbed_official 324:406fd2029f23 1202 */
mbed_official 324:406fd2029f23 1203 /*@{*/
mbed_official 324:406fd2029f23 1204 #define BP_I2C_FLT_SHEN (7U) /*!< Bit position for I2C_FLT_SHEN. */
mbed_official 324:406fd2029f23 1205 #define BM_I2C_FLT_SHEN (0x80U) /*!< Bit mask for I2C_FLT_SHEN. */
mbed_official 324:406fd2029f23 1206 #define BS_I2C_FLT_SHEN (1U) /*!< Bit field size in bits for I2C_FLT_SHEN. */
mbed_official 324:406fd2029f23 1207
mbed_official 324:406fd2029f23 1208 /*! @brief Read current value of the I2C_FLT_SHEN field. */
mbed_official 324:406fd2029f23 1209 #define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
mbed_official 324:406fd2029f23 1210
mbed_official 324:406fd2029f23 1211 /*! @brief Format value for bitfield I2C_FLT_SHEN. */
mbed_official 324:406fd2029f23 1212 #define BF_I2C_FLT_SHEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN)
mbed_official 324:406fd2029f23 1213
mbed_official 324:406fd2029f23 1214 /*! @brief Set the SHEN field to a new value. */
mbed_official 324:406fd2029f23 1215 #define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
mbed_official 324:406fd2029f23 1216 /*@}*/
mbed_official 324:406fd2029f23 1217
mbed_official 324:406fd2029f23 1218 /*******************************************************************************
mbed_official 324:406fd2029f23 1219 * HW_I2C_RA - I2C Range Address register
mbed_official 324:406fd2029f23 1220 ******************************************************************************/
mbed_official 324:406fd2029f23 1221
mbed_official 324:406fd2029f23 1222 /*!
mbed_official 324:406fd2029f23 1223 * @brief HW_I2C_RA - I2C Range Address register (RW)
mbed_official 324:406fd2029f23 1224 *
mbed_official 324:406fd2029f23 1225 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1226 */
mbed_official 324:406fd2029f23 1227 typedef union _hw_i2c_ra
mbed_official 324:406fd2029f23 1228 {
mbed_official 324:406fd2029f23 1229 uint8_t U;
mbed_official 324:406fd2029f23 1230 struct _hw_i2c_ra_bitfields
mbed_official 324:406fd2029f23 1231 {
mbed_official 324:406fd2029f23 1232 uint8_t RESERVED0 : 1; /*!< [0] */
mbed_official 324:406fd2029f23 1233 uint8_t RAD : 7; /*!< [7:1] Range Slave Address */
mbed_official 324:406fd2029f23 1234 } B;
mbed_official 324:406fd2029f23 1235 } hw_i2c_ra_t;
mbed_official 324:406fd2029f23 1236
mbed_official 324:406fd2029f23 1237 /*!
mbed_official 324:406fd2029f23 1238 * @name Constants and macros for entire I2C_RA register
mbed_official 324:406fd2029f23 1239 */
mbed_official 324:406fd2029f23 1240 /*@{*/
mbed_official 324:406fd2029f23 1241 #define HW_I2C_RA_ADDR(x) ((x) + 0x7U)
mbed_official 324:406fd2029f23 1242
mbed_official 324:406fd2029f23 1243 #define HW_I2C_RA(x) (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
mbed_official 324:406fd2029f23 1244 #define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U)
mbed_official 324:406fd2029f23 1245 #define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v))
mbed_official 324:406fd2029f23 1246 #define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) | (v)))
mbed_official 324:406fd2029f23 1247 #define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1248 #define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1249 /*@}*/
mbed_official 324:406fd2029f23 1250
mbed_official 324:406fd2029f23 1251 /*
mbed_official 324:406fd2029f23 1252 * Constants & macros for individual I2C_RA bitfields
mbed_official 324:406fd2029f23 1253 */
mbed_official 324:406fd2029f23 1254
mbed_official 324:406fd2029f23 1255 /*!
mbed_official 324:406fd2029f23 1256 * @name Register I2C_RA, field RAD[7:1] (RW)
mbed_official 324:406fd2029f23 1257 *
mbed_official 324:406fd2029f23 1258 * This field contains the slave address to be used by the I2C module. The field
mbed_official 324:406fd2029f23 1259 * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
mbed_official 324:406fd2029f23 1260 * value write enables this register. This register value can be considered as a
mbed_official 324:406fd2029f23 1261 * maximum boundary in the range matching mode.
mbed_official 324:406fd2029f23 1262 */
mbed_official 324:406fd2029f23 1263 /*@{*/
mbed_official 324:406fd2029f23 1264 #define BP_I2C_RA_RAD (1U) /*!< Bit position for I2C_RA_RAD. */
mbed_official 324:406fd2029f23 1265 #define BM_I2C_RA_RAD (0xFEU) /*!< Bit mask for I2C_RA_RAD. */
mbed_official 324:406fd2029f23 1266 #define BS_I2C_RA_RAD (7U) /*!< Bit field size in bits for I2C_RA_RAD. */
mbed_official 324:406fd2029f23 1267
mbed_official 324:406fd2029f23 1268 /*! @brief Read current value of the I2C_RA_RAD field. */
mbed_official 324:406fd2029f23 1269 #define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD)
mbed_official 324:406fd2029f23 1270
mbed_official 324:406fd2029f23 1271 /*! @brief Format value for bitfield I2C_RA_RAD. */
mbed_official 324:406fd2029f23 1272 #define BF_I2C_RA_RAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD)
mbed_official 324:406fd2029f23 1273
mbed_official 324:406fd2029f23 1274 /*! @brief Set the RAD field to a new value. */
mbed_official 324:406fd2029f23 1275 #define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
mbed_official 324:406fd2029f23 1276 /*@}*/
mbed_official 324:406fd2029f23 1277
mbed_official 324:406fd2029f23 1278 /*******************************************************************************
mbed_official 324:406fd2029f23 1279 * HW_I2C_SMB - I2C SMBus Control and Status register
mbed_official 324:406fd2029f23 1280 ******************************************************************************/
mbed_official 324:406fd2029f23 1281
mbed_official 324:406fd2029f23 1282 /*!
mbed_official 324:406fd2029f23 1283 * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
mbed_official 324:406fd2029f23 1284 *
mbed_official 324:406fd2029f23 1285 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1286 *
mbed_official 324:406fd2029f23 1287 * When the SCL and SDA signals are held high for a length of time greater than
mbed_official 324:406fd2029f23 1288 * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
mbed_official 324:406fd2029f23 1289 * while the system is detecting how long these signals are being held high, a
mbed_official 324:406fd2029f23 1290 * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
mbed_official 324:406fd2029f23 1291 * bus transmission process with the idle bus state. When the TCKSEL bit is set,
mbed_official 324:406fd2029f23 1292 * there is no need to monitor the SHTF1 bit because the bus speed is too high to
mbed_official 324:406fd2029f23 1293 * match the protocol of SMBus.
mbed_official 324:406fd2029f23 1294 */
mbed_official 324:406fd2029f23 1295 typedef union _hw_i2c_smb
mbed_official 324:406fd2029f23 1296 {
mbed_official 324:406fd2029f23 1297 uint8_t U;
mbed_official 324:406fd2029f23 1298 struct _hw_i2c_smb_bitfields
mbed_official 324:406fd2029f23 1299 {
mbed_official 324:406fd2029f23 1300 uint8_t SHTF2IE : 1; /*!< [0] SHTF2 Interrupt Enable */
mbed_official 324:406fd2029f23 1301 uint8_t SHTF2 : 1; /*!< [1] SCL High Timeout Flag 2 */
mbed_official 324:406fd2029f23 1302 uint8_t SHTF1 : 1; /*!< [2] SCL High Timeout Flag 1 */
mbed_official 324:406fd2029f23 1303 uint8_t SLTF : 1; /*!< [3] SCL Low Timeout Flag */
mbed_official 324:406fd2029f23 1304 uint8_t TCKSEL : 1; /*!< [4] Timeout Counter Clock Select */
mbed_official 324:406fd2029f23 1305 uint8_t SIICAEN : 1; /*!< [5] Second I2C Address Enable */
mbed_official 324:406fd2029f23 1306 uint8_t ALERTEN : 1; /*!< [6] SMBus Alert Response Address Enable */
mbed_official 324:406fd2029f23 1307 uint8_t FACK : 1; /*!< [7] Fast NACK/ACK Enable */
mbed_official 324:406fd2029f23 1308 } B;
mbed_official 324:406fd2029f23 1309 } hw_i2c_smb_t;
mbed_official 324:406fd2029f23 1310
mbed_official 324:406fd2029f23 1311 /*!
mbed_official 324:406fd2029f23 1312 * @name Constants and macros for entire I2C_SMB register
mbed_official 324:406fd2029f23 1313 */
mbed_official 324:406fd2029f23 1314 /*@{*/
mbed_official 324:406fd2029f23 1315 #define HW_I2C_SMB_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 1316
mbed_official 324:406fd2029f23 1317 #define HW_I2C_SMB(x) (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
mbed_official 324:406fd2029f23 1318 #define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U)
mbed_official 324:406fd2029f23 1319 #define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v))
mbed_official 324:406fd2029f23 1320 #define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) | (v)))
mbed_official 324:406fd2029f23 1321 #define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1322 #define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1323 /*@}*/
mbed_official 324:406fd2029f23 1324
mbed_official 324:406fd2029f23 1325 /*
mbed_official 324:406fd2029f23 1326 * Constants & macros for individual I2C_SMB bitfields
mbed_official 324:406fd2029f23 1327 */
mbed_official 324:406fd2029f23 1328
mbed_official 324:406fd2029f23 1329 /*!
mbed_official 324:406fd2029f23 1330 * @name Register I2C_SMB, field SHTF2IE[0] (RW)
mbed_official 324:406fd2029f23 1331 *
mbed_official 324:406fd2029f23 1332 * Enables SCL high and SDA low timeout interrupt.
mbed_official 324:406fd2029f23 1333 *
mbed_official 324:406fd2029f23 1334 * Values:
mbed_official 324:406fd2029f23 1335 * - 0 - SHTF2 interrupt is disabled
mbed_official 324:406fd2029f23 1336 * - 1 - SHTF2 interrupt is enabled
mbed_official 324:406fd2029f23 1337 */
mbed_official 324:406fd2029f23 1338 /*@{*/
mbed_official 324:406fd2029f23 1339 #define BP_I2C_SMB_SHTF2IE (0U) /*!< Bit position for I2C_SMB_SHTF2IE. */
mbed_official 324:406fd2029f23 1340 #define BM_I2C_SMB_SHTF2IE (0x01U) /*!< Bit mask for I2C_SMB_SHTF2IE. */
mbed_official 324:406fd2029f23 1341 #define BS_I2C_SMB_SHTF2IE (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */
mbed_official 324:406fd2029f23 1342
mbed_official 324:406fd2029f23 1343 /*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
mbed_official 324:406fd2029f23 1344 #define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
mbed_official 324:406fd2029f23 1345
mbed_official 324:406fd2029f23 1346 /*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */
mbed_official 324:406fd2029f23 1347 #define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE)
mbed_official 324:406fd2029f23 1348
mbed_official 324:406fd2029f23 1349 /*! @brief Set the SHTF2IE field to a new value. */
mbed_official 324:406fd2029f23 1350 #define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
mbed_official 324:406fd2029f23 1351 /*@}*/
mbed_official 324:406fd2029f23 1352
mbed_official 324:406fd2029f23 1353 /*!
mbed_official 324:406fd2029f23 1354 * @name Register I2C_SMB, field SHTF2[1] (W1C)
mbed_official 324:406fd2029f23 1355 *
mbed_official 324:406fd2029f23 1356 * This bit sets when SCL is held high and SDA is held low more than clock *
mbed_official 324:406fd2029f23 1357 * LoValue / 512. Software clears this bit by writing 1 to it.
mbed_official 324:406fd2029f23 1358 *
mbed_official 324:406fd2029f23 1359 * Values:
mbed_official 324:406fd2029f23 1360 * - 0 - No SCL high and SDA low timeout occurs
mbed_official 324:406fd2029f23 1361 * - 1 - SCL high and SDA low timeout occurs
mbed_official 324:406fd2029f23 1362 */
mbed_official 324:406fd2029f23 1363 /*@{*/
mbed_official 324:406fd2029f23 1364 #define BP_I2C_SMB_SHTF2 (1U) /*!< Bit position for I2C_SMB_SHTF2. */
mbed_official 324:406fd2029f23 1365 #define BM_I2C_SMB_SHTF2 (0x02U) /*!< Bit mask for I2C_SMB_SHTF2. */
mbed_official 324:406fd2029f23 1366 #define BS_I2C_SMB_SHTF2 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2. */
mbed_official 324:406fd2029f23 1367
mbed_official 324:406fd2029f23 1368 /*! @brief Read current value of the I2C_SMB_SHTF2 field. */
mbed_official 324:406fd2029f23 1369 #define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
mbed_official 324:406fd2029f23 1370
mbed_official 324:406fd2029f23 1371 /*! @brief Format value for bitfield I2C_SMB_SHTF2. */
mbed_official 324:406fd2029f23 1372 #define BF_I2C_SMB_SHTF2(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2)
mbed_official 324:406fd2029f23 1373
mbed_official 324:406fd2029f23 1374 /*! @brief Set the SHTF2 field to a new value. */
mbed_official 324:406fd2029f23 1375 #define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
mbed_official 324:406fd2029f23 1376 /*@}*/
mbed_official 324:406fd2029f23 1377
mbed_official 324:406fd2029f23 1378 /*!
mbed_official 324:406fd2029f23 1379 * @name Register I2C_SMB, field SHTF1[2] (RO)
mbed_official 324:406fd2029f23 1380 *
mbed_official 324:406fd2029f23 1381 * This read-only bit sets when SCL and SDA are held high more than clock *
mbed_official 324:406fd2029f23 1382 * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
mbed_official 324:406fd2029f23 1383 *
mbed_official 324:406fd2029f23 1384 * Values:
mbed_official 324:406fd2029f23 1385 * - 0 - No SCL high and SDA high timeout occurs
mbed_official 324:406fd2029f23 1386 * - 1 - SCL high and SDA high timeout occurs
mbed_official 324:406fd2029f23 1387 */
mbed_official 324:406fd2029f23 1388 /*@{*/
mbed_official 324:406fd2029f23 1389 #define BP_I2C_SMB_SHTF1 (2U) /*!< Bit position for I2C_SMB_SHTF1. */
mbed_official 324:406fd2029f23 1390 #define BM_I2C_SMB_SHTF1 (0x04U) /*!< Bit mask for I2C_SMB_SHTF1. */
mbed_official 324:406fd2029f23 1391 #define BS_I2C_SMB_SHTF1 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF1. */
mbed_official 324:406fd2029f23 1392
mbed_official 324:406fd2029f23 1393 /*! @brief Read current value of the I2C_SMB_SHTF1 field. */
mbed_official 324:406fd2029f23 1394 #define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
mbed_official 324:406fd2029f23 1395 /*@}*/
mbed_official 324:406fd2029f23 1396
mbed_official 324:406fd2029f23 1397 /*!
mbed_official 324:406fd2029f23 1398 * @name Register I2C_SMB, field SLTF[3] (W1C)
mbed_official 324:406fd2029f23 1399 *
mbed_official 324:406fd2029f23 1400 * This bit is set when the SLT register (consisting of the SLTH and SLTL
mbed_official 324:406fd2029f23 1401 * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
mbed_official 324:406fd2029f23 1402 * Software clears this bit by writing a logic 1 to it. The low timeout function
mbed_official 324:406fd2029f23 1403 * is disabled when the SLT register's value is 0.
mbed_official 324:406fd2029f23 1404 *
mbed_official 324:406fd2029f23 1405 * Values:
mbed_official 324:406fd2029f23 1406 * - 0 - No low timeout occurs
mbed_official 324:406fd2029f23 1407 * - 1 - Low timeout occurs
mbed_official 324:406fd2029f23 1408 */
mbed_official 324:406fd2029f23 1409 /*@{*/
mbed_official 324:406fd2029f23 1410 #define BP_I2C_SMB_SLTF (3U) /*!< Bit position for I2C_SMB_SLTF. */
mbed_official 324:406fd2029f23 1411 #define BM_I2C_SMB_SLTF (0x08U) /*!< Bit mask for I2C_SMB_SLTF. */
mbed_official 324:406fd2029f23 1412 #define BS_I2C_SMB_SLTF (1U) /*!< Bit field size in bits for I2C_SMB_SLTF. */
mbed_official 324:406fd2029f23 1413
mbed_official 324:406fd2029f23 1414 /*! @brief Read current value of the I2C_SMB_SLTF field. */
mbed_official 324:406fd2029f23 1415 #define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
mbed_official 324:406fd2029f23 1416
mbed_official 324:406fd2029f23 1417 /*! @brief Format value for bitfield I2C_SMB_SLTF. */
mbed_official 324:406fd2029f23 1418 #define BF_I2C_SMB_SLTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF)
mbed_official 324:406fd2029f23 1419
mbed_official 324:406fd2029f23 1420 /*! @brief Set the SLTF field to a new value. */
mbed_official 324:406fd2029f23 1421 #define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
mbed_official 324:406fd2029f23 1422 /*@}*/
mbed_official 324:406fd2029f23 1423
mbed_official 324:406fd2029f23 1424 /*!
mbed_official 324:406fd2029f23 1425 * @name Register I2C_SMB, field TCKSEL[4] (RW)
mbed_official 324:406fd2029f23 1426 *
mbed_official 324:406fd2029f23 1427 * Selects the clock source of the timeout counter.
mbed_official 324:406fd2029f23 1428 *
mbed_official 324:406fd2029f23 1429 * Values:
mbed_official 324:406fd2029f23 1430 * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
mbed_official 324:406fd2029f23 1431 * - 1 - Timeout counter counts at the frequency of the I2C module clock
mbed_official 324:406fd2029f23 1432 */
mbed_official 324:406fd2029f23 1433 /*@{*/
mbed_official 324:406fd2029f23 1434 #define BP_I2C_SMB_TCKSEL (4U) /*!< Bit position for I2C_SMB_TCKSEL. */
mbed_official 324:406fd2029f23 1435 #define BM_I2C_SMB_TCKSEL (0x10U) /*!< Bit mask for I2C_SMB_TCKSEL. */
mbed_official 324:406fd2029f23 1436 #define BS_I2C_SMB_TCKSEL (1U) /*!< Bit field size in bits for I2C_SMB_TCKSEL. */
mbed_official 324:406fd2029f23 1437
mbed_official 324:406fd2029f23 1438 /*! @brief Read current value of the I2C_SMB_TCKSEL field. */
mbed_official 324:406fd2029f23 1439 #define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
mbed_official 324:406fd2029f23 1440
mbed_official 324:406fd2029f23 1441 /*! @brief Format value for bitfield I2C_SMB_TCKSEL. */
mbed_official 324:406fd2029f23 1442 #define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL)
mbed_official 324:406fd2029f23 1443
mbed_official 324:406fd2029f23 1444 /*! @brief Set the TCKSEL field to a new value. */
mbed_official 324:406fd2029f23 1445 #define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
mbed_official 324:406fd2029f23 1446 /*@}*/
mbed_official 324:406fd2029f23 1447
mbed_official 324:406fd2029f23 1448 /*!
mbed_official 324:406fd2029f23 1449 * @name Register I2C_SMB, field SIICAEN[5] (RW)
mbed_official 324:406fd2029f23 1450 *
mbed_official 324:406fd2029f23 1451 * Enables or disables SMBus device default address.
mbed_official 324:406fd2029f23 1452 *
mbed_official 324:406fd2029f23 1453 * Values:
mbed_official 324:406fd2029f23 1454 * - 0 - I2C address register 2 matching is disabled
mbed_official 324:406fd2029f23 1455 * - 1 - I2C address register 2 matching is enabled
mbed_official 324:406fd2029f23 1456 */
mbed_official 324:406fd2029f23 1457 /*@{*/
mbed_official 324:406fd2029f23 1458 #define BP_I2C_SMB_SIICAEN (5U) /*!< Bit position for I2C_SMB_SIICAEN. */
mbed_official 324:406fd2029f23 1459 #define BM_I2C_SMB_SIICAEN (0x20U) /*!< Bit mask for I2C_SMB_SIICAEN. */
mbed_official 324:406fd2029f23 1460 #define BS_I2C_SMB_SIICAEN (1U) /*!< Bit field size in bits for I2C_SMB_SIICAEN. */
mbed_official 324:406fd2029f23 1461
mbed_official 324:406fd2029f23 1462 /*! @brief Read current value of the I2C_SMB_SIICAEN field. */
mbed_official 324:406fd2029f23 1463 #define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
mbed_official 324:406fd2029f23 1464
mbed_official 324:406fd2029f23 1465 /*! @brief Format value for bitfield I2C_SMB_SIICAEN. */
mbed_official 324:406fd2029f23 1466 #define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN)
mbed_official 324:406fd2029f23 1467
mbed_official 324:406fd2029f23 1468 /*! @brief Set the SIICAEN field to a new value. */
mbed_official 324:406fd2029f23 1469 #define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
mbed_official 324:406fd2029f23 1470 /*@}*/
mbed_official 324:406fd2029f23 1471
mbed_official 324:406fd2029f23 1472 /*!
mbed_official 324:406fd2029f23 1473 * @name Register I2C_SMB, field ALERTEN[6] (RW)
mbed_official 324:406fd2029f23 1474 *
mbed_official 324:406fd2029f23 1475 * Enables or disables SMBus alert response address matching. After the host
mbed_official 324:406fd2029f23 1476 * responds to a device that used the alert response address, you must use software
mbed_official 324:406fd2029f23 1477 * to put the device's address on the bus. The alert protocol is described in the
mbed_official 324:406fd2029f23 1478 * SMBus specification.
mbed_official 324:406fd2029f23 1479 *
mbed_official 324:406fd2029f23 1480 * Values:
mbed_official 324:406fd2029f23 1481 * - 0 - SMBus alert response address matching is disabled
mbed_official 324:406fd2029f23 1482 * - 1 - SMBus alert response address matching is enabled
mbed_official 324:406fd2029f23 1483 */
mbed_official 324:406fd2029f23 1484 /*@{*/
mbed_official 324:406fd2029f23 1485 #define BP_I2C_SMB_ALERTEN (6U) /*!< Bit position for I2C_SMB_ALERTEN. */
mbed_official 324:406fd2029f23 1486 #define BM_I2C_SMB_ALERTEN (0x40U) /*!< Bit mask for I2C_SMB_ALERTEN. */
mbed_official 324:406fd2029f23 1487 #define BS_I2C_SMB_ALERTEN (1U) /*!< Bit field size in bits for I2C_SMB_ALERTEN. */
mbed_official 324:406fd2029f23 1488
mbed_official 324:406fd2029f23 1489 /*! @brief Read current value of the I2C_SMB_ALERTEN field. */
mbed_official 324:406fd2029f23 1490 #define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
mbed_official 324:406fd2029f23 1491
mbed_official 324:406fd2029f23 1492 /*! @brief Format value for bitfield I2C_SMB_ALERTEN. */
mbed_official 324:406fd2029f23 1493 #define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN)
mbed_official 324:406fd2029f23 1494
mbed_official 324:406fd2029f23 1495 /*! @brief Set the ALERTEN field to a new value. */
mbed_official 324:406fd2029f23 1496 #define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
mbed_official 324:406fd2029f23 1497 /*@}*/
mbed_official 324:406fd2029f23 1498
mbed_official 324:406fd2029f23 1499 /*!
mbed_official 324:406fd2029f23 1500 * @name Register I2C_SMB, field FACK[7] (RW)
mbed_official 324:406fd2029f23 1501 *
mbed_official 324:406fd2029f23 1502 * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
mbed_official 324:406fd2029f23 1503 * according to the result of receiving data byte.
mbed_official 324:406fd2029f23 1504 *
mbed_official 324:406fd2029f23 1505 * Values:
mbed_official 324:406fd2029f23 1506 * - 0 - An ACK or NACK is sent on the following receiving data byte
mbed_official 324:406fd2029f23 1507 * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
mbed_official 324:406fd2029f23 1508 * 1 to TXAK after receiving a data byte generates a NACK.
mbed_official 324:406fd2029f23 1509 */
mbed_official 324:406fd2029f23 1510 /*@{*/
mbed_official 324:406fd2029f23 1511 #define BP_I2C_SMB_FACK (7U) /*!< Bit position for I2C_SMB_FACK. */
mbed_official 324:406fd2029f23 1512 #define BM_I2C_SMB_FACK (0x80U) /*!< Bit mask for I2C_SMB_FACK. */
mbed_official 324:406fd2029f23 1513 #define BS_I2C_SMB_FACK (1U) /*!< Bit field size in bits for I2C_SMB_FACK. */
mbed_official 324:406fd2029f23 1514
mbed_official 324:406fd2029f23 1515 /*! @brief Read current value of the I2C_SMB_FACK field. */
mbed_official 324:406fd2029f23 1516 #define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
mbed_official 324:406fd2029f23 1517
mbed_official 324:406fd2029f23 1518 /*! @brief Format value for bitfield I2C_SMB_FACK. */
mbed_official 324:406fd2029f23 1519 #define BF_I2C_SMB_FACK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK)
mbed_official 324:406fd2029f23 1520
mbed_official 324:406fd2029f23 1521 /*! @brief Set the FACK field to a new value. */
mbed_official 324:406fd2029f23 1522 #define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
mbed_official 324:406fd2029f23 1523 /*@}*/
mbed_official 324:406fd2029f23 1524
mbed_official 324:406fd2029f23 1525 /*******************************************************************************
mbed_official 324:406fd2029f23 1526 * HW_I2C_A2 - I2C Address Register 2
mbed_official 324:406fd2029f23 1527 ******************************************************************************/
mbed_official 324:406fd2029f23 1528
mbed_official 324:406fd2029f23 1529 /*!
mbed_official 324:406fd2029f23 1530 * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
mbed_official 324:406fd2029f23 1531 *
mbed_official 324:406fd2029f23 1532 * Reset value: 0xC2U
mbed_official 324:406fd2029f23 1533 */
mbed_official 324:406fd2029f23 1534 typedef union _hw_i2c_a2
mbed_official 324:406fd2029f23 1535 {
mbed_official 324:406fd2029f23 1536 uint8_t U;
mbed_official 324:406fd2029f23 1537 struct _hw_i2c_a2_bitfields
mbed_official 324:406fd2029f23 1538 {
mbed_official 324:406fd2029f23 1539 uint8_t RESERVED0 : 1; /*!< [0] */
mbed_official 324:406fd2029f23 1540 uint8_t SAD : 7; /*!< [7:1] SMBus Address */
mbed_official 324:406fd2029f23 1541 } B;
mbed_official 324:406fd2029f23 1542 } hw_i2c_a2_t;
mbed_official 324:406fd2029f23 1543
mbed_official 324:406fd2029f23 1544 /*!
mbed_official 324:406fd2029f23 1545 * @name Constants and macros for entire I2C_A2 register
mbed_official 324:406fd2029f23 1546 */
mbed_official 324:406fd2029f23 1547 /*@{*/
mbed_official 324:406fd2029f23 1548 #define HW_I2C_A2_ADDR(x) ((x) + 0x9U)
mbed_official 324:406fd2029f23 1549
mbed_official 324:406fd2029f23 1550 #define HW_I2C_A2(x) (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
mbed_official 324:406fd2029f23 1551 #define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U)
mbed_official 324:406fd2029f23 1552 #define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v))
mbed_official 324:406fd2029f23 1553 #define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) | (v)))
mbed_official 324:406fd2029f23 1554 #define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1555 #define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1556 /*@}*/
mbed_official 324:406fd2029f23 1557
mbed_official 324:406fd2029f23 1558 /*
mbed_official 324:406fd2029f23 1559 * Constants & macros for individual I2C_A2 bitfields
mbed_official 324:406fd2029f23 1560 */
mbed_official 324:406fd2029f23 1561
mbed_official 324:406fd2029f23 1562 /*!
mbed_official 324:406fd2029f23 1563 * @name Register I2C_A2, field SAD[7:1] (RW)
mbed_official 324:406fd2029f23 1564 *
mbed_official 324:406fd2029f23 1565 * Contains the slave address used by the SMBus. This field is used on the
mbed_official 324:406fd2029f23 1566 * device default address or other related addresses.
mbed_official 324:406fd2029f23 1567 */
mbed_official 324:406fd2029f23 1568 /*@{*/
mbed_official 324:406fd2029f23 1569 #define BP_I2C_A2_SAD (1U) /*!< Bit position for I2C_A2_SAD. */
mbed_official 324:406fd2029f23 1570 #define BM_I2C_A2_SAD (0xFEU) /*!< Bit mask for I2C_A2_SAD. */
mbed_official 324:406fd2029f23 1571 #define BS_I2C_A2_SAD (7U) /*!< Bit field size in bits for I2C_A2_SAD. */
mbed_official 324:406fd2029f23 1572
mbed_official 324:406fd2029f23 1573 /*! @brief Read current value of the I2C_A2_SAD field. */
mbed_official 324:406fd2029f23 1574 #define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD)
mbed_official 324:406fd2029f23 1575
mbed_official 324:406fd2029f23 1576 /*! @brief Format value for bitfield I2C_A2_SAD. */
mbed_official 324:406fd2029f23 1577 #define BF_I2C_A2_SAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD)
mbed_official 324:406fd2029f23 1578
mbed_official 324:406fd2029f23 1579 /*! @brief Set the SAD field to a new value. */
mbed_official 324:406fd2029f23 1580 #define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
mbed_official 324:406fd2029f23 1581 /*@}*/
mbed_official 324:406fd2029f23 1582
mbed_official 324:406fd2029f23 1583 /*******************************************************************************
mbed_official 324:406fd2029f23 1584 * HW_I2C_SLTH - I2C SCL Low Timeout Register High
mbed_official 324:406fd2029f23 1585 ******************************************************************************/
mbed_official 324:406fd2029f23 1586
mbed_official 324:406fd2029f23 1587 /*!
mbed_official 324:406fd2029f23 1588 * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
mbed_official 324:406fd2029f23 1589 *
mbed_official 324:406fd2029f23 1590 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1591 */
mbed_official 324:406fd2029f23 1592 typedef union _hw_i2c_slth
mbed_official 324:406fd2029f23 1593 {
mbed_official 324:406fd2029f23 1594 uint8_t U;
mbed_official 324:406fd2029f23 1595 struct _hw_i2c_slth_bitfields
mbed_official 324:406fd2029f23 1596 {
mbed_official 324:406fd2029f23 1597 uint8_t SSLT : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1598 } B;
mbed_official 324:406fd2029f23 1599 } hw_i2c_slth_t;
mbed_official 324:406fd2029f23 1600
mbed_official 324:406fd2029f23 1601 /*!
mbed_official 324:406fd2029f23 1602 * @name Constants and macros for entire I2C_SLTH register
mbed_official 324:406fd2029f23 1603 */
mbed_official 324:406fd2029f23 1604 /*@{*/
mbed_official 324:406fd2029f23 1605 #define HW_I2C_SLTH_ADDR(x) ((x) + 0xAU)
mbed_official 324:406fd2029f23 1606
mbed_official 324:406fd2029f23 1607 #define HW_I2C_SLTH(x) (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
mbed_official 324:406fd2029f23 1608 #define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U)
mbed_official 324:406fd2029f23 1609 #define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v))
mbed_official 324:406fd2029f23 1610 #define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) | (v)))
mbed_official 324:406fd2029f23 1611 #define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1612 #define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1613 /*@}*/
mbed_official 324:406fd2029f23 1614
mbed_official 324:406fd2029f23 1615 /*
mbed_official 324:406fd2029f23 1616 * Constants & macros for individual I2C_SLTH bitfields
mbed_official 324:406fd2029f23 1617 */
mbed_official 324:406fd2029f23 1618
mbed_official 324:406fd2029f23 1619 /*!
mbed_official 324:406fd2029f23 1620 * @name Register I2C_SLTH, field SSLT[7:0] (RW)
mbed_official 324:406fd2029f23 1621 *
mbed_official 324:406fd2029f23 1622 * Most significant byte of SCL low timeout value that determines the timeout
mbed_official 324:406fd2029f23 1623 * period of SCL low.
mbed_official 324:406fd2029f23 1624 */
mbed_official 324:406fd2029f23 1625 /*@{*/
mbed_official 324:406fd2029f23 1626 #define BP_I2C_SLTH_SSLT (0U) /*!< Bit position for I2C_SLTH_SSLT. */
mbed_official 324:406fd2029f23 1627 #define BM_I2C_SLTH_SSLT (0xFFU) /*!< Bit mask for I2C_SLTH_SSLT. */
mbed_official 324:406fd2029f23 1628 #define BS_I2C_SLTH_SSLT (8U) /*!< Bit field size in bits for I2C_SLTH_SSLT. */
mbed_official 324:406fd2029f23 1629
mbed_official 324:406fd2029f23 1630 /*! @brief Read current value of the I2C_SLTH_SSLT field. */
mbed_official 324:406fd2029f23 1631 #define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U)
mbed_official 324:406fd2029f23 1632
mbed_official 324:406fd2029f23 1633 /*! @brief Format value for bitfield I2C_SLTH_SSLT. */
mbed_official 324:406fd2029f23 1634 #define BF_I2C_SLTH_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT)
mbed_official 324:406fd2029f23 1635
mbed_official 324:406fd2029f23 1636 /*! @brief Set the SSLT field to a new value. */
mbed_official 324:406fd2029f23 1637 #define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
mbed_official 324:406fd2029f23 1638 /*@}*/
mbed_official 324:406fd2029f23 1639
mbed_official 324:406fd2029f23 1640 /*******************************************************************************
mbed_official 324:406fd2029f23 1641 * HW_I2C_SLTL - I2C SCL Low Timeout Register Low
mbed_official 324:406fd2029f23 1642 ******************************************************************************/
mbed_official 324:406fd2029f23 1643
mbed_official 324:406fd2029f23 1644 /*!
mbed_official 324:406fd2029f23 1645 * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
mbed_official 324:406fd2029f23 1646 *
mbed_official 324:406fd2029f23 1647 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1648 */
mbed_official 324:406fd2029f23 1649 typedef union _hw_i2c_sltl
mbed_official 324:406fd2029f23 1650 {
mbed_official 324:406fd2029f23 1651 uint8_t U;
mbed_official 324:406fd2029f23 1652 struct _hw_i2c_sltl_bitfields
mbed_official 324:406fd2029f23 1653 {
mbed_official 324:406fd2029f23 1654 uint8_t SSLT : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1655 } B;
mbed_official 324:406fd2029f23 1656 } hw_i2c_sltl_t;
mbed_official 324:406fd2029f23 1657
mbed_official 324:406fd2029f23 1658 /*!
mbed_official 324:406fd2029f23 1659 * @name Constants and macros for entire I2C_SLTL register
mbed_official 324:406fd2029f23 1660 */
mbed_official 324:406fd2029f23 1661 /*@{*/
mbed_official 324:406fd2029f23 1662 #define HW_I2C_SLTL_ADDR(x) ((x) + 0xBU)
mbed_official 324:406fd2029f23 1663
mbed_official 324:406fd2029f23 1664 #define HW_I2C_SLTL(x) (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
mbed_official 324:406fd2029f23 1665 #define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U)
mbed_official 324:406fd2029f23 1666 #define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v))
mbed_official 324:406fd2029f23 1667 #define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) | (v)))
mbed_official 324:406fd2029f23 1668 #define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1669 #define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1670 /*@}*/
mbed_official 324:406fd2029f23 1671
mbed_official 324:406fd2029f23 1672 /*
mbed_official 324:406fd2029f23 1673 * Constants & macros for individual I2C_SLTL bitfields
mbed_official 324:406fd2029f23 1674 */
mbed_official 324:406fd2029f23 1675
mbed_official 324:406fd2029f23 1676 /*!
mbed_official 324:406fd2029f23 1677 * @name Register I2C_SLTL, field SSLT[7:0] (RW)
mbed_official 324:406fd2029f23 1678 *
mbed_official 324:406fd2029f23 1679 * Least significant byte of SCL low timeout value that determines the timeout
mbed_official 324:406fd2029f23 1680 * period of SCL low.
mbed_official 324:406fd2029f23 1681 */
mbed_official 324:406fd2029f23 1682 /*@{*/
mbed_official 324:406fd2029f23 1683 #define BP_I2C_SLTL_SSLT (0U) /*!< Bit position for I2C_SLTL_SSLT. */
mbed_official 324:406fd2029f23 1684 #define BM_I2C_SLTL_SSLT (0xFFU) /*!< Bit mask for I2C_SLTL_SSLT. */
mbed_official 324:406fd2029f23 1685 #define BS_I2C_SLTL_SSLT (8U) /*!< Bit field size in bits for I2C_SLTL_SSLT. */
mbed_official 324:406fd2029f23 1686
mbed_official 324:406fd2029f23 1687 /*! @brief Read current value of the I2C_SLTL_SSLT field. */
mbed_official 324:406fd2029f23 1688 #define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U)
mbed_official 324:406fd2029f23 1689
mbed_official 324:406fd2029f23 1690 /*! @brief Format value for bitfield I2C_SLTL_SSLT. */
mbed_official 324:406fd2029f23 1691 #define BF_I2C_SLTL_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT)
mbed_official 324:406fd2029f23 1692
mbed_official 324:406fd2029f23 1693 /*! @brief Set the SSLT field to a new value. */
mbed_official 324:406fd2029f23 1694 #define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
mbed_official 324:406fd2029f23 1695 /*@}*/
mbed_official 324:406fd2029f23 1696
mbed_official 324:406fd2029f23 1697 /*******************************************************************************
mbed_official 324:406fd2029f23 1698 * hw_i2c_t - module struct
mbed_official 324:406fd2029f23 1699 ******************************************************************************/
mbed_official 324:406fd2029f23 1700 /*!
mbed_official 324:406fd2029f23 1701 * @brief All I2C module registers.
mbed_official 324:406fd2029f23 1702 */
mbed_official 324:406fd2029f23 1703 #pragma pack(1)
mbed_official 324:406fd2029f23 1704 typedef struct _hw_i2c
mbed_official 324:406fd2029f23 1705 {
mbed_official 324:406fd2029f23 1706 __IO hw_i2c_a1_t A1; /*!< [0x0] I2C Address Register 1 */
mbed_official 324:406fd2029f23 1707 __IO hw_i2c_f_t F; /*!< [0x1] I2C Frequency Divider register */
mbed_official 324:406fd2029f23 1708 __IO hw_i2c_c1_t C1; /*!< [0x2] I2C Control Register 1 */
mbed_official 324:406fd2029f23 1709 __IO hw_i2c_s_t S; /*!< [0x3] I2C Status register */
mbed_official 324:406fd2029f23 1710 __IO hw_i2c_d_t D; /*!< [0x4] I2C Data I/O register */
mbed_official 324:406fd2029f23 1711 __IO hw_i2c_c2_t C2; /*!< [0x5] I2C Control Register 2 */
mbed_official 324:406fd2029f23 1712 __IO hw_i2c_flt_t FLT; /*!< [0x6] I2C Programmable Input Glitch Filter register */
mbed_official 324:406fd2029f23 1713 __IO hw_i2c_ra_t RA; /*!< [0x7] I2C Range Address register */
mbed_official 324:406fd2029f23 1714 __IO hw_i2c_smb_t SMB; /*!< [0x8] I2C SMBus Control and Status register */
mbed_official 324:406fd2029f23 1715 __IO hw_i2c_a2_t A2; /*!< [0x9] I2C Address Register 2 */
mbed_official 324:406fd2029f23 1716 __IO hw_i2c_slth_t SLTH; /*!< [0xA] I2C SCL Low Timeout Register High */
mbed_official 324:406fd2029f23 1717 __IO hw_i2c_sltl_t SLTL; /*!< [0xB] I2C SCL Low Timeout Register Low */
mbed_official 324:406fd2029f23 1718 } hw_i2c_t;
mbed_official 324:406fd2029f23 1719 #pragma pack()
mbed_official 324:406fd2029f23 1720
mbed_official 324:406fd2029f23 1721 /*! @brief Macro to access all I2C registers. */
mbed_official 324:406fd2029f23 1722 /*! @param x I2C module instance base address. */
mbed_official 324:406fd2029f23 1723 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 1724 * use the '&' operator, like <code>&HW_I2C(I2C0_BASE)</code>. */
mbed_official 324:406fd2029f23 1725 #define HW_I2C(x) (*(hw_i2c_t *)(x))
mbed_official 324:406fd2029f23 1726
mbed_official 324:406fd2029f23 1727 #endif /* __HW_I2C_REGISTERS_H__ */
mbed_official 324:406fd2029f23 1728 /* EOF */