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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_FTM_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_FTM_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 FTM
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * FlexTimer Module
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_FTM_SC - Status And Control
mbed_official 324:406fd2029f23 93 * - HW_FTM_CNT - Counter
mbed_official 324:406fd2029f23 94 * - HW_FTM_MOD - Modulo
mbed_official 324:406fd2029f23 95 * - HW_FTM_CnSC - Channel (n) Status And Control
mbed_official 324:406fd2029f23 96 * - HW_FTM_CnV - Channel (n) Value
mbed_official 324:406fd2029f23 97 * - HW_FTM_CNTIN - Counter Initial Value
mbed_official 324:406fd2029f23 98 * - HW_FTM_STATUS - Capture And Compare Status
mbed_official 324:406fd2029f23 99 * - HW_FTM_MODE - Features Mode Selection
mbed_official 324:406fd2029f23 100 * - HW_FTM_SYNC - Synchronization
mbed_official 324:406fd2029f23 101 * - HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official 324:406fd2029f23 102 * - HW_FTM_OUTMASK - Output Mask
mbed_official 324:406fd2029f23 103 * - HW_FTM_COMBINE - Function For Linked Channels
mbed_official 324:406fd2029f23 104 * - HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official 324:406fd2029f23 105 * - HW_FTM_EXTTRIG - FTM External Trigger
mbed_official 324:406fd2029f23 106 * - HW_FTM_POL - Channels Polarity
mbed_official 324:406fd2029f23 107 * - HW_FTM_FMS - Fault Mode Status
mbed_official 324:406fd2029f23 108 * - HW_FTM_FILTER - Input Capture Filter Control
mbed_official 324:406fd2029f23 109 * - HW_FTM_FLTCTRL - Fault Control
mbed_official 324:406fd2029f23 110 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official 324:406fd2029f23 111 * - HW_FTM_CONF - Configuration
mbed_official 324:406fd2029f23 112 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official 324:406fd2029f23 113 * - HW_FTM_SYNCONF - Synchronization Configuration
mbed_official 324:406fd2029f23 114 * - HW_FTM_INVCTRL - FTM Inverting Control
mbed_official 324:406fd2029f23 115 * - HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official 324:406fd2029f23 116 * - HW_FTM_PWMLOAD - FTM PWM Load
mbed_official 324:406fd2029f23 117 *
mbed_official 324:406fd2029f23 118 * - hw_ftm_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 119 */
mbed_official 324:406fd2029f23 120
mbed_official 324:406fd2029f23 121 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
mbed_official 324:406fd2029f23 122 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
mbed_official 324:406fd2029f23 123 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
mbed_official 324:406fd2029f23 124 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
mbed_official 324:406fd2029f23 125 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
mbed_official 324:406fd2029f23 126
mbed_official 324:406fd2029f23 127 /*******************************************************************************
mbed_official 324:406fd2029f23 128 * HW_FTM_SC - Status And Control
mbed_official 324:406fd2029f23 129 ******************************************************************************/
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 /*!
mbed_official 324:406fd2029f23 132 * @brief HW_FTM_SC - Status And Control (RW)
mbed_official 324:406fd2029f23 133 *
mbed_official 324:406fd2029f23 134 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 135 *
mbed_official 324:406fd2029f23 136 * SC contains the overflow status flag and control bits used to configure the
mbed_official 324:406fd2029f23 137 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
mbed_official 324:406fd2029f23 138 * controls relate to all channels within this module.
mbed_official 324:406fd2029f23 139 */
mbed_official 324:406fd2029f23 140 typedef union _hw_ftm_sc
mbed_official 324:406fd2029f23 141 {
mbed_official 324:406fd2029f23 142 uint32_t U;
mbed_official 324:406fd2029f23 143 struct _hw_ftm_sc_bitfields
mbed_official 324:406fd2029f23 144 {
mbed_official 324:406fd2029f23 145 uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */
mbed_official 324:406fd2029f23 146 uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */
mbed_official 324:406fd2029f23 147 uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */
mbed_official 324:406fd2029f23 148 uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */
mbed_official 324:406fd2029f23 149 uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */
mbed_official 324:406fd2029f23 150 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 151 } B;
mbed_official 324:406fd2029f23 152 } hw_ftm_sc_t;
mbed_official 324:406fd2029f23 153
mbed_official 324:406fd2029f23 154 /*!
mbed_official 324:406fd2029f23 155 * @name Constants and macros for entire FTM_SC register
mbed_official 324:406fd2029f23 156 */
mbed_official 324:406fd2029f23 157 /*@{*/
mbed_official 324:406fd2029f23 158 #define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 159
mbed_official 324:406fd2029f23 160 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
mbed_official 324:406fd2029f23 161 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
mbed_official 324:406fd2029f23 162 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
mbed_official 324:406fd2029f23 163 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
mbed_official 324:406fd2029f23 164 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 165 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 166 /*@}*/
mbed_official 324:406fd2029f23 167
mbed_official 324:406fd2029f23 168 /*
mbed_official 324:406fd2029f23 169 * Constants & macros for individual FTM_SC bitfields
mbed_official 324:406fd2029f23 170 */
mbed_official 324:406fd2029f23 171
mbed_official 324:406fd2029f23 172 /*!
mbed_official 324:406fd2029f23 173 * @name Register FTM_SC, field PS[2:0] (RW)
mbed_official 324:406fd2029f23 174 *
mbed_official 324:406fd2029f23 175 * Selects one of 8 division factors for the clock source selected by CLKS. The
mbed_official 324:406fd2029f23 176 * new prescaler factor affects the clock source on the next system clock cycle
mbed_official 324:406fd2029f23 177 * after the new value is updated into the register bits. This field is write
mbed_official 324:406fd2029f23 178 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 179 *
mbed_official 324:406fd2029f23 180 * Values:
mbed_official 324:406fd2029f23 181 * - 000 - Divide by 1
mbed_official 324:406fd2029f23 182 * - 001 - Divide by 2
mbed_official 324:406fd2029f23 183 * - 010 - Divide by 4
mbed_official 324:406fd2029f23 184 * - 011 - Divide by 8
mbed_official 324:406fd2029f23 185 * - 100 - Divide by 16
mbed_official 324:406fd2029f23 186 * - 101 - Divide by 32
mbed_official 324:406fd2029f23 187 * - 110 - Divide by 64
mbed_official 324:406fd2029f23 188 * - 111 - Divide by 128
mbed_official 324:406fd2029f23 189 */
mbed_official 324:406fd2029f23 190 /*@{*/
mbed_official 324:406fd2029f23 191 #define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */
mbed_official 324:406fd2029f23 192 #define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
mbed_official 324:406fd2029f23 193 #define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */
mbed_official 324:406fd2029f23 194
mbed_official 324:406fd2029f23 195 /*! @brief Read current value of the FTM_SC_PS field. */
mbed_official 324:406fd2029f23 196 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*! @brief Format value for bitfield FTM_SC_PS. */
mbed_official 324:406fd2029f23 199 #define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 /*! @brief Set the PS field to a new value. */
mbed_official 324:406fd2029f23 202 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
mbed_official 324:406fd2029f23 203 /*@}*/
mbed_official 324:406fd2029f23 204
mbed_official 324:406fd2029f23 205 /*!
mbed_official 324:406fd2029f23 206 * @name Register FTM_SC, field CLKS[4:3] (RW)
mbed_official 324:406fd2029f23 207 *
mbed_official 324:406fd2029f23 208 * Selects one of the three FTM counter clock sources. This field is write
mbed_official 324:406fd2029f23 209 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 210 *
mbed_official 324:406fd2029f23 211 * Values:
mbed_official 324:406fd2029f23 212 * - 00 - No clock selected. This in effect disables the FTM counter.
mbed_official 324:406fd2029f23 213 * - 01 - System clock
mbed_official 324:406fd2029f23 214 * - 10 - Fixed frequency clock
mbed_official 324:406fd2029f23 215 * - 11 - External clock
mbed_official 324:406fd2029f23 216 */
mbed_official 324:406fd2029f23 217 /*@{*/
mbed_official 324:406fd2029f23 218 #define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */
mbed_official 324:406fd2029f23 219 #define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
mbed_official 324:406fd2029f23 220 #define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */
mbed_official 324:406fd2029f23 221
mbed_official 324:406fd2029f23 222 /*! @brief Read current value of the FTM_SC_CLKS field. */
mbed_official 324:406fd2029f23 223 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
mbed_official 324:406fd2029f23 224
mbed_official 324:406fd2029f23 225 /*! @brief Format value for bitfield FTM_SC_CLKS. */
mbed_official 324:406fd2029f23 226 #define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
mbed_official 324:406fd2029f23 227
mbed_official 324:406fd2029f23 228 /*! @brief Set the CLKS field to a new value. */
mbed_official 324:406fd2029f23 229 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
mbed_official 324:406fd2029f23 230 /*@}*/
mbed_official 324:406fd2029f23 231
mbed_official 324:406fd2029f23 232 /*!
mbed_official 324:406fd2029f23 233 * @name Register FTM_SC, field CPWMS[5] (RW)
mbed_official 324:406fd2029f23 234 *
mbed_official 324:406fd2029f23 235 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
mbed_official 324:406fd2029f23 236 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official 324:406fd2029f23 237 * = 1.
mbed_official 324:406fd2029f23 238 *
mbed_official 324:406fd2029f23 239 * Values:
mbed_official 324:406fd2029f23 240 * - 0 - FTM counter operates in Up Counting mode.
mbed_official 324:406fd2029f23 241 * - 1 - FTM counter operates in Up-Down Counting mode.
mbed_official 324:406fd2029f23 242 */
mbed_official 324:406fd2029f23 243 /*@{*/
mbed_official 324:406fd2029f23 244 #define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */
mbed_official 324:406fd2029f23 245 #define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
mbed_official 324:406fd2029f23 246 #define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */
mbed_official 324:406fd2029f23 247
mbed_official 324:406fd2029f23 248 /*! @brief Read current value of the FTM_SC_CPWMS field. */
mbed_official 324:406fd2029f23 249 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
mbed_official 324:406fd2029f23 250
mbed_official 324:406fd2029f23 251 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
mbed_official 324:406fd2029f23 252 #define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
mbed_official 324:406fd2029f23 253
mbed_official 324:406fd2029f23 254 /*! @brief Set the CPWMS field to a new value. */
mbed_official 324:406fd2029f23 255 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
mbed_official 324:406fd2029f23 256 /*@}*/
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 /*!
mbed_official 324:406fd2029f23 259 * @name Register FTM_SC, field TOIE[6] (RW)
mbed_official 324:406fd2029f23 260 *
mbed_official 324:406fd2029f23 261 * Enables FTM overflow interrupts.
mbed_official 324:406fd2029f23 262 *
mbed_official 324:406fd2029f23 263 * Values:
mbed_official 324:406fd2029f23 264 * - 0 - Disable TOF interrupts. Use software polling.
mbed_official 324:406fd2029f23 265 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
mbed_official 324:406fd2029f23 266 */
mbed_official 324:406fd2029f23 267 /*@{*/
mbed_official 324:406fd2029f23 268 #define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */
mbed_official 324:406fd2029f23 269 #define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
mbed_official 324:406fd2029f23 270 #define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */
mbed_official 324:406fd2029f23 271
mbed_official 324:406fd2029f23 272 /*! @brief Read current value of the FTM_SC_TOIE field. */
mbed_official 324:406fd2029f23 273 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
mbed_official 324:406fd2029f23 274
mbed_official 324:406fd2029f23 275 /*! @brief Format value for bitfield FTM_SC_TOIE. */
mbed_official 324:406fd2029f23 276 #define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
mbed_official 324:406fd2029f23 277
mbed_official 324:406fd2029f23 278 /*! @brief Set the TOIE field to a new value. */
mbed_official 324:406fd2029f23 279 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
mbed_official 324:406fd2029f23 280 /*@}*/
mbed_official 324:406fd2029f23 281
mbed_official 324:406fd2029f23 282 /*!
mbed_official 324:406fd2029f23 283 * @name Register FTM_SC, field TOF[7] (ROWZ)
mbed_official 324:406fd2029f23 284 *
mbed_official 324:406fd2029f23 285 * Set by hardware when the FTM counter passes the value in the MOD register.
mbed_official 324:406fd2029f23 286 * The TOF bit is cleared by reading the SC register while TOF is set and then
mbed_official 324:406fd2029f23 287 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
mbed_official 324:406fd2029f23 288 * occurs between the read and write operations, the write operation has no
mbed_official 324:406fd2029f23 289 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
mbed_official 324:406fd2029f23 290 * case, a TOF interrupt request is not lost due to the clearing sequence for a
mbed_official 324:406fd2029f23 291 * previous TOF.
mbed_official 324:406fd2029f23 292 *
mbed_official 324:406fd2029f23 293 * Values:
mbed_official 324:406fd2029f23 294 * - 0 - FTM counter has not overflowed.
mbed_official 324:406fd2029f23 295 * - 1 - FTM counter has overflowed.
mbed_official 324:406fd2029f23 296 */
mbed_official 324:406fd2029f23 297 /*@{*/
mbed_official 324:406fd2029f23 298 #define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */
mbed_official 324:406fd2029f23 299 #define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
mbed_official 324:406fd2029f23 300 #define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */
mbed_official 324:406fd2029f23 301
mbed_official 324:406fd2029f23 302 /*! @brief Read current value of the FTM_SC_TOF field. */
mbed_official 324:406fd2029f23 303 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
mbed_official 324:406fd2029f23 304
mbed_official 324:406fd2029f23 305 /*! @brief Format value for bitfield FTM_SC_TOF. */
mbed_official 324:406fd2029f23 306 #define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
mbed_official 324:406fd2029f23 307
mbed_official 324:406fd2029f23 308 /*! @brief Set the TOF field to a new value. */
mbed_official 324:406fd2029f23 309 #define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
mbed_official 324:406fd2029f23 310 /*@}*/
mbed_official 324:406fd2029f23 311
mbed_official 324:406fd2029f23 312 /*******************************************************************************
mbed_official 324:406fd2029f23 313 * HW_FTM_CNT - Counter
mbed_official 324:406fd2029f23 314 ******************************************************************************/
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 /*!
mbed_official 324:406fd2029f23 317 * @brief HW_FTM_CNT - Counter (RW)
mbed_official 324:406fd2029f23 318 *
mbed_official 324:406fd2029f23 319 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 320 *
mbed_official 324:406fd2029f23 321 * The CNT register contains the FTM counter value. Reset clears the CNT
mbed_official 324:406fd2029f23 322 * register. Writing any value to COUNT updates the counter with its initial value,
mbed_official 324:406fd2029f23 323 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
mbed_official 324:406fd2029f23 324 * may read.
mbed_official 324:406fd2029f23 325 */
mbed_official 324:406fd2029f23 326 typedef union _hw_ftm_cnt
mbed_official 324:406fd2029f23 327 {
mbed_official 324:406fd2029f23 328 uint32_t U;
mbed_official 324:406fd2029f23 329 struct _hw_ftm_cnt_bitfields
mbed_official 324:406fd2029f23 330 {
mbed_official 324:406fd2029f23 331 uint32_t COUNT : 16; /*!< [15:0] Counter Value */
mbed_official 324:406fd2029f23 332 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 333 } B;
mbed_official 324:406fd2029f23 334 } hw_ftm_cnt_t;
mbed_official 324:406fd2029f23 335
mbed_official 324:406fd2029f23 336 /*!
mbed_official 324:406fd2029f23 337 * @name Constants and macros for entire FTM_CNT register
mbed_official 324:406fd2029f23 338 */
mbed_official 324:406fd2029f23 339 /*@{*/
mbed_official 324:406fd2029f23 340 #define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 341
mbed_official 324:406fd2029f23 342 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
mbed_official 324:406fd2029f23 343 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
mbed_official 324:406fd2029f23 344 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
mbed_official 324:406fd2029f23 345 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
mbed_official 324:406fd2029f23 346 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 347 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 348 /*@}*/
mbed_official 324:406fd2029f23 349
mbed_official 324:406fd2029f23 350 /*
mbed_official 324:406fd2029f23 351 * Constants & macros for individual FTM_CNT bitfields
mbed_official 324:406fd2029f23 352 */
mbed_official 324:406fd2029f23 353
mbed_official 324:406fd2029f23 354 /*!
mbed_official 324:406fd2029f23 355 * @name Register FTM_CNT, field COUNT[15:0] (RW)
mbed_official 324:406fd2029f23 356 */
mbed_official 324:406fd2029f23 357 /*@{*/
mbed_official 324:406fd2029f23 358 #define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */
mbed_official 324:406fd2029f23 359 #define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
mbed_official 324:406fd2029f23 360 #define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */
mbed_official 324:406fd2029f23 361
mbed_official 324:406fd2029f23 362 /*! @brief Read current value of the FTM_CNT_COUNT field. */
mbed_official 324:406fd2029f23 363 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
mbed_official 324:406fd2029f23 364
mbed_official 324:406fd2029f23 365 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
mbed_official 324:406fd2029f23 366 #define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
mbed_official 324:406fd2029f23 367
mbed_official 324:406fd2029f23 368 /*! @brief Set the COUNT field to a new value. */
mbed_official 324:406fd2029f23 369 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
mbed_official 324:406fd2029f23 370 /*@}*/
mbed_official 324:406fd2029f23 371
mbed_official 324:406fd2029f23 372 /*******************************************************************************
mbed_official 324:406fd2029f23 373 * HW_FTM_MOD - Modulo
mbed_official 324:406fd2029f23 374 ******************************************************************************/
mbed_official 324:406fd2029f23 375
mbed_official 324:406fd2029f23 376 /*!
mbed_official 324:406fd2029f23 377 * @brief HW_FTM_MOD - Modulo (RW)
mbed_official 324:406fd2029f23 378 *
mbed_official 324:406fd2029f23 379 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 380 *
mbed_official 324:406fd2029f23 381 * The Modulo register contains the modulo value for the FTM counter. After the
mbed_official 324:406fd2029f23 382 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
mbed_official 324:406fd2029f23 383 * the next clock, and the next value of FTM counter depends on the selected
mbed_official 324:406fd2029f23 384 * counting method; see Counter. Writing to the MOD register latches the value into a
mbed_official 324:406fd2029f23 385 * buffer. The MOD register is updated with the value of its write buffer
mbed_official 324:406fd2029f23 386 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
mbed_official 324:406fd2029f23 387 * mechanism may be manually reset by writing to the SC register whether BDM is
mbed_official 324:406fd2029f23 388 * active or not. Initialize the FTM counter, by writing to CNT, before writing
mbed_official 324:406fd2029f23 389 * to the MOD register to avoid confusion about when the first counter overflow
mbed_official 324:406fd2029f23 390 * will occur.
mbed_official 324:406fd2029f23 391 */
mbed_official 324:406fd2029f23 392 typedef union _hw_ftm_mod
mbed_official 324:406fd2029f23 393 {
mbed_official 324:406fd2029f23 394 uint32_t U;
mbed_official 324:406fd2029f23 395 struct _hw_ftm_mod_bitfields
mbed_official 324:406fd2029f23 396 {
mbed_official 324:406fd2029f23 397 uint32_t MOD : 16; /*!< [15:0] */
mbed_official 324:406fd2029f23 398 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 399 } B;
mbed_official 324:406fd2029f23 400 } hw_ftm_mod_t;
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /*!
mbed_official 324:406fd2029f23 403 * @name Constants and macros for entire FTM_MOD register
mbed_official 324:406fd2029f23 404 */
mbed_official 324:406fd2029f23 405 /*@{*/
mbed_official 324:406fd2029f23 406 #define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 407
mbed_official 324:406fd2029f23 408 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
mbed_official 324:406fd2029f23 409 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
mbed_official 324:406fd2029f23 410 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
mbed_official 324:406fd2029f23 411 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
mbed_official 324:406fd2029f23 412 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 413 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 414 /*@}*/
mbed_official 324:406fd2029f23 415
mbed_official 324:406fd2029f23 416 /*
mbed_official 324:406fd2029f23 417 * Constants & macros for individual FTM_MOD bitfields
mbed_official 324:406fd2029f23 418 */
mbed_official 324:406fd2029f23 419
mbed_official 324:406fd2029f23 420 /*!
mbed_official 324:406fd2029f23 421 * @name Register FTM_MOD, field MOD[15:0] (RW)
mbed_official 324:406fd2029f23 422 *
mbed_official 324:406fd2029f23 423 * Modulo Value
mbed_official 324:406fd2029f23 424 */
mbed_official 324:406fd2029f23 425 /*@{*/
mbed_official 324:406fd2029f23 426 #define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */
mbed_official 324:406fd2029f23 427 #define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
mbed_official 324:406fd2029f23 428 #define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */
mbed_official 324:406fd2029f23 429
mbed_official 324:406fd2029f23 430 /*! @brief Read current value of the FTM_MOD_MOD field. */
mbed_official 324:406fd2029f23 431 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Format value for bitfield FTM_MOD_MOD. */
mbed_official 324:406fd2029f23 434 #define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*! @brief Set the MOD field to a new value. */
mbed_official 324:406fd2029f23 437 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
mbed_official 324:406fd2029f23 438 /*@}*/
mbed_official 324:406fd2029f23 439
mbed_official 324:406fd2029f23 440 /*******************************************************************************
mbed_official 324:406fd2029f23 441 * HW_FTM_CnSC - Channel (n) Status And Control
mbed_official 324:406fd2029f23 442 ******************************************************************************/
mbed_official 324:406fd2029f23 443
mbed_official 324:406fd2029f23 444 /*!
mbed_official 324:406fd2029f23 445 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
mbed_official 324:406fd2029f23 446 *
mbed_official 324:406fd2029f23 447 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 448 *
mbed_official 324:406fd2029f23 449 * CnSC contains the channel-interrupt-status flag and control bits used to
mbed_official 324:406fd2029f23 450 * configure the interrupt enable, channel configuration, and pin function. Mode,
mbed_official 324:406fd2029f23 451 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
mbed_official 324:406fd2029f23 452 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
mbed_official 324:406fd2029f23 453 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
mbed_official 324:406fd2029f23 454 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
mbed_official 324:406fd2029f23 455 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
mbed_official 324:406fd2029f23 456 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
mbed_official 324:406fd2029f23 457 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
mbed_official 324:406fd2029f23 458 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
mbed_official 324:406fd2029f23 459 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
mbed_official 324:406fd2029f23 460 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
mbed_official 324:406fd2029f23 461 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
mbed_official 324:406fd2029f23 462 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
mbed_official 324:406fd2029f23 463 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
mbed_official 324:406fd2029f23 464 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
mbed_official 324:406fd2029f23 465 * Enabled Rising and falling edges
mbed_official 324:406fd2029f23 466 */
mbed_official 324:406fd2029f23 467 typedef union _hw_ftm_cnsc
mbed_official 324:406fd2029f23 468 {
mbed_official 324:406fd2029f23 469 uint32_t U;
mbed_official 324:406fd2029f23 470 struct _hw_ftm_cnsc_bitfields
mbed_official 324:406fd2029f23 471 {
mbed_official 324:406fd2029f23 472 uint32_t DMA : 1; /*!< [0] DMA Enable */
mbed_official 324:406fd2029f23 473 uint32_t RESERVED0 : 1; /*!< [1] */
mbed_official 324:406fd2029f23 474 uint32_t ELSA : 1; /*!< [2] Edge or Level Select */
mbed_official 324:406fd2029f23 475 uint32_t ELSB : 1; /*!< [3] Edge or Level Select */
mbed_official 324:406fd2029f23 476 uint32_t MSA : 1; /*!< [4] Channel Mode Select */
mbed_official 324:406fd2029f23 477 uint32_t MSB : 1; /*!< [5] Channel Mode Select */
mbed_official 324:406fd2029f23 478 uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */
mbed_official 324:406fd2029f23 479 uint32_t CHF : 1; /*!< [7] Channel Flag */
mbed_official 324:406fd2029f23 480 uint32_t RESERVED1 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 481 } B;
mbed_official 324:406fd2029f23 482 } hw_ftm_cnsc_t;
mbed_official 324:406fd2029f23 483
mbed_official 324:406fd2029f23 484 /*!
mbed_official 324:406fd2029f23 485 * @name Constants and macros for entire FTM_CnSC register
mbed_official 324:406fd2029f23 486 */
mbed_official 324:406fd2029f23 487 /*@{*/
mbed_official 324:406fd2029f23 488 #define HW_FTM_CnSC_COUNT (8U)
mbed_official 324:406fd2029f23 489
mbed_official 324:406fd2029f23 490 #define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
mbed_official 324:406fd2029f23 491
mbed_official 324:406fd2029f23 492 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
mbed_official 324:406fd2029f23 493 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
mbed_official 324:406fd2029f23 494 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
mbed_official 324:406fd2029f23 495 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 496 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 497 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 498 /*@}*/
mbed_official 324:406fd2029f23 499
mbed_official 324:406fd2029f23 500 /*
mbed_official 324:406fd2029f23 501 * Constants & macros for individual FTM_CnSC bitfields
mbed_official 324:406fd2029f23 502 */
mbed_official 324:406fd2029f23 503
mbed_official 324:406fd2029f23 504 /*!
mbed_official 324:406fd2029f23 505 * @name Register FTM_CnSC, field DMA[0] (RW)
mbed_official 324:406fd2029f23 506 *
mbed_official 324:406fd2029f23 507 * Enables DMA transfers for the channel.
mbed_official 324:406fd2029f23 508 *
mbed_official 324:406fd2029f23 509 * Values:
mbed_official 324:406fd2029f23 510 * - 0 - Disable DMA transfers.
mbed_official 324:406fd2029f23 511 * - 1 - Enable DMA transfers.
mbed_official 324:406fd2029f23 512 */
mbed_official 324:406fd2029f23 513 /*@{*/
mbed_official 324:406fd2029f23 514 #define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */
mbed_official 324:406fd2029f23 515 #define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
mbed_official 324:406fd2029f23 516 #define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */
mbed_official 324:406fd2029f23 517
mbed_official 324:406fd2029f23 518 /*! @brief Read current value of the FTM_CnSC_DMA field. */
mbed_official 324:406fd2029f23 519 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
mbed_official 324:406fd2029f23 520
mbed_official 324:406fd2029f23 521 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
mbed_official 324:406fd2029f23 522 #define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
mbed_official 324:406fd2029f23 523
mbed_official 324:406fd2029f23 524 /*! @brief Set the DMA field to a new value. */
mbed_official 324:406fd2029f23 525 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
mbed_official 324:406fd2029f23 526 /*@}*/
mbed_official 324:406fd2029f23 527
mbed_official 324:406fd2029f23 528 /*!
mbed_official 324:406fd2029f23 529 * @name Register FTM_CnSC, field ELSA[2] (RW)
mbed_official 324:406fd2029f23 530 *
mbed_official 324:406fd2029f23 531 * The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official 324:406fd2029f23 532 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official 324:406fd2029f23 533 * = 1.
mbed_official 324:406fd2029f23 534 */
mbed_official 324:406fd2029f23 535 /*@{*/
mbed_official 324:406fd2029f23 536 #define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */
mbed_official 324:406fd2029f23 537 #define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
mbed_official 324:406fd2029f23 538 #define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */
mbed_official 324:406fd2029f23 539
mbed_official 324:406fd2029f23 540 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
mbed_official 324:406fd2029f23 541 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
mbed_official 324:406fd2029f23 542
mbed_official 324:406fd2029f23 543 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
mbed_official 324:406fd2029f23 544 #define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
mbed_official 324:406fd2029f23 545
mbed_official 324:406fd2029f23 546 /*! @brief Set the ELSA field to a new value. */
mbed_official 324:406fd2029f23 547 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
mbed_official 324:406fd2029f23 548 /*@}*/
mbed_official 324:406fd2029f23 549
mbed_official 324:406fd2029f23 550 /*!
mbed_official 324:406fd2029f23 551 * @name Register FTM_CnSC, field ELSB[3] (RW)
mbed_official 324:406fd2029f23 552 *
mbed_official 324:406fd2029f23 553 * The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official 324:406fd2029f23 554 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official 324:406fd2029f23 555 * = 1.
mbed_official 324:406fd2029f23 556 */
mbed_official 324:406fd2029f23 557 /*@{*/
mbed_official 324:406fd2029f23 558 #define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */
mbed_official 324:406fd2029f23 559 #define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
mbed_official 324:406fd2029f23 560 #define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */
mbed_official 324:406fd2029f23 561
mbed_official 324:406fd2029f23 562 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
mbed_official 324:406fd2029f23 563 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
mbed_official 324:406fd2029f23 564
mbed_official 324:406fd2029f23 565 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
mbed_official 324:406fd2029f23 566 #define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
mbed_official 324:406fd2029f23 567
mbed_official 324:406fd2029f23 568 /*! @brief Set the ELSB field to a new value. */
mbed_official 324:406fd2029f23 569 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
mbed_official 324:406fd2029f23 570 /*@}*/
mbed_official 324:406fd2029f23 571
mbed_official 324:406fd2029f23 572 /*!
mbed_official 324:406fd2029f23 573 * @name Register FTM_CnSC, field MSA[4] (RW)
mbed_official 324:406fd2029f23 574 *
mbed_official 324:406fd2029f23 575 * Used for further selections in the channel logic. Its functionality is
mbed_official 324:406fd2029f23 576 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official 324:406fd2029f23 577 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 578 */
mbed_official 324:406fd2029f23 579 /*@{*/
mbed_official 324:406fd2029f23 580 #define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */
mbed_official 324:406fd2029f23 581 #define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
mbed_official 324:406fd2029f23 582 #define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */
mbed_official 324:406fd2029f23 583
mbed_official 324:406fd2029f23 584 /*! @brief Read current value of the FTM_CnSC_MSA field. */
mbed_official 324:406fd2029f23 585 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
mbed_official 324:406fd2029f23 588 #define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
mbed_official 324:406fd2029f23 589
mbed_official 324:406fd2029f23 590 /*! @brief Set the MSA field to a new value. */
mbed_official 324:406fd2029f23 591 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
mbed_official 324:406fd2029f23 592 /*@}*/
mbed_official 324:406fd2029f23 593
mbed_official 324:406fd2029f23 594 /*!
mbed_official 324:406fd2029f23 595 * @name Register FTM_CnSC, field MSB[5] (RW)
mbed_official 324:406fd2029f23 596 *
mbed_official 324:406fd2029f23 597 * Used for further selections in the channel logic. Its functionality is
mbed_official 324:406fd2029f23 598 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official 324:406fd2029f23 599 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 600 */
mbed_official 324:406fd2029f23 601 /*@{*/
mbed_official 324:406fd2029f23 602 #define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */
mbed_official 324:406fd2029f23 603 #define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
mbed_official 324:406fd2029f23 604 #define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */
mbed_official 324:406fd2029f23 605
mbed_official 324:406fd2029f23 606 /*! @brief Read current value of the FTM_CnSC_MSB field. */
mbed_official 324:406fd2029f23 607 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
mbed_official 324:406fd2029f23 608
mbed_official 324:406fd2029f23 609 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
mbed_official 324:406fd2029f23 610 #define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
mbed_official 324:406fd2029f23 611
mbed_official 324:406fd2029f23 612 /*! @brief Set the MSB field to a new value. */
mbed_official 324:406fd2029f23 613 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
mbed_official 324:406fd2029f23 614 /*@}*/
mbed_official 324:406fd2029f23 615
mbed_official 324:406fd2029f23 616 /*!
mbed_official 324:406fd2029f23 617 * @name Register FTM_CnSC, field CHIE[6] (RW)
mbed_official 324:406fd2029f23 618 *
mbed_official 324:406fd2029f23 619 * Enables channel interrupts.
mbed_official 324:406fd2029f23 620 *
mbed_official 324:406fd2029f23 621 * Values:
mbed_official 324:406fd2029f23 622 * - 0 - Disable channel interrupts. Use software polling.
mbed_official 324:406fd2029f23 623 * - 1 - Enable channel interrupts.
mbed_official 324:406fd2029f23 624 */
mbed_official 324:406fd2029f23 625 /*@{*/
mbed_official 324:406fd2029f23 626 #define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */
mbed_official 324:406fd2029f23 627 #define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
mbed_official 324:406fd2029f23 628 #define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */
mbed_official 324:406fd2029f23 629
mbed_official 324:406fd2029f23 630 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
mbed_official 324:406fd2029f23 631 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
mbed_official 324:406fd2029f23 632
mbed_official 324:406fd2029f23 633 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
mbed_official 324:406fd2029f23 634 #define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
mbed_official 324:406fd2029f23 635
mbed_official 324:406fd2029f23 636 /*! @brief Set the CHIE field to a new value. */
mbed_official 324:406fd2029f23 637 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
mbed_official 324:406fd2029f23 638 /*@}*/
mbed_official 324:406fd2029f23 639
mbed_official 324:406fd2029f23 640 /*!
mbed_official 324:406fd2029f23 641 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
mbed_official 324:406fd2029f23 642 *
mbed_official 324:406fd2029f23 643 * Set by hardware when an event occurs on the channel. CHF is cleared by
mbed_official 324:406fd2029f23 644 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
mbed_official 324:406fd2029f23 645 * Writing a 1 to CHF has no effect. If another event occurs between the read and
mbed_official 324:406fd2029f23 646 * write operations, the write operation has no effect; therefore, CHF remains set
mbed_official 324:406fd2029f23 647 * indicating an event has occurred. In this case a CHF interrupt request is not
mbed_official 324:406fd2029f23 648 * lost due to the clearing sequence for a previous CHF.
mbed_official 324:406fd2029f23 649 *
mbed_official 324:406fd2029f23 650 * Values:
mbed_official 324:406fd2029f23 651 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 652 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 653 */
mbed_official 324:406fd2029f23 654 /*@{*/
mbed_official 324:406fd2029f23 655 #define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */
mbed_official 324:406fd2029f23 656 #define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
mbed_official 324:406fd2029f23 657 #define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */
mbed_official 324:406fd2029f23 658
mbed_official 324:406fd2029f23 659 /*! @brief Read current value of the FTM_CnSC_CHF field. */
mbed_official 324:406fd2029f23 660 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
mbed_official 324:406fd2029f23 661
mbed_official 324:406fd2029f23 662 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
mbed_official 324:406fd2029f23 663 #define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
mbed_official 324:406fd2029f23 664
mbed_official 324:406fd2029f23 665 /*! @brief Set the CHF field to a new value. */
mbed_official 324:406fd2029f23 666 #define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
mbed_official 324:406fd2029f23 667 /*@}*/
mbed_official 324:406fd2029f23 668 /*******************************************************************************
mbed_official 324:406fd2029f23 669 * HW_FTM_CnV - Channel (n) Value
mbed_official 324:406fd2029f23 670 ******************************************************************************/
mbed_official 324:406fd2029f23 671
mbed_official 324:406fd2029f23 672 /*!
mbed_official 324:406fd2029f23 673 * @brief HW_FTM_CnV - Channel (n) Value (RW)
mbed_official 324:406fd2029f23 674 *
mbed_official 324:406fd2029f23 675 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 676 *
mbed_official 324:406fd2029f23 677 * These registers contain the captured FTM counter value for the input modes or
mbed_official 324:406fd2029f23 678 * the match value for the output modes. In Input Capture, Capture Test, and
mbed_official 324:406fd2029f23 679 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
mbed_official 324:406fd2029f23 680 * writing to a CnV register latches the value into a buffer. A CnV register is
mbed_official 324:406fd2029f23 681 * updated with the value of its write buffer according to Registers updated from
mbed_official 324:406fd2029f23 682 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
mbed_official 324:406fd2029f23 683 * reset by writing to the CnSC register whether BDM mode is active or not.
mbed_official 324:406fd2029f23 684 */
mbed_official 324:406fd2029f23 685 typedef union _hw_ftm_cnv
mbed_official 324:406fd2029f23 686 {
mbed_official 324:406fd2029f23 687 uint32_t U;
mbed_official 324:406fd2029f23 688 struct _hw_ftm_cnv_bitfields
mbed_official 324:406fd2029f23 689 {
mbed_official 324:406fd2029f23 690 uint32_t VAL : 16; /*!< [15:0] Channel Value */
mbed_official 324:406fd2029f23 691 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 692 } B;
mbed_official 324:406fd2029f23 693 } hw_ftm_cnv_t;
mbed_official 324:406fd2029f23 694
mbed_official 324:406fd2029f23 695 /*!
mbed_official 324:406fd2029f23 696 * @name Constants and macros for entire FTM_CnV register
mbed_official 324:406fd2029f23 697 */
mbed_official 324:406fd2029f23 698 /*@{*/
mbed_official 324:406fd2029f23 699 #define HW_FTM_CnV_COUNT (8U)
mbed_official 324:406fd2029f23 700
mbed_official 324:406fd2029f23 701 #define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
mbed_official 324:406fd2029f23 702
mbed_official 324:406fd2029f23 703 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
mbed_official 324:406fd2029f23 704 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
mbed_official 324:406fd2029f23 705 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
mbed_official 324:406fd2029f23 706 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 707 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 708 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 709 /*@}*/
mbed_official 324:406fd2029f23 710
mbed_official 324:406fd2029f23 711 /*
mbed_official 324:406fd2029f23 712 * Constants & macros for individual FTM_CnV bitfields
mbed_official 324:406fd2029f23 713 */
mbed_official 324:406fd2029f23 714
mbed_official 324:406fd2029f23 715 /*!
mbed_official 324:406fd2029f23 716 * @name Register FTM_CnV, field VAL[15:0] (RW)
mbed_official 324:406fd2029f23 717 *
mbed_official 324:406fd2029f23 718 * Captured FTM counter value of the input modes or the match value for the
mbed_official 324:406fd2029f23 719 * output modes
mbed_official 324:406fd2029f23 720 */
mbed_official 324:406fd2029f23 721 /*@{*/
mbed_official 324:406fd2029f23 722 #define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */
mbed_official 324:406fd2029f23 723 #define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
mbed_official 324:406fd2029f23 724 #define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */
mbed_official 324:406fd2029f23 725
mbed_official 324:406fd2029f23 726 /*! @brief Read current value of the FTM_CnV_VAL field. */
mbed_official 324:406fd2029f23 727 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
mbed_official 324:406fd2029f23 728
mbed_official 324:406fd2029f23 729 /*! @brief Format value for bitfield FTM_CnV_VAL. */
mbed_official 324:406fd2029f23 730 #define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
mbed_official 324:406fd2029f23 731
mbed_official 324:406fd2029f23 732 /*! @brief Set the VAL field to a new value. */
mbed_official 324:406fd2029f23 733 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
mbed_official 324:406fd2029f23 734 /*@}*/
mbed_official 324:406fd2029f23 735
mbed_official 324:406fd2029f23 736 /*******************************************************************************
mbed_official 324:406fd2029f23 737 * HW_FTM_CNTIN - Counter Initial Value
mbed_official 324:406fd2029f23 738 ******************************************************************************/
mbed_official 324:406fd2029f23 739
mbed_official 324:406fd2029f23 740 /*!
mbed_official 324:406fd2029f23 741 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
mbed_official 324:406fd2029f23 742 *
mbed_official 324:406fd2029f23 743 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 744 *
mbed_official 324:406fd2029f23 745 * The Counter Initial Value register contains the initial value for the FTM
mbed_official 324:406fd2029f23 746 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
mbed_official 324:406fd2029f23 747 * register is updated with the value of its write buffer according to Registers
mbed_official 324:406fd2029f23 748 * updated from write buffers. When the FTM clock is initially selected, by
mbed_official 324:406fd2029f23 749 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
mbed_official 324:406fd2029f23 750 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
mbed_official 324:406fd2029f23 751 * write the new value to the the CNTIN register and then initialize the FTM
mbed_official 324:406fd2029f23 752 * counter by writing any value to the CNT register.
mbed_official 324:406fd2029f23 753 */
mbed_official 324:406fd2029f23 754 typedef union _hw_ftm_cntin
mbed_official 324:406fd2029f23 755 {
mbed_official 324:406fd2029f23 756 uint32_t U;
mbed_official 324:406fd2029f23 757 struct _hw_ftm_cntin_bitfields
mbed_official 324:406fd2029f23 758 {
mbed_official 324:406fd2029f23 759 uint32_t INIT : 16; /*!< [15:0] */
mbed_official 324:406fd2029f23 760 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 761 } B;
mbed_official 324:406fd2029f23 762 } hw_ftm_cntin_t;
mbed_official 324:406fd2029f23 763
mbed_official 324:406fd2029f23 764 /*!
mbed_official 324:406fd2029f23 765 * @name Constants and macros for entire FTM_CNTIN register
mbed_official 324:406fd2029f23 766 */
mbed_official 324:406fd2029f23 767 /*@{*/
mbed_official 324:406fd2029f23 768 #define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
mbed_official 324:406fd2029f23 769
mbed_official 324:406fd2029f23 770 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
mbed_official 324:406fd2029f23 771 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
mbed_official 324:406fd2029f23 772 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
mbed_official 324:406fd2029f23 773 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
mbed_official 324:406fd2029f23 774 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 775 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 776 /*@}*/
mbed_official 324:406fd2029f23 777
mbed_official 324:406fd2029f23 778 /*
mbed_official 324:406fd2029f23 779 * Constants & macros for individual FTM_CNTIN bitfields
mbed_official 324:406fd2029f23 780 */
mbed_official 324:406fd2029f23 781
mbed_official 324:406fd2029f23 782 /*!
mbed_official 324:406fd2029f23 783 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
mbed_official 324:406fd2029f23 784 *
mbed_official 324:406fd2029f23 785 * Initial Value Of The FTM Counter
mbed_official 324:406fd2029f23 786 */
mbed_official 324:406fd2029f23 787 /*@{*/
mbed_official 324:406fd2029f23 788 #define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */
mbed_official 324:406fd2029f23 789 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
mbed_official 324:406fd2029f23 790 #define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */
mbed_official 324:406fd2029f23 791
mbed_official 324:406fd2029f23 792 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
mbed_official 324:406fd2029f23 793 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
mbed_official 324:406fd2029f23 794
mbed_official 324:406fd2029f23 795 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
mbed_official 324:406fd2029f23 796 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
mbed_official 324:406fd2029f23 797
mbed_official 324:406fd2029f23 798 /*! @brief Set the INIT field to a new value. */
mbed_official 324:406fd2029f23 799 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
mbed_official 324:406fd2029f23 800 /*@}*/
mbed_official 324:406fd2029f23 801
mbed_official 324:406fd2029f23 802 /*******************************************************************************
mbed_official 324:406fd2029f23 803 * HW_FTM_STATUS - Capture And Compare Status
mbed_official 324:406fd2029f23 804 ******************************************************************************/
mbed_official 324:406fd2029f23 805
mbed_official 324:406fd2029f23 806 /*!
mbed_official 324:406fd2029f23 807 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
mbed_official 324:406fd2029f23 808 *
mbed_official 324:406fd2029f23 809 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 810 *
mbed_official 324:406fd2029f23 811 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
mbed_official 324:406fd2029f23 812 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
mbed_official 324:406fd2029f23 813 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
mbed_official 324:406fd2029f23 814 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
mbed_official 324:406fd2029f23 815 * STATUS. Hardware sets the individual channel flags when an event occurs on the
mbed_official 324:406fd2029f23 816 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
mbed_official 324:406fd2029f23 817 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
mbed_official 324:406fd2029f23 818 * occurs between the read and write operations, the write operation has no effect;
mbed_official 324:406fd2029f23 819 * therefore, CHnF remains set indicating an event has occurred. In this case, a
mbed_official 324:406fd2029f23 820 * CHnF interrupt request is not lost due to the clearing sequence for a previous
mbed_official 324:406fd2029f23 821 * CHnF. The STATUS register should be used only in Combine mode.
mbed_official 324:406fd2029f23 822 */
mbed_official 324:406fd2029f23 823 typedef union _hw_ftm_status
mbed_official 324:406fd2029f23 824 {
mbed_official 324:406fd2029f23 825 uint32_t U;
mbed_official 324:406fd2029f23 826 struct _hw_ftm_status_bitfields
mbed_official 324:406fd2029f23 827 {
mbed_official 324:406fd2029f23 828 uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */
mbed_official 324:406fd2029f23 829 uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */
mbed_official 324:406fd2029f23 830 uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */
mbed_official 324:406fd2029f23 831 uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */
mbed_official 324:406fd2029f23 832 uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */
mbed_official 324:406fd2029f23 833 uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */
mbed_official 324:406fd2029f23 834 uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */
mbed_official 324:406fd2029f23 835 uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */
mbed_official 324:406fd2029f23 836 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 837 } B;
mbed_official 324:406fd2029f23 838 } hw_ftm_status_t;
mbed_official 324:406fd2029f23 839
mbed_official 324:406fd2029f23 840 /*!
mbed_official 324:406fd2029f23 841 * @name Constants and macros for entire FTM_STATUS register
mbed_official 324:406fd2029f23 842 */
mbed_official 324:406fd2029f23 843 /*@{*/
mbed_official 324:406fd2029f23 844 #define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
mbed_official 324:406fd2029f23 845
mbed_official 324:406fd2029f23 846 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
mbed_official 324:406fd2029f23 847 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
mbed_official 324:406fd2029f23 848 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
mbed_official 324:406fd2029f23 849 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
mbed_official 324:406fd2029f23 850 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 851 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 852 /*@}*/
mbed_official 324:406fd2029f23 853
mbed_official 324:406fd2029f23 854 /*
mbed_official 324:406fd2029f23 855 * Constants & macros for individual FTM_STATUS bitfields
mbed_official 324:406fd2029f23 856 */
mbed_official 324:406fd2029f23 857
mbed_official 324:406fd2029f23 858 /*!
mbed_official 324:406fd2029f23 859 * @name Register FTM_STATUS, field CH0F[0] (W1C)
mbed_official 324:406fd2029f23 860 *
mbed_official 324:406fd2029f23 861 * See the register description.
mbed_official 324:406fd2029f23 862 *
mbed_official 324:406fd2029f23 863 * Values:
mbed_official 324:406fd2029f23 864 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 865 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 866 */
mbed_official 324:406fd2029f23 867 /*@{*/
mbed_official 324:406fd2029f23 868 #define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */
mbed_official 324:406fd2029f23 869 #define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
mbed_official 324:406fd2029f23 870 #define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */
mbed_official 324:406fd2029f23 871
mbed_official 324:406fd2029f23 872 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
mbed_official 324:406fd2029f23 873 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
mbed_official 324:406fd2029f23 874
mbed_official 324:406fd2029f23 875 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
mbed_official 324:406fd2029f23 876 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
mbed_official 324:406fd2029f23 877
mbed_official 324:406fd2029f23 878 /*! @brief Set the CH0F field to a new value. */
mbed_official 324:406fd2029f23 879 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
mbed_official 324:406fd2029f23 880 /*@}*/
mbed_official 324:406fd2029f23 881
mbed_official 324:406fd2029f23 882 /*!
mbed_official 324:406fd2029f23 883 * @name Register FTM_STATUS, field CH1F[1] (W1C)
mbed_official 324:406fd2029f23 884 *
mbed_official 324:406fd2029f23 885 * See the register description.
mbed_official 324:406fd2029f23 886 *
mbed_official 324:406fd2029f23 887 * Values:
mbed_official 324:406fd2029f23 888 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 889 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 890 */
mbed_official 324:406fd2029f23 891 /*@{*/
mbed_official 324:406fd2029f23 892 #define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */
mbed_official 324:406fd2029f23 893 #define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
mbed_official 324:406fd2029f23 894 #define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */
mbed_official 324:406fd2029f23 895
mbed_official 324:406fd2029f23 896 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
mbed_official 324:406fd2029f23 897 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
mbed_official 324:406fd2029f23 898
mbed_official 324:406fd2029f23 899 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
mbed_official 324:406fd2029f23 900 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
mbed_official 324:406fd2029f23 901
mbed_official 324:406fd2029f23 902 /*! @brief Set the CH1F field to a new value. */
mbed_official 324:406fd2029f23 903 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
mbed_official 324:406fd2029f23 904 /*@}*/
mbed_official 324:406fd2029f23 905
mbed_official 324:406fd2029f23 906 /*!
mbed_official 324:406fd2029f23 907 * @name Register FTM_STATUS, field CH2F[2] (W1C)
mbed_official 324:406fd2029f23 908 *
mbed_official 324:406fd2029f23 909 * See the register description.
mbed_official 324:406fd2029f23 910 *
mbed_official 324:406fd2029f23 911 * Values:
mbed_official 324:406fd2029f23 912 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 913 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 914 */
mbed_official 324:406fd2029f23 915 /*@{*/
mbed_official 324:406fd2029f23 916 #define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */
mbed_official 324:406fd2029f23 917 #define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
mbed_official 324:406fd2029f23 918 #define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */
mbed_official 324:406fd2029f23 919
mbed_official 324:406fd2029f23 920 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
mbed_official 324:406fd2029f23 921 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
mbed_official 324:406fd2029f23 922
mbed_official 324:406fd2029f23 923 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
mbed_official 324:406fd2029f23 924 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
mbed_official 324:406fd2029f23 925
mbed_official 324:406fd2029f23 926 /*! @brief Set the CH2F field to a new value. */
mbed_official 324:406fd2029f23 927 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
mbed_official 324:406fd2029f23 928 /*@}*/
mbed_official 324:406fd2029f23 929
mbed_official 324:406fd2029f23 930 /*!
mbed_official 324:406fd2029f23 931 * @name Register FTM_STATUS, field CH3F[3] (W1C)
mbed_official 324:406fd2029f23 932 *
mbed_official 324:406fd2029f23 933 * See the register description.
mbed_official 324:406fd2029f23 934 *
mbed_official 324:406fd2029f23 935 * Values:
mbed_official 324:406fd2029f23 936 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 937 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 938 */
mbed_official 324:406fd2029f23 939 /*@{*/
mbed_official 324:406fd2029f23 940 #define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */
mbed_official 324:406fd2029f23 941 #define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
mbed_official 324:406fd2029f23 942 #define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */
mbed_official 324:406fd2029f23 943
mbed_official 324:406fd2029f23 944 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
mbed_official 324:406fd2029f23 945 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
mbed_official 324:406fd2029f23 946
mbed_official 324:406fd2029f23 947 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
mbed_official 324:406fd2029f23 948 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
mbed_official 324:406fd2029f23 949
mbed_official 324:406fd2029f23 950 /*! @brief Set the CH3F field to a new value. */
mbed_official 324:406fd2029f23 951 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
mbed_official 324:406fd2029f23 952 /*@}*/
mbed_official 324:406fd2029f23 953
mbed_official 324:406fd2029f23 954 /*!
mbed_official 324:406fd2029f23 955 * @name Register FTM_STATUS, field CH4F[4] (W1C)
mbed_official 324:406fd2029f23 956 *
mbed_official 324:406fd2029f23 957 * See the register description.
mbed_official 324:406fd2029f23 958 *
mbed_official 324:406fd2029f23 959 * Values:
mbed_official 324:406fd2029f23 960 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 961 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 962 */
mbed_official 324:406fd2029f23 963 /*@{*/
mbed_official 324:406fd2029f23 964 #define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */
mbed_official 324:406fd2029f23 965 #define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
mbed_official 324:406fd2029f23 966 #define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */
mbed_official 324:406fd2029f23 967
mbed_official 324:406fd2029f23 968 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
mbed_official 324:406fd2029f23 969 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
mbed_official 324:406fd2029f23 970
mbed_official 324:406fd2029f23 971 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
mbed_official 324:406fd2029f23 972 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
mbed_official 324:406fd2029f23 973
mbed_official 324:406fd2029f23 974 /*! @brief Set the CH4F field to a new value. */
mbed_official 324:406fd2029f23 975 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
mbed_official 324:406fd2029f23 976 /*@}*/
mbed_official 324:406fd2029f23 977
mbed_official 324:406fd2029f23 978 /*!
mbed_official 324:406fd2029f23 979 * @name Register FTM_STATUS, field CH5F[5] (W1C)
mbed_official 324:406fd2029f23 980 *
mbed_official 324:406fd2029f23 981 * See the register description.
mbed_official 324:406fd2029f23 982 *
mbed_official 324:406fd2029f23 983 * Values:
mbed_official 324:406fd2029f23 984 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 985 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 986 */
mbed_official 324:406fd2029f23 987 /*@{*/
mbed_official 324:406fd2029f23 988 #define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */
mbed_official 324:406fd2029f23 989 #define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
mbed_official 324:406fd2029f23 990 #define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */
mbed_official 324:406fd2029f23 991
mbed_official 324:406fd2029f23 992 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
mbed_official 324:406fd2029f23 993 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
mbed_official 324:406fd2029f23 994
mbed_official 324:406fd2029f23 995 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
mbed_official 324:406fd2029f23 996 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
mbed_official 324:406fd2029f23 997
mbed_official 324:406fd2029f23 998 /*! @brief Set the CH5F field to a new value. */
mbed_official 324:406fd2029f23 999 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
mbed_official 324:406fd2029f23 1000 /*@}*/
mbed_official 324:406fd2029f23 1001
mbed_official 324:406fd2029f23 1002 /*!
mbed_official 324:406fd2029f23 1003 * @name Register FTM_STATUS, field CH6F[6] (W1C)
mbed_official 324:406fd2029f23 1004 *
mbed_official 324:406fd2029f23 1005 * See the register description.
mbed_official 324:406fd2029f23 1006 *
mbed_official 324:406fd2029f23 1007 * Values:
mbed_official 324:406fd2029f23 1008 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 1009 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 1010 */
mbed_official 324:406fd2029f23 1011 /*@{*/
mbed_official 324:406fd2029f23 1012 #define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */
mbed_official 324:406fd2029f23 1013 #define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
mbed_official 324:406fd2029f23 1014 #define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */
mbed_official 324:406fd2029f23 1015
mbed_official 324:406fd2029f23 1016 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
mbed_official 324:406fd2029f23 1017 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
mbed_official 324:406fd2029f23 1018
mbed_official 324:406fd2029f23 1019 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
mbed_official 324:406fd2029f23 1020 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
mbed_official 324:406fd2029f23 1021
mbed_official 324:406fd2029f23 1022 /*! @brief Set the CH6F field to a new value. */
mbed_official 324:406fd2029f23 1023 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
mbed_official 324:406fd2029f23 1024 /*@}*/
mbed_official 324:406fd2029f23 1025
mbed_official 324:406fd2029f23 1026 /*!
mbed_official 324:406fd2029f23 1027 * @name Register FTM_STATUS, field CH7F[7] (W1C)
mbed_official 324:406fd2029f23 1028 *
mbed_official 324:406fd2029f23 1029 * See the register description.
mbed_official 324:406fd2029f23 1030 *
mbed_official 324:406fd2029f23 1031 * Values:
mbed_official 324:406fd2029f23 1032 * - 0 - No channel event has occurred.
mbed_official 324:406fd2029f23 1033 * - 1 - A channel event has occurred.
mbed_official 324:406fd2029f23 1034 */
mbed_official 324:406fd2029f23 1035 /*@{*/
mbed_official 324:406fd2029f23 1036 #define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */
mbed_official 324:406fd2029f23 1037 #define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
mbed_official 324:406fd2029f23 1038 #define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */
mbed_official 324:406fd2029f23 1039
mbed_official 324:406fd2029f23 1040 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
mbed_official 324:406fd2029f23 1041 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
mbed_official 324:406fd2029f23 1042
mbed_official 324:406fd2029f23 1043 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
mbed_official 324:406fd2029f23 1044 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
mbed_official 324:406fd2029f23 1045
mbed_official 324:406fd2029f23 1046 /*! @brief Set the CH7F field to a new value. */
mbed_official 324:406fd2029f23 1047 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
mbed_official 324:406fd2029f23 1048 /*@}*/
mbed_official 324:406fd2029f23 1049
mbed_official 324:406fd2029f23 1050 /*******************************************************************************
mbed_official 324:406fd2029f23 1051 * HW_FTM_MODE - Features Mode Selection
mbed_official 324:406fd2029f23 1052 ******************************************************************************/
mbed_official 324:406fd2029f23 1053
mbed_official 324:406fd2029f23 1054 /*!
mbed_official 324:406fd2029f23 1055 * @brief HW_FTM_MODE - Features Mode Selection (RW)
mbed_official 324:406fd2029f23 1056 *
mbed_official 324:406fd2029f23 1057 * Reset value: 0x00000004U
mbed_official 324:406fd2029f23 1058 *
mbed_official 324:406fd2029f23 1059 * This register contains the global enable bit for FTM-specific features and
mbed_official 324:406fd2029f23 1060 * the control bits used to configure: Fault control mode and interrupt Capture
mbed_official 324:406fd2029f23 1061 * Test mode PWM synchronization Write protection Channel output initialization
mbed_official 324:406fd2029f23 1062 * These controls relate to all channels within this module.
mbed_official 324:406fd2029f23 1063 */
mbed_official 324:406fd2029f23 1064 typedef union _hw_ftm_mode
mbed_official 324:406fd2029f23 1065 {
mbed_official 324:406fd2029f23 1066 uint32_t U;
mbed_official 324:406fd2029f23 1067 struct _hw_ftm_mode_bitfields
mbed_official 324:406fd2029f23 1068 {
mbed_official 324:406fd2029f23 1069 uint32_t FTMEN : 1; /*!< [0] FTM Enable */
mbed_official 324:406fd2029f23 1070 uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */
mbed_official 324:406fd2029f23 1071 uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */
mbed_official 324:406fd2029f23 1072 uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */
mbed_official 324:406fd2029f23 1073 uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */
mbed_official 324:406fd2029f23 1074 uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */
mbed_official 324:406fd2029f23 1075 uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */
mbed_official 324:406fd2029f23 1076 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1077 } B;
mbed_official 324:406fd2029f23 1078 } hw_ftm_mode_t;
mbed_official 324:406fd2029f23 1079
mbed_official 324:406fd2029f23 1080 /*!
mbed_official 324:406fd2029f23 1081 * @name Constants and macros for entire FTM_MODE register
mbed_official 324:406fd2029f23 1082 */
mbed_official 324:406fd2029f23 1083 /*@{*/
mbed_official 324:406fd2029f23 1084 #define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
mbed_official 324:406fd2029f23 1085
mbed_official 324:406fd2029f23 1086 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
mbed_official 324:406fd2029f23 1087 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
mbed_official 324:406fd2029f23 1088 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
mbed_official 324:406fd2029f23 1089 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
mbed_official 324:406fd2029f23 1090 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1091 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1092 /*@}*/
mbed_official 324:406fd2029f23 1093
mbed_official 324:406fd2029f23 1094 /*
mbed_official 324:406fd2029f23 1095 * Constants & macros for individual FTM_MODE bitfields
mbed_official 324:406fd2029f23 1096 */
mbed_official 324:406fd2029f23 1097
mbed_official 324:406fd2029f23 1098 /*!
mbed_official 324:406fd2029f23 1099 * @name Register FTM_MODE, field FTMEN[0] (RW)
mbed_official 324:406fd2029f23 1100 *
mbed_official 324:406fd2029f23 1101 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 1102 *
mbed_official 324:406fd2029f23 1103 * Values:
mbed_official 324:406fd2029f23 1104 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
mbed_official 324:406fd2029f23 1105 * without any restriction. Do not use the FTM-specific registers.
mbed_official 324:406fd2029f23 1106 * - 1 - All registers including the FTM-specific registers (second set of
mbed_official 324:406fd2029f23 1107 * registers) are available for use with no restrictions.
mbed_official 324:406fd2029f23 1108 */
mbed_official 324:406fd2029f23 1109 /*@{*/
mbed_official 324:406fd2029f23 1110 #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
mbed_official 324:406fd2029f23 1111 #define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
mbed_official 324:406fd2029f23 1112 #define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */
mbed_official 324:406fd2029f23 1113
mbed_official 324:406fd2029f23 1114 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
mbed_official 324:406fd2029f23 1115 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
mbed_official 324:406fd2029f23 1116
mbed_official 324:406fd2029f23 1117 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
mbed_official 324:406fd2029f23 1118 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
mbed_official 324:406fd2029f23 1119
mbed_official 324:406fd2029f23 1120 /*! @brief Set the FTMEN field to a new value. */
mbed_official 324:406fd2029f23 1121 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
mbed_official 324:406fd2029f23 1122 /*@}*/
mbed_official 324:406fd2029f23 1123
mbed_official 324:406fd2029f23 1124 /*!
mbed_official 324:406fd2029f23 1125 * @name Register FTM_MODE, field INIT[1] (RW)
mbed_official 324:406fd2029f23 1126 *
mbed_official 324:406fd2029f23 1127 * When a 1 is written to INIT bit the channels output is initialized according
mbed_official 324:406fd2029f23 1128 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
mbed_official 324:406fd2029f23 1129 * to INIT bit has no effect. The INIT bit is always read as 0.
mbed_official 324:406fd2029f23 1130 */
mbed_official 324:406fd2029f23 1131 /*@{*/
mbed_official 324:406fd2029f23 1132 #define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */
mbed_official 324:406fd2029f23 1133 #define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
mbed_official 324:406fd2029f23 1134 #define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */
mbed_official 324:406fd2029f23 1135
mbed_official 324:406fd2029f23 1136 /*! @brief Read current value of the FTM_MODE_INIT field. */
mbed_official 324:406fd2029f23 1137 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
mbed_official 324:406fd2029f23 1138
mbed_official 324:406fd2029f23 1139 /*! @brief Format value for bitfield FTM_MODE_INIT. */
mbed_official 324:406fd2029f23 1140 #define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
mbed_official 324:406fd2029f23 1141
mbed_official 324:406fd2029f23 1142 /*! @brief Set the INIT field to a new value. */
mbed_official 324:406fd2029f23 1143 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
mbed_official 324:406fd2029f23 1144 /*@}*/
mbed_official 324:406fd2029f23 1145
mbed_official 324:406fd2029f23 1146 /*!
mbed_official 324:406fd2029f23 1147 * @name Register FTM_MODE, field WPDIS[2] (RW)
mbed_official 324:406fd2029f23 1148 *
mbed_official 324:406fd2029f23 1149 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
mbed_official 324:406fd2029f23 1150 * written. When write protection is disabled (WPDIS = 1), write protected bits
mbed_official 324:406fd2029f23 1151 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
mbed_official 324:406fd2029f23 1152 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
mbed_official 324:406fd2029f23 1153 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
mbed_official 324:406fd2029f23 1154 *
mbed_official 324:406fd2029f23 1155 * Values:
mbed_official 324:406fd2029f23 1156 * - 0 - Write protection is enabled.
mbed_official 324:406fd2029f23 1157 * - 1 - Write protection is disabled.
mbed_official 324:406fd2029f23 1158 */
mbed_official 324:406fd2029f23 1159 /*@{*/
mbed_official 324:406fd2029f23 1160 #define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */
mbed_official 324:406fd2029f23 1161 #define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
mbed_official 324:406fd2029f23 1162 #define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */
mbed_official 324:406fd2029f23 1163
mbed_official 324:406fd2029f23 1164 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
mbed_official 324:406fd2029f23 1165 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
mbed_official 324:406fd2029f23 1166
mbed_official 324:406fd2029f23 1167 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
mbed_official 324:406fd2029f23 1168 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
mbed_official 324:406fd2029f23 1169
mbed_official 324:406fd2029f23 1170 /*! @brief Set the WPDIS field to a new value. */
mbed_official 324:406fd2029f23 1171 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
mbed_official 324:406fd2029f23 1172 /*@}*/
mbed_official 324:406fd2029f23 1173
mbed_official 324:406fd2029f23 1174 /*!
mbed_official 324:406fd2029f23 1175 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
mbed_official 324:406fd2029f23 1176 *
mbed_official 324:406fd2029f23 1177 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
mbed_official 324:406fd2029f23 1178 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
mbed_official 324:406fd2029f23 1179 * synchronization when SYNCMODE is 0.
mbed_official 324:406fd2029f23 1180 *
mbed_official 324:406fd2029f23 1181 * Values:
mbed_official 324:406fd2029f23 1182 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
mbed_official 324:406fd2029f23 1183 * CnV, OUTMASK, and FTM counter synchronization.
mbed_official 324:406fd2029f23 1184 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
mbed_official 324:406fd2029f23 1185 * hardware triggers can only be used by OUTMASK and FTM counter
mbed_official 324:406fd2029f23 1186 * synchronization.
mbed_official 324:406fd2029f23 1187 */
mbed_official 324:406fd2029f23 1188 /*@{*/
mbed_official 324:406fd2029f23 1189 #define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */
mbed_official 324:406fd2029f23 1190 #define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
mbed_official 324:406fd2029f23 1191 #define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
mbed_official 324:406fd2029f23 1192
mbed_official 324:406fd2029f23 1193 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
mbed_official 324:406fd2029f23 1194 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
mbed_official 324:406fd2029f23 1195
mbed_official 324:406fd2029f23 1196 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
mbed_official 324:406fd2029f23 1197 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
mbed_official 324:406fd2029f23 1198
mbed_official 324:406fd2029f23 1199 /*! @brief Set the PWMSYNC field to a new value. */
mbed_official 324:406fd2029f23 1200 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
mbed_official 324:406fd2029f23 1201 /*@}*/
mbed_official 324:406fd2029f23 1202
mbed_official 324:406fd2029f23 1203 /*!
mbed_official 324:406fd2029f23 1204 * @name Register FTM_MODE, field CAPTEST[4] (RW)
mbed_official 324:406fd2029f23 1205 *
mbed_official 324:406fd2029f23 1206 * Enables the capture test mode. This field is write protected. It can be
mbed_official 324:406fd2029f23 1207 * written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 1208 *
mbed_official 324:406fd2029f23 1209 * Values:
mbed_official 324:406fd2029f23 1210 * - 0 - Capture test mode is disabled.
mbed_official 324:406fd2029f23 1211 * - 1 - Capture test mode is enabled.
mbed_official 324:406fd2029f23 1212 */
mbed_official 324:406fd2029f23 1213 /*@{*/
mbed_official 324:406fd2029f23 1214 #define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */
mbed_official 324:406fd2029f23 1215 #define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
mbed_official 324:406fd2029f23 1216 #define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
mbed_official 324:406fd2029f23 1217
mbed_official 324:406fd2029f23 1218 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
mbed_official 324:406fd2029f23 1219 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
mbed_official 324:406fd2029f23 1220
mbed_official 324:406fd2029f23 1221 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
mbed_official 324:406fd2029f23 1222 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
mbed_official 324:406fd2029f23 1223
mbed_official 324:406fd2029f23 1224 /*! @brief Set the CAPTEST field to a new value. */
mbed_official 324:406fd2029f23 1225 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
mbed_official 324:406fd2029f23 1226 /*@}*/
mbed_official 324:406fd2029f23 1227
mbed_official 324:406fd2029f23 1228 /*!
mbed_official 324:406fd2029f23 1229 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
mbed_official 324:406fd2029f23 1230 *
mbed_official 324:406fd2029f23 1231 * Defines the FTM fault control mode. This field is write protected. It can be
mbed_official 324:406fd2029f23 1232 * written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 1233 *
mbed_official 324:406fd2029f23 1234 * Values:
mbed_official 324:406fd2029f23 1235 * - 00 - Fault control is disabled for all channels.
mbed_official 324:406fd2029f23 1236 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
mbed_official 324:406fd2029f23 1237 * 6), and the selected mode is the manual fault clearing.
mbed_official 324:406fd2029f23 1238 * - 10 - Fault control is enabled for all channels, and the selected mode is
mbed_official 324:406fd2029f23 1239 * the manual fault clearing.
mbed_official 324:406fd2029f23 1240 * - 11 - Fault control is enabled for all channels, and the selected mode is
mbed_official 324:406fd2029f23 1241 * the automatic fault clearing.
mbed_official 324:406fd2029f23 1242 */
mbed_official 324:406fd2029f23 1243 /*@{*/
mbed_official 324:406fd2029f23 1244 #define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */
mbed_official 324:406fd2029f23 1245 #define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
mbed_official 324:406fd2029f23 1246 #define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */
mbed_official 324:406fd2029f23 1247
mbed_official 324:406fd2029f23 1248 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
mbed_official 324:406fd2029f23 1249 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
mbed_official 324:406fd2029f23 1250
mbed_official 324:406fd2029f23 1251 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
mbed_official 324:406fd2029f23 1252 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
mbed_official 324:406fd2029f23 1253
mbed_official 324:406fd2029f23 1254 /*! @brief Set the FAULTM field to a new value. */
mbed_official 324:406fd2029f23 1255 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
mbed_official 324:406fd2029f23 1256 /*@}*/
mbed_official 324:406fd2029f23 1257
mbed_official 324:406fd2029f23 1258 /*!
mbed_official 324:406fd2029f23 1259 * @name Register FTM_MODE, field FAULTIE[7] (RW)
mbed_official 324:406fd2029f23 1260 *
mbed_official 324:406fd2029f23 1261 * Enables the generation of an interrupt when a fault is detected by FTM and
mbed_official 324:406fd2029f23 1262 * the FTM fault control is enabled.
mbed_official 324:406fd2029f23 1263 *
mbed_official 324:406fd2029f23 1264 * Values:
mbed_official 324:406fd2029f23 1265 * - 0 - Fault control interrupt is disabled.
mbed_official 324:406fd2029f23 1266 * - 1 - Fault control interrupt is enabled.
mbed_official 324:406fd2029f23 1267 */
mbed_official 324:406fd2029f23 1268 /*@{*/
mbed_official 324:406fd2029f23 1269 #define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */
mbed_official 324:406fd2029f23 1270 #define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
mbed_official 324:406fd2029f23 1271 #define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
mbed_official 324:406fd2029f23 1272
mbed_official 324:406fd2029f23 1273 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
mbed_official 324:406fd2029f23 1274 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
mbed_official 324:406fd2029f23 1275
mbed_official 324:406fd2029f23 1276 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
mbed_official 324:406fd2029f23 1277 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
mbed_official 324:406fd2029f23 1278
mbed_official 324:406fd2029f23 1279 /*! @brief Set the FAULTIE field to a new value. */
mbed_official 324:406fd2029f23 1280 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
mbed_official 324:406fd2029f23 1281 /*@}*/
mbed_official 324:406fd2029f23 1282
mbed_official 324:406fd2029f23 1283 /*******************************************************************************
mbed_official 324:406fd2029f23 1284 * HW_FTM_SYNC - Synchronization
mbed_official 324:406fd2029f23 1285 ******************************************************************************/
mbed_official 324:406fd2029f23 1286
mbed_official 324:406fd2029f23 1287 /*!
mbed_official 324:406fd2029f23 1288 * @brief HW_FTM_SYNC - Synchronization (RW)
mbed_official 324:406fd2029f23 1289 *
mbed_official 324:406fd2029f23 1290 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1291 *
mbed_official 324:406fd2029f23 1292 * This register configures the PWM synchronization. A synchronization event can
mbed_official 324:406fd2029f23 1293 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
mbed_official 324:406fd2029f23 1294 * value of their write buffer and the FTM counter initialization. The software
mbed_official 324:406fd2029f23 1295 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
mbed_official 324:406fd2029f23 1296 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
mbed_official 324:406fd2029f23 1297 * software triggers but not both at the same time, otherwise unpredictable behavior
mbed_official 324:406fd2029f23 1298 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
mbed_official 324:406fd2029f23 1299 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
mbed_official 324:406fd2029f23 1300 * all enabled channels simultaneously. The use of the loading point selection
mbed_official 324:406fd2029f23 1301 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
mbed_official 324:406fd2029f23 1302 * bits, is likely to result in unpredictable behavior. The synchronization
mbed_official 324:406fd2029f23 1303 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
mbed_official 324:406fd2029f23 1304 * register) bits. See PWM synchronization.
mbed_official 324:406fd2029f23 1305 */
mbed_official 324:406fd2029f23 1306 typedef union _hw_ftm_sync
mbed_official 324:406fd2029f23 1307 {
mbed_official 324:406fd2029f23 1308 uint32_t U;
mbed_official 324:406fd2029f23 1309 struct _hw_ftm_sync_bitfields
mbed_official 324:406fd2029f23 1310 {
mbed_official 324:406fd2029f23 1311 uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */
mbed_official 324:406fd2029f23 1312 uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */
mbed_official 324:406fd2029f23 1313 uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By
mbed_official 324:406fd2029f23 1314 * Synchronization (FTM counter synchronization) */
mbed_official 324:406fd2029f23 1315 uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */
mbed_official 324:406fd2029f23 1316 uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */
mbed_official 324:406fd2029f23 1317 uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */
mbed_official 324:406fd2029f23 1318 uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */
mbed_official 324:406fd2029f23 1319 uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */
mbed_official 324:406fd2029f23 1320 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1321 } B;
mbed_official 324:406fd2029f23 1322 } hw_ftm_sync_t;
mbed_official 324:406fd2029f23 1323
mbed_official 324:406fd2029f23 1324 /*!
mbed_official 324:406fd2029f23 1325 * @name Constants and macros for entire FTM_SYNC register
mbed_official 324:406fd2029f23 1326 */
mbed_official 324:406fd2029f23 1327 /*@{*/
mbed_official 324:406fd2029f23 1328 #define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
mbed_official 324:406fd2029f23 1329
mbed_official 324:406fd2029f23 1330 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
mbed_official 324:406fd2029f23 1331 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
mbed_official 324:406fd2029f23 1332 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
mbed_official 324:406fd2029f23 1333 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
mbed_official 324:406fd2029f23 1334 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1335 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1336 /*@}*/
mbed_official 324:406fd2029f23 1337
mbed_official 324:406fd2029f23 1338 /*
mbed_official 324:406fd2029f23 1339 * Constants & macros for individual FTM_SYNC bitfields
mbed_official 324:406fd2029f23 1340 */
mbed_official 324:406fd2029f23 1341
mbed_official 324:406fd2029f23 1342 /*!
mbed_official 324:406fd2029f23 1343 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
mbed_official 324:406fd2029f23 1344 *
mbed_official 324:406fd2029f23 1345 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
mbed_official 324:406fd2029f23 1346 * and loading points. If CNTMIN is one, the selected loading point is when the
mbed_official 324:406fd2029f23 1347 * FTM counter reaches its minimum value (CNTIN register).
mbed_official 324:406fd2029f23 1348 *
mbed_official 324:406fd2029f23 1349 * Values:
mbed_official 324:406fd2029f23 1350 * - 0 - The minimum loading point is disabled.
mbed_official 324:406fd2029f23 1351 * - 1 - The minimum loading point is enabled.
mbed_official 324:406fd2029f23 1352 */
mbed_official 324:406fd2029f23 1353 /*@{*/
mbed_official 324:406fd2029f23 1354 #define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */
mbed_official 324:406fd2029f23 1355 #define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
mbed_official 324:406fd2029f23 1356 #define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
mbed_official 324:406fd2029f23 1357
mbed_official 324:406fd2029f23 1358 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
mbed_official 324:406fd2029f23 1359 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
mbed_official 324:406fd2029f23 1360
mbed_official 324:406fd2029f23 1361 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
mbed_official 324:406fd2029f23 1362 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
mbed_official 324:406fd2029f23 1363
mbed_official 324:406fd2029f23 1364 /*! @brief Set the CNTMIN field to a new value. */
mbed_official 324:406fd2029f23 1365 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
mbed_official 324:406fd2029f23 1366 /*@}*/
mbed_official 324:406fd2029f23 1367
mbed_official 324:406fd2029f23 1368 /*!
mbed_official 324:406fd2029f23 1369 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
mbed_official 324:406fd2029f23 1370 *
mbed_official 324:406fd2029f23 1371 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
mbed_official 324:406fd2029f23 1372 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
mbed_official 324:406fd2029f23 1373 * counter reaches its maximum value (MOD register).
mbed_official 324:406fd2029f23 1374 *
mbed_official 324:406fd2029f23 1375 * Values:
mbed_official 324:406fd2029f23 1376 * - 0 - The maximum loading point is disabled.
mbed_official 324:406fd2029f23 1377 * - 1 - The maximum loading point is enabled.
mbed_official 324:406fd2029f23 1378 */
mbed_official 324:406fd2029f23 1379 /*@{*/
mbed_official 324:406fd2029f23 1380 #define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */
mbed_official 324:406fd2029f23 1381 #define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
mbed_official 324:406fd2029f23 1382 #define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
mbed_official 324:406fd2029f23 1383
mbed_official 324:406fd2029f23 1384 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
mbed_official 324:406fd2029f23 1385 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
mbed_official 324:406fd2029f23 1386
mbed_official 324:406fd2029f23 1387 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
mbed_official 324:406fd2029f23 1388 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
mbed_official 324:406fd2029f23 1389
mbed_official 324:406fd2029f23 1390 /*! @brief Set the CNTMAX field to a new value. */
mbed_official 324:406fd2029f23 1391 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
mbed_official 324:406fd2029f23 1392 /*@}*/
mbed_official 324:406fd2029f23 1393
mbed_official 324:406fd2029f23 1394 /*!
mbed_official 324:406fd2029f23 1395 * @name Register FTM_SYNC, field REINIT[2] (RW)
mbed_official 324:406fd2029f23 1396 *
mbed_official 324:406fd2029f23 1397 * Determines if the FTM counter is reinitialized when the selected trigger for
mbed_official 324:406fd2029f23 1398 * the synchronization is detected. The REINIT bit configures the synchronization
mbed_official 324:406fd2029f23 1399 * when SYNCMODE is zero.
mbed_official 324:406fd2029f23 1400 *
mbed_official 324:406fd2029f23 1401 * Values:
mbed_official 324:406fd2029f23 1402 * - 0 - FTM counter continues to count normally.
mbed_official 324:406fd2029f23 1403 * - 1 - FTM counter is updated with its initial value when the selected trigger
mbed_official 324:406fd2029f23 1404 * is detected.
mbed_official 324:406fd2029f23 1405 */
mbed_official 324:406fd2029f23 1406 /*@{*/
mbed_official 324:406fd2029f23 1407 #define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */
mbed_official 324:406fd2029f23 1408 #define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
mbed_official 324:406fd2029f23 1409 #define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */
mbed_official 324:406fd2029f23 1410
mbed_official 324:406fd2029f23 1411 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
mbed_official 324:406fd2029f23 1412 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
mbed_official 324:406fd2029f23 1413
mbed_official 324:406fd2029f23 1414 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
mbed_official 324:406fd2029f23 1415 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
mbed_official 324:406fd2029f23 1416
mbed_official 324:406fd2029f23 1417 /*! @brief Set the REINIT field to a new value. */
mbed_official 324:406fd2029f23 1418 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
mbed_official 324:406fd2029f23 1419 /*@}*/
mbed_official 324:406fd2029f23 1420
mbed_official 324:406fd2029f23 1421 /*!
mbed_official 324:406fd2029f23 1422 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
mbed_official 324:406fd2029f23 1423 *
mbed_official 324:406fd2029f23 1424 * Selects when the OUTMASK register is updated with the value of its buffer.
mbed_official 324:406fd2029f23 1425 *
mbed_official 324:406fd2029f23 1426 * Values:
mbed_official 324:406fd2029f23 1427 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
mbed_official 324:406fd2029f23 1428 * edges of the system clock.
mbed_official 324:406fd2029f23 1429 * - 1 - OUTMASK register is updated with the value of its buffer only by the
mbed_official 324:406fd2029f23 1430 * PWM synchronization.
mbed_official 324:406fd2029f23 1431 */
mbed_official 324:406fd2029f23 1432 /*@{*/
mbed_official 324:406fd2029f23 1433 #define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */
mbed_official 324:406fd2029f23 1434 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
mbed_official 324:406fd2029f23 1435 #define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
mbed_official 324:406fd2029f23 1436
mbed_official 324:406fd2029f23 1437 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
mbed_official 324:406fd2029f23 1438 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
mbed_official 324:406fd2029f23 1439
mbed_official 324:406fd2029f23 1440 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
mbed_official 324:406fd2029f23 1441 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
mbed_official 324:406fd2029f23 1442
mbed_official 324:406fd2029f23 1443 /*! @brief Set the SYNCHOM field to a new value. */
mbed_official 324:406fd2029f23 1444 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
mbed_official 324:406fd2029f23 1445 /*@}*/
mbed_official 324:406fd2029f23 1446
mbed_official 324:406fd2029f23 1447 /*!
mbed_official 324:406fd2029f23 1448 * @name Register FTM_SYNC, field TRIG0[4] (RW)
mbed_official 324:406fd2029f23 1449 *
mbed_official 324:406fd2029f23 1450 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
mbed_official 324:406fd2029f23 1451 * occurs when a rising edge is detected at the trigger 0 input signal.
mbed_official 324:406fd2029f23 1452 *
mbed_official 324:406fd2029f23 1453 * Values:
mbed_official 324:406fd2029f23 1454 * - 0 - Trigger is disabled.
mbed_official 324:406fd2029f23 1455 * - 1 - Trigger is enabled.
mbed_official 324:406fd2029f23 1456 */
mbed_official 324:406fd2029f23 1457 /*@{*/
mbed_official 324:406fd2029f23 1458 #define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */
mbed_official 324:406fd2029f23 1459 #define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
mbed_official 324:406fd2029f23 1460 #define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
mbed_official 324:406fd2029f23 1461
mbed_official 324:406fd2029f23 1462 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
mbed_official 324:406fd2029f23 1463 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
mbed_official 324:406fd2029f23 1464
mbed_official 324:406fd2029f23 1465 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
mbed_official 324:406fd2029f23 1466 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
mbed_official 324:406fd2029f23 1467
mbed_official 324:406fd2029f23 1468 /*! @brief Set the TRIG0 field to a new value. */
mbed_official 324:406fd2029f23 1469 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
mbed_official 324:406fd2029f23 1470 /*@}*/
mbed_official 324:406fd2029f23 1471
mbed_official 324:406fd2029f23 1472 /*!
mbed_official 324:406fd2029f23 1473 * @name Register FTM_SYNC, field TRIG1[5] (RW)
mbed_official 324:406fd2029f23 1474 *
mbed_official 324:406fd2029f23 1475 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
mbed_official 324:406fd2029f23 1476 * happens when a rising edge is detected at the trigger 1 input signal.
mbed_official 324:406fd2029f23 1477 *
mbed_official 324:406fd2029f23 1478 * Values:
mbed_official 324:406fd2029f23 1479 * - 0 - Trigger is disabled.
mbed_official 324:406fd2029f23 1480 * - 1 - Trigger is enabled.
mbed_official 324:406fd2029f23 1481 */
mbed_official 324:406fd2029f23 1482 /*@{*/
mbed_official 324:406fd2029f23 1483 #define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */
mbed_official 324:406fd2029f23 1484 #define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
mbed_official 324:406fd2029f23 1485 #define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
mbed_official 324:406fd2029f23 1486
mbed_official 324:406fd2029f23 1487 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
mbed_official 324:406fd2029f23 1488 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
mbed_official 324:406fd2029f23 1489
mbed_official 324:406fd2029f23 1490 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
mbed_official 324:406fd2029f23 1491 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
mbed_official 324:406fd2029f23 1492
mbed_official 324:406fd2029f23 1493 /*! @brief Set the TRIG1 field to a new value. */
mbed_official 324:406fd2029f23 1494 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
mbed_official 324:406fd2029f23 1495 /*@}*/
mbed_official 324:406fd2029f23 1496
mbed_official 324:406fd2029f23 1497 /*!
mbed_official 324:406fd2029f23 1498 * @name Register FTM_SYNC, field TRIG2[6] (RW)
mbed_official 324:406fd2029f23 1499 *
mbed_official 324:406fd2029f23 1500 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
mbed_official 324:406fd2029f23 1501 * happens when a rising edge is detected at the trigger 2 input signal.
mbed_official 324:406fd2029f23 1502 *
mbed_official 324:406fd2029f23 1503 * Values:
mbed_official 324:406fd2029f23 1504 * - 0 - Trigger is disabled.
mbed_official 324:406fd2029f23 1505 * - 1 - Trigger is enabled.
mbed_official 324:406fd2029f23 1506 */
mbed_official 324:406fd2029f23 1507 /*@{*/
mbed_official 324:406fd2029f23 1508 #define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */
mbed_official 324:406fd2029f23 1509 #define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
mbed_official 324:406fd2029f23 1510 #define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
mbed_official 324:406fd2029f23 1511
mbed_official 324:406fd2029f23 1512 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
mbed_official 324:406fd2029f23 1513 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
mbed_official 324:406fd2029f23 1514
mbed_official 324:406fd2029f23 1515 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
mbed_official 324:406fd2029f23 1516 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
mbed_official 324:406fd2029f23 1517
mbed_official 324:406fd2029f23 1518 /*! @brief Set the TRIG2 field to a new value. */
mbed_official 324:406fd2029f23 1519 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
mbed_official 324:406fd2029f23 1520 /*@}*/
mbed_official 324:406fd2029f23 1521
mbed_official 324:406fd2029f23 1522 /*!
mbed_official 324:406fd2029f23 1523 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
mbed_official 324:406fd2029f23 1524 *
mbed_official 324:406fd2029f23 1525 * Selects the software trigger as the PWM synchronization trigger. The software
mbed_official 324:406fd2029f23 1526 * trigger happens when a 1 is written to SWSYNC bit.
mbed_official 324:406fd2029f23 1527 *
mbed_official 324:406fd2029f23 1528 * Values:
mbed_official 324:406fd2029f23 1529 * - 0 - Software trigger is not selected.
mbed_official 324:406fd2029f23 1530 * - 1 - Software trigger is selected.
mbed_official 324:406fd2029f23 1531 */
mbed_official 324:406fd2029f23 1532 /*@{*/
mbed_official 324:406fd2029f23 1533 #define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */
mbed_official 324:406fd2029f23 1534 #define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
mbed_official 324:406fd2029f23 1535 #define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
mbed_official 324:406fd2029f23 1536
mbed_official 324:406fd2029f23 1537 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
mbed_official 324:406fd2029f23 1538 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
mbed_official 324:406fd2029f23 1539
mbed_official 324:406fd2029f23 1540 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
mbed_official 324:406fd2029f23 1541 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
mbed_official 324:406fd2029f23 1542
mbed_official 324:406fd2029f23 1543 /*! @brief Set the SWSYNC field to a new value. */
mbed_official 324:406fd2029f23 1544 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
mbed_official 324:406fd2029f23 1545 /*@}*/
mbed_official 324:406fd2029f23 1546
mbed_official 324:406fd2029f23 1547 /*******************************************************************************
mbed_official 324:406fd2029f23 1548 * HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official 324:406fd2029f23 1549 ******************************************************************************/
mbed_official 324:406fd2029f23 1550
mbed_official 324:406fd2029f23 1551 /*!
mbed_official 324:406fd2029f23 1552 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
mbed_official 324:406fd2029f23 1553 *
mbed_official 324:406fd2029f23 1554 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1555 */
mbed_official 324:406fd2029f23 1556 typedef union _hw_ftm_outinit
mbed_official 324:406fd2029f23 1557 {
mbed_official 324:406fd2029f23 1558 uint32_t U;
mbed_official 324:406fd2029f23 1559 struct _hw_ftm_outinit_bitfields
mbed_official 324:406fd2029f23 1560 {
mbed_official 324:406fd2029f23 1561 uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */
mbed_official 324:406fd2029f23 1562 uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */
mbed_official 324:406fd2029f23 1563 uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */
mbed_official 324:406fd2029f23 1564 uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */
mbed_official 324:406fd2029f23 1565 uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */
mbed_official 324:406fd2029f23 1566 uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */
mbed_official 324:406fd2029f23 1567 uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */
mbed_official 324:406fd2029f23 1568 uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */
mbed_official 324:406fd2029f23 1569 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1570 } B;
mbed_official 324:406fd2029f23 1571 } hw_ftm_outinit_t;
mbed_official 324:406fd2029f23 1572
mbed_official 324:406fd2029f23 1573 /*!
mbed_official 324:406fd2029f23 1574 * @name Constants and macros for entire FTM_OUTINIT register
mbed_official 324:406fd2029f23 1575 */
mbed_official 324:406fd2029f23 1576 /*@{*/
mbed_official 324:406fd2029f23 1577 #define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
mbed_official 324:406fd2029f23 1578
mbed_official 324:406fd2029f23 1579 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
mbed_official 324:406fd2029f23 1580 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
mbed_official 324:406fd2029f23 1581 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
mbed_official 324:406fd2029f23 1582 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
mbed_official 324:406fd2029f23 1583 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1584 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1585 /*@}*/
mbed_official 324:406fd2029f23 1586
mbed_official 324:406fd2029f23 1587 /*
mbed_official 324:406fd2029f23 1588 * Constants & macros for individual FTM_OUTINIT bitfields
mbed_official 324:406fd2029f23 1589 */
mbed_official 324:406fd2029f23 1590
mbed_official 324:406fd2029f23 1591 /*!
mbed_official 324:406fd2029f23 1592 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
mbed_official 324:406fd2029f23 1593 *
mbed_official 324:406fd2029f23 1594 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1595 * initialization occurs.
mbed_official 324:406fd2029f23 1596 *
mbed_official 324:406fd2029f23 1597 * Values:
mbed_official 324:406fd2029f23 1598 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1599 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1600 */
mbed_official 324:406fd2029f23 1601 /*@{*/
mbed_official 324:406fd2029f23 1602 #define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */
mbed_official 324:406fd2029f23 1603 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
mbed_official 324:406fd2029f23 1604 #define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
mbed_official 324:406fd2029f23 1605
mbed_official 324:406fd2029f23 1606 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
mbed_official 324:406fd2029f23 1607 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
mbed_official 324:406fd2029f23 1608
mbed_official 324:406fd2029f23 1609 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
mbed_official 324:406fd2029f23 1610 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
mbed_official 324:406fd2029f23 1611
mbed_official 324:406fd2029f23 1612 /*! @brief Set the CH0OI field to a new value. */
mbed_official 324:406fd2029f23 1613 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
mbed_official 324:406fd2029f23 1614 /*@}*/
mbed_official 324:406fd2029f23 1615
mbed_official 324:406fd2029f23 1616 /*!
mbed_official 324:406fd2029f23 1617 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
mbed_official 324:406fd2029f23 1618 *
mbed_official 324:406fd2029f23 1619 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1620 * initialization occurs.
mbed_official 324:406fd2029f23 1621 *
mbed_official 324:406fd2029f23 1622 * Values:
mbed_official 324:406fd2029f23 1623 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1624 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1625 */
mbed_official 324:406fd2029f23 1626 /*@{*/
mbed_official 324:406fd2029f23 1627 #define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */
mbed_official 324:406fd2029f23 1628 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
mbed_official 324:406fd2029f23 1629 #define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
mbed_official 324:406fd2029f23 1630
mbed_official 324:406fd2029f23 1631 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
mbed_official 324:406fd2029f23 1632 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
mbed_official 324:406fd2029f23 1633
mbed_official 324:406fd2029f23 1634 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
mbed_official 324:406fd2029f23 1635 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
mbed_official 324:406fd2029f23 1636
mbed_official 324:406fd2029f23 1637 /*! @brief Set the CH1OI field to a new value. */
mbed_official 324:406fd2029f23 1638 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
mbed_official 324:406fd2029f23 1639 /*@}*/
mbed_official 324:406fd2029f23 1640
mbed_official 324:406fd2029f23 1641 /*!
mbed_official 324:406fd2029f23 1642 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
mbed_official 324:406fd2029f23 1643 *
mbed_official 324:406fd2029f23 1644 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1645 * initialization occurs.
mbed_official 324:406fd2029f23 1646 *
mbed_official 324:406fd2029f23 1647 * Values:
mbed_official 324:406fd2029f23 1648 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1649 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1650 */
mbed_official 324:406fd2029f23 1651 /*@{*/
mbed_official 324:406fd2029f23 1652 #define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */
mbed_official 324:406fd2029f23 1653 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
mbed_official 324:406fd2029f23 1654 #define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
mbed_official 324:406fd2029f23 1655
mbed_official 324:406fd2029f23 1656 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
mbed_official 324:406fd2029f23 1657 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
mbed_official 324:406fd2029f23 1658
mbed_official 324:406fd2029f23 1659 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
mbed_official 324:406fd2029f23 1660 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
mbed_official 324:406fd2029f23 1661
mbed_official 324:406fd2029f23 1662 /*! @brief Set the CH2OI field to a new value. */
mbed_official 324:406fd2029f23 1663 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
mbed_official 324:406fd2029f23 1664 /*@}*/
mbed_official 324:406fd2029f23 1665
mbed_official 324:406fd2029f23 1666 /*!
mbed_official 324:406fd2029f23 1667 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
mbed_official 324:406fd2029f23 1668 *
mbed_official 324:406fd2029f23 1669 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1670 * initialization occurs.
mbed_official 324:406fd2029f23 1671 *
mbed_official 324:406fd2029f23 1672 * Values:
mbed_official 324:406fd2029f23 1673 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1674 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1675 */
mbed_official 324:406fd2029f23 1676 /*@{*/
mbed_official 324:406fd2029f23 1677 #define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */
mbed_official 324:406fd2029f23 1678 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
mbed_official 324:406fd2029f23 1679 #define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
mbed_official 324:406fd2029f23 1680
mbed_official 324:406fd2029f23 1681 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
mbed_official 324:406fd2029f23 1682 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
mbed_official 324:406fd2029f23 1683
mbed_official 324:406fd2029f23 1684 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
mbed_official 324:406fd2029f23 1685 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
mbed_official 324:406fd2029f23 1686
mbed_official 324:406fd2029f23 1687 /*! @brief Set the CH3OI field to a new value. */
mbed_official 324:406fd2029f23 1688 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
mbed_official 324:406fd2029f23 1689 /*@}*/
mbed_official 324:406fd2029f23 1690
mbed_official 324:406fd2029f23 1691 /*!
mbed_official 324:406fd2029f23 1692 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
mbed_official 324:406fd2029f23 1693 *
mbed_official 324:406fd2029f23 1694 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1695 * initialization occurs.
mbed_official 324:406fd2029f23 1696 *
mbed_official 324:406fd2029f23 1697 * Values:
mbed_official 324:406fd2029f23 1698 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1699 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1700 */
mbed_official 324:406fd2029f23 1701 /*@{*/
mbed_official 324:406fd2029f23 1702 #define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */
mbed_official 324:406fd2029f23 1703 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
mbed_official 324:406fd2029f23 1704 #define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
mbed_official 324:406fd2029f23 1705
mbed_official 324:406fd2029f23 1706 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
mbed_official 324:406fd2029f23 1707 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
mbed_official 324:406fd2029f23 1708
mbed_official 324:406fd2029f23 1709 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
mbed_official 324:406fd2029f23 1710 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
mbed_official 324:406fd2029f23 1711
mbed_official 324:406fd2029f23 1712 /*! @brief Set the CH4OI field to a new value. */
mbed_official 324:406fd2029f23 1713 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
mbed_official 324:406fd2029f23 1714 /*@}*/
mbed_official 324:406fd2029f23 1715
mbed_official 324:406fd2029f23 1716 /*!
mbed_official 324:406fd2029f23 1717 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
mbed_official 324:406fd2029f23 1718 *
mbed_official 324:406fd2029f23 1719 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1720 * initialization occurs.
mbed_official 324:406fd2029f23 1721 *
mbed_official 324:406fd2029f23 1722 * Values:
mbed_official 324:406fd2029f23 1723 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1724 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1725 */
mbed_official 324:406fd2029f23 1726 /*@{*/
mbed_official 324:406fd2029f23 1727 #define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */
mbed_official 324:406fd2029f23 1728 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
mbed_official 324:406fd2029f23 1729 #define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
mbed_official 324:406fd2029f23 1730
mbed_official 324:406fd2029f23 1731 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
mbed_official 324:406fd2029f23 1732 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
mbed_official 324:406fd2029f23 1733
mbed_official 324:406fd2029f23 1734 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
mbed_official 324:406fd2029f23 1735 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
mbed_official 324:406fd2029f23 1736
mbed_official 324:406fd2029f23 1737 /*! @brief Set the CH5OI field to a new value. */
mbed_official 324:406fd2029f23 1738 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
mbed_official 324:406fd2029f23 1739 /*@}*/
mbed_official 324:406fd2029f23 1740
mbed_official 324:406fd2029f23 1741 /*!
mbed_official 324:406fd2029f23 1742 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
mbed_official 324:406fd2029f23 1743 *
mbed_official 324:406fd2029f23 1744 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1745 * initialization occurs.
mbed_official 324:406fd2029f23 1746 *
mbed_official 324:406fd2029f23 1747 * Values:
mbed_official 324:406fd2029f23 1748 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1749 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1750 */
mbed_official 324:406fd2029f23 1751 /*@{*/
mbed_official 324:406fd2029f23 1752 #define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */
mbed_official 324:406fd2029f23 1753 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
mbed_official 324:406fd2029f23 1754 #define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
mbed_official 324:406fd2029f23 1755
mbed_official 324:406fd2029f23 1756 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
mbed_official 324:406fd2029f23 1757 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
mbed_official 324:406fd2029f23 1758
mbed_official 324:406fd2029f23 1759 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
mbed_official 324:406fd2029f23 1760 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
mbed_official 324:406fd2029f23 1761
mbed_official 324:406fd2029f23 1762 /*! @brief Set the CH6OI field to a new value. */
mbed_official 324:406fd2029f23 1763 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
mbed_official 324:406fd2029f23 1764 /*@}*/
mbed_official 324:406fd2029f23 1765
mbed_official 324:406fd2029f23 1766 /*!
mbed_official 324:406fd2029f23 1767 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
mbed_official 324:406fd2029f23 1768 *
mbed_official 324:406fd2029f23 1769 * Selects the value that is forced into the channel output when the
mbed_official 324:406fd2029f23 1770 * initialization occurs.
mbed_official 324:406fd2029f23 1771 *
mbed_official 324:406fd2029f23 1772 * Values:
mbed_official 324:406fd2029f23 1773 * - 0 - The initialization value is 0.
mbed_official 324:406fd2029f23 1774 * - 1 - The initialization value is 1.
mbed_official 324:406fd2029f23 1775 */
mbed_official 324:406fd2029f23 1776 /*@{*/
mbed_official 324:406fd2029f23 1777 #define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */
mbed_official 324:406fd2029f23 1778 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
mbed_official 324:406fd2029f23 1779 #define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
mbed_official 324:406fd2029f23 1780
mbed_official 324:406fd2029f23 1781 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
mbed_official 324:406fd2029f23 1782 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
mbed_official 324:406fd2029f23 1783
mbed_official 324:406fd2029f23 1784 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
mbed_official 324:406fd2029f23 1785 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
mbed_official 324:406fd2029f23 1786
mbed_official 324:406fd2029f23 1787 /*! @brief Set the CH7OI field to a new value. */
mbed_official 324:406fd2029f23 1788 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
mbed_official 324:406fd2029f23 1789 /*@}*/
mbed_official 324:406fd2029f23 1790
mbed_official 324:406fd2029f23 1791 /*******************************************************************************
mbed_official 324:406fd2029f23 1792 * HW_FTM_OUTMASK - Output Mask
mbed_official 324:406fd2029f23 1793 ******************************************************************************/
mbed_official 324:406fd2029f23 1794
mbed_official 324:406fd2029f23 1795 /*!
mbed_official 324:406fd2029f23 1796 * @brief HW_FTM_OUTMASK - Output Mask (RW)
mbed_official 324:406fd2029f23 1797 *
mbed_official 324:406fd2029f23 1798 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1799 *
mbed_official 324:406fd2029f23 1800 * This register provides a mask for each FTM channel. The mask of a channel
mbed_official 324:406fd2029f23 1801 * determines if its output responds, that is, it is masked or not, when a match
mbed_official 324:406fd2029f23 1802 * occurs. This feature is used for BLDC control where the PWM signal is presented
mbed_official 324:406fd2029f23 1803 * to an electric motor at specific times to provide electronic commutation. Any
mbed_official 324:406fd2029f23 1804 * write to the OUTMASK register, stores the value in its write buffer. The
mbed_official 324:406fd2029f23 1805 * register is updated with the value of its write buffer according to PWM
mbed_official 324:406fd2029f23 1806 * synchronization.
mbed_official 324:406fd2029f23 1807 */
mbed_official 324:406fd2029f23 1808 typedef union _hw_ftm_outmask
mbed_official 324:406fd2029f23 1809 {
mbed_official 324:406fd2029f23 1810 uint32_t U;
mbed_official 324:406fd2029f23 1811 struct _hw_ftm_outmask_bitfields
mbed_official 324:406fd2029f23 1812 {
mbed_official 324:406fd2029f23 1813 uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */
mbed_official 324:406fd2029f23 1814 uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */
mbed_official 324:406fd2029f23 1815 uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */
mbed_official 324:406fd2029f23 1816 uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */
mbed_official 324:406fd2029f23 1817 uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */
mbed_official 324:406fd2029f23 1818 uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */
mbed_official 324:406fd2029f23 1819 uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */
mbed_official 324:406fd2029f23 1820 uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */
mbed_official 324:406fd2029f23 1821 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1822 } B;
mbed_official 324:406fd2029f23 1823 } hw_ftm_outmask_t;
mbed_official 324:406fd2029f23 1824
mbed_official 324:406fd2029f23 1825 /*!
mbed_official 324:406fd2029f23 1826 * @name Constants and macros for entire FTM_OUTMASK register
mbed_official 324:406fd2029f23 1827 */
mbed_official 324:406fd2029f23 1828 /*@{*/
mbed_official 324:406fd2029f23 1829 #define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
mbed_official 324:406fd2029f23 1830
mbed_official 324:406fd2029f23 1831 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
mbed_official 324:406fd2029f23 1832 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
mbed_official 324:406fd2029f23 1833 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
mbed_official 324:406fd2029f23 1834 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
mbed_official 324:406fd2029f23 1835 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1836 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1837 /*@}*/
mbed_official 324:406fd2029f23 1838
mbed_official 324:406fd2029f23 1839 /*
mbed_official 324:406fd2029f23 1840 * Constants & macros for individual FTM_OUTMASK bitfields
mbed_official 324:406fd2029f23 1841 */
mbed_official 324:406fd2029f23 1842
mbed_official 324:406fd2029f23 1843 /*!
mbed_official 324:406fd2029f23 1844 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
mbed_official 324:406fd2029f23 1845 *
mbed_official 324:406fd2029f23 1846 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1847 *
mbed_official 324:406fd2029f23 1848 * Values:
mbed_official 324:406fd2029f23 1849 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1850 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1851 */
mbed_official 324:406fd2029f23 1852 /*@{*/
mbed_official 324:406fd2029f23 1853 #define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */
mbed_official 324:406fd2029f23 1854 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
mbed_official 324:406fd2029f23 1855 #define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
mbed_official 324:406fd2029f23 1856
mbed_official 324:406fd2029f23 1857 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
mbed_official 324:406fd2029f23 1858 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
mbed_official 324:406fd2029f23 1859
mbed_official 324:406fd2029f23 1860 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
mbed_official 324:406fd2029f23 1861 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
mbed_official 324:406fd2029f23 1862
mbed_official 324:406fd2029f23 1863 /*! @brief Set the CH0OM field to a new value. */
mbed_official 324:406fd2029f23 1864 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
mbed_official 324:406fd2029f23 1865 /*@}*/
mbed_official 324:406fd2029f23 1866
mbed_official 324:406fd2029f23 1867 /*!
mbed_official 324:406fd2029f23 1868 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
mbed_official 324:406fd2029f23 1869 *
mbed_official 324:406fd2029f23 1870 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1871 *
mbed_official 324:406fd2029f23 1872 * Values:
mbed_official 324:406fd2029f23 1873 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1874 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1875 */
mbed_official 324:406fd2029f23 1876 /*@{*/
mbed_official 324:406fd2029f23 1877 #define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */
mbed_official 324:406fd2029f23 1878 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
mbed_official 324:406fd2029f23 1879 #define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
mbed_official 324:406fd2029f23 1880
mbed_official 324:406fd2029f23 1881 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
mbed_official 324:406fd2029f23 1882 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
mbed_official 324:406fd2029f23 1883
mbed_official 324:406fd2029f23 1884 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
mbed_official 324:406fd2029f23 1885 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
mbed_official 324:406fd2029f23 1886
mbed_official 324:406fd2029f23 1887 /*! @brief Set the CH1OM field to a new value. */
mbed_official 324:406fd2029f23 1888 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
mbed_official 324:406fd2029f23 1889 /*@}*/
mbed_official 324:406fd2029f23 1890
mbed_official 324:406fd2029f23 1891 /*!
mbed_official 324:406fd2029f23 1892 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
mbed_official 324:406fd2029f23 1893 *
mbed_official 324:406fd2029f23 1894 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1895 *
mbed_official 324:406fd2029f23 1896 * Values:
mbed_official 324:406fd2029f23 1897 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1898 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1899 */
mbed_official 324:406fd2029f23 1900 /*@{*/
mbed_official 324:406fd2029f23 1901 #define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */
mbed_official 324:406fd2029f23 1902 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
mbed_official 324:406fd2029f23 1903 #define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
mbed_official 324:406fd2029f23 1904
mbed_official 324:406fd2029f23 1905 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
mbed_official 324:406fd2029f23 1906 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
mbed_official 324:406fd2029f23 1907
mbed_official 324:406fd2029f23 1908 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
mbed_official 324:406fd2029f23 1909 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
mbed_official 324:406fd2029f23 1910
mbed_official 324:406fd2029f23 1911 /*! @brief Set the CH2OM field to a new value. */
mbed_official 324:406fd2029f23 1912 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
mbed_official 324:406fd2029f23 1913 /*@}*/
mbed_official 324:406fd2029f23 1914
mbed_official 324:406fd2029f23 1915 /*!
mbed_official 324:406fd2029f23 1916 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
mbed_official 324:406fd2029f23 1917 *
mbed_official 324:406fd2029f23 1918 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1919 *
mbed_official 324:406fd2029f23 1920 * Values:
mbed_official 324:406fd2029f23 1921 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1922 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1923 */
mbed_official 324:406fd2029f23 1924 /*@{*/
mbed_official 324:406fd2029f23 1925 #define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */
mbed_official 324:406fd2029f23 1926 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
mbed_official 324:406fd2029f23 1927 #define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
mbed_official 324:406fd2029f23 1928
mbed_official 324:406fd2029f23 1929 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
mbed_official 324:406fd2029f23 1930 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
mbed_official 324:406fd2029f23 1931
mbed_official 324:406fd2029f23 1932 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
mbed_official 324:406fd2029f23 1933 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
mbed_official 324:406fd2029f23 1934
mbed_official 324:406fd2029f23 1935 /*! @brief Set the CH3OM field to a new value. */
mbed_official 324:406fd2029f23 1936 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
mbed_official 324:406fd2029f23 1937 /*@}*/
mbed_official 324:406fd2029f23 1938
mbed_official 324:406fd2029f23 1939 /*!
mbed_official 324:406fd2029f23 1940 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
mbed_official 324:406fd2029f23 1941 *
mbed_official 324:406fd2029f23 1942 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1943 *
mbed_official 324:406fd2029f23 1944 * Values:
mbed_official 324:406fd2029f23 1945 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1946 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1947 */
mbed_official 324:406fd2029f23 1948 /*@{*/
mbed_official 324:406fd2029f23 1949 #define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */
mbed_official 324:406fd2029f23 1950 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
mbed_official 324:406fd2029f23 1951 #define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
mbed_official 324:406fd2029f23 1952
mbed_official 324:406fd2029f23 1953 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
mbed_official 324:406fd2029f23 1954 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
mbed_official 324:406fd2029f23 1955
mbed_official 324:406fd2029f23 1956 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
mbed_official 324:406fd2029f23 1957 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
mbed_official 324:406fd2029f23 1958
mbed_official 324:406fd2029f23 1959 /*! @brief Set the CH4OM field to a new value. */
mbed_official 324:406fd2029f23 1960 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
mbed_official 324:406fd2029f23 1961 /*@}*/
mbed_official 324:406fd2029f23 1962
mbed_official 324:406fd2029f23 1963 /*!
mbed_official 324:406fd2029f23 1964 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
mbed_official 324:406fd2029f23 1965 *
mbed_official 324:406fd2029f23 1966 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1967 *
mbed_official 324:406fd2029f23 1968 * Values:
mbed_official 324:406fd2029f23 1969 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1970 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1971 */
mbed_official 324:406fd2029f23 1972 /*@{*/
mbed_official 324:406fd2029f23 1973 #define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */
mbed_official 324:406fd2029f23 1974 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
mbed_official 324:406fd2029f23 1975 #define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
mbed_official 324:406fd2029f23 1976
mbed_official 324:406fd2029f23 1977 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
mbed_official 324:406fd2029f23 1978 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
mbed_official 324:406fd2029f23 1979
mbed_official 324:406fd2029f23 1980 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
mbed_official 324:406fd2029f23 1981 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
mbed_official 324:406fd2029f23 1982
mbed_official 324:406fd2029f23 1983 /*! @brief Set the CH5OM field to a new value. */
mbed_official 324:406fd2029f23 1984 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
mbed_official 324:406fd2029f23 1985 /*@}*/
mbed_official 324:406fd2029f23 1986
mbed_official 324:406fd2029f23 1987 /*!
mbed_official 324:406fd2029f23 1988 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
mbed_official 324:406fd2029f23 1989 *
mbed_official 324:406fd2029f23 1990 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 1991 *
mbed_official 324:406fd2029f23 1992 * Values:
mbed_official 324:406fd2029f23 1993 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 1994 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 1995 */
mbed_official 324:406fd2029f23 1996 /*@{*/
mbed_official 324:406fd2029f23 1997 #define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */
mbed_official 324:406fd2029f23 1998 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
mbed_official 324:406fd2029f23 1999 #define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
mbed_official 324:406fd2029f23 2000
mbed_official 324:406fd2029f23 2001 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
mbed_official 324:406fd2029f23 2002 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
mbed_official 324:406fd2029f23 2003
mbed_official 324:406fd2029f23 2004 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
mbed_official 324:406fd2029f23 2005 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
mbed_official 324:406fd2029f23 2006
mbed_official 324:406fd2029f23 2007 /*! @brief Set the CH6OM field to a new value. */
mbed_official 324:406fd2029f23 2008 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
mbed_official 324:406fd2029f23 2009 /*@}*/
mbed_official 324:406fd2029f23 2010
mbed_official 324:406fd2029f23 2011 /*!
mbed_official 324:406fd2029f23 2012 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
mbed_official 324:406fd2029f23 2013 *
mbed_official 324:406fd2029f23 2014 * Defines if the channel output is masked or unmasked.
mbed_official 324:406fd2029f23 2015 *
mbed_official 324:406fd2029f23 2016 * Values:
mbed_official 324:406fd2029f23 2017 * - 0 - Channel output is not masked. It continues to operate normally.
mbed_official 324:406fd2029f23 2018 * - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official 324:406fd2029f23 2019 */
mbed_official 324:406fd2029f23 2020 /*@{*/
mbed_official 324:406fd2029f23 2021 #define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */
mbed_official 324:406fd2029f23 2022 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
mbed_official 324:406fd2029f23 2023 #define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
mbed_official 324:406fd2029f23 2024
mbed_official 324:406fd2029f23 2025 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
mbed_official 324:406fd2029f23 2026 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
mbed_official 324:406fd2029f23 2027
mbed_official 324:406fd2029f23 2028 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
mbed_official 324:406fd2029f23 2029 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
mbed_official 324:406fd2029f23 2030
mbed_official 324:406fd2029f23 2031 /*! @brief Set the CH7OM field to a new value. */
mbed_official 324:406fd2029f23 2032 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
mbed_official 324:406fd2029f23 2033 /*@}*/
mbed_official 324:406fd2029f23 2034
mbed_official 324:406fd2029f23 2035 /*******************************************************************************
mbed_official 324:406fd2029f23 2036 * HW_FTM_COMBINE - Function For Linked Channels
mbed_official 324:406fd2029f23 2037 ******************************************************************************/
mbed_official 324:406fd2029f23 2038
mbed_official 324:406fd2029f23 2039 /*!
mbed_official 324:406fd2029f23 2040 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
mbed_official 324:406fd2029f23 2041 *
mbed_official 324:406fd2029f23 2042 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2043 *
mbed_official 324:406fd2029f23 2044 * This register contains the control bits used to configure the fault control,
mbed_official 324:406fd2029f23 2045 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
mbed_official 324:406fd2029f23 2046 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
mbed_official 324:406fd2029f23 2047 * 4, and 6.
mbed_official 324:406fd2029f23 2048 */
mbed_official 324:406fd2029f23 2049 typedef union _hw_ftm_combine
mbed_official 324:406fd2029f23 2050 {
mbed_official 324:406fd2029f23 2051 uint32_t U;
mbed_official 324:406fd2029f23 2052 struct _hw_ftm_combine_bitfields
mbed_official 324:406fd2029f23 2053 {
mbed_official 324:406fd2029f23 2054 uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */
mbed_official 324:406fd2029f23 2055 uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */
mbed_official 324:406fd2029f23 2056 uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n =
mbed_official 324:406fd2029f23 2057 * 0 */
mbed_official 324:406fd2029f23 2058 uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n =
mbed_official 324:406fd2029f23 2059 * 0 */
mbed_official 324:406fd2029f23 2060 uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */
mbed_official 324:406fd2029f23 2061 uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */
mbed_official 324:406fd2029f23 2062 uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */
mbed_official 324:406fd2029f23 2063 uint32_t RESERVED0 : 1; /*!< [7] */
mbed_official 324:406fd2029f23 2064 uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */
mbed_official 324:406fd2029f23 2065 uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */
mbed_official 324:406fd2029f23 2066 uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n
mbed_official 324:406fd2029f23 2067 * = 2 */
mbed_official 324:406fd2029f23 2068 uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n
mbed_official 324:406fd2029f23 2069 * = 2 */
mbed_official 324:406fd2029f23 2070 uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */
mbed_official 324:406fd2029f23 2071 uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */
mbed_official 324:406fd2029f23 2072 uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */
mbed_official 324:406fd2029f23 2073 uint32_t RESERVED1 : 1; /*!< [15] */
mbed_official 324:406fd2029f23 2074 uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */
mbed_official 324:406fd2029f23 2075 uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */
mbed_official 324:406fd2029f23 2076 uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n
mbed_official 324:406fd2029f23 2077 * = 4 */
mbed_official 324:406fd2029f23 2078 uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n
mbed_official 324:406fd2029f23 2079 * = 4 */
mbed_official 324:406fd2029f23 2080 uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */
mbed_official 324:406fd2029f23 2081 uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */
mbed_official 324:406fd2029f23 2082 uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */
mbed_official 324:406fd2029f23 2083 uint32_t RESERVED2 : 1; /*!< [23] */
mbed_official 324:406fd2029f23 2084 uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */
mbed_official 324:406fd2029f23 2085 uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */
mbed_official 324:406fd2029f23 2086 uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n
mbed_official 324:406fd2029f23 2087 * = 6 */
mbed_official 324:406fd2029f23 2088 uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n
mbed_official 324:406fd2029f23 2089 * = 6 */
mbed_official 324:406fd2029f23 2090 uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */
mbed_official 324:406fd2029f23 2091 uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */
mbed_official 324:406fd2029f23 2092 uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */
mbed_official 324:406fd2029f23 2093 uint32_t RESERVED3 : 1; /*!< [31] */
mbed_official 324:406fd2029f23 2094 } B;
mbed_official 324:406fd2029f23 2095 } hw_ftm_combine_t;
mbed_official 324:406fd2029f23 2096
mbed_official 324:406fd2029f23 2097 /*!
mbed_official 324:406fd2029f23 2098 * @name Constants and macros for entire FTM_COMBINE register
mbed_official 324:406fd2029f23 2099 */
mbed_official 324:406fd2029f23 2100 /*@{*/
mbed_official 324:406fd2029f23 2101 #define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
mbed_official 324:406fd2029f23 2102
mbed_official 324:406fd2029f23 2103 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
mbed_official 324:406fd2029f23 2104 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
mbed_official 324:406fd2029f23 2105 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
mbed_official 324:406fd2029f23 2106 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
mbed_official 324:406fd2029f23 2107 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2108 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2109 /*@}*/
mbed_official 324:406fd2029f23 2110
mbed_official 324:406fd2029f23 2111 /*
mbed_official 324:406fd2029f23 2112 * Constants & macros for individual FTM_COMBINE bitfields
mbed_official 324:406fd2029f23 2113 */
mbed_official 324:406fd2029f23 2114
mbed_official 324:406fd2029f23 2115 /*!
mbed_official 324:406fd2029f23 2116 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
mbed_official 324:406fd2029f23 2117 *
mbed_official 324:406fd2029f23 2118 * Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2119 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2120 *
mbed_official 324:406fd2029f23 2121 * Values:
mbed_official 324:406fd2029f23 2122 * - 0 - Channels (n) and (n+1) are independent.
mbed_official 324:406fd2029f23 2123 * - 1 - Channels (n) and (n+1) are combined.
mbed_official 324:406fd2029f23 2124 */
mbed_official 324:406fd2029f23 2125 /*@{*/
mbed_official 324:406fd2029f23 2126 #define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */
mbed_official 324:406fd2029f23 2127 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
mbed_official 324:406fd2029f23 2128 #define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
mbed_official 324:406fd2029f23 2129
mbed_official 324:406fd2029f23 2130 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
mbed_official 324:406fd2029f23 2131 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
mbed_official 324:406fd2029f23 2132
mbed_official 324:406fd2029f23 2133 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
mbed_official 324:406fd2029f23 2134 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
mbed_official 324:406fd2029f23 2135
mbed_official 324:406fd2029f23 2136 /*! @brief Set the COMBINE0 field to a new value. */
mbed_official 324:406fd2029f23 2137 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
mbed_official 324:406fd2029f23 2138 /*@}*/
mbed_official 324:406fd2029f23 2139
mbed_official 324:406fd2029f23 2140 /*!
mbed_official 324:406fd2029f23 2141 * @name Register FTM_COMBINE, field COMP0[1] (RW)
mbed_official 324:406fd2029f23 2142 *
mbed_official 324:406fd2029f23 2143 * Enables Complementary mode for the combined channels. In Complementary mode
mbed_official 324:406fd2029f23 2144 * the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official 324:406fd2029f23 2145 * is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2146 *
mbed_official 324:406fd2029f23 2147 * Values:
mbed_official 324:406fd2029f23 2148 * - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official 324:406fd2029f23 2149 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official 324:406fd2029f23 2150 */
mbed_official 324:406fd2029f23 2151 /*@{*/
mbed_official 324:406fd2029f23 2152 #define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */
mbed_official 324:406fd2029f23 2153 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
mbed_official 324:406fd2029f23 2154 #define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
mbed_official 324:406fd2029f23 2155
mbed_official 324:406fd2029f23 2156 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
mbed_official 324:406fd2029f23 2157 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
mbed_official 324:406fd2029f23 2158
mbed_official 324:406fd2029f23 2159 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
mbed_official 324:406fd2029f23 2160 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
mbed_official 324:406fd2029f23 2161
mbed_official 324:406fd2029f23 2162 /*! @brief Set the COMP0 field to a new value. */
mbed_official 324:406fd2029f23 2163 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
mbed_official 324:406fd2029f23 2164 /*@}*/
mbed_official 324:406fd2029f23 2165
mbed_official 324:406fd2029f23 2166 /*!
mbed_official 324:406fd2029f23 2167 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
mbed_official 324:406fd2029f23 2168 *
mbed_official 324:406fd2029f23 2169 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official 324:406fd2029f23 2170 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official 324:406fd2029f23 2171 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official 324:406fd2029f23 2172 * when FTMEN = 1. This field is write protected. It can be written only when
mbed_official 324:406fd2029f23 2173 * MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2174 *
mbed_official 324:406fd2029f23 2175 * Values:
mbed_official 324:406fd2029f23 2176 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2177 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2178 */
mbed_official 324:406fd2029f23 2179 /*@{*/
mbed_official 324:406fd2029f23 2180 #define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */
mbed_official 324:406fd2029f23 2181 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
mbed_official 324:406fd2029f23 2182 #define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
mbed_official 324:406fd2029f23 2183
mbed_official 324:406fd2029f23 2184 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
mbed_official 324:406fd2029f23 2185 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
mbed_official 324:406fd2029f23 2186
mbed_official 324:406fd2029f23 2187 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
mbed_official 324:406fd2029f23 2188 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
mbed_official 324:406fd2029f23 2189
mbed_official 324:406fd2029f23 2190 /*! @brief Set the DECAPEN0 field to a new value. */
mbed_official 324:406fd2029f23 2191 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
mbed_official 324:406fd2029f23 2192 /*@}*/
mbed_official 324:406fd2029f23 2193
mbed_official 324:406fd2029f23 2194 /*!
mbed_official 324:406fd2029f23 2195 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
mbed_official 324:406fd2029f23 2196 *
mbed_official 324:406fd2029f23 2197 * Enables the capture of the FTM counter value according to the channel (n)
mbed_official 324:406fd2029f23 2198 * input event and the configuration of the dual edge capture bits. This field
mbed_official 324:406fd2029f23 2199 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official 324:406fd2029f23 2200 * hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official 324:406fd2029f23 2201 * of channel (n+1) event is made.
mbed_official 324:406fd2029f23 2202 *
mbed_official 324:406fd2029f23 2203 * Values:
mbed_official 324:406fd2029f23 2204 * - 0 - The dual edge captures are inactive.
mbed_official 324:406fd2029f23 2205 * - 1 - The dual edge captures are active.
mbed_official 324:406fd2029f23 2206 */
mbed_official 324:406fd2029f23 2207 /*@{*/
mbed_official 324:406fd2029f23 2208 #define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */
mbed_official 324:406fd2029f23 2209 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
mbed_official 324:406fd2029f23 2210 #define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
mbed_official 324:406fd2029f23 2211
mbed_official 324:406fd2029f23 2212 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
mbed_official 324:406fd2029f23 2213 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
mbed_official 324:406fd2029f23 2214
mbed_official 324:406fd2029f23 2215 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
mbed_official 324:406fd2029f23 2216 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
mbed_official 324:406fd2029f23 2217
mbed_official 324:406fd2029f23 2218 /*! @brief Set the DECAP0 field to a new value. */
mbed_official 324:406fd2029f23 2219 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
mbed_official 324:406fd2029f23 2220 /*@}*/
mbed_official 324:406fd2029f23 2221
mbed_official 324:406fd2029f23 2222 /*!
mbed_official 324:406fd2029f23 2223 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
mbed_official 324:406fd2029f23 2224 *
mbed_official 324:406fd2029f23 2225 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official 324:406fd2029f23 2226 * write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2227 *
mbed_official 324:406fd2029f23 2228 * Values:
mbed_official 324:406fd2029f23 2229 * - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2230 * - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2231 */
mbed_official 324:406fd2029f23 2232 /*@{*/
mbed_official 324:406fd2029f23 2233 #define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */
mbed_official 324:406fd2029f23 2234 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
mbed_official 324:406fd2029f23 2235 #define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
mbed_official 324:406fd2029f23 2236
mbed_official 324:406fd2029f23 2237 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
mbed_official 324:406fd2029f23 2238 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
mbed_official 324:406fd2029f23 2239
mbed_official 324:406fd2029f23 2240 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
mbed_official 324:406fd2029f23 2241 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
mbed_official 324:406fd2029f23 2242
mbed_official 324:406fd2029f23 2243 /*! @brief Set the DTEN0 field to a new value. */
mbed_official 324:406fd2029f23 2244 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
mbed_official 324:406fd2029f23 2245 /*@}*/
mbed_official 324:406fd2029f23 2246
mbed_official 324:406fd2029f23 2247 /*!
mbed_official 324:406fd2029f23 2248 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
mbed_official 324:406fd2029f23 2249 *
mbed_official 324:406fd2029f23 2250 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official 324:406fd2029f23 2251 *
mbed_official 324:406fd2029f23 2252 * Values:
mbed_official 324:406fd2029f23 2253 * - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2254 * - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2255 */
mbed_official 324:406fd2029f23 2256 /*@{*/
mbed_official 324:406fd2029f23 2257 #define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */
mbed_official 324:406fd2029f23 2258 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
mbed_official 324:406fd2029f23 2259 #define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
mbed_official 324:406fd2029f23 2260
mbed_official 324:406fd2029f23 2261 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
mbed_official 324:406fd2029f23 2262 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
mbed_official 324:406fd2029f23 2263
mbed_official 324:406fd2029f23 2264 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
mbed_official 324:406fd2029f23 2265 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
mbed_official 324:406fd2029f23 2266
mbed_official 324:406fd2029f23 2267 /*! @brief Set the SYNCEN0 field to a new value. */
mbed_official 324:406fd2029f23 2268 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
mbed_official 324:406fd2029f23 2269 /*@}*/
mbed_official 324:406fd2029f23 2270
mbed_official 324:406fd2029f23 2271 /*!
mbed_official 324:406fd2029f23 2272 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
mbed_official 324:406fd2029f23 2273 *
mbed_official 324:406fd2029f23 2274 * Enables the fault control in channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2275 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2276 *
mbed_official 324:406fd2029f23 2277 * Values:
mbed_official 324:406fd2029f23 2278 * - 0 - The fault control in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2279 * - 1 - The fault control in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2280 */
mbed_official 324:406fd2029f23 2281 /*@{*/
mbed_official 324:406fd2029f23 2282 #define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */
mbed_official 324:406fd2029f23 2283 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
mbed_official 324:406fd2029f23 2284 #define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
mbed_official 324:406fd2029f23 2285
mbed_official 324:406fd2029f23 2286 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
mbed_official 324:406fd2029f23 2287 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
mbed_official 324:406fd2029f23 2288
mbed_official 324:406fd2029f23 2289 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
mbed_official 324:406fd2029f23 2290 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
mbed_official 324:406fd2029f23 2291
mbed_official 324:406fd2029f23 2292 /*! @brief Set the FAULTEN0 field to a new value. */
mbed_official 324:406fd2029f23 2293 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
mbed_official 324:406fd2029f23 2294 /*@}*/
mbed_official 324:406fd2029f23 2295
mbed_official 324:406fd2029f23 2296 /*!
mbed_official 324:406fd2029f23 2297 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
mbed_official 324:406fd2029f23 2298 *
mbed_official 324:406fd2029f23 2299 * Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2300 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2301 *
mbed_official 324:406fd2029f23 2302 * Values:
mbed_official 324:406fd2029f23 2303 * - 0 - Channels (n) and (n+1) are independent.
mbed_official 324:406fd2029f23 2304 * - 1 - Channels (n) and (n+1) are combined.
mbed_official 324:406fd2029f23 2305 */
mbed_official 324:406fd2029f23 2306 /*@{*/
mbed_official 324:406fd2029f23 2307 #define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */
mbed_official 324:406fd2029f23 2308 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
mbed_official 324:406fd2029f23 2309 #define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
mbed_official 324:406fd2029f23 2310
mbed_official 324:406fd2029f23 2311 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
mbed_official 324:406fd2029f23 2312 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
mbed_official 324:406fd2029f23 2313
mbed_official 324:406fd2029f23 2314 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
mbed_official 324:406fd2029f23 2315 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
mbed_official 324:406fd2029f23 2316
mbed_official 324:406fd2029f23 2317 /*! @brief Set the COMBINE1 field to a new value. */
mbed_official 324:406fd2029f23 2318 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
mbed_official 324:406fd2029f23 2319 /*@}*/
mbed_official 324:406fd2029f23 2320
mbed_official 324:406fd2029f23 2321 /*!
mbed_official 324:406fd2029f23 2322 * @name Register FTM_COMBINE, field COMP1[9] (RW)
mbed_official 324:406fd2029f23 2323 *
mbed_official 324:406fd2029f23 2324 * Enables Complementary mode for the combined channels. In Complementary mode
mbed_official 324:406fd2029f23 2325 * the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official 324:406fd2029f23 2326 * is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2327 *
mbed_official 324:406fd2029f23 2328 * Values:
mbed_official 324:406fd2029f23 2329 * - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official 324:406fd2029f23 2330 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official 324:406fd2029f23 2331 */
mbed_official 324:406fd2029f23 2332 /*@{*/
mbed_official 324:406fd2029f23 2333 #define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */
mbed_official 324:406fd2029f23 2334 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
mbed_official 324:406fd2029f23 2335 #define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
mbed_official 324:406fd2029f23 2336
mbed_official 324:406fd2029f23 2337 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
mbed_official 324:406fd2029f23 2338 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
mbed_official 324:406fd2029f23 2339
mbed_official 324:406fd2029f23 2340 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
mbed_official 324:406fd2029f23 2341 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
mbed_official 324:406fd2029f23 2342
mbed_official 324:406fd2029f23 2343 /*! @brief Set the COMP1 field to a new value. */
mbed_official 324:406fd2029f23 2344 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
mbed_official 324:406fd2029f23 2345 /*@}*/
mbed_official 324:406fd2029f23 2346
mbed_official 324:406fd2029f23 2347 /*!
mbed_official 324:406fd2029f23 2348 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
mbed_official 324:406fd2029f23 2349 *
mbed_official 324:406fd2029f23 2350 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official 324:406fd2029f23 2351 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official 324:406fd2029f23 2352 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official 324:406fd2029f23 2353 * when FTMEN = 1. This field is write protected. It can be written only when
mbed_official 324:406fd2029f23 2354 * MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2355 *
mbed_official 324:406fd2029f23 2356 * Values:
mbed_official 324:406fd2029f23 2357 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2358 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2359 */
mbed_official 324:406fd2029f23 2360 /*@{*/
mbed_official 324:406fd2029f23 2361 #define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */
mbed_official 324:406fd2029f23 2362 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
mbed_official 324:406fd2029f23 2363 #define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
mbed_official 324:406fd2029f23 2364
mbed_official 324:406fd2029f23 2365 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
mbed_official 324:406fd2029f23 2366 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
mbed_official 324:406fd2029f23 2367
mbed_official 324:406fd2029f23 2368 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
mbed_official 324:406fd2029f23 2369 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
mbed_official 324:406fd2029f23 2370
mbed_official 324:406fd2029f23 2371 /*! @brief Set the DECAPEN1 field to a new value. */
mbed_official 324:406fd2029f23 2372 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
mbed_official 324:406fd2029f23 2373 /*@}*/
mbed_official 324:406fd2029f23 2374
mbed_official 324:406fd2029f23 2375 /*!
mbed_official 324:406fd2029f23 2376 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
mbed_official 324:406fd2029f23 2377 *
mbed_official 324:406fd2029f23 2378 * Enables the capture of the FTM counter value according to the channel (n)
mbed_official 324:406fd2029f23 2379 * input event and the configuration of the dual edge capture bits. This field
mbed_official 324:406fd2029f23 2380 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official 324:406fd2029f23 2381 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
mbed_official 324:406fd2029f23 2382 * of channel (n+1) event is made.
mbed_official 324:406fd2029f23 2383 *
mbed_official 324:406fd2029f23 2384 * Values:
mbed_official 324:406fd2029f23 2385 * - 0 - The dual edge captures are inactive.
mbed_official 324:406fd2029f23 2386 * - 1 - The dual edge captures are active.
mbed_official 324:406fd2029f23 2387 */
mbed_official 324:406fd2029f23 2388 /*@{*/
mbed_official 324:406fd2029f23 2389 #define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */
mbed_official 324:406fd2029f23 2390 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
mbed_official 324:406fd2029f23 2391 #define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
mbed_official 324:406fd2029f23 2392
mbed_official 324:406fd2029f23 2393 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
mbed_official 324:406fd2029f23 2394 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
mbed_official 324:406fd2029f23 2395
mbed_official 324:406fd2029f23 2396 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
mbed_official 324:406fd2029f23 2397 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
mbed_official 324:406fd2029f23 2398
mbed_official 324:406fd2029f23 2399 /*! @brief Set the DECAP1 field to a new value. */
mbed_official 324:406fd2029f23 2400 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
mbed_official 324:406fd2029f23 2401 /*@}*/
mbed_official 324:406fd2029f23 2402
mbed_official 324:406fd2029f23 2403 /*!
mbed_official 324:406fd2029f23 2404 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
mbed_official 324:406fd2029f23 2405 *
mbed_official 324:406fd2029f23 2406 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official 324:406fd2029f23 2407 * write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2408 *
mbed_official 324:406fd2029f23 2409 * Values:
mbed_official 324:406fd2029f23 2410 * - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2411 * - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2412 */
mbed_official 324:406fd2029f23 2413 /*@{*/
mbed_official 324:406fd2029f23 2414 #define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */
mbed_official 324:406fd2029f23 2415 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
mbed_official 324:406fd2029f23 2416 #define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
mbed_official 324:406fd2029f23 2417
mbed_official 324:406fd2029f23 2418 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
mbed_official 324:406fd2029f23 2419 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
mbed_official 324:406fd2029f23 2420
mbed_official 324:406fd2029f23 2421 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
mbed_official 324:406fd2029f23 2422 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
mbed_official 324:406fd2029f23 2423
mbed_official 324:406fd2029f23 2424 /*! @brief Set the DTEN1 field to a new value. */
mbed_official 324:406fd2029f23 2425 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
mbed_official 324:406fd2029f23 2426 /*@}*/
mbed_official 324:406fd2029f23 2427
mbed_official 324:406fd2029f23 2428 /*!
mbed_official 324:406fd2029f23 2429 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
mbed_official 324:406fd2029f23 2430 *
mbed_official 324:406fd2029f23 2431 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official 324:406fd2029f23 2432 *
mbed_official 324:406fd2029f23 2433 * Values:
mbed_official 324:406fd2029f23 2434 * - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2435 * - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2436 */
mbed_official 324:406fd2029f23 2437 /*@{*/
mbed_official 324:406fd2029f23 2438 #define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */
mbed_official 324:406fd2029f23 2439 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
mbed_official 324:406fd2029f23 2440 #define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
mbed_official 324:406fd2029f23 2441
mbed_official 324:406fd2029f23 2442 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
mbed_official 324:406fd2029f23 2443 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
mbed_official 324:406fd2029f23 2444
mbed_official 324:406fd2029f23 2445 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
mbed_official 324:406fd2029f23 2446 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
mbed_official 324:406fd2029f23 2447
mbed_official 324:406fd2029f23 2448 /*! @brief Set the SYNCEN1 field to a new value. */
mbed_official 324:406fd2029f23 2449 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
mbed_official 324:406fd2029f23 2450 /*@}*/
mbed_official 324:406fd2029f23 2451
mbed_official 324:406fd2029f23 2452 /*!
mbed_official 324:406fd2029f23 2453 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
mbed_official 324:406fd2029f23 2454 *
mbed_official 324:406fd2029f23 2455 * Enables the fault control in channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2456 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2457 *
mbed_official 324:406fd2029f23 2458 * Values:
mbed_official 324:406fd2029f23 2459 * - 0 - The fault control in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2460 * - 1 - The fault control in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2461 */
mbed_official 324:406fd2029f23 2462 /*@{*/
mbed_official 324:406fd2029f23 2463 #define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */
mbed_official 324:406fd2029f23 2464 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
mbed_official 324:406fd2029f23 2465 #define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
mbed_official 324:406fd2029f23 2466
mbed_official 324:406fd2029f23 2467 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
mbed_official 324:406fd2029f23 2468 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
mbed_official 324:406fd2029f23 2469
mbed_official 324:406fd2029f23 2470 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
mbed_official 324:406fd2029f23 2471 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
mbed_official 324:406fd2029f23 2472
mbed_official 324:406fd2029f23 2473 /*! @brief Set the FAULTEN1 field to a new value. */
mbed_official 324:406fd2029f23 2474 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
mbed_official 324:406fd2029f23 2475 /*@}*/
mbed_official 324:406fd2029f23 2476
mbed_official 324:406fd2029f23 2477 /*!
mbed_official 324:406fd2029f23 2478 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
mbed_official 324:406fd2029f23 2479 *
mbed_official 324:406fd2029f23 2480 * Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2481 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2482 *
mbed_official 324:406fd2029f23 2483 * Values:
mbed_official 324:406fd2029f23 2484 * - 0 - Channels (n) and (n+1) are independent.
mbed_official 324:406fd2029f23 2485 * - 1 - Channels (n) and (n+1) are combined.
mbed_official 324:406fd2029f23 2486 */
mbed_official 324:406fd2029f23 2487 /*@{*/
mbed_official 324:406fd2029f23 2488 #define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */
mbed_official 324:406fd2029f23 2489 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
mbed_official 324:406fd2029f23 2490 #define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
mbed_official 324:406fd2029f23 2491
mbed_official 324:406fd2029f23 2492 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
mbed_official 324:406fd2029f23 2493 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
mbed_official 324:406fd2029f23 2494
mbed_official 324:406fd2029f23 2495 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
mbed_official 324:406fd2029f23 2496 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
mbed_official 324:406fd2029f23 2497
mbed_official 324:406fd2029f23 2498 /*! @brief Set the COMBINE2 field to a new value. */
mbed_official 324:406fd2029f23 2499 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
mbed_official 324:406fd2029f23 2500 /*@}*/
mbed_official 324:406fd2029f23 2501
mbed_official 324:406fd2029f23 2502 /*!
mbed_official 324:406fd2029f23 2503 * @name Register FTM_COMBINE, field COMP2[17] (RW)
mbed_official 324:406fd2029f23 2504 *
mbed_official 324:406fd2029f23 2505 * Enables Complementary mode for the combined channels. In Complementary mode
mbed_official 324:406fd2029f23 2506 * the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official 324:406fd2029f23 2507 * is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2508 *
mbed_official 324:406fd2029f23 2509 * Values:
mbed_official 324:406fd2029f23 2510 * - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official 324:406fd2029f23 2511 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official 324:406fd2029f23 2512 */
mbed_official 324:406fd2029f23 2513 /*@{*/
mbed_official 324:406fd2029f23 2514 #define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */
mbed_official 324:406fd2029f23 2515 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
mbed_official 324:406fd2029f23 2516 #define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
mbed_official 324:406fd2029f23 2517
mbed_official 324:406fd2029f23 2518 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
mbed_official 324:406fd2029f23 2519 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
mbed_official 324:406fd2029f23 2520
mbed_official 324:406fd2029f23 2521 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
mbed_official 324:406fd2029f23 2522 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
mbed_official 324:406fd2029f23 2523
mbed_official 324:406fd2029f23 2524 /*! @brief Set the COMP2 field to a new value. */
mbed_official 324:406fd2029f23 2525 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
mbed_official 324:406fd2029f23 2526 /*@}*/
mbed_official 324:406fd2029f23 2527
mbed_official 324:406fd2029f23 2528 /*!
mbed_official 324:406fd2029f23 2529 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
mbed_official 324:406fd2029f23 2530 *
mbed_official 324:406fd2029f23 2531 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official 324:406fd2029f23 2532 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official 324:406fd2029f23 2533 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official 324:406fd2029f23 2534 * when FTMEN = 1. This field is write protected. It can be written only when
mbed_official 324:406fd2029f23 2535 * MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2536 *
mbed_official 324:406fd2029f23 2537 * Values:
mbed_official 324:406fd2029f23 2538 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2539 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2540 */
mbed_official 324:406fd2029f23 2541 /*@{*/
mbed_official 324:406fd2029f23 2542 #define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */
mbed_official 324:406fd2029f23 2543 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
mbed_official 324:406fd2029f23 2544 #define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
mbed_official 324:406fd2029f23 2545
mbed_official 324:406fd2029f23 2546 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
mbed_official 324:406fd2029f23 2547 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
mbed_official 324:406fd2029f23 2548
mbed_official 324:406fd2029f23 2549 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
mbed_official 324:406fd2029f23 2550 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
mbed_official 324:406fd2029f23 2551
mbed_official 324:406fd2029f23 2552 /*! @brief Set the DECAPEN2 field to a new value. */
mbed_official 324:406fd2029f23 2553 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
mbed_official 324:406fd2029f23 2554 /*@}*/
mbed_official 324:406fd2029f23 2555
mbed_official 324:406fd2029f23 2556 /*!
mbed_official 324:406fd2029f23 2557 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
mbed_official 324:406fd2029f23 2558 *
mbed_official 324:406fd2029f23 2559 * Enables the capture of the FTM counter value according to the channel (n)
mbed_official 324:406fd2029f23 2560 * input event and the configuration of the dual edge capture bits. This field
mbed_official 324:406fd2029f23 2561 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official 324:406fd2029f23 2562 * hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official 324:406fd2029f23 2563 * of channel (n+1) event is made.
mbed_official 324:406fd2029f23 2564 *
mbed_official 324:406fd2029f23 2565 * Values:
mbed_official 324:406fd2029f23 2566 * - 0 - The dual edge captures are inactive.
mbed_official 324:406fd2029f23 2567 * - 1 - The dual edge captures are active.
mbed_official 324:406fd2029f23 2568 */
mbed_official 324:406fd2029f23 2569 /*@{*/
mbed_official 324:406fd2029f23 2570 #define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */
mbed_official 324:406fd2029f23 2571 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
mbed_official 324:406fd2029f23 2572 #define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
mbed_official 324:406fd2029f23 2573
mbed_official 324:406fd2029f23 2574 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
mbed_official 324:406fd2029f23 2575 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
mbed_official 324:406fd2029f23 2576
mbed_official 324:406fd2029f23 2577 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
mbed_official 324:406fd2029f23 2578 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
mbed_official 324:406fd2029f23 2579
mbed_official 324:406fd2029f23 2580 /*! @brief Set the DECAP2 field to a new value. */
mbed_official 324:406fd2029f23 2581 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
mbed_official 324:406fd2029f23 2582 /*@}*/
mbed_official 324:406fd2029f23 2583
mbed_official 324:406fd2029f23 2584 /*!
mbed_official 324:406fd2029f23 2585 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
mbed_official 324:406fd2029f23 2586 *
mbed_official 324:406fd2029f23 2587 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official 324:406fd2029f23 2588 * write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2589 *
mbed_official 324:406fd2029f23 2590 * Values:
mbed_official 324:406fd2029f23 2591 * - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2592 * - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2593 */
mbed_official 324:406fd2029f23 2594 /*@{*/
mbed_official 324:406fd2029f23 2595 #define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */
mbed_official 324:406fd2029f23 2596 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
mbed_official 324:406fd2029f23 2597 #define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
mbed_official 324:406fd2029f23 2598
mbed_official 324:406fd2029f23 2599 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
mbed_official 324:406fd2029f23 2600 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
mbed_official 324:406fd2029f23 2601
mbed_official 324:406fd2029f23 2602 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
mbed_official 324:406fd2029f23 2603 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
mbed_official 324:406fd2029f23 2604
mbed_official 324:406fd2029f23 2605 /*! @brief Set the DTEN2 field to a new value. */
mbed_official 324:406fd2029f23 2606 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
mbed_official 324:406fd2029f23 2607 /*@}*/
mbed_official 324:406fd2029f23 2608
mbed_official 324:406fd2029f23 2609 /*!
mbed_official 324:406fd2029f23 2610 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
mbed_official 324:406fd2029f23 2611 *
mbed_official 324:406fd2029f23 2612 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official 324:406fd2029f23 2613 *
mbed_official 324:406fd2029f23 2614 * Values:
mbed_official 324:406fd2029f23 2615 * - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2616 * - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2617 */
mbed_official 324:406fd2029f23 2618 /*@{*/
mbed_official 324:406fd2029f23 2619 #define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */
mbed_official 324:406fd2029f23 2620 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
mbed_official 324:406fd2029f23 2621 #define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
mbed_official 324:406fd2029f23 2622
mbed_official 324:406fd2029f23 2623 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
mbed_official 324:406fd2029f23 2624 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
mbed_official 324:406fd2029f23 2625
mbed_official 324:406fd2029f23 2626 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
mbed_official 324:406fd2029f23 2627 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
mbed_official 324:406fd2029f23 2628
mbed_official 324:406fd2029f23 2629 /*! @brief Set the SYNCEN2 field to a new value. */
mbed_official 324:406fd2029f23 2630 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
mbed_official 324:406fd2029f23 2631 /*@}*/
mbed_official 324:406fd2029f23 2632
mbed_official 324:406fd2029f23 2633 /*!
mbed_official 324:406fd2029f23 2634 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
mbed_official 324:406fd2029f23 2635 *
mbed_official 324:406fd2029f23 2636 * Enables the fault control in channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2637 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2638 *
mbed_official 324:406fd2029f23 2639 * Values:
mbed_official 324:406fd2029f23 2640 * - 0 - The fault control in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2641 * - 1 - The fault control in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2642 */
mbed_official 324:406fd2029f23 2643 /*@{*/
mbed_official 324:406fd2029f23 2644 #define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */
mbed_official 324:406fd2029f23 2645 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
mbed_official 324:406fd2029f23 2646 #define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
mbed_official 324:406fd2029f23 2647
mbed_official 324:406fd2029f23 2648 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
mbed_official 324:406fd2029f23 2649 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
mbed_official 324:406fd2029f23 2650
mbed_official 324:406fd2029f23 2651 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
mbed_official 324:406fd2029f23 2652 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
mbed_official 324:406fd2029f23 2653
mbed_official 324:406fd2029f23 2654 /*! @brief Set the FAULTEN2 field to a new value. */
mbed_official 324:406fd2029f23 2655 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
mbed_official 324:406fd2029f23 2656 /*@}*/
mbed_official 324:406fd2029f23 2657
mbed_official 324:406fd2029f23 2658 /*!
mbed_official 324:406fd2029f23 2659 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
mbed_official 324:406fd2029f23 2660 *
mbed_official 324:406fd2029f23 2661 * Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2662 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2663 *
mbed_official 324:406fd2029f23 2664 * Values:
mbed_official 324:406fd2029f23 2665 * - 0 - Channels (n) and (n+1) are independent.
mbed_official 324:406fd2029f23 2666 * - 1 - Channels (n) and (n+1) are combined.
mbed_official 324:406fd2029f23 2667 */
mbed_official 324:406fd2029f23 2668 /*@{*/
mbed_official 324:406fd2029f23 2669 #define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */
mbed_official 324:406fd2029f23 2670 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
mbed_official 324:406fd2029f23 2671 #define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
mbed_official 324:406fd2029f23 2672
mbed_official 324:406fd2029f23 2673 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
mbed_official 324:406fd2029f23 2674 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
mbed_official 324:406fd2029f23 2675
mbed_official 324:406fd2029f23 2676 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
mbed_official 324:406fd2029f23 2677 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
mbed_official 324:406fd2029f23 2678
mbed_official 324:406fd2029f23 2679 /*! @brief Set the COMBINE3 field to a new value. */
mbed_official 324:406fd2029f23 2680 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
mbed_official 324:406fd2029f23 2681 /*@}*/
mbed_official 324:406fd2029f23 2682
mbed_official 324:406fd2029f23 2683 /*!
mbed_official 324:406fd2029f23 2684 * @name Register FTM_COMBINE, field COMP3[25] (RW)
mbed_official 324:406fd2029f23 2685 *
mbed_official 324:406fd2029f23 2686 * Enables Complementary mode for the combined channels. In Complementary mode
mbed_official 324:406fd2029f23 2687 * the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official 324:406fd2029f23 2688 * is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2689 *
mbed_official 324:406fd2029f23 2690 * Values:
mbed_official 324:406fd2029f23 2691 * - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official 324:406fd2029f23 2692 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official 324:406fd2029f23 2693 */
mbed_official 324:406fd2029f23 2694 /*@{*/
mbed_official 324:406fd2029f23 2695 #define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */
mbed_official 324:406fd2029f23 2696 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
mbed_official 324:406fd2029f23 2697 #define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
mbed_official 324:406fd2029f23 2698
mbed_official 324:406fd2029f23 2699 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
mbed_official 324:406fd2029f23 2700 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
mbed_official 324:406fd2029f23 2701
mbed_official 324:406fd2029f23 2702 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
mbed_official 324:406fd2029f23 2703 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
mbed_official 324:406fd2029f23 2704
mbed_official 324:406fd2029f23 2705 /*! @brief Set the COMP3 field to a new value. */
mbed_official 324:406fd2029f23 2706 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
mbed_official 324:406fd2029f23 2707 /*@}*/
mbed_official 324:406fd2029f23 2708
mbed_official 324:406fd2029f23 2709 /*!
mbed_official 324:406fd2029f23 2710 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
mbed_official 324:406fd2029f23 2711 *
mbed_official 324:406fd2029f23 2712 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official 324:406fd2029f23 2713 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official 324:406fd2029f23 2714 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official 324:406fd2029f23 2715 * when FTMEN = 1. This field is write protected. It can be written only when
mbed_official 324:406fd2029f23 2716 * MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2717 *
mbed_official 324:406fd2029f23 2718 * Values:
mbed_official 324:406fd2029f23 2719 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2720 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2721 */
mbed_official 324:406fd2029f23 2722 /*@{*/
mbed_official 324:406fd2029f23 2723 #define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */
mbed_official 324:406fd2029f23 2724 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
mbed_official 324:406fd2029f23 2725 #define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
mbed_official 324:406fd2029f23 2726
mbed_official 324:406fd2029f23 2727 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
mbed_official 324:406fd2029f23 2728 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
mbed_official 324:406fd2029f23 2729
mbed_official 324:406fd2029f23 2730 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
mbed_official 324:406fd2029f23 2731 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
mbed_official 324:406fd2029f23 2732
mbed_official 324:406fd2029f23 2733 /*! @brief Set the DECAPEN3 field to a new value. */
mbed_official 324:406fd2029f23 2734 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
mbed_official 324:406fd2029f23 2735 /*@}*/
mbed_official 324:406fd2029f23 2736
mbed_official 324:406fd2029f23 2737 /*!
mbed_official 324:406fd2029f23 2738 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
mbed_official 324:406fd2029f23 2739 *
mbed_official 324:406fd2029f23 2740 * Enables the capture of the FTM counter value according to the channel (n)
mbed_official 324:406fd2029f23 2741 * input event and the configuration of the dual edge capture bits. This field
mbed_official 324:406fd2029f23 2742 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official 324:406fd2029f23 2743 * hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official 324:406fd2029f23 2744 * of channel (n+1) event is made.
mbed_official 324:406fd2029f23 2745 *
mbed_official 324:406fd2029f23 2746 * Values:
mbed_official 324:406fd2029f23 2747 * - 0 - The dual edge captures are inactive.
mbed_official 324:406fd2029f23 2748 * - 1 - The dual edge captures are active.
mbed_official 324:406fd2029f23 2749 */
mbed_official 324:406fd2029f23 2750 /*@{*/
mbed_official 324:406fd2029f23 2751 #define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */
mbed_official 324:406fd2029f23 2752 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
mbed_official 324:406fd2029f23 2753 #define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
mbed_official 324:406fd2029f23 2754
mbed_official 324:406fd2029f23 2755 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
mbed_official 324:406fd2029f23 2756 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
mbed_official 324:406fd2029f23 2757
mbed_official 324:406fd2029f23 2758 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
mbed_official 324:406fd2029f23 2759 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
mbed_official 324:406fd2029f23 2760
mbed_official 324:406fd2029f23 2761 /*! @brief Set the DECAP3 field to a new value. */
mbed_official 324:406fd2029f23 2762 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
mbed_official 324:406fd2029f23 2763 /*@}*/
mbed_official 324:406fd2029f23 2764
mbed_official 324:406fd2029f23 2765 /*!
mbed_official 324:406fd2029f23 2766 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
mbed_official 324:406fd2029f23 2767 *
mbed_official 324:406fd2029f23 2768 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official 324:406fd2029f23 2769 * write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2770 *
mbed_official 324:406fd2029f23 2771 * Values:
mbed_official 324:406fd2029f23 2772 * - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2773 * - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2774 */
mbed_official 324:406fd2029f23 2775 /*@{*/
mbed_official 324:406fd2029f23 2776 #define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */
mbed_official 324:406fd2029f23 2777 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
mbed_official 324:406fd2029f23 2778 #define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
mbed_official 324:406fd2029f23 2779
mbed_official 324:406fd2029f23 2780 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
mbed_official 324:406fd2029f23 2781 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
mbed_official 324:406fd2029f23 2782
mbed_official 324:406fd2029f23 2783 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
mbed_official 324:406fd2029f23 2784 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
mbed_official 324:406fd2029f23 2785
mbed_official 324:406fd2029f23 2786 /*! @brief Set the DTEN3 field to a new value. */
mbed_official 324:406fd2029f23 2787 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
mbed_official 324:406fd2029f23 2788 /*@}*/
mbed_official 324:406fd2029f23 2789
mbed_official 324:406fd2029f23 2790 /*!
mbed_official 324:406fd2029f23 2791 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
mbed_official 324:406fd2029f23 2792 *
mbed_official 324:406fd2029f23 2793 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official 324:406fd2029f23 2794 *
mbed_official 324:406fd2029f23 2795 * Values:
mbed_official 324:406fd2029f23 2796 * - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2797 * - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2798 */
mbed_official 324:406fd2029f23 2799 /*@{*/
mbed_official 324:406fd2029f23 2800 #define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */
mbed_official 324:406fd2029f23 2801 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
mbed_official 324:406fd2029f23 2802 #define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
mbed_official 324:406fd2029f23 2803
mbed_official 324:406fd2029f23 2804 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
mbed_official 324:406fd2029f23 2805 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
mbed_official 324:406fd2029f23 2806
mbed_official 324:406fd2029f23 2807 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
mbed_official 324:406fd2029f23 2808 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
mbed_official 324:406fd2029f23 2809
mbed_official 324:406fd2029f23 2810 /*! @brief Set the SYNCEN3 field to a new value. */
mbed_official 324:406fd2029f23 2811 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
mbed_official 324:406fd2029f23 2812 /*@}*/
mbed_official 324:406fd2029f23 2813
mbed_official 324:406fd2029f23 2814 /*!
mbed_official 324:406fd2029f23 2815 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
mbed_official 324:406fd2029f23 2816 *
mbed_official 324:406fd2029f23 2817 * Enables the fault control in channels (n) and (n+1). This field is write
mbed_official 324:406fd2029f23 2818 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2819 *
mbed_official 324:406fd2029f23 2820 * Values:
mbed_official 324:406fd2029f23 2821 * - 0 - The fault control in this pair of channels is disabled.
mbed_official 324:406fd2029f23 2822 * - 1 - The fault control in this pair of channels is enabled.
mbed_official 324:406fd2029f23 2823 */
mbed_official 324:406fd2029f23 2824 /*@{*/
mbed_official 324:406fd2029f23 2825 #define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */
mbed_official 324:406fd2029f23 2826 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
mbed_official 324:406fd2029f23 2827 #define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
mbed_official 324:406fd2029f23 2828
mbed_official 324:406fd2029f23 2829 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
mbed_official 324:406fd2029f23 2830 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
mbed_official 324:406fd2029f23 2831
mbed_official 324:406fd2029f23 2832 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
mbed_official 324:406fd2029f23 2833 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
mbed_official 324:406fd2029f23 2834
mbed_official 324:406fd2029f23 2835 /*! @brief Set the FAULTEN3 field to a new value. */
mbed_official 324:406fd2029f23 2836 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
mbed_official 324:406fd2029f23 2837 /*@}*/
mbed_official 324:406fd2029f23 2838
mbed_official 324:406fd2029f23 2839 /*******************************************************************************
mbed_official 324:406fd2029f23 2840 * HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official 324:406fd2029f23 2841 ******************************************************************************/
mbed_official 324:406fd2029f23 2842
mbed_official 324:406fd2029f23 2843 /*!
mbed_official 324:406fd2029f23 2844 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
mbed_official 324:406fd2029f23 2845 *
mbed_official 324:406fd2029f23 2846 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2847 *
mbed_official 324:406fd2029f23 2848 * This register selects the deadtime prescaler factor and deadtime value. All
mbed_official 324:406fd2029f23 2849 * FTM channels use this clock prescaler and this deadtime value for the deadtime
mbed_official 324:406fd2029f23 2850 * insertion.
mbed_official 324:406fd2029f23 2851 */
mbed_official 324:406fd2029f23 2852 typedef union _hw_ftm_deadtime
mbed_official 324:406fd2029f23 2853 {
mbed_official 324:406fd2029f23 2854 uint32_t U;
mbed_official 324:406fd2029f23 2855 struct _hw_ftm_deadtime_bitfields
mbed_official 324:406fd2029f23 2856 {
mbed_official 324:406fd2029f23 2857 uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */
mbed_official 324:406fd2029f23 2858 uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */
mbed_official 324:406fd2029f23 2859 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 2860 } B;
mbed_official 324:406fd2029f23 2861 } hw_ftm_deadtime_t;
mbed_official 324:406fd2029f23 2862
mbed_official 324:406fd2029f23 2863 /*!
mbed_official 324:406fd2029f23 2864 * @name Constants and macros for entire FTM_DEADTIME register
mbed_official 324:406fd2029f23 2865 */
mbed_official 324:406fd2029f23 2866 /*@{*/
mbed_official 324:406fd2029f23 2867 #define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
mbed_official 324:406fd2029f23 2868
mbed_official 324:406fd2029f23 2869 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
mbed_official 324:406fd2029f23 2870 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
mbed_official 324:406fd2029f23 2871 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
mbed_official 324:406fd2029f23 2872 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
mbed_official 324:406fd2029f23 2873 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2874 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2875 /*@}*/
mbed_official 324:406fd2029f23 2876
mbed_official 324:406fd2029f23 2877 /*
mbed_official 324:406fd2029f23 2878 * Constants & macros for individual FTM_DEADTIME bitfields
mbed_official 324:406fd2029f23 2879 */
mbed_official 324:406fd2029f23 2880
mbed_official 324:406fd2029f23 2881 /*!
mbed_official 324:406fd2029f23 2882 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
mbed_official 324:406fd2029f23 2883 *
mbed_official 324:406fd2029f23 2884 * Selects the deadtime insertion value for the deadtime counter. The deadtime
mbed_official 324:406fd2029f23 2885 * counter is clocked by a scaled version of the system clock. See the description
mbed_official 324:406fd2029f23 2886 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
mbed_official 324:406fd2029f23 2887 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
mbed_official 324:406fd2029f23 2888 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
mbed_official 324:406fd2029f23 2889 * This pattern continues up to a possible 63 counts. This field is write
mbed_official 324:406fd2029f23 2890 * protected. It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2891 */
mbed_official 324:406fd2029f23 2892 /*@{*/
mbed_official 324:406fd2029f23 2893 #define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */
mbed_official 324:406fd2029f23 2894 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
mbed_official 324:406fd2029f23 2895 #define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
mbed_official 324:406fd2029f23 2896
mbed_official 324:406fd2029f23 2897 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
mbed_official 324:406fd2029f23 2898 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
mbed_official 324:406fd2029f23 2899
mbed_official 324:406fd2029f23 2900 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
mbed_official 324:406fd2029f23 2901 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
mbed_official 324:406fd2029f23 2902
mbed_official 324:406fd2029f23 2903 /*! @brief Set the DTVAL field to a new value. */
mbed_official 324:406fd2029f23 2904 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
mbed_official 324:406fd2029f23 2905 /*@}*/
mbed_official 324:406fd2029f23 2906
mbed_official 324:406fd2029f23 2907 /*!
mbed_official 324:406fd2029f23 2908 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
mbed_official 324:406fd2029f23 2909 *
mbed_official 324:406fd2029f23 2910 * Selects the division factor of the system clock. This prescaled clock is used
mbed_official 324:406fd2029f23 2911 * by the deadtime counter. This field is write protected. It can be written
mbed_official 324:406fd2029f23 2912 * only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 2913 *
mbed_official 324:406fd2029f23 2914 * Values:
mbed_official 324:406fd2029f23 2915 * - 0x - Divide the system clock by 1.
mbed_official 324:406fd2029f23 2916 * - 10 - Divide the system clock by 4.
mbed_official 324:406fd2029f23 2917 * - 11 - Divide the system clock by 16.
mbed_official 324:406fd2029f23 2918 */
mbed_official 324:406fd2029f23 2919 /*@{*/
mbed_official 324:406fd2029f23 2920 #define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */
mbed_official 324:406fd2029f23 2921 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
mbed_official 324:406fd2029f23 2922 #define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
mbed_official 324:406fd2029f23 2923
mbed_official 324:406fd2029f23 2924 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
mbed_official 324:406fd2029f23 2925 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
mbed_official 324:406fd2029f23 2926
mbed_official 324:406fd2029f23 2927 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
mbed_official 324:406fd2029f23 2928 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
mbed_official 324:406fd2029f23 2929
mbed_official 324:406fd2029f23 2930 /*! @brief Set the DTPS field to a new value. */
mbed_official 324:406fd2029f23 2931 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
mbed_official 324:406fd2029f23 2932 /*@}*/
mbed_official 324:406fd2029f23 2933
mbed_official 324:406fd2029f23 2934 /*******************************************************************************
mbed_official 324:406fd2029f23 2935 * HW_FTM_EXTTRIG - FTM External Trigger
mbed_official 324:406fd2029f23 2936 ******************************************************************************/
mbed_official 324:406fd2029f23 2937
mbed_official 324:406fd2029f23 2938 /*!
mbed_official 324:406fd2029f23 2939 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
mbed_official 324:406fd2029f23 2940 *
mbed_official 324:406fd2029f23 2941 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2942 *
mbed_official 324:406fd2029f23 2943 * This register: Indicates when a channel trigger was generated Enables the
mbed_official 324:406fd2029f23 2944 * generation of a trigger when the FTM counter is equal to its initial value
mbed_official 324:406fd2029f23 2945 * Selects which channels are used in the generation of the channel triggers Several
mbed_official 324:406fd2029f23 2946 * channels can be selected to generate multiple triggers in one PWM period.
mbed_official 324:406fd2029f23 2947 * Channels 6 and 7 are not used to generate channel triggers.
mbed_official 324:406fd2029f23 2948 */
mbed_official 324:406fd2029f23 2949 typedef union _hw_ftm_exttrig
mbed_official 324:406fd2029f23 2950 {
mbed_official 324:406fd2029f23 2951 uint32_t U;
mbed_official 324:406fd2029f23 2952 struct _hw_ftm_exttrig_bitfields
mbed_official 324:406fd2029f23 2953 {
mbed_official 324:406fd2029f23 2954 uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */
mbed_official 324:406fd2029f23 2955 uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */
mbed_official 324:406fd2029f23 2956 uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */
mbed_official 324:406fd2029f23 2957 uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */
mbed_official 324:406fd2029f23 2958 uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */
mbed_official 324:406fd2029f23 2959 uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */
mbed_official 324:406fd2029f23 2960 uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */
mbed_official 324:406fd2029f23 2961 uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */
mbed_official 324:406fd2029f23 2962 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 2963 } B;
mbed_official 324:406fd2029f23 2964 } hw_ftm_exttrig_t;
mbed_official 324:406fd2029f23 2965
mbed_official 324:406fd2029f23 2966 /*!
mbed_official 324:406fd2029f23 2967 * @name Constants and macros for entire FTM_EXTTRIG register
mbed_official 324:406fd2029f23 2968 */
mbed_official 324:406fd2029f23 2969 /*@{*/
mbed_official 324:406fd2029f23 2970 #define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
mbed_official 324:406fd2029f23 2971
mbed_official 324:406fd2029f23 2972 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
mbed_official 324:406fd2029f23 2973 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
mbed_official 324:406fd2029f23 2974 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
mbed_official 324:406fd2029f23 2975 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
mbed_official 324:406fd2029f23 2976 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2977 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2978 /*@}*/
mbed_official 324:406fd2029f23 2979
mbed_official 324:406fd2029f23 2980 /*
mbed_official 324:406fd2029f23 2981 * Constants & macros for individual FTM_EXTTRIG bitfields
mbed_official 324:406fd2029f23 2982 */
mbed_official 324:406fd2029f23 2983
mbed_official 324:406fd2029f23 2984 /*!
mbed_official 324:406fd2029f23 2985 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
mbed_official 324:406fd2029f23 2986 *
mbed_official 324:406fd2029f23 2987 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 2988 * to the CnV register.
mbed_official 324:406fd2029f23 2989 *
mbed_official 324:406fd2029f23 2990 * Values:
mbed_official 324:406fd2029f23 2991 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 2992 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 2993 */
mbed_official 324:406fd2029f23 2994 /*@{*/
mbed_official 324:406fd2029f23 2995 #define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
mbed_official 324:406fd2029f23 2996 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
mbed_official 324:406fd2029f23 2997 #define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
mbed_official 324:406fd2029f23 2998
mbed_official 324:406fd2029f23 2999 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
mbed_official 324:406fd2029f23 3000 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
mbed_official 324:406fd2029f23 3001
mbed_official 324:406fd2029f23 3002 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
mbed_official 324:406fd2029f23 3003 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
mbed_official 324:406fd2029f23 3004
mbed_official 324:406fd2029f23 3005 /*! @brief Set the CH2TRIG field to a new value. */
mbed_official 324:406fd2029f23 3006 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
mbed_official 324:406fd2029f23 3007 /*@}*/
mbed_official 324:406fd2029f23 3008
mbed_official 324:406fd2029f23 3009 /*!
mbed_official 324:406fd2029f23 3010 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
mbed_official 324:406fd2029f23 3011 *
mbed_official 324:406fd2029f23 3012 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 3013 * to the CnV register.
mbed_official 324:406fd2029f23 3014 *
mbed_official 324:406fd2029f23 3015 * Values:
mbed_official 324:406fd2029f23 3016 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 3017 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 3018 */
mbed_official 324:406fd2029f23 3019 /*@{*/
mbed_official 324:406fd2029f23 3020 #define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
mbed_official 324:406fd2029f23 3021 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
mbed_official 324:406fd2029f23 3022 #define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
mbed_official 324:406fd2029f23 3023
mbed_official 324:406fd2029f23 3024 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
mbed_official 324:406fd2029f23 3025 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
mbed_official 324:406fd2029f23 3026
mbed_official 324:406fd2029f23 3027 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
mbed_official 324:406fd2029f23 3028 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
mbed_official 324:406fd2029f23 3029
mbed_official 324:406fd2029f23 3030 /*! @brief Set the CH3TRIG field to a new value. */
mbed_official 324:406fd2029f23 3031 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
mbed_official 324:406fd2029f23 3032 /*@}*/
mbed_official 324:406fd2029f23 3033
mbed_official 324:406fd2029f23 3034 /*!
mbed_official 324:406fd2029f23 3035 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
mbed_official 324:406fd2029f23 3036 *
mbed_official 324:406fd2029f23 3037 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 3038 * to the CnV register.
mbed_official 324:406fd2029f23 3039 *
mbed_official 324:406fd2029f23 3040 * Values:
mbed_official 324:406fd2029f23 3041 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 3042 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 3043 */
mbed_official 324:406fd2029f23 3044 /*@{*/
mbed_official 324:406fd2029f23 3045 #define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
mbed_official 324:406fd2029f23 3046 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
mbed_official 324:406fd2029f23 3047 #define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
mbed_official 324:406fd2029f23 3048
mbed_official 324:406fd2029f23 3049 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
mbed_official 324:406fd2029f23 3050 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
mbed_official 324:406fd2029f23 3051
mbed_official 324:406fd2029f23 3052 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
mbed_official 324:406fd2029f23 3053 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
mbed_official 324:406fd2029f23 3054
mbed_official 324:406fd2029f23 3055 /*! @brief Set the CH4TRIG field to a new value. */
mbed_official 324:406fd2029f23 3056 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
mbed_official 324:406fd2029f23 3057 /*@}*/
mbed_official 324:406fd2029f23 3058
mbed_official 324:406fd2029f23 3059 /*!
mbed_official 324:406fd2029f23 3060 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
mbed_official 324:406fd2029f23 3061 *
mbed_official 324:406fd2029f23 3062 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 3063 * to the CnV register.
mbed_official 324:406fd2029f23 3064 *
mbed_official 324:406fd2029f23 3065 * Values:
mbed_official 324:406fd2029f23 3066 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 3067 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 3068 */
mbed_official 324:406fd2029f23 3069 /*@{*/
mbed_official 324:406fd2029f23 3070 #define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
mbed_official 324:406fd2029f23 3071 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
mbed_official 324:406fd2029f23 3072 #define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
mbed_official 324:406fd2029f23 3073
mbed_official 324:406fd2029f23 3074 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
mbed_official 324:406fd2029f23 3075 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
mbed_official 324:406fd2029f23 3076
mbed_official 324:406fd2029f23 3077 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
mbed_official 324:406fd2029f23 3078 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
mbed_official 324:406fd2029f23 3079
mbed_official 324:406fd2029f23 3080 /*! @brief Set the CH5TRIG field to a new value. */
mbed_official 324:406fd2029f23 3081 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
mbed_official 324:406fd2029f23 3082 /*@}*/
mbed_official 324:406fd2029f23 3083
mbed_official 324:406fd2029f23 3084 /*!
mbed_official 324:406fd2029f23 3085 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
mbed_official 324:406fd2029f23 3086 *
mbed_official 324:406fd2029f23 3087 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 3088 * to the CnV register.
mbed_official 324:406fd2029f23 3089 *
mbed_official 324:406fd2029f23 3090 * Values:
mbed_official 324:406fd2029f23 3091 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 3092 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 3093 */
mbed_official 324:406fd2029f23 3094 /*@{*/
mbed_official 324:406fd2029f23 3095 #define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
mbed_official 324:406fd2029f23 3096 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
mbed_official 324:406fd2029f23 3097 #define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
mbed_official 324:406fd2029f23 3098
mbed_official 324:406fd2029f23 3099 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
mbed_official 324:406fd2029f23 3100 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
mbed_official 324:406fd2029f23 3101
mbed_official 324:406fd2029f23 3102 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
mbed_official 324:406fd2029f23 3103 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
mbed_official 324:406fd2029f23 3104
mbed_official 324:406fd2029f23 3105 /*! @brief Set the CH0TRIG field to a new value. */
mbed_official 324:406fd2029f23 3106 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
mbed_official 324:406fd2029f23 3107 /*@}*/
mbed_official 324:406fd2029f23 3108
mbed_official 324:406fd2029f23 3109 /*!
mbed_official 324:406fd2029f23 3110 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
mbed_official 324:406fd2029f23 3111 *
mbed_official 324:406fd2029f23 3112 * Enables the generation of the channel trigger when the FTM counter is equal
mbed_official 324:406fd2029f23 3113 * to the CnV register.
mbed_official 324:406fd2029f23 3114 *
mbed_official 324:406fd2029f23 3115 * Values:
mbed_official 324:406fd2029f23 3116 * - 0 - The generation of the channel trigger is disabled.
mbed_official 324:406fd2029f23 3117 * - 1 - The generation of the channel trigger is enabled.
mbed_official 324:406fd2029f23 3118 */
mbed_official 324:406fd2029f23 3119 /*@{*/
mbed_official 324:406fd2029f23 3120 #define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
mbed_official 324:406fd2029f23 3121 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
mbed_official 324:406fd2029f23 3122 #define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
mbed_official 324:406fd2029f23 3123
mbed_official 324:406fd2029f23 3124 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
mbed_official 324:406fd2029f23 3125 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
mbed_official 324:406fd2029f23 3126
mbed_official 324:406fd2029f23 3127 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
mbed_official 324:406fd2029f23 3128 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
mbed_official 324:406fd2029f23 3129
mbed_official 324:406fd2029f23 3130 /*! @brief Set the CH1TRIG field to a new value. */
mbed_official 324:406fd2029f23 3131 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
mbed_official 324:406fd2029f23 3132 /*@}*/
mbed_official 324:406fd2029f23 3133
mbed_official 324:406fd2029f23 3134 /*!
mbed_official 324:406fd2029f23 3135 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
mbed_official 324:406fd2029f23 3136 *
mbed_official 324:406fd2029f23 3137 * Enables the generation of the trigger when the FTM counter is equal to the
mbed_official 324:406fd2029f23 3138 * CNTIN register.
mbed_official 324:406fd2029f23 3139 *
mbed_official 324:406fd2029f23 3140 * Values:
mbed_official 324:406fd2029f23 3141 * - 0 - The generation of initialization trigger is disabled.
mbed_official 324:406fd2029f23 3142 * - 1 - The generation of initialization trigger is enabled.
mbed_official 324:406fd2029f23 3143 */
mbed_official 324:406fd2029f23 3144 /*@{*/
mbed_official 324:406fd2029f23 3145 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
mbed_official 324:406fd2029f23 3146 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
mbed_official 324:406fd2029f23 3147 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
mbed_official 324:406fd2029f23 3148
mbed_official 324:406fd2029f23 3149 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
mbed_official 324:406fd2029f23 3150 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
mbed_official 324:406fd2029f23 3151
mbed_official 324:406fd2029f23 3152 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
mbed_official 324:406fd2029f23 3153 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
mbed_official 324:406fd2029f23 3154
mbed_official 324:406fd2029f23 3155 /*! @brief Set the INITTRIGEN field to a new value. */
mbed_official 324:406fd2029f23 3156 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
mbed_official 324:406fd2029f23 3157 /*@}*/
mbed_official 324:406fd2029f23 3158
mbed_official 324:406fd2029f23 3159 /*!
mbed_official 324:406fd2029f23 3160 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
mbed_official 324:406fd2029f23 3161 *
mbed_official 324:406fd2029f23 3162 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
mbed_official 324:406fd2029f23 3163 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
mbed_official 324:406fd2029f23 3164 * has no effect. If another channel trigger is generated before the clearing
mbed_official 324:406fd2029f23 3165 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
mbed_official 324:406fd2029f23 3166 * sequence is completed for the earlier TRIGF.
mbed_official 324:406fd2029f23 3167 *
mbed_official 324:406fd2029f23 3168 * Values:
mbed_official 324:406fd2029f23 3169 * - 0 - No channel trigger was generated.
mbed_official 324:406fd2029f23 3170 * - 1 - A channel trigger was generated.
mbed_official 324:406fd2029f23 3171 */
mbed_official 324:406fd2029f23 3172 /*@{*/
mbed_official 324:406fd2029f23 3173 #define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */
mbed_official 324:406fd2029f23 3174 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
mbed_official 324:406fd2029f23 3175 #define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
mbed_official 324:406fd2029f23 3176
mbed_official 324:406fd2029f23 3177 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
mbed_official 324:406fd2029f23 3178 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
mbed_official 324:406fd2029f23 3179
mbed_official 324:406fd2029f23 3180 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
mbed_official 324:406fd2029f23 3181 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
mbed_official 324:406fd2029f23 3182
mbed_official 324:406fd2029f23 3183 /*! @brief Set the TRIGF field to a new value. */
mbed_official 324:406fd2029f23 3184 #define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
mbed_official 324:406fd2029f23 3185 /*@}*/
mbed_official 324:406fd2029f23 3186
mbed_official 324:406fd2029f23 3187 /*******************************************************************************
mbed_official 324:406fd2029f23 3188 * HW_FTM_POL - Channels Polarity
mbed_official 324:406fd2029f23 3189 ******************************************************************************/
mbed_official 324:406fd2029f23 3190
mbed_official 324:406fd2029f23 3191 /*!
mbed_official 324:406fd2029f23 3192 * @brief HW_FTM_POL - Channels Polarity (RW)
mbed_official 324:406fd2029f23 3193 *
mbed_official 324:406fd2029f23 3194 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3195 *
mbed_official 324:406fd2029f23 3196 * This register defines the output polarity of the FTM channels. The safe value
mbed_official 324:406fd2029f23 3197 * that is driven in a channel output when the fault control is enabled and a
mbed_official 324:406fd2029f23 3198 * fault condition is detected is the inactive state of the channel. That is, the
mbed_official 324:406fd2029f23 3199 * safe value of a channel is the value of its POL bit.
mbed_official 324:406fd2029f23 3200 */
mbed_official 324:406fd2029f23 3201 typedef union _hw_ftm_pol
mbed_official 324:406fd2029f23 3202 {
mbed_official 324:406fd2029f23 3203 uint32_t U;
mbed_official 324:406fd2029f23 3204 struct _hw_ftm_pol_bitfields
mbed_official 324:406fd2029f23 3205 {
mbed_official 324:406fd2029f23 3206 uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */
mbed_official 324:406fd2029f23 3207 uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */
mbed_official 324:406fd2029f23 3208 uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */
mbed_official 324:406fd2029f23 3209 uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */
mbed_official 324:406fd2029f23 3210 uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */
mbed_official 324:406fd2029f23 3211 uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */
mbed_official 324:406fd2029f23 3212 uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */
mbed_official 324:406fd2029f23 3213 uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */
mbed_official 324:406fd2029f23 3214 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 3215 } B;
mbed_official 324:406fd2029f23 3216 } hw_ftm_pol_t;
mbed_official 324:406fd2029f23 3217
mbed_official 324:406fd2029f23 3218 /*!
mbed_official 324:406fd2029f23 3219 * @name Constants and macros for entire FTM_POL register
mbed_official 324:406fd2029f23 3220 */
mbed_official 324:406fd2029f23 3221 /*@{*/
mbed_official 324:406fd2029f23 3222 #define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
mbed_official 324:406fd2029f23 3223
mbed_official 324:406fd2029f23 3224 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
mbed_official 324:406fd2029f23 3225 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
mbed_official 324:406fd2029f23 3226 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
mbed_official 324:406fd2029f23 3227 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
mbed_official 324:406fd2029f23 3228 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3229 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3230 /*@}*/
mbed_official 324:406fd2029f23 3231
mbed_official 324:406fd2029f23 3232 /*
mbed_official 324:406fd2029f23 3233 * Constants & macros for individual FTM_POL bitfields
mbed_official 324:406fd2029f23 3234 */
mbed_official 324:406fd2029f23 3235
mbed_official 324:406fd2029f23 3236 /*!
mbed_official 324:406fd2029f23 3237 * @name Register FTM_POL, field POL0[0] (RW)
mbed_official 324:406fd2029f23 3238 *
mbed_official 324:406fd2029f23 3239 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3240 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3241 *
mbed_official 324:406fd2029f23 3242 * Values:
mbed_official 324:406fd2029f23 3243 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3244 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3245 */
mbed_official 324:406fd2029f23 3246 /*@{*/
mbed_official 324:406fd2029f23 3247 #define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */
mbed_official 324:406fd2029f23 3248 #define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
mbed_official 324:406fd2029f23 3249 #define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */
mbed_official 324:406fd2029f23 3250
mbed_official 324:406fd2029f23 3251 /*! @brief Read current value of the FTM_POL_POL0 field. */
mbed_official 324:406fd2029f23 3252 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
mbed_official 324:406fd2029f23 3253
mbed_official 324:406fd2029f23 3254 /*! @brief Format value for bitfield FTM_POL_POL0. */
mbed_official 324:406fd2029f23 3255 #define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
mbed_official 324:406fd2029f23 3256
mbed_official 324:406fd2029f23 3257 /*! @brief Set the POL0 field to a new value. */
mbed_official 324:406fd2029f23 3258 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
mbed_official 324:406fd2029f23 3259 /*@}*/
mbed_official 324:406fd2029f23 3260
mbed_official 324:406fd2029f23 3261 /*!
mbed_official 324:406fd2029f23 3262 * @name Register FTM_POL, field POL1[1] (RW)
mbed_official 324:406fd2029f23 3263 *
mbed_official 324:406fd2029f23 3264 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3265 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3266 *
mbed_official 324:406fd2029f23 3267 * Values:
mbed_official 324:406fd2029f23 3268 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3269 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3270 */
mbed_official 324:406fd2029f23 3271 /*@{*/
mbed_official 324:406fd2029f23 3272 #define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */
mbed_official 324:406fd2029f23 3273 #define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
mbed_official 324:406fd2029f23 3274 #define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */
mbed_official 324:406fd2029f23 3275
mbed_official 324:406fd2029f23 3276 /*! @brief Read current value of the FTM_POL_POL1 field. */
mbed_official 324:406fd2029f23 3277 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
mbed_official 324:406fd2029f23 3278
mbed_official 324:406fd2029f23 3279 /*! @brief Format value for bitfield FTM_POL_POL1. */
mbed_official 324:406fd2029f23 3280 #define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
mbed_official 324:406fd2029f23 3281
mbed_official 324:406fd2029f23 3282 /*! @brief Set the POL1 field to a new value. */
mbed_official 324:406fd2029f23 3283 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
mbed_official 324:406fd2029f23 3284 /*@}*/
mbed_official 324:406fd2029f23 3285
mbed_official 324:406fd2029f23 3286 /*!
mbed_official 324:406fd2029f23 3287 * @name Register FTM_POL, field POL2[2] (RW)
mbed_official 324:406fd2029f23 3288 *
mbed_official 324:406fd2029f23 3289 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3290 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3291 *
mbed_official 324:406fd2029f23 3292 * Values:
mbed_official 324:406fd2029f23 3293 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3294 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3295 */
mbed_official 324:406fd2029f23 3296 /*@{*/
mbed_official 324:406fd2029f23 3297 #define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */
mbed_official 324:406fd2029f23 3298 #define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
mbed_official 324:406fd2029f23 3299 #define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */
mbed_official 324:406fd2029f23 3300
mbed_official 324:406fd2029f23 3301 /*! @brief Read current value of the FTM_POL_POL2 field. */
mbed_official 324:406fd2029f23 3302 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
mbed_official 324:406fd2029f23 3303
mbed_official 324:406fd2029f23 3304 /*! @brief Format value for bitfield FTM_POL_POL2. */
mbed_official 324:406fd2029f23 3305 #define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
mbed_official 324:406fd2029f23 3306
mbed_official 324:406fd2029f23 3307 /*! @brief Set the POL2 field to a new value. */
mbed_official 324:406fd2029f23 3308 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
mbed_official 324:406fd2029f23 3309 /*@}*/
mbed_official 324:406fd2029f23 3310
mbed_official 324:406fd2029f23 3311 /*!
mbed_official 324:406fd2029f23 3312 * @name Register FTM_POL, field POL3[3] (RW)
mbed_official 324:406fd2029f23 3313 *
mbed_official 324:406fd2029f23 3314 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3315 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3316 *
mbed_official 324:406fd2029f23 3317 * Values:
mbed_official 324:406fd2029f23 3318 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3319 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3320 */
mbed_official 324:406fd2029f23 3321 /*@{*/
mbed_official 324:406fd2029f23 3322 #define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */
mbed_official 324:406fd2029f23 3323 #define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
mbed_official 324:406fd2029f23 3324 #define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */
mbed_official 324:406fd2029f23 3325
mbed_official 324:406fd2029f23 3326 /*! @brief Read current value of the FTM_POL_POL3 field. */
mbed_official 324:406fd2029f23 3327 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
mbed_official 324:406fd2029f23 3328
mbed_official 324:406fd2029f23 3329 /*! @brief Format value for bitfield FTM_POL_POL3. */
mbed_official 324:406fd2029f23 3330 #define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
mbed_official 324:406fd2029f23 3331
mbed_official 324:406fd2029f23 3332 /*! @brief Set the POL3 field to a new value. */
mbed_official 324:406fd2029f23 3333 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
mbed_official 324:406fd2029f23 3334 /*@}*/
mbed_official 324:406fd2029f23 3335
mbed_official 324:406fd2029f23 3336 /*!
mbed_official 324:406fd2029f23 3337 * @name Register FTM_POL, field POL4[4] (RW)
mbed_official 324:406fd2029f23 3338 *
mbed_official 324:406fd2029f23 3339 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3340 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3341 *
mbed_official 324:406fd2029f23 3342 * Values:
mbed_official 324:406fd2029f23 3343 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3344 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3345 */
mbed_official 324:406fd2029f23 3346 /*@{*/
mbed_official 324:406fd2029f23 3347 #define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */
mbed_official 324:406fd2029f23 3348 #define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
mbed_official 324:406fd2029f23 3349 #define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */
mbed_official 324:406fd2029f23 3350
mbed_official 324:406fd2029f23 3351 /*! @brief Read current value of the FTM_POL_POL4 field. */
mbed_official 324:406fd2029f23 3352 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
mbed_official 324:406fd2029f23 3353
mbed_official 324:406fd2029f23 3354 /*! @brief Format value for bitfield FTM_POL_POL4. */
mbed_official 324:406fd2029f23 3355 #define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
mbed_official 324:406fd2029f23 3356
mbed_official 324:406fd2029f23 3357 /*! @brief Set the POL4 field to a new value. */
mbed_official 324:406fd2029f23 3358 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
mbed_official 324:406fd2029f23 3359 /*@}*/
mbed_official 324:406fd2029f23 3360
mbed_official 324:406fd2029f23 3361 /*!
mbed_official 324:406fd2029f23 3362 * @name Register FTM_POL, field POL5[5] (RW)
mbed_official 324:406fd2029f23 3363 *
mbed_official 324:406fd2029f23 3364 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3365 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3366 *
mbed_official 324:406fd2029f23 3367 * Values:
mbed_official 324:406fd2029f23 3368 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3369 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3370 */
mbed_official 324:406fd2029f23 3371 /*@{*/
mbed_official 324:406fd2029f23 3372 #define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */
mbed_official 324:406fd2029f23 3373 #define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
mbed_official 324:406fd2029f23 3374 #define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */
mbed_official 324:406fd2029f23 3375
mbed_official 324:406fd2029f23 3376 /*! @brief Read current value of the FTM_POL_POL5 field. */
mbed_official 324:406fd2029f23 3377 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
mbed_official 324:406fd2029f23 3378
mbed_official 324:406fd2029f23 3379 /*! @brief Format value for bitfield FTM_POL_POL5. */
mbed_official 324:406fd2029f23 3380 #define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
mbed_official 324:406fd2029f23 3381
mbed_official 324:406fd2029f23 3382 /*! @brief Set the POL5 field to a new value. */
mbed_official 324:406fd2029f23 3383 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
mbed_official 324:406fd2029f23 3384 /*@}*/
mbed_official 324:406fd2029f23 3385
mbed_official 324:406fd2029f23 3386 /*!
mbed_official 324:406fd2029f23 3387 * @name Register FTM_POL, field POL6[6] (RW)
mbed_official 324:406fd2029f23 3388 *
mbed_official 324:406fd2029f23 3389 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3390 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3391 *
mbed_official 324:406fd2029f23 3392 * Values:
mbed_official 324:406fd2029f23 3393 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3394 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3395 */
mbed_official 324:406fd2029f23 3396 /*@{*/
mbed_official 324:406fd2029f23 3397 #define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */
mbed_official 324:406fd2029f23 3398 #define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
mbed_official 324:406fd2029f23 3399 #define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */
mbed_official 324:406fd2029f23 3400
mbed_official 324:406fd2029f23 3401 /*! @brief Read current value of the FTM_POL_POL6 field. */
mbed_official 324:406fd2029f23 3402 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
mbed_official 324:406fd2029f23 3403
mbed_official 324:406fd2029f23 3404 /*! @brief Format value for bitfield FTM_POL_POL6. */
mbed_official 324:406fd2029f23 3405 #define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
mbed_official 324:406fd2029f23 3406
mbed_official 324:406fd2029f23 3407 /*! @brief Set the POL6 field to a new value. */
mbed_official 324:406fd2029f23 3408 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
mbed_official 324:406fd2029f23 3409 /*@}*/
mbed_official 324:406fd2029f23 3410
mbed_official 324:406fd2029f23 3411 /*!
mbed_official 324:406fd2029f23 3412 * @name Register FTM_POL, field POL7[7] (RW)
mbed_official 324:406fd2029f23 3413 *
mbed_official 324:406fd2029f23 3414 * Defines the polarity of the channel output. This field is write protected. It
mbed_official 324:406fd2029f23 3415 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3416 *
mbed_official 324:406fd2029f23 3417 * Values:
mbed_official 324:406fd2029f23 3418 * - 0 - The channel polarity is active high.
mbed_official 324:406fd2029f23 3419 * - 1 - The channel polarity is active low.
mbed_official 324:406fd2029f23 3420 */
mbed_official 324:406fd2029f23 3421 /*@{*/
mbed_official 324:406fd2029f23 3422 #define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */
mbed_official 324:406fd2029f23 3423 #define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
mbed_official 324:406fd2029f23 3424 #define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */
mbed_official 324:406fd2029f23 3425
mbed_official 324:406fd2029f23 3426 /*! @brief Read current value of the FTM_POL_POL7 field. */
mbed_official 324:406fd2029f23 3427 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
mbed_official 324:406fd2029f23 3428
mbed_official 324:406fd2029f23 3429 /*! @brief Format value for bitfield FTM_POL_POL7. */
mbed_official 324:406fd2029f23 3430 #define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
mbed_official 324:406fd2029f23 3431
mbed_official 324:406fd2029f23 3432 /*! @brief Set the POL7 field to a new value. */
mbed_official 324:406fd2029f23 3433 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
mbed_official 324:406fd2029f23 3434 /*@}*/
mbed_official 324:406fd2029f23 3435
mbed_official 324:406fd2029f23 3436 /*******************************************************************************
mbed_official 324:406fd2029f23 3437 * HW_FTM_FMS - Fault Mode Status
mbed_official 324:406fd2029f23 3438 ******************************************************************************/
mbed_official 324:406fd2029f23 3439
mbed_official 324:406fd2029f23 3440 /*!
mbed_official 324:406fd2029f23 3441 * @brief HW_FTM_FMS - Fault Mode Status (RW)
mbed_official 324:406fd2029f23 3442 *
mbed_official 324:406fd2029f23 3443 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3444 *
mbed_official 324:406fd2029f23 3445 * This register contains the fault detection flags, write protection enable
mbed_official 324:406fd2029f23 3446 * bit, and the logic OR of the enabled fault inputs.
mbed_official 324:406fd2029f23 3447 */
mbed_official 324:406fd2029f23 3448 typedef union _hw_ftm_fms
mbed_official 324:406fd2029f23 3449 {
mbed_official 324:406fd2029f23 3450 uint32_t U;
mbed_official 324:406fd2029f23 3451 struct _hw_ftm_fms_bitfields
mbed_official 324:406fd2029f23 3452 {
mbed_official 324:406fd2029f23 3453 uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */
mbed_official 324:406fd2029f23 3454 uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */
mbed_official 324:406fd2029f23 3455 uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */
mbed_official 324:406fd2029f23 3456 uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */
mbed_official 324:406fd2029f23 3457 uint32_t RESERVED0 : 1; /*!< [4] */
mbed_official 324:406fd2029f23 3458 uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */
mbed_official 324:406fd2029f23 3459 uint32_t WPEN : 1; /*!< [6] Write Protection Enable */
mbed_official 324:406fd2029f23 3460 uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */
mbed_official 324:406fd2029f23 3461 uint32_t RESERVED1 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 3462 } B;
mbed_official 324:406fd2029f23 3463 } hw_ftm_fms_t;
mbed_official 324:406fd2029f23 3464
mbed_official 324:406fd2029f23 3465 /*!
mbed_official 324:406fd2029f23 3466 * @name Constants and macros for entire FTM_FMS register
mbed_official 324:406fd2029f23 3467 */
mbed_official 324:406fd2029f23 3468 /*@{*/
mbed_official 324:406fd2029f23 3469 #define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
mbed_official 324:406fd2029f23 3470
mbed_official 324:406fd2029f23 3471 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
mbed_official 324:406fd2029f23 3472 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
mbed_official 324:406fd2029f23 3473 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
mbed_official 324:406fd2029f23 3474 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
mbed_official 324:406fd2029f23 3475 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3476 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3477 /*@}*/
mbed_official 324:406fd2029f23 3478
mbed_official 324:406fd2029f23 3479 /*
mbed_official 324:406fd2029f23 3480 * Constants & macros for individual FTM_FMS bitfields
mbed_official 324:406fd2029f23 3481 */
mbed_official 324:406fd2029f23 3482
mbed_official 324:406fd2029f23 3483 /*!
mbed_official 324:406fd2029f23 3484 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
mbed_official 324:406fd2029f23 3485 *
mbed_official 324:406fd2029f23 3486 * Set by hardware when fault control is enabled, the corresponding fault input
mbed_official 324:406fd2029f23 3487 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
mbed_official 324:406fd2029f23 3488 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
mbed_official 324:406fd2029f23 3489 * FAULTF0 while there is no existing fault condition at the corresponding fault
mbed_official 324:406fd2029f23 3490 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
mbed_official 324:406fd2029f23 3491 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official 324:406fd2029f23 3492 * fault input before the clearing sequence is completed, the sequence is reset
mbed_official 324:406fd2029f23 3493 * so FAULTF0 remains set after the clearing sequence is completed for the
mbed_official 324:406fd2029f23 3494 * earlier fault condition.
mbed_official 324:406fd2029f23 3495 *
mbed_official 324:406fd2029f23 3496 * Values:
mbed_official 324:406fd2029f23 3497 * - 0 - No fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3498 * - 1 - A fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3499 */
mbed_official 324:406fd2029f23 3500 /*@{*/
mbed_official 324:406fd2029f23 3501 #define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */
mbed_official 324:406fd2029f23 3502 #define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
mbed_official 324:406fd2029f23 3503 #define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
mbed_official 324:406fd2029f23 3504
mbed_official 324:406fd2029f23 3505 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
mbed_official 324:406fd2029f23 3506 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
mbed_official 324:406fd2029f23 3507
mbed_official 324:406fd2029f23 3508 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
mbed_official 324:406fd2029f23 3509 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
mbed_official 324:406fd2029f23 3510
mbed_official 324:406fd2029f23 3511 /*! @brief Set the FAULTF0 field to a new value. */
mbed_official 324:406fd2029f23 3512 #define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
mbed_official 324:406fd2029f23 3513 /*@}*/
mbed_official 324:406fd2029f23 3514
mbed_official 324:406fd2029f23 3515 /*!
mbed_official 324:406fd2029f23 3516 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
mbed_official 324:406fd2029f23 3517 *
mbed_official 324:406fd2029f23 3518 * Set by hardware when fault control is enabled, the corresponding fault input
mbed_official 324:406fd2029f23 3519 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
mbed_official 324:406fd2029f23 3520 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
mbed_official 324:406fd2029f23 3521 * FAULTF1 while there is no existing fault condition at the corresponding fault
mbed_official 324:406fd2029f23 3522 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
mbed_official 324:406fd2029f23 3523 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official 324:406fd2029f23 3524 * fault input before the clearing sequence is completed, the sequence is reset
mbed_official 324:406fd2029f23 3525 * so FAULTF1 remains set after the clearing sequence is completed for the
mbed_official 324:406fd2029f23 3526 * earlier fault condition.
mbed_official 324:406fd2029f23 3527 *
mbed_official 324:406fd2029f23 3528 * Values:
mbed_official 324:406fd2029f23 3529 * - 0 - No fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3530 * - 1 - A fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3531 */
mbed_official 324:406fd2029f23 3532 /*@{*/
mbed_official 324:406fd2029f23 3533 #define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */
mbed_official 324:406fd2029f23 3534 #define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
mbed_official 324:406fd2029f23 3535 #define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
mbed_official 324:406fd2029f23 3536
mbed_official 324:406fd2029f23 3537 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
mbed_official 324:406fd2029f23 3538 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
mbed_official 324:406fd2029f23 3539
mbed_official 324:406fd2029f23 3540 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
mbed_official 324:406fd2029f23 3541 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
mbed_official 324:406fd2029f23 3542
mbed_official 324:406fd2029f23 3543 /*! @brief Set the FAULTF1 field to a new value. */
mbed_official 324:406fd2029f23 3544 #define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
mbed_official 324:406fd2029f23 3545 /*@}*/
mbed_official 324:406fd2029f23 3546
mbed_official 324:406fd2029f23 3547 /*!
mbed_official 324:406fd2029f23 3548 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
mbed_official 324:406fd2029f23 3549 *
mbed_official 324:406fd2029f23 3550 * Set by hardware when fault control is enabled, the corresponding fault input
mbed_official 324:406fd2029f23 3551 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
mbed_official 324:406fd2029f23 3552 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
mbed_official 324:406fd2029f23 3553 * FAULTF2 while there is no existing fault condition at the corresponding fault
mbed_official 324:406fd2029f23 3554 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
mbed_official 324:406fd2029f23 3555 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official 324:406fd2029f23 3556 * fault input before the clearing sequence is completed, the sequence is reset
mbed_official 324:406fd2029f23 3557 * so FAULTF2 remains set after the clearing sequence is completed for the
mbed_official 324:406fd2029f23 3558 * earlier fault condition.
mbed_official 324:406fd2029f23 3559 *
mbed_official 324:406fd2029f23 3560 * Values:
mbed_official 324:406fd2029f23 3561 * - 0 - No fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3562 * - 1 - A fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3563 */
mbed_official 324:406fd2029f23 3564 /*@{*/
mbed_official 324:406fd2029f23 3565 #define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */
mbed_official 324:406fd2029f23 3566 #define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
mbed_official 324:406fd2029f23 3567 #define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
mbed_official 324:406fd2029f23 3568
mbed_official 324:406fd2029f23 3569 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
mbed_official 324:406fd2029f23 3570 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
mbed_official 324:406fd2029f23 3571
mbed_official 324:406fd2029f23 3572 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
mbed_official 324:406fd2029f23 3573 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
mbed_official 324:406fd2029f23 3574
mbed_official 324:406fd2029f23 3575 /*! @brief Set the FAULTF2 field to a new value. */
mbed_official 324:406fd2029f23 3576 #define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
mbed_official 324:406fd2029f23 3577 /*@}*/
mbed_official 324:406fd2029f23 3578
mbed_official 324:406fd2029f23 3579 /*!
mbed_official 324:406fd2029f23 3580 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
mbed_official 324:406fd2029f23 3581 *
mbed_official 324:406fd2029f23 3582 * Set by hardware when fault control is enabled, the corresponding fault input
mbed_official 324:406fd2029f23 3583 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
mbed_official 324:406fd2029f23 3584 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
mbed_official 324:406fd2029f23 3585 * FAULTF3 while there is no existing fault condition at the corresponding fault
mbed_official 324:406fd2029f23 3586 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
mbed_official 324:406fd2029f23 3587 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official 324:406fd2029f23 3588 * fault input before the clearing sequence is completed, the sequence is reset
mbed_official 324:406fd2029f23 3589 * so FAULTF3 remains set after the clearing sequence is completed for the
mbed_official 324:406fd2029f23 3590 * earlier fault condition.
mbed_official 324:406fd2029f23 3591 *
mbed_official 324:406fd2029f23 3592 * Values:
mbed_official 324:406fd2029f23 3593 * - 0 - No fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3594 * - 1 - A fault condition was detected at the fault input.
mbed_official 324:406fd2029f23 3595 */
mbed_official 324:406fd2029f23 3596 /*@{*/
mbed_official 324:406fd2029f23 3597 #define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */
mbed_official 324:406fd2029f23 3598 #define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
mbed_official 324:406fd2029f23 3599 #define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
mbed_official 324:406fd2029f23 3600
mbed_official 324:406fd2029f23 3601 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
mbed_official 324:406fd2029f23 3602 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
mbed_official 324:406fd2029f23 3603
mbed_official 324:406fd2029f23 3604 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
mbed_official 324:406fd2029f23 3605 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
mbed_official 324:406fd2029f23 3606
mbed_official 324:406fd2029f23 3607 /*! @brief Set the FAULTF3 field to a new value. */
mbed_official 324:406fd2029f23 3608 #define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
mbed_official 324:406fd2029f23 3609 /*@}*/
mbed_official 324:406fd2029f23 3610
mbed_official 324:406fd2029f23 3611 /*!
mbed_official 324:406fd2029f23 3612 * @name Register FTM_FMS, field FAULTIN[5] (RO)
mbed_official 324:406fd2029f23 3613 *
mbed_official 324:406fd2029f23 3614 * Represents the logic OR of the enabled fault inputs after their filter (if
mbed_official 324:406fd2029f23 3615 * their filter is enabled) when fault control is enabled.
mbed_official 324:406fd2029f23 3616 *
mbed_official 324:406fd2029f23 3617 * Values:
mbed_official 324:406fd2029f23 3618 * - 0 - The logic OR of the enabled fault inputs is 0.
mbed_official 324:406fd2029f23 3619 * - 1 - The logic OR of the enabled fault inputs is 1.
mbed_official 324:406fd2029f23 3620 */
mbed_official 324:406fd2029f23 3621 /*@{*/
mbed_official 324:406fd2029f23 3622 #define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */
mbed_official 324:406fd2029f23 3623 #define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
mbed_official 324:406fd2029f23 3624 #define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
mbed_official 324:406fd2029f23 3625
mbed_official 324:406fd2029f23 3626 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
mbed_official 324:406fd2029f23 3627 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
mbed_official 324:406fd2029f23 3628 /*@}*/
mbed_official 324:406fd2029f23 3629
mbed_official 324:406fd2029f23 3630 /*!
mbed_official 324:406fd2029f23 3631 * @name Register FTM_FMS, field WPEN[6] (RW)
mbed_official 324:406fd2029f23 3632 *
mbed_official 324:406fd2029f23 3633 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
mbed_official 324:406fd2029f23 3634 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
mbed_official 324:406fd2029f23 3635 * WPDIS. Writing 0 to WPEN has no effect.
mbed_official 324:406fd2029f23 3636 *
mbed_official 324:406fd2029f23 3637 * Values:
mbed_official 324:406fd2029f23 3638 * - 0 - Write protection is disabled. Write protected bits can be written.
mbed_official 324:406fd2029f23 3639 * - 1 - Write protection is enabled. Write protected bits cannot be written.
mbed_official 324:406fd2029f23 3640 */
mbed_official 324:406fd2029f23 3641 /*@{*/
mbed_official 324:406fd2029f23 3642 #define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */
mbed_official 324:406fd2029f23 3643 #define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
mbed_official 324:406fd2029f23 3644 #define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */
mbed_official 324:406fd2029f23 3645
mbed_official 324:406fd2029f23 3646 /*! @brief Read current value of the FTM_FMS_WPEN field. */
mbed_official 324:406fd2029f23 3647 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
mbed_official 324:406fd2029f23 3648
mbed_official 324:406fd2029f23 3649 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
mbed_official 324:406fd2029f23 3650 #define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
mbed_official 324:406fd2029f23 3651
mbed_official 324:406fd2029f23 3652 /*! @brief Set the WPEN field to a new value. */
mbed_official 324:406fd2029f23 3653 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
mbed_official 324:406fd2029f23 3654 /*@}*/
mbed_official 324:406fd2029f23 3655
mbed_official 324:406fd2029f23 3656 /*!
mbed_official 324:406fd2029f23 3657 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
mbed_official 324:406fd2029f23 3658 *
mbed_official 324:406fd2029f23 3659 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
mbed_official 324:406fd2029f23 3660 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
mbed_official 324:406fd2029f23 3661 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
mbed_official 324:406fd2029f23 3662 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
mbed_official 324:406fd2029f23 3663 * detected in an enabled fault input before the clearing sequence is completed, the
mbed_official 324:406fd2029f23 3664 * sequence is reset so FAULTF remains set after the clearing sequence is
mbed_official 324:406fd2029f23 3665 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
mbed_official 324:406fd2029f23 3666 * are cleared individually.
mbed_official 324:406fd2029f23 3667 *
mbed_official 324:406fd2029f23 3668 * Values:
mbed_official 324:406fd2029f23 3669 * - 0 - No fault condition was detected.
mbed_official 324:406fd2029f23 3670 * - 1 - A fault condition was detected.
mbed_official 324:406fd2029f23 3671 */
mbed_official 324:406fd2029f23 3672 /*@{*/
mbed_official 324:406fd2029f23 3673 #define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */
mbed_official 324:406fd2029f23 3674 #define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
mbed_official 324:406fd2029f23 3675 #define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */
mbed_official 324:406fd2029f23 3676
mbed_official 324:406fd2029f23 3677 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
mbed_official 324:406fd2029f23 3678 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
mbed_official 324:406fd2029f23 3679
mbed_official 324:406fd2029f23 3680 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
mbed_official 324:406fd2029f23 3681 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
mbed_official 324:406fd2029f23 3682
mbed_official 324:406fd2029f23 3683 /*! @brief Set the FAULTF field to a new value. */
mbed_official 324:406fd2029f23 3684 #define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
mbed_official 324:406fd2029f23 3685 /*@}*/
mbed_official 324:406fd2029f23 3686
mbed_official 324:406fd2029f23 3687 /*******************************************************************************
mbed_official 324:406fd2029f23 3688 * HW_FTM_FILTER - Input Capture Filter Control
mbed_official 324:406fd2029f23 3689 ******************************************************************************/
mbed_official 324:406fd2029f23 3690
mbed_official 324:406fd2029f23 3691 /*!
mbed_official 324:406fd2029f23 3692 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
mbed_official 324:406fd2029f23 3693 *
mbed_official 324:406fd2029f23 3694 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3695 *
mbed_official 324:406fd2029f23 3696 * This register selects the filter value for the inputs of channels. Channels
mbed_official 324:406fd2029f23 3697 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
mbed_official 324:406fd2029f23 3698 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
mbed_official 324:406fd2029f23 3699 * in input modes. Failure to do this could result in a missing valid signal.
mbed_official 324:406fd2029f23 3700 */
mbed_official 324:406fd2029f23 3701 typedef union _hw_ftm_filter
mbed_official 324:406fd2029f23 3702 {
mbed_official 324:406fd2029f23 3703 uint32_t U;
mbed_official 324:406fd2029f23 3704 struct _hw_ftm_filter_bitfields
mbed_official 324:406fd2029f23 3705 {
mbed_official 324:406fd2029f23 3706 uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */
mbed_official 324:406fd2029f23 3707 uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */
mbed_official 324:406fd2029f23 3708 uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */
mbed_official 324:406fd2029f23 3709 uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */
mbed_official 324:406fd2029f23 3710 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 3711 } B;
mbed_official 324:406fd2029f23 3712 } hw_ftm_filter_t;
mbed_official 324:406fd2029f23 3713
mbed_official 324:406fd2029f23 3714 /*!
mbed_official 324:406fd2029f23 3715 * @name Constants and macros for entire FTM_FILTER register
mbed_official 324:406fd2029f23 3716 */
mbed_official 324:406fd2029f23 3717 /*@{*/
mbed_official 324:406fd2029f23 3718 #define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
mbed_official 324:406fd2029f23 3719
mbed_official 324:406fd2029f23 3720 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
mbed_official 324:406fd2029f23 3721 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
mbed_official 324:406fd2029f23 3722 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
mbed_official 324:406fd2029f23 3723 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
mbed_official 324:406fd2029f23 3724 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3725 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3726 /*@}*/
mbed_official 324:406fd2029f23 3727
mbed_official 324:406fd2029f23 3728 /*
mbed_official 324:406fd2029f23 3729 * Constants & macros for individual FTM_FILTER bitfields
mbed_official 324:406fd2029f23 3730 */
mbed_official 324:406fd2029f23 3731
mbed_official 324:406fd2029f23 3732 /*!
mbed_official 324:406fd2029f23 3733 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
mbed_official 324:406fd2029f23 3734 *
mbed_official 324:406fd2029f23 3735 * Selects the filter value for the channel input. The filter is disabled when
mbed_official 324:406fd2029f23 3736 * the value is zero.
mbed_official 324:406fd2029f23 3737 */
mbed_official 324:406fd2029f23 3738 /*@{*/
mbed_official 324:406fd2029f23 3739 #define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */
mbed_official 324:406fd2029f23 3740 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
mbed_official 324:406fd2029f23 3741 #define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
mbed_official 324:406fd2029f23 3742
mbed_official 324:406fd2029f23 3743 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
mbed_official 324:406fd2029f23 3744 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
mbed_official 324:406fd2029f23 3745
mbed_official 324:406fd2029f23 3746 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
mbed_official 324:406fd2029f23 3747 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
mbed_official 324:406fd2029f23 3748
mbed_official 324:406fd2029f23 3749 /*! @brief Set the CH0FVAL field to a new value. */
mbed_official 324:406fd2029f23 3750 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
mbed_official 324:406fd2029f23 3751 /*@}*/
mbed_official 324:406fd2029f23 3752
mbed_official 324:406fd2029f23 3753 /*!
mbed_official 324:406fd2029f23 3754 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
mbed_official 324:406fd2029f23 3755 *
mbed_official 324:406fd2029f23 3756 * Selects the filter value for the channel input. The filter is disabled when
mbed_official 324:406fd2029f23 3757 * the value is zero.
mbed_official 324:406fd2029f23 3758 */
mbed_official 324:406fd2029f23 3759 /*@{*/
mbed_official 324:406fd2029f23 3760 #define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */
mbed_official 324:406fd2029f23 3761 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
mbed_official 324:406fd2029f23 3762 #define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
mbed_official 324:406fd2029f23 3763
mbed_official 324:406fd2029f23 3764 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
mbed_official 324:406fd2029f23 3765 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
mbed_official 324:406fd2029f23 3766
mbed_official 324:406fd2029f23 3767 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
mbed_official 324:406fd2029f23 3768 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
mbed_official 324:406fd2029f23 3769
mbed_official 324:406fd2029f23 3770 /*! @brief Set the CH1FVAL field to a new value. */
mbed_official 324:406fd2029f23 3771 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
mbed_official 324:406fd2029f23 3772 /*@}*/
mbed_official 324:406fd2029f23 3773
mbed_official 324:406fd2029f23 3774 /*!
mbed_official 324:406fd2029f23 3775 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
mbed_official 324:406fd2029f23 3776 *
mbed_official 324:406fd2029f23 3777 * Selects the filter value for the channel input. The filter is disabled when
mbed_official 324:406fd2029f23 3778 * the value is zero.
mbed_official 324:406fd2029f23 3779 */
mbed_official 324:406fd2029f23 3780 /*@{*/
mbed_official 324:406fd2029f23 3781 #define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */
mbed_official 324:406fd2029f23 3782 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
mbed_official 324:406fd2029f23 3783 #define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
mbed_official 324:406fd2029f23 3784
mbed_official 324:406fd2029f23 3785 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
mbed_official 324:406fd2029f23 3786 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
mbed_official 324:406fd2029f23 3787
mbed_official 324:406fd2029f23 3788 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
mbed_official 324:406fd2029f23 3789 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
mbed_official 324:406fd2029f23 3790
mbed_official 324:406fd2029f23 3791 /*! @brief Set the CH2FVAL field to a new value. */
mbed_official 324:406fd2029f23 3792 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
mbed_official 324:406fd2029f23 3793 /*@}*/
mbed_official 324:406fd2029f23 3794
mbed_official 324:406fd2029f23 3795 /*!
mbed_official 324:406fd2029f23 3796 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
mbed_official 324:406fd2029f23 3797 *
mbed_official 324:406fd2029f23 3798 * Selects the filter value for the channel input. The filter is disabled when
mbed_official 324:406fd2029f23 3799 * the value is zero.
mbed_official 324:406fd2029f23 3800 */
mbed_official 324:406fd2029f23 3801 /*@{*/
mbed_official 324:406fd2029f23 3802 #define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */
mbed_official 324:406fd2029f23 3803 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
mbed_official 324:406fd2029f23 3804 #define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
mbed_official 324:406fd2029f23 3805
mbed_official 324:406fd2029f23 3806 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
mbed_official 324:406fd2029f23 3807 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
mbed_official 324:406fd2029f23 3808
mbed_official 324:406fd2029f23 3809 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
mbed_official 324:406fd2029f23 3810 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
mbed_official 324:406fd2029f23 3811
mbed_official 324:406fd2029f23 3812 /*! @brief Set the CH3FVAL field to a new value. */
mbed_official 324:406fd2029f23 3813 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
mbed_official 324:406fd2029f23 3814 /*@}*/
mbed_official 324:406fd2029f23 3815
mbed_official 324:406fd2029f23 3816 /*******************************************************************************
mbed_official 324:406fd2029f23 3817 * HW_FTM_FLTCTRL - Fault Control
mbed_official 324:406fd2029f23 3818 ******************************************************************************/
mbed_official 324:406fd2029f23 3819
mbed_official 324:406fd2029f23 3820 /*!
mbed_official 324:406fd2029f23 3821 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
mbed_official 324:406fd2029f23 3822 *
mbed_official 324:406fd2029f23 3823 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3824 *
mbed_official 324:406fd2029f23 3825 * This register selects the filter value for the fault inputs, enables the
mbed_official 324:406fd2029f23 3826 * fault inputs and the fault inputs filter.
mbed_official 324:406fd2029f23 3827 */
mbed_official 324:406fd2029f23 3828 typedef union _hw_ftm_fltctrl
mbed_official 324:406fd2029f23 3829 {
mbed_official 324:406fd2029f23 3830 uint32_t U;
mbed_official 324:406fd2029f23 3831 struct _hw_ftm_fltctrl_bitfields
mbed_official 324:406fd2029f23 3832 {
mbed_official 324:406fd2029f23 3833 uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */
mbed_official 324:406fd2029f23 3834 uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */
mbed_official 324:406fd2029f23 3835 uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */
mbed_official 324:406fd2029f23 3836 uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */
mbed_official 324:406fd2029f23 3837 uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */
mbed_official 324:406fd2029f23 3838 uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */
mbed_official 324:406fd2029f23 3839 uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */
mbed_official 324:406fd2029f23 3840 uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */
mbed_official 324:406fd2029f23 3841 uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */
mbed_official 324:406fd2029f23 3842 uint32_t RESERVED0 : 20; /*!< [31:12] */
mbed_official 324:406fd2029f23 3843 } B;
mbed_official 324:406fd2029f23 3844 } hw_ftm_fltctrl_t;
mbed_official 324:406fd2029f23 3845
mbed_official 324:406fd2029f23 3846 /*!
mbed_official 324:406fd2029f23 3847 * @name Constants and macros for entire FTM_FLTCTRL register
mbed_official 324:406fd2029f23 3848 */
mbed_official 324:406fd2029f23 3849 /*@{*/
mbed_official 324:406fd2029f23 3850 #define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
mbed_official 324:406fd2029f23 3851
mbed_official 324:406fd2029f23 3852 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
mbed_official 324:406fd2029f23 3853 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
mbed_official 324:406fd2029f23 3854 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
mbed_official 324:406fd2029f23 3855 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 3856 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3857 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3858 /*@}*/
mbed_official 324:406fd2029f23 3859
mbed_official 324:406fd2029f23 3860 /*
mbed_official 324:406fd2029f23 3861 * Constants & macros for individual FTM_FLTCTRL bitfields
mbed_official 324:406fd2029f23 3862 */
mbed_official 324:406fd2029f23 3863
mbed_official 324:406fd2029f23 3864 /*!
mbed_official 324:406fd2029f23 3865 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
mbed_official 324:406fd2029f23 3866 *
mbed_official 324:406fd2029f23 3867 * Enables the fault input. This field is write protected. It can be written
mbed_official 324:406fd2029f23 3868 * only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3869 *
mbed_official 324:406fd2029f23 3870 * Values:
mbed_official 324:406fd2029f23 3871 * - 0 - Fault input is disabled.
mbed_official 324:406fd2029f23 3872 * - 1 - Fault input is enabled.
mbed_official 324:406fd2029f23 3873 */
mbed_official 324:406fd2029f23 3874 /*@{*/
mbed_official 324:406fd2029f23 3875 #define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
mbed_official 324:406fd2029f23 3876 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
mbed_official 324:406fd2029f23 3877 #define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
mbed_official 324:406fd2029f23 3878
mbed_official 324:406fd2029f23 3879 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
mbed_official 324:406fd2029f23 3880 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
mbed_official 324:406fd2029f23 3881
mbed_official 324:406fd2029f23 3882 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
mbed_official 324:406fd2029f23 3883 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
mbed_official 324:406fd2029f23 3884
mbed_official 324:406fd2029f23 3885 /*! @brief Set the FAULT0EN field to a new value. */
mbed_official 324:406fd2029f23 3886 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
mbed_official 324:406fd2029f23 3887 /*@}*/
mbed_official 324:406fd2029f23 3888
mbed_official 324:406fd2029f23 3889 /*!
mbed_official 324:406fd2029f23 3890 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
mbed_official 324:406fd2029f23 3891 *
mbed_official 324:406fd2029f23 3892 * Enables the fault input. This field is write protected. It can be written
mbed_official 324:406fd2029f23 3893 * only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3894 *
mbed_official 324:406fd2029f23 3895 * Values:
mbed_official 324:406fd2029f23 3896 * - 0 - Fault input is disabled.
mbed_official 324:406fd2029f23 3897 * - 1 - Fault input is enabled.
mbed_official 324:406fd2029f23 3898 */
mbed_official 324:406fd2029f23 3899 /*@{*/
mbed_official 324:406fd2029f23 3900 #define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
mbed_official 324:406fd2029f23 3901 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
mbed_official 324:406fd2029f23 3902 #define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
mbed_official 324:406fd2029f23 3903
mbed_official 324:406fd2029f23 3904 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
mbed_official 324:406fd2029f23 3905 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
mbed_official 324:406fd2029f23 3906
mbed_official 324:406fd2029f23 3907 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
mbed_official 324:406fd2029f23 3908 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
mbed_official 324:406fd2029f23 3909
mbed_official 324:406fd2029f23 3910 /*! @brief Set the FAULT1EN field to a new value. */
mbed_official 324:406fd2029f23 3911 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
mbed_official 324:406fd2029f23 3912 /*@}*/
mbed_official 324:406fd2029f23 3913
mbed_official 324:406fd2029f23 3914 /*!
mbed_official 324:406fd2029f23 3915 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
mbed_official 324:406fd2029f23 3916 *
mbed_official 324:406fd2029f23 3917 * Enables the fault input. This field is write protected. It can be written
mbed_official 324:406fd2029f23 3918 * only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3919 *
mbed_official 324:406fd2029f23 3920 * Values:
mbed_official 324:406fd2029f23 3921 * - 0 - Fault input is disabled.
mbed_official 324:406fd2029f23 3922 * - 1 - Fault input is enabled.
mbed_official 324:406fd2029f23 3923 */
mbed_official 324:406fd2029f23 3924 /*@{*/
mbed_official 324:406fd2029f23 3925 #define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
mbed_official 324:406fd2029f23 3926 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
mbed_official 324:406fd2029f23 3927 #define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
mbed_official 324:406fd2029f23 3928
mbed_official 324:406fd2029f23 3929 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
mbed_official 324:406fd2029f23 3930 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
mbed_official 324:406fd2029f23 3931
mbed_official 324:406fd2029f23 3932 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
mbed_official 324:406fd2029f23 3933 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
mbed_official 324:406fd2029f23 3934
mbed_official 324:406fd2029f23 3935 /*! @brief Set the FAULT2EN field to a new value. */
mbed_official 324:406fd2029f23 3936 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
mbed_official 324:406fd2029f23 3937 /*@}*/
mbed_official 324:406fd2029f23 3938
mbed_official 324:406fd2029f23 3939 /*!
mbed_official 324:406fd2029f23 3940 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
mbed_official 324:406fd2029f23 3941 *
mbed_official 324:406fd2029f23 3942 * Enables the fault input. This field is write protected. It can be written
mbed_official 324:406fd2029f23 3943 * only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3944 *
mbed_official 324:406fd2029f23 3945 * Values:
mbed_official 324:406fd2029f23 3946 * - 0 - Fault input is disabled.
mbed_official 324:406fd2029f23 3947 * - 1 - Fault input is enabled.
mbed_official 324:406fd2029f23 3948 */
mbed_official 324:406fd2029f23 3949 /*@{*/
mbed_official 324:406fd2029f23 3950 #define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
mbed_official 324:406fd2029f23 3951 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
mbed_official 324:406fd2029f23 3952 #define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
mbed_official 324:406fd2029f23 3953
mbed_official 324:406fd2029f23 3954 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
mbed_official 324:406fd2029f23 3955 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
mbed_official 324:406fd2029f23 3956
mbed_official 324:406fd2029f23 3957 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
mbed_official 324:406fd2029f23 3958 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
mbed_official 324:406fd2029f23 3959
mbed_official 324:406fd2029f23 3960 /*! @brief Set the FAULT3EN field to a new value. */
mbed_official 324:406fd2029f23 3961 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
mbed_official 324:406fd2029f23 3962 /*@}*/
mbed_official 324:406fd2029f23 3963
mbed_official 324:406fd2029f23 3964 /*!
mbed_official 324:406fd2029f23 3965 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
mbed_official 324:406fd2029f23 3966 *
mbed_official 324:406fd2029f23 3967 * Enables the filter for the fault input. This field is write protected. It can
mbed_official 324:406fd2029f23 3968 * be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3969 *
mbed_official 324:406fd2029f23 3970 * Values:
mbed_official 324:406fd2029f23 3971 * - 0 - Fault input filter is disabled.
mbed_official 324:406fd2029f23 3972 * - 1 - Fault input filter is enabled.
mbed_official 324:406fd2029f23 3973 */
mbed_official 324:406fd2029f23 3974 /*@{*/
mbed_official 324:406fd2029f23 3975 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
mbed_official 324:406fd2029f23 3976 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
mbed_official 324:406fd2029f23 3977 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
mbed_official 324:406fd2029f23 3978
mbed_official 324:406fd2029f23 3979 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
mbed_official 324:406fd2029f23 3980 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
mbed_official 324:406fd2029f23 3981
mbed_official 324:406fd2029f23 3982 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
mbed_official 324:406fd2029f23 3983 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
mbed_official 324:406fd2029f23 3984
mbed_official 324:406fd2029f23 3985 /*! @brief Set the FFLTR0EN field to a new value. */
mbed_official 324:406fd2029f23 3986 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
mbed_official 324:406fd2029f23 3987 /*@}*/
mbed_official 324:406fd2029f23 3988
mbed_official 324:406fd2029f23 3989 /*!
mbed_official 324:406fd2029f23 3990 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
mbed_official 324:406fd2029f23 3991 *
mbed_official 324:406fd2029f23 3992 * Enables the filter for the fault input. This field is write protected. It can
mbed_official 324:406fd2029f23 3993 * be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 3994 *
mbed_official 324:406fd2029f23 3995 * Values:
mbed_official 324:406fd2029f23 3996 * - 0 - Fault input filter is disabled.
mbed_official 324:406fd2029f23 3997 * - 1 - Fault input filter is enabled.
mbed_official 324:406fd2029f23 3998 */
mbed_official 324:406fd2029f23 3999 /*@{*/
mbed_official 324:406fd2029f23 4000 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
mbed_official 324:406fd2029f23 4001 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
mbed_official 324:406fd2029f23 4002 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
mbed_official 324:406fd2029f23 4003
mbed_official 324:406fd2029f23 4004 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
mbed_official 324:406fd2029f23 4005 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
mbed_official 324:406fd2029f23 4006
mbed_official 324:406fd2029f23 4007 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
mbed_official 324:406fd2029f23 4008 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
mbed_official 324:406fd2029f23 4009
mbed_official 324:406fd2029f23 4010 /*! @brief Set the FFLTR1EN field to a new value. */
mbed_official 324:406fd2029f23 4011 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
mbed_official 324:406fd2029f23 4012 /*@}*/
mbed_official 324:406fd2029f23 4013
mbed_official 324:406fd2029f23 4014 /*!
mbed_official 324:406fd2029f23 4015 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
mbed_official 324:406fd2029f23 4016 *
mbed_official 324:406fd2029f23 4017 * Enables the filter for the fault input. This field is write protected. It can
mbed_official 324:406fd2029f23 4018 * be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4019 *
mbed_official 324:406fd2029f23 4020 * Values:
mbed_official 324:406fd2029f23 4021 * - 0 - Fault input filter is disabled.
mbed_official 324:406fd2029f23 4022 * - 1 - Fault input filter is enabled.
mbed_official 324:406fd2029f23 4023 */
mbed_official 324:406fd2029f23 4024 /*@{*/
mbed_official 324:406fd2029f23 4025 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
mbed_official 324:406fd2029f23 4026 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
mbed_official 324:406fd2029f23 4027 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
mbed_official 324:406fd2029f23 4028
mbed_official 324:406fd2029f23 4029 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
mbed_official 324:406fd2029f23 4030 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
mbed_official 324:406fd2029f23 4031
mbed_official 324:406fd2029f23 4032 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
mbed_official 324:406fd2029f23 4033 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
mbed_official 324:406fd2029f23 4034
mbed_official 324:406fd2029f23 4035 /*! @brief Set the FFLTR2EN field to a new value. */
mbed_official 324:406fd2029f23 4036 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
mbed_official 324:406fd2029f23 4037 /*@}*/
mbed_official 324:406fd2029f23 4038
mbed_official 324:406fd2029f23 4039 /*!
mbed_official 324:406fd2029f23 4040 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
mbed_official 324:406fd2029f23 4041 *
mbed_official 324:406fd2029f23 4042 * Enables the filter for the fault input. This field is write protected. It can
mbed_official 324:406fd2029f23 4043 * be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4044 *
mbed_official 324:406fd2029f23 4045 * Values:
mbed_official 324:406fd2029f23 4046 * - 0 - Fault input filter is disabled.
mbed_official 324:406fd2029f23 4047 * - 1 - Fault input filter is enabled.
mbed_official 324:406fd2029f23 4048 */
mbed_official 324:406fd2029f23 4049 /*@{*/
mbed_official 324:406fd2029f23 4050 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
mbed_official 324:406fd2029f23 4051 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
mbed_official 324:406fd2029f23 4052 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
mbed_official 324:406fd2029f23 4053
mbed_official 324:406fd2029f23 4054 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
mbed_official 324:406fd2029f23 4055 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
mbed_official 324:406fd2029f23 4056
mbed_official 324:406fd2029f23 4057 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
mbed_official 324:406fd2029f23 4058 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
mbed_official 324:406fd2029f23 4059
mbed_official 324:406fd2029f23 4060 /*! @brief Set the FFLTR3EN field to a new value. */
mbed_official 324:406fd2029f23 4061 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
mbed_official 324:406fd2029f23 4062 /*@}*/
mbed_official 324:406fd2029f23 4063
mbed_official 324:406fd2029f23 4064 /*!
mbed_official 324:406fd2029f23 4065 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
mbed_official 324:406fd2029f23 4066 *
mbed_official 324:406fd2029f23 4067 * Selects the filter value for the fault inputs. The fault filter is disabled
mbed_official 324:406fd2029f23 4068 * when the value is zero. Writing to this field has immediate effect and must be
mbed_official 324:406fd2029f23 4069 * done only when the fault control or all fault inputs are disabled. Failure to
mbed_official 324:406fd2029f23 4070 * do this could result in a missing fault detection.
mbed_official 324:406fd2029f23 4071 */
mbed_official 324:406fd2029f23 4072 /*@{*/
mbed_official 324:406fd2029f23 4073 #define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */
mbed_official 324:406fd2029f23 4074 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
mbed_official 324:406fd2029f23 4075 #define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
mbed_official 324:406fd2029f23 4076
mbed_official 324:406fd2029f23 4077 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
mbed_official 324:406fd2029f23 4078 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
mbed_official 324:406fd2029f23 4079
mbed_official 324:406fd2029f23 4080 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
mbed_official 324:406fd2029f23 4081 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
mbed_official 324:406fd2029f23 4082
mbed_official 324:406fd2029f23 4083 /*! @brief Set the FFVAL field to a new value. */
mbed_official 324:406fd2029f23 4084 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
mbed_official 324:406fd2029f23 4085 /*@}*/
mbed_official 324:406fd2029f23 4086
mbed_official 324:406fd2029f23 4087 /*******************************************************************************
mbed_official 324:406fd2029f23 4088 * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official 324:406fd2029f23 4089 ******************************************************************************/
mbed_official 324:406fd2029f23 4090
mbed_official 324:406fd2029f23 4091 /*!
mbed_official 324:406fd2029f23 4092 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
mbed_official 324:406fd2029f23 4093 *
mbed_official 324:406fd2029f23 4094 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4095 *
mbed_official 324:406fd2029f23 4096 * This register has the control and status bits for the Quadrature Decoder mode.
mbed_official 324:406fd2029f23 4097 */
mbed_official 324:406fd2029f23 4098 typedef union _hw_ftm_qdctrl
mbed_official 324:406fd2029f23 4099 {
mbed_official 324:406fd2029f23 4100 uint32_t U;
mbed_official 324:406fd2029f23 4101 struct _hw_ftm_qdctrl_bitfields
mbed_official 324:406fd2029f23 4102 {
mbed_official 324:406fd2029f23 4103 uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */
mbed_official 324:406fd2029f23 4104 uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature
mbed_official 324:406fd2029f23 4105 * Decoder Mode */
mbed_official 324:406fd2029f23 4106 uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature
mbed_official 324:406fd2029f23 4107 * Decoder Mode */
mbed_official 324:406fd2029f23 4108 uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */
mbed_official 324:406fd2029f23 4109 uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */
mbed_official 324:406fd2029f23 4110 uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */
mbed_official 324:406fd2029f23 4111 uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */
mbed_official 324:406fd2029f23 4112 uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */
mbed_official 324:406fd2029f23 4113 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 4114 } B;
mbed_official 324:406fd2029f23 4115 } hw_ftm_qdctrl_t;
mbed_official 324:406fd2029f23 4116
mbed_official 324:406fd2029f23 4117 /*!
mbed_official 324:406fd2029f23 4118 * @name Constants and macros for entire FTM_QDCTRL register
mbed_official 324:406fd2029f23 4119 */
mbed_official 324:406fd2029f23 4120 /*@{*/
mbed_official 324:406fd2029f23 4121 #define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
mbed_official 324:406fd2029f23 4122
mbed_official 324:406fd2029f23 4123 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
mbed_official 324:406fd2029f23 4124 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
mbed_official 324:406fd2029f23 4125 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
mbed_official 324:406fd2029f23 4126 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 4127 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 4128 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 4129 /*@}*/
mbed_official 324:406fd2029f23 4130
mbed_official 324:406fd2029f23 4131 /*
mbed_official 324:406fd2029f23 4132 * Constants & macros for individual FTM_QDCTRL bitfields
mbed_official 324:406fd2029f23 4133 */
mbed_official 324:406fd2029f23 4134
mbed_official 324:406fd2029f23 4135 /*!
mbed_official 324:406fd2029f23 4136 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
mbed_official 324:406fd2029f23 4137 *
mbed_official 324:406fd2029f23 4138 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
mbed_official 324:406fd2029f23 4139 * signals control the FTM counter direction. The Quadrature Decoder mode has
mbed_official 324:406fd2029f23 4140 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
mbed_official 324:406fd2029f23 4141 * It can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4142 *
mbed_official 324:406fd2029f23 4143 * Values:
mbed_official 324:406fd2029f23 4144 * - 0 - Quadrature Decoder mode is disabled.
mbed_official 324:406fd2029f23 4145 * - 1 - Quadrature Decoder mode is enabled.
mbed_official 324:406fd2029f23 4146 */
mbed_official 324:406fd2029f23 4147 /*@{*/
mbed_official 324:406fd2029f23 4148 #define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */
mbed_official 324:406fd2029f23 4149 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
mbed_official 324:406fd2029f23 4150 #define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
mbed_official 324:406fd2029f23 4151
mbed_official 324:406fd2029f23 4152 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
mbed_official 324:406fd2029f23 4153 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
mbed_official 324:406fd2029f23 4154
mbed_official 324:406fd2029f23 4155 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
mbed_official 324:406fd2029f23 4156 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
mbed_official 324:406fd2029f23 4157
mbed_official 324:406fd2029f23 4158 /*! @brief Set the QUADEN field to a new value. */
mbed_official 324:406fd2029f23 4159 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
mbed_official 324:406fd2029f23 4160 /*@}*/
mbed_official 324:406fd2029f23 4161
mbed_official 324:406fd2029f23 4162 /*!
mbed_official 324:406fd2029f23 4163 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
mbed_official 324:406fd2029f23 4164 *
mbed_official 324:406fd2029f23 4165 * Indicates if the TOF bit was set on the top or the bottom of counting.
mbed_official 324:406fd2029f23 4166 *
mbed_official 324:406fd2029f23 4167 * Values:
mbed_official 324:406fd2029f23 4168 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
mbed_official 324:406fd2029f23 4169 * decrement and FTM counter changes from its minimum value (CNTIN register) to
mbed_official 324:406fd2029f23 4170 * its maximum value (MOD register).
mbed_official 324:406fd2029f23 4171 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
mbed_official 324:406fd2029f23 4172 * increment and FTM counter changes from its maximum value (MOD register) to its
mbed_official 324:406fd2029f23 4173 * minimum value (CNTIN register).
mbed_official 324:406fd2029f23 4174 */
mbed_official 324:406fd2029f23 4175 /*@{*/
mbed_official 324:406fd2029f23 4176 #define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */
mbed_official 324:406fd2029f23 4177 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
mbed_official 324:406fd2029f23 4178 #define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
mbed_official 324:406fd2029f23 4179
mbed_official 324:406fd2029f23 4180 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
mbed_official 324:406fd2029f23 4181 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
mbed_official 324:406fd2029f23 4182 /*@}*/
mbed_official 324:406fd2029f23 4183
mbed_official 324:406fd2029f23 4184 /*!
mbed_official 324:406fd2029f23 4185 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
mbed_official 324:406fd2029f23 4186 *
mbed_official 324:406fd2029f23 4187 * Indicates the counting direction.
mbed_official 324:406fd2029f23 4188 *
mbed_official 324:406fd2029f23 4189 * Values:
mbed_official 324:406fd2029f23 4190 * - 0 - Counting direction is decreasing (FTM counter decrement).
mbed_official 324:406fd2029f23 4191 * - 1 - Counting direction is increasing (FTM counter increment).
mbed_official 324:406fd2029f23 4192 */
mbed_official 324:406fd2029f23 4193 /*@{*/
mbed_official 324:406fd2029f23 4194 #define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */
mbed_official 324:406fd2029f23 4195 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
mbed_official 324:406fd2029f23 4196 #define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
mbed_official 324:406fd2029f23 4197
mbed_official 324:406fd2029f23 4198 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
mbed_official 324:406fd2029f23 4199 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
mbed_official 324:406fd2029f23 4200 /*@}*/
mbed_official 324:406fd2029f23 4201
mbed_official 324:406fd2029f23 4202 /*!
mbed_official 324:406fd2029f23 4203 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
mbed_official 324:406fd2029f23 4204 *
mbed_official 324:406fd2029f23 4205 * Selects the encoding mode used in the Quadrature Decoder mode.
mbed_official 324:406fd2029f23 4206 *
mbed_official 324:406fd2029f23 4207 * Values:
mbed_official 324:406fd2029f23 4208 * - 0 - Phase A and phase B encoding mode.
mbed_official 324:406fd2029f23 4209 * - 1 - Count and direction encoding mode.
mbed_official 324:406fd2029f23 4210 */
mbed_official 324:406fd2029f23 4211 /*@{*/
mbed_official 324:406fd2029f23 4212 #define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */
mbed_official 324:406fd2029f23 4213 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
mbed_official 324:406fd2029f23 4214 #define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
mbed_official 324:406fd2029f23 4215
mbed_official 324:406fd2029f23 4216 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
mbed_official 324:406fd2029f23 4217 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
mbed_official 324:406fd2029f23 4218
mbed_official 324:406fd2029f23 4219 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
mbed_official 324:406fd2029f23 4220 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
mbed_official 324:406fd2029f23 4221
mbed_official 324:406fd2029f23 4222 /*! @brief Set the QUADMODE field to a new value. */
mbed_official 324:406fd2029f23 4223 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
mbed_official 324:406fd2029f23 4224 /*@}*/
mbed_official 324:406fd2029f23 4225
mbed_official 324:406fd2029f23 4226 /*!
mbed_official 324:406fd2029f23 4227 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
mbed_official 324:406fd2029f23 4228 *
mbed_official 324:406fd2029f23 4229 * Selects the polarity for the quadrature decoder phase B input.
mbed_official 324:406fd2029f23 4230 *
mbed_official 324:406fd2029f23 4231 * Values:
mbed_official 324:406fd2029f23 4232 * - 0 - Normal polarity. Phase B input signal is not inverted before
mbed_official 324:406fd2029f23 4233 * identifying the rising and falling edges of this signal.
mbed_official 324:406fd2029f23 4234 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
mbed_official 324:406fd2029f23 4235 * the rising and falling edges of this signal.
mbed_official 324:406fd2029f23 4236 */
mbed_official 324:406fd2029f23 4237 /*@{*/
mbed_official 324:406fd2029f23 4238 #define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */
mbed_official 324:406fd2029f23 4239 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
mbed_official 324:406fd2029f23 4240 #define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
mbed_official 324:406fd2029f23 4241
mbed_official 324:406fd2029f23 4242 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
mbed_official 324:406fd2029f23 4243 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
mbed_official 324:406fd2029f23 4244
mbed_official 324:406fd2029f23 4245 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
mbed_official 324:406fd2029f23 4246 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
mbed_official 324:406fd2029f23 4247
mbed_official 324:406fd2029f23 4248 /*! @brief Set the PHBPOL field to a new value. */
mbed_official 324:406fd2029f23 4249 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
mbed_official 324:406fd2029f23 4250 /*@}*/
mbed_official 324:406fd2029f23 4251
mbed_official 324:406fd2029f23 4252 /*!
mbed_official 324:406fd2029f23 4253 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
mbed_official 324:406fd2029f23 4254 *
mbed_official 324:406fd2029f23 4255 * Selects the polarity for the quadrature decoder phase A input.
mbed_official 324:406fd2029f23 4256 *
mbed_official 324:406fd2029f23 4257 * Values:
mbed_official 324:406fd2029f23 4258 * - 0 - Normal polarity. Phase A input signal is not inverted before
mbed_official 324:406fd2029f23 4259 * identifying the rising and falling edges of this signal.
mbed_official 324:406fd2029f23 4260 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
mbed_official 324:406fd2029f23 4261 * the rising and falling edges of this signal.
mbed_official 324:406fd2029f23 4262 */
mbed_official 324:406fd2029f23 4263 /*@{*/
mbed_official 324:406fd2029f23 4264 #define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */
mbed_official 324:406fd2029f23 4265 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
mbed_official 324:406fd2029f23 4266 #define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
mbed_official 324:406fd2029f23 4267
mbed_official 324:406fd2029f23 4268 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
mbed_official 324:406fd2029f23 4269 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
mbed_official 324:406fd2029f23 4270
mbed_official 324:406fd2029f23 4271 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
mbed_official 324:406fd2029f23 4272 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
mbed_official 324:406fd2029f23 4273
mbed_official 324:406fd2029f23 4274 /*! @brief Set the PHAPOL field to a new value. */
mbed_official 324:406fd2029f23 4275 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
mbed_official 324:406fd2029f23 4276 /*@}*/
mbed_official 324:406fd2029f23 4277
mbed_official 324:406fd2029f23 4278 /*!
mbed_official 324:406fd2029f23 4279 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
mbed_official 324:406fd2029f23 4280 *
mbed_official 324:406fd2029f23 4281 * Enables the filter for the quadrature decoder phase B input. The filter value
mbed_official 324:406fd2029f23 4282 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
mbed_official 324:406fd2029f23 4283 * filter is also disabled when CH1FVAL is zero.
mbed_official 324:406fd2029f23 4284 *
mbed_official 324:406fd2029f23 4285 * Values:
mbed_official 324:406fd2029f23 4286 * - 0 - Phase B input filter is disabled.
mbed_official 324:406fd2029f23 4287 * - 1 - Phase B input filter is enabled.
mbed_official 324:406fd2029f23 4288 */
mbed_official 324:406fd2029f23 4289 /*@{*/
mbed_official 324:406fd2029f23 4290 #define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
mbed_official 324:406fd2029f23 4291 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
mbed_official 324:406fd2029f23 4292 #define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
mbed_official 324:406fd2029f23 4293
mbed_official 324:406fd2029f23 4294 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
mbed_official 324:406fd2029f23 4295 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
mbed_official 324:406fd2029f23 4296
mbed_official 324:406fd2029f23 4297 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
mbed_official 324:406fd2029f23 4298 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
mbed_official 324:406fd2029f23 4299
mbed_official 324:406fd2029f23 4300 /*! @brief Set the PHBFLTREN field to a new value. */
mbed_official 324:406fd2029f23 4301 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
mbed_official 324:406fd2029f23 4302 /*@}*/
mbed_official 324:406fd2029f23 4303
mbed_official 324:406fd2029f23 4304 /*!
mbed_official 324:406fd2029f23 4305 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
mbed_official 324:406fd2029f23 4306 *
mbed_official 324:406fd2029f23 4307 * Enables the filter for the quadrature decoder phase A input. The filter value
mbed_official 324:406fd2029f23 4308 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
mbed_official 324:406fd2029f23 4309 * filter is also disabled when CH0FVAL is zero.
mbed_official 324:406fd2029f23 4310 *
mbed_official 324:406fd2029f23 4311 * Values:
mbed_official 324:406fd2029f23 4312 * - 0 - Phase A input filter is disabled.
mbed_official 324:406fd2029f23 4313 * - 1 - Phase A input filter is enabled.
mbed_official 324:406fd2029f23 4314 */
mbed_official 324:406fd2029f23 4315 /*@{*/
mbed_official 324:406fd2029f23 4316 #define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
mbed_official 324:406fd2029f23 4317 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
mbed_official 324:406fd2029f23 4318 #define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
mbed_official 324:406fd2029f23 4319
mbed_official 324:406fd2029f23 4320 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
mbed_official 324:406fd2029f23 4321 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
mbed_official 324:406fd2029f23 4322
mbed_official 324:406fd2029f23 4323 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
mbed_official 324:406fd2029f23 4324 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
mbed_official 324:406fd2029f23 4325
mbed_official 324:406fd2029f23 4326 /*! @brief Set the PHAFLTREN field to a new value. */
mbed_official 324:406fd2029f23 4327 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
mbed_official 324:406fd2029f23 4328 /*@}*/
mbed_official 324:406fd2029f23 4329
mbed_official 324:406fd2029f23 4330 /*******************************************************************************
mbed_official 324:406fd2029f23 4331 * HW_FTM_CONF - Configuration
mbed_official 324:406fd2029f23 4332 ******************************************************************************/
mbed_official 324:406fd2029f23 4333
mbed_official 324:406fd2029f23 4334 /*!
mbed_official 324:406fd2029f23 4335 * @brief HW_FTM_CONF - Configuration (RW)
mbed_official 324:406fd2029f23 4336 *
mbed_official 324:406fd2029f23 4337 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4338 *
mbed_official 324:406fd2029f23 4339 * This register selects the number of times that the FTM counter overflow
mbed_official 324:406fd2029f23 4340 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
mbed_official 324:406fd2029f23 4341 * of an external global time base, and the global time base signal generation.
mbed_official 324:406fd2029f23 4342 */
mbed_official 324:406fd2029f23 4343 typedef union _hw_ftm_conf
mbed_official 324:406fd2029f23 4344 {
mbed_official 324:406fd2029f23 4345 uint32_t U;
mbed_official 324:406fd2029f23 4346 struct _hw_ftm_conf_bitfields
mbed_official 324:406fd2029f23 4347 {
mbed_official 324:406fd2029f23 4348 uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */
mbed_official 324:406fd2029f23 4349 uint32_t RESERVED0 : 1; /*!< [5] */
mbed_official 324:406fd2029f23 4350 uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */
mbed_official 324:406fd2029f23 4351 uint32_t RESERVED1 : 1; /*!< [8] */
mbed_official 324:406fd2029f23 4352 uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */
mbed_official 324:406fd2029f23 4353 uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */
mbed_official 324:406fd2029f23 4354 uint32_t RESERVED2 : 21; /*!< [31:11] */
mbed_official 324:406fd2029f23 4355 } B;
mbed_official 324:406fd2029f23 4356 } hw_ftm_conf_t;
mbed_official 324:406fd2029f23 4357
mbed_official 324:406fd2029f23 4358 /*!
mbed_official 324:406fd2029f23 4359 * @name Constants and macros for entire FTM_CONF register
mbed_official 324:406fd2029f23 4360 */
mbed_official 324:406fd2029f23 4361 /*@{*/
mbed_official 324:406fd2029f23 4362 #define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
mbed_official 324:406fd2029f23 4363
mbed_official 324:406fd2029f23 4364 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
mbed_official 324:406fd2029f23 4365 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
mbed_official 324:406fd2029f23 4366 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
mbed_official 324:406fd2029f23 4367 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
mbed_official 324:406fd2029f23 4368 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 4369 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 4370 /*@}*/
mbed_official 324:406fd2029f23 4371
mbed_official 324:406fd2029f23 4372 /*
mbed_official 324:406fd2029f23 4373 * Constants & macros for individual FTM_CONF bitfields
mbed_official 324:406fd2029f23 4374 */
mbed_official 324:406fd2029f23 4375
mbed_official 324:406fd2029f23 4376 /*!
mbed_official 324:406fd2029f23 4377 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
mbed_official 324:406fd2029f23 4378 *
mbed_official 324:406fd2029f23 4379 * Selects the ratio between the number of counter overflows to the number of
mbed_official 324:406fd2029f23 4380 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
mbed_official 324:406fd2029f23 4381 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
mbed_official 324:406fd2029f23 4382 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
mbed_official 324:406fd2029f23 4383 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
mbed_official 324:406fd2029f23 4384 * first counter overflow but not for the next 3 overflows. This pattern continues
mbed_official 324:406fd2029f23 4385 * up to a maximum of 31.
mbed_official 324:406fd2029f23 4386 */
mbed_official 324:406fd2029f23 4387 /*@{*/
mbed_official 324:406fd2029f23 4388 #define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */
mbed_official 324:406fd2029f23 4389 #define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
mbed_official 324:406fd2029f23 4390 #define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
mbed_official 324:406fd2029f23 4391
mbed_official 324:406fd2029f23 4392 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
mbed_official 324:406fd2029f23 4393 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
mbed_official 324:406fd2029f23 4394
mbed_official 324:406fd2029f23 4395 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
mbed_official 324:406fd2029f23 4396 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
mbed_official 324:406fd2029f23 4397
mbed_official 324:406fd2029f23 4398 /*! @brief Set the NUMTOF field to a new value. */
mbed_official 324:406fd2029f23 4399 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
mbed_official 324:406fd2029f23 4400 /*@}*/
mbed_official 324:406fd2029f23 4401
mbed_official 324:406fd2029f23 4402 /*!
mbed_official 324:406fd2029f23 4403 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
mbed_official 324:406fd2029f23 4404 *
mbed_official 324:406fd2029f23 4405 * Selects the FTM behavior in BDM mode. See BDM mode.
mbed_official 324:406fd2029f23 4406 */
mbed_official 324:406fd2029f23 4407 /*@{*/
mbed_official 324:406fd2029f23 4408 #define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */
mbed_official 324:406fd2029f23 4409 #define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
mbed_official 324:406fd2029f23 4410 #define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
mbed_official 324:406fd2029f23 4411
mbed_official 324:406fd2029f23 4412 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
mbed_official 324:406fd2029f23 4413 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
mbed_official 324:406fd2029f23 4414
mbed_official 324:406fd2029f23 4415 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
mbed_official 324:406fd2029f23 4416 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
mbed_official 324:406fd2029f23 4417
mbed_official 324:406fd2029f23 4418 /*! @brief Set the BDMMODE field to a new value. */
mbed_official 324:406fd2029f23 4419 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
mbed_official 324:406fd2029f23 4420 /*@}*/
mbed_official 324:406fd2029f23 4421
mbed_official 324:406fd2029f23 4422 /*!
mbed_official 324:406fd2029f23 4423 * @name Register FTM_CONF, field GTBEEN[9] (RW)
mbed_official 324:406fd2029f23 4424 *
mbed_official 324:406fd2029f23 4425 * Configures the FTM to use an external global time base signal that is
mbed_official 324:406fd2029f23 4426 * generated by another FTM.
mbed_official 324:406fd2029f23 4427 *
mbed_official 324:406fd2029f23 4428 * Values:
mbed_official 324:406fd2029f23 4429 * - 0 - Use of an external global time base is disabled.
mbed_official 324:406fd2029f23 4430 * - 1 - Use of an external global time base is enabled.
mbed_official 324:406fd2029f23 4431 */
mbed_official 324:406fd2029f23 4432 /*@{*/
mbed_official 324:406fd2029f23 4433 #define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */
mbed_official 324:406fd2029f23 4434 #define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
mbed_official 324:406fd2029f23 4435 #define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
mbed_official 324:406fd2029f23 4436
mbed_official 324:406fd2029f23 4437 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
mbed_official 324:406fd2029f23 4438 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
mbed_official 324:406fd2029f23 4439
mbed_official 324:406fd2029f23 4440 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
mbed_official 324:406fd2029f23 4441 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
mbed_official 324:406fd2029f23 4442
mbed_official 324:406fd2029f23 4443 /*! @brief Set the GTBEEN field to a new value. */
mbed_official 324:406fd2029f23 4444 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
mbed_official 324:406fd2029f23 4445 /*@}*/
mbed_official 324:406fd2029f23 4446
mbed_official 324:406fd2029f23 4447 /*!
mbed_official 324:406fd2029f23 4448 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
mbed_official 324:406fd2029f23 4449 *
mbed_official 324:406fd2029f23 4450 * Enables the global time base signal generation to other FTMs.
mbed_official 324:406fd2029f23 4451 *
mbed_official 324:406fd2029f23 4452 * Values:
mbed_official 324:406fd2029f23 4453 * - 0 - A global time base signal generation is disabled.
mbed_official 324:406fd2029f23 4454 * - 1 - A global time base signal generation is enabled.
mbed_official 324:406fd2029f23 4455 */
mbed_official 324:406fd2029f23 4456 /*@{*/
mbed_official 324:406fd2029f23 4457 #define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */
mbed_official 324:406fd2029f23 4458 #define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
mbed_official 324:406fd2029f23 4459 #define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
mbed_official 324:406fd2029f23 4460
mbed_official 324:406fd2029f23 4461 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
mbed_official 324:406fd2029f23 4462 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
mbed_official 324:406fd2029f23 4463
mbed_official 324:406fd2029f23 4464 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
mbed_official 324:406fd2029f23 4465 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
mbed_official 324:406fd2029f23 4466
mbed_official 324:406fd2029f23 4467 /*! @brief Set the GTBEOUT field to a new value. */
mbed_official 324:406fd2029f23 4468 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
mbed_official 324:406fd2029f23 4469 /*@}*/
mbed_official 324:406fd2029f23 4470
mbed_official 324:406fd2029f23 4471 /*******************************************************************************
mbed_official 324:406fd2029f23 4472 * HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official 324:406fd2029f23 4473 ******************************************************************************/
mbed_official 324:406fd2029f23 4474
mbed_official 324:406fd2029f23 4475 /*!
mbed_official 324:406fd2029f23 4476 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
mbed_official 324:406fd2029f23 4477 *
mbed_official 324:406fd2029f23 4478 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4479 *
mbed_official 324:406fd2029f23 4480 * This register defines the fault inputs polarity.
mbed_official 324:406fd2029f23 4481 */
mbed_official 324:406fd2029f23 4482 typedef union _hw_ftm_fltpol
mbed_official 324:406fd2029f23 4483 {
mbed_official 324:406fd2029f23 4484 uint32_t U;
mbed_official 324:406fd2029f23 4485 struct _hw_ftm_fltpol_bitfields
mbed_official 324:406fd2029f23 4486 {
mbed_official 324:406fd2029f23 4487 uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */
mbed_official 324:406fd2029f23 4488 uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */
mbed_official 324:406fd2029f23 4489 uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */
mbed_official 324:406fd2029f23 4490 uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */
mbed_official 324:406fd2029f23 4491 uint32_t RESERVED0 : 28; /*!< [31:4] */
mbed_official 324:406fd2029f23 4492 } B;
mbed_official 324:406fd2029f23 4493 } hw_ftm_fltpol_t;
mbed_official 324:406fd2029f23 4494
mbed_official 324:406fd2029f23 4495 /*!
mbed_official 324:406fd2029f23 4496 * @name Constants and macros for entire FTM_FLTPOL register
mbed_official 324:406fd2029f23 4497 */
mbed_official 324:406fd2029f23 4498 /*@{*/
mbed_official 324:406fd2029f23 4499 #define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
mbed_official 324:406fd2029f23 4500
mbed_official 324:406fd2029f23 4501 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
mbed_official 324:406fd2029f23 4502 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
mbed_official 324:406fd2029f23 4503 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
mbed_official 324:406fd2029f23 4504 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
mbed_official 324:406fd2029f23 4505 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 4506 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 4507 /*@}*/
mbed_official 324:406fd2029f23 4508
mbed_official 324:406fd2029f23 4509 /*
mbed_official 324:406fd2029f23 4510 * Constants & macros for individual FTM_FLTPOL bitfields
mbed_official 324:406fd2029f23 4511 */
mbed_official 324:406fd2029f23 4512
mbed_official 324:406fd2029f23 4513 /*!
mbed_official 324:406fd2029f23 4514 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
mbed_official 324:406fd2029f23 4515 *
mbed_official 324:406fd2029f23 4516 * Defines the polarity of the fault input. This field is write protected. It
mbed_official 324:406fd2029f23 4517 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4518 *
mbed_official 324:406fd2029f23 4519 * Values:
mbed_official 324:406fd2029f23 4520 * - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official 324:406fd2029f23 4521 * indicates a fault.
mbed_official 324:406fd2029f23 4522 * - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official 324:406fd2029f23 4523 * indicates a fault.
mbed_official 324:406fd2029f23 4524 */
mbed_official 324:406fd2029f23 4525 /*@{*/
mbed_official 324:406fd2029f23 4526 #define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */
mbed_official 324:406fd2029f23 4527 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
mbed_official 324:406fd2029f23 4528 #define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
mbed_official 324:406fd2029f23 4529
mbed_official 324:406fd2029f23 4530 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
mbed_official 324:406fd2029f23 4531 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
mbed_official 324:406fd2029f23 4532
mbed_official 324:406fd2029f23 4533 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
mbed_official 324:406fd2029f23 4534 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
mbed_official 324:406fd2029f23 4535
mbed_official 324:406fd2029f23 4536 /*! @brief Set the FLT0POL field to a new value. */
mbed_official 324:406fd2029f23 4537 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
mbed_official 324:406fd2029f23 4538 /*@}*/
mbed_official 324:406fd2029f23 4539
mbed_official 324:406fd2029f23 4540 /*!
mbed_official 324:406fd2029f23 4541 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
mbed_official 324:406fd2029f23 4542 *
mbed_official 324:406fd2029f23 4543 * Defines the polarity of the fault input. This field is write protected. It
mbed_official 324:406fd2029f23 4544 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4545 *
mbed_official 324:406fd2029f23 4546 * Values:
mbed_official 324:406fd2029f23 4547 * - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official 324:406fd2029f23 4548 * indicates a fault.
mbed_official 324:406fd2029f23 4549 * - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official 324:406fd2029f23 4550 * indicates a fault.
mbed_official 324:406fd2029f23 4551 */
mbed_official 324:406fd2029f23 4552 /*@{*/
mbed_official 324:406fd2029f23 4553 #define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */
mbed_official 324:406fd2029f23 4554 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
mbed_official 324:406fd2029f23 4555 #define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
mbed_official 324:406fd2029f23 4556
mbed_official 324:406fd2029f23 4557 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
mbed_official 324:406fd2029f23 4558 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
mbed_official 324:406fd2029f23 4559
mbed_official 324:406fd2029f23 4560 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
mbed_official 324:406fd2029f23 4561 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
mbed_official 324:406fd2029f23 4562
mbed_official 324:406fd2029f23 4563 /*! @brief Set the FLT1POL field to a new value. */
mbed_official 324:406fd2029f23 4564 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
mbed_official 324:406fd2029f23 4565 /*@}*/
mbed_official 324:406fd2029f23 4566
mbed_official 324:406fd2029f23 4567 /*!
mbed_official 324:406fd2029f23 4568 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
mbed_official 324:406fd2029f23 4569 *
mbed_official 324:406fd2029f23 4570 * Defines the polarity of the fault input. This field is write protected. It
mbed_official 324:406fd2029f23 4571 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4572 *
mbed_official 324:406fd2029f23 4573 * Values:
mbed_official 324:406fd2029f23 4574 * - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official 324:406fd2029f23 4575 * indicates a fault.
mbed_official 324:406fd2029f23 4576 * - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official 324:406fd2029f23 4577 * indicates a fault.
mbed_official 324:406fd2029f23 4578 */
mbed_official 324:406fd2029f23 4579 /*@{*/
mbed_official 324:406fd2029f23 4580 #define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */
mbed_official 324:406fd2029f23 4581 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
mbed_official 324:406fd2029f23 4582 #define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
mbed_official 324:406fd2029f23 4583
mbed_official 324:406fd2029f23 4584 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
mbed_official 324:406fd2029f23 4585 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
mbed_official 324:406fd2029f23 4586
mbed_official 324:406fd2029f23 4587 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
mbed_official 324:406fd2029f23 4588 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
mbed_official 324:406fd2029f23 4589
mbed_official 324:406fd2029f23 4590 /*! @brief Set the FLT2POL field to a new value. */
mbed_official 324:406fd2029f23 4591 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
mbed_official 324:406fd2029f23 4592 /*@}*/
mbed_official 324:406fd2029f23 4593
mbed_official 324:406fd2029f23 4594 /*!
mbed_official 324:406fd2029f23 4595 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
mbed_official 324:406fd2029f23 4596 *
mbed_official 324:406fd2029f23 4597 * Defines the polarity of the fault input. This field is write protected. It
mbed_official 324:406fd2029f23 4598 * can be written only when MODE[WPDIS] = 1.
mbed_official 324:406fd2029f23 4599 *
mbed_official 324:406fd2029f23 4600 * Values:
mbed_official 324:406fd2029f23 4601 * - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official 324:406fd2029f23 4602 * indicates a fault.
mbed_official 324:406fd2029f23 4603 * - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official 324:406fd2029f23 4604 * indicates a fault.
mbed_official 324:406fd2029f23 4605 */
mbed_official 324:406fd2029f23 4606 /*@{*/
mbed_official 324:406fd2029f23 4607 #define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */
mbed_official 324:406fd2029f23 4608 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
mbed_official 324:406fd2029f23 4609 #define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
mbed_official 324:406fd2029f23 4610
mbed_official 324:406fd2029f23 4611 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
mbed_official 324:406fd2029f23 4612 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
mbed_official 324:406fd2029f23 4613
mbed_official 324:406fd2029f23 4614 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
mbed_official 324:406fd2029f23 4615 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
mbed_official 324:406fd2029f23 4616
mbed_official 324:406fd2029f23 4617 /*! @brief Set the FLT3POL field to a new value. */
mbed_official 324:406fd2029f23 4618 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
mbed_official 324:406fd2029f23 4619 /*@}*/
mbed_official 324:406fd2029f23 4620
mbed_official 324:406fd2029f23 4621 /*******************************************************************************
mbed_official 324:406fd2029f23 4622 * HW_FTM_SYNCONF - Synchronization Configuration
mbed_official 324:406fd2029f23 4623 ******************************************************************************/
mbed_official 324:406fd2029f23 4624
mbed_official 324:406fd2029f23 4625 /*!
mbed_official 324:406fd2029f23 4626 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
mbed_official 324:406fd2029f23 4627 *
mbed_official 324:406fd2029f23 4628 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4629 *
mbed_official 324:406fd2029f23 4630 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
mbed_official 324:406fd2029f23 4631 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
mbed_official 324:406fd2029f23 4632 * 0, 1, 2, when the hardware trigger j is detected.
mbed_official 324:406fd2029f23 4633 */
mbed_official 324:406fd2029f23 4634 typedef union _hw_ftm_synconf
mbed_official 324:406fd2029f23 4635 {
mbed_official 324:406fd2029f23 4636 uint32_t U;
mbed_official 324:406fd2029f23 4637 struct _hw_ftm_synconf_bitfields
mbed_official 324:406fd2029f23 4638 {
mbed_official 324:406fd2029f23 4639 uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */
mbed_official 324:406fd2029f23 4640 uint32_t RESERVED0 : 1; /*!< [1] */
mbed_official 324:406fd2029f23 4641 uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */
mbed_official 324:406fd2029f23 4642 uint32_t RESERVED1 : 1; /*!< [3] */
mbed_official 324:406fd2029f23 4643 uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */
mbed_official 324:406fd2029f23 4644 uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */
mbed_official 324:406fd2029f23 4645 uint32_t RESERVED2 : 1; /*!< [6] */
mbed_official 324:406fd2029f23 4646 uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */
mbed_official 324:406fd2029f23 4647 uint32_t SWRSTCNT : 1; /*!< [8] */
mbed_official 324:406fd2029f23 4648 uint32_t SWWRBUF : 1; /*!< [9] */
mbed_official 324:406fd2029f23 4649 uint32_t SWOM : 1; /*!< [10] */
mbed_official 324:406fd2029f23 4650 uint32_t SWINVC : 1; /*!< [11] */
mbed_official 324:406fd2029f23 4651 uint32_t SWSOC : 1; /*!< [12] */
mbed_official 324:406fd2029f23 4652 uint32_t RESERVED3 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 4653 uint32_t HWRSTCNT : 1; /*!< [16] */
mbed_official 324:406fd2029f23 4654 uint32_t HWWRBUF : 1; /*!< [17] */
mbed_official 324:406fd2029f23 4655 uint32_t HWOM : 1; /*!< [18] */
mbed_official 324:406fd2029f23 4656 uint32_t HWINVC : 1; /*!< [19] */
mbed_official 324:406fd2029f23 4657 uint32_t HWSOC : 1; /*!< [20] */
mbed_official 324:406fd2029f23 4658 uint32_t RESERVED4 : 11; /*!< [31:21] */
mbed_official 324:406fd2029f23 4659 } B;
mbed_official 324:406fd2029f23 4660 } hw_ftm_synconf_t;
mbed_official 324:406fd2029f23 4661
mbed_official 324:406fd2029f23 4662 /*!
mbed_official 324:406fd2029f23 4663 * @name Constants and macros for entire FTM_SYNCONF register
mbed_official 324:406fd2029f23 4664 */
mbed_official 324:406fd2029f23 4665 /*@{*/
mbed_official 324:406fd2029f23 4666 #define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
mbed_official 324:406fd2029f23 4667
mbed_official 324:406fd2029f23 4668 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
mbed_official 324:406fd2029f23 4669 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
mbed_official 324:406fd2029f23 4670 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
mbed_official 324:406fd2029f23 4671 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
mbed_official 324:406fd2029f23 4672 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 4673 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 4674 /*@}*/
mbed_official 324:406fd2029f23 4675
mbed_official 324:406fd2029f23 4676 /*
mbed_official 324:406fd2029f23 4677 * Constants & macros for individual FTM_SYNCONF bitfields
mbed_official 324:406fd2029f23 4678 */
mbed_official 324:406fd2029f23 4679
mbed_official 324:406fd2029f23 4680 /*!
mbed_official 324:406fd2029f23 4681 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
mbed_official 324:406fd2029f23 4682 *
mbed_official 324:406fd2029f23 4683 * Values:
mbed_official 324:406fd2029f23 4684 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
mbed_official 324:406fd2029f23 4685 * j = 0, 1,2.
mbed_official 324:406fd2029f23 4686 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
mbed_official 324:406fd2029f23 4687 * detected, where j = 0, 1,2.
mbed_official 324:406fd2029f23 4688 */
mbed_official 324:406fd2029f23 4689 /*@{*/
mbed_official 324:406fd2029f23 4690 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
mbed_official 324:406fd2029f23 4691 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
mbed_official 324:406fd2029f23 4692 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
mbed_official 324:406fd2029f23 4693
mbed_official 324:406fd2029f23 4694 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
mbed_official 324:406fd2029f23 4695 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
mbed_official 324:406fd2029f23 4696
mbed_official 324:406fd2029f23 4697 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
mbed_official 324:406fd2029f23 4698 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
mbed_official 324:406fd2029f23 4699
mbed_official 324:406fd2029f23 4700 /*! @brief Set the HWTRIGMODE field to a new value. */
mbed_official 324:406fd2029f23 4701 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
mbed_official 324:406fd2029f23 4702 /*@}*/
mbed_official 324:406fd2029f23 4703
mbed_official 324:406fd2029f23 4704 /*!
mbed_official 324:406fd2029f23 4705 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
mbed_official 324:406fd2029f23 4706 *
mbed_official 324:406fd2029f23 4707 * Values:
mbed_official 324:406fd2029f23 4708 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
mbed_official 324:406fd2029f23 4709 * system clock.
mbed_official 324:406fd2029f23 4710 * - 1 - CNTIN register is updated with its buffer value by the PWM
mbed_official 324:406fd2029f23 4711 * synchronization.
mbed_official 324:406fd2029f23 4712 */
mbed_official 324:406fd2029f23 4713 /*@{*/
mbed_official 324:406fd2029f23 4714 #define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */
mbed_official 324:406fd2029f23 4715 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
mbed_official 324:406fd2029f23 4716 #define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
mbed_official 324:406fd2029f23 4717
mbed_official 324:406fd2029f23 4718 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
mbed_official 324:406fd2029f23 4719 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
mbed_official 324:406fd2029f23 4720
mbed_official 324:406fd2029f23 4721 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
mbed_official 324:406fd2029f23 4722 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
mbed_official 324:406fd2029f23 4723
mbed_official 324:406fd2029f23 4724 /*! @brief Set the CNTINC field to a new value. */
mbed_official 324:406fd2029f23 4725 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
mbed_official 324:406fd2029f23 4726 /*@}*/
mbed_official 324:406fd2029f23 4727
mbed_official 324:406fd2029f23 4728 /*!
mbed_official 324:406fd2029f23 4729 * @name Register FTM_SYNCONF, field INVC[4] (RW)
mbed_official 324:406fd2029f23 4730 *
mbed_official 324:406fd2029f23 4731 * Values:
mbed_official 324:406fd2029f23 4732 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
mbed_official 324:406fd2029f23 4733 * of system clock.
mbed_official 324:406fd2029f23 4734 * - 1 - INVCTRL register is updated with its buffer value by the PWM
mbed_official 324:406fd2029f23 4735 * synchronization.
mbed_official 324:406fd2029f23 4736 */
mbed_official 324:406fd2029f23 4737 /*@{*/
mbed_official 324:406fd2029f23 4738 #define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */
mbed_official 324:406fd2029f23 4739 #define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
mbed_official 324:406fd2029f23 4740 #define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
mbed_official 324:406fd2029f23 4741
mbed_official 324:406fd2029f23 4742 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
mbed_official 324:406fd2029f23 4743 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
mbed_official 324:406fd2029f23 4744
mbed_official 324:406fd2029f23 4745 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
mbed_official 324:406fd2029f23 4746 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
mbed_official 324:406fd2029f23 4747
mbed_official 324:406fd2029f23 4748 /*! @brief Set the INVC field to a new value. */
mbed_official 324:406fd2029f23 4749 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
mbed_official 324:406fd2029f23 4750 /*@}*/
mbed_official 324:406fd2029f23 4751
mbed_official 324:406fd2029f23 4752 /*!
mbed_official 324:406fd2029f23 4753 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
mbed_official 324:406fd2029f23 4754 *
mbed_official 324:406fd2029f23 4755 * Values:
mbed_official 324:406fd2029f23 4756 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
mbed_official 324:406fd2029f23 4757 * of system clock.
mbed_official 324:406fd2029f23 4758 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
mbed_official 324:406fd2029f23 4759 * synchronization.
mbed_official 324:406fd2029f23 4760 */
mbed_official 324:406fd2029f23 4761 /*@{*/
mbed_official 324:406fd2029f23 4762 #define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */
mbed_official 324:406fd2029f23 4763 #define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
mbed_official 324:406fd2029f23 4764 #define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
mbed_official 324:406fd2029f23 4765
mbed_official 324:406fd2029f23 4766 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
mbed_official 324:406fd2029f23 4767 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
mbed_official 324:406fd2029f23 4768
mbed_official 324:406fd2029f23 4769 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
mbed_official 324:406fd2029f23 4770 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
mbed_official 324:406fd2029f23 4771
mbed_official 324:406fd2029f23 4772 /*! @brief Set the SWOC field to a new value. */
mbed_official 324:406fd2029f23 4773 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
mbed_official 324:406fd2029f23 4774 /*@}*/
mbed_official 324:406fd2029f23 4775
mbed_official 324:406fd2029f23 4776 /*!
mbed_official 324:406fd2029f23 4777 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
mbed_official 324:406fd2029f23 4778 *
mbed_official 324:406fd2029f23 4779 * Selects the PWM Synchronization mode.
mbed_official 324:406fd2029f23 4780 *
mbed_official 324:406fd2029f23 4781 * Values:
mbed_official 324:406fd2029f23 4782 * - 0 - Legacy PWM synchronization is selected.
mbed_official 324:406fd2029f23 4783 * - 1 - Enhanced PWM synchronization is selected.
mbed_official 324:406fd2029f23 4784 */
mbed_official 324:406fd2029f23 4785 /*@{*/
mbed_official 324:406fd2029f23 4786 #define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
mbed_official 324:406fd2029f23 4787 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
mbed_official 324:406fd2029f23 4788 #define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
mbed_official 324:406fd2029f23 4789
mbed_official 324:406fd2029f23 4790 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
mbed_official 324:406fd2029f23 4791 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
mbed_official 324:406fd2029f23 4792
mbed_official 324:406fd2029f23 4793 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
mbed_official 324:406fd2029f23 4794 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
mbed_official 324:406fd2029f23 4795
mbed_official 324:406fd2029f23 4796 /*! @brief Set the SYNCMODE field to a new value. */
mbed_official 324:406fd2029f23 4797 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
mbed_official 324:406fd2029f23 4798 /*@}*/
mbed_official 324:406fd2029f23 4799
mbed_official 324:406fd2029f23 4800 /*!
mbed_official 324:406fd2029f23 4801 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
mbed_official 324:406fd2029f23 4802 *
mbed_official 324:406fd2029f23 4803 * FTM counter synchronization is activated by the software trigger.
mbed_official 324:406fd2029f23 4804 *
mbed_official 324:406fd2029f23 4805 * Values:
mbed_official 324:406fd2029f23 4806 * - 0 - The software trigger does not activate the FTM counter synchronization.
mbed_official 324:406fd2029f23 4807 * - 1 - The software trigger activates the FTM counter synchronization.
mbed_official 324:406fd2029f23 4808 */
mbed_official 324:406fd2029f23 4809 /*@{*/
mbed_official 324:406fd2029f23 4810 #define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
mbed_official 324:406fd2029f23 4811 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
mbed_official 324:406fd2029f23 4812 #define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
mbed_official 324:406fd2029f23 4813
mbed_official 324:406fd2029f23 4814 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
mbed_official 324:406fd2029f23 4815 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
mbed_official 324:406fd2029f23 4816
mbed_official 324:406fd2029f23 4817 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
mbed_official 324:406fd2029f23 4818 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
mbed_official 324:406fd2029f23 4819
mbed_official 324:406fd2029f23 4820 /*! @brief Set the SWRSTCNT field to a new value. */
mbed_official 324:406fd2029f23 4821 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
mbed_official 324:406fd2029f23 4822 /*@}*/
mbed_official 324:406fd2029f23 4823
mbed_official 324:406fd2029f23 4824 /*!
mbed_official 324:406fd2029f23 4825 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
mbed_official 324:406fd2029f23 4826 *
mbed_official 324:406fd2029f23 4827 * MOD, CNTIN, and CV registers synchronization is activated by the software
mbed_official 324:406fd2029f23 4828 * trigger.
mbed_official 324:406fd2029f23 4829 *
mbed_official 324:406fd2029f23 4830 * Values:
mbed_official 324:406fd2029f23 4831 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
mbed_official 324:406fd2029f23 4832 * synchronization.
mbed_official 324:406fd2029f23 4833 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
mbed_official 324:406fd2029f23 4834 * synchronization.
mbed_official 324:406fd2029f23 4835 */
mbed_official 324:406fd2029f23 4836 /*@{*/
mbed_official 324:406fd2029f23 4837 #define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
mbed_official 324:406fd2029f23 4838 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
mbed_official 324:406fd2029f23 4839 #define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
mbed_official 324:406fd2029f23 4840
mbed_official 324:406fd2029f23 4841 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
mbed_official 324:406fd2029f23 4842 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
mbed_official 324:406fd2029f23 4843
mbed_official 324:406fd2029f23 4844 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
mbed_official 324:406fd2029f23 4845 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
mbed_official 324:406fd2029f23 4846
mbed_official 324:406fd2029f23 4847 /*! @brief Set the SWWRBUF field to a new value. */
mbed_official 324:406fd2029f23 4848 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
mbed_official 324:406fd2029f23 4849 /*@}*/
mbed_official 324:406fd2029f23 4850
mbed_official 324:406fd2029f23 4851 /*!
mbed_official 324:406fd2029f23 4852 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
mbed_official 324:406fd2029f23 4853 *
mbed_official 324:406fd2029f23 4854 * Output mask synchronization is activated by the software trigger.
mbed_official 324:406fd2029f23 4855 *
mbed_official 324:406fd2029f23 4856 * Values:
mbed_official 324:406fd2029f23 4857 * - 0 - The software trigger does not activate the OUTMASK register
mbed_official 324:406fd2029f23 4858 * synchronization.
mbed_official 324:406fd2029f23 4859 * - 1 - The software trigger activates the OUTMASK register synchronization.
mbed_official 324:406fd2029f23 4860 */
mbed_official 324:406fd2029f23 4861 /*@{*/
mbed_official 324:406fd2029f23 4862 #define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */
mbed_official 324:406fd2029f23 4863 #define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
mbed_official 324:406fd2029f23 4864 #define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
mbed_official 324:406fd2029f23 4865
mbed_official 324:406fd2029f23 4866 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
mbed_official 324:406fd2029f23 4867 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
mbed_official 324:406fd2029f23 4868
mbed_official 324:406fd2029f23 4869 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
mbed_official 324:406fd2029f23 4870 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
mbed_official 324:406fd2029f23 4871
mbed_official 324:406fd2029f23 4872 /*! @brief Set the SWOM field to a new value. */
mbed_official 324:406fd2029f23 4873 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
mbed_official 324:406fd2029f23 4874 /*@}*/
mbed_official 324:406fd2029f23 4875
mbed_official 324:406fd2029f23 4876 /*!
mbed_official 324:406fd2029f23 4877 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
mbed_official 324:406fd2029f23 4878 *
mbed_official 324:406fd2029f23 4879 * Inverting control synchronization is activated by the software trigger.
mbed_official 324:406fd2029f23 4880 *
mbed_official 324:406fd2029f23 4881 * Values:
mbed_official 324:406fd2029f23 4882 * - 0 - The software trigger does not activate the INVCTRL register
mbed_official 324:406fd2029f23 4883 * synchronization.
mbed_official 324:406fd2029f23 4884 * - 1 - The software trigger activates the INVCTRL register synchronization.
mbed_official 324:406fd2029f23 4885 */
mbed_official 324:406fd2029f23 4886 /*@{*/
mbed_official 324:406fd2029f23 4887 #define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */
mbed_official 324:406fd2029f23 4888 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
mbed_official 324:406fd2029f23 4889 #define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
mbed_official 324:406fd2029f23 4890
mbed_official 324:406fd2029f23 4891 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
mbed_official 324:406fd2029f23 4892 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
mbed_official 324:406fd2029f23 4893
mbed_official 324:406fd2029f23 4894 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
mbed_official 324:406fd2029f23 4895 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
mbed_official 324:406fd2029f23 4896
mbed_official 324:406fd2029f23 4897 /*! @brief Set the SWINVC field to a new value. */
mbed_official 324:406fd2029f23 4898 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
mbed_official 324:406fd2029f23 4899 /*@}*/
mbed_official 324:406fd2029f23 4900
mbed_official 324:406fd2029f23 4901 /*!
mbed_official 324:406fd2029f23 4902 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
mbed_official 324:406fd2029f23 4903 *
mbed_official 324:406fd2029f23 4904 * Software output control synchronization is activated by the software trigger.
mbed_official 324:406fd2029f23 4905 *
mbed_official 324:406fd2029f23 4906 * Values:
mbed_official 324:406fd2029f23 4907 * - 0 - The software trigger does not activate the SWOCTRL register
mbed_official 324:406fd2029f23 4908 * synchronization.
mbed_official 324:406fd2029f23 4909 * - 1 - The software trigger activates the SWOCTRL register synchronization.
mbed_official 324:406fd2029f23 4910 */
mbed_official 324:406fd2029f23 4911 /*@{*/
mbed_official 324:406fd2029f23 4912 #define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */
mbed_official 324:406fd2029f23 4913 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
mbed_official 324:406fd2029f23 4914 #define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
mbed_official 324:406fd2029f23 4915
mbed_official 324:406fd2029f23 4916 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
mbed_official 324:406fd2029f23 4917 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
mbed_official 324:406fd2029f23 4918
mbed_official 324:406fd2029f23 4919 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
mbed_official 324:406fd2029f23 4920 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
mbed_official 324:406fd2029f23 4921
mbed_official 324:406fd2029f23 4922 /*! @brief Set the SWSOC field to a new value. */
mbed_official 324:406fd2029f23 4923 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
mbed_official 324:406fd2029f23 4924 /*@}*/
mbed_official 324:406fd2029f23 4925
mbed_official 324:406fd2029f23 4926 /*!
mbed_official 324:406fd2029f23 4927 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
mbed_official 324:406fd2029f23 4928 *
mbed_official 324:406fd2029f23 4929 * FTM counter synchronization is activated by a hardware trigger.
mbed_official 324:406fd2029f23 4930 *
mbed_official 324:406fd2029f23 4931 * Values:
mbed_official 324:406fd2029f23 4932 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
mbed_official 324:406fd2029f23 4933 * - 1 - A hardware trigger activates the FTM counter synchronization.
mbed_official 324:406fd2029f23 4934 */
mbed_official 324:406fd2029f23 4935 /*@{*/
mbed_official 324:406fd2029f23 4936 #define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
mbed_official 324:406fd2029f23 4937 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
mbed_official 324:406fd2029f23 4938 #define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
mbed_official 324:406fd2029f23 4939
mbed_official 324:406fd2029f23 4940 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
mbed_official 324:406fd2029f23 4941 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
mbed_official 324:406fd2029f23 4942
mbed_official 324:406fd2029f23 4943 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
mbed_official 324:406fd2029f23 4944 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
mbed_official 324:406fd2029f23 4945
mbed_official 324:406fd2029f23 4946 /*! @brief Set the HWRSTCNT field to a new value. */
mbed_official 324:406fd2029f23 4947 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
mbed_official 324:406fd2029f23 4948 /*@}*/
mbed_official 324:406fd2029f23 4949
mbed_official 324:406fd2029f23 4950 /*!
mbed_official 324:406fd2029f23 4951 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
mbed_official 324:406fd2029f23 4952 *
mbed_official 324:406fd2029f23 4953 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
mbed_official 324:406fd2029f23 4954 * trigger.
mbed_official 324:406fd2029f23 4955 *
mbed_official 324:406fd2029f23 4956 * Values:
mbed_official 324:406fd2029f23 4957 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
mbed_official 324:406fd2029f23 4958 * synchronization.
mbed_official 324:406fd2029f23 4959 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
mbed_official 324:406fd2029f23 4960 * synchronization.
mbed_official 324:406fd2029f23 4961 */
mbed_official 324:406fd2029f23 4962 /*@{*/
mbed_official 324:406fd2029f23 4963 #define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
mbed_official 324:406fd2029f23 4964 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
mbed_official 324:406fd2029f23 4965 #define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
mbed_official 324:406fd2029f23 4966
mbed_official 324:406fd2029f23 4967 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
mbed_official 324:406fd2029f23 4968 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
mbed_official 324:406fd2029f23 4969
mbed_official 324:406fd2029f23 4970 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
mbed_official 324:406fd2029f23 4971 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
mbed_official 324:406fd2029f23 4972
mbed_official 324:406fd2029f23 4973 /*! @brief Set the HWWRBUF field to a new value. */
mbed_official 324:406fd2029f23 4974 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
mbed_official 324:406fd2029f23 4975 /*@}*/
mbed_official 324:406fd2029f23 4976
mbed_official 324:406fd2029f23 4977 /*!
mbed_official 324:406fd2029f23 4978 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
mbed_official 324:406fd2029f23 4979 *
mbed_official 324:406fd2029f23 4980 * Output mask synchronization is activated by a hardware trigger.
mbed_official 324:406fd2029f23 4981 *
mbed_official 324:406fd2029f23 4982 * Values:
mbed_official 324:406fd2029f23 4983 * - 0 - A hardware trigger does not activate the OUTMASK register
mbed_official 324:406fd2029f23 4984 * synchronization.
mbed_official 324:406fd2029f23 4985 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
mbed_official 324:406fd2029f23 4986 */
mbed_official 324:406fd2029f23 4987 /*@{*/
mbed_official 324:406fd2029f23 4988 #define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */
mbed_official 324:406fd2029f23 4989 #define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
mbed_official 324:406fd2029f23 4990 #define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
mbed_official 324:406fd2029f23 4991
mbed_official 324:406fd2029f23 4992 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
mbed_official 324:406fd2029f23 4993 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
mbed_official 324:406fd2029f23 4994
mbed_official 324:406fd2029f23 4995 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
mbed_official 324:406fd2029f23 4996 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
mbed_official 324:406fd2029f23 4997
mbed_official 324:406fd2029f23 4998 /*! @brief Set the HWOM field to a new value. */
mbed_official 324:406fd2029f23 4999 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
mbed_official 324:406fd2029f23 5000 /*@}*/
mbed_official 324:406fd2029f23 5001
mbed_official 324:406fd2029f23 5002 /*!
mbed_official 324:406fd2029f23 5003 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
mbed_official 324:406fd2029f23 5004 *
mbed_official 324:406fd2029f23 5005 * Inverting control synchronization is activated by a hardware trigger.
mbed_official 324:406fd2029f23 5006 *
mbed_official 324:406fd2029f23 5007 * Values:
mbed_official 324:406fd2029f23 5008 * - 0 - A hardware trigger does not activate the INVCTRL register
mbed_official 324:406fd2029f23 5009 * synchronization.
mbed_official 324:406fd2029f23 5010 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
mbed_official 324:406fd2029f23 5011 */
mbed_official 324:406fd2029f23 5012 /*@{*/
mbed_official 324:406fd2029f23 5013 #define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */
mbed_official 324:406fd2029f23 5014 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
mbed_official 324:406fd2029f23 5015 #define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
mbed_official 324:406fd2029f23 5016
mbed_official 324:406fd2029f23 5017 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
mbed_official 324:406fd2029f23 5018 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
mbed_official 324:406fd2029f23 5019
mbed_official 324:406fd2029f23 5020 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
mbed_official 324:406fd2029f23 5021 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
mbed_official 324:406fd2029f23 5022
mbed_official 324:406fd2029f23 5023 /*! @brief Set the HWINVC field to a new value. */
mbed_official 324:406fd2029f23 5024 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
mbed_official 324:406fd2029f23 5025 /*@}*/
mbed_official 324:406fd2029f23 5026
mbed_official 324:406fd2029f23 5027 /*!
mbed_official 324:406fd2029f23 5028 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
mbed_official 324:406fd2029f23 5029 *
mbed_official 324:406fd2029f23 5030 * Software output control synchronization is activated by a hardware trigger.
mbed_official 324:406fd2029f23 5031 *
mbed_official 324:406fd2029f23 5032 * Values:
mbed_official 324:406fd2029f23 5033 * - 0 - A hardware trigger does not activate the SWOCTRL register
mbed_official 324:406fd2029f23 5034 * synchronization.
mbed_official 324:406fd2029f23 5035 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
mbed_official 324:406fd2029f23 5036 */
mbed_official 324:406fd2029f23 5037 /*@{*/
mbed_official 324:406fd2029f23 5038 #define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */
mbed_official 324:406fd2029f23 5039 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
mbed_official 324:406fd2029f23 5040 #define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
mbed_official 324:406fd2029f23 5041
mbed_official 324:406fd2029f23 5042 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
mbed_official 324:406fd2029f23 5043 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
mbed_official 324:406fd2029f23 5044
mbed_official 324:406fd2029f23 5045 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
mbed_official 324:406fd2029f23 5046 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
mbed_official 324:406fd2029f23 5047
mbed_official 324:406fd2029f23 5048 /*! @brief Set the HWSOC field to a new value. */
mbed_official 324:406fd2029f23 5049 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
mbed_official 324:406fd2029f23 5050 /*@}*/
mbed_official 324:406fd2029f23 5051
mbed_official 324:406fd2029f23 5052 /*******************************************************************************
mbed_official 324:406fd2029f23 5053 * HW_FTM_INVCTRL - FTM Inverting Control
mbed_official 324:406fd2029f23 5054 ******************************************************************************/
mbed_official 324:406fd2029f23 5055
mbed_official 324:406fd2029f23 5056 /*!
mbed_official 324:406fd2029f23 5057 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
mbed_official 324:406fd2029f23 5058 *
mbed_official 324:406fd2029f23 5059 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 5060 *
mbed_official 324:406fd2029f23 5061 * This register controls when the channel (n) output becomes the channel (n+1)
mbed_official 324:406fd2029f23 5062 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
mbed_official 324:406fd2029f23 5063 * bit enables the inverting operation for the corresponding pair channels m. This
mbed_official 324:406fd2029f23 5064 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
mbed_official 324:406fd2029f23 5065 * register synchronization.
mbed_official 324:406fd2029f23 5066 */
mbed_official 324:406fd2029f23 5067 typedef union _hw_ftm_invctrl
mbed_official 324:406fd2029f23 5068 {
mbed_official 324:406fd2029f23 5069 uint32_t U;
mbed_official 324:406fd2029f23 5070 struct _hw_ftm_invctrl_bitfields
mbed_official 324:406fd2029f23 5071 {
mbed_official 324:406fd2029f23 5072 uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */
mbed_official 324:406fd2029f23 5073 uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */
mbed_official 324:406fd2029f23 5074 uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */
mbed_official 324:406fd2029f23 5075 uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */
mbed_official 324:406fd2029f23 5076 uint32_t RESERVED0 : 28; /*!< [31:4] */
mbed_official 324:406fd2029f23 5077 } B;
mbed_official 324:406fd2029f23 5078 } hw_ftm_invctrl_t;
mbed_official 324:406fd2029f23 5079
mbed_official 324:406fd2029f23 5080 /*!
mbed_official 324:406fd2029f23 5081 * @name Constants and macros for entire FTM_INVCTRL register
mbed_official 324:406fd2029f23 5082 */
mbed_official 324:406fd2029f23 5083 /*@{*/
mbed_official 324:406fd2029f23 5084 #define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
mbed_official 324:406fd2029f23 5085
mbed_official 324:406fd2029f23 5086 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
mbed_official 324:406fd2029f23 5087 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
mbed_official 324:406fd2029f23 5088 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
mbed_official 324:406fd2029f23 5089 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 5090 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 5091 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 5092 /*@}*/
mbed_official 324:406fd2029f23 5093
mbed_official 324:406fd2029f23 5094 /*
mbed_official 324:406fd2029f23 5095 * Constants & macros for individual FTM_INVCTRL bitfields
mbed_official 324:406fd2029f23 5096 */
mbed_official 324:406fd2029f23 5097
mbed_official 324:406fd2029f23 5098 /*!
mbed_official 324:406fd2029f23 5099 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
mbed_official 324:406fd2029f23 5100 *
mbed_official 324:406fd2029f23 5101 * Values:
mbed_official 324:406fd2029f23 5102 * - 0 - Inverting is disabled.
mbed_official 324:406fd2029f23 5103 * - 1 - Inverting is enabled.
mbed_official 324:406fd2029f23 5104 */
mbed_official 324:406fd2029f23 5105 /*@{*/
mbed_official 324:406fd2029f23 5106 #define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */
mbed_official 324:406fd2029f23 5107 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
mbed_official 324:406fd2029f23 5108 #define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
mbed_official 324:406fd2029f23 5109
mbed_official 324:406fd2029f23 5110 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
mbed_official 324:406fd2029f23 5111 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
mbed_official 324:406fd2029f23 5112
mbed_official 324:406fd2029f23 5113 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
mbed_official 324:406fd2029f23 5114 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
mbed_official 324:406fd2029f23 5115
mbed_official 324:406fd2029f23 5116 /*! @brief Set the INV0EN field to a new value. */
mbed_official 324:406fd2029f23 5117 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
mbed_official 324:406fd2029f23 5118 /*@}*/
mbed_official 324:406fd2029f23 5119
mbed_official 324:406fd2029f23 5120 /*!
mbed_official 324:406fd2029f23 5121 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
mbed_official 324:406fd2029f23 5122 *
mbed_official 324:406fd2029f23 5123 * Values:
mbed_official 324:406fd2029f23 5124 * - 0 - Inverting is disabled.
mbed_official 324:406fd2029f23 5125 * - 1 - Inverting is enabled.
mbed_official 324:406fd2029f23 5126 */
mbed_official 324:406fd2029f23 5127 /*@{*/
mbed_official 324:406fd2029f23 5128 #define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */
mbed_official 324:406fd2029f23 5129 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
mbed_official 324:406fd2029f23 5130 #define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
mbed_official 324:406fd2029f23 5131
mbed_official 324:406fd2029f23 5132 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
mbed_official 324:406fd2029f23 5133 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
mbed_official 324:406fd2029f23 5134
mbed_official 324:406fd2029f23 5135 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
mbed_official 324:406fd2029f23 5136 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
mbed_official 324:406fd2029f23 5137
mbed_official 324:406fd2029f23 5138 /*! @brief Set the INV1EN field to a new value. */
mbed_official 324:406fd2029f23 5139 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
mbed_official 324:406fd2029f23 5140 /*@}*/
mbed_official 324:406fd2029f23 5141
mbed_official 324:406fd2029f23 5142 /*!
mbed_official 324:406fd2029f23 5143 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
mbed_official 324:406fd2029f23 5144 *
mbed_official 324:406fd2029f23 5145 * Values:
mbed_official 324:406fd2029f23 5146 * - 0 - Inverting is disabled.
mbed_official 324:406fd2029f23 5147 * - 1 - Inverting is enabled.
mbed_official 324:406fd2029f23 5148 */
mbed_official 324:406fd2029f23 5149 /*@{*/
mbed_official 324:406fd2029f23 5150 #define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */
mbed_official 324:406fd2029f23 5151 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
mbed_official 324:406fd2029f23 5152 #define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
mbed_official 324:406fd2029f23 5153
mbed_official 324:406fd2029f23 5154 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
mbed_official 324:406fd2029f23 5155 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
mbed_official 324:406fd2029f23 5156
mbed_official 324:406fd2029f23 5157 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
mbed_official 324:406fd2029f23 5158 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
mbed_official 324:406fd2029f23 5159
mbed_official 324:406fd2029f23 5160 /*! @brief Set the INV2EN field to a new value. */
mbed_official 324:406fd2029f23 5161 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
mbed_official 324:406fd2029f23 5162 /*@}*/
mbed_official 324:406fd2029f23 5163
mbed_official 324:406fd2029f23 5164 /*!
mbed_official 324:406fd2029f23 5165 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
mbed_official 324:406fd2029f23 5166 *
mbed_official 324:406fd2029f23 5167 * Values:
mbed_official 324:406fd2029f23 5168 * - 0 - Inverting is disabled.
mbed_official 324:406fd2029f23 5169 * - 1 - Inverting is enabled.
mbed_official 324:406fd2029f23 5170 */
mbed_official 324:406fd2029f23 5171 /*@{*/
mbed_official 324:406fd2029f23 5172 #define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */
mbed_official 324:406fd2029f23 5173 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
mbed_official 324:406fd2029f23 5174 #define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
mbed_official 324:406fd2029f23 5175
mbed_official 324:406fd2029f23 5176 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
mbed_official 324:406fd2029f23 5177 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
mbed_official 324:406fd2029f23 5178
mbed_official 324:406fd2029f23 5179 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
mbed_official 324:406fd2029f23 5180 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
mbed_official 324:406fd2029f23 5181
mbed_official 324:406fd2029f23 5182 /*! @brief Set the INV3EN field to a new value. */
mbed_official 324:406fd2029f23 5183 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
mbed_official 324:406fd2029f23 5184 /*@}*/
mbed_official 324:406fd2029f23 5185
mbed_official 324:406fd2029f23 5186 /*******************************************************************************
mbed_official 324:406fd2029f23 5187 * HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official 324:406fd2029f23 5188 ******************************************************************************/
mbed_official 324:406fd2029f23 5189
mbed_official 324:406fd2029f23 5190 /*!
mbed_official 324:406fd2029f23 5191 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
mbed_official 324:406fd2029f23 5192 *
mbed_official 324:406fd2029f23 5193 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 5194 *
mbed_official 324:406fd2029f23 5195 * This register enables software control of channel (n) output and defines the
mbed_official 324:406fd2029f23 5196 * value forced to the channel (n) output: The CHnOC bits enable the control of
mbed_official 324:406fd2029f23 5197 * the corresponding channel (n) output by software. The CHnOCV bits select the
mbed_official 324:406fd2029f23 5198 * value that is forced at the corresponding channel (n) output. This register has
mbed_official 324:406fd2029f23 5199 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
mbed_official 324:406fd2029f23 5200 */
mbed_official 324:406fd2029f23 5201 typedef union _hw_ftm_swoctrl
mbed_official 324:406fd2029f23 5202 {
mbed_official 324:406fd2029f23 5203 uint32_t U;
mbed_official 324:406fd2029f23 5204 struct _hw_ftm_swoctrl_bitfields
mbed_official 324:406fd2029f23 5205 {
mbed_official 324:406fd2029f23 5206 uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable
mbed_official 324:406fd2029f23 5207 * */
mbed_official 324:406fd2029f23 5208 uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable
mbed_official 324:406fd2029f23 5209 * */
mbed_official 324:406fd2029f23 5210 uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable
mbed_official 324:406fd2029f23 5211 * */
mbed_official 324:406fd2029f23 5212 uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable
mbed_official 324:406fd2029f23 5213 * */
mbed_official 324:406fd2029f23 5214 uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable
mbed_official 324:406fd2029f23 5215 * */
mbed_official 324:406fd2029f23 5216 uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable
mbed_official 324:406fd2029f23 5217 * */
mbed_official 324:406fd2029f23 5218 uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable
mbed_official 324:406fd2029f23 5219 * */
mbed_official 324:406fd2029f23 5220 uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable
mbed_official 324:406fd2029f23 5221 * */
mbed_official 324:406fd2029f23 5222 uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value
mbed_official 324:406fd2029f23 5223 * */
mbed_official 324:406fd2029f23 5224 uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value
mbed_official 324:406fd2029f23 5225 * */
mbed_official 324:406fd2029f23 5226 uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control
mbed_official 324:406fd2029f23 5227 * Value */
mbed_official 324:406fd2029f23 5228 uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control
mbed_official 324:406fd2029f23 5229 * Value */
mbed_official 324:406fd2029f23 5230 uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control
mbed_official 324:406fd2029f23 5231 * Value */
mbed_official 324:406fd2029f23 5232 uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control
mbed_official 324:406fd2029f23 5233 * Value */
mbed_official 324:406fd2029f23 5234 uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control
mbed_official 324:406fd2029f23 5235 * Value */
mbed_official 324:406fd2029f23 5236 uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control
mbed_official 324:406fd2029f23 5237 * Value */
mbed_official 324:406fd2029f23 5238 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 5239 } B;
mbed_official 324:406fd2029f23 5240 } hw_ftm_swoctrl_t;
mbed_official 324:406fd2029f23 5241
mbed_official 324:406fd2029f23 5242 /*!
mbed_official 324:406fd2029f23 5243 * @name Constants and macros for entire FTM_SWOCTRL register
mbed_official 324:406fd2029f23 5244 */
mbed_official 324:406fd2029f23 5245 /*@{*/
mbed_official 324:406fd2029f23 5246 #define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
mbed_official 324:406fd2029f23 5247
mbed_official 324:406fd2029f23 5248 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
mbed_official 324:406fd2029f23 5249 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
mbed_official 324:406fd2029f23 5250 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
mbed_official 324:406fd2029f23 5251 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 5252 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 5253 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 5254 /*@}*/
mbed_official 324:406fd2029f23 5255
mbed_official 324:406fd2029f23 5256 /*
mbed_official 324:406fd2029f23 5257 * Constants & macros for individual FTM_SWOCTRL bitfields
mbed_official 324:406fd2029f23 5258 */
mbed_official 324:406fd2029f23 5259
mbed_official 324:406fd2029f23 5260 /*!
mbed_official 324:406fd2029f23 5261 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
mbed_official 324:406fd2029f23 5262 *
mbed_official 324:406fd2029f23 5263 * Values:
mbed_official 324:406fd2029f23 5264 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5265 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5266 */
mbed_official 324:406fd2029f23 5267 /*@{*/
mbed_official 324:406fd2029f23 5268 #define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */
mbed_official 324:406fd2029f23 5269 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
mbed_official 324:406fd2029f23 5270 #define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
mbed_official 324:406fd2029f23 5271
mbed_official 324:406fd2029f23 5272 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
mbed_official 324:406fd2029f23 5273 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
mbed_official 324:406fd2029f23 5274
mbed_official 324:406fd2029f23 5275 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
mbed_official 324:406fd2029f23 5276 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
mbed_official 324:406fd2029f23 5277
mbed_official 324:406fd2029f23 5278 /*! @brief Set the CH0OC field to a new value. */
mbed_official 324:406fd2029f23 5279 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
mbed_official 324:406fd2029f23 5280 /*@}*/
mbed_official 324:406fd2029f23 5281
mbed_official 324:406fd2029f23 5282 /*!
mbed_official 324:406fd2029f23 5283 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
mbed_official 324:406fd2029f23 5284 *
mbed_official 324:406fd2029f23 5285 * Values:
mbed_official 324:406fd2029f23 5286 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5287 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5288 */
mbed_official 324:406fd2029f23 5289 /*@{*/
mbed_official 324:406fd2029f23 5290 #define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */
mbed_official 324:406fd2029f23 5291 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
mbed_official 324:406fd2029f23 5292 #define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
mbed_official 324:406fd2029f23 5293
mbed_official 324:406fd2029f23 5294 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
mbed_official 324:406fd2029f23 5295 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
mbed_official 324:406fd2029f23 5296
mbed_official 324:406fd2029f23 5297 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
mbed_official 324:406fd2029f23 5298 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
mbed_official 324:406fd2029f23 5299
mbed_official 324:406fd2029f23 5300 /*! @brief Set the CH1OC field to a new value. */
mbed_official 324:406fd2029f23 5301 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
mbed_official 324:406fd2029f23 5302 /*@}*/
mbed_official 324:406fd2029f23 5303
mbed_official 324:406fd2029f23 5304 /*!
mbed_official 324:406fd2029f23 5305 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
mbed_official 324:406fd2029f23 5306 *
mbed_official 324:406fd2029f23 5307 * Values:
mbed_official 324:406fd2029f23 5308 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5309 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5310 */
mbed_official 324:406fd2029f23 5311 /*@{*/
mbed_official 324:406fd2029f23 5312 #define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */
mbed_official 324:406fd2029f23 5313 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
mbed_official 324:406fd2029f23 5314 #define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
mbed_official 324:406fd2029f23 5315
mbed_official 324:406fd2029f23 5316 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
mbed_official 324:406fd2029f23 5317 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
mbed_official 324:406fd2029f23 5318
mbed_official 324:406fd2029f23 5319 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
mbed_official 324:406fd2029f23 5320 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
mbed_official 324:406fd2029f23 5321
mbed_official 324:406fd2029f23 5322 /*! @brief Set the CH2OC field to a new value. */
mbed_official 324:406fd2029f23 5323 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
mbed_official 324:406fd2029f23 5324 /*@}*/
mbed_official 324:406fd2029f23 5325
mbed_official 324:406fd2029f23 5326 /*!
mbed_official 324:406fd2029f23 5327 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
mbed_official 324:406fd2029f23 5328 *
mbed_official 324:406fd2029f23 5329 * Values:
mbed_official 324:406fd2029f23 5330 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5331 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5332 */
mbed_official 324:406fd2029f23 5333 /*@{*/
mbed_official 324:406fd2029f23 5334 #define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */
mbed_official 324:406fd2029f23 5335 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
mbed_official 324:406fd2029f23 5336 #define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
mbed_official 324:406fd2029f23 5337
mbed_official 324:406fd2029f23 5338 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
mbed_official 324:406fd2029f23 5339 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
mbed_official 324:406fd2029f23 5340
mbed_official 324:406fd2029f23 5341 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
mbed_official 324:406fd2029f23 5342 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
mbed_official 324:406fd2029f23 5343
mbed_official 324:406fd2029f23 5344 /*! @brief Set the CH3OC field to a new value. */
mbed_official 324:406fd2029f23 5345 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
mbed_official 324:406fd2029f23 5346 /*@}*/
mbed_official 324:406fd2029f23 5347
mbed_official 324:406fd2029f23 5348 /*!
mbed_official 324:406fd2029f23 5349 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
mbed_official 324:406fd2029f23 5350 *
mbed_official 324:406fd2029f23 5351 * Values:
mbed_official 324:406fd2029f23 5352 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5353 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5354 */
mbed_official 324:406fd2029f23 5355 /*@{*/
mbed_official 324:406fd2029f23 5356 #define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */
mbed_official 324:406fd2029f23 5357 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
mbed_official 324:406fd2029f23 5358 #define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
mbed_official 324:406fd2029f23 5359
mbed_official 324:406fd2029f23 5360 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
mbed_official 324:406fd2029f23 5361 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
mbed_official 324:406fd2029f23 5362
mbed_official 324:406fd2029f23 5363 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
mbed_official 324:406fd2029f23 5364 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
mbed_official 324:406fd2029f23 5365
mbed_official 324:406fd2029f23 5366 /*! @brief Set the CH4OC field to a new value. */
mbed_official 324:406fd2029f23 5367 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
mbed_official 324:406fd2029f23 5368 /*@}*/
mbed_official 324:406fd2029f23 5369
mbed_official 324:406fd2029f23 5370 /*!
mbed_official 324:406fd2029f23 5371 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
mbed_official 324:406fd2029f23 5372 *
mbed_official 324:406fd2029f23 5373 * Values:
mbed_official 324:406fd2029f23 5374 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5375 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5376 */
mbed_official 324:406fd2029f23 5377 /*@{*/
mbed_official 324:406fd2029f23 5378 #define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */
mbed_official 324:406fd2029f23 5379 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
mbed_official 324:406fd2029f23 5380 #define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
mbed_official 324:406fd2029f23 5381
mbed_official 324:406fd2029f23 5382 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
mbed_official 324:406fd2029f23 5383 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
mbed_official 324:406fd2029f23 5384
mbed_official 324:406fd2029f23 5385 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
mbed_official 324:406fd2029f23 5386 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
mbed_official 324:406fd2029f23 5387
mbed_official 324:406fd2029f23 5388 /*! @brief Set the CH5OC field to a new value. */
mbed_official 324:406fd2029f23 5389 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
mbed_official 324:406fd2029f23 5390 /*@}*/
mbed_official 324:406fd2029f23 5391
mbed_official 324:406fd2029f23 5392 /*!
mbed_official 324:406fd2029f23 5393 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
mbed_official 324:406fd2029f23 5394 *
mbed_official 324:406fd2029f23 5395 * Values:
mbed_official 324:406fd2029f23 5396 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5397 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5398 */
mbed_official 324:406fd2029f23 5399 /*@{*/
mbed_official 324:406fd2029f23 5400 #define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */
mbed_official 324:406fd2029f23 5401 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
mbed_official 324:406fd2029f23 5402 #define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
mbed_official 324:406fd2029f23 5403
mbed_official 324:406fd2029f23 5404 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
mbed_official 324:406fd2029f23 5405 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
mbed_official 324:406fd2029f23 5406
mbed_official 324:406fd2029f23 5407 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
mbed_official 324:406fd2029f23 5408 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
mbed_official 324:406fd2029f23 5409
mbed_official 324:406fd2029f23 5410 /*! @brief Set the CH6OC field to a new value. */
mbed_official 324:406fd2029f23 5411 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
mbed_official 324:406fd2029f23 5412 /*@}*/
mbed_official 324:406fd2029f23 5413
mbed_official 324:406fd2029f23 5414 /*!
mbed_official 324:406fd2029f23 5415 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
mbed_official 324:406fd2029f23 5416 *
mbed_official 324:406fd2029f23 5417 * Values:
mbed_official 324:406fd2029f23 5418 * - 0 - The channel output is not affected by software output control.
mbed_official 324:406fd2029f23 5419 * - 1 - The channel output is affected by software output control.
mbed_official 324:406fd2029f23 5420 */
mbed_official 324:406fd2029f23 5421 /*@{*/
mbed_official 324:406fd2029f23 5422 #define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */
mbed_official 324:406fd2029f23 5423 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
mbed_official 324:406fd2029f23 5424 #define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
mbed_official 324:406fd2029f23 5425
mbed_official 324:406fd2029f23 5426 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
mbed_official 324:406fd2029f23 5427 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
mbed_official 324:406fd2029f23 5428
mbed_official 324:406fd2029f23 5429 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
mbed_official 324:406fd2029f23 5430 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
mbed_official 324:406fd2029f23 5431
mbed_official 324:406fd2029f23 5432 /*! @brief Set the CH7OC field to a new value. */
mbed_official 324:406fd2029f23 5433 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
mbed_official 324:406fd2029f23 5434 /*@}*/
mbed_official 324:406fd2029f23 5435
mbed_official 324:406fd2029f23 5436 /*!
mbed_official 324:406fd2029f23 5437 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
mbed_official 324:406fd2029f23 5438 *
mbed_official 324:406fd2029f23 5439 * Values:
mbed_official 324:406fd2029f23 5440 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5441 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5442 */
mbed_official 324:406fd2029f23 5443 /*@{*/
mbed_official 324:406fd2029f23 5444 #define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
mbed_official 324:406fd2029f23 5445 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
mbed_official 324:406fd2029f23 5446 #define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
mbed_official 324:406fd2029f23 5447
mbed_official 324:406fd2029f23 5448 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
mbed_official 324:406fd2029f23 5449 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
mbed_official 324:406fd2029f23 5450
mbed_official 324:406fd2029f23 5451 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
mbed_official 324:406fd2029f23 5452 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
mbed_official 324:406fd2029f23 5453
mbed_official 324:406fd2029f23 5454 /*! @brief Set the CH0OCV field to a new value. */
mbed_official 324:406fd2029f23 5455 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
mbed_official 324:406fd2029f23 5456 /*@}*/
mbed_official 324:406fd2029f23 5457
mbed_official 324:406fd2029f23 5458 /*!
mbed_official 324:406fd2029f23 5459 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
mbed_official 324:406fd2029f23 5460 *
mbed_official 324:406fd2029f23 5461 * Values:
mbed_official 324:406fd2029f23 5462 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5463 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5464 */
mbed_official 324:406fd2029f23 5465 /*@{*/
mbed_official 324:406fd2029f23 5466 #define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
mbed_official 324:406fd2029f23 5467 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
mbed_official 324:406fd2029f23 5468 #define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
mbed_official 324:406fd2029f23 5469
mbed_official 324:406fd2029f23 5470 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
mbed_official 324:406fd2029f23 5471 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
mbed_official 324:406fd2029f23 5472
mbed_official 324:406fd2029f23 5473 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
mbed_official 324:406fd2029f23 5474 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
mbed_official 324:406fd2029f23 5475
mbed_official 324:406fd2029f23 5476 /*! @brief Set the CH1OCV field to a new value. */
mbed_official 324:406fd2029f23 5477 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
mbed_official 324:406fd2029f23 5478 /*@}*/
mbed_official 324:406fd2029f23 5479
mbed_official 324:406fd2029f23 5480 /*!
mbed_official 324:406fd2029f23 5481 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
mbed_official 324:406fd2029f23 5482 *
mbed_official 324:406fd2029f23 5483 * Values:
mbed_official 324:406fd2029f23 5484 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5485 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5486 */
mbed_official 324:406fd2029f23 5487 /*@{*/
mbed_official 324:406fd2029f23 5488 #define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
mbed_official 324:406fd2029f23 5489 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
mbed_official 324:406fd2029f23 5490 #define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
mbed_official 324:406fd2029f23 5491
mbed_official 324:406fd2029f23 5492 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
mbed_official 324:406fd2029f23 5493 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
mbed_official 324:406fd2029f23 5494
mbed_official 324:406fd2029f23 5495 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
mbed_official 324:406fd2029f23 5496 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
mbed_official 324:406fd2029f23 5497
mbed_official 324:406fd2029f23 5498 /*! @brief Set the CH2OCV field to a new value. */
mbed_official 324:406fd2029f23 5499 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
mbed_official 324:406fd2029f23 5500 /*@}*/
mbed_official 324:406fd2029f23 5501
mbed_official 324:406fd2029f23 5502 /*!
mbed_official 324:406fd2029f23 5503 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
mbed_official 324:406fd2029f23 5504 *
mbed_official 324:406fd2029f23 5505 * Values:
mbed_official 324:406fd2029f23 5506 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5507 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5508 */
mbed_official 324:406fd2029f23 5509 /*@{*/
mbed_official 324:406fd2029f23 5510 #define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
mbed_official 324:406fd2029f23 5511 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
mbed_official 324:406fd2029f23 5512 #define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
mbed_official 324:406fd2029f23 5513
mbed_official 324:406fd2029f23 5514 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
mbed_official 324:406fd2029f23 5515 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
mbed_official 324:406fd2029f23 5516
mbed_official 324:406fd2029f23 5517 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
mbed_official 324:406fd2029f23 5518 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
mbed_official 324:406fd2029f23 5519
mbed_official 324:406fd2029f23 5520 /*! @brief Set the CH3OCV field to a new value. */
mbed_official 324:406fd2029f23 5521 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
mbed_official 324:406fd2029f23 5522 /*@}*/
mbed_official 324:406fd2029f23 5523
mbed_official 324:406fd2029f23 5524 /*!
mbed_official 324:406fd2029f23 5525 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
mbed_official 324:406fd2029f23 5526 *
mbed_official 324:406fd2029f23 5527 * Values:
mbed_official 324:406fd2029f23 5528 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5529 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5530 */
mbed_official 324:406fd2029f23 5531 /*@{*/
mbed_official 324:406fd2029f23 5532 #define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
mbed_official 324:406fd2029f23 5533 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
mbed_official 324:406fd2029f23 5534 #define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
mbed_official 324:406fd2029f23 5535
mbed_official 324:406fd2029f23 5536 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
mbed_official 324:406fd2029f23 5537 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
mbed_official 324:406fd2029f23 5538
mbed_official 324:406fd2029f23 5539 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
mbed_official 324:406fd2029f23 5540 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
mbed_official 324:406fd2029f23 5541
mbed_official 324:406fd2029f23 5542 /*! @brief Set the CH4OCV field to a new value. */
mbed_official 324:406fd2029f23 5543 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
mbed_official 324:406fd2029f23 5544 /*@}*/
mbed_official 324:406fd2029f23 5545
mbed_official 324:406fd2029f23 5546 /*!
mbed_official 324:406fd2029f23 5547 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
mbed_official 324:406fd2029f23 5548 *
mbed_official 324:406fd2029f23 5549 * Values:
mbed_official 324:406fd2029f23 5550 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5551 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5552 */
mbed_official 324:406fd2029f23 5553 /*@{*/
mbed_official 324:406fd2029f23 5554 #define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
mbed_official 324:406fd2029f23 5555 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
mbed_official 324:406fd2029f23 5556 #define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
mbed_official 324:406fd2029f23 5557
mbed_official 324:406fd2029f23 5558 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
mbed_official 324:406fd2029f23 5559 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
mbed_official 324:406fd2029f23 5560
mbed_official 324:406fd2029f23 5561 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
mbed_official 324:406fd2029f23 5562 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
mbed_official 324:406fd2029f23 5563
mbed_official 324:406fd2029f23 5564 /*! @brief Set the CH5OCV field to a new value. */
mbed_official 324:406fd2029f23 5565 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
mbed_official 324:406fd2029f23 5566 /*@}*/
mbed_official 324:406fd2029f23 5567
mbed_official 324:406fd2029f23 5568 /*!
mbed_official 324:406fd2029f23 5569 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
mbed_official 324:406fd2029f23 5570 *
mbed_official 324:406fd2029f23 5571 * Values:
mbed_official 324:406fd2029f23 5572 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5573 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5574 */
mbed_official 324:406fd2029f23 5575 /*@{*/
mbed_official 324:406fd2029f23 5576 #define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
mbed_official 324:406fd2029f23 5577 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
mbed_official 324:406fd2029f23 5578 #define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
mbed_official 324:406fd2029f23 5579
mbed_official 324:406fd2029f23 5580 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
mbed_official 324:406fd2029f23 5581 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
mbed_official 324:406fd2029f23 5582
mbed_official 324:406fd2029f23 5583 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
mbed_official 324:406fd2029f23 5584 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
mbed_official 324:406fd2029f23 5585
mbed_official 324:406fd2029f23 5586 /*! @brief Set the CH6OCV field to a new value. */
mbed_official 324:406fd2029f23 5587 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
mbed_official 324:406fd2029f23 5588 /*@}*/
mbed_official 324:406fd2029f23 5589
mbed_official 324:406fd2029f23 5590 /*!
mbed_official 324:406fd2029f23 5591 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
mbed_official 324:406fd2029f23 5592 *
mbed_official 324:406fd2029f23 5593 * Values:
mbed_official 324:406fd2029f23 5594 * - 0 - The software output control forces 0 to the channel output.
mbed_official 324:406fd2029f23 5595 * - 1 - The software output control forces 1 to the channel output.
mbed_official 324:406fd2029f23 5596 */
mbed_official 324:406fd2029f23 5597 /*@{*/
mbed_official 324:406fd2029f23 5598 #define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
mbed_official 324:406fd2029f23 5599 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
mbed_official 324:406fd2029f23 5600 #define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
mbed_official 324:406fd2029f23 5601
mbed_official 324:406fd2029f23 5602 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
mbed_official 324:406fd2029f23 5603 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
mbed_official 324:406fd2029f23 5604
mbed_official 324:406fd2029f23 5605 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
mbed_official 324:406fd2029f23 5606 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
mbed_official 324:406fd2029f23 5607
mbed_official 324:406fd2029f23 5608 /*! @brief Set the CH7OCV field to a new value. */
mbed_official 324:406fd2029f23 5609 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
mbed_official 324:406fd2029f23 5610 /*@}*/
mbed_official 324:406fd2029f23 5611
mbed_official 324:406fd2029f23 5612 /*******************************************************************************
mbed_official 324:406fd2029f23 5613 * HW_FTM_PWMLOAD - FTM PWM Load
mbed_official 324:406fd2029f23 5614 ******************************************************************************/
mbed_official 324:406fd2029f23 5615
mbed_official 324:406fd2029f23 5616 /*!
mbed_official 324:406fd2029f23 5617 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
mbed_official 324:406fd2029f23 5618 *
mbed_official 324:406fd2029f23 5619 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 5620 *
mbed_official 324:406fd2029f23 5621 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
mbed_official 324:406fd2029f23 5622 * values of their write buffers when the FTM counter changes from the MOD
mbed_official 324:406fd2029f23 5623 * register value to its next value or when a channel (j) match occurs. A match occurs
mbed_official 324:406fd2029f23 5624 * for the channel (j) when FTM counter = C(j)V.
mbed_official 324:406fd2029f23 5625 */
mbed_official 324:406fd2029f23 5626 typedef union _hw_ftm_pwmload
mbed_official 324:406fd2029f23 5627 {
mbed_official 324:406fd2029f23 5628 uint32_t U;
mbed_official 324:406fd2029f23 5629 struct _hw_ftm_pwmload_bitfields
mbed_official 324:406fd2029f23 5630 {
mbed_official 324:406fd2029f23 5631 uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */
mbed_official 324:406fd2029f23 5632 uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */
mbed_official 324:406fd2029f23 5633 uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */
mbed_official 324:406fd2029f23 5634 uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */
mbed_official 324:406fd2029f23 5635 uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */
mbed_official 324:406fd2029f23 5636 uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */
mbed_official 324:406fd2029f23 5637 uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */
mbed_official 324:406fd2029f23 5638 uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */
mbed_official 324:406fd2029f23 5639 uint32_t RESERVED0 : 1; /*!< [8] */
mbed_official 324:406fd2029f23 5640 uint32_t LDOK : 1; /*!< [9] Load Enable */
mbed_official 324:406fd2029f23 5641 uint32_t RESERVED1 : 22; /*!< [31:10] */
mbed_official 324:406fd2029f23 5642 } B;
mbed_official 324:406fd2029f23 5643 } hw_ftm_pwmload_t;
mbed_official 324:406fd2029f23 5644
mbed_official 324:406fd2029f23 5645 /*!
mbed_official 324:406fd2029f23 5646 * @name Constants and macros for entire FTM_PWMLOAD register
mbed_official 324:406fd2029f23 5647 */
mbed_official 324:406fd2029f23 5648 /*@{*/
mbed_official 324:406fd2029f23 5649 #define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
mbed_official 324:406fd2029f23 5650
mbed_official 324:406fd2029f23 5651 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
mbed_official 324:406fd2029f23 5652 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
mbed_official 324:406fd2029f23 5653 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
mbed_official 324:406fd2029f23 5654 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
mbed_official 324:406fd2029f23 5655 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 5656 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 5657 /*@}*/
mbed_official 324:406fd2029f23 5658
mbed_official 324:406fd2029f23 5659 /*
mbed_official 324:406fd2029f23 5660 * Constants & macros for individual FTM_PWMLOAD bitfields
mbed_official 324:406fd2029f23 5661 */
mbed_official 324:406fd2029f23 5662
mbed_official 324:406fd2029f23 5663 /*!
mbed_official 324:406fd2029f23 5664 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
mbed_official 324:406fd2029f23 5665 *
mbed_official 324:406fd2029f23 5666 * Values:
mbed_official 324:406fd2029f23 5667 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5668 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5669 */
mbed_official 324:406fd2029f23 5670 /*@{*/
mbed_official 324:406fd2029f23 5671 #define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
mbed_official 324:406fd2029f23 5672 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
mbed_official 324:406fd2029f23 5673 #define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
mbed_official 324:406fd2029f23 5674
mbed_official 324:406fd2029f23 5675 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
mbed_official 324:406fd2029f23 5676 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
mbed_official 324:406fd2029f23 5677
mbed_official 324:406fd2029f23 5678 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
mbed_official 324:406fd2029f23 5679 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
mbed_official 324:406fd2029f23 5680
mbed_official 324:406fd2029f23 5681 /*! @brief Set the CH0SEL field to a new value. */
mbed_official 324:406fd2029f23 5682 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
mbed_official 324:406fd2029f23 5683 /*@}*/
mbed_official 324:406fd2029f23 5684
mbed_official 324:406fd2029f23 5685 /*!
mbed_official 324:406fd2029f23 5686 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
mbed_official 324:406fd2029f23 5687 *
mbed_official 324:406fd2029f23 5688 * Values:
mbed_official 324:406fd2029f23 5689 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5690 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5691 */
mbed_official 324:406fd2029f23 5692 /*@{*/
mbed_official 324:406fd2029f23 5693 #define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
mbed_official 324:406fd2029f23 5694 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
mbed_official 324:406fd2029f23 5695 #define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
mbed_official 324:406fd2029f23 5696
mbed_official 324:406fd2029f23 5697 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
mbed_official 324:406fd2029f23 5698 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
mbed_official 324:406fd2029f23 5699
mbed_official 324:406fd2029f23 5700 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
mbed_official 324:406fd2029f23 5701 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
mbed_official 324:406fd2029f23 5702
mbed_official 324:406fd2029f23 5703 /*! @brief Set the CH1SEL field to a new value. */
mbed_official 324:406fd2029f23 5704 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
mbed_official 324:406fd2029f23 5705 /*@}*/
mbed_official 324:406fd2029f23 5706
mbed_official 324:406fd2029f23 5707 /*!
mbed_official 324:406fd2029f23 5708 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
mbed_official 324:406fd2029f23 5709 *
mbed_official 324:406fd2029f23 5710 * Values:
mbed_official 324:406fd2029f23 5711 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5712 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5713 */
mbed_official 324:406fd2029f23 5714 /*@{*/
mbed_official 324:406fd2029f23 5715 #define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
mbed_official 324:406fd2029f23 5716 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
mbed_official 324:406fd2029f23 5717 #define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
mbed_official 324:406fd2029f23 5718
mbed_official 324:406fd2029f23 5719 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
mbed_official 324:406fd2029f23 5720 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
mbed_official 324:406fd2029f23 5721
mbed_official 324:406fd2029f23 5722 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
mbed_official 324:406fd2029f23 5723 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
mbed_official 324:406fd2029f23 5724
mbed_official 324:406fd2029f23 5725 /*! @brief Set the CH2SEL field to a new value. */
mbed_official 324:406fd2029f23 5726 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
mbed_official 324:406fd2029f23 5727 /*@}*/
mbed_official 324:406fd2029f23 5728
mbed_official 324:406fd2029f23 5729 /*!
mbed_official 324:406fd2029f23 5730 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
mbed_official 324:406fd2029f23 5731 *
mbed_official 324:406fd2029f23 5732 * Values:
mbed_official 324:406fd2029f23 5733 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5734 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5735 */
mbed_official 324:406fd2029f23 5736 /*@{*/
mbed_official 324:406fd2029f23 5737 #define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
mbed_official 324:406fd2029f23 5738 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
mbed_official 324:406fd2029f23 5739 #define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
mbed_official 324:406fd2029f23 5740
mbed_official 324:406fd2029f23 5741 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
mbed_official 324:406fd2029f23 5742 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
mbed_official 324:406fd2029f23 5743
mbed_official 324:406fd2029f23 5744 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
mbed_official 324:406fd2029f23 5745 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
mbed_official 324:406fd2029f23 5746
mbed_official 324:406fd2029f23 5747 /*! @brief Set the CH3SEL field to a new value. */
mbed_official 324:406fd2029f23 5748 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
mbed_official 324:406fd2029f23 5749 /*@}*/
mbed_official 324:406fd2029f23 5750
mbed_official 324:406fd2029f23 5751 /*!
mbed_official 324:406fd2029f23 5752 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
mbed_official 324:406fd2029f23 5753 *
mbed_official 324:406fd2029f23 5754 * Values:
mbed_official 324:406fd2029f23 5755 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5756 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5757 */
mbed_official 324:406fd2029f23 5758 /*@{*/
mbed_official 324:406fd2029f23 5759 #define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
mbed_official 324:406fd2029f23 5760 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
mbed_official 324:406fd2029f23 5761 #define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
mbed_official 324:406fd2029f23 5762
mbed_official 324:406fd2029f23 5763 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
mbed_official 324:406fd2029f23 5764 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
mbed_official 324:406fd2029f23 5765
mbed_official 324:406fd2029f23 5766 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
mbed_official 324:406fd2029f23 5767 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
mbed_official 324:406fd2029f23 5768
mbed_official 324:406fd2029f23 5769 /*! @brief Set the CH4SEL field to a new value. */
mbed_official 324:406fd2029f23 5770 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
mbed_official 324:406fd2029f23 5771 /*@}*/
mbed_official 324:406fd2029f23 5772
mbed_official 324:406fd2029f23 5773 /*!
mbed_official 324:406fd2029f23 5774 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
mbed_official 324:406fd2029f23 5775 *
mbed_official 324:406fd2029f23 5776 * Values:
mbed_official 324:406fd2029f23 5777 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5778 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5779 */
mbed_official 324:406fd2029f23 5780 /*@{*/
mbed_official 324:406fd2029f23 5781 #define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
mbed_official 324:406fd2029f23 5782 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
mbed_official 324:406fd2029f23 5783 #define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
mbed_official 324:406fd2029f23 5784
mbed_official 324:406fd2029f23 5785 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
mbed_official 324:406fd2029f23 5786 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
mbed_official 324:406fd2029f23 5787
mbed_official 324:406fd2029f23 5788 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
mbed_official 324:406fd2029f23 5789 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
mbed_official 324:406fd2029f23 5790
mbed_official 324:406fd2029f23 5791 /*! @brief Set the CH5SEL field to a new value. */
mbed_official 324:406fd2029f23 5792 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
mbed_official 324:406fd2029f23 5793 /*@}*/
mbed_official 324:406fd2029f23 5794
mbed_official 324:406fd2029f23 5795 /*!
mbed_official 324:406fd2029f23 5796 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
mbed_official 324:406fd2029f23 5797 *
mbed_official 324:406fd2029f23 5798 * Values:
mbed_official 324:406fd2029f23 5799 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5800 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5801 */
mbed_official 324:406fd2029f23 5802 /*@{*/
mbed_official 324:406fd2029f23 5803 #define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
mbed_official 324:406fd2029f23 5804 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
mbed_official 324:406fd2029f23 5805 #define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
mbed_official 324:406fd2029f23 5806
mbed_official 324:406fd2029f23 5807 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
mbed_official 324:406fd2029f23 5808 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
mbed_official 324:406fd2029f23 5809
mbed_official 324:406fd2029f23 5810 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
mbed_official 324:406fd2029f23 5811 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
mbed_official 324:406fd2029f23 5812
mbed_official 324:406fd2029f23 5813 /*! @brief Set the CH6SEL field to a new value. */
mbed_official 324:406fd2029f23 5814 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
mbed_official 324:406fd2029f23 5815 /*@}*/
mbed_official 324:406fd2029f23 5816
mbed_official 324:406fd2029f23 5817 /*!
mbed_official 324:406fd2029f23 5818 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
mbed_official 324:406fd2029f23 5819 *
mbed_official 324:406fd2029f23 5820 * Values:
mbed_official 324:406fd2029f23 5821 * - 0 - Do not include the channel in the matching process.
mbed_official 324:406fd2029f23 5822 * - 1 - Include the channel in the matching process.
mbed_official 324:406fd2029f23 5823 */
mbed_official 324:406fd2029f23 5824 /*@{*/
mbed_official 324:406fd2029f23 5825 #define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
mbed_official 324:406fd2029f23 5826 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
mbed_official 324:406fd2029f23 5827 #define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
mbed_official 324:406fd2029f23 5828
mbed_official 324:406fd2029f23 5829 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
mbed_official 324:406fd2029f23 5830 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
mbed_official 324:406fd2029f23 5831
mbed_official 324:406fd2029f23 5832 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
mbed_official 324:406fd2029f23 5833 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
mbed_official 324:406fd2029f23 5834
mbed_official 324:406fd2029f23 5835 /*! @brief Set the CH7SEL field to a new value. */
mbed_official 324:406fd2029f23 5836 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
mbed_official 324:406fd2029f23 5837 /*@}*/
mbed_official 324:406fd2029f23 5838
mbed_official 324:406fd2029f23 5839 /*!
mbed_official 324:406fd2029f23 5840 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
mbed_official 324:406fd2029f23 5841 *
mbed_official 324:406fd2029f23 5842 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
mbed_official 324:406fd2029f23 5843 * their write buffers.
mbed_official 324:406fd2029f23 5844 *
mbed_official 324:406fd2029f23 5845 * Values:
mbed_official 324:406fd2029f23 5846 * - 0 - Loading updated values is disabled.
mbed_official 324:406fd2029f23 5847 * - 1 - Loading updated values is enabled.
mbed_official 324:406fd2029f23 5848 */
mbed_official 324:406fd2029f23 5849 /*@{*/
mbed_official 324:406fd2029f23 5850 #define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */
mbed_official 324:406fd2029f23 5851 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
mbed_official 324:406fd2029f23 5852 #define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
mbed_official 324:406fd2029f23 5853
mbed_official 324:406fd2029f23 5854 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
mbed_official 324:406fd2029f23 5855 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
mbed_official 324:406fd2029f23 5856
mbed_official 324:406fd2029f23 5857 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
mbed_official 324:406fd2029f23 5858 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
mbed_official 324:406fd2029f23 5859
mbed_official 324:406fd2029f23 5860 /*! @brief Set the LDOK field to a new value. */
mbed_official 324:406fd2029f23 5861 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
mbed_official 324:406fd2029f23 5862 /*@}*/
mbed_official 324:406fd2029f23 5863
mbed_official 324:406fd2029f23 5864 /*******************************************************************************
mbed_official 324:406fd2029f23 5865 * hw_ftm_t - module struct
mbed_official 324:406fd2029f23 5866 ******************************************************************************/
mbed_official 324:406fd2029f23 5867 /*!
mbed_official 324:406fd2029f23 5868 * @brief All FTM module registers.
mbed_official 324:406fd2029f23 5869 */
mbed_official 324:406fd2029f23 5870 #pragma pack(1)
mbed_official 324:406fd2029f23 5871 typedef struct _hw_ftm
mbed_official 324:406fd2029f23 5872 {
mbed_official 324:406fd2029f23 5873 __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */
mbed_official 324:406fd2029f23 5874 __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */
mbed_official 324:406fd2029f23 5875 __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */
mbed_official 324:406fd2029f23 5876 struct {
mbed_official 324:406fd2029f23 5877 __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */
mbed_official 324:406fd2029f23 5878 __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */
mbed_official 324:406fd2029f23 5879 } CONTROLS[8];
mbed_official 324:406fd2029f23 5880 __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */
mbed_official 324:406fd2029f23 5881 __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */
mbed_official 324:406fd2029f23 5882 __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */
mbed_official 324:406fd2029f23 5883 __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */
mbed_official 324:406fd2029f23 5884 __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */
mbed_official 324:406fd2029f23 5885 __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */
mbed_official 324:406fd2029f23 5886 __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */
mbed_official 324:406fd2029f23 5887 __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */
mbed_official 324:406fd2029f23 5888 __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */
mbed_official 324:406fd2029f23 5889 __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */
mbed_official 324:406fd2029f23 5890 __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */
mbed_official 324:406fd2029f23 5891 __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */
mbed_official 324:406fd2029f23 5892 __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */
mbed_official 324:406fd2029f23 5893 __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */
mbed_official 324:406fd2029f23 5894 __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */
mbed_official 324:406fd2029f23 5895 __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */
mbed_official 324:406fd2029f23 5896 __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */
mbed_official 324:406fd2029f23 5897 __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */
mbed_official 324:406fd2029f23 5898 __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */
mbed_official 324:406fd2029f23 5899 __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */
mbed_official 324:406fd2029f23 5900 } hw_ftm_t;
mbed_official 324:406fd2029f23 5901 #pragma pack()
mbed_official 324:406fd2029f23 5902
mbed_official 324:406fd2029f23 5903 /*! @brief Macro to access all FTM registers. */
mbed_official 324:406fd2029f23 5904 /*! @param x FTM module instance base address. */
mbed_official 324:406fd2029f23 5905 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 5906 * use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
mbed_official 324:406fd2029f23 5907 #define HW_FTM(x) (*(hw_ftm_t *)(x))
mbed_official 324:406fd2029f23 5908
mbed_official 324:406fd2029f23 5909 #endif /* __HW_FTM_REGISTERS_H__ */
mbed_official 324:406fd2029f23 5910 /* EOF */