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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftfe.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_FTFE_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_FTFE_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 FTFE
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Flash Memory Interface
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_FTFE_FSTAT - Flash Status Register
mbed_official	324:406fd2029f23	93	* - HW_FTFE_FCNFG - Flash Configuration Register
mbed_official	324:406fd2029f23	94	* - HW_FTFE_FSEC - Flash Security Register
mbed_official	324:406fd2029f23	95	* - HW_FTFE_FOPT - Flash Option Register
mbed_official	324:406fd2029f23	96	* - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	97	* - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	98	* - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	99	* - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	100	* - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	101	* - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	102	* - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	103	* - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	104	* - HW_FTFE_FCCOBB - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	105	* - HW_FTFE_FCCOBA - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	106	* - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	107	* - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	108	* - HW_FTFE_FPROT3 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	109	* - HW_FTFE_FPROT2 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	110	* - HW_FTFE_FPROT1 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	111	* - HW_FTFE_FPROT0 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	112	* - HW_FTFE_FEPROT - EEPROM Protection Register
mbed_official	324:406fd2029f23	113	* - HW_FTFE_FDPROT - Data Flash Protection Register
mbed_official	324:406fd2029f23	114	*
mbed_official	324:406fd2029f23	115	* - hw_ftfe_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	116	*/
mbed_official	324:406fd2029f23	117
mbed_official	324:406fd2029f23	118	#define HW_FTFE_INSTANCE_COUNT (1U) /!< Number of instances of the FTFE module. /
mbed_official	324:406fd2029f23	119
mbed_official	324:406fd2029f23	120	/*******************************************************************************
mbed_official	324:406fd2029f23	121	* HW_FTFE_FSTAT - Flash Status Register
mbed_official	324:406fd2029f23	122	******************************************************************************/
mbed_official	324:406fd2029f23	123
mbed_official	324:406fd2029f23	124	/*!
mbed_official	324:406fd2029f23	125	* @brief HW_FTFE_FSTAT - Flash Status Register (RW)
mbed_official	324:406fd2029f23	126	*
mbed_official	324:406fd2029f23	127	* Reset value: 0x00U
mbed_official	324:406fd2029f23	128	*
mbed_official	324:406fd2029f23	129	* The FSTAT register reports the operational status of the FTFE module. The
mbed_official	324:406fd2029f23	130	* CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
mbed_official	324:406fd2029f23	131	* bit is read only. The unassigned bits read 0 and are not writable. When set, the
mbed_official	324:406fd2029f23	132	* Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
mbed_official	324:406fd2029f23	133	* register prevent the launch of any more commands or writes to the FlexRAM (when
mbed_official	324:406fd2029f23	134	* EEERDY is set) until the flag is cleared (by writing a one to it).
mbed_official	324:406fd2029f23	135	*/
mbed_official	324:406fd2029f23	136	typedef union _hw_ftfe_fstat
mbed_official	324:406fd2029f23	137	{
mbed_official	324:406fd2029f23	138	uint8_t U;
mbed_official	324:406fd2029f23	139	struct _hw_ftfe_fstat_bitfields
mbed_official	324:406fd2029f23	140	{
mbed_official	324:406fd2029f23	141	uint8_t MGSTAT0 : 1; /*!< [0] Memory Controller Command Completion
mbed_official	324:406fd2029f23	142	* Status Flag */
mbed_official	324:406fd2029f23	143	uint8_t RESERVED0 : 3; /!< [3:1] /
mbed_official	324:406fd2029f23	144	uint8_t FPVIOL : 1; /!< [4] Flash Protection Violation Flag /
mbed_official	324:406fd2029f23	145	uint8_t ACCERR : 1; /!< [5] Flash Access Error Flag /
mbed_official	324:406fd2029f23	146	uint8_t RDCOLERR : 1; /!< [6] FTFE Read Collision Error Flag /
mbed_official	324:406fd2029f23	147	uint8_t CCIF : 1; /!< [7] Command Complete Interrupt Flag /
mbed_official	324:406fd2029f23	148	} B;
mbed_official	324:406fd2029f23	149	} hw_ftfe_fstat_t;
mbed_official	324:406fd2029f23	150
mbed_official	324:406fd2029f23	151	/*!
mbed_official	324:406fd2029f23	152	* @name Constants and macros for entire FTFE_FSTAT register
mbed_official	324:406fd2029f23	153	*/
mbed_official	324:406fd2029f23	154	/@{/
mbed_official	324:406fd2029f23	155	#define HW_FTFE_FSTAT_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	156
mbed_official	324:406fd2029f23	157	#define HW_FTFE_FSTAT(x) ((__IO hw_ftfe_fstat_t ) HW_FTFE_FSTAT_ADDR(x))
mbed_official	324:406fd2029f23	158	#define HW_FTFE_FSTAT_RD(x) (HW_FTFE_FSTAT(x).U)
mbed_official	324:406fd2029f23	159	#define HW_FTFE_FSTAT_WR(x, v) (HW_FTFE_FSTAT(x).U = (v))
mbed_official	324:406fd2029f23	160	#define HW_FTFE_FSTAT_SET(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	161	#define HW_FTFE_FSTAT_CLR(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	162	#define HW_FTFE_FSTAT_TOG(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	163	/@}/
mbed_official	324:406fd2029f23	164
mbed_official	324:406fd2029f23	165	/*
mbed_official	324:406fd2029f23	166	* Constants & macros for individual FTFE_FSTAT bitfields
mbed_official	324:406fd2029f23	167	*/
mbed_official	324:406fd2029f23	168
mbed_official	324:406fd2029f23	169	/*!
mbed_official	324:406fd2029f23	170	* @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
mbed_official	324:406fd2029f23	171	*
mbed_official	324:406fd2029f23	172	* The MGSTAT0 status flag is set if an error is detected during execution of an
mbed_official	324:406fd2029f23	173	* FTFE command or during the flash reset sequence. As a status flag, this bit
mbed_official	324:406fd2029f23	174	* cannot (and need not) be cleared by the user like the other error flags in this
mbed_official	324:406fd2029f23	175	* register. The value of the MGSTAT0 bit for "command-N" is valid only at the
mbed_official	324:406fd2029f23	176	* end of the "command-N" execution when CCIF=1 and before the next command has
mbed_official	324:406fd2029f23	177	* been launched. At some point during the execution of "command-N+1," the previous
mbed_official	324:406fd2029f23	178	* result is discarded and any previous error is cleared.
mbed_official	324:406fd2029f23	179	*/
mbed_official	324:406fd2029f23	180	/@{/
mbed_official	324:406fd2029f23	181	#define BP_FTFE_FSTAT_MGSTAT0 (0U) /!< Bit position for FTFE_FSTAT_MGSTAT0. /
mbed_official	324:406fd2029f23	182	#define BM_FTFE_FSTAT_MGSTAT0 (0x01U) /!< Bit mask for FTFE_FSTAT_MGSTAT0. /
mbed_official	324:406fd2029f23	183	#define BS_FTFE_FSTAT_MGSTAT0 (1U) /!< Bit field size in bits for FTFE_FSTAT_MGSTAT0. /
mbed_official	324:406fd2029f23	184
mbed_official	324:406fd2029f23	185	/! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. /
mbed_official	324:406fd2029f23	186	#define BR_FTFE_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_MGSTAT0))
mbed_official	324:406fd2029f23	187	/@}/
mbed_official	324:406fd2029f23	188
mbed_official	324:406fd2029f23	189	/*!
mbed_official	324:406fd2029f23	190	* @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
mbed_official	324:406fd2029f23	191	*
mbed_official	324:406fd2029f23	192	* The FPVIOL error bit indicates an attempt was made to program or erase an
mbed_official	324:406fd2029f23	193	* address in a protected area of program flash or data flash memory during a
mbed_official	324:406fd2029f23	194	* command write sequence or a write was attempted to a protected area of the FlexRAM
mbed_official	324:406fd2029f23	195	* while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
mbed_official	324:406fd2029f23	196	* to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
mbed_official	324:406fd2029f23	197	* 0 to the FPVIOL bit has no effect.
mbed_official	324:406fd2029f23	198	*
mbed_official	324:406fd2029f23	199	* Values:
mbed_official	324:406fd2029f23	200	* - 0 - No protection violation detected
mbed_official	324:406fd2029f23	201	* - 1 - Protection violation detected
mbed_official	324:406fd2029f23	202	*/
mbed_official	324:406fd2029f23	203	/@{/
mbed_official	324:406fd2029f23	204	#define BP_FTFE_FSTAT_FPVIOL (4U) /!< Bit position for FTFE_FSTAT_FPVIOL. /
mbed_official	324:406fd2029f23	205	#define BM_FTFE_FSTAT_FPVIOL (0x10U) /!< Bit mask for FTFE_FSTAT_FPVIOL. /
mbed_official	324:406fd2029f23	206	#define BS_FTFE_FSTAT_FPVIOL (1U) /!< Bit field size in bits for FTFE_FSTAT_FPVIOL. /
mbed_official	324:406fd2029f23	207
mbed_official	324:406fd2029f23	208	/! @brief Read current value of the FTFE_FSTAT_FPVIOL field. /
mbed_official	324:406fd2029f23	209	#define BR_FTFE_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL))
mbed_official	324:406fd2029f23	210
mbed_official	324:406fd2029f23	211	/! @brief Format value for bitfield FTFE_FSTAT_FPVIOL. /
mbed_official	324:406fd2029f23	212	#define BF_FTFE_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_FPVIOL) & BM_FTFE_FSTAT_FPVIOL)
mbed_official	324:406fd2029f23	213
mbed_official	324:406fd2029f23	214	/! @brief Set the FPVIOL field to a new value. /
mbed_official	324:406fd2029f23	215	#define BW_FTFE_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL) = (v))
mbed_official	324:406fd2029f23	216	/@}/
mbed_official	324:406fd2029f23	217
mbed_official	324:406fd2029f23	218	/*!
mbed_official	324:406fd2029f23	219	* @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
mbed_official	324:406fd2029f23	220	*
mbed_official	324:406fd2029f23	221	* The ACCERR error bit indicates an illegal access has occurred to an FTFE
mbed_official	324:406fd2029f23	222	* resource caused by a violation of the command write sequence or issuing an illegal
mbed_official	324:406fd2029f23	223	* FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
mbed_official	324:406fd2029f23	224	* a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
mbed_official	324:406fd2029f23	225	* ACCERR bit has no effect.
mbed_official	324:406fd2029f23	226	*
mbed_official	324:406fd2029f23	227	* Values:
mbed_official	324:406fd2029f23	228	* - 0 - No access error detected
mbed_official	324:406fd2029f23	229	* - 1 - Access error detected
mbed_official	324:406fd2029f23	230	*/
mbed_official	324:406fd2029f23	231	/@{/
mbed_official	324:406fd2029f23	232	#define BP_FTFE_FSTAT_ACCERR (5U) /!< Bit position for FTFE_FSTAT_ACCERR. /
mbed_official	324:406fd2029f23	233	#define BM_FTFE_FSTAT_ACCERR (0x20U) /!< Bit mask for FTFE_FSTAT_ACCERR. /
mbed_official	324:406fd2029f23	234	#define BS_FTFE_FSTAT_ACCERR (1U) /!< Bit field size in bits for FTFE_FSTAT_ACCERR. /
mbed_official	324:406fd2029f23	235
mbed_official	324:406fd2029f23	236	/! @brief Read current value of the FTFE_FSTAT_ACCERR field. /
mbed_official	324:406fd2029f23	237	#define BR_FTFE_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR))
mbed_official	324:406fd2029f23	238
mbed_official	324:406fd2029f23	239	/! @brief Format value for bitfield FTFE_FSTAT_ACCERR. /
mbed_official	324:406fd2029f23	240	#define BF_FTFE_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_ACCERR) & BM_FTFE_FSTAT_ACCERR)
mbed_official	324:406fd2029f23	241
mbed_official	324:406fd2029f23	242	/! @brief Set the ACCERR field to a new value. /
mbed_official	324:406fd2029f23	243	#define BW_FTFE_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR) = (v))
mbed_official	324:406fd2029f23	244	/@}/
mbed_official	324:406fd2029f23	245
mbed_official	324:406fd2029f23	246	/*!
mbed_official	324:406fd2029f23	247	* @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
mbed_official	324:406fd2029f23	248	*
mbed_official	324:406fd2029f23	249	* The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
mbed_official	324:406fd2029f23	250	* resource that was being manipulated by an FTFE command (CCIF=0). Any
mbed_official	324:406fd2029f23	251	* simultaneous access is detected as a collision error by the block arbitration logic. The
mbed_official	324:406fd2029f23	252	* read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
mbed_official	324:406fd2029f23	253	* writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
mbed_official	324:406fd2029f23	254	*
mbed_official	324:406fd2029f23	255	* Values:
mbed_official	324:406fd2029f23	256	* - 0 - No collision error detected
mbed_official	324:406fd2029f23	257	* - 1 - Collision error detected
mbed_official	324:406fd2029f23	258	*/
mbed_official	324:406fd2029f23	259	/@{/
mbed_official	324:406fd2029f23	260	#define BP_FTFE_FSTAT_RDCOLERR (6U) /!< Bit position for FTFE_FSTAT_RDCOLERR. /
mbed_official	324:406fd2029f23	261	#define BM_FTFE_FSTAT_RDCOLERR (0x40U) /!< Bit mask for FTFE_FSTAT_RDCOLERR. /
mbed_official	324:406fd2029f23	262	#define BS_FTFE_FSTAT_RDCOLERR (1U) /!< Bit field size in bits for FTFE_FSTAT_RDCOLERR. /
mbed_official	324:406fd2029f23	263
mbed_official	324:406fd2029f23	264	/! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. /
mbed_official	324:406fd2029f23	265	#define BR_FTFE_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR))
mbed_official	324:406fd2029f23	266
mbed_official	324:406fd2029f23	267	/! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR. /
mbed_official	324:406fd2029f23	268	#define BF_FTFE_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_RDCOLERR) & BM_FTFE_FSTAT_RDCOLERR)
mbed_official	324:406fd2029f23	269
mbed_official	324:406fd2029f23	270	/! @brief Set the RDCOLERR field to a new value. /
mbed_official	324:406fd2029f23	271	#define BW_FTFE_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR) = (v))
mbed_official	324:406fd2029f23	272	/@}/
mbed_official	324:406fd2029f23	273
mbed_official	324:406fd2029f23	274	/*!
mbed_official	324:406fd2029f23	275	* @name Register FTFE_FSTAT, field CCIF[7] (W1C)
mbed_official	324:406fd2029f23	276	*
mbed_official	324:406fd2029f23	277	* The CCIF flag indicates that a FTFE command or EEPROM file system operation
mbed_official	324:406fd2029f23	278	* has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
mbed_official	324:406fd2029f23	279	* command, and CCIF stays low until command completion or command violation. The
mbed_official	324:406fd2029f23	280	* CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
mbed_official	324:406fd2029f23	281	* and CCIF stays low until the EEPROM file system has created the associated
mbed_official	324:406fd2029f23	282	* EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
mbed_official	324:406fd2029f23	283	* controller at the end of the reset initialization sequence. Depending on how
mbed_official	324:406fd2029f23	284	* quickly the read occurs after reset release, the user may or may not see the 0
mbed_official	324:406fd2029f23	285	* hardware reset value.
mbed_official	324:406fd2029f23	286	*
mbed_official	324:406fd2029f23	287	* Values:
mbed_official	324:406fd2029f23	288	* - 0 - FTFE command or EEPROM file system operation in progress
mbed_official	324:406fd2029f23	289	* - 1 - FTFE command or EEPROM file system operation has completed
mbed_official	324:406fd2029f23	290	*/
mbed_official	324:406fd2029f23	291	/@{/
mbed_official	324:406fd2029f23	292	#define BP_FTFE_FSTAT_CCIF (7U) /!< Bit position for FTFE_FSTAT_CCIF. /
mbed_official	324:406fd2029f23	293	#define BM_FTFE_FSTAT_CCIF (0x80U) /!< Bit mask for FTFE_FSTAT_CCIF. /
mbed_official	324:406fd2029f23	294	#define BS_FTFE_FSTAT_CCIF (1U) /!< Bit field size in bits for FTFE_FSTAT_CCIF. /
mbed_official	324:406fd2029f23	295
mbed_official	324:406fd2029f23	296	/! @brief Read current value of the FTFE_FSTAT_CCIF field. /
mbed_official	324:406fd2029f23	297	#define BR_FTFE_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF))
mbed_official	324:406fd2029f23	298
mbed_official	324:406fd2029f23	299	/! @brief Format value for bitfield FTFE_FSTAT_CCIF. /
mbed_official	324:406fd2029f23	300	#define BF_FTFE_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_CCIF) & BM_FTFE_FSTAT_CCIF)
mbed_official	324:406fd2029f23	301
mbed_official	324:406fd2029f23	302	/! @brief Set the CCIF field to a new value. /
mbed_official	324:406fd2029f23	303	#define BW_FTFE_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF) = (v))
mbed_official	324:406fd2029f23	304	/@}/
mbed_official	324:406fd2029f23	305
mbed_official	324:406fd2029f23	306	/*******************************************************************************
mbed_official	324:406fd2029f23	307	* HW_FTFE_FCNFG - Flash Configuration Register
mbed_official	324:406fd2029f23	308	******************************************************************************/
mbed_official	324:406fd2029f23	309
mbed_official	324:406fd2029f23	310	/*!
mbed_official	324:406fd2029f23	311	* @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
mbed_official	324:406fd2029f23	312	*
mbed_official	324:406fd2029f23	313	* Reset value: 0x00U
mbed_official	324:406fd2029f23	314	*
mbed_official	324:406fd2029f23	315	* This register provides information on the current functional state of the
mbed_official	324:406fd2029f23	316	* FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
mbed_official	324:406fd2029f23	317	* restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
mbed_official	324:406fd2029f23	318	* bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
mbed_official	324:406fd2029f23	319	* RAMRDY, and EEERDY bits are determined during the reset sequence.
mbed_official	324:406fd2029f23	320	*/
mbed_official	324:406fd2029f23	321	typedef union _hw_ftfe_fcnfg
mbed_official	324:406fd2029f23	322	{
mbed_official	324:406fd2029f23	323	uint8_t U;
mbed_official	324:406fd2029f23	324	struct _hw_ftfe_fcnfg_bitfields
mbed_official	324:406fd2029f23	325	{
mbed_official	324:406fd2029f23	326	uint8_t EEERDY : 1; /!< [0] /
mbed_official	324:406fd2029f23	327	uint8_t RAMRDY : 1; /!< [1] RAM Ready /
mbed_official	324:406fd2029f23	328	uint8_t PFLSH : 1; /!< [2] FTFE configuration /
mbed_official	324:406fd2029f23	329	uint8_t SWAP : 1; /!< [3] Swap /
mbed_official	324:406fd2029f23	330	uint8_t ERSSUSP : 1; /!< [4] Erase Suspend /
mbed_official	324:406fd2029f23	331	uint8_t ERSAREQ : 1; /!< [5] Erase All Request /
mbed_official	324:406fd2029f23	332	uint8_t RDCOLLIE : 1; /*!< [6] Read Collision Error Interrupt Enable
mbed_official	324:406fd2029f23	333	* */
mbed_official	324:406fd2029f23	334	uint8_t CCIE : 1; /!< [7] Command Complete Interrupt Enable /
mbed_official	324:406fd2029f23	335	} B;
mbed_official	324:406fd2029f23	336	} hw_ftfe_fcnfg_t;
mbed_official	324:406fd2029f23	337
mbed_official	324:406fd2029f23	338	/*!
mbed_official	324:406fd2029f23	339	* @name Constants and macros for entire FTFE_FCNFG register
mbed_official	324:406fd2029f23	340	*/
mbed_official	324:406fd2029f23	341	/@{/
mbed_official	324:406fd2029f23	342	#define HW_FTFE_FCNFG_ADDR(x) ((x) + 0x1U)
mbed_official	324:406fd2029f23	343
mbed_official	324:406fd2029f23	344	#define HW_FTFE_FCNFG(x) ((__IO hw_ftfe_fcnfg_t ) HW_FTFE_FCNFG_ADDR(x))
mbed_official	324:406fd2029f23	345	#define HW_FTFE_FCNFG_RD(x) (HW_FTFE_FCNFG(x).U)
mbed_official	324:406fd2029f23	346	#define HW_FTFE_FCNFG_WR(x, v) (HW_FTFE_FCNFG(x).U = (v))
mbed_official	324:406fd2029f23	347	#define HW_FTFE_FCNFG_SET(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) \| (v)))
mbed_official	324:406fd2029f23	348	#define HW_FTFE_FCNFG_CLR(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	349	#define HW_FTFE_FCNFG_TOG(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	350	/@}/
mbed_official	324:406fd2029f23	351
mbed_official	324:406fd2029f23	352	/*
mbed_official	324:406fd2029f23	353	* Constants & macros for individual FTFE_FCNFG bitfields
mbed_official	324:406fd2029f23	354	*/
mbed_official	324:406fd2029f23	355
mbed_official	324:406fd2029f23	356	/*!
mbed_official	324:406fd2029f23	357	* @name Register FTFE_FCNFG, field EEERDY[0] (RO)
mbed_official	324:406fd2029f23	358	*
mbed_official	324:406fd2029f23	359	* For devices with FlexNVM: This flag indicates if the EEPROM backup data has
mbed_official	324:406fd2029f23	360	* been copied to the FlexRAM and is therefore available for read access. During
mbed_official	324:406fd2029f23	361	* the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
mbed_official	324:406fd2029f23	362	* the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
mbed_official	324:406fd2029f23	363	* This bit is reserved.
mbed_official	324:406fd2029f23	364	*
mbed_official	324:406fd2029f23	365	* Values:
mbed_official	324:406fd2029f23	366	* - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
mbed_official	324:406fd2029f23	367	* - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
mbed_official	324:406fd2029f23	368	* where: reads from the FlexRAM return data previously written to the FlexRAM
mbed_official	324:406fd2029f23	369	* in EEPROM mode and writes launch an EEPROM operation to store the written
mbed_official	324:406fd2029f23	370	* data in the FlexRAM and EEPROM backup.
mbed_official	324:406fd2029f23	371	*/
mbed_official	324:406fd2029f23	372	/@{/
mbed_official	324:406fd2029f23	373	#define BP_FTFE_FCNFG_EEERDY (0U) /!< Bit position for FTFE_FCNFG_EEERDY. /
mbed_official	324:406fd2029f23	374	#define BM_FTFE_FCNFG_EEERDY (0x01U) /!< Bit mask for FTFE_FCNFG_EEERDY. /
mbed_official	324:406fd2029f23	375	#define BS_FTFE_FCNFG_EEERDY (1U) /!< Bit field size in bits for FTFE_FCNFG_EEERDY. /
mbed_official	324:406fd2029f23	376
mbed_official	324:406fd2029f23	377	/! @brief Read current value of the FTFE_FCNFG_EEERDY field. /
mbed_official	324:406fd2029f23	378	#define BR_FTFE_FCNFG_EEERDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_EEERDY))
mbed_official	324:406fd2029f23	379	/@}/
mbed_official	324:406fd2029f23	380
mbed_official	324:406fd2029f23	381	/*!
mbed_official	324:406fd2029f23	382	* @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
mbed_official	324:406fd2029f23	383	*
mbed_official	324:406fd2029f23	384	* This flag indicates the current status of the FlexRAM/ programming
mbed_official	324:406fd2029f23	385	* acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
mbed_official	324:406fd2029f23	386	* controlled by the Set FlexRAM Function command. During the reset sequence, the
mbed_official	324:406fd2029f23	387	* RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
mbed_official	324:406fd2029f23	388	* be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
mbed_official	324:406fd2029f23	389	* cleared if the Program Partition command is run to partition the FlexNVM block
mbed_official	324:406fd2029f23	390	* for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
mbed_official	324:406fd2029f23	391	* command or execution of the erase-all operation triggered external to the FTFE.
mbed_official	324:406fd2029f23	392	* For devices without FlexNVM: This bit should always be set.
mbed_official	324:406fd2029f23	393	*
mbed_official	324:406fd2029f23	394	* Values:
mbed_official	324:406fd2029f23	395	* - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
mbed_official	324:406fd2029f23	396	* access. For devices without FlexNVM: Programming acceleration RAM is not
mbed_official	324:406fd2029f23	397	* available.
mbed_official	324:406fd2029f23	398	* - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
mbed_official	324:406fd2029f23	399	* writes to the FlexRAM do not trigger EEPROM operations. For devices
mbed_official	324:406fd2029f23	400	* without FlexNVM: Programming acceleration RAM is available.
mbed_official	324:406fd2029f23	401	*/
mbed_official	324:406fd2029f23	402	/@{/
mbed_official	324:406fd2029f23	403	#define BP_FTFE_FCNFG_RAMRDY (1U) /!< Bit position for FTFE_FCNFG_RAMRDY. /
mbed_official	324:406fd2029f23	404	#define BM_FTFE_FCNFG_RAMRDY (0x02U) /!< Bit mask for FTFE_FCNFG_RAMRDY. /
mbed_official	324:406fd2029f23	405	#define BS_FTFE_FCNFG_RAMRDY (1U) /!< Bit field size in bits for FTFE_FCNFG_RAMRDY. /
mbed_official	324:406fd2029f23	406
mbed_official	324:406fd2029f23	407	/! @brief Read current value of the FTFE_FCNFG_RAMRDY field. /
mbed_official	324:406fd2029f23	408	#define BR_FTFE_FCNFG_RAMRDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RAMRDY))
mbed_official	324:406fd2029f23	409	/@}/
mbed_official	324:406fd2029f23	410
mbed_official	324:406fd2029f23	411	/*!
mbed_official	324:406fd2029f23	412	* @name Register FTFE_FCNFG, field PFLSH[2] (RO)
mbed_official	324:406fd2029f23	413	*
mbed_official	324:406fd2029f23	414	* Values:
mbed_official	324:406fd2029f23	415	* - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
mbed_official	324:406fd2029f23	416	* blocks and two FlexNVM blocks For devices with program flash only:
mbed_official	324:406fd2029f23	417	* Reserved
mbed_official	324:406fd2029f23	418	* - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
mbed_official	324:406fd2029f23	419	* FTFE configuration supports four program flash blocks
mbed_official	324:406fd2029f23	420	*/
mbed_official	324:406fd2029f23	421	/@{/
mbed_official	324:406fd2029f23	422	#define BP_FTFE_FCNFG_PFLSH (2U) /!< Bit position for FTFE_FCNFG_PFLSH. /
mbed_official	324:406fd2029f23	423	#define BM_FTFE_FCNFG_PFLSH (0x04U) /!< Bit mask for FTFE_FCNFG_PFLSH. /
mbed_official	324:406fd2029f23	424	#define BS_FTFE_FCNFG_PFLSH (1U) /!< Bit field size in bits for FTFE_FCNFG_PFLSH. /
mbed_official	324:406fd2029f23	425
mbed_official	324:406fd2029f23	426	/! @brief Read current value of the FTFE_FCNFG_PFLSH field. /
mbed_official	324:406fd2029f23	427	#define BR_FTFE_FCNFG_PFLSH(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_PFLSH))
mbed_official	324:406fd2029f23	428	/@}/
mbed_official	324:406fd2029f23	429
mbed_official	324:406fd2029f23	430	/*!
mbed_official	324:406fd2029f23	431	* @name Register FTFE_FCNFG, field SWAP[3] (RO)
mbed_official	324:406fd2029f23	432	*
mbed_official	324:406fd2029f23	433	* The SWAP flag indicates which half of the program flash space is located at
mbed_official	324:406fd2029f23	434	* relative address 0x0000. The state of the SWAP flag is set by the FTFE during
mbed_official	324:406fd2029f23	435	* the reset sequence. See for information on swap management.
mbed_official	324:406fd2029f23	436	*
mbed_official	324:406fd2029f23	437	* Values:
mbed_official	324:406fd2029f23	438	* - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
mbed_official	324:406fd2029f23	439	* address 0x0000 For devices with program flash only: Program flash 0 block
mbed_official	324:406fd2029f23	440	* is located at relative address 0x0000
mbed_official	324:406fd2029f23	441	* - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
mbed_official	324:406fd2029f23	442	* Program flash 1 block is located at relative address 0x0000
mbed_official	324:406fd2029f23	443	*/
mbed_official	324:406fd2029f23	444	/@{/
mbed_official	324:406fd2029f23	445	#define BP_FTFE_FCNFG_SWAP (3U) /!< Bit position for FTFE_FCNFG_SWAP. /
mbed_official	324:406fd2029f23	446	#define BM_FTFE_FCNFG_SWAP (0x08U) /!< Bit mask for FTFE_FCNFG_SWAP. /
mbed_official	324:406fd2029f23	447	#define BS_FTFE_FCNFG_SWAP (1U) /!< Bit field size in bits for FTFE_FCNFG_SWAP. /
mbed_official	324:406fd2029f23	448
mbed_official	324:406fd2029f23	449	/! @brief Read current value of the FTFE_FCNFG_SWAP field. /
mbed_official	324:406fd2029f23	450	#define BR_FTFE_FCNFG_SWAP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_SWAP))
mbed_official	324:406fd2029f23	451	/@}/
mbed_official	324:406fd2029f23	452
mbed_official	324:406fd2029f23	453	/*!
mbed_official	324:406fd2029f23	454	* @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
mbed_official	324:406fd2029f23	455	*
mbed_official	324:406fd2029f23	456	* The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
mbed_official	324:406fd2029f23	457	* command while it is executing.
mbed_official	324:406fd2029f23	458	*
mbed_official	324:406fd2029f23	459	* Values:
mbed_official	324:406fd2029f23	460	* - 0 - No suspend requested
mbed_official	324:406fd2029f23	461	* - 1 - Suspend the current Erase Flash Sector command execution.
mbed_official	324:406fd2029f23	462	*/
mbed_official	324:406fd2029f23	463	/@{/
mbed_official	324:406fd2029f23	464	#define BP_FTFE_FCNFG_ERSSUSP (4U) /!< Bit position for FTFE_FCNFG_ERSSUSP. /
mbed_official	324:406fd2029f23	465	#define BM_FTFE_FCNFG_ERSSUSP (0x10U) /!< Bit mask for FTFE_FCNFG_ERSSUSP. /
mbed_official	324:406fd2029f23	466	#define BS_FTFE_FCNFG_ERSSUSP (1U) /!< Bit field size in bits for FTFE_FCNFG_ERSSUSP. /
mbed_official	324:406fd2029f23	467
mbed_official	324:406fd2029f23	468	/! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. /
mbed_official	324:406fd2029f23	469	#define BR_FTFE_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP))
mbed_official	324:406fd2029f23	470
mbed_official	324:406fd2029f23	471	/! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP. /
mbed_official	324:406fd2029f23	472	#define BF_FTFE_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_ERSSUSP) & BM_FTFE_FCNFG_ERSSUSP)
mbed_official	324:406fd2029f23	473
mbed_official	324:406fd2029f23	474	/! @brief Set the ERSSUSP field to a new value. /
mbed_official	324:406fd2029f23	475	#define BW_FTFE_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP) = (v))
mbed_official	324:406fd2029f23	476	/@}/
mbed_official	324:406fd2029f23	477
mbed_official	324:406fd2029f23	478	/*!
mbed_official	324:406fd2029f23	479	* @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
mbed_official	324:406fd2029f23	480	*
mbed_official	324:406fd2029f23	481	* This bit issues a request to the memory controller to execute the Erase All
mbed_official	324:406fd2029f23	482	* Blocks command and release security. ERSAREQ is not directly writable but is
mbed_official	324:406fd2029f23	483	* under indirect user control. Refer to the device's Chip Configuration details on
mbed_official	324:406fd2029f23	484	* how to request this command. The ERSAREQ bit sets when an erase all request
mbed_official	324:406fd2029f23	485	* is triggered external to the FTFE and CCIF is set (no command is currently
mbed_official	324:406fd2029f23	486	* being executed). ERSAREQ is cleared by the FTFE when the operation completes.
mbed_official	324:406fd2029f23	487	*
mbed_official	324:406fd2029f23	488	* Values:
mbed_official	324:406fd2029f23	489	* - 0 - No request or request complete
mbed_official	324:406fd2029f23	490	* - 1 - Request to: run the Erase All Blocks command, verify the erased state,
mbed_official	324:406fd2029f23	491	* program the security byte in the Flash Configuration Field to the unsecure
mbed_official	324:406fd2029f23	492	* state, and release MCU security by setting the FSEC[SEC] field to the
mbed_official	324:406fd2029f23	493	* unsecure state.
mbed_official	324:406fd2029f23	494	*/
mbed_official	324:406fd2029f23	495	/@{/
mbed_official	324:406fd2029f23	496	#define BP_FTFE_FCNFG_ERSAREQ (5U) /!< Bit position for FTFE_FCNFG_ERSAREQ. /
mbed_official	324:406fd2029f23	497	#define BM_FTFE_FCNFG_ERSAREQ (0x20U) /!< Bit mask for FTFE_FCNFG_ERSAREQ. /
mbed_official	324:406fd2029f23	498	#define BS_FTFE_FCNFG_ERSAREQ (1U) /!< Bit field size in bits for FTFE_FCNFG_ERSAREQ. /
mbed_official	324:406fd2029f23	499
mbed_official	324:406fd2029f23	500	/! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. /
mbed_official	324:406fd2029f23	501	#define BR_FTFE_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSAREQ))
mbed_official	324:406fd2029f23	502	/@}/
mbed_official	324:406fd2029f23	503
mbed_official	324:406fd2029f23	504	/*!
mbed_official	324:406fd2029f23	505	* @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
mbed_official	324:406fd2029f23	506	*
mbed_official	324:406fd2029f23	507	* The RDCOLLIE bit controls interrupt generation when an FTFE read collision
mbed_official	324:406fd2029f23	508	* error occurs.
mbed_official	324:406fd2029f23	509	*
mbed_official	324:406fd2029f23	510	* Values:
mbed_official	324:406fd2029f23	511	* - 0 - Read collision error interrupt disabled
mbed_official	324:406fd2029f23	512	* - 1 - Read collision error interrupt enabled. An interrupt request is
mbed_official	324:406fd2029f23	513	* generated whenever an FTFE read collision error is detected (see the description
mbed_official	324:406fd2029f23	514	* of FSTAT[RDCOLERR]).
mbed_official	324:406fd2029f23	515	*/
mbed_official	324:406fd2029f23	516	/@{/
mbed_official	324:406fd2029f23	517	#define BP_FTFE_FCNFG_RDCOLLIE (6U) /!< Bit position for FTFE_FCNFG_RDCOLLIE. /
mbed_official	324:406fd2029f23	518	#define BM_FTFE_FCNFG_RDCOLLIE (0x40U) /!< Bit mask for FTFE_FCNFG_RDCOLLIE. /
mbed_official	324:406fd2029f23	519	#define BS_FTFE_FCNFG_RDCOLLIE (1U) /!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE. /
mbed_official	324:406fd2029f23	520
mbed_official	324:406fd2029f23	521	/! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. /
mbed_official	324:406fd2029f23	522	#define BR_FTFE_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE))
mbed_official	324:406fd2029f23	523
mbed_official	324:406fd2029f23	524	/! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE. /
mbed_official	324:406fd2029f23	525	#define BF_FTFE_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_RDCOLLIE) & BM_FTFE_FCNFG_RDCOLLIE)
mbed_official	324:406fd2029f23	526
mbed_official	324:406fd2029f23	527	/! @brief Set the RDCOLLIE field to a new value. /
mbed_official	324:406fd2029f23	528	#define BW_FTFE_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE) = (v))
mbed_official	324:406fd2029f23	529	/@}/
mbed_official	324:406fd2029f23	530
mbed_official	324:406fd2029f23	531	/*!
mbed_official	324:406fd2029f23	532	* @name Register FTFE_FCNFG, field CCIE[7] (RW)
mbed_official	324:406fd2029f23	533	*
mbed_official	324:406fd2029f23	534	* The CCIE bit controls interrupt generation when an FTFE command completes.
mbed_official	324:406fd2029f23	535	*
mbed_official	324:406fd2029f23	536	* Values:
mbed_official	324:406fd2029f23	537	* - 0 - Command complete interrupt disabled
mbed_official	324:406fd2029f23	538	* - 1 - Command complete interrupt enabled. An interrupt request is generated
mbed_official	324:406fd2029f23	539	* whenever the FSTAT[CCIF] flag is set.
mbed_official	324:406fd2029f23	540	*/
mbed_official	324:406fd2029f23	541	/@{/
mbed_official	324:406fd2029f23	542	#define BP_FTFE_FCNFG_CCIE (7U) /!< Bit position for FTFE_FCNFG_CCIE. /
mbed_official	324:406fd2029f23	543	#define BM_FTFE_FCNFG_CCIE (0x80U) /!< Bit mask for FTFE_FCNFG_CCIE. /
mbed_official	324:406fd2029f23	544	#define BS_FTFE_FCNFG_CCIE (1U) /!< Bit field size in bits for FTFE_FCNFG_CCIE. /
mbed_official	324:406fd2029f23	545
mbed_official	324:406fd2029f23	546	/! @brief Read current value of the FTFE_FCNFG_CCIE field. /
mbed_official	324:406fd2029f23	547	#define BR_FTFE_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE))
mbed_official	324:406fd2029f23	548
mbed_official	324:406fd2029f23	549	/! @brief Format value for bitfield FTFE_FCNFG_CCIE. /
mbed_official	324:406fd2029f23	550	#define BF_FTFE_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_CCIE) & BM_FTFE_FCNFG_CCIE)
mbed_official	324:406fd2029f23	551
mbed_official	324:406fd2029f23	552	/! @brief Set the CCIE field to a new value. /
mbed_official	324:406fd2029f23	553	#define BW_FTFE_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE) = (v))
mbed_official	324:406fd2029f23	554	/@}/
mbed_official	324:406fd2029f23	555
mbed_official	324:406fd2029f23	556	/*******************************************************************************
mbed_official	324:406fd2029f23	557	* HW_FTFE_FSEC - Flash Security Register
mbed_official	324:406fd2029f23	558	******************************************************************************/
mbed_official	324:406fd2029f23	559
mbed_official	324:406fd2029f23	560	/*!
mbed_official	324:406fd2029f23	561	* @brief HW_FTFE_FSEC - Flash Security Register (RO)
mbed_official	324:406fd2029f23	562	*
mbed_official	324:406fd2029f23	563	* Reset value: 0x00U
mbed_official	324:406fd2029f23	564	*
mbed_official	324:406fd2029f23	565	* This read-only register holds all bits associated with the security of the
mbed_official	324:406fd2029f23	566	* MCU and FTFE module. During the reset sequence, the register is loaded with the
mbed_official	324:406fd2029f23	567	* contents of the flash security byte in the Flash Configuration Field located
mbed_official	324:406fd2029f23	568	* in program flash memory. The Flash basis for the values is signified by X in
mbed_official	324:406fd2029f23	569	* the reset value.
mbed_official	324:406fd2029f23	570	*/
mbed_official	324:406fd2029f23	571	typedef union _hw_ftfe_fsec
mbed_official	324:406fd2029f23	572	{
mbed_official	324:406fd2029f23	573	uint8_t U;
mbed_official	324:406fd2029f23	574	struct _hw_ftfe_fsec_bitfields
mbed_official	324:406fd2029f23	575	{
mbed_official	324:406fd2029f23	576	uint8_t SEC : 2; /!< [1:0] Flash Security /
mbed_official	324:406fd2029f23	577	uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code
mbed_official	324:406fd2029f23	578	* */
mbed_official	324:406fd2029f23	579	uint8_t MEEN : 2; /!< [5:4] Mass Erase Enable Bits /
mbed_official	324:406fd2029f23	580	uint8_t KEYEN : 2; /!< [7:6] Backdoor Key Security Enable /
mbed_official	324:406fd2029f23	581	} B;
mbed_official	324:406fd2029f23	582	} hw_ftfe_fsec_t;
mbed_official	324:406fd2029f23	583
mbed_official	324:406fd2029f23	584	/*!
mbed_official	324:406fd2029f23	585	* @name Constants and macros for entire FTFE_FSEC register
mbed_official	324:406fd2029f23	586	*/
mbed_official	324:406fd2029f23	587	/@{/
mbed_official	324:406fd2029f23	588	#define HW_FTFE_FSEC_ADDR(x) ((x) + 0x2U)
mbed_official	324:406fd2029f23	589
mbed_official	324:406fd2029f23	590	#define HW_FTFE_FSEC(x) ((__I hw_ftfe_fsec_t ) HW_FTFE_FSEC_ADDR(x))
mbed_official	324:406fd2029f23	591	#define HW_FTFE_FSEC_RD(x) (HW_FTFE_FSEC(x).U)
mbed_official	324:406fd2029f23	592	/@}/
mbed_official	324:406fd2029f23	593
mbed_official	324:406fd2029f23	594	/*
mbed_official	324:406fd2029f23	595	* Constants & macros for individual FTFE_FSEC bitfields
mbed_official	324:406fd2029f23	596	*/
mbed_official	324:406fd2029f23	597
mbed_official	324:406fd2029f23	598	/*!
mbed_official	324:406fd2029f23	599	* @name Register FTFE_FSEC, field SEC[1:0] (RO)
mbed_official	324:406fd2029f23	600	*
mbed_official	324:406fd2029f23	601	* These bits define the security state of the MCU. In the secure state, the MCU
mbed_official	324:406fd2029f23	602	* limits access to FTFE module resources. The limitations are defined per
mbed_official	324:406fd2029f23	603	* device and are detailed in the Chip Configuration details. If the FTFE module is
mbed_official	324:406fd2029f23	604	* unsecured using backdoor key access, the SEC bits are forced to 10b.
mbed_official	324:406fd2029f23	605	*
mbed_official	324:406fd2029f23	606	* Values:
mbed_official	324:406fd2029f23	607	* - 00 - MCU security status is secure
mbed_official	324:406fd2029f23	608	* - 01 - MCU security status is secure
mbed_official	324:406fd2029f23	609	* - 10 - MCU security status is unsecure (The standard shipping condition of
mbed_official	324:406fd2029f23	610	* the FTFE is unsecure.)
mbed_official	324:406fd2029f23	611	* - 11 - MCU security status is secure
mbed_official	324:406fd2029f23	612	*/
mbed_official	324:406fd2029f23	613	/@{/
mbed_official	324:406fd2029f23	614	#define BP_FTFE_FSEC_SEC (0U) /!< Bit position for FTFE_FSEC_SEC. /
mbed_official	324:406fd2029f23	615	#define BM_FTFE_FSEC_SEC (0x03U) /!< Bit mask for FTFE_FSEC_SEC. /
mbed_official	324:406fd2029f23	616	#define BS_FTFE_FSEC_SEC (2U) /!< Bit field size in bits for FTFE_FSEC_SEC. /
mbed_official	324:406fd2029f23	617
mbed_official	324:406fd2029f23	618	/! @brief Read current value of the FTFE_FSEC_SEC field. /
mbed_official	324:406fd2029f23	619	#define BR_FTFE_FSEC_SEC(x) (HW_FTFE_FSEC(x).B.SEC)
mbed_official	324:406fd2029f23	620	/@}/
mbed_official	324:406fd2029f23	621
mbed_official	324:406fd2029f23	622	/*!
mbed_official	324:406fd2029f23	623	* @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
mbed_official	324:406fd2029f23	624	*
mbed_official	324:406fd2029f23	625	* These bits enable or disable access to the flash memory contents during
mbed_official	324:406fd2029f23	626	* returned part failure analysis at Freescale. When SEC is secure and FSLACC is
mbed_official	324:406fd2029f23	627	* denied, access to the program flash contents is denied and any failure analysis
mbed_official	324:406fd2029f23	628	* performed by Freescale factory test must begin with a full erase to unsecure the
mbed_official	324:406fd2029f23	629	* part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
mbed_official	324:406fd2029f23	630	* granted), Freescale factory testing has visibility of the current flash
mbed_official	324:406fd2029f23	631	* contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
mbed_official	324:406fd2029f23	632	* secure. When the SEC field is set to unsecure, the FSLACC setting does not
mbed_official	324:406fd2029f23	633	* matter.
mbed_official	324:406fd2029f23	634	*
mbed_official	324:406fd2029f23	635	* Values:
mbed_official	324:406fd2029f23	636	* - 00 - Freescale factory access granted
mbed_official	324:406fd2029f23	637	* - 01 - Freescale factory access denied
mbed_official	324:406fd2029f23	638	* - 10 - Freescale factory access denied
mbed_official	324:406fd2029f23	639	* - 11 - Freescale factory access granted
mbed_official	324:406fd2029f23	640	*/
mbed_official	324:406fd2029f23	641	/@{/
mbed_official	324:406fd2029f23	642	#define BP_FTFE_FSEC_FSLACC (2U) /!< Bit position for FTFE_FSEC_FSLACC. /
mbed_official	324:406fd2029f23	643	#define BM_FTFE_FSEC_FSLACC (0x0CU) /!< Bit mask for FTFE_FSEC_FSLACC. /
mbed_official	324:406fd2029f23	644	#define BS_FTFE_FSEC_FSLACC (2U) /!< Bit field size in bits for FTFE_FSEC_FSLACC. /
mbed_official	324:406fd2029f23	645
mbed_official	324:406fd2029f23	646	/! @brief Read current value of the FTFE_FSEC_FSLACC field. /
mbed_official	324:406fd2029f23	647	#define BR_FTFE_FSEC_FSLACC(x) (HW_FTFE_FSEC(x).B.FSLACC)
mbed_official	324:406fd2029f23	648	/@}/
mbed_official	324:406fd2029f23	649
mbed_official	324:406fd2029f23	650	/*!
mbed_official	324:406fd2029f23	651	* @name Register FTFE_FSEC, field MEEN[5:4] (RO)
mbed_official	324:406fd2029f23	652	*
mbed_official	324:406fd2029f23	653	* Enables and disables mass erase capability of the FTFE module. The state of
mbed_official	324:406fd2029f23	654	* the MEEN bits is only relevant when the SEC bits are set to secure outside of
mbed_official	324:406fd2029f23	655	* NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
mbed_official	324:406fd2029f23	656	* not matter.
mbed_official	324:406fd2029f23	657	*
mbed_official	324:406fd2029f23	658	* Values:
mbed_official	324:406fd2029f23	659	* - 00 - Mass erase is enabled
mbed_official	324:406fd2029f23	660	* - 01 - Mass erase is enabled
mbed_official	324:406fd2029f23	661	* - 10 - Mass erase is disabled
mbed_official	324:406fd2029f23	662	* - 11 - Mass erase is enabled
mbed_official	324:406fd2029f23	663	*/
mbed_official	324:406fd2029f23	664	/@{/
mbed_official	324:406fd2029f23	665	#define BP_FTFE_FSEC_MEEN (4U) /!< Bit position for FTFE_FSEC_MEEN. /
mbed_official	324:406fd2029f23	666	#define BM_FTFE_FSEC_MEEN (0x30U) /!< Bit mask for FTFE_FSEC_MEEN. /
mbed_official	324:406fd2029f23	667	#define BS_FTFE_FSEC_MEEN (2U) /!< Bit field size in bits for FTFE_FSEC_MEEN. /
mbed_official	324:406fd2029f23	668
mbed_official	324:406fd2029f23	669	/! @brief Read current value of the FTFE_FSEC_MEEN field. /
mbed_official	324:406fd2029f23	670	#define BR_FTFE_FSEC_MEEN(x) (HW_FTFE_FSEC(x).B.MEEN)
mbed_official	324:406fd2029f23	671	/@}/
mbed_official	324:406fd2029f23	672
mbed_official	324:406fd2029f23	673	/*!
mbed_official	324:406fd2029f23	674	* @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
mbed_official	324:406fd2029f23	675	*
mbed_official	324:406fd2029f23	676	* These bits enable and disable backdoor key access to the FTFE module.
mbed_official	324:406fd2029f23	677	*
mbed_official	324:406fd2029f23	678	* Values:
mbed_official	324:406fd2029f23	679	* - 00 - Backdoor key access disabled
mbed_official	324:406fd2029f23	680	* - 01 - Backdoor key access disabled (preferred KEYEN state to disable
mbed_official	324:406fd2029f23	681	* backdoor key access)
mbed_official	324:406fd2029f23	682	* - 10 - Backdoor key access enabled
mbed_official	324:406fd2029f23	683	* - 11 - Backdoor key access disabled
mbed_official	324:406fd2029f23	684	*/
mbed_official	324:406fd2029f23	685	/@{/
mbed_official	324:406fd2029f23	686	#define BP_FTFE_FSEC_KEYEN (6U) /!< Bit position for FTFE_FSEC_KEYEN. /
mbed_official	324:406fd2029f23	687	#define BM_FTFE_FSEC_KEYEN (0xC0U) /!< Bit mask for FTFE_FSEC_KEYEN. /
mbed_official	324:406fd2029f23	688	#define BS_FTFE_FSEC_KEYEN (2U) /!< Bit field size in bits for FTFE_FSEC_KEYEN. /
mbed_official	324:406fd2029f23	689
mbed_official	324:406fd2029f23	690	/! @brief Read current value of the FTFE_FSEC_KEYEN field. /
mbed_official	324:406fd2029f23	691	#define BR_FTFE_FSEC_KEYEN(x) (HW_FTFE_FSEC(x).B.KEYEN)
mbed_official	324:406fd2029f23	692	/@}/
mbed_official	324:406fd2029f23	693
mbed_official	324:406fd2029f23	694	/*******************************************************************************
mbed_official	324:406fd2029f23	695	* HW_FTFE_FOPT - Flash Option Register
mbed_official	324:406fd2029f23	696	******************************************************************************/
mbed_official	324:406fd2029f23	697
mbed_official	324:406fd2029f23	698	/*!
mbed_official	324:406fd2029f23	699	* @brief HW_FTFE_FOPT - Flash Option Register (RO)
mbed_official	324:406fd2029f23	700	*
mbed_official	324:406fd2029f23	701	* Reset value: 0x00U
mbed_official	324:406fd2029f23	702	*
mbed_official	324:406fd2029f23	703	* The flash option register allows the MCU to customize its operations by
mbed_official	324:406fd2029f23	704	* examining the state of these read-only bits, which are loaded from NVM at reset.
mbed_official	324:406fd2029f23	705	* The function of the bits is defined in the device's Chip Configuration details.
mbed_official	324:406fd2029f23	706	* All bits in the register are read-only. During the reset sequence, the
mbed_official	324:406fd2029f23	707	* register is loaded from the flash nonvolatile option byte in the Flash Configuration
mbed_official	324:406fd2029f23	708	* Field located in program flash memory. The flash basis for the values is
mbed_official	324:406fd2029f23	709	* signified by X in the reset value.
mbed_official	324:406fd2029f23	710	*/
mbed_official	324:406fd2029f23	711	typedef union _hw_ftfe_fopt
mbed_official	324:406fd2029f23	712	{
mbed_official	324:406fd2029f23	713	uint8_t U;
mbed_official	324:406fd2029f23	714	struct _hw_ftfe_fopt_bitfields
mbed_official	324:406fd2029f23	715	{
mbed_official	324:406fd2029f23	716	uint8_t OPT : 8; /!< [7:0] Nonvolatile Option /
mbed_official	324:406fd2029f23	717	} B;
mbed_official	324:406fd2029f23	718	} hw_ftfe_fopt_t;
mbed_official	324:406fd2029f23	719
mbed_official	324:406fd2029f23	720	/*!
mbed_official	324:406fd2029f23	721	* @name Constants and macros for entire FTFE_FOPT register
mbed_official	324:406fd2029f23	722	*/
mbed_official	324:406fd2029f23	723	/@{/
mbed_official	324:406fd2029f23	724	#define HW_FTFE_FOPT_ADDR(x) ((x) + 0x3U)
mbed_official	324:406fd2029f23	725
mbed_official	324:406fd2029f23	726	#define HW_FTFE_FOPT(x) ((__I hw_ftfe_fopt_t ) HW_FTFE_FOPT_ADDR(x))
mbed_official	324:406fd2029f23	727	#define HW_FTFE_FOPT_RD(x) (HW_FTFE_FOPT(x).U)
mbed_official	324:406fd2029f23	728	/@}/
mbed_official	324:406fd2029f23	729
mbed_official	324:406fd2029f23	730	/*
mbed_official	324:406fd2029f23	731	* Constants & macros for individual FTFE_FOPT bitfields
mbed_official	324:406fd2029f23	732	*/
mbed_official	324:406fd2029f23	733
mbed_official	324:406fd2029f23	734	/*!
mbed_official	324:406fd2029f23	735	* @name Register FTFE_FOPT, field OPT[7:0] (RO)
mbed_official	324:406fd2029f23	736	*
mbed_official	324:406fd2029f23	737	* These bits are loaded from flash to this register at reset. Refer to the
mbed_official	324:406fd2029f23	738	* device's Chip Configuration details for the definition and use of these bits.
mbed_official	324:406fd2029f23	739	*/
mbed_official	324:406fd2029f23	740	/@{/
mbed_official	324:406fd2029f23	741	#define BP_FTFE_FOPT_OPT (0U) /!< Bit position for FTFE_FOPT_OPT. /
mbed_official	324:406fd2029f23	742	#define BM_FTFE_FOPT_OPT (0xFFU) /!< Bit mask for FTFE_FOPT_OPT. /
mbed_official	324:406fd2029f23	743	#define BS_FTFE_FOPT_OPT (8U) /!< Bit field size in bits for FTFE_FOPT_OPT. /
mbed_official	324:406fd2029f23	744
mbed_official	324:406fd2029f23	745	/! @brief Read current value of the FTFE_FOPT_OPT field. /
mbed_official	324:406fd2029f23	746	#define BR_FTFE_FOPT_OPT(x) (HW_FTFE_FOPT(x).U)
mbed_official	324:406fd2029f23	747	/@}/
mbed_official	324:406fd2029f23	748
mbed_official	324:406fd2029f23	749	/*******************************************************************************
mbed_official	324:406fd2029f23	750	* HW_FTFE_FCCOB3 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	751	******************************************************************************/
mbed_official	324:406fd2029f23	752
mbed_official	324:406fd2029f23	753	/*!
mbed_official	324:406fd2029f23	754	* @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	755	*
mbed_official	324:406fd2029f23	756	* Reset value: 0x00U
mbed_official	324:406fd2029f23	757	*
mbed_official	324:406fd2029f23	758	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	759	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	760	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	761	*/
mbed_official	324:406fd2029f23	762	typedef union _hw_ftfe_fccob3
mbed_official	324:406fd2029f23	763	{
mbed_official	324:406fd2029f23	764	uint8_t U;
mbed_official	324:406fd2029f23	765	struct _hw_ftfe_fccob3_bitfields
mbed_official	324:406fd2029f23	766	{
mbed_official	324:406fd2029f23	767	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	768	} B;
mbed_official	324:406fd2029f23	769	} hw_ftfe_fccob3_t;
mbed_official	324:406fd2029f23	770
mbed_official	324:406fd2029f23	771	/*!
mbed_official	324:406fd2029f23	772	* @name Constants and macros for entire FTFE_FCCOB3 register
mbed_official	324:406fd2029f23	773	*/
mbed_official	324:406fd2029f23	774	/@{/
mbed_official	324:406fd2029f23	775	#define HW_FTFE_FCCOB3_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	776
mbed_official	324:406fd2029f23	777	#define HW_FTFE_FCCOB3(x) ((__IO hw_ftfe_fccob3_t ) HW_FTFE_FCCOB3_ADDR(x))
mbed_official	324:406fd2029f23	778	#define HW_FTFE_FCCOB3_RD(x) (HW_FTFE_FCCOB3(x).U)
mbed_official	324:406fd2029f23	779	#define HW_FTFE_FCCOB3_WR(x, v) (HW_FTFE_FCCOB3(x).U = (v))
mbed_official	324:406fd2029f23	780	#define HW_FTFE_FCCOB3_SET(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) \| (v)))
mbed_official	324:406fd2029f23	781	#define HW_FTFE_FCCOB3_CLR(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	782	#define HW_FTFE_FCCOB3_TOG(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	783	/@}/
mbed_official	324:406fd2029f23	784
mbed_official	324:406fd2029f23	785	/*
mbed_official	324:406fd2029f23	786	* Constants & macros for individual FTFE_FCCOB3 bitfields
mbed_official	324:406fd2029f23	787	*/
mbed_official	324:406fd2029f23	788
mbed_official	324:406fd2029f23	789	/*!
mbed_official	324:406fd2029f23	790	* @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	791	*
mbed_official	324:406fd2029f23	792	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	793	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	794	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	795	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	796	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	797	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	798	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	799	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	800	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	801	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	802	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	803	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	804	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	805	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	806	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	807	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	808	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	809	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	810	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	811	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	812	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	813	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	814	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	815	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	816	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	817	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	818	*/
mbed_official	324:406fd2029f23	819	/@{/
mbed_official	324:406fd2029f23	820	#define BP_FTFE_FCCOB3_CCOBn (0U) /!< Bit position for FTFE_FCCOB3_CCOBn. /
mbed_official	324:406fd2029f23	821	#define BM_FTFE_FCCOB3_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB3_CCOBn. /
mbed_official	324:406fd2029f23	822	#define BS_FTFE_FCCOB3_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB3_CCOBn. /
mbed_official	324:406fd2029f23	823
mbed_official	324:406fd2029f23	824	/! @brief Read current value of the FTFE_FCCOB3_CCOBn field. /
mbed_official	324:406fd2029f23	825	#define BR_FTFE_FCCOB3_CCOBn(x) (HW_FTFE_FCCOB3(x).U)
mbed_official	324:406fd2029f23	826
mbed_official	324:406fd2029f23	827	/! @brief Format value for bitfield FTFE_FCCOB3_CCOBn. /
mbed_official	324:406fd2029f23	828	#define BF_FTFE_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB3_CCOBn) & BM_FTFE_FCCOB3_CCOBn)
mbed_official	324:406fd2029f23	829
mbed_official	324:406fd2029f23	830	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	831	#define BW_FTFE_FCCOB3_CCOBn(x, v) (HW_FTFE_FCCOB3_WR(x, v))
mbed_official	324:406fd2029f23	832	/@}/
mbed_official	324:406fd2029f23	833
mbed_official	324:406fd2029f23	834	/*******************************************************************************
mbed_official	324:406fd2029f23	835	* HW_FTFE_FCCOB2 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	836	******************************************************************************/
mbed_official	324:406fd2029f23	837
mbed_official	324:406fd2029f23	838	/*!
mbed_official	324:406fd2029f23	839	* @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	840	*
mbed_official	324:406fd2029f23	841	* Reset value: 0x00U
mbed_official	324:406fd2029f23	842	*
mbed_official	324:406fd2029f23	843	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	844	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	845	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	846	*/
mbed_official	324:406fd2029f23	847	typedef union _hw_ftfe_fccob2
mbed_official	324:406fd2029f23	848	{
mbed_official	324:406fd2029f23	849	uint8_t U;
mbed_official	324:406fd2029f23	850	struct _hw_ftfe_fccob2_bitfields
mbed_official	324:406fd2029f23	851	{
mbed_official	324:406fd2029f23	852	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	853	} B;
mbed_official	324:406fd2029f23	854	} hw_ftfe_fccob2_t;
mbed_official	324:406fd2029f23	855
mbed_official	324:406fd2029f23	856	/*!
mbed_official	324:406fd2029f23	857	* @name Constants and macros for entire FTFE_FCCOB2 register
mbed_official	324:406fd2029f23	858	*/
mbed_official	324:406fd2029f23	859	/@{/
mbed_official	324:406fd2029f23	860	#define HW_FTFE_FCCOB2_ADDR(x) ((x) + 0x5U)
mbed_official	324:406fd2029f23	861
mbed_official	324:406fd2029f23	862	#define HW_FTFE_FCCOB2(x) ((__IO hw_ftfe_fccob2_t ) HW_FTFE_FCCOB2_ADDR(x))
mbed_official	324:406fd2029f23	863	#define HW_FTFE_FCCOB2_RD(x) (HW_FTFE_FCCOB2(x).U)
mbed_official	324:406fd2029f23	864	#define HW_FTFE_FCCOB2_WR(x, v) (HW_FTFE_FCCOB2(x).U = (v))
mbed_official	324:406fd2029f23	865	#define HW_FTFE_FCCOB2_SET(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	866	#define HW_FTFE_FCCOB2_CLR(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	867	#define HW_FTFE_FCCOB2_TOG(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	868	/@}/
mbed_official	324:406fd2029f23	869
mbed_official	324:406fd2029f23	870	/*
mbed_official	324:406fd2029f23	871	* Constants & macros for individual FTFE_FCCOB2 bitfields
mbed_official	324:406fd2029f23	872	*/
mbed_official	324:406fd2029f23	873
mbed_official	324:406fd2029f23	874	/*!
mbed_official	324:406fd2029f23	875	* @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	876	*
mbed_official	324:406fd2029f23	877	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	878	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	879	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	880	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	881	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	882	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	883	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	884	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	885	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	886	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	887	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	888	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	889	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	890	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	891	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	892	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	893	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	894	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	895	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	896	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	897	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	898	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	899	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	900	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	901	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	902	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	903	*/
mbed_official	324:406fd2029f23	904	/@{/
mbed_official	324:406fd2029f23	905	#define BP_FTFE_FCCOB2_CCOBn (0U) /!< Bit position for FTFE_FCCOB2_CCOBn. /
mbed_official	324:406fd2029f23	906	#define BM_FTFE_FCCOB2_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB2_CCOBn. /
mbed_official	324:406fd2029f23	907	#define BS_FTFE_FCCOB2_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB2_CCOBn. /
mbed_official	324:406fd2029f23	908
mbed_official	324:406fd2029f23	909	/! @brief Read current value of the FTFE_FCCOB2_CCOBn field. /
mbed_official	324:406fd2029f23	910	#define BR_FTFE_FCCOB2_CCOBn(x) (HW_FTFE_FCCOB2(x).U)
mbed_official	324:406fd2029f23	911
mbed_official	324:406fd2029f23	912	/! @brief Format value for bitfield FTFE_FCCOB2_CCOBn. /
mbed_official	324:406fd2029f23	913	#define BF_FTFE_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB2_CCOBn) & BM_FTFE_FCCOB2_CCOBn)
mbed_official	324:406fd2029f23	914
mbed_official	324:406fd2029f23	915	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	916	#define BW_FTFE_FCCOB2_CCOBn(x, v) (HW_FTFE_FCCOB2_WR(x, v))
mbed_official	324:406fd2029f23	917	/@}/
mbed_official	324:406fd2029f23	918
mbed_official	324:406fd2029f23	919	/*******************************************************************************
mbed_official	324:406fd2029f23	920	* HW_FTFE_FCCOB1 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	921	******************************************************************************/
mbed_official	324:406fd2029f23	922
mbed_official	324:406fd2029f23	923	/*!
mbed_official	324:406fd2029f23	924	* @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	925	*
mbed_official	324:406fd2029f23	926	* Reset value: 0x00U
mbed_official	324:406fd2029f23	927	*
mbed_official	324:406fd2029f23	928	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	929	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	930	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	931	*/
mbed_official	324:406fd2029f23	932	typedef union _hw_ftfe_fccob1
mbed_official	324:406fd2029f23	933	{
mbed_official	324:406fd2029f23	934	uint8_t U;
mbed_official	324:406fd2029f23	935	struct _hw_ftfe_fccob1_bitfields
mbed_official	324:406fd2029f23	936	{
mbed_official	324:406fd2029f23	937	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	938	} B;
mbed_official	324:406fd2029f23	939	} hw_ftfe_fccob1_t;
mbed_official	324:406fd2029f23	940
mbed_official	324:406fd2029f23	941	/*!
mbed_official	324:406fd2029f23	942	* @name Constants and macros for entire FTFE_FCCOB1 register
mbed_official	324:406fd2029f23	943	*/
mbed_official	324:406fd2029f23	944	/@{/
mbed_official	324:406fd2029f23	945	#define HW_FTFE_FCCOB1_ADDR(x) ((x) + 0x6U)
mbed_official	324:406fd2029f23	946
mbed_official	324:406fd2029f23	947	#define HW_FTFE_FCCOB1(x) ((__IO hw_ftfe_fccob1_t ) HW_FTFE_FCCOB1_ADDR(x))
mbed_official	324:406fd2029f23	948	#define HW_FTFE_FCCOB1_RD(x) (HW_FTFE_FCCOB1(x).U)
mbed_official	324:406fd2029f23	949	#define HW_FTFE_FCCOB1_WR(x, v) (HW_FTFE_FCCOB1(x).U = (v))
mbed_official	324:406fd2029f23	950	#define HW_FTFE_FCCOB1_SET(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	951	#define HW_FTFE_FCCOB1_CLR(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	952	#define HW_FTFE_FCCOB1_TOG(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	953	/@}/
mbed_official	324:406fd2029f23	954
mbed_official	324:406fd2029f23	955	/*
mbed_official	324:406fd2029f23	956	* Constants & macros for individual FTFE_FCCOB1 bitfields
mbed_official	324:406fd2029f23	957	*/
mbed_official	324:406fd2029f23	958
mbed_official	324:406fd2029f23	959	/*!
mbed_official	324:406fd2029f23	960	* @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	961	*
mbed_official	324:406fd2029f23	962	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	963	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	964	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	965	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	966	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	967	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	968	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	969	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	970	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	971	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	972	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	973	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	974	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	975	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	976	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	977	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	978	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	979	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	980	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	981	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	982	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	983	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	984	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	985	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	986	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	987	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	988	*/
mbed_official	324:406fd2029f23	989	/@{/
mbed_official	324:406fd2029f23	990	#define BP_FTFE_FCCOB1_CCOBn (0U) /!< Bit position for FTFE_FCCOB1_CCOBn. /
mbed_official	324:406fd2029f23	991	#define BM_FTFE_FCCOB1_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB1_CCOBn. /
mbed_official	324:406fd2029f23	992	#define BS_FTFE_FCCOB1_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB1_CCOBn. /
mbed_official	324:406fd2029f23	993
mbed_official	324:406fd2029f23	994	/! @brief Read current value of the FTFE_FCCOB1_CCOBn field. /
mbed_official	324:406fd2029f23	995	#define BR_FTFE_FCCOB1_CCOBn(x) (HW_FTFE_FCCOB1(x).U)
mbed_official	324:406fd2029f23	996
mbed_official	324:406fd2029f23	997	/! @brief Format value for bitfield FTFE_FCCOB1_CCOBn. /
mbed_official	324:406fd2029f23	998	#define BF_FTFE_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB1_CCOBn) & BM_FTFE_FCCOB1_CCOBn)
mbed_official	324:406fd2029f23	999
mbed_official	324:406fd2029f23	1000	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1001	#define BW_FTFE_FCCOB1_CCOBn(x, v) (HW_FTFE_FCCOB1_WR(x, v))
mbed_official	324:406fd2029f23	1002	/@}/
mbed_official	324:406fd2029f23	1003
mbed_official	324:406fd2029f23	1004	/*******************************************************************************
mbed_official	324:406fd2029f23	1005	* HW_FTFE_FCCOB0 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1006	******************************************************************************/
mbed_official	324:406fd2029f23	1007
mbed_official	324:406fd2029f23	1008	/*!
mbed_official	324:406fd2029f23	1009	* @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1010	*
mbed_official	324:406fd2029f23	1011	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1012	*
mbed_official	324:406fd2029f23	1013	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1014	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1015	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1016	*/
mbed_official	324:406fd2029f23	1017	typedef union _hw_ftfe_fccob0
mbed_official	324:406fd2029f23	1018	{
mbed_official	324:406fd2029f23	1019	uint8_t U;
mbed_official	324:406fd2029f23	1020	struct _hw_ftfe_fccob0_bitfields
mbed_official	324:406fd2029f23	1021	{
mbed_official	324:406fd2029f23	1022	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1023	} B;
mbed_official	324:406fd2029f23	1024	} hw_ftfe_fccob0_t;
mbed_official	324:406fd2029f23	1025
mbed_official	324:406fd2029f23	1026	/*!
mbed_official	324:406fd2029f23	1027	* @name Constants and macros for entire FTFE_FCCOB0 register
mbed_official	324:406fd2029f23	1028	*/
mbed_official	324:406fd2029f23	1029	/@{/
mbed_official	324:406fd2029f23	1030	#define HW_FTFE_FCCOB0_ADDR(x) ((x) + 0x7U)
mbed_official	324:406fd2029f23	1031
mbed_official	324:406fd2029f23	1032	#define HW_FTFE_FCCOB0(x) ((__IO hw_ftfe_fccob0_t ) HW_FTFE_FCCOB0_ADDR(x))
mbed_official	324:406fd2029f23	1033	#define HW_FTFE_FCCOB0_RD(x) (HW_FTFE_FCCOB0(x).U)
mbed_official	324:406fd2029f23	1034	#define HW_FTFE_FCCOB0_WR(x, v) (HW_FTFE_FCCOB0(x).U = (v))
mbed_official	324:406fd2029f23	1035	#define HW_FTFE_FCCOB0_SET(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1036	#define HW_FTFE_FCCOB0_CLR(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1037	#define HW_FTFE_FCCOB0_TOG(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1038	/@}/
mbed_official	324:406fd2029f23	1039
mbed_official	324:406fd2029f23	1040	/*
mbed_official	324:406fd2029f23	1041	* Constants & macros for individual FTFE_FCCOB0 bitfields
mbed_official	324:406fd2029f23	1042	*/
mbed_official	324:406fd2029f23	1043
mbed_official	324:406fd2029f23	1044	/*!
mbed_official	324:406fd2029f23	1045	* @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1046	*
mbed_official	324:406fd2029f23	1047	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1048	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1049	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1050	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1051	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1052	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1053	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1054	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1055	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1056	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1057	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1058	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1059	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1060	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1061	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1062	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1063	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1064	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1065	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1066	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1067	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1068	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1069	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1070	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1071	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1072	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1073	*/
mbed_official	324:406fd2029f23	1074	/@{/
mbed_official	324:406fd2029f23	1075	#define BP_FTFE_FCCOB0_CCOBn (0U) /!< Bit position for FTFE_FCCOB0_CCOBn. /
mbed_official	324:406fd2029f23	1076	#define BM_FTFE_FCCOB0_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB0_CCOBn. /
mbed_official	324:406fd2029f23	1077	#define BS_FTFE_FCCOB0_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB0_CCOBn. /
mbed_official	324:406fd2029f23	1078
mbed_official	324:406fd2029f23	1079	/! @brief Read current value of the FTFE_FCCOB0_CCOBn field. /
mbed_official	324:406fd2029f23	1080	#define BR_FTFE_FCCOB0_CCOBn(x) (HW_FTFE_FCCOB0(x).U)
mbed_official	324:406fd2029f23	1081
mbed_official	324:406fd2029f23	1082	/! @brief Format value for bitfield FTFE_FCCOB0_CCOBn. /
mbed_official	324:406fd2029f23	1083	#define BF_FTFE_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB0_CCOBn) & BM_FTFE_FCCOB0_CCOBn)
mbed_official	324:406fd2029f23	1084
mbed_official	324:406fd2029f23	1085	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1086	#define BW_FTFE_FCCOB0_CCOBn(x, v) (HW_FTFE_FCCOB0_WR(x, v))
mbed_official	324:406fd2029f23	1087	/@}/
mbed_official	324:406fd2029f23	1088
mbed_official	324:406fd2029f23	1089	/*******************************************************************************
mbed_official	324:406fd2029f23	1090	* HW_FTFE_FCCOB7 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1091	******************************************************************************/
mbed_official	324:406fd2029f23	1092
mbed_official	324:406fd2029f23	1093	/*!
mbed_official	324:406fd2029f23	1094	* @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1095	*
mbed_official	324:406fd2029f23	1096	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1097	*
mbed_official	324:406fd2029f23	1098	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1099	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1100	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1101	*/
mbed_official	324:406fd2029f23	1102	typedef union _hw_ftfe_fccob7
mbed_official	324:406fd2029f23	1103	{
mbed_official	324:406fd2029f23	1104	uint8_t U;
mbed_official	324:406fd2029f23	1105	struct _hw_ftfe_fccob7_bitfields
mbed_official	324:406fd2029f23	1106	{
mbed_official	324:406fd2029f23	1107	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1108	} B;
mbed_official	324:406fd2029f23	1109	} hw_ftfe_fccob7_t;
mbed_official	324:406fd2029f23	1110
mbed_official	324:406fd2029f23	1111	/*!
mbed_official	324:406fd2029f23	1112	* @name Constants and macros for entire FTFE_FCCOB7 register
mbed_official	324:406fd2029f23	1113	*/
mbed_official	324:406fd2029f23	1114	/@{/
mbed_official	324:406fd2029f23	1115	#define HW_FTFE_FCCOB7_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	1116
mbed_official	324:406fd2029f23	1117	#define HW_FTFE_FCCOB7(x) ((__IO hw_ftfe_fccob7_t ) HW_FTFE_FCCOB7_ADDR(x))
mbed_official	324:406fd2029f23	1118	#define HW_FTFE_FCCOB7_RD(x) (HW_FTFE_FCCOB7(x).U)
mbed_official	324:406fd2029f23	1119	#define HW_FTFE_FCCOB7_WR(x, v) (HW_FTFE_FCCOB7(x).U = (v))
mbed_official	324:406fd2029f23	1120	#define HW_FTFE_FCCOB7_SET(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1121	#define HW_FTFE_FCCOB7_CLR(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1122	#define HW_FTFE_FCCOB7_TOG(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1123	/@}/
mbed_official	324:406fd2029f23	1124
mbed_official	324:406fd2029f23	1125	/*
mbed_official	324:406fd2029f23	1126	* Constants & macros for individual FTFE_FCCOB7 bitfields
mbed_official	324:406fd2029f23	1127	*/
mbed_official	324:406fd2029f23	1128
mbed_official	324:406fd2029f23	1129	/*!
mbed_official	324:406fd2029f23	1130	* @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1131	*
mbed_official	324:406fd2029f23	1132	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1133	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1134	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1135	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1136	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1137	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1138	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1139	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1140	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1141	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1142	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1143	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1144	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1145	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1146	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1147	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1148	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1149	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1150	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1151	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1152	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1153	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1154	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1155	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1156	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1157	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1158	*/
mbed_official	324:406fd2029f23	1159	/@{/
mbed_official	324:406fd2029f23	1160	#define BP_FTFE_FCCOB7_CCOBn (0U) /!< Bit position for FTFE_FCCOB7_CCOBn. /
mbed_official	324:406fd2029f23	1161	#define BM_FTFE_FCCOB7_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB7_CCOBn. /
mbed_official	324:406fd2029f23	1162	#define BS_FTFE_FCCOB7_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB7_CCOBn. /
mbed_official	324:406fd2029f23	1163
mbed_official	324:406fd2029f23	1164	/! @brief Read current value of the FTFE_FCCOB7_CCOBn field. /
mbed_official	324:406fd2029f23	1165	#define BR_FTFE_FCCOB7_CCOBn(x) (HW_FTFE_FCCOB7(x).U)
mbed_official	324:406fd2029f23	1166
mbed_official	324:406fd2029f23	1167	/! @brief Format value for bitfield FTFE_FCCOB7_CCOBn. /
mbed_official	324:406fd2029f23	1168	#define BF_FTFE_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB7_CCOBn) & BM_FTFE_FCCOB7_CCOBn)
mbed_official	324:406fd2029f23	1169
mbed_official	324:406fd2029f23	1170	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1171	#define BW_FTFE_FCCOB7_CCOBn(x, v) (HW_FTFE_FCCOB7_WR(x, v))
mbed_official	324:406fd2029f23	1172	/@}/
mbed_official	324:406fd2029f23	1173
mbed_official	324:406fd2029f23	1174	/*******************************************************************************
mbed_official	324:406fd2029f23	1175	* HW_FTFE_FCCOB6 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1176	******************************************************************************/
mbed_official	324:406fd2029f23	1177
mbed_official	324:406fd2029f23	1178	/*!
mbed_official	324:406fd2029f23	1179	* @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1180	*
mbed_official	324:406fd2029f23	1181	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1182	*
mbed_official	324:406fd2029f23	1183	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1184	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1185	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1186	*/
mbed_official	324:406fd2029f23	1187	typedef union _hw_ftfe_fccob6
mbed_official	324:406fd2029f23	1188	{
mbed_official	324:406fd2029f23	1189	uint8_t U;
mbed_official	324:406fd2029f23	1190	struct _hw_ftfe_fccob6_bitfields
mbed_official	324:406fd2029f23	1191	{
mbed_official	324:406fd2029f23	1192	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1193	} B;
mbed_official	324:406fd2029f23	1194	} hw_ftfe_fccob6_t;
mbed_official	324:406fd2029f23	1195
mbed_official	324:406fd2029f23	1196	/*!
mbed_official	324:406fd2029f23	1197	* @name Constants and macros for entire FTFE_FCCOB6 register
mbed_official	324:406fd2029f23	1198	*/
mbed_official	324:406fd2029f23	1199	/@{/
mbed_official	324:406fd2029f23	1200	#define HW_FTFE_FCCOB6_ADDR(x) ((x) + 0x9U)
mbed_official	324:406fd2029f23	1201
mbed_official	324:406fd2029f23	1202	#define HW_FTFE_FCCOB6(x) ((__IO hw_ftfe_fccob6_t ) HW_FTFE_FCCOB6_ADDR(x))
mbed_official	324:406fd2029f23	1203	#define HW_FTFE_FCCOB6_RD(x) (HW_FTFE_FCCOB6(x).U)
mbed_official	324:406fd2029f23	1204	#define HW_FTFE_FCCOB6_WR(x, v) (HW_FTFE_FCCOB6(x).U = (v))
mbed_official	324:406fd2029f23	1205	#define HW_FTFE_FCCOB6_SET(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1206	#define HW_FTFE_FCCOB6_CLR(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1207	#define HW_FTFE_FCCOB6_TOG(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1208	/@}/
mbed_official	324:406fd2029f23	1209
mbed_official	324:406fd2029f23	1210	/*
mbed_official	324:406fd2029f23	1211	* Constants & macros for individual FTFE_FCCOB6 bitfields
mbed_official	324:406fd2029f23	1212	*/
mbed_official	324:406fd2029f23	1213
mbed_official	324:406fd2029f23	1214	/*!
mbed_official	324:406fd2029f23	1215	* @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1216	*
mbed_official	324:406fd2029f23	1217	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1218	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1219	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1220	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1221	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1222	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1223	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1224	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1225	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1226	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1227	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1228	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1229	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1230	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1231	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1232	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1233	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1234	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1235	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1236	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1237	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1238	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1239	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1240	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1241	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1242	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1243	*/
mbed_official	324:406fd2029f23	1244	/@{/
mbed_official	324:406fd2029f23	1245	#define BP_FTFE_FCCOB6_CCOBn (0U) /!< Bit position for FTFE_FCCOB6_CCOBn. /
mbed_official	324:406fd2029f23	1246	#define BM_FTFE_FCCOB6_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB6_CCOBn. /
mbed_official	324:406fd2029f23	1247	#define BS_FTFE_FCCOB6_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB6_CCOBn. /
mbed_official	324:406fd2029f23	1248
mbed_official	324:406fd2029f23	1249	/! @brief Read current value of the FTFE_FCCOB6_CCOBn field. /
mbed_official	324:406fd2029f23	1250	#define BR_FTFE_FCCOB6_CCOBn(x) (HW_FTFE_FCCOB6(x).U)
mbed_official	324:406fd2029f23	1251
mbed_official	324:406fd2029f23	1252	/! @brief Format value for bitfield FTFE_FCCOB6_CCOBn. /
mbed_official	324:406fd2029f23	1253	#define BF_FTFE_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB6_CCOBn) & BM_FTFE_FCCOB6_CCOBn)
mbed_official	324:406fd2029f23	1254
mbed_official	324:406fd2029f23	1255	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1256	#define BW_FTFE_FCCOB6_CCOBn(x, v) (HW_FTFE_FCCOB6_WR(x, v))
mbed_official	324:406fd2029f23	1257	/@}/
mbed_official	324:406fd2029f23	1258
mbed_official	324:406fd2029f23	1259	/*******************************************************************************
mbed_official	324:406fd2029f23	1260	* HW_FTFE_FCCOB5 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1261	******************************************************************************/
mbed_official	324:406fd2029f23	1262
mbed_official	324:406fd2029f23	1263	/*!
mbed_official	324:406fd2029f23	1264	* @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1265	*
mbed_official	324:406fd2029f23	1266	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1267	*
mbed_official	324:406fd2029f23	1268	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1269	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1270	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1271	*/
mbed_official	324:406fd2029f23	1272	typedef union _hw_ftfe_fccob5
mbed_official	324:406fd2029f23	1273	{
mbed_official	324:406fd2029f23	1274	uint8_t U;
mbed_official	324:406fd2029f23	1275	struct _hw_ftfe_fccob5_bitfields
mbed_official	324:406fd2029f23	1276	{
mbed_official	324:406fd2029f23	1277	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1278	} B;
mbed_official	324:406fd2029f23	1279	} hw_ftfe_fccob5_t;
mbed_official	324:406fd2029f23	1280
mbed_official	324:406fd2029f23	1281	/*!
mbed_official	324:406fd2029f23	1282	* @name Constants and macros for entire FTFE_FCCOB5 register
mbed_official	324:406fd2029f23	1283	*/
mbed_official	324:406fd2029f23	1284	/@{/
mbed_official	324:406fd2029f23	1285	#define HW_FTFE_FCCOB5_ADDR(x) ((x) + 0xAU)
mbed_official	324:406fd2029f23	1286
mbed_official	324:406fd2029f23	1287	#define HW_FTFE_FCCOB5(x) ((__IO hw_ftfe_fccob5_t ) HW_FTFE_FCCOB5_ADDR(x))
mbed_official	324:406fd2029f23	1288	#define HW_FTFE_FCCOB5_RD(x) (HW_FTFE_FCCOB5(x).U)
mbed_official	324:406fd2029f23	1289	#define HW_FTFE_FCCOB5_WR(x, v) (HW_FTFE_FCCOB5(x).U = (v))
mbed_official	324:406fd2029f23	1290	#define HW_FTFE_FCCOB5_SET(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1291	#define HW_FTFE_FCCOB5_CLR(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1292	#define HW_FTFE_FCCOB5_TOG(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1293	/@}/
mbed_official	324:406fd2029f23	1294
mbed_official	324:406fd2029f23	1295	/*
mbed_official	324:406fd2029f23	1296	* Constants & macros for individual FTFE_FCCOB5 bitfields
mbed_official	324:406fd2029f23	1297	*/
mbed_official	324:406fd2029f23	1298
mbed_official	324:406fd2029f23	1299	/*!
mbed_official	324:406fd2029f23	1300	* @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1301	*
mbed_official	324:406fd2029f23	1302	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1303	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1304	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1305	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1306	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1307	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1308	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1309	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1310	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1311	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1312	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1313	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1314	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1315	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1316	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1317	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1318	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1319	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1320	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1321	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1322	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1323	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1324	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1325	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1326	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1327	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1328	*/
mbed_official	324:406fd2029f23	1329	/@{/
mbed_official	324:406fd2029f23	1330	#define BP_FTFE_FCCOB5_CCOBn (0U) /!< Bit position for FTFE_FCCOB5_CCOBn. /
mbed_official	324:406fd2029f23	1331	#define BM_FTFE_FCCOB5_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB5_CCOBn. /
mbed_official	324:406fd2029f23	1332	#define BS_FTFE_FCCOB5_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB5_CCOBn. /
mbed_official	324:406fd2029f23	1333
mbed_official	324:406fd2029f23	1334	/! @brief Read current value of the FTFE_FCCOB5_CCOBn field. /
mbed_official	324:406fd2029f23	1335	#define BR_FTFE_FCCOB5_CCOBn(x) (HW_FTFE_FCCOB5(x).U)
mbed_official	324:406fd2029f23	1336
mbed_official	324:406fd2029f23	1337	/! @brief Format value for bitfield FTFE_FCCOB5_CCOBn. /
mbed_official	324:406fd2029f23	1338	#define BF_FTFE_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB5_CCOBn) & BM_FTFE_FCCOB5_CCOBn)
mbed_official	324:406fd2029f23	1339
mbed_official	324:406fd2029f23	1340	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1341	#define BW_FTFE_FCCOB5_CCOBn(x, v) (HW_FTFE_FCCOB5_WR(x, v))
mbed_official	324:406fd2029f23	1342	/@}/
mbed_official	324:406fd2029f23	1343
mbed_official	324:406fd2029f23	1344	/*******************************************************************************
mbed_official	324:406fd2029f23	1345	* HW_FTFE_FCCOB4 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1346	******************************************************************************/
mbed_official	324:406fd2029f23	1347
mbed_official	324:406fd2029f23	1348	/*!
mbed_official	324:406fd2029f23	1349	* @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1350	*
mbed_official	324:406fd2029f23	1351	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1352	*
mbed_official	324:406fd2029f23	1353	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1354	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1355	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1356	*/
mbed_official	324:406fd2029f23	1357	typedef union _hw_ftfe_fccob4
mbed_official	324:406fd2029f23	1358	{
mbed_official	324:406fd2029f23	1359	uint8_t U;
mbed_official	324:406fd2029f23	1360	struct _hw_ftfe_fccob4_bitfields
mbed_official	324:406fd2029f23	1361	{
mbed_official	324:406fd2029f23	1362	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1363	} B;
mbed_official	324:406fd2029f23	1364	} hw_ftfe_fccob4_t;
mbed_official	324:406fd2029f23	1365
mbed_official	324:406fd2029f23	1366	/*!
mbed_official	324:406fd2029f23	1367	* @name Constants and macros for entire FTFE_FCCOB4 register
mbed_official	324:406fd2029f23	1368	*/
mbed_official	324:406fd2029f23	1369	/@{/
mbed_official	324:406fd2029f23	1370	#define HW_FTFE_FCCOB4_ADDR(x) ((x) + 0xBU)
mbed_official	324:406fd2029f23	1371
mbed_official	324:406fd2029f23	1372	#define HW_FTFE_FCCOB4(x) ((__IO hw_ftfe_fccob4_t ) HW_FTFE_FCCOB4_ADDR(x))
mbed_official	324:406fd2029f23	1373	#define HW_FTFE_FCCOB4_RD(x) (HW_FTFE_FCCOB4(x).U)
mbed_official	324:406fd2029f23	1374	#define HW_FTFE_FCCOB4_WR(x, v) (HW_FTFE_FCCOB4(x).U = (v))
mbed_official	324:406fd2029f23	1375	#define HW_FTFE_FCCOB4_SET(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1376	#define HW_FTFE_FCCOB4_CLR(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1377	#define HW_FTFE_FCCOB4_TOG(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1378	/@}/
mbed_official	324:406fd2029f23	1379
mbed_official	324:406fd2029f23	1380	/*
mbed_official	324:406fd2029f23	1381	* Constants & macros for individual FTFE_FCCOB4 bitfields
mbed_official	324:406fd2029f23	1382	*/
mbed_official	324:406fd2029f23	1383
mbed_official	324:406fd2029f23	1384	/*!
mbed_official	324:406fd2029f23	1385	* @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1386	*
mbed_official	324:406fd2029f23	1387	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1388	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1389	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1390	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1391	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1392	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1393	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1394	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1395	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1396	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1397	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1398	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1399	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1400	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1401	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1402	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1403	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1404	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1405	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1406	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1407	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1408	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1409	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1410	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1411	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1412	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1413	*/
mbed_official	324:406fd2029f23	1414	/@{/
mbed_official	324:406fd2029f23	1415	#define BP_FTFE_FCCOB4_CCOBn (0U) /!< Bit position for FTFE_FCCOB4_CCOBn. /
mbed_official	324:406fd2029f23	1416	#define BM_FTFE_FCCOB4_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB4_CCOBn. /
mbed_official	324:406fd2029f23	1417	#define BS_FTFE_FCCOB4_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB4_CCOBn. /
mbed_official	324:406fd2029f23	1418
mbed_official	324:406fd2029f23	1419	/! @brief Read current value of the FTFE_FCCOB4_CCOBn field. /
mbed_official	324:406fd2029f23	1420	#define BR_FTFE_FCCOB4_CCOBn(x) (HW_FTFE_FCCOB4(x).U)
mbed_official	324:406fd2029f23	1421
mbed_official	324:406fd2029f23	1422	/! @brief Format value for bitfield FTFE_FCCOB4_CCOBn. /
mbed_official	324:406fd2029f23	1423	#define BF_FTFE_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB4_CCOBn) & BM_FTFE_FCCOB4_CCOBn)
mbed_official	324:406fd2029f23	1424
mbed_official	324:406fd2029f23	1425	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1426	#define BW_FTFE_FCCOB4_CCOBn(x, v) (HW_FTFE_FCCOB4_WR(x, v))
mbed_official	324:406fd2029f23	1427	/@}/
mbed_official	324:406fd2029f23	1428
mbed_official	324:406fd2029f23	1429	/*******************************************************************************
mbed_official	324:406fd2029f23	1430	* HW_FTFE_FCCOBB - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1431	******************************************************************************/
mbed_official	324:406fd2029f23	1432
mbed_official	324:406fd2029f23	1433	/*!
mbed_official	324:406fd2029f23	1434	* @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1435	*
mbed_official	324:406fd2029f23	1436	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1437	*
mbed_official	324:406fd2029f23	1438	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1439	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1440	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1441	*/
mbed_official	324:406fd2029f23	1442	typedef union _hw_ftfe_fccobb
mbed_official	324:406fd2029f23	1443	{
mbed_official	324:406fd2029f23	1444	uint8_t U;
mbed_official	324:406fd2029f23	1445	struct _hw_ftfe_fccobb_bitfields
mbed_official	324:406fd2029f23	1446	{
mbed_official	324:406fd2029f23	1447	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1448	} B;
mbed_official	324:406fd2029f23	1449	} hw_ftfe_fccobb_t;
mbed_official	324:406fd2029f23	1450
mbed_official	324:406fd2029f23	1451	/*!
mbed_official	324:406fd2029f23	1452	* @name Constants and macros for entire FTFE_FCCOBB register
mbed_official	324:406fd2029f23	1453	*/
mbed_official	324:406fd2029f23	1454	/@{/
mbed_official	324:406fd2029f23	1455	#define HW_FTFE_FCCOBB_ADDR(x) ((x) + 0xCU)
mbed_official	324:406fd2029f23	1456
mbed_official	324:406fd2029f23	1457	#define HW_FTFE_FCCOBB(x) ((__IO hw_ftfe_fccobb_t ) HW_FTFE_FCCOBB_ADDR(x))
mbed_official	324:406fd2029f23	1458	#define HW_FTFE_FCCOBB_RD(x) (HW_FTFE_FCCOBB(x).U)
mbed_official	324:406fd2029f23	1459	#define HW_FTFE_FCCOBB_WR(x, v) (HW_FTFE_FCCOBB(x).U = (v))
mbed_official	324:406fd2029f23	1460	#define HW_FTFE_FCCOBB_SET(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1461	#define HW_FTFE_FCCOBB_CLR(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1462	#define HW_FTFE_FCCOBB_TOG(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1463	/@}/
mbed_official	324:406fd2029f23	1464
mbed_official	324:406fd2029f23	1465	/*
mbed_official	324:406fd2029f23	1466	* Constants & macros for individual FTFE_FCCOBB bitfields
mbed_official	324:406fd2029f23	1467	*/
mbed_official	324:406fd2029f23	1468
mbed_official	324:406fd2029f23	1469	/*!
mbed_official	324:406fd2029f23	1470	* @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1471	*
mbed_official	324:406fd2029f23	1472	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1473	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1474	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1475	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1476	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1477	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1478	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1479	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1480	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1481	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1482	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1483	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1484	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1485	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1486	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1487	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1488	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1489	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1490	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1491	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1492	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1493	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1494	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1495	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1496	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1497	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1498	*/
mbed_official	324:406fd2029f23	1499	/@{/
mbed_official	324:406fd2029f23	1500	#define BP_FTFE_FCCOBB_CCOBn (0U) /!< Bit position for FTFE_FCCOBB_CCOBn. /
mbed_official	324:406fd2029f23	1501	#define BM_FTFE_FCCOBB_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOBB_CCOBn. /
mbed_official	324:406fd2029f23	1502	#define BS_FTFE_FCCOBB_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOBB_CCOBn. /
mbed_official	324:406fd2029f23	1503
mbed_official	324:406fd2029f23	1504	/! @brief Read current value of the FTFE_FCCOBB_CCOBn field. /
mbed_official	324:406fd2029f23	1505	#define BR_FTFE_FCCOBB_CCOBn(x) (HW_FTFE_FCCOBB(x).U)
mbed_official	324:406fd2029f23	1506
mbed_official	324:406fd2029f23	1507	/! @brief Format value for bitfield FTFE_FCCOBB_CCOBn. /
mbed_official	324:406fd2029f23	1508	#define BF_FTFE_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBB_CCOBn) & BM_FTFE_FCCOBB_CCOBn)
mbed_official	324:406fd2029f23	1509
mbed_official	324:406fd2029f23	1510	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1511	#define BW_FTFE_FCCOBB_CCOBn(x, v) (HW_FTFE_FCCOBB_WR(x, v))
mbed_official	324:406fd2029f23	1512	/@}/
mbed_official	324:406fd2029f23	1513
mbed_official	324:406fd2029f23	1514	/*******************************************************************************
mbed_official	324:406fd2029f23	1515	* HW_FTFE_FCCOBA - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1516	******************************************************************************/
mbed_official	324:406fd2029f23	1517
mbed_official	324:406fd2029f23	1518	/*!
mbed_official	324:406fd2029f23	1519	* @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1520	*
mbed_official	324:406fd2029f23	1521	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1522	*
mbed_official	324:406fd2029f23	1523	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1524	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1525	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1526	*/
mbed_official	324:406fd2029f23	1527	typedef union _hw_ftfe_fccoba
mbed_official	324:406fd2029f23	1528	{
mbed_official	324:406fd2029f23	1529	uint8_t U;
mbed_official	324:406fd2029f23	1530	struct _hw_ftfe_fccoba_bitfields
mbed_official	324:406fd2029f23	1531	{
mbed_official	324:406fd2029f23	1532	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1533	} B;
mbed_official	324:406fd2029f23	1534	} hw_ftfe_fccoba_t;
mbed_official	324:406fd2029f23	1535
mbed_official	324:406fd2029f23	1536	/*!
mbed_official	324:406fd2029f23	1537	* @name Constants and macros for entire FTFE_FCCOBA register
mbed_official	324:406fd2029f23	1538	*/
mbed_official	324:406fd2029f23	1539	/@{/
mbed_official	324:406fd2029f23	1540	#define HW_FTFE_FCCOBA_ADDR(x) ((x) + 0xDU)
mbed_official	324:406fd2029f23	1541
mbed_official	324:406fd2029f23	1542	#define HW_FTFE_FCCOBA(x) ((__IO hw_ftfe_fccoba_t ) HW_FTFE_FCCOBA_ADDR(x))
mbed_official	324:406fd2029f23	1543	#define HW_FTFE_FCCOBA_RD(x) (HW_FTFE_FCCOBA(x).U)
mbed_official	324:406fd2029f23	1544	#define HW_FTFE_FCCOBA_WR(x, v) (HW_FTFE_FCCOBA(x).U = (v))
mbed_official	324:406fd2029f23	1545	#define HW_FTFE_FCCOBA_SET(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1546	#define HW_FTFE_FCCOBA_CLR(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1547	#define HW_FTFE_FCCOBA_TOG(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1548	/@}/
mbed_official	324:406fd2029f23	1549
mbed_official	324:406fd2029f23	1550	/*
mbed_official	324:406fd2029f23	1551	* Constants & macros for individual FTFE_FCCOBA bitfields
mbed_official	324:406fd2029f23	1552	*/
mbed_official	324:406fd2029f23	1553
mbed_official	324:406fd2029f23	1554	/*!
mbed_official	324:406fd2029f23	1555	* @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1556	*
mbed_official	324:406fd2029f23	1557	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1558	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1559	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1560	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1561	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1562	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1563	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1564	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1565	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1566	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1567	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1568	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1569	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1570	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1571	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1572	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1573	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1574	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1575	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1576	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1577	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1578	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1579	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1580	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1581	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1582	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1583	*/
mbed_official	324:406fd2029f23	1584	/@{/
mbed_official	324:406fd2029f23	1585	#define BP_FTFE_FCCOBA_CCOBn (0U) /!< Bit position for FTFE_FCCOBA_CCOBn. /
mbed_official	324:406fd2029f23	1586	#define BM_FTFE_FCCOBA_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOBA_CCOBn. /
mbed_official	324:406fd2029f23	1587	#define BS_FTFE_FCCOBA_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOBA_CCOBn. /
mbed_official	324:406fd2029f23	1588
mbed_official	324:406fd2029f23	1589	/! @brief Read current value of the FTFE_FCCOBA_CCOBn field. /
mbed_official	324:406fd2029f23	1590	#define BR_FTFE_FCCOBA_CCOBn(x) (HW_FTFE_FCCOBA(x).U)
mbed_official	324:406fd2029f23	1591
mbed_official	324:406fd2029f23	1592	/! @brief Format value for bitfield FTFE_FCCOBA_CCOBn. /
mbed_official	324:406fd2029f23	1593	#define BF_FTFE_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBA_CCOBn) & BM_FTFE_FCCOBA_CCOBn)
mbed_official	324:406fd2029f23	1594
mbed_official	324:406fd2029f23	1595	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1596	#define BW_FTFE_FCCOBA_CCOBn(x, v) (HW_FTFE_FCCOBA_WR(x, v))
mbed_official	324:406fd2029f23	1597	/@}/
mbed_official	324:406fd2029f23	1598
mbed_official	324:406fd2029f23	1599	/*******************************************************************************
mbed_official	324:406fd2029f23	1600	* HW_FTFE_FCCOB9 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1601	******************************************************************************/
mbed_official	324:406fd2029f23	1602
mbed_official	324:406fd2029f23	1603	/*!
mbed_official	324:406fd2029f23	1604	* @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1605	*
mbed_official	324:406fd2029f23	1606	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1607	*
mbed_official	324:406fd2029f23	1608	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1609	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1610	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1611	*/
mbed_official	324:406fd2029f23	1612	typedef union _hw_ftfe_fccob9
mbed_official	324:406fd2029f23	1613	{
mbed_official	324:406fd2029f23	1614	uint8_t U;
mbed_official	324:406fd2029f23	1615	struct _hw_ftfe_fccob9_bitfields
mbed_official	324:406fd2029f23	1616	{
mbed_official	324:406fd2029f23	1617	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1618	} B;
mbed_official	324:406fd2029f23	1619	} hw_ftfe_fccob9_t;
mbed_official	324:406fd2029f23	1620
mbed_official	324:406fd2029f23	1621	/*!
mbed_official	324:406fd2029f23	1622	* @name Constants and macros for entire FTFE_FCCOB9 register
mbed_official	324:406fd2029f23	1623	*/
mbed_official	324:406fd2029f23	1624	/@{/
mbed_official	324:406fd2029f23	1625	#define HW_FTFE_FCCOB9_ADDR(x) ((x) + 0xEU)
mbed_official	324:406fd2029f23	1626
mbed_official	324:406fd2029f23	1627	#define HW_FTFE_FCCOB9(x) ((__IO hw_ftfe_fccob9_t ) HW_FTFE_FCCOB9_ADDR(x))
mbed_official	324:406fd2029f23	1628	#define HW_FTFE_FCCOB9_RD(x) (HW_FTFE_FCCOB9(x).U)
mbed_official	324:406fd2029f23	1629	#define HW_FTFE_FCCOB9_WR(x, v) (HW_FTFE_FCCOB9(x).U = (v))
mbed_official	324:406fd2029f23	1630	#define HW_FTFE_FCCOB9_SET(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1631	#define HW_FTFE_FCCOB9_CLR(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1632	#define HW_FTFE_FCCOB9_TOG(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1633	/@}/
mbed_official	324:406fd2029f23	1634
mbed_official	324:406fd2029f23	1635	/*
mbed_official	324:406fd2029f23	1636	* Constants & macros for individual FTFE_FCCOB9 bitfields
mbed_official	324:406fd2029f23	1637	*/
mbed_official	324:406fd2029f23	1638
mbed_official	324:406fd2029f23	1639	/*!
mbed_official	324:406fd2029f23	1640	* @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1641	*
mbed_official	324:406fd2029f23	1642	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1643	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1644	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1645	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1646	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1647	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1648	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1649	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1650	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1651	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1652	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1653	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1654	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1655	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1656	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1657	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1658	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1659	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1660	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1661	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1662	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1663	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1664	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1665	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1666	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1667	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1668	*/
mbed_official	324:406fd2029f23	1669	/@{/
mbed_official	324:406fd2029f23	1670	#define BP_FTFE_FCCOB9_CCOBn (0U) /!< Bit position for FTFE_FCCOB9_CCOBn. /
mbed_official	324:406fd2029f23	1671	#define BM_FTFE_FCCOB9_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB9_CCOBn. /
mbed_official	324:406fd2029f23	1672	#define BS_FTFE_FCCOB9_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB9_CCOBn. /
mbed_official	324:406fd2029f23	1673
mbed_official	324:406fd2029f23	1674	/! @brief Read current value of the FTFE_FCCOB9_CCOBn field. /
mbed_official	324:406fd2029f23	1675	#define BR_FTFE_FCCOB9_CCOBn(x) (HW_FTFE_FCCOB9(x).U)
mbed_official	324:406fd2029f23	1676
mbed_official	324:406fd2029f23	1677	/! @brief Format value for bitfield FTFE_FCCOB9_CCOBn. /
mbed_official	324:406fd2029f23	1678	#define BF_FTFE_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB9_CCOBn) & BM_FTFE_FCCOB9_CCOBn)
mbed_official	324:406fd2029f23	1679
mbed_official	324:406fd2029f23	1680	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1681	#define BW_FTFE_FCCOB9_CCOBn(x, v) (HW_FTFE_FCCOB9_WR(x, v))
mbed_official	324:406fd2029f23	1682	/@}/
mbed_official	324:406fd2029f23	1683
mbed_official	324:406fd2029f23	1684	/*******************************************************************************
mbed_official	324:406fd2029f23	1685	* HW_FTFE_FCCOB8 - Flash Common Command Object Registers
mbed_official	324:406fd2029f23	1686	******************************************************************************/
mbed_official	324:406fd2029f23	1687
mbed_official	324:406fd2029f23	1688	/*!
mbed_official	324:406fd2029f23	1689	* @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
mbed_official	324:406fd2029f23	1690	*
mbed_official	324:406fd2029f23	1691	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1692	*
mbed_official	324:406fd2029f23	1693	* The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official	324:406fd2029f23	1694	* The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official	324:406fd2029f23	1695	* register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official	324:406fd2029f23	1696	*/
mbed_official	324:406fd2029f23	1697	typedef union _hw_ftfe_fccob8
mbed_official	324:406fd2029f23	1698	{
mbed_official	324:406fd2029f23	1699	uint8_t U;
mbed_official	324:406fd2029f23	1700	struct _hw_ftfe_fccob8_bitfields
mbed_official	324:406fd2029f23	1701	{
mbed_official	324:406fd2029f23	1702	uint8_t CCOBn : 8; /!< [7:0] /
mbed_official	324:406fd2029f23	1703	} B;
mbed_official	324:406fd2029f23	1704	} hw_ftfe_fccob8_t;
mbed_official	324:406fd2029f23	1705
mbed_official	324:406fd2029f23	1706	/*!
mbed_official	324:406fd2029f23	1707	* @name Constants and macros for entire FTFE_FCCOB8 register
mbed_official	324:406fd2029f23	1708	*/
mbed_official	324:406fd2029f23	1709	/@{/
mbed_official	324:406fd2029f23	1710	#define HW_FTFE_FCCOB8_ADDR(x) ((x) + 0xFU)
mbed_official	324:406fd2029f23	1711
mbed_official	324:406fd2029f23	1712	#define HW_FTFE_FCCOB8(x) ((__IO hw_ftfe_fccob8_t ) HW_FTFE_FCCOB8_ADDR(x))
mbed_official	324:406fd2029f23	1713	#define HW_FTFE_FCCOB8_RD(x) (HW_FTFE_FCCOB8(x).U)
mbed_official	324:406fd2029f23	1714	#define HW_FTFE_FCCOB8_WR(x, v) (HW_FTFE_FCCOB8(x).U = (v))
mbed_official	324:406fd2029f23	1715	#define HW_FTFE_FCCOB8_SET(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1716	#define HW_FTFE_FCCOB8_CLR(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1717	#define HW_FTFE_FCCOB8_TOG(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1718	/@}/
mbed_official	324:406fd2029f23	1719
mbed_official	324:406fd2029f23	1720	/*
mbed_official	324:406fd2029f23	1721	* Constants & macros for individual FTFE_FCCOB8 bitfields
mbed_official	324:406fd2029f23	1722	*/
mbed_official	324:406fd2029f23	1723
mbed_official	324:406fd2029f23	1724	/*!
mbed_official	324:406fd2029f23	1725	* @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
mbed_official	324:406fd2029f23	1726	*
mbed_official	324:406fd2029f23	1727	* The FCCOB register provides a command code and relevant parameters to the
mbed_official	324:406fd2029f23	1728	* memory controller. The individual registers that compose the FCCOB data set can
mbed_official	324:406fd2029f23	1729	* be written in any order, but you must provide all needed values, which vary
mbed_official	324:406fd2029f23	1730	* from command to command. First, set up all required FCCOB fields and then
mbed_official	324:406fd2029f23	1731	* initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official	324:406fd2029f23	1732	* the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official	324:406fd2029f23	1733	* by the user until the command completes (CCIF returns to 1). No command
mbed_official	324:406fd2029f23	1734	* buffering or queueing is provided; the next command can be loaded only after the
mbed_official	324:406fd2029f23	1735	* current command completes. Some commands return information to the FCCOB
mbed_official	324:406fd2029f23	1736	* registers. Any values returned to FCCOB are available for reading after the
mbed_official	324:406fd2029f23	1737	* FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official	324:406fd2029f23	1738	* generic FTFE command format. The first FCCOB register, FCCOB0, always contains
mbed_official	324:406fd2029f23	1739	* the command code. This 8-bit value defines the command to be executed. The
mbed_official	324:406fd2029f23	1740	* command code is followed by the parameters required for this specific FTFE command,
mbed_official	324:406fd2029f23	1741	* typically an address and/or data values. The command parameter table is
mbed_official	324:406fd2029f23	1742	* written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official	324:406fd2029f23	1743	* number is a reference to the FCCOB register name and is not the register address.
mbed_official	324:406fd2029f23	1744	* FCCOB NumberRefers to FCCOB register name, not register address Typical
mbed_official	324:406fd2029f23	1745	* Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
mbed_official	324:406fd2029f23	1746	* Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
mbed_official	324:406fd2029f23	1747	* 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
mbed_official	324:406fd2029f23	1748	* Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
mbed_official	324:406fd2029f23	1749	* register group uses a big endian addressing convention. For all command parameter
mbed_official	324:406fd2029f23	1750	* fields larger than 1 byte, the most significant data resides in the lowest FCCOB
mbed_official	324:406fd2029f23	1751	* register number. The FCCOB register group may be read and written as
mbed_official	324:406fd2029f23	1752	* individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
mbed_official	324:406fd2029f23	1753	*/
mbed_official	324:406fd2029f23	1754	/@{/
mbed_official	324:406fd2029f23	1755	#define BP_FTFE_FCCOB8_CCOBn (0U) /!< Bit position for FTFE_FCCOB8_CCOBn. /
mbed_official	324:406fd2029f23	1756	#define BM_FTFE_FCCOB8_CCOBn (0xFFU) /!< Bit mask for FTFE_FCCOB8_CCOBn. /
mbed_official	324:406fd2029f23	1757	#define BS_FTFE_FCCOB8_CCOBn (8U) /!< Bit field size in bits for FTFE_FCCOB8_CCOBn. /
mbed_official	324:406fd2029f23	1758
mbed_official	324:406fd2029f23	1759	/! @brief Read current value of the FTFE_FCCOB8_CCOBn field. /
mbed_official	324:406fd2029f23	1760	#define BR_FTFE_FCCOB8_CCOBn(x) (HW_FTFE_FCCOB8(x).U)
mbed_official	324:406fd2029f23	1761
mbed_official	324:406fd2029f23	1762	/! @brief Format value for bitfield FTFE_FCCOB8_CCOBn. /
mbed_official	324:406fd2029f23	1763	#define BF_FTFE_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB8_CCOBn) & BM_FTFE_FCCOB8_CCOBn)
mbed_official	324:406fd2029f23	1764
mbed_official	324:406fd2029f23	1765	/! @brief Set the CCOBn field to a new value. /
mbed_official	324:406fd2029f23	1766	#define BW_FTFE_FCCOB8_CCOBn(x, v) (HW_FTFE_FCCOB8_WR(x, v))
mbed_official	324:406fd2029f23	1767	/@}/
mbed_official	324:406fd2029f23	1768
mbed_official	324:406fd2029f23	1769	/*******************************************************************************
mbed_official	324:406fd2029f23	1770	* HW_FTFE_FPROT3 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	1771	******************************************************************************/
mbed_official	324:406fd2029f23	1772
mbed_official	324:406fd2029f23	1773	/*!
mbed_official	324:406fd2029f23	1774	* @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
mbed_official	324:406fd2029f23	1775	*
mbed_official	324:406fd2029f23	1776	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1777	*
mbed_official	324:406fd2029f23	1778	* The FPROT registers define which program flash regions are protected from
mbed_official	324:406fd2029f23	1779	* program and erase operations. Protected flash regions cannot have their content
mbed_official	324:406fd2029f23	1780	* changed; that is, these regions cannot be programmed and cannot be erased by
mbed_official	324:406fd2029f23	1781	* any FTFE command. Unprotected regions can be changed by program and erase
mbed_official	324:406fd2029f23	1782	* operations. The four FPROT registers allow up to 32 protectable regions of equal
mbed_official	324:406fd2029f23	1783	* memory size. Program flash protection register Program flash protection bits
mbed_official	324:406fd2029f23	1784	* FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
mbed_official	324:406fd2029f23	1785	* the reset sequence, the FPROT registers are loaded with the contents of the
mbed_official	324:406fd2029f23	1786	* program flash protection bytes in the Flash Configuration Field as indicated in
mbed_official	324:406fd2029f23	1787	* the following table. Program flash protection register Flash Configuration Field
mbed_official	324:406fd2029f23	1788	* offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
mbed_official	324:406fd2029f23	1789	* change the program flash protection that is loaded during the reset sequence,
mbed_official	324:406fd2029f23	1790	* unprotect the sector of program flash memory that contains the Flash
mbed_official	324:406fd2029f23	1791	* Configuration Field. Then, reprogram the program flash protection byte.
mbed_official	324:406fd2029f23	1792	*/
mbed_official	324:406fd2029f23	1793	typedef union _hw_ftfe_fprot3
mbed_official	324:406fd2029f23	1794	{
mbed_official	324:406fd2029f23	1795	uint8_t U;
mbed_official	324:406fd2029f23	1796	struct _hw_ftfe_fprot3_bitfields
mbed_official	324:406fd2029f23	1797	{
mbed_official	324:406fd2029f23	1798	uint8_t PROT : 8; /!< [7:0] Program Flash Region Protect /
mbed_official	324:406fd2029f23	1799	} B;
mbed_official	324:406fd2029f23	1800	} hw_ftfe_fprot3_t;
mbed_official	324:406fd2029f23	1801
mbed_official	324:406fd2029f23	1802	/*!
mbed_official	324:406fd2029f23	1803	* @name Constants and macros for entire FTFE_FPROT3 register
mbed_official	324:406fd2029f23	1804	*/
mbed_official	324:406fd2029f23	1805	/@{/
mbed_official	324:406fd2029f23	1806	#define HW_FTFE_FPROT3_ADDR(x) ((x) + 0x10U)
mbed_official	324:406fd2029f23	1807
mbed_official	324:406fd2029f23	1808	#define HW_FTFE_FPROT3(x) ((__IO hw_ftfe_fprot3_t ) HW_FTFE_FPROT3_ADDR(x))
mbed_official	324:406fd2029f23	1809	#define HW_FTFE_FPROT3_RD(x) (HW_FTFE_FPROT3(x).U)
mbed_official	324:406fd2029f23	1810	#define HW_FTFE_FPROT3_WR(x, v) (HW_FTFE_FPROT3(x).U = (v))
mbed_official	324:406fd2029f23	1811	#define HW_FTFE_FPROT3_SET(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1812	#define HW_FTFE_FPROT3_CLR(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1813	#define HW_FTFE_FPROT3_TOG(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1814	/@}/
mbed_official	324:406fd2029f23	1815
mbed_official	324:406fd2029f23	1816	/*
mbed_official	324:406fd2029f23	1817	* Constants & macros for individual FTFE_FPROT3 bitfields
mbed_official	324:406fd2029f23	1818	*/
mbed_official	324:406fd2029f23	1819
mbed_official	324:406fd2029f23	1820	/*!
mbed_official	324:406fd2029f23	1821	* @name Register FTFE_FPROT3, field PROT[7:0] (RW)
mbed_official	324:406fd2029f23	1822	*
mbed_official	324:406fd2029f23	1823	* Each program flash region can be protected from program and erase operations
mbed_official	324:406fd2029f23	1824	* by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official	324:406fd2029f23	1825	* only be increased, meaning that currently unprotected memory can be protected,
mbed_official	324:406fd2029f23	1826	* but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official	324:406fd2029f23	1827	* are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official	324:406fd2029f23	1828	* 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official	324:406fd2029f23	1829	* basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official	324:406fd2029f23	1830	* 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official	324:406fd2029f23	1831	* writable without restriction. Unprotected areas can be protected and protected
mbed_official	324:406fd2029f23	1832	* areas can be unprotected. The user must never write to any FPROT register while
mbed_official	324:406fd2029f23	1833	* a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official	324:406fd2029f23	1834	* the program flash memory results in a protection violation error and sets the
mbed_official	324:406fd2029f23	1835	* FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official	324:406fd2029f23	1836	* if it contains any protected region.
mbed_official	324:406fd2029f23	1837	*
mbed_official	324:406fd2029f23	1838	* Values:
mbed_official	324:406fd2029f23	1839	* - 0 - Program flash region is protected.
mbed_official	324:406fd2029f23	1840	* - 1 - Program flash region is not protected
mbed_official	324:406fd2029f23	1841	*/
mbed_official	324:406fd2029f23	1842	/@{/
mbed_official	324:406fd2029f23	1843	#define BP_FTFE_FPROT3_PROT (0U) /!< Bit position for FTFE_FPROT3_PROT. /
mbed_official	324:406fd2029f23	1844	#define BM_FTFE_FPROT3_PROT (0xFFU) /!< Bit mask for FTFE_FPROT3_PROT. /
mbed_official	324:406fd2029f23	1845	#define BS_FTFE_FPROT3_PROT (8U) /!< Bit field size in bits for FTFE_FPROT3_PROT. /
mbed_official	324:406fd2029f23	1846
mbed_official	324:406fd2029f23	1847	/! @brief Read current value of the FTFE_FPROT3_PROT field. /
mbed_official	324:406fd2029f23	1848	#define BR_FTFE_FPROT3_PROT(x) (HW_FTFE_FPROT3(x).U)
mbed_official	324:406fd2029f23	1849
mbed_official	324:406fd2029f23	1850	/! @brief Format value for bitfield FTFE_FPROT3_PROT. /
mbed_official	324:406fd2029f23	1851	#define BF_FTFE_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT3_PROT) & BM_FTFE_FPROT3_PROT)
mbed_official	324:406fd2029f23	1852
mbed_official	324:406fd2029f23	1853	/! @brief Set the PROT field to a new value. /
mbed_official	324:406fd2029f23	1854	#define BW_FTFE_FPROT3_PROT(x, v) (HW_FTFE_FPROT3_WR(x, v))
mbed_official	324:406fd2029f23	1855	/@}/
mbed_official	324:406fd2029f23	1856
mbed_official	324:406fd2029f23	1857	/*******************************************************************************
mbed_official	324:406fd2029f23	1858	* HW_FTFE_FPROT2 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	1859	******************************************************************************/
mbed_official	324:406fd2029f23	1860
mbed_official	324:406fd2029f23	1861	/*!
mbed_official	324:406fd2029f23	1862	* @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
mbed_official	324:406fd2029f23	1863	*
mbed_official	324:406fd2029f23	1864	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1865	*
mbed_official	324:406fd2029f23	1866	* The FPROT registers define which program flash regions are protected from
mbed_official	324:406fd2029f23	1867	* program and erase operations. Protected flash regions cannot have their content
mbed_official	324:406fd2029f23	1868	* changed; that is, these regions cannot be programmed and cannot be erased by
mbed_official	324:406fd2029f23	1869	* any FTFE command. Unprotected regions can be changed by program and erase
mbed_official	324:406fd2029f23	1870	* operations. The four FPROT registers allow up to 32 protectable regions of equal
mbed_official	324:406fd2029f23	1871	* memory size. Program flash protection register Program flash protection bits
mbed_official	324:406fd2029f23	1872	* FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
mbed_official	324:406fd2029f23	1873	* the reset sequence, the FPROT registers are loaded with the contents of the
mbed_official	324:406fd2029f23	1874	* program flash protection bytes in the Flash Configuration Field as indicated in
mbed_official	324:406fd2029f23	1875	* the following table. Program flash protection register Flash Configuration Field
mbed_official	324:406fd2029f23	1876	* offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
mbed_official	324:406fd2029f23	1877	* change the program flash protection that is loaded during the reset sequence,
mbed_official	324:406fd2029f23	1878	* unprotect the sector of program flash memory that contains the Flash
mbed_official	324:406fd2029f23	1879	* Configuration Field. Then, reprogram the program flash protection byte.
mbed_official	324:406fd2029f23	1880	*/
mbed_official	324:406fd2029f23	1881	typedef union _hw_ftfe_fprot2
mbed_official	324:406fd2029f23	1882	{
mbed_official	324:406fd2029f23	1883	uint8_t U;
mbed_official	324:406fd2029f23	1884	struct _hw_ftfe_fprot2_bitfields
mbed_official	324:406fd2029f23	1885	{
mbed_official	324:406fd2029f23	1886	uint8_t PROT : 8; /!< [7:0] Program Flash Region Protect /
mbed_official	324:406fd2029f23	1887	} B;
mbed_official	324:406fd2029f23	1888	} hw_ftfe_fprot2_t;
mbed_official	324:406fd2029f23	1889
mbed_official	324:406fd2029f23	1890	/*!
mbed_official	324:406fd2029f23	1891	* @name Constants and macros for entire FTFE_FPROT2 register
mbed_official	324:406fd2029f23	1892	*/
mbed_official	324:406fd2029f23	1893	/@{/
mbed_official	324:406fd2029f23	1894	#define HW_FTFE_FPROT2_ADDR(x) ((x) + 0x11U)
mbed_official	324:406fd2029f23	1895
mbed_official	324:406fd2029f23	1896	#define HW_FTFE_FPROT2(x) ((__IO hw_ftfe_fprot2_t ) HW_FTFE_FPROT2_ADDR(x))
mbed_official	324:406fd2029f23	1897	#define HW_FTFE_FPROT2_RD(x) (HW_FTFE_FPROT2(x).U)
mbed_official	324:406fd2029f23	1898	#define HW_FTFE_FPROT2_WR(x, v) (HW_FTFE_FPROT2(x).U = (v))
mbed_official	324:406fd2029f23	1899	#define HW_FTFE_FPROT2_SET(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1900	#define HW_FTFE_FPROT2_CLR(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1901	#define HW_FTFE_FPROT2_TOG(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1902	/@}/
mbed_official	324:406fd2029f23	1903
mbed_official	324:406fd2029f23	1904	/*
mbed_official	324:406fd2029f23	1905	* Constants & macros for individual FTFE_FPROT2 bitfields
mbed_official	324:406fd2029f23	1906	*/
mbed_official	324:406fd2029f23	1907
mbed_official	324:406fd2029f23	1908	/*!
mbed_official	324:406fd2029f23	1909	* @name Register FTFE_FPROT2, field PROT[7:0] (RW)
mbed_official	324:406fd2029f23	1910	*
mbed_official	324:406fd2029f23	1911	* Each program flash region can be protected from program and erase operations
mbed_official	324:406fd2029f23	1912	* by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official	324:406fd2029f23	1913	* only be increased, meaning that currently unprotected memory can be protected,
mbed_official	324:406fd2029f23	1914	* but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official	324:406fd2029f23	1915	* are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official	324:406fd2029f23	1916	* 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official	324:406fd2029f23	1917	* basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official	324:406fd2029f23	1918	* 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official	324:406fd2029f23	1919	* writable without restriction. Unprotected areas can be protected and protected
mbed_official	324:406fd2029f23	1920	* areas can be unprotected. The user must never write to any FPROT register while
mbed_official	324:406fd2029f23	1921	* a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official	324:406fd2029f23	1922	* the program flash memory results in a protection violation error and sets the
mbed_official	324:406fd2029f23	1923	* FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official	324:406fd2029f23	1924	* if it contains any protected region.
mbed_official	324:406fd2029f23	1925	*
mbed_official	324:406fd2029f23	1926	* Values:
mbed_official	324:406fd2029f23	1927	* - 0 - Program flash region is protected.
mbed_official	324:406fd2029f23	1928	* - 1 - Program flash region is not protected
mbed_official	324:406fd2029f23	1929	*/
mbed_official	324:406fd2029f23	1930	/@{/
mbed_official	324:406fd2029f23	1931	#define BP_FTFE_FPROT2_PROT (0U) /!< Bit position for FTFE_FPROT2_PROT. /
mbed_official	324:406fd2029f23	1932	#define BM_FTFE_FPROT2_PROT (0xFFU) /!< Bit mask for FTFE_FPROT2_PROT. /
mbed_official	324:406fd2029f23	1933	#define BS_FTFE_FPROT2_PROT (8U) /!< Bit field size in bits for FTFE_FPROT2_PROT. /
mbed_official	324:406fd2029f23	1934
mbed_official	324:406fd2029f23	1935	/! @brief Read current value of the FTFE_FPROT2_PROT field. /
mbed_official	324:406fd2029f23	1936	#define BR_FTFE_FPROT2_PROT(x) (HW_FTFE_FPROT2(x).U)
mbed_official	324:406fd2029f23	1937
mbed_official	324:406fd2029f23	1938	/! @brief Format value for bitfield FTFE_FPROT2_PROT. /
mbed_official	324:406fd2029f23	1939	#define BF_FTFE_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT2_PROT) & BM_FTFE_FPROT2_PROT)
mbed_official	324:406fd2029f23	1940
mbed_official	324:406fd2029f23	1941	/! @brief Set the PROT field to a new value. /
mbed_official	324:406fd2029f23	1942	#define BW_FTFE_FPROT2_PROT(x, v) (HW_FTFE_FPROT2_WR(x, v))
mbed_official	324:406fd2029f23	1943	/@}/
mbed_official	324:406fd2029f23	1944
mbed_official	324:406fd2029f23	1945	/*******************************************************************************
mbed_official	324:406fd2029f23	1946	* HW_FTFE_FPROT1 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	1947	******************************************************************************/
mbed_official	324:406fd2029f23	1948
mbed_official	324:406fd2029f23	1949	/*!
mbed_official	324:406fd2029f23	1950	* @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
mbed_official	324:406fd2029f23	1951	*
mbed_official	324:406fd2029f23	1952	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1953	*
mbed_official	324:406fd2029f23	1954	* The FPROT registers define which program flash regions are protected from
mbed_official	324:406fd2029f23	1955	* program and erase operations. Protected flash regions cannot have their content
mbed_official	324:406fd2029f23	1956	* changed; that is, these regions cannot be programmed and cannot be erased by
mbed_official	324:406fd2029f23	1957	* any FTFE command. Unprotected regions can be changed by program and erase
mbed_official	324:406fd2029f23	1958	* operations. The four FPROT registers allow up to 32 protectable regions of equal
mbed_official	324:406fd2029f23	1959	* memory size. Program flash protection register Program flash protection bits
mbed_official	324:406fd2029f23	1960	* FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
mbed_official	324:406fd2029f23	1961	* the reset sequence, the FPROT registers are loaded with the contents of the
mbed_official	324:406fd2029f23	1962	* program flash protection bytes in the Flash Configuration Field as indicated in
mbed_official	324:406fd2029f23	1963	* the following table. Program flash protection register Flash Configuration Field
mbed_official	324:406fd2029f23	1964	* offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
mbed_official	324:406fd2029f23	1965	* change the program flash protection that is loaded during the reset sequence,
mbed_official	324:406fd2029f23	1966	* unprotect the sector of program flash memory that contains the Flash
mbed_official	324:406fd2029f23	1967	* Configuration Field. Then, reprogram the program flash protection byte.
mbed_official	324:406fd2029f23	1968	*/
mbed_official	324:406fd2029f23	1969	typedef union _hw_ftfe_fprot1
mbed_official	324:406fd2029f23	1970	{
mbed_official	324:406fd2029f23	1971	uint8_t U;
mbed_official	324:406fd2029f23	1972	struct _hw_ftfe_fprot1_bitfields
mbed_official	324:406fd2029f23	1973	{
mbed_official	324:406fd2029f23	1974	uint8_t PROT : 8; /!< [7:0] Program Flash Region Protect /
mbed_official	324:406fd2029f23	1975	} B;
mbed_official	324:406fd2029f23	1976	} hw_ftfe_fprot1_t;
mbed_official	324:406fd2029f23	1977
mbed_official	324:406fd2029f23	1978	/*!
mbed_official	324:406fd2029f23	1979	* @name Constants and macros for entire FTFE_FPROT1 register
mbed_official	324:406fd2029f23	1980	*/
mbed_official	324:406fd2029f23	1981	/@{/
mbed_official	324:406fd2029f23	1982	#define HW_FTFE_FPROT1_ADDR(x) ((x) + 0x12U)
mbed_official	324:406fd2029f23	1983
mbed_official	324:406fd2029f23	1984	#define HW_FTFE_FPROT1(x) ((__IO hw_ftfe_fprot1_t ) HW_FTFE_FPROT1_ADDR(x))
mbed_official	324:406fd2029f23	1985	#define HW_FTFE_FPROT1_RD(x) (HW_FTFE_FPROT1(x).U)
mbed_official	324:406fd2029f23	1986	#define HW_FTFE_FPROT1_WR(x, v) (HW_FTFE_FPROT1(x).U = (v))
mbed_official	324:406fd2029f23	1987	#define HW_FTFE_FPROT1_SET(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1988	#define HW_FTFE_FPROT1_CLR(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1989	#define HW_FTFE_FPROT1_TOG(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1990	/@}/
mbed_official	324:406fd2029f23	1991
mbed_official	324:406fd2029f23	1992	/*
mbed_official	324:406fd2029f23	1993	* Constants & macros for individual FTFE_FPROT1 bitfields
mbed_official	324:406fd2029f23	1994	*/
mbed_official	324:406fd2029f23	1995
mbed_official	324:406fd2029f23	1996	/*!
mbed_official	324:406fd2029f23	1997	* @name Register FTFE_FPROT1, field PROT[7:0] (RW)
mbed_official	324:406fd2029f23	1998	*
mbed_official	324:406fd2029f23	1999	* Each program flash region can be protected from program and erase operations
mbed_official	324:406fd2029f23	2000	* by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official	324:406fd2029f23	2001	* only be increased, meaning that currently unprotected memory can be protected,
mbed_official	324:406fd2029f23	2002	* but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official	324:406fd2029f23	2003	* are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official	324:406fd2029f23	2004	* 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official	324:406fd2029f23	2005	* basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official	324:406fd2029f23	2006	* 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official	324:406fd2029f23	2007	* writable without restriction. Unprotected areas can be protected and protected
mbed_official	324:406fd2029f23	2008	* areas can be unprotected. The user must never write to any FPROT register while
mbed_official	324:406fd2029f23	2009	* a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official	324:406fd2029f23	2010	* the program flash memory results in a protection violation error and sets the
mbed_official	324:406fd2029f23	2011	* FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official	324:406fd2029f23	2012	* if it contains any protected region.
mbed_official	324:406fd2029f23	2013	*
mbed_official	324:406fd2029f23	2014	* Values:
mbed_official	324:406fd2029f23	2015	* - 0 - Program flash region is protected.
mbed_official	324:406fd2029f23	2016	* - 1 - Program flash region is not protected
mbed_official	324:406fd2029f23	2017	*/
mbed_official	324:406fd2029f23	2018	/@{/
mbed_official	324:406fd2029f23	2019	#define BP_FTFE_FPROT1_PROT (0U) /!< Bit position for FTFE_FPROT1_PROT. /
mbed_official	324:406fd2029f23	2020	#define BM_FTFE_FPROT1_PROT (0xFFU) /!< Bit mask for FTFE_FPROT1_PROT. /
mbed_official	324:406fd2029f23	2021	#define BS_FTFE_FPROT1_PROT (8U) /!< Bit field size in bits for FTFE_FPROT1_PROT. /
mbed_official	324:406fd2029f23	2022
mbed_official	324:406fd2029f23	2023	/! @brief Read current value of the FTFE_FPROT1_PROT field. /
mbed_official	324:406fd2029f23	2024	#define BR_FTFE_FPROT1_PROT(x) (HW_FTFE_FPROT1(x).U)
mbed_official	324:406fd2029f23	2025
mbed_official	324:406fd2029f23	2026	/! @brief Format value for bitfield FTFE_FPROT1_PROT. /
mbed_official	324:406fd2029f23	2027	#define BF_FTFE_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT1_PROT) & BM_FTFE_FPROT1_PROT)
mbed_official	324:406fd2029f23	2028
mbed_official	324:406fd2029f23	2029	/! @brief Set the PROT field to a new value. /
mbed_official	324:406fd2029f23	2030	#define BW_FTFE_FPROT1_PROT(x, v) (HW_FTFE_FPROT1_WR(x, v))
mbed_official	324:406fd2029f23	2031	/@}/
mbed_official	324:406fd2029f23	2032
mbed_official	324:406fd2029f23	2033	/*******************************************************************************
mbed_official	324:406fd2029f23	2034	* HW_FTFE_FPROT0 - Program Flash Protection Registers
mbed_official	324:406fd2029f23	2035	******************************************************************************/
mbed_official	324:406fd2029f23	2036
mbed_official	324:406fd2029f23	2037	/*!
mbed_official	324:406fd2029f23	2038	* @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
mbed_official	324:406fd2029f23	2039	*
mbed_official	324:406fd2029f23	2040	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2041	*
mbed_official	324:406fd2029f23	2042	* The FPROT registers define which program flash regions are protected from
mbed_official	324:406fd2029f23	2043	* program and erase operations. Protected flash regions cannot have their content
mbed_official	324:406fd2029f23	2044	* changed; that is, these regions cannot be programmed and cannot be erased by
mbed_official	324:406fd2029f23	2045	* any FTFE command. Unprotected regions can be changed by program and erase
mbed_official	324:406fd2029f23	2046	* operations. The four FPROT registers allow up to 32 protectable regions of equal
mbed_official	324:406fd2029f23	2047	* memory size. Program flash protection register Program flash protection bits
mbed_official	324:406fd2029f23	2048	* FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
mbed_official	324:406fd2029f23	2049	* the reset sequence, the FPROT registers are loaded with the contents of the
mbed_official	324:406fd2029f23	2050	* program flash protection bytes in the Flash Configuration Field as indicated in
mbed_official	324:406fd2029f23	2051	* the following table. Program flash protection register Flash Configuration Field
mbed_official	324:406fd2029f23	2052	* offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
mbed_official	324:406fd2029f23	2053	* change the program flash protection that is loaded during the reset sequence,
mbed_official	324:406fd2029f23	2054	* unprotect the sector of program flash memory that contains the Flash
mbed_official	324:406fd2029f23	2055	* Configuration Field. Then, reprogram the program flash protection byte.
mbed_official	324:406fd2029f23	2056	*/
mbed_official	324:406fd2029f23	2057	typedef union _hw_ftfe_fprot0
mbed_official	324:406fd2029f23	2058	{
mbed_official	324:406fd2029f23	2059	uint8_t U;
mbed_official	324:406fd2029f23	2060	struct _hw_ftfe_fprot0_bitfields
mbed_official	324:406fd2029f23	2061	{
mbed_official	324:406fd2029f23	2062	uint8_t PROT : 8; /!< [7:0] Program Flash Region Protect /
mbed_official	324:406fd2029f23	2063	} B;
mbed_official	324:406fd2029f23	2064	} hw_ftfe_fprot0_t;
mbed_official	324:406fd2029f23	2065
mbed_official	324:406fd2029f23	2066	/*!
mbed_official	324:406fd2029f23	2067	* @name Constants and macros for entire FTFE_FPROT0 register
mbed_official	324:406fd2029f23	2068	*/
mbed_official	324:406fd2029f23	2069	/@{/
mbed_official	324:406fd2029f23	2070	#define HW_FTFE_FPROT0_ADDR(x) ((x) + 0x13U)
mbed_official	324:406fd2029f23	2071
mbed_official	324:406fd2029f23	2072	#define HW_FTFE_FPROT0(x) ((__IO hw_ftfe_fprot0_t ) HW_FTFE_FPROT0_ADDR(x))
mbed_official	324:406fd2029f23	2073	#define HW_FTFE_FPROT0_RD(x) (HW_FTFE_FPROT0(x).U)
mbed_official	324:406fd2029f23	2074	#define HW_FTFE_FPROT0_WR(x, v) (HW_FTFE_FPROT0(x).U = (v))
mbed_official	324:406fd2029f23	2075	#define HW_FTFE_FPROT0_SET(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2076	#define HW_FTFE_FPROT0_CLR(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2077	#define HW_FTFE_FPROT0_TOG(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2078	/@}/
mbed_official	324:406fd2029f23	2079
mbed_official	324:406fd2029f23	2080	/*
mbed_official	324:406fd2029f23	2081	* Constants & macros for individual FTFE_FPROT0 bitfields
mbed_official	324:406fd2029f23	2082	*/
mbed_official	324:406fd2029f23	2083
mbed_official	324:406fd2029f23	2084	/*!
mbed_official	324:406fd2029f23	2085	* @name Register FTFE_FPROT0, field PROT[7:0] (RW)
mbed_official	324:406fd2029f23	2086	*
mbed_official	324:406fd2029f23	2087	* Each program flash region can be protected from program and erase operations
mbed_official	324:406fd2029f23	2088	* by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official	324:406fd2029f23	2089	* only be increased, meaning that currently unprotected memory can be protected,
mbed_official	324:406fd2029f23	2090	* but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official	324:406fd2029f23	2091	* are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official	324:406fd2029f23	2092	* 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official	324:406fd2029f23	2093	* basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official	324:406fd2029f23	2094	* 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official	324:406fd2029f23	2095	* writable without restriction. Unprotected areas can be protected and protected
mbed_official	324:406fd2029f23	2096	* areas can be unprotected. The user must never write to any FPROT register while
mbed_official	324:406fd2029f23	2097	* a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official	324:406fd2029f23	2098	* the program flash memory results in a protection violation error and sets the
mbed_official	324:406fd2029f23	2099	* FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official	324:406fd2029f23	2100	* if it contains any protected region.
mbed_official	324:406fd2029f23	2101	*
mbed_official	324:406fd2029f23	2102	* Values:
mbed_official	324:406fd2029f23	2103	* - 0 - Program flash region is protected.
mbed_official	324:406fd2029f23	2104	* - 1 - Program flash region is not protected
mbed_official	324:406fd2029f23	2105	*/
mbed_official	324:406fd2029f23	2106	/@{/
mbed_official	324:406fd2029f23	2107	#define BP_FTFE_FPROT0_PROT (0U) /!< Bit position for FTFE_FPROT0_PROT. /
mbed_official	324:406fd2029f23	2108	#define BM_FTFE_FPROT0_PROT (0xFFU) /!< Bit mask for FTFE_FPROT0_PROT. /
mbed_official	324:406fd2029f23	2109	#define BS_FTFE_FPROT0_PROT (8U) /!< Bit field size in bits for FTFE_FPROT0_PROT. /
mbed_official	324:406fd2029f23	2110
mbed_official	324:406fd2029f23	2111	/! @brief Read current value of the FTFE_FPROT0_PROT field. /
mbed_official	324:406fd2029f23	2112	#define BR_FTFE_FPROT0_PROT(x) (HW_FTFE_FPROT0(x).U)
mbed_official	324:406fd2029f23	2113
mbed_official	324:406fd2029f23	2114	/! @brief Format value for bitfield FTFE_FPROT0_PROT. /
mbed_official	324:406fd2029f23	2115	#define BF_FTFE_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT0_PROT) & BM_FTFE_FPROT0_PROT)
mbed_official	324:406fd2029f23	2116
mbed_official	324:406fd2029f23	2117	/! @brief Set the PROT field to a new value. /
mbed_official	324:406fd2029f23	2118	#define BW_FTFE_FPROT0_PROT(x, v) (HW_FTFE_FPROT0_WR(x, v))
mbed_official	324:406fd2029f23	2119	/@}/
mbed_official	324:406fd2029f23	2120
mbed_official	324:406fd2029f23	2121	/*******************************************************************************
mbed_official	324:406fd2029f23	2122	* HW_FTFE_FEPROT - EEPROM Protection Register
mbed_official	324:406fd2029f23	2123	******************************************************************************/
mbed_official	324:406fd2029f23	2124
mbed_official	324:406fd2029f23	2125	/*!
mbed_official	324:406fd2029f23	2126	* @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
mbed_official	324:406fd2029f23	2127	*
mbed_official	324:406fd2029f23	2128	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2129	*
mbed_official	324:406fd2029f23	2130	* For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
mbed_official	324:406fd2029f23	2131	* the FlexRAM are protected against program and erase operations. Protected
mbed_official	324:406fd2029f23	2132	* EEPROM regions cannot have their content changed by writing to it. Unprotected
mbed_official	324:406fd2029f23	2133	* regions can be changed by writing to the FlexRAM. For devices with program flash
mbed_official	324:406fd2029f23	2134	* only: This register is reserved and not used.
mbed_official	324:406fd2029f23	2135	*/
mbed_official	324:406fd2029f23	2136	typedef union _hw_ftfe_feprot
mbed_official	324:406fd2029f23	2137	{
mbed_official	324:406fd2029f23	2138	uint8_t U;
mbed_official	324:406fd2029f23	2139	struct _hw_ftfe_feprot_bitfields
mbed_official	324:406fd2029f23	2140	{
mbed_official	324:406fd2029f23	2141	uint8_t EPROT : 8; /!< [7:0] EEPROM Region Protect /
mbed_official	324:406fd2029f23	2142	} B;
mbed_official	324:406fd2029f23	2143	} hw_ftfe_feprot_t;
mbed_official	324:406fd2029f23	2144
mbed_official	324:406fd2029f23	2145	/*!
mbed_official	324:406fd2029f23	2146	* @name Constants and macros for entire FTFE_FEPROT register
mbed_official	324:406fd2029f23	2147	*/
mbed_official	324:406fd2029f23	2148	/@{/
mbed_official	324:406fd2029f23	2149	#define HW_FTFE_FEPROT_ADDR(x) ((x) + 0x16U)
mbed_official	324:406fd2029f23	2150
mbed_official	324:406fd2029f23	2151	#define HW_FTFE_FEPROT(x) ((__IO hw_ftfe_feprot_t ) HW_FTFE_FEPROT_ADDR(x))
mbed_official	324:406fd2029f23	2152	#define HW_FTFE_FEPROT_RD(x) (HW_FTFE_FEPROT(x).U)
mbed_official	324:406fd2029f23	2153	#define HW_FTFE_FEPROT_WR(x, v) (HW_FTFE_FEPROT(x).U = (v))
mbed_official	324:406fd2029f23	2154	#define HW_FTFE_FEPROT_SET(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2155	#define HW_FTFE_FEPROT_CLR(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2156	#define HW_FTFE_FEPROT_TOG(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2157	/@}/
mbed_official	324:406fd2029f23	2158
mbed_official	324:406fd2029f23	2159	/*
mbed_official	324:406fd2029f23	2160	* Constants & macros for individual FTFE_FEPROT bitfields
mbed_official	324:406fd2029f23	2161	*/
mbed_official	324:406fd2029f23	2162
mbed_official	324:406fd2029f23	2163	/*!
mbed_official	324:406fd2029f23	2164	* @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
mbed_official	324:406fd2029f23	2165	*
mbed_official	324:406fd2029f23	2166	* For devices with program flash only: Reserved For devices with FlexNVM:
mbed_official	324:406fd2029f23	2167	* Individual EEPROM regions can be protected from alteration by setting the
mbed_official	324:406fd2029f23	2168	* associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
mbed_official	324:406fd2029f23	2169	* set to data flash only. When the FlexNVM Partition Code is set to data flash and
mbed_official	324:406fd2029f23	2170	* EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
mbed_official	324:406fd2029f23	2171	* EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
mbed_official	324:406fd2029f23	2172	* mode: The protection can only be increased. This means that
mbed_official	324:406fd2029f23	2173	* currently-unprotected memory can be protected, but currently-protected memory cannot be
mbed_official	324:406fd2029f23	2174	* unprotected. Since unprotected regions are marked with a 1 and protected regions use a
mbed_official	324:406fd2029f23	2175	* 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
mbed_official	324:406fd2029f23	2176	* performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
mbed_official	324:406fd2029f23	2177	* are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
mbed_official	324:406fd2029f23	2178	* mode: All bits of the FEPROT register are writable without restriction.
mbed_official	324:406fd2029f23	2179	* Unprotected areas can be protected and protected areas can be unprotected. Never
mbed_official	324:406fd2029f23	2180	* write to the FEPROT register while a command is running (CCIF=0). Reset: During
mbed_official	324:406fd2029f23	2181	* the reset sequence, the FEPROT register is loaded with the contents of the
mbed_official	324:406fd2029f23	2182	* FlexRAM protection byte in the Flash Configuration Field located in program flash.
mbed_official	324:406fd2029f23	2183	* The flash basis for the reset values is signified by X in the register
mbed_official	324:406fd2029f23	2184	* diagram. To change the EEPROM protection that will be loaded during the reset
mbed_official	324:406fd2029f23	2185	* sequence, the sector of program flash that contains the Flash Configuration Field
mbed_official	324:406fd2029f23	2186	* must be unprotected; then the EEPROM protection byte must be erased and
mbed_official	324:406fd2029f23	2187	* reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
mbed_official	324:406fd2029f23	2188	* results in a protection violation error and sets the FSTAT[FPVIOL] bit.
mbed_official	324:406fd2029f23	2189	*
mbed_official	324:406fd2029f23	2190	* Values:
mbed_official	324:406fd2029f23	2191	* - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
mbed_official	324:406fd2029f23	2192	* EEPROM region is protected
mbed_official	324:406fd2029f23	2193	* - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
mbed_official	324:406fd2029f23	2194	* EEPROM region is not protected
mbed_official	324:406fd2029f23	2195	*/
mbed_official	324:406fd2029f23	2196	/@{/
mbed_official	324:406fd2029f23	2197	#define BP_FTFE_FEPROT_EPROT (0U) /!< Bit position for FTFE_FEPROT_EPROT. /
mbed_official	324:406fd2029f23	2198	#define BM_FTFE_FEPROT_EPROT (0xFFU) /!< Bit mask for FTFE_FEPROT_EPROT. /
mbed_official	324:406fd2029f23	2199	#define BS_FTFE_FEPROT_EPROT (8U) /!< Bit field size in bits for FTFE_FEPROT_EPROT. /
mbed_official	324:406fd2029f23	2200
mbed_official	324:406fd2029f23	2201	/! @brief Read current value of the FTFE_FEPROT_EPROT field. /
mbed_official	324:406fd2029f23	2202	#define BR_FTFE_FEPROT_EPROT(x) (HW_FTFE_FEPROT(x).U)
mbed_official	324:406fd2029f23	2203
mbed_official	324:406fd2029f23	2204	/! @brief Format value for bitfield FTFE_FEPROT_EPROT. /
mbed_official	324:406fd2029f23	2205	#define BF_FTFE_FEPROT_EPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FEPROT_EPROT) & BM_FTFE_FEPROT_EPROT)
mbed_official	324:406fd2029f23	2206
mbed_official	324:406fd2029f23	2207	/! @brief Set the EPROT field to a new value. /
mbed_official	324:406fd2029f23	2208	#define BW_FTFE_FEPROT_EPROT(x, v) (HW_FTFE_FEPROT_WR(x, v))
mbed_official	324:406fd2029f23	2209	/@}/
mbed_official	324:406fd2029f23	2210
mbed_official	324:406fd2029f23	2211	/*******************************************************************************
mbed_official	324:406fd2029f23	2212	* HW_FTFE_FDPROT - Data Flash Protection Register
mbed_official	324:406fd2029f23	2213	******************************************************************************/
mbed_official	324:406fd2029f23	2214
mbed_official	324:406fd2029f23	2215	/*!
mbed_official	324:406fd2029f23	2216	* @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
mbed_official	324:406fd2029f23	2217	*
mbed_official	324:406fd2029f23	2218	* Reset value: 0x00U
mbed_official	324:406fd2029f23	2219	*
mbed_official	324:406fd2029f23	2220	* The FDPROT register defines which data flash regions are protected against
mbed_official	324:406fd2029f23	2221	* program and erase operations. Protected Flash regions cannot have their content
mbed_official	324:406fd2029f23	2222	* changed; that is, these regions cannot be programmed and cannot be erased by
mbed_official	324:406fd2029f23	2223	* any FTFE command. Unprotected regions can be changed by both program and erase
mbed_official	324:406fd2029f23	2224	* operations.
mbed_official	324:406fd2029f23	2225	*/
mbed_official	324:406fd2029f23	2226	typedef union _hw_ftfe_fdprot
mbed_official	324:406fd2029f23	2227	{
mbed_official	324:406fd2029f23	2228	uint8_t U;
mbed_official	324:406fd2029f23	2229	struct _hw_ftfe_fdprot_bitfields
mbed_official	324:406fd2029f23	2230	{
mbed_official	324:406fd2029f23	2231	uint8_t DPROT : 8; /!< [7:0] Data Flash Region Protect /
mbed_official	324:406fd2029f23	2232	} B;
mbed_official	324:406fd2029f23	2233	} hw_ftfe_fdprot_t;
mbed_official	324:406fd2029f23	2234
mbed_official	324:406fd2029f23	2235	/*!
mbed_official	324:406fd2029f23	2236	* @name Constants and macros for entire FTFE_FDPROT register
mbed_official	324:406fd2029f23	2237	*/
mbed_official	324:406fd2029f23	2238	/@{/
mbed_official	324:406fd2029f23	2239	#define HW_FTFE_FDPROT_ADDR(x) ((x) + 0x17U)
mbed_official	324:406fd2029f23	2240
mbed_official	324:406fd2029f23	2241	#define HW_FTFE_FDPROT(x) ((__IO hw_ftfe_fdprot_t ) HW_FTFE_FDPROT_ADDR(x))
mbed_official	324:406fd2029f23	2242	#define HW_FTFE_FDPROT_RD(x) (HW_FTFE_FDPROT(x).U)
mbed_official	324:406fd2029f23	2243	#define HW_FTFE_FDPROT_WR(x, v) (HW_FTFE_FDPROT(x).U = (v))
mbed_official	324:406fd2029f23	2244	#define HW_FTFE_FDPROT_SET(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2245	#define HW_FTFE_FDPROT_CLR(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2246	#define HW_FTFE_FDPROT_TOG(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2247	/@}/
mbed_official	324:406fd2029f23	2248
mbed_official	324:406fd2029f23	2249	/*
mbed_official	324:406fd2029f23	2250	* Constants & macros for individual FTFE_FDPROT bitfields
mbed_official	324:406fd2029f23	2251	*/
mbed_official	324:406fd2029f23	2252
mbed_official	324:406fd2029f23	2253	/*!
mbed_official	324:406fd2029f23	2254	* @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
mbed_official	324:406fd2029f23	2255	*
mbed_official	324:406fd2029f23	2256	* Individual data flash regions can be protected from program and erase
mbed_official	324:406fd2029f23	2257	* operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
mbed_official	324:406fd2029f23	2258	* the partitioned data flash memory space. The granularity of data flash
mbed_official	324:406fd2029f23	2259	* protection cannot be less than the data flash sector size. If an unused DPROT bit is
mbed_official	324:406fd2029f23	2260	* set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
mbed_official	324:406fd2029f23	2261	* bit. In NVM Normal mode: The protection can only be increased, meaning that
mbed_official	324:406fd2029f23	2262	* currently unprotected memory can be protected but currently protected memory
mbed_official	324:406fd2029f23	2263	* cannot be unprotected. Since unprotected regions are marked with a 1 and
mbed_official	324:406fd2029f23	2264	* protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
mbed_official	324:406fd2029f23	2265	* transition check is performed on a bit-by-bit basis. Those FDPROT bits with
mbed_official	324:406fd2029f23	2266	* 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
mbed_official	324:406fd2029f23	2267	* ignored. In NVM Special mode: All bits of the FDPROT register are writable without
mbed_official	324:406fd2029f23	2268	* restriction. Unprotected areas can be protected and protected areas can be
mbed_official	324:406fd2029f23	2269	* unprotected. The user must never write to the FDPROT register while a command is
mbed_official	324:406fd2029f23	2270	* running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
mbed_official	324:406fd2029f23	2271	* loaded with the contents of the data flash protection byte in the Flash
mbed_official	324:406fd2029f23	2272	* Configuration Field located in program flash memory. The flash basis for the reset values
mbed_official	324:406fd2029f23	2273	* is signified by X in the register diagram. To change the data flash
mbed_official	324:406fd2029f23	2274	* protection that will be loaded during the reset sequence, unprotect the sector of
mbed_official	324:406fd2029f23	2275	* program flash that contains the Flash Configuration Field. Then, erase and
mbed_official	324:406fd2029f23	2276	* reprogram the data flash protection byte. Trying to alter data with the program and
mbed_official	324:406fd2029f23	2277	* erase commands in any protected area in the data flash memory results in a
mbed_official	324:406fd2029f23	2278	* protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
mbed_official	324:406fd2029f23	2279	* data flash memory block (see the Erase Flash Block command description) is not
mbed_official	324:406fd2029f23	2280	* possible if the data flash block contains any protected region or if the FlexNVM
mbed_official	324:406fd2029f23	2281	* memory has been partitioned for EEPROM.
mbed_official	324:406fd2029f23	2282	*
mbed_official	324:406fd2029f23	2283	* Values:
mbed_official	324:406fd2029f23	2284	* - 0 - Data Flash region is protected
mbed_official	324:406fd2029f23	2285	* - 1 - Data Flash region is not protected
mbed_official	324:406fd2029f23	2286	*/
mbed_official	324:406fd2029f23	2287	/@{/
mbed_official	324:406fd2029f23	2288	#define BP_FTFE_FDPROT_DPROT (0U) /!< Bit position for FTFE_FDPROT_DPROT. /
mbed_official	324:406fd2029f23	2289	#define BM_FTFE_FDPROT_DPROT (0xFFU) /!< Bit mask for FTFE_FDPROT_DPROT. /
mbed_official	324:406fd2029f23	2290	#define BS_FTFE_FDPROT_DPROT (8U) /!< Bit field size in bits for FTFE_FDPROT_DPROT. /
mbed_official	324:406fd2029f23	2291
mbed_official	324:406fd2029f23	2292	/! @brief Read current value of the FTFE_FDPROT_DPROT field. /
mbed_official	324:406fd2029f23	2293	#define BR_FTFE_FDPROT_DPROT(x) (HW_FTFE_FDPROT(x).U)
mbed_official	324:406fd2029f23	2294
mbed_official	324:406fd2029f23	2295	/! @brief Format value for bitfield FTFE_FDPROT_DPROT. /
mbed_official	324:406fd2029f23	2296	#define BF_FTFE_FDPROT_DPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FDPROT_DPROT) & BM_FTFE_FDPROT_DPROT)
mbed_official	324:406fd2029f23	2297
mbed_official	324:406fd2029f23	2298	/! @brief Set the DPROT field to a new value. /
mbed_official	324:406fd2029f23	2299	#define BW_FTFE_FDPROT_DPROT(x, v) (HW_FTFE_FDPROT_WR(x, v))
mbed_official	324:406fd2029f23	2300	/@}/
mbed_official	324:406fd2029f23	2301
mbed_official	324:406fd2029f23	2302	/*******************************************************************************
mbed_official	324:406fd2029f23	2303	* hw_ftfe_t - module struct
mbed_official	324:406fd2029f23	2304	******************************************************************************/
mbed_official	324:406fd2029f23	2305	/*!
mbed_official	324:406fd2029f23	2306	* @brief All FTFE module registers.
mbed_official	324:406fd2029f23	2307	*/
mbed_official	324:406fd2029f23	2308	#pragma pack(1)
mbed_official	324:406fd2029f23	2309	typedef struct _hw_ftfe
mbed_official	324:406fd2029f23	2310	{
mbed_official	324:406fd2029f23	2311	__IO hw_ftfe_fstat_t FSTAT; /!< [0x0] Flash Status Register /
mbed_official	324:406fd2029f23	2312	__IO hw_ftfe_fcnfg_t FCNFG; /!< [0x1] Flash Configuration Register /
mbed_official	324:406fd2029f23	2313	__I hw_ftfe_fsec_t FSEC; /!< [0x2] Flash Security Register /
mbed_official	324:406fd2029f23	2314	__I hw_ftfe_fopt_t FOPT; /!< [0x3] Flash Option Register /
mbed_official	324:406fd2029f23	2315	__IO hw_ftfe_fccob3_t FCCOB3; /!< [0x4] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2316	__IO hw_ftfe_fccob2_t FCCOB2; /!< [0x5] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2317	__IO hw_ftfe_fccob1_t FCCOB1; /!< [0x6] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2318	__IO hw_ftfe_fccob0_t FCCOB0; /!< [0x7] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2319	__IO hw_ftfe_fccob7_t FCCOB7; /!< [0x8] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2320	__IO hw_ftfe_fccob6_t FCCOB6; /!< [0x9] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2321	__IO hw_ftfe_fccob5_t FCCOB5; /!< [0xA] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2322	__IO hw_ftfe_fccob4_t FCCOB4; /!< [0xB] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2323	__IO hw_ftfe_fccobb_t FCCOBB; /!< [0xC] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2324	__IO hw_ftfe_fccoba_t FCCOBA; /!< [0xD] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2325	__IO hw_ftfe_fccob9_t FCCOB9; /!< [0xE] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2326	__IO hw_ftfe_fccob8_t FCCOB8; /!< [0xF] Flash Common Command Object Registers /
mbed_official	324:406fd2029f23	2327	__IO hw_ftfe_fprot3_t FPROT3; /!< [0x10] Program Flash Protection Registers /
mbed_official	324:406fd2029f23	2328	__IO hw_ftfe_fprot2_t FPROT2; /!< [0x11] Program Flash Protection Registers /
mbed_official	324:406fd2029f23	2329	__IO hw_ftfe_fprot1_t FPROT1; /!< [0x12] Program Flash Protection Registers /
mbed_official	324:406fd2029f23	2330	__IO hw_ftfe_fprot0_t FPROT0; /!< [0x13] Program Flash Protection Registers /
mbed_official	324:406fd2029f23	2331	uint8_t _reserved0[2];
mbed_official	324:406fd2029f23	2332	__IO hw_ftfe_feprot_t FEPROT; /!< [0x16] EEPROM Protection Register /
mbed_official	324:406fd2029f23	2333	__IO hw_ftfe_fdprot_t FDPROT; /!< [0x17] Data Flash Protection Register /
mbed_official	324:406fd2029f23	2334	} hw_ftfe_t;
mbed_official	324:406fd2029f23	2335	#pragma pack()
mbed_official	324:406fd2029f23	2336
mbed_official	324:406fd2029f23	2337	/! @brief Macro to access all FTFE registers. /
mbed_official	324:406fd2029f23	2338	/! @param x FTFE module instance base address. /
mbed_official	324:406fd2029f23	2339	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	2340	* use the '&' operator, like <code>&HW_FTFE(FTFE_BASE)</code>. */
mbed_official	324:406fd2029f23	2341	#define HW_FTFE(x) ((hw_ftfe_t )(x))
mbed_official	324:406fd2029f23	2342
mbed_official	324:406fd2029f23	2343	#endif /* __HW_FTFE_REGISTERS_H__ */
mbed_official	324:406fd2029f23	2344	/* EOF */